1 /* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 268487 2014-07-10 09:42:34Z kevlo $ 20 */ 21 22 /* 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 24 */ 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/sysctl.h> 29 #include <sys/lock.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/module.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/linker.h> 39 #include <sys/firmware.h> 40 #include <net/ifq_var.h> 41 42 #include <sys/rman.h> 43 44 #include <net/bpf.h> 45 #include <net/if.h> 46 #include <net/if_var.h> 47 #include <net/if_arp.h> 48 #include <net/ethernet.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/if_types.h> 52 53 #include <netinet/in.h> 54 #include <netinet/in_systm.h> 55 #include <netinet/in_var.h> 56 #include <netinet/if_ether.h> 57 #include <netinet/ip.h> 58 59 #include <netproto/802_11/ieee80211_var.h> 60 #include <netproto/802_11/ieee80211_regdomain.h> 61 #include <netproto/802_11/ieee80211_radiotap.h> 62 #include <netproto/802_11/ieee80211_ratectl.h> 63 64 #include <bus/u4b/usb.h> 65 #include <bus/u4b/usbdi.h> 66 #include "usbdevs.h" 67 68 #define USB_DEBUG_VAR urtwn_debug 69 #include <bus/u4b/usb_debug.h> 70 71 #include <bus/u4b/wlan/if_urtwnreg.h> 72 73 #ifdef USB_DEBUG 74 static int urtwn_debug = 0; 75 76 SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 77 SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RW, &urtwn_debug, 0, 78 "Debug level"); 79 #endif 80 81 #define URTWN_RSSI(r) (r) - 110 82 #define IEEE80211_HAS_ADDR4(wh) \ 83 (((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) 84 85 /* various supported device vendors/products */ 86 static const STRUCT_USB_HOST_ID urtwn_devs[] = { 87 #define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 88 #define URTWN_RTL8188E_DEV(v,p) \ 89 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 90 #define URTWN_RTL8188E 1 91 URTWN_DEV(ABOCOM, RTL8188CU_1), 92 URTWN_DEV(ABOCOM, RTL8188CU_2), 93 URTWN_DEV(ABOCOM, RTL8192CU), 94 URTWN_DEV(ASUS, RTL8192CU), 95 URTWN_DEV(ASUS, USBN10NANO), 96 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 97 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 98 URTWN_DEV(AZUREWAVE, RTL8188CU), 99 URTWN_DEV(BELKIN, F7D2102), 100 URTWN_DEV(BELKIN, RTL8188CU), 101 URTWN_DEV(BELKIN, RTL8192CU), 102 URTWN_DEV(CHICONY, RTL8188CUS_1), 103 URTWN_DEV(CHICONY, RTL8188CUS_2), 104 URTWN_DEV(CHICONY, RTL8188CUS_3), 105 URTWN_DEV(CHICONY, RTL8188CUS_4), 106 URTWN_DEV(CHICONY, RTL8188CUS_5), 107 URTWN_DEV(COREGA, RTL8192CU), 108 URTWN_DEV(DLINK, RTL8188CU), 109 URTWN_DEV(DLINK, RTL8192CU_1), 110 URTWN_DEV(DLINK, RTL8192CU_2), 111 URTWN_DEV(DLINK, RTL8192CU_3), 112 URTWN_DEV(DLINK, DWA131B), 113 URTWN_DEV(EDIMAX, EW7811UN), 114 URTWN_DEV(EDIMAX, RTL8192CU), 115 URTWN_DEV(FEIXUN, RTL8188CU), 116 URTWN_DEV(FEIXUN, RTL8192CU), 117 URTWN_DEV(GUILLEMOT, HWNUP150), 118 URTWN_DEV(HAWKING, RTL8192CU), 119 URTWN_DEV(HP3, RTL8188CU), 120 URTWN_DEV(NETGEAR, WNA1000M), 121 URTWN_DEV(NETGEAR, RTL8192CU), 122 URTWN_DEV(NETGEAR4, RTL8188CU), 123 URTWN_DEV(NOVATECH, RTL8188CU), 124 URTWN_DEV(PLANEX2, RTL8188CU_1), 125 URTWN_DEV(PLANEX2, RTL8188CU_2), 126 URTWN_DEV(PLANEX2, RTL8188CU_3), 127 URTWN_DEV(PLANEX2, RTL8188CU_4), 128 URTWN_DEV(PLANEX2, RTL8188CUS), 129 URTWN_DEV(PLANEX2, RTL8192CU), 130 URTWN_DEV(REALTEK, RTL8188CE_0), 131 URTWN_DEV(REALTEK, RTL8188CE_1), 132 URTWN_DEV(REALTEK, RTL8188CTV), 133 URTWN_DEV(REALTEK, RTL8188CU_0), 134 URTWN_DEV(REALTEK, RTL8188CU_1), 135 URTWN_DEV(REALTEK, RTL8188CU_2), 136 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 137 URTWN_DEV(REALTEK, RTL8188CUS), 138 URTWN_DEV(REALTEK, RTL8188RU_1), 139 URTWN_DEV(REALTEK, RTL8188RU_2), 140 URTWN_DEV(REALTEK, RTL8191CU), 141 URTWN_DEV(REALTEK, RTL8192CE), 142 URTWN_DEV(REALTEK, RTL8192CU), 143 URTWN_DEV(SITECOMEU, RTL8188CU_1), 144 URTWN_DEV(SITECOMEU, RTL8188CU_2), 145 URTWN_DEV(SITECOMEU, RTL8192CU), 146 URTWN_DEV(TRENDNET, RTL8188CU), 147 URTWN_DEV(TRENDNET, RTL8192CU), 148 URTWN_DEV(ZYXEL, RTL8192CU), 149 /* URTWN_RTL8188E */ 150 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 151 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 152 #undef URTWN_RTL8188E_DEV 153 #undef URTWN_DEV 154 }; 155 156 static device_probe_t urtwn_match; 157 static device_attach_t urtwn_attach; 158 static device_detach_t urtwn_detach; 159 160 static usb_callback_t urtwn_bulk_tx_callback; 161 static usb_callback_t urtwn_bulk_rx_callback; 162 163 static usb_error_t urtwn_do_request(struct urtwn_softc *sc, 164 struct usb_device_request *req, void *data); 165 static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 166 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 167 const uint8_t [IEEE80211_ADDR_LEN], 168 const uint8_t [IEEE80211_ADDR_LEN]); 169 static void urtwn_vap_delete(struct ieee80211vap *); 170 static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 171 int *); 172 static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 173 int *, int8_t *); 174 static void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 175 static int urtwn_alloc_list(struct urtwn_softc *, 176 struct urtwn_data[], int, int); 177 static int urtwn_alloc_rx_list(struct urtwn_softc *); 178 static int urtwn_alloc_tx_list(struct urtwn_softc *); 179 static void urtwn_free_tx_list(struct urtwn_softc *); 180 static void urtwn_free_rx_list(struct urtwn_softc *); 181 static void urtwn_free_list(struct urtwn_softc *, 182 struct urtwn_data data[], int); 183 static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 184 static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 185 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 186 uint8_t *, int); 187 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 188 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 189 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 190 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 191 uint8_t *, int); 192 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 193 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 194 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 195 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 196 const void *, int); 197 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 198 uint8_t, uint32_t); 199 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 200 uint8_t, uint32_t); 201 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 202 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 203 uint32_t); 204 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 205 static void urtwn_efuse_read(struct urtwn_softc *); 206 static void urtwn_efuse_switch_power(struct urtwn_softc *); 207 static int urtwn_read_chipid(struct urtwn_softc *); 208 static void urtwn_read_rom(struct urtwn_softc *); 209 static void urtwn_r88e_read_rom(struct urtwn_softc *); 210 static int urtwn_ra_init(struct urtwn_softc *); 211 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 212 static void urtwn_set_led(struct urtwn_softc *, int, int); 213 static int urtwn_newstate(struct ieee80211vap *, 214 enum ieee80211_state, int); 215 static void urtwn_watchdog(void *); 216 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 217 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 218 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 219 static int urtwn_tx_start(struct urtwn_softc *, 220 struct ieee80211_node *, struct mbuf *, 221 struct urtwn_data *); 222 static void urtwn_start(struct ifnet *, struct ifaltq_subque *); 223 static void urtwn_start_locked(struct ifnet *); 224 static int urtwn_ioctl(struct ifnet *, u_long, caddr_t, 225 struct ucred *); 226 static int urtwn_r92c_power_on(struct urtwn_softc *); 227 static int urtwn_r88e_power_on(struct urtwn_softc *); 228 static int urtwn_llt_init(struct urtwn_softc *); 229 static void urtwn_fw_reset(struct urtwn_softc *); 230 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 231 static int urtwn_fw_loadpage(struct urtwn_softc *, int, 232 const uint8_t *, int); 233 static int urtwn_load_firmware(struct urtwn_softc *); 234 static int urtwn_r92c_dma_init(struct urtwn_softc *); 235 static int urtwn_r88e_dma_init(struct urtwn_softc *); 236 static void urtwn_mac_init(struct urtwn_softc *); 237 static void urtwn_bb_init(struct urtwn_softc *); 238 static void urtwn_rf_init(struct urtwn_softc *); 239 static void urtwn_cam_init(struct urtwn_softc *); 240 static void urtwn_pa_bias_init(struct urtwn_softc *); 241 static void urtwn_rxfilter_init(struct urtwn_softc *); 242 static void urtwn_edca_init(struct urtwn_softc *); 243 static void urtwn_write_txpower(struct urtwn_softc *, int, 244 uint16_t[]); 245 static void urtwn_get_txpower(struct urtwn_softc *, int, 246 struct ieee80211_channel *, 247 struct ieee80211_channel *, uint16_t[]); 248 static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 249 struct ieee80211_channel *, 250 struct ieee80211_channel *, uint16_t[]); 251 static void urtwn_set_txpower(struct urtwn_softc *, 252 struct ieee80211_channel *, 253 struct ieee80211_channel *); 254 static void urtwn_scan_start(struct ieee80211com *); 255 static void urtwn_scan_end(struct ieee80211com *); 256 static void urtwn_set_channel(struct ieee80211com *); 257 static void urtwn_set_chan(struct urtwn_softc *, 258 struct ieee80211_channel *, 259 struct ieee80211_channel *); 260 static void urtwn_update_mcast(struct ifnet *); 261 static void urtwn_iq_calib(struct urtwn_softc *); 262 static void urtwn_lc_calib(struct urtwn_softc *); 263 static void urtwn_init(void *); 264 static void urtwn_init_locked(void *); 265 static void urtwn_stop(struct ifnet *); 266 static void urtwn_stop_locked(struct ifnet *); 267 static void urtwn_abort_xfers(struct urtwn_softc *); 268 static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 269 const struct ieee80211_bpf_params *); 270 static void urtwn_ms_delay(struct urtwn_softc *); 271 272 /* Aliases. */ 273 #define urtwn_bb_write urtwn_write_4 274 #define urtwn_bb_read urtwn_read_4 275 276 static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 277 [URTWN_BULK_RX] = { 278 .type = UE_BULK, 279 .endpoint = UE_ADDR_ANY, 280 .direction = UE_DIR_IN, 281 .bufsize = URTWN_RXBUFSZ, 282 .flags = { 283 .pipe_bof = 1, 284 .short_xfer_ok = 1 285 }, 286 .callback = urtwn_bulk_rx_callback, 287 }, 288 [URTWN_BULK_TX_BE] = { 289 .type = UE_BULK, 290 .endpoint = 0x03, 291 .direction = UE_DIR_OUT, 292 .bufsize = URTWN_TXBUFSZ, 293 .flags = { 294 .ext_buffer = 1, 295 .pipe_bof = 1, 296 .force_short_xfer = 1 297 }, 298 .callback = urtwn_bulk_tx_callback, 299 .timeout = URTWN_TX_TIMEOUT, /* ms */ 300 }, 301 [URTWN_BULK_TX_BK] = { 302 .type = UE_BULK, 303 .endpoint = 0x03, 304 .direction = UE_DIR_OUT, 305 .bufsize = URTWN_TXBUFSZ, 306 .flags = { 307 .ext_buffer = 1, 308 .pipe_bof = 1, 309 .force_short_xfer = 1, 310 }, 311 .callback = urtwn_bulk_tx_callback, 312 .timeout = URTWN_TX_TIMEOUT, /* ms */ 313 }, 314 [URTWN_BULK_TX_VI] = { 315 .type = UE_BULK, 316 .endpoint = 0x02, 317 .direction = UE_DIR_OUT, 318 .bufsize = URTWN_TXBUFSZ, 319 .flags = { 320 .ext_buffer = 1, 321 .pipe_bof = 1, 322 .force_short_xfer = 1 323 }, 324 .callback = urtwn_bulk_tx_callback, 325 .timeout = URTWN_TX_TIMEOUT, /* ms */ 326 }, 327 [URTWN_BULK_TX_VO] = { 328 .type = UE_BULK, 329 .endpoint = 0x02, 330 .direction = UE_DIR_OUT, 331 .bufsize = URTWN_TXBUFSZ, 332 .flags = { 333 .ext_buffer = 1, 334 .pipe_bof = 1, 335 .force_short_xfer = 1 336 }, 337 .callback = urtwn_bulk_tx_callback, 338 .timeout = URTWN_TX_TIMEOUT, /* ms */ 339 }, 340 }; 341 342 static int 343 urtwn_match(device_t self) 344 { 345 struct usb_attach_arg *uaa = device_get_ivars(self); 346 347 if (uaa->usb_mode != USB_MODE_HOST) 348 return (ENXIO); 349 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 350 return (ENXIO); 351 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 352 return (ENXIO); 353 354 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 355 } 356 357 static int 358 urtwn_attach(device_t self) 359 { 360 struct usb_attach_arg *uaa = device_get_ivars(self); 361 struct urtwn_softc *sc = device_get_softc(self); 362 struct ifnet *ifp; 363 struct ieee80211com *ic; 364 uint8_t iface_index, bands; 365 int error; 366 367 wlan_serialize_enter(); 368 device_set_usb_desc(self); 369 sc->sc_udev = uaa->device; 370 sc->sc_dev = self; 371 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 372 sc->chip |= URTWN_CHIP_88E; 373 374 lockinit(&sc->sc_lock, device_get_nameunit(self), 0, LK_CANRECURSE); 375 callout_init(&sc->sc_watchdog_ch); 376 377 iface_index = URTWN_IFACE_INDEX; 378 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 379 urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_lock); 380 if (error) { 381 device_printf(self, "could not allocate USB transfers, " 382 "err=%s\n", usbd_errstr(error)); 383 goto detach; 384 } 385 386 URTWN_LOCK(sc); 387 388 error = urtwn_read_chipid(sc); 389 if (error) { 390 device_printf(sc->sc_dev, "unsupported test chip\n"); 391 URTWN_UNLOCK(sc); 392 goto detach; 393 } 394 395 /* Determine number of Tx/Rx chains. */ 396 if (sc->chip & URTWN_CHIP_92C) { 397 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 398 sc->nrxchains = 2; 399 } else { 400 sc->ntxchains = 1; 401 sc->nrxchains = 1; 402 } 403 404 if (sc->chip & URTWN_CHIP_88E) 405 urtwn_r88e_read_rom(sc); 406 else 407 urtwn_read_rom(sc); 408 409 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 410 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 411 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 412 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 413 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 414 "8188CUS", sc->ntxchains, sc->nrxchains); 415 416 URTWN_UNLOCK(sc); 417 418 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 419 if (ifp == NULL) { 420 device_printf(sc->sc_dev, "can not if_alloc()\n"); 421 goto detach; 422 } 423 ic = ifp->if_l2com; 424 425 ifp->if_softc = sc; 426 if_initname(ifp, "urtwn", device_get_unit(sc->sc_dev)); 427 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 428 ifp->if_init = urtwn_init; 429 ifp->if_ioctl = urtwn_ioctl; 430 ifp->if_start = urtwn_start; 431 ifq_set_maxlen(&ifp->if_snd, ifqmaxlen); 432 #if 0 /* XXX swildner: see c3d4131842e47b168d93a0650d58d425ebeef789 */ 433 IFQ_SET_READY(&ifp->if_snd); 434 #endif 435 436 ic->ic_ifp = ifp; 437 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 438 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 439 440 /* set device capabilities */ 441 ic->ic_caps = 442 IEEE80211_C_STA /* station mode */ 443 | IEEE80211_C_MONITOR /* monitor mode */ 444 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 445 | IEEE80211_C_SHSLOT /* short slot time supported */ 446 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 447 | IEEE80211_C_WPA /* 802.11i */ 448 ; 449 450 bands = 0; 451 setbit(&bands, IEEE80211_MODE_11B); 452 setbit(&bands, IEEE80211_MODE_11G); 453 ieee80211_init_channels(ic, NULL, &bands); 454 455 ieee80211_ifattach(ic, sc->sc_bssid); 456 ic->ic_raw_xmit = urtwn_raw_xmit; 457 ic->ic_scan_start = urtwn_scan_start; 458 ic->ic_scan_end = urtwn_scan_end; 459 ic->ic_set_channel = urtwn_set_channel; 460 461 ic->ic_vap_create = urtwn_vap_create; 462 ic->ic_vap_delete = urtwn_vap_delete; 463 ic->ic_update_mcast = urtwn_update_mcast; 464 465 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 466 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 467 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 468 URTWN_RX_RADIOTAP_PRESENT); 469 470 if (bootverbose) 471 ieee80211_announce(ic); 472 473 wlan_serialize_exit(); 474 return (0); 475 476 detach: 477 wlan_serialize_exit(); 478 urtwn_detach(self); 479 return (ENXIO); /* failure */ 480 } 481 482 static int 483 urtwn_detach(device_t self) 484 { 485 struct urtwn_softc *sc = device_get_softc(self); 486 struct ifnet *ifp = sc->sc_ifp; 487 struct ieee80211com *ic = ifp->if_l2com; 488 unsigned int x; 489 490 wlan_serialize_enter(); 491 492 /* Prevent further ioctls. */ 493 URTWN_LOCK(sc); 494 sc->sc_flags |= URTWN_DETACHED; 495 URTWN_UNLOCK(sc); 496 497 urtwn_stop(ifp); 498 499 callout_stop_sync(&sc->sc_watchdog_ch); 500 501 /* Prevent further allocations from RX/TX data lists. */ 502 URTWN_LOCK(sc); 503 STAILQ_INIT(&sc->sc_tx_active); 504 STAILQ_INIT(&sc->sc_tx_inactive); 505 STAILQ_INIT(&sc->sc_tx_pending); 506 507 STAILQ_INIT(&sc->sc_rx_active); 508 STAILQ_INIT(&sc->sc_rx_inactive); 509 URTWN_UNLOCK(sc); 510 511 /* drain USB transfers */ 512 for (x = 0; x != URTWN_N_TRANSFER; x++) 513 usbd_transfer_drain(sc->sc_xfer[x]); 514 515 /* Free data buffers. */ 516 URTWN_LOCK(sc); 517 urtwn_free_tx_list(sc); 518 urtwn_free_rx_list(sc); 519 URTWN_UNLOCK(sc); 520 521 /* stop all USB transfers */ 522 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 523 ieee80211_ifdetach(ic); 524 525 if_free(ifp); 526 lockuninit(&sc->sc_lock); 527 528 wlan_serialize_exit(); 529 return (0); 530 } 531 532 static void 533 urtwn_free_tx_list(struct urtwn_softc *sc) 534 { 535 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 536 } 537 538 static void 539 urtwn_free_rx_list(struct urtwn_softc *sc) 540 { 541 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 542 } 543 544 static void 545 urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 546 { 547 int i; 548 549 for (i = 0; i < ndata; i++) { 550 struct urtwn_data *dp = &data[i]; 551 552 if (dp->buf != NULL) { 553 kfree(dp->buf, M_USBDEV); 554 dp->buf = NULL; 555 } 556 if (dp->ni != NULL) { 557 ieee80211_free_node(dp->ni); 558 dp->ni = NULL; 559 } 560 } 561 } 562 563 static usb_error_t 564 urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 565 void *data) 566 { 567 usb_error_t err; 568 int ntries = 10; 569 570 URTWN_ASSERT_LOCKED(sc); 571 572 while (ntries--) { 573 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_lock, 574 req, data, 0, NULL, 250 /* ms */); 575 if (err == 0) 576 break; 577 578 DPRINTFN(1, "Control request failed, %s (retrying)\n", 579 usbd_errstr(err)); 580 usb_pause_mtx(&sc->sc_lock, hz / 100); 581 } 582 return (err); 583 } 584 585 static struct ieee80211vap * 586 urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 587 enum ieee80211_opmode opmode, int flags, 588 const uint8_t bssid[IEEE80211_ADDR_LEN], 589 const uint8_t mac[IEEE80211_ADDR_LEN]) 590 { 591 struct urtwn_vap *uvp; 592 struct ieee80211vap *vap; 593 594 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 595 return (NULL); 596 597 uvp = (struct urtwn_vap *) kmalloc(sizeof(struct urtwn_vap), 598 M_80211_VAP, M_INTWAIT | M_ZERO); 599 vap = &uvp->vap; 600 /* enable s/w bmiss handling for sta mode */ 601 602 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 603 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac) != 0) { 604 /* out of memory */ 605 kfree(uvp, M_80211_VAP); 606 return (NULL); 607 } 608 609 /* override state transition machine */ 610 uvp->newstate = vap->iv_newstate; 611 vap->iv_newstate = urtwn_newstate; 612 613 /* complete setup */ 614 ieee80211_vap_attach(vap, ieee80211_media_change, 615 ieee80211_media_status); 616 ic->ic_opmode = opmode; 617 return (vap); 618 } 619 620 static void 621 urtwn_vap_delete(struct ieee80211vap *vap) 622 { 623 struct urtwn_vap *uvp = URTWN_VAP(vap); 624 625 ieee80211_vap_detach(vap); 626 kfree(uvp, M_80211_VAP); 627 } 628 629 static struct mbuf * 630 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 631 { 632 struct ifnet *ifp = sc->sc_ifp; 633 struct ieee80211com *ic = ifp->if_l2com; 634 struct ieee80211_frame *wh; 635 struct mbuf *m; 636 struct r92c_rx_stat *stat; 637 uint32_t rxdw0, rxdw3; 638 uint8_t rate; 639 int8_t rssi = 0; 640 int infosz; 641 642 /* 643 * don't pass packets to the ieee80211 framework if the driver isn't 644 * RUNNING. 645 */ 646 if (!(ifp->if_flags & IFF_RUNNING)) 647 return (NULL); 648 649 stat = (struct r92c_rx_stat *)buf; 650 rxdw0 = le32toh(stat->rxdw0); 651 rxdw3 = le32toh(stat->rxdw3); 652 653 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 654 /* 655 * This should not happen since we setup our Rx filter 656 * to not receive these frames. 657 */ 658 ifp->if_ierrors++; 659 return (NULL); 660 } 661 662 rate = MS(rxdw3, R92C_RXDW3_RATE); 663 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 664 665 /* Get RSSI from PHY status descriptor if present. */ 666 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 667 if (sc->chip & URTWN_CHIP_88E) 668 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 669 else 670 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 671 /* Update our average RSSI. */ 672 urtwn_update_avgrssi(sc, rate, rssi); 673 /* 674 * Convert the RSSI to a range that will be accepted 675 * by net80211. 676 */ 677 rssi = URTWN_RSSI(rssi); 678 } 679 680 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 681 if (m == NULL) { 682 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 683 return (NULL); 684 } 685 686 /* Finalize mbuf. */ 687 m->m_pkthdr.rcvif = ifp; 688 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 689 memcpy(mtod(m, uint8_t *), wh, pktlen); 690 m->m_pkthdr.len = m->m_len = pktlen; 691 692 if (ieee80211_radiotap_active(ic)) { 693 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 694 695 tap->wr_flags = 0; 696 /* Map HW rate index to 802.11 rate. */ 697 if (!(rxdw3 & R92C_RXDW3_HT)) { 698 switch (rate) { 699 /* CCK. */ 700 case 0: tap->wr_rate = 2; break; 701 case 1: tap->wr_rate = 4; break; 702 case 2: tap->wr_rate = 11; break; 703 case 3: tap->wr_rate = 22; break; 704 /* OFDM. */ 705 case 4: tap->wr_rate = 12; break; 706 case 5: tap->wr_rate = 18; break; 707 case 6: tap->wr_rate = 24; break; 708 case 7: tap->wr_rate = 36; break; 709 case 8: tap->wr_rate = 48; break; 710 case 9: tap->wr_rate = 72; break; 711 case 10: tap->wr_rate = 96; break; 712 case 11: tap->wr_rate = 108; break; 713 } 714 } else if (rate >= 12) { /* MCS0~15. */ 715 /* Bit 7 set means HT MCS instead of rate. */ 716 tap->wr_rate = 0x80 | (rate - 12); 717 } 718 tap->wr_dbm_antsignal = rssi; 719 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 720 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 721 } 722 723 *rssi_p = rssi; 724 725 return (m); 726 } 727 728 static struct mbuf * 729 urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 730 int8_t *nf) 731 { 732 struct urtwn_softc *sc = data->sc; 733 struct ifnet *ifp = sc->sc_ifp; 734 struct r92c_rx_stat *stat; 735 struct mbuf *m, *m0 = NULL, *prevm = NULL; 736 uint32_t rxdw0; 737 uint8_t *buf; 738 int len, totlen, pktlen, infosz, npkts; 739 740 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 741 742 if (len < sizeof(*stat)) { 743 ifp->if_ierrors++; 744 return (NULL); 745 } 746 747 buf = data->buf; 748 /* Get the number of encapsulated frames. */ 749 stat = (struct r92c_rx_stat *)buf; 750 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 751 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 752 753 /* Process all of them. */ 754 while (npkts-- > 0) { 755 if (len < sizeof(*stat)) 756 break; 757 stat = (struct r92c_rx_stat *)buf; 758 rxdw0 = le32toh(stat->rxdw0); 759 760 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 761 if (pktlen == 0) 762 break; 763 764 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 765 766 /* Make sure everything fits in xfer. */ 767 totlen = sizeof(*stat) + infosz + pktlen; 768 if (totlen > len) 769 break; 770 771 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 772 if (m0 == NULL) 773 m0 = m; 774 if (prevm == NULL) 775 prevm = m; 776 else { 777 prevm->m_next = m; 778 prevm = m; 779 } 780 781 /* Next chunk is 128-byte aligned. */ 782 totlen = (totlen + 127) & ~127; 783 buf += totlen; 784 len -= totlen; 785 } 786 787 return (m0); 788 } 789 790 static void 791 urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 792 { 793 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 794 struct ifnet *ifp = sc->sc_ifp; 795 struct ieee80211com *ic = ifp->if_l2com; 796 struct ieee80211_frame *wh; 797 struct ieee80211_node *ni; 798 struct mbuf *m = NULL, *next; 799 struct urtwn_data *data; 800 int8_t nf; 801 int rssi = 1; 802 803 URTWN_ASSERT_LOCKED(sc); 804 805 switch (USB_GET_STATE(xfer)) { 806 case USB_ST_TRANSFERRED: 807 data = STAILQ_FIRST(&sc->sc_rx_active); 808 if (data == NULL) 809 goto tr_setup; 810 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 811 m = urtwn_rxeof(xfer, data, &rssi, &nf); 812 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 813 /* FALLTHROUGH */ 814 case USB_ST_SETUP: 815 tr_setup: 816 data = STAILQ_FIRST(&sc->sc_rx_inactive); 817 if (data == NULL) { 818 KASSERT(m == NULL, ("mbuf isn't NULL")); 819 return; 820 } 821 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 822 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 823 usbd_xfer_set_frame_data(xfer, 0, data->buf, 824 usbd_xfer_max_len(xfer)); 825 usbd_transfer_submit(xfer); 826 827 /* 828 * To avoid LOR we should unlock our private mutex here to call 829 * ieee80211_input() because here is at the end of a USB 830 * callback and safe to unlock. 831 */ 832 URTWN_UNLOCK(sc); 833 while (m != NULL) { 834 next = m->m_next; 835 m->m_next = NULL; 836 wh = mtod(m, struct ieee80211_frame *); 837 ni = ieee80211_find_rxnode(ic, 838 (struct ieee80211_frame_min *)wh); 839 nf = URTWN_NOISE_FLOOR; 840 if (ni != NULL) { 841 (void)ieee80211_input(ni, m, rssi, nf); 842 ieee80211_free_node(ni); 843 } else 844 (void)ieee80211_input_all(ic, m, rssi, nf); 845 m = next; 846 } 847 URTWN_LOCK(sc); 848 break; 849 default: 850 /* needs it to the inactive queue due to a error. */ 851 data = STAILQ_FIRST(&sc->sc_rx_active); 852 if (data != NULL) { 853 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 854 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 855 } 856 if (error != USB_ERR_CANCELLED) { 857 usbd_xfer_set_stall(xfer); 858 ifp->if_ierrors++; 859 goto tr_setup; 860 } 861 break; 862 } 863 } 864 865 static void 866 urtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 867 { 868 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 869 struct ifnet *ifp = sc->sc_ifp; 870 struct mbuf *m; 871 872 URTWN_ASSERT_LOCKED(sc); 873 874 /* 875 * Do any tx complete callback. Note this must be done before releasing 876 * the node reference. 877 */ 878 if (data->m) { 879 m = data->m; 880 if (m->m_flags & M_TXCB) { 881 /* XXX status? */ 882 ieee80211_process_callback(data->ni, m, 0); 883 } 884 m_freem(m); 885 data->m = NULL; 886 } 887 if (data->ni) { 888 ieee80211_free_node(data->ni); 889 data->ni = NULL; 890 } 891 sc->sc_txtimer = 0; 892 ifp->if_opackets++; 893 ifq_clr_oactive(&ifp->if_snd); 894 } 895 896 static void 897 urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 898 { 899 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 900 struct ifnet *ifp = sc->sc_ifp; 901 struct urtwn_data *data; 902 903 URTWN_ASSERT_LOCKED(sc); 904 905 switch (USB_GET_STATE(xfer)){ 906 case USB_ST_TRANSFERRED: 907 data = STAILQ_FIRST(&sc->sc_tx_active); 908 if (data == NULL) 909 goto tr_setup; 910 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 911 urtwn_txeof(xfer, data); 912 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 913 /* FALLTHROUGH */ 914 case USB_ST_SETUP: 915 tr_setup: 916 data = STAILQ_FIRST(&sc->sc_tx_pending); 917 if (data == NULL) { 918 DPRINTF("%s: empty pending queue\n", __func__); 919 return; 920 } 921 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 922 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 923 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 924 usbd_transfer_submit(xfer); 925 926 urtwn_start_locked(ifp); 927 break; 928 default: 929 data = STAILQ_FIRST(&sc->sc_tx_active); 930 if (data == NULL) 931 goto tr_setup; 932 if (data->ni != NULL) { 933 ieee80211_free_node(data->ni); 934 data->ni = NULL; 935 ifp->if_oerrors++; 936 } 937 if (error != USB_ERR_CANCELLED) { 938 usbd_xfer_set_stall(xfer); 939 goto tr_setup; 940 } 941 break; 942 } 943 } 944 945 static struct urtwn_data * 946 _urtwn_getbuf(struct urtwn_softc *sc) 947 { 948 struct urtwn_data *bf; 949 950 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 951 if (bf != NULL) 952 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 953 else 954 bf = NULL; 955 if (bf == NULL) 956 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 957 return (bf); 958 } 959 960 static struct urtwn_data * 961 urtwn_getbuf(struct urtwn_softc *sc) 962 { 963 struct urtwn_data *bf; 964 965 URTWN_ASSERT_LOCKED(sc); 966 967 bf = _urtwn_getbuf(sc); 968 if (bf == NULL) { 969 struct ifnet *ifp = sc->sc_ifp; 970 DPRINTF("%s: stop queue\n", __func__); 971 ifq_set_oactive(&ifp->if_snd); 972 } 973 return (bf); 974 } 975 976 static int 977 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 978 int len) 979 { 980 usb_device_request_t req; 981 982 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 983 req.bRequest = R92C_REQ_REGS; 984 USETW(req.wValue, addr); 985 USETW(req.wIndex, 0); 986 USETW(req.wLength, len); 987 return (urtwn_do_request(sc, &req, buf)); 988 } 989 990 static void 991 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 992 { 993 urtwn_write_region_1(sc, addr, &val, 1); 994 } 995 996 static void 997 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 998 { 999 val = htole16(val); 1000 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1001 } 1002 1003 static void 1004 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1005 { 1006 val = htole32(val); 1007 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1008 } 1009 1010 static int 1011 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1012 int len) 1013 { 1014 usb_device_request_t req; 1015 1016 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1017 req.bRequest = R92C_REQ_REGS; 1018 USETW(req.wValue, addr); 1019 USETW(req.wIndex, 0); 1020 USETW(req.wLength, len); 1021 return (urtwn_do_request(sc, &req, buf)); 1022 } 1023 1024 static uint8_t 1025 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1026 { 1027 uint8_t val; 1028 1029 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1030 return (0xff); 1031 return (val); 1032 } 1033 1034 static uint16_t 1035 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1036 { 1037 uint16_t val; 1038 1039 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1040 return (0xffff); 1041 return (le16toh(val)); 1042 } 1043 1044 static uint32_t 1045 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1046 { 1047 uint32_t val; 1048 1049 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1050 return (0xffffffff); 1051 return (le32toh(val)); 1052 } 1053 1054 static int 1055 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1056 { 1057 struct r92c_fw_cmd cmd; 1058 int ntries; 1059 1060 /* Wait for current FW box to be empty. */ 1061 for (ntries = 0; ntries < 100; ntries++) { 1062 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1063 break; 1064 urtwn_ms_delay(sc); 1065 } 1066 if (ntries == 100) { 1067 device_printf(sc->sc_dev, 1068 "could not send firmware command\n"); 1069 return (ETIMEDOUT); 1070 } 1071 memset(&cmd, 0, sizeof(cmd)); 1072 cmd.id = id; 1073 if (len > 3) 1074 cmd.id |= R92C_CMD_FLAG_EXT; 1075 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1076 memcpy(cmd.msg, buf, len); 1077 1078 /* Write the first word last since that will trigger the FW. */ 1079 urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1080 (uint8_t *)&cmd + 4, 2); 1081 urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1082 (uint8_t *)&cmd + 0, 4); 1083 1084 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1085 return (0); 1086 } 1087 1088 static __inline void 1089 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1090 { 1091 1092 sc->sc_rf_write(sc, chain, addr, val); 1093 } 1094 1095 static void 1096 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1097 uint32_t val) 1098 { 1099 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1100 SM(R92C_LSSI_PARAM_ADDR, addr) | 1101 SM(R92C_LSSI_PARAM_DATA, val)); 1102 } 1103 1104 static void 1105 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1106 uint32_t val) 1107 { 1108 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1109 SM(R88E_LSSI_PARAM_ADDR, addr) | 1110 SM(R92C_LSSI_PARAM_DATA, val)); 1111 } 1112 1113 static uint32_t 1114 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1115 { 1116 uint32_t reg[R92C_MAX_CHAINS], val; 1117 1118 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1119 if (chain != 0) 1120 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1121 1122 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1123 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1124 urtwn_ms_delay(sc); 1125 1126 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1127 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1128 R92C_HSSI_PARAM2_READ_EDGE); 1129 urtwn_ms_delay(sc); 1130 1131 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1132 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1133 urtwn_ms_delay(sc); 1134 1135 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1136 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1137 else 1138 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1139 return (MS(val, R92C_LSSI_READBACK_DATA)); 1140 } 1141 1142 static int 1143 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1144 { 1145 int ntries; 1146 1147 urtwn_write_4(sc, R92C_LLT_INIT, 1148 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1149 SM(R92C_LLT_INIT_ADDR, addr) | 1150 SM(R92C_LLT_INIT_DATA, data)); 1151 /* Wait for write operation to complete. */ 1152 for (ntries = 0; ntries < 20; ntries++) { 1153 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1154 R92C_LLT_INIT_OP_NO_ACTIVE) 1155 return (0); 1156 urtwn_ms_delay(sc); 1157 } 1158 return (ETIMEDOUT); 1159 } 1160 1161 static uint8_t 1162 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1163 { 1164 uint32_t reg; 1165 int ntries; 1166 1167 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1168 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1169 reg &= ~R92C_EFUSE_CTRL_VALID; 1170 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1171 /* Wait for read operation to complete. */ 1172 for (ntries = 0; ntries < 100; ntries++) { 1173 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1174 if (reg & R92C_EFUSE_CTRL_VALID) 1175 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1176 urtwn_ms_delay(sc); 1177 } 1178 device_printf(sc->sc_dev, 1179 "could not read efuse byte at address 0x%x\n", addr); 1180 return (0xff); 1181 } 1182 1183 static void 1184 urtwn_efuse_read(struct urtwn_softc *sc) 1185 { 1186 uint8_t *rom = (uint8_t *)&sc->rom; 1187 uint16_t addr = 0; 1188 uint32_t reg; 1189 uint8_t off, msk; 1190 int i; 1191 1192 urtwn_efuse_switch_power(sc); 1193 1194 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1195 while (addr < 512) { 1196 reg = urtwn_efuse_read_1(sc, addr); 1197 if (reg == 0xff) 1198 break; 1199 addr++; 1200 off = reg >> 4; 1201 msk = reg & 0xf; 1202 for (i = 0; i < 4; i++) { 1203 if (msk & (1 << i)) 1204 continue; 1205 rom[off * 8 + i * 2 + 0] = 1206 urtwn_efuse_read_1(sc, addr); 1207 addr++; 1208 rom[off * 8 + i * 2 + 1] = 1209 urtwn_efuse_read_1(sc, addr); 1210 addr++; 1211 } 1212 } 1213 #ifdef URTWN_DEBUG 1214 if (urtwn_debug >= 2) { 1215 /* Dump ROM content. */ 1216 printf("\n"); 1217 for (i = 0; i < sizeof(sc->rom); i++) 1218 printf("%02x:", rom[i]); 1219 printf("\n"); 1220 } 1221 #endif 1222 } 1223 static void 1224 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1225 { 1226 uint32_t reg; 1227 1228 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1229 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1230 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1231 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1232 } 1233 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1234 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1235 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1236 reg | R92C_SYS_FUNC_EN_ELDR); 1237 } 1238 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1239 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1240 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1241 urtwn_write_2(sc, R92C_SYS_CLKR, 1242 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1243 } 1244 } 1245 1246 static int 1247 urtwn_read_chipid(struct urtwn_softc *sc) 1248 { 1249 uint32_t reg; 1250 1251 if (sc->chip & URTWN_CHIP_88E) 1252 return (0); 1253 1254 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1255 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1256 return (EIO); 1257 1258 if (reg & R92C_SYS_CFG_TYPE_92C) { 1259 sc->chip |= URTWN_CHIP_92C; 1260 /* Check if it is a castrated 8192C. */ 1261 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1262 R92C_HPON_FSM_CHIP_BONDING_ID) == 1263 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1264 sc->chip |= URTWN_CHIP_92C_1T2R; 1265 } 1266 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1267 sc->chip |= URTWN_CHIP_UMC; 1268 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1269 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1270 } 1271 return (0); 1272 } 1273 1274 static void 1275 urtwn_read_rom(struct urtwn_softc *sc) 1276 { 1277 struct r92c_rom *rom = &sc->rom; 1278 1279 /* Read full ROM image. */ 1280 urtwn_efuse_read(sc); 1281 1282 /* XXX Weird but this is what the vendor driver does. */ 1283 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1284 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1285 1286 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1287 1288 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1289 DPRINTF("regulatory type=%d\n", sc->regulatory); 1290 IEEE80211_ADDR_COPY(sc->sc_bssid, rom->macaddr); 1291 1292 sc->sc_rf_write = urtwn_r92c_rf_write; 1293 sc->sc_power_on = urtwn_r92c_power_on; 1294 sc->sc_dma_init = urtwn_r92c_dma_init; 1295 } 1296 1297 static void 1298 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1299 { 1300 uint8_t *rom = sc->r88e_rom; 1301 uint16_t addr = 0; 1302 uint32_t reg; 1303 uint8_t off, msk, tmp; 1304 int i; 1305 1306 off = 0; 1307 urtwn_efuse_switch_power(sc); 1308 1309 /* Read full ROM image. */ 1310 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1311 while (addr < 1024) { 1312 reg = urtwn_efuse_read_1(sc, addr); 1313 if (reg == 0xff) 1314 break; 1315 addr++; 1316 if ((reg & 0x1f) == 0x0f) { 1317 tmp = (reg & 0xe0) >> 5; 1318 reg = urtwn_efuse_read_1(sc, addr); 1319 if ((reg & 0x0f) != 0x0f) 1320 off = ((reg & 0xf0) >> 1) | tmp; 1321 addr++; 1322 } else 1323 off = reg >> 4; 1324 msk = reg & 0xf; 1325 for (i = 0; i < 4; i++) { 1326 if (msk & (1 << i)) 1327 continue; 1328 rom[off * 8 + i * 2 + 0] = 1329 urtwn_efuse_read_1(sc, addr); 1330 addr++; 1331 rom[off * 8 + i * 2 + 1] = 1332 urtwn_efuse_read_1(sc, addr); 1333 addr++; 1334 } 1335 } 1336 1337 addr = 0x10; 1338 for (i = 0; i < 6; i++) 1339 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1340 for (i = 0; i < 5; i++) 1341 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1342 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1343 if (sc->bw20_tx_pwr_diff & 0x08) 1344 sc->bw20_tx_pwr_diff |= 0xf0; 1345 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1346 if (sc->ofdm_tx_pwr_diff & 0x08) 1347 sc->ofdm_tx_pwr_diff |= 0xf0; 1348 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1349 IEEE80211_ADDR_COPY(sc->sc_bssid, &sc->r88e_rom[0xd7]); 1350 1351 sc->sc_rf_write = urtwn_r88e_rf_write; 1352 sc->sc_power_on = urtwn_r88e_power_on; 1353 sc->sc_dma_init = urtwn_r88e_dma_init; 1354 } 1355 1356 /* 1357 * Initialize rate adaptation in firmware. 1358 */ 1359 static int 1360 urtwn_ra_init(struct urtwn_softc *sc) 1361 { 1362 static const uint8_t map[] = 1363 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1364 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1365 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1366 struct ieee80211_node *ni; 1367 struct ieee80211_rateset *rs; 1368 struct r92c_fw_cmd_macid_cfg cmd; 1369 uint32_t rates, basicrates; 1370 uint8_t mode; 1371 int maxrate, maxbasicrate, error, i, j; 1372 1373 ni = ieee80211_ref_node(vap->iv_bss); 1374 rs = &ni->ni_rates; 1375 1376 /* Get normal and basic rates mask. */ 1377 rates = basicrates = 0; 1378 maxrate = maxbasicrate = 0; 1379 for (i = 0; i < rs->rs_nrates; i++) { 1380 /* Convert 802.11 rate to HW rate index. */ 1381 for (j = 0; j < NELEM(map); j++) 1382 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1383 break; 1384 if (j == NELEM(map)) /* Unknown rate, skip. */ 1385 continue; 1386 rates |= 1 << j; 1387 if (j > maxrate) 1388 maxrate = j; 1389 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1390 basicrates |= 1 << j; 1391 if (j > maxbasicrate) 1392 maxbasicrate = j; 1393 } 1394 } 1395 if (ic->ic_curmode == IEEE80211_MODE_11B) 1396 mode = R92C_RAID_11B; 1397 else 1398 mode = R92C_RAID_11BG; 1399 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1400 mode, rates, basicrates); 1401 1402 /* Set rates mask for group addressed frames. */ 1403 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1404 cmd.mask = htole32(mode << 28 | basicrates); 1405 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1406 if (error != 0) { 1407 ieee80211_free_node(ni); 1408 device_printf(sc->sc_dev, 1409 "could not add broadcast station\n"); 1410 return (error); 1411 } 1412 /* Set initial MRR rate. */ 1413 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1414 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1415 maxbasicrate); 1416 1417 /* Set rates mask for unicast frames. */ 1418 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1419 cmd.mask = htole32(mode << 28 | rates); 1420 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1421 if (error != 0) { 1422 ieee80211_free_node(ni); 1423 device_printf(sc->sc_dev, "could not add BSS station\n"); 1424 return (error); 1425 } 1426 /* Set initial MRR rate. */ 1427 DPRINTF("maxrate=%d\n", maxrate); 1428 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1429 maxrate); 1430 1431 /* Indicate highest supported rate. */ 1432 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1433 ieee80211_free_node(ni); 1434 1435 return (0); 1436 } 1437 1438 void 1439 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1440 { 1441 struct ifnet *ifp = sc->sc_ifp; 1442 struct ieee80211com *ic = ifp->if_l2com; 1443 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1444 struct ieee80211_node *ni = vap->iv_bss; 1445 1446 uint64_t tsf; 1447 1448 /* Enable TSF synchronization. */ 1449 urtwn_write_1(sc, R92C_BCN_CTRL, 1450 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1451 1452 urtwn_write_1(sc, R92C_BCN_CTRL, 1453 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1454 1455 /* Set initial TSF. */ 1456 memcpy(&tsf, ni->ni_tstamp.data, 8); 1457 tsf = le64toh(tsf); 1458 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1459 tsf -= IEEE80211_DUR_TU; 1460 urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1461 urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1462 1463 urtwn_write_1(sc, R92C_BCN_CTRL, 1464 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1465 } 1466 1467 static void 1468 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1469 { 1470 uint8_t reg; 1471 1472 if (led == URTWN_LED_LINK) { 1473 if (sc->chip & URTWN_CHIP_88E) { 1474 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1475 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1476 if (!on) { 1477 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1478 urtwn_write_1(sc, R92C_LEDCFG2, 1479 reg | R92C_LEDCFG0_DIS); 1480 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1481 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1482 0xfe); 1483 } 1484 } else { 1485 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1486 if (!on) 1487 reg |= R92C_LEDCFG0_DIS; 1488 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1489 } 1490 sc->ledlink = on; /* Save LED state. */ 1491 } 1492 } 1493 1494 static int 1495 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1496 { 1497 struct urtwn_vap *uvp = URTWN_VAP(vap); 1498 struct ieee80211com *ic = vap->iv_ic; 1499 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1500 struct ieee80211_node *ni; 1501 enum ieee80211_state ostate; 1502 uint32_t reg; 1503 1504 ostate = vap->iv_state; 1505 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1506 ieee80211_state_name[nstate]); 1507 1508 URTWN_LOCK(sc); 1509 callout_stop(&sc->sc_watchdog_ch); 1510 1511 if (ostate == IEEE80211_S_RUN) { 1512 /* Turn link LED off. */ 1513 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1514 1515 /* Set media status to 'No Link'. */ 1516 reg = urtwn_read_4(sc, R92C_CR); 1517 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1518 urtwn_write_4(sc, R92C_CR, reg); 1519 1520 /* Stop Rx of data frames. */ 1521 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1522 1523 /* Rest TSF. */ 1524 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1525 1526 /* Disable TSF synchronization. */ 1527 urtwn_write_1(sc, R92C_BCN_CTRL, 1528 urtwn_read_1(sc, R92C_BCN_CTRL) | 1529 R92C_BCN_CTRL_DIS_TSF_UDT0); 1530 1531 /* Reset EDCA parameters. */ 1532 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1533 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1534 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1535 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1536 } 1537 1538 switch (nstate) { 1539 case IEEE80211_S_INIT: 1540 /* Turn link LED off. */ 1541 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1542 break; 1543 case IEEE80211_S_SCAN: 1544 if (ostate != IEEE80211_S_SCAN) { 1545 /* Allow Rx from any BSSID. */ 1546 urtwn_write_4(sc, R92C_RCR, 1547 urtwn_read_4(sc, R92C_RCR) & 1548 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1549 1550 /* Set gain for scanning. */ 1551 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1552 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1553 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1554 1555 if (!(sc->chip & URTWN_CHIP_88E)) { 1556 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1557 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1558 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1559 } 1560 } 1561 /* Make link LED blink during scan. */ 1562 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1563 1564 /* Pause AC Tx queues. */ 1565 urtwn_write_1(sc, R92C_TXPAUSE, 1566 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1567 1568 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1569 break; 1570 case IEEE80211_S_AUTH: 1571 /* Set initial gain under link. */ 1572 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1573 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1574 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1575 1576 if (!(sc->chip & URTWN_CHIP_88E)) { 1577 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1578 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1579 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1580 } 1581 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1582 break; 1583 case IEEE80211_S_RUN: 1584 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1585 /* Enable Rx of data frames. */ 1586 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1587 1588 /* Turn link LED on. */ 1589 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1590 break; 1591 } 1592 1593 ni = ieee80211_ref_node(vap->iv_bss); 1594 /* Set media status to 'Associated'. */ 1595 reg = urtwn_read_4(sc, R92C_CR); 1596 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1597 urtwn_write_4(sc, R92C_CR, reg); 1598 1599 /* Set BSSID. */ 1600 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1601 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1602 1603 if (ic->ic_curmode == IEEE80211_MODE_11B) 1604 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1605 else /* 802.11b/g */ 1606 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1607 1608 /* Enable Rx of data frames. */ 1609 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1610 1611 /* Flush all AC queues. */ 1612 urtwn_write_1(sc, R92C_TXPAUSE, 0); 1613 1614 /* Set beacon interval. */ 1615 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1616 1617 /* Allow Rx from our BSSID only. */ 1618 urtwn_write_4(sc, R92C_RCR, 1619 urtwn_read_4(sc, R92C_RCR) | 1620 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1621 1622 /* Enable TSF synchronization. */ 1623 urtwn_tsf_sync_enable(sc); 1624 1625 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1626 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1627 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1628 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1629 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1630 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1631 1632 /* Intialize rate adaptation. */ 1633 if (sc->chip & URTWN_CHIP_88E) 1634 ni->ni_txrate = 1635 ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1636 else 1637 urtwn_ra_init(sc); 1638 /* Turn link LED on. */ 1639 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1640 1641 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1642 /* Reset temperature calibration state machine. */ 1643 sc->thcal_state = 0; 1644 sc->thcal_lctemp = 0; 1645 ieee80211_free_node(ni); 1646 break; 1647 default: 1648 break; 1649 } 1650 URTWN_UNLOCK(sc); 1651 return(uvp->newstate(vap, nstate, arg)); 1652 } 1653 1654 static void 1655 urtwn_watchdog(void *arg) 1656 { 1657 struct urtwn_softc *sc = arg; 1658 struct ifnet *ifp = sc->sc_ifp; 1659 1660 if (sc->sc_txtimer > 0) { 1661 if (--sc->sc_txtimer == 0) { 1662 device_printf(sc->sc_dev, "device timeout\n"); 1663 ifp->if_oerrors++; 1664 return; 1665 } 1666 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1667 } 1668 } 1669 1670 static void 1671 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1672 { 1673 int pwdb; 1674 1675 /* Convert antenna signal to percentage. */ 1676 if (rssi <= -100 || rssi >= 20) 1677 pwdb = 0; 1678 else if (rssi >= 0) 1679 pwdb = 100; 1680 else 1681 pwdb = 100 + rssi; 1682 if (!(sc->chip & URTWN_CHIP_88E)) { 1683 if (rate <= 3) { 1684 /* CCK gain is smaller than OFDM/MCS gain. */ 1685 pwdb += 6; 1686 if (pwdb > 100) 1687 pwdb = 100; 1688 if (pwdb <= 14) 1689 pwdb -= 4; 1690 else if (pwdb <= 26) 1691 pwdb -= 8; 1692 else if (pwdb <= 34) 1693 pwdb -= 6; 1694 else if (pwdb <= 42) 1695 pwdb -= 2; 1696 } 1697 } 1698 if (sc->avg_pwdb == -1) /* Init. */ 1699 sc->avg_pwdb = pwdb; 1700 else if (sc->avg_pwdb < pwdb) 1701 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1702 else 1703 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1704 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1705 } 1706 1707 static int8_t 1708 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1709 { 1710 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1711 struct r92c_rx_phystat *phy; 1712 struct r92c_rx_cck *cck; 1713 uint8_t rpt; 1714 int8_t rssi; 1715 1716 if (rate <= 3) { 1717 cck = (struct r92c_rx_cck *)physt; 1718 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1719 rpt = (cck->agc_rpt >> 5) & 0x3; 1720 rssi = (cck->agc_rpt & 0x1f) << 1; 1721 } else { 1722 rpt = (cck->agc_rpt >> 6) & 0x3; 1723 rssi = cck->agc_rpt & 0x3e; 1724 } 1725 rssi = cckoff[rpt] - rssi; 1726 } else { /* OFDM/HT. */ 1727 phy = (struct r92c_rx_phystat *)physt; 1728 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1729 } 1730 return (rssi); 1731 } 1732 1733 static int8_t 1734 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1735 { 1736 struct r92c_rx_phystat *phy; 1737 struct r88e_rx_cck *cck; 1738 uint8_t cck_agc_rpt, lna_idx, vga_idx; 1739 int8_t rssi; 1740 1741 rssi = 0; 1742 if (rate <= 3) { 1743 cck = (struct r88e_rx_cck *)physt; 1744 cck_agc_rpt = cck->agc_rpt; 1745 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1746 vga_idx = cck_agc_rpt & 0x1f; 1747 switch (lna_idx) { 1748 case 7: 1749 if (vga_idx <= 27) 1750 rssi = -100 + 2* (27 - vga_idx); 1751 else 1752 rssi = -100; 1753 break; 1754 case 6: 1755 rssi = -48 + 2 * (2 - vga_idx); 1756 break; 1757 case 5: 1758 rssi = -42 + 2 * (7 - vga_idx); 1759 break; 1760 case 4: 1761 rssi = -36 + 2 * (7 - vga_idx); 1762 break; 1763 case 3: 1764 rssi = -24 + 2 * (7 - vga_idx); 1765 break; 1766 case 2: 1767 rssi = -12 + 2 * (5 - vga_idx); 1768 break; 1769 case 1: 1770 rssi = 8 - (2 * vga_idx); 1771 break; 1772 case 0: 1773 rssi = 14 - (2 * vga_idx); 1774 break; 1775 } 1776 rssi += 6; 1777 } else { /* OFDM/HT. */ 1778 phy = (struct r92c_rx_phystat *)physt; 1779 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1780 } 1781 return (rssi); 1782 } 1783 1784 1785 static int 1786 urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1787 struct mbuf *m0, struct urtwn_data *data) 1788 { 1789 struct ifnet *ifp = sc->sc_ifp; 1790 struct ieee80211_frame *wh; 1791 struct ieee80211_key *k; 1792 struct ieee80211com *ic = ifp->if_l2com; 1793 struct ieee80211vap *vap = ni->ni_vap; 1794 struct usb_xfer *xfer; 1795 struct r92c_tx_desc *txd; 1796 uint8_t raid, type; 1797 uint16_t sum; 1798 int i, hasqos, xferlen; 1799 struct usb_xfer *urtwn_pipes[4] = { 1800 sc->sc_xfer[URTWN_BULK_TX_BE], 1801 sc->sc_xfer[URTWN_BULK_TX_BK], 1802 sc->sc_xfer[URTWN_BULK_TX_VI], 1803 sc->sc_xfer[URTWN_BULK_TX_VO] 1804 }; 1805 1806 URTWN_ASSERT_LOCKED(sc); 1807 1808 /* 1809 * Software crypto. 1810 */ 1811 wh = mtod(m0, struct ieee80211_frame *); 1812 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1813 1814 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1815 k = ieee80211_crypto_encap(ni, m0); 1816 if (k == NULL) { 1817 device_printf(sc->sc_dev, 1818 "ieee80211_crypto_encap returns NULL.\n"); 1819 /* XXX we don't expect the fragmented frames */ 1820 m_freem(m0); 1821 return (ENOBUFS); 1822 } 1823 1824 /* in case packet header moved, reset pointer */ 1825 wh = mtod(m0, struct ieee80211_frame *); 1826 } 1827 1828 switch (type) { 1829 case IEEE80211_FC0_TYPE_CTL: 1830 case IEEE80211_FC0_TYPE_MGT: 1831 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1832 break; 1833 default: 1834 KASSERT(M_WME_GETAC(m0) < 4, 1835 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1836 xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1837 break; 1838 } 1839 1840 hasqos = 0; 1841 1842 /* Fill Tx descriptor. */ 1843 txd = (struct r92c_tx_desc *)data->buf; 1844 memset(txd, 0, sizeof(*txd)); 1845 1846 txd->txdw0 |= htole32( 1847 SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1848 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1849 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1850 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1851 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1852 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1853 type == IEEE80211_FC0_TYPE_DATA) { 1854 if (ic->ic_curmode == IEEE80211_MODE_11B) 1855 raid = R92C_RAID_11B; 1856 else 1857 raid = R92C_RAID_11BG; 1858 if (sc->chip & URTWN_CHIP_88E) { 1859 txd->txdw1 |= htole32( 1860 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1861 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1862 SM(R92C_TXDW1_RAID, raid)); 1863 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1864 } else { 1865 txd->txdw1 |= htole32( 1866 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1867 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1868 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1869 } 1870 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1871 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1872 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1873 R92C_TXDW4_HWRTSEN); 1874 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1875 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1876 R92C_TXDW4_HWRTSEN); 1877 } 1878 } 1879 /* Send RTS at OFDM24. */ 1880 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1881 txd->txdw5 |= htole32(0x0001ff00); 1882 /* Send data at OFDM54. */ 1883 if (sc->chip & URTWN_CHIP_88E) 1884 txd->txdw5 |= htole32(0x13 & 0x3f); 1885 else 1886 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1887 } else { 1888 txd->txdw1 |= htole32( 1889 SM(R92C_TXDW1_MACID, 0) | 1890 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1891 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1892 1893 /* Force CCK1. */ 1894 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1895 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1896 } 1897 /* Set sequence number (already little endian). */ 1898 txd->txdseq |= *(uint16_t *)wh->i_seq; 1899 1900 if (!hasqos) { 1901 /* Use HW sequence numbering for non-QoS frames. */ 1902 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1903 txd->txdseq |= htole16(0x8000); 1904 } else 1905 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1906 1907 /* Compute Tx descriptor checksum. */ 1908 sum = 0; 1909 for (i = 0; i < sizeof(*txd) / 2; i++) 1910 sum ^= ((uint16_t *)txd)[i]; 1911 txd->txdsum = sum; /* NB: already little endian. */ 1912 1913 if (ieee80211_radiotap_active_vap(vap)) { 1914 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1915 1916 tap->wt_flags = 0; 1917 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1918 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1919 ieee80211_radiotap_tx(vap, m0); 1920 } 1921 1922 xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1923 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1924 1925 data->buflen = xferlen; 1926 data->ni = ni; 1927 data->m = m0; 1928 1929 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1930 usbd_transfer_start(xfer); 1931 return (0); 1932 } 1933 1934 static void 1935 urtwn_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1936 { 1937 if ((ifp->if_flags & IFF_RUNNING) == 0) 1938 return; 1939 1940 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1941 urtwn_start_locked(ifp); 1942 } 1943 1944 static void 1945 urtwn_start_locked(struct ifnet *ifp) 1946 { 1947 struct urtwn_softc *sc = ifp->if_softc; 1948 struct ieee80211_node *ni; 1949 struct mbuf *m; 1950 struct urtwn_data *bf; 1951 1952 URTWN_LOCK(sc); 1953 for (;;) { 1954 m = ifq_dequeue(&ifp->if_snd); 1955 if (m == NULL) 1956 break; 1957 bf = urtwn_getbuf(sc); 1958 if (bf == NULL) { 1959 ifq_prepend(&ifp->if_snd, m); 1960 break; 1961 } 1962 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1963 m->m_pkthdr.rcvif = NULL; 1964 1965 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 1966 ifp->if_oerrors++; 1967 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1968 ieee80211_free_node(ni); 1969 break; 1970 } 1971 1972 sc->sc_txtimer = 5; 1973 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1974 } 1975 URTWN_UNLOCK(sc); 1976 } 1977 1978 static int 1979 urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred) 1980 { 1981 struct urtwn_softc *sc = ifp->if_softc; 1982 struct ieee80211com *ic = ifp->if_l2com; 1983 struct ifreq *ifr = (struct ifreq *) data; 1984 int error = 0, startall = 0; 1985 1986 URTWN_LOCK(sc); 1987 error = (sc->sc_flags & URTWN_DETACHED) ? ENXIO : 0; 1988 URTWN_UNLOCK(sc); 1989 if (error != 0) 1990 return (error); 1991 1992 switch (cmd) { 1993 case SIOCSIFFLAGS: 1994 if (ifp->if_flags & IFF_UP) { 1995 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1996 urtwn_init(ifp->if_softc); 1997 startall = 1; 1998 } 1999 } else { 2000 if (ifp->if_flags & IFF_RUNNING) 2001 urtwn_stop(ifp); 2002 } 2003 if (startall) 2004 ieee80211_start_all(ic); 2005 break; 2006 case SIOCGIFMEDIA: 2007 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 2008 break; 2009 case SIOCGIFADDR: 2010 error = ether_ioctl(ifp, cmd, data); 2011 break; 2012 default: 2013 error = EINVAL; 2014 break; 2015 } 2016 return (error); 2017 } 2018 2019 static int 2020 urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 2021 int ndata, int maxsz) 2022 { 2023 int i; 2024 2025 for (i = 0; i < ndata; i++) { 2026 struct urtwn_data *dp = &data[i]; 2027 dp->sc = sc; 2028 dp->m = NULL; 2029 dp->buf = kmalloc(maxsz, M_USBDEV, M_WAITOK); 2030 dp->ni = NULL; 2031 } 2032 2033 return (0); 2034 } 2035 2036 static int 2037 urtwn_alloc_rx_list(struct urtwn_softc *sc) 2038 { 2039 int error, i; 2040 2041 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 2042 URTWN_RXBUFSZ); 2043 if (error != 0) 2044 return (error); 2045 2046 STAILQ_INIT(&sc->sc_rx_active); 2047 STAILQ_INIT(&sc->sc_rx_inactive); 2048 2049 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 2050 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 2051 2052 return (0); 2053 } 2054 2055 static int 2056 urtwn_alloc_tx_list(struct urtwn_softc *sc) 2057 { 2058 int error, i; 2059 2060 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 2061 URTWN_TXBUFSZ); 2062 if (error != 0) 2063 return (error); 2064 2065 STAILQ_INIT(&sc->sc_tx_active); 2066 STAILQ_INIT(&sc->sc_tx_inactive); 2067 STAILQ_INIT(&sc->sc_tx_pending); 2068 2069 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 2070 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 2071 2072 return (0); 2073 } 2074 2075 static __inline int 2076 urtwn_power_on(struct urtwn_softc *sc) 2077 { 2078 2079 return sc->sc_power_on(sc); 2080 } 2081 2082 static int 2083 urtwn_r92c_power_on(struct urtwn_softc *sc) 2084 { 2085 uint32_t reg; 2086 int ntries; 2087 2088 /* Wait for autoload done bit. */ 2089 for (ntries = 0; ntries < 1000; ntries++) { 2090 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2091 break; 2092 urtwn_ms_delay(sc); 2093 } 2094 if (ntries == 1000) { 2095 device_printf(sc->sc_dev, 2096 "timeout waiting for chip autoload\n"); 2097 return (ETIMEDOUT); 2098 } 2099 2100 /* Unlock ISO/CLK/Power control register. */ 2101 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2102 /* Move SPS into PWM mode. */ 2103 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2104 urtwn_ms_delay(sc); 2105 2106 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2107 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2108 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2109 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2110 urtwn_ms_delay(sc); 2111 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2112 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2113 ~R92C_SYS_ISO_CTRL_MD2PP); 2114 } 2115 2116 /* Auto enable WLAN. */ 2117 urtwn_write_2(sc, R92C_APS_FSMCO, 2118 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2119 for (ntries = 0; ntries < 1000; ntries++) { 2120 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2121 R92C_APS_FSMCO_APFM_ONMAC)) 2122 break; 2123 urtwn_ms_delay(sc); 2124 } 2125 if (ntries == 1000) { 2126 device_printf(sc->sc_dev, 2127 "timeout waiting for MAC auto ON\n"); 2128 return (ETIMEDOUT); 2129 } 2130 2131 /* Enable radio, GPIO and LED functions. */ 2132 urtwn_write_2(sc, R92C_APS_FSMCO, 2133 R92C_APS_FSMCO_AFSM_HSUS | 2134 R92C_APS_FSMCO_PDN_EN | 2135 R92C_APS_FSMCO_PFM_ALDN); 2136 /* Release RF digital isolation. */ 2137 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2138 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2139 2140 /* Initialize MAC. */ 2141 urtwn_write_1(sc, R92C_APSD_CTRL, 2142 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2143 for (ntries = 0; ntries < 200; ntries++) { 2144 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2145 R92C_APSD_CTRL_OFF_STATUS)) 2146 break; 2147 urtwn_ms_delay(sc); 2148 } 2149 if (ntries == 200) { 2150 device_printf(sc->sc_dev, 2151 "timeout waiting for MAC initialization\n"); 2152 return (ETIMEDOUT); 2153 } 2154 2155 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2156 reg = urtwn_read_2(sc, R92C_CR); 2157 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2158 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2159 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2160 R92C_CR_ENSEC; 2161 urtwn_write_2(sc, R92C_CR, reg); 2162 2163 urtwn_write_1(sc, 0xfe10, 0x19); 2164 return (0); 2165 } 2166 2167 static int 2168 urtwn_r88e_power_on(struct urtwn_softc *sc) 2169 { 2170 uint8_t val; 2171 uint32_t reg; 2172 int ntries; 2173 2174 /* Wait for power ready bit. */ 2175 for (ntries = 0; ntries < 5000; ntries++) { 2176 val = urtwn_read_1(sc, 0x6) & 0x2; 2177 if (val == 0x2) 2178 break; 2179 urtwn_ms_delay(sc); 2180 } 2181 if (ntries == 5000) { 2182 device_printf(sc->sc_dev, 2183 "timeout waiting for chip power up\n"); 2184 return (ETIMEDOUT); 2185 } 2186 2187 /* Reset BB. */ 2188 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2189 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2190 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2191 2192 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 2193 2194 /* Disable HWPDN. */ 2195 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 2196 2197 /* Disable WL suspend. */ 2198 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 2199 2200 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 2201 for (ntries = 0; ntries < 5000; ntries++) { 2202 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 2203 break; 2204 urtwn_ms_delay(sc); 2205 } 2206 if (ntries == 5000) 2207 return (ETIMEDOUT); 2208 2209 /* Enable LDO normal mode. */ 2210 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 2211 2212 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2213 urtwn_write_2(sc, R92C_CR, 0); 2214 reg = urtwn_read_2(sc, R92C_CR); 2215 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2216 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2217 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2218 urtwn_write_2(sc, R92C_CR, reg); 2219 2220 return (0); 2221 } 2222 2223 static int 2224 urtwn_llt_init(struct urtwn_softc *sc) 2225 { 2226 int i, error, page_count, pktbuf_count; 2227 2228 page_count = (sc->chip & URTWN_CHIP_88E) ? 2229 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2230 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2231 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2232 2233 /* Reserve pages [0; page_count]. */ 2234 for (i = 0; i < page_count; i++) { 2235 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2236 return (error); 2237 } 2238 /* NB: 0xff indicates end-of-list. */ 2239 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2240 return (error); 2241 /* 2242 * Use pages [page_count + 1; pktbuf_count - 1] 2243 * as ring buffer. 2244 */ 2245 for (++i; i < pktbuf_count - 1; i++) { 2246 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2247 return (error); 2248 } 2249 /* Make the last page point to the beginning of the ring buffer. */ 2250 error = urtwn_llt_write(sc, i, page_count + 1); 2251 return (error); 2252 } 2253 2254 static void 2255 urtwn_fw_reset(struct urtwn_softc *sc) 2256 { 2257 uint16_t reg; 2258 int ntries; 2259 2260 /* Tell 8051 to reset itself. */ 2261 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2262 2263 /* Wait until 8051 resets by itself. */ 2264 for (ntries = 0; ntries < 100; ntries++) { 2265 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2266 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2267 return; 2268 urtwn_ms_delay(sc); 2269 } 2270 /* Force 8051 reset. */ 2271 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2272 } 2273 2274 static void 2275 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 2276 { 2277 uint16_t reg; 2278 2279 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2280 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2281 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2282 } 2283 2284 static int 2285 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2286 { 2287 uint32_t reg; 2288 int off, mlen, error = 0; 2289 2290 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2291 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2292 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2293 2294 off = R92C_FW_START_ADDR; 2295 while (len > 0) { 2296 if (len > 196) 2297 mlen = 196; 2298 else if (len > 4) 2299 mlen = 4; 2300 else 2301 mlen = 1; 2302 /* XXX fix this deconst */ 2303 error = urtwn_write_region_1(sc, off, 2304 __DECONST(uint8_t *, buf), mlen); 2305 if (error != 0) 2306 break; 2307 off += mlen; 2308 buf += mlen; 2309 len -= mlen; 2310 } 2311 return (error); 2312 } 2313 2314 static int 2315 urtwn_load_firmware(struct urtwn_softc *sc) 2316 { 2317 const struct firmware *fw; 2318 const struct r92c_fw_hdr *hdr; 2319 const char *imagename; 2320 const u_char *ptr; 2321 size_t len; 2322 uint32_t reg; 2323 int mlen, ntries, page, error; 2324 2325 URTWN_UNLOCK(sc); 2326 /* Read firmware image from the filesystem. */ 2327 if (sc->chip & URTWN_CHIP_88E) 2328 imagename = "urtwn-rtl8188eufw"; 2329 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2330 URTWN_CHIP_UMC_A_CUT) 2331 imagename = "urtwn-rtl8192cfwU"; 2332 else 2333 imagename = "urtwn-rtl8192cfwT"; 2334 2335 fw = firmware_get(imagename); 2336 URTWN_LOCK(sc); 2337 if (fw == NULL) { 2338 device_printf(sc->sc_dev, 2339 "failed loadfirmware of file %s\n", imagename); 2340 return (ENOENT); 2341 } 2342 2343 len = fw->datasize; 2344 2345 if (len < sizeof(*hdr)) { 2346 device_printf(sc->sc_dev, "firmware too short\n"); 2347 error = EINVAL; 2348 goto fail; 2349 } 2350 ptr = fw->data; 2351 hdr = (const struct r92c_fw_hdr *)ptr; 2352 /* Check if there is a valid FW header and skip it. */ 2353 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2354 (le16toh(hdr->signature) >> 4) == 0x88e || 2355 (le16toh(hdr->signature) >> 4) == 0x92c) { 2356 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2357 le16toh(hdr->version), le16toh(hdr->subversion), 2358 hdr->month, hdr->date, hdr->hour, hdr->minute); 2359 ptr += sizeof(*hdr); 2360 len -= sizeof(*hdr); 2361 } 2362 2363 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2364 if (sc->chip & URTWN_CHIP_88E) 2365 urtwn_r88e_fw_reset(sc); 2366 else 2367 urtwn_fw_reset(sc); 2368 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2369 } 2370 2371 if (!(sc->chip & URTWN_CHIP_88E)) { 2372 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2373 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2374 R92C_SYS_FUNC_EN_CPUEN); 2375 } 2376 urtwn_write_1(sc, R92C_MCUFWDL, 2377 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2378 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2379 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2380 2381 /* Reset the FWDL checksum. */ 2382 urtwn_write_1(sc, R92C_MCUFWDL, 2383 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2384 2385 for (page = 0; len > 0; page++) { 2386 mlen = min(len, R92C_FW_PAGE_SIZE); 2387 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2388 if (error != 0) { 2389 device_printf(sc->sc_dev, 2390 "could not load firmware page\n"); 2391 goto fail; 2392 } 2393 ptr += mlen; 2394 len -= mlen; 2395 } 2396 urtwn_write_1(sc, R92C_MCUFWDL, 2397 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2398 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2399 2400 /* Wait for checksum report. */ 2401 for (ntries = 0; ntries < 1000; ntries++) { 2402 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2403 break; 2404 urtwn_ms_delay(sc); 2405 } 2406 if (ntries == 1000) { 2407 device_printf(sc->sc_dev, 2408 "timeout waiting for checksum report\n"); 2409 error = ETIMEDOUT; 2410 goto fail; 2411 } 2412 2413 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2414 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2415 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2416 if (sc->chip & URTWN_CHIP_88E) 2417 urtwn_r88e_fw_reset(sc); 2418 /* Wait for firmware readiness. */ 2419 for (ntries = 0; ntries < 1000; ntries++) { 2420 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2421 break; 2422 urtwn_ms_delay(sc); 2423 } 2424 if (ntries == 1000) { 2425 device_printf(sc->sc_dev, 2426 "timeout waiting for firmware readiness\n"); 2427 error = ETIMEDOUT; 2428 goto fail; 2429 } 2430 fail: 2431 firmware_put(fw, FIRMWARE_UNLOAD); 2432 return (error); 2433 } 2434 2435 static __inline int 2436 urtwn_dma_init(struct urtwn_softc *sc) 2437 { 2438 return sc->sc_dma_init(sc); 2439 } 2440 2441 static int 2442 urtwn_r92c_dma_init(struct urtwn_softc *sc) 2443 { 2444 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2445 uint32_t reg; 2446 int error; 2447 2448 /* Initialize LLT table. */ 2449 error = urtwn_llt_init(sc); 2450 if (error != 0) 2451 return (error); 2452 2453 /* Get Tx queues to USB endpoints mapping. */ 2454 hashq = hasnq = haslq = 0; 2455 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2456 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2457 if (MS(reg, R92C_USB_EP_HQ) != 0) 2458 hashq = 1; 2459 if (MS(reg, R92C_USB_EP_NQ) != 0) 2460 hasnq = 1; 2461 if (MS(reg, R92C_USB_EP_LQ) != 0) 2462 haslq = 1; 2463 nqueues = hashq + hasnq + haslq; 2464 if (nqueues == 0) 2465 return (EIO); 2466 /* Get the number of pages for each queue. */ 2467 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2468 /* The remaining pages are assigned to the high priority queue. */ 2469 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2470 2471 /* Set number of pages for normal priority queue. */ 2472 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2473 urtwn_write_4(sc, R92C_RQPN, 2474 /* Set number of pages for public queue. */ 2475 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2476 /* Set number of pages for high priority queue. */ 2477 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2478 /* Set number of pages for low priority queue. */ 2479 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2480 /* Load values. */ 2481 R92C_RQPN_LD); 2482 2483 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2484 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2485 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2486 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2487 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2488 2489 /* Set queue to USB pipe mapping. */ 2490 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2491 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2492 if (nqueues == 1) { 2493 if (hashq) 2494 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2495 else if (hasnq) 2496 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2497 else 2498 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2499 } else if (nqueues == 2) { 2500 /* All 2-endpoints configs have a high priority queue. */ 2501 if (!hashq) 2502 return (EIO); 2503 if (hasnq) 2504 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2505 else 2506 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2507 } else 2508 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2509 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2510 2511 /* Set Tx/Rx transfer page boundary. */ 2512 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2513 2514 /* Set Tx/Rx transfer page size. */ 2515 urtwn_write_1(sc, R92C_PBP, 2516 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2517 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2518 return (0); 2519 } 2520 2521 static int 2522 urtwn_r88e_dma_init(struct urtwn_softc *sc) 2523 { 2524 struct usb_interface *iface; 2525 uint32_t reg; 2526 int nqueues; 2527 int error; 2528 2529 /* Initialize LLT table. */ 2530 error = urtwn_llt_init(sc); 2531 if (error != 0) 2532 return (error); 2533 2534 /* Get Tx queues to USB endpoints mapping. */ 2535 iface = usbd_get_iface(sc->sc_udev, 0); 2536 nqueues = iface->idesc->bNumEndpoints - 1; 2537 if (nqueues == 0) 2538 return (EIO); 2539 2540 /* Set number of pages for normal priority queue. */ 2541 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2542 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2543 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2544 2545 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2546 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2547 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2548 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2549 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2550 2551 /* Set queue to USB pipe mapping. */ 2552 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2553 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2554 if (nqueues == 1) 2555 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2556 else if (nqueues == 2) 2557 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2558 else 2559 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2560 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2561 2562 /* Set Tx/Rx transfer page boundary. */ 2563 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2564 2565 /* Set Tx/Rx transfer page size. */ 2566 urtwn_write_1(sc, R92C_PBP, 2567 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2568 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2569 2570 return (0); 2571 } 2572 2573 static void 2574 urtwn_mac_init(struct urtwn_softc *sc) 2575 { 2576 int i; 2577 2578 /* Write MAC initialization values. */ 2579 if (sc->chip & URTWN_CHIP_88E) { 2580 for (i = 0; i < NELEM(rtl8188eu_mac); i++) { 2581 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2582 rtl8188eu_mac[i].val); 2583 } 2584 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2585 } else { 2586 for (i = 0; i < NELEM(rtl8192cu_mac); i++) 2587 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2588 rtl8192cu_mac[i].val); 2589 } 2590 } 2591 2592 static void 2593 urtwn_bb_init(struct urtwn_softc *sc) 2594 { 2595 const struct urtwn_bb_prog *prog; 2596 uint32_t reg; 2597 uint8_t crystalcap; 2598 int i; 2599 2600 /* Enable BB and RF. */ 2601 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2602 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2603 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2604 R92C_SYS_FUNC_EN_DIO_RF); 2605 2606 if (!(sc->chip & URTWN_CHIP_88E)) 2607 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2608 2609 urtwn_write_1(sc, R92C_RF_CTRL, 2610 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2611 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2612 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2613 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2614 2615 if (!(sc->chip & URTWN_CHIP_88E)) { 2616 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2617 urtwn_write_1(sc, 0x15, 0xe9); 2618 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2619 } 2620 2621 /* Select BB programming based on board type. */ 2622 if (sc->chip & URTWN_CHIP_88E) 2623 prog = &rtl8188eu_bb_prog; 2624 else if (!(sc->chip & URTWN_CHIP_92C)) { 2625 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2626 prog = &rtl8188ce_bb_prog; 2627 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2628 prog = &rtl8188ru_bb_prog; 2629 else 2630 prog = &rtl8188cu_bb_prog; 2631 } else { 2632 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2633 prog = &rtl8192ce_bb_prog; 2634 else 2635 prog = &rtl8192cu_bb_prog; 2636 } 2637 /* Write BB initialization values. */ 2638 for (i = 0; i < prog->count; i++) { 2639 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2640 urtwn_ms_delay(sc); 2641 } 2642 2643 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2644 /* 8192C 1T only configuration. */ 2645 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2646 reg = (reg & ~0x00000003) | 0x2; 2647 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2648 2649 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2650 reg = (reg & ~0x00300033) | 0x00200022; 2651 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2652 2653 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2654 reg = (reg & ~0xff000000) | 0x45 << 24; 2655 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2656 2657 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2658 reg = (reg & ~0x000000ff) | 0x23; 2659 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2660 2661 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2662 reg = (reg & ~0x00000030) | 1 << 4; 2663 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2664 2665 reg = urtwn_bb_read(sc, 0xe74); 2666 reg = (reg & ~0x0c000000) | 2 << 26; 2667 urtwn_bb_write(sc, 0xe74, reg); 2668 reg = urtwn_bb_read(sc, 0xe78); 2669 reg = (reg & ~0x0c000000) | 2 << 26; 2670 urtwn_bb_write(sc, 0xe78, reg); 2671 reg = urtwn_bb_read(sc, 0xe7c); 2672 reg = (reg & ~0x0c000000) | 2 << 26; 2673 urtwn_bb_write(sc, 0xe7c, reg); 2674 reg = urtwn_bb_read(sc, 0xe80); 2675 reg = (reg & ~0x0c000000) | 2 << 26; 2676 urtwn_bb_write(sc, 0xe80, reg); 2677 reg = urtwn_bb_read(sc, 0xe88); 2678 reg = (reg & ~0x0c000000) | 2 << 26; 2679 urtwn_bb_write(sc, 0xe88, reg); 2680 } 2681 2682 /* Write AGC values. */ 2683 for (i = 0; i < prog->agccount; i++) { 2684 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2685 prog->agcvals[i]); 2686 urtwn_ms_delay(sc); 2687 } 2688 2689 if (sc->chip & URTWN_CHIP_88E) { 2690 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2691 urtwn_ms_delay(sc); 2692 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2693 urtwn_ms_delay(sc); 2694 2695 crystalcap = sc->r88e_rom[0xb9]; 2696 if (crystalcap == 0xff) 2697 crystalcap = 0x20; 2698 crystalcap &= 0x3f; 2699 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2700 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2701 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2702 crystalcap | crystalcap << 6)); 2703 } else { 2704 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2705 R92C_HSSI_PARAM2_CCK_HIPWR) 2706 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2707 } 2708 } 2709 2710 void 2711 urtwn_rf_init(struct urtwn_softc *sc) 2712 { 2713 const struct urtwn_rf_prog *prog; 2714 uint32_t reg, type; 2715 int i, j, idx, off; 2716 2717 /* Select RF programming based on board type. */ 2718 if (sc->chip & URTWN_CHIP_88E) 2719 prog = rtl8188eu_rf_prog; 2720 else if (!(sc->chip & URTWN_CHIP_92C)) { 2721 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2722 prog = rtl8188ce_rf_prog; 2723 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2724 prog = rtl8188ru_rf_prog; 2725 else 2726 prog = rtl8188cu_rf_prog; 2727 } else 2728 prog = rtl8192ce_rf_prog; 2729 2730 for (i = 0; i < sc->nrxchains; i++) { 2731 /* Save RF_ENV control type. */ 2732 idx = i / 2; 2733 off = (i % 2) * 16; 2734 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2735 type = (reg >> off) & 0x10; 2736 2737 /* Set RF_ENV enable. */ 2738 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2739 reg |= 0x100000; 2740 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2741 urtwn_ms_delay(sc); 2742 /* Set RF_ENV output high. */ 2743 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2744 reg |= 0x10; 2745 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2746 urtwn_ms_delay(sc); 2747 /* Set address and data lengths of RF registers. */ 2748 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2749 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2750 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2751 urtwn_ms_delay(sc); 2752 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2753 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2754 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2755 urtwn_ms_delay(sc); 2756 2757 /* Write RF initialization values for this chain. */ 2758 for (j = 0; j < prog[i].count; j++) { 2759 if (prog[i].regs[j] >= 0xf9 && 2760 prog[i].regs[j] <= 0xfe) { 2761 /* 2762 * These are fake RF registers offsets that 2763 * indicate a delay is required. 2764 */ 2765 usb_pause_mtx(&sc->sc_lock, hz / 20); 2766 continue; 2767 } 2768 urtwn_rf_write(sc, i, prog[i].regs[j], 2769 prog[i].vals[j]); 2770 urtwn_ms_delay(sc); 2771 } 2772 2773 /* Restore RF_ENV control type. */ 2774 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2775 reg &= ~(0x10 << off) | (type << off); 2776 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2777 2778 /* Cache RF register CHNLBW. */ 2779 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2780 } 2781 2782 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2783 URTWN_CHIP_UMC_A_CUT) { 2784 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2785 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2786 } 2787 } 2788 2789 static void 2790 urtwn_cam_init(struct urtwn_softc *sc) 2791 { 2792 /* Invalidate all CAM entries. */ 2793 urtwn_write_4(sc, R92C_CAMCMD, 2794 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2795 } 2796 2797 static void 2798 urtwn_pa_bias_init(struct urtwn_softc *sc) 2799 { 2800 uint8_t reg; 2801 int i; 2802 2803 for (i = 0; i < sc->nrxchains; i++) { 2804 if (sc->pa_setting & (1 << i)) 2805 continue; 2806 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2807 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2808 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2809 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2810 } 2811 if (!(sc->pa_setting & 0x10)) { 2812 reg = urtwn_read_1(sc, 0x16); 2813 reg = (reg & ~0xf0) | 0x90; 2814 urtwn_write_1(sc, 0x16, reg); 2815 } 2816 } 2817 2818 static void 2819 urtwn_rxfilter_init(struct urtwn_softc *sc) 2820 { 2821 /* Initialize Rx filter. */ 2822 /* TODO: use better filter for monitor mode. */ 2823 urtwn_write_4(sc, R92C_RCR, 2824 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2825 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2826 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2827 /* Accept all multicast frames. */ 2828 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2829 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2830 /* Accept all management frames. */ 2831 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2832 /* Reject all control frames. */ 2833 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2834 /* Accept all data frames. */ 2835 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2836 } 2837 2838 static void 2839 urtwn_edca_init(struct urtwn_softc *sc) 2840 { 2841 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2842 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2843 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2844 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2845 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2846 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2847 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2848 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2849 } 2850 2851 void 2852 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 2853 uint16_t power[URTWN_RIDX_COUNT]) 2854 { 2855 uint32_t reg; 2856 2857 /* Write per-CCK rate Tx power. */ 2858 if (chain == 0) { 2859 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2860 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2861 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2862 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2863 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2864 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2865 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2866 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2867 } else { 2868 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2869 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2870 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2871 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2872 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2873 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2874 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2875 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2876 } 2877 /* Write per-OFDM rate Tx power. */ 2878 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2879 SM(R92C_TXAGC_RATE06, power[ 4]) | 2880 SM(R92C_TXAGC_RATE09, power[ 5]) | 2881 SM(R92C_TXAGC_RATE12, power[ 6]) | 2882 SM(R92C_TXAGC_RATE18, power[ 7])); 2883 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2884 SM(R92C_TXAGC_RATE24, power[ 8]) | 2885 SM(R92C_TXAGC_RATE36, power[ 9]) | 2886 SM(R92C_TXAGC_RATE48, power[10]) | 2887 SM(R92C_TXAGC_RATE54, power[11])); 2888 /* Write per-MCS Tx power. */ 2889 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2890 SM(R92C_TXAGC_MCS00, power[12]) | 2891 SM(R92C_TXAGC_MCS01, power[13]) | 2892 SM(R92C_TXAGC_MCS02, power[14]) | 2893 SM(R92C_TXAGC_MCS03, power[15])); 2894 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2895 SM(R92C_TXAGC_MCS04, power[16]) | 2896 SM(R92C_TXAGC_MCS05, power[17]) | 2897 SM(R92C_TXAGC_MCS06, power[18]) | 2898 SM(R92C_TXAGC_MCS07, power[19])); 2899 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2900 SM(R92C_TXAGC_MCS08, power[20]) | 2901 SM(R92C_TXAGC_MCS09, power[21]) | 2902 SM(R92C_TXAGC_MCS10, power[22]) | 2903 SM(R92C_TXAGC_MCS11, power[23])); 2904 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2905 SM(R92C_TXAGC_MCS12, power[24]) | 2906 SM(R92C_TXAGC_MCS13, power[25]) | 2907 SM(R92C_TXAGC_MCS14, power[26]) | 2908 SM(R92C_TXAGC_MCS15, power[27])); 2909 } 2910 2911 void 2912 urtwn_get_txpower(struct urtwn_softc *sc, int chain, 2913 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2914 uint16_t power[URTWN_RIDX_COUNT]) 2915 { 2916 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2917 struct r92c_rom *rom = &sc->rom; 2918 uint16_t cckpow, ofdmpow, htpow, diff, max; 2919 const struct urtwn_txpwr *base; 2920 int ridx, chan, group; 2921 2922 /* Determine channel group. */ 2923 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2924 if (chan <= 3) 2925 group = 0; 2926 else if (chan <= 9) 2927 group = 1; 2928 else 2929 group = 2; 2930 2931 /* Get original Tx power based on board type and RF chain. */ 2932 if (!(sc->chip & URTWN_CHIP_92C)) { 2933 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2934 base = &rtl8188ru_txagc[chain]; 2935 else 2936 base = &rtl8192cu_txagc[chain]; 2937 } else 2938 base = &rtl8192cu_txagc[chain]; 2939 2940 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2941 if (sc->regulatory == 0) { 2942 for (ridx = 0; ridx <= 3; ridx++) 2943 power[ridx] = base->pwr[0][ridx]; 2944 } 2945 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 2946 if (sc->regulatory == 3) { 2947 power[ridx] = base->pwr[0][ridx]; 2948 /* Apply vendor limits. */ 2949 if (extc != NULL) 2950 max = rom->ht40_max_pwr[group]; 2951 else 2952 max = rom->ht20_max_pwr[group]; 2953 max = (max >> (chain * 4)) & 0xf; 2954 if (power[ridx] > max) 2955 power[ridx] = max; 2956 } else if (sc->regulatory == 1) { 2957 if (extc == NULL) 2958 power[ridx] = base->pwr[group][ridx]; 2959 } else if (sc->regulatory != 2) 2960 power[ridx] = base->pwr[0][ridx]; 2961 } 2962 2963 /* Compute per-CCK rate Tx power. */ 2964 cckpow = rom->cck_tx_pwr[chain][group]; 2965 for (ridx = 0; ridx <= 3; ridx++) { 2966 power[ridx] += cckpow; 2967 if (power[ridx] > R92C_MAX_TX_PWR) 2968 power[ridx] = R92C_MAX_TX_PWR; 2969 } 2970 2971 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2972 if (sc->ntxchains > 1) { 2973 /* Apply reduction for 2 spatial streams. */ 2974 diff = rom->ht40_2s_tx_pwr_diff[group]; 2975 diff = (diff >> (chain * 4)) & 0xf; 2976 htpow = (htpow > diff) ? htpow - diff : 0; 2977 } 2978 2979 /* Compute per-OFDM rate Tx power. */ 2980 diff = rom->ofdm_tx_pwr_diff[group]; 2981 diff = (diff >> (chain * 4)) & 0xf; 2982 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2983 for (ridx = 4; ridx <= 11; ridx++) { 2984 power[ridx] += ofdmpow; 2985 if (power[ridx] > R92C_MAX_TX_PWR) 2986 power[ridx] = R92C_MAX_TX_PWR; 2987 } 2988 2989 /* Compute per-MCS Tx power. */ 2990 if (extc == NULL) { 2991 diff = rom->ht20_tx_pwr_diff[group]; 2992 diff = (diff >> (chain * 4)) & 0xf; 2993 htpow += diff; /* HT40->HT20 correction. */ 2994 } 2995 for (ridx = 12; ridx <= 27; ridx++) { 2996 power[ridx] += htpow; 2997 if (power[ridx] > R92C_MAX_TX_PWR) 2998 power[ridx] = R92C_MAX_TX_PWR; 2999 } 3000 #ifdef URTWN_DEBUG 3001 if (urtwn_debug >= 4) { 3002 /* Dump per-rate Tx power values. */ 3003 printf("Tx power for chain %d:\n", chain); 3004 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 3005 printf("Rate %d = %u\n", ridx, power[ridx]); 3006 } 3007 #endif 3008 } 3009 3010 void 3011 urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3012 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3013 uint16_t power[URTWN_RIDX_COUNT]) 3014 { 3015 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3016 uint16_t cckpow, ofdmpow, bw20pow, htpow; 3017 const struct urtwn_r88e_txpwr *base; 3018 int ridx, chan, group; 3019 3020 /* Determine channel group. */ 3021 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3022 if (chan <= 2) 3023 group = 0; 3024 else if (chan <= 5) 3025 group = 1; 3026 else if (chan <= 8) 3027 group = 2; 3028 else if (chan <= 11) 3029 group = 3; 3030 else if (chan <= 13) 3031 group = 4; 3032 else 3033 group = 5; 3034 3035 /* Get original Tx power based on board type and RF chain. */ 3036 base = &rtl8188eu_txagc[chain]; 3037 3038 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3039 if (sc->regulatory == 0) { 3040 for (ridx = 0; ridx <= 3; ridx++) 3041 power[ridx] = base->pwr[0][ridx]; 3042 } 3043 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3044 if (sc->regulatory == 3) 3045 power[ridx] = base->pwr[0][ridx]; 3046 else if (sc->regulatory == 1) { 3047 if (extc == NULL) 3048 power[ridx] = base->pwr[group][ridx]; 3049 } else if (sc->regulatory != 2) 3050 power[ridx] = base->pwr[0][ridx]; 3051 } 3052 3053 /* Compute per-CCK rate Tx power. */ 3054 cckpow = sc->cck_tx_pwr[group]; 3055 for (ridx = 0; ridx <= 3; ridx++) { 3056 power[ridx] += cckpow; 3057 if (power[ridx] > R92C_MAX_TX_PWR) 3058 power[ridx] = R92C_MAX_TX_PWR; 3059 } 3060 3061 htpow = sc->ht40_tx_pwr[group]; 3062 3063 /* Compute per-OFDM rate Tx power. */ 3064 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3065 for (ridx = 4; ridx <= 11; ridx++) { 3066 power[ridx] += ofdmpow; 3067 if (power[ridx] > R92C_MAX_TX_PWR) 3068 power[ridx] = R92C_MAX_TX_PWR; 3069 } 3070 3071 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3072 for (ridx = 12; ridx <= 27; ridx++) { 3073 power[ridx] += bw20pow; 3074 if (power[ridx] > R92C_MAX_TX_PWR) 3075 power[ridx] = R92C_MAX_TX_PWR; 3076 } 3077 } 3078 3079 void 3080 urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3081 struct ieee80211_channel *extc) 3082 { 3083 uint16_t power[URTWN_RIDX_COUNT]; 3084 int i; 3085 3086 for (i = 0; i < sc->ntxchains; i++) { 3087 /* Compute per-rate Tx power values. */ 3088 if (sc->chip & URTWN_CHIP_88E) 3089 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3090 else 3091 urtwn_get_txpower(sc, i, c, extc, power); 3092 /* Write per-rate Tx power values to hardware. */ 3093 urtwn_write_txpower(sc, i, power); 3094 } 3095 } 3096 3097 static void 3098 urtwn_scan_start(struct ieee80211com *ic) 3099 { 3100 /* XXX do nothing? */ 3101 } 3102 3103 static void 3104 urtwn_scan_end(struct ieee80211com *ic) 3105 { 3106 /* XXX do nothing? */ 3107 } 3108 3109 static void 3110 urtwn_set_channel(struct ieee80211com *ic) 3111 { 3112 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 3113 3114 URTWN_LOCK(sc); 3115 urtwn_set_chan(sc, ic->ic_curchan, NULL); 3116 URTWN_UNLOCK(sc); 3117 } 3118 3119 static void 3120 urtwn_update_mcast(struct ifnet *ifp) 3121 { 3122 /* XXX do nothing? */ 3123 } 3124 3125 static void 3126 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3127 struct ieee80211_channel *extc) 3128 { 3129 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3130 uint32_t reg; 3131 u_int chan; 3132 int i; 3133 3134 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3135 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3136 device_printf(sc->sc_dev, 3137 "%s: invalid channel %x\n", __func__, chan); 3138 return; 3139 } 3140 3141 /* Set Tx power for this new channel. */ 3142 urtwn_set_txpower(sc, c, extc); 3143 3144 for (i = 0; i < sc->nrxchains; i++) { 3145 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3146 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3147 } 3148 #ifndef IEEE80211_NO_HT 3149 if (extc != NULL) { 3150 /* Is secondary channel below or above primary? */ 3151 int prichlo = c->ic_freq < extc->ic_freq; 3152 3153 urtwn_write_1(sc, R92C_BWOPMODE, 3154 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3155 3156 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3157 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3158 urtwn_write_1(sc, R92C_RRSR + 2, reg); 3159 3160 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3161 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3162 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3163 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3164 3165 /* Set CCK side band. */ 3166 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3167 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3168 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3169 3170 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3171 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3172 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3173 3174 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3175 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3176 ~R92C_FPGA0_ANAPARAM2_CBW20); 3177 3178 reg = urtwn_bb_read(sc, 0x818); 3179 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3180 urtwn_bb_write(sc, 0x818, reg); 3181 3182 /* Select 40MHz bandwidth. */ 3183 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3184 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3185 } else 3186 #endif 3187 { 3188 urtwn_write_1(sc, R92C_BWOPMODE, 3189 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3190 3191 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3192 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3193 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3194 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3195 3196 if (!(sc->chip & URTWN_CHIP_88E)) { 3197 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3198 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3199 R92C_FPGA0_ANAPARAM2_CBW20); 3200 } 3201 3202 /* Select 20MHz bandwidth. */ 3203 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3204 (sc->rf_chnlbw[0] & ~0xfff) | chan | 3205 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3206 R92C_RF_CHNLBW_BW20)); 3207 } 3208 } 3209 3210 static void 3211 urtwn_iq_calib(struct urtwn_softc *sc) 3212 { 3213 /* TODO */ 3214 } 3215 3216 static void 3217 urtwn_lc_calib(struct urtwn_softc *sc) 3218 { 3219 uint32_t rf_ac[2]; 3220 uint8_t txmode; 3221 int i; 3222 3223 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3224 if ((txmode & 0x70) != 0) { 3225 /* Disable all continuous Tx. */ 3226 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3227 3228 /* Set RF mode to standby mode. */ 3229 for (i = 0; i < sc->nrxchains; i++) { 3230 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3231 urtwn_rf_write(sc, i, R92C_RF_AC, 3232 RW(rf_ac[i], R92C_RF_AC_MODE, 3233 R92C_RF_AC_MODE_STANDBY)); 3234 } 3235 } else { 3236 /* Block all Tx queues. */ 3237 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3238 } 3239 /* Start calibration. */ 3240 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3241 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3242 3243 /* Give calibration the time to complete. */ 3244 usb_pause_mtx(&sc->sc_lock, hz / 10); /* 100ms */ 3245 3246 /* Restore configuration. */ 3247 if ((txmode & 0x70) != 0) { 3248 /* Restore Tx mode. */ 3249 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3250 /* Restore RF mode. */ 3251 for (i = 0; i < sc->nrxchains; i++) 3252 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3253 } else { 3254 /* Unblock all Tx queues. */ 3255 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3256 } 3257 } 3258 3259 static void 3260 urtwn_init_locked(void *arg) 3261 { 3262 struct urtwn_softc *sc = arg; 3263 struct ifnet *ifp = sc->sc_ifp; 3264 uint32_t reg; 3265 int error; 3266 3267 URTWN_ASSERT_LOCKED(sc); 3268 3269 if (ifp->if_flags & IFF_RUNNING) 3270 urtwn_stop_locked(ifp); 3271 3272 /* Init firmware commands ring. */ 3273 sc->fwcur = 0; 3274 3275 /* Allocate Tx/Rx buffers. */ 3276 error = urtwn_alloc_rx_list(sc); 3277 if (error != 0) 3278 goto fail; 3279 3280 error = urtwn_alloc_tx_list(sc); 3281 if (error != 0) 3282 goto fail; 3283 3284 /* Power on adapter. */ 3285 error = urtwn_power_on(sc); 3286 if (error != 0) 3287 goto fail; 3288 3289 /* Initialize DMA. */ 3290 error = urtwn_dma_init(sc); 3291 if (error != 0) 3292 goto fail; 3293 3294 /* Set info size in Rx descriptors (in 64-bit words). */ 3295 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3296 3297 /* Init interrupts. */ 3298 if (sc->chip & URTWN_CHIP_88E) { 3299 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3300 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3301 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3302 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3303 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3304 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3305 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3306 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3307 } else { 3308 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3309 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3310 } 3311 3312 /* Set MAC address. */ 3313 urtwn_write_region_1(sc, R92C_MACID, IF_LLADDR(ifp), 3314 IEEE80211_ADDR_LEN); 3315 3316 /* Set initial network type. */ 3317 reg = urtwn_read_4(sc, R92C_CR); 3318 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3319 urtwn_write_4(sc, R92C_CR, reg); 3320 3321 urtwn_rxfilter_init(sc); 3322 3323 reg = urtwn_read_4(sc, R92C_RRSR); 3324 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3325 urtwn_write_4(sc, R92C_RRSR, reg); 3326 3327 /* Set short/long retry limits. */ 3328 urtwn_write_2(sc, R92C_RL, 3329 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3330 3331 /* Initialize EDCA parameters. */ 3332 urtwn_edca_init(sc); 3333 3334 /* Setup rate fallback. */ 3335 if (!(sc->chip & URTWN_CHIP_88E)) { 3336 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3337 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3338 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3339 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3340 } 3341 3342 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3343 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3344 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3345 /* Set ACK timeout. */ 3346 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3347 3348 /* Setup USB aggregation. */ 3349 reg = urtwn_read_4(sc, R92C_TDECTRL); 3350 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3351 urtwn_write_4(sc, R92C_TDECTRL, reg); 3352 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3353 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3354 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3355 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3356 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3357 R92C_USB_SPECIAL_OPTION_AGG_EN); 3358 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3359 if (sc->chip & URTWN_CHIP_88E) 3360 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3361 else 3362 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3363 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3364 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3365 3366 /* Initialize beacon parameters. */ 3367 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3368 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3369 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3370 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3371 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3372 3373 if (!(sc->chip & URTWN_CHIP_88E)) { 3374 /* Setup AMPDU aggregation. */ 3375 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3376 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3377 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3378 3379 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3380 } 3381 3382 /* Load 8051 microcode. */ 3383 error = urtwn_load_firmware(sc); 3384 if (error != 0) 3385 goto fail; 3386 3387 /* Initialize MAC/BB/RF blocks. */ 3388 urtwn_mac_init(sc); 3389 urtwn_bb_init(sc); 3390 urtwn_rf_init(sc); 3391 3392 if (sc->chip & URTWN_CHIP_88E) { 3393 urtwn_write_2(sc, R92C_CR, 3394 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3395 R92C_CR_MACRXEN); 3396 } 3397 3398 /* Turn CCK and OFDM blocks on. */ 3399 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3400 reg |= R92C_RFMOD_CCK_EN; 3401 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3402 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3403 reg |= R92C_RFMOD_OFDM_EN; 3404 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3405 3406 /* Clear per-station keys table. */ 3407 urtwn_cam_init(sc); 3408 3409 /* Enable hardware sequence numbering. */ 3410 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3411 3412 /* Perform LO and IQ calibrations. */ 3413 urtwn_iq_calib(sc); 3414 /* Perform LC calibration. */ 3415 urtwn_lc_calib(sc); 3416 3417 /* Fix USB interference issue. */ 3418 if (!(sc->chip & URTWN_CHIP_88E)) { 3419 urtwn_write_1(sc, 0xfe40, 0xe0); 3420 urtwn_write_1(sc, 0xfe41, 0x8d); 3421 urtwn_write_1(sc, 0xfe42, 0x80); 3422 3423 urtwn_pa_bias_init(sc); 3424 } 3425 3426 /* Initialize GPIO setting. */ 3427 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3428 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3429 3430 /* Fix for lower temperature. */ 3431 if (!(sc->chip & URTWN_CHIP_88E)) 3432 urtwn_write_1(sc, 0x15, 0xe9); 3433 3434 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3435 3436 ifq_clr_oactive(&ifp->if_snd); 3437 ifp->if_flags |= IFF_RUNNING; 3438 3439 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3440 fail: 3441 return; 3442 } 3443 3444 static void 3445 urtwn_init(void *arg) 3446 { 3447 struct urtwn_softc *sc = arg; 3448 3449 URTWN_LOCK(sc); 3450 urtwn_init_locked(arg); 3451 URTWN_UNLOCK(sc); 3452 } 3453 3454 static void 3455 urtwn_stop_locked(struct ifnet *ifp) 3456 { 3457 struct urtwn_softc *sc = ifp->if_softc; 3458 3459 URTWN_ASSERT_LOCKED(sc); 3460 3461 ifp->if_flags &= ~IFF_RUNNING; 3462 ifq_clr_oactive(&ifp->if_snd); 3463 3464 callout_stop(&sc->sc_watchdog_ch); 3465 urtwn_abort_xfers(sc); 3466 } 3467 3468 static void 3469 urtwn_stop(struct ifnet *ifp) 3470 { 3471 struct urtwn_softc *sc = ifp->if_softc; 3472 3473 URTWN_LOCK(sc); 3474 urtwn_stop_locked(ifp); 3475 URTWN_UNLOCK(sc); 3476 } 3477 3478 static void 3479 urtwn_abort_xfers(struct urtwn_softc *sc) 3480 { 3481 int i; 3482 3483 URTWN_ASSERT_LOCKED(sc); 3484 3485 /* abort any pending transfers */ 3486 for (i = 0; i < URTWN_N_TRANSFER; i++) 3487 usbd_transfer_stop(sc->sc_xfer[i]); 3488 } 3489 3490 static int 3491 urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3492 const struct ieee80211_bpf_params *params) 3493 { 3494 struct ieee80211com *ic = ni->ni_ic; 3495 struct ifnet *ifp = ic->ic_ifp; 3496 struct urtwn_softc *sc = ifp->if_softc; 3497 struct urtwn_data *bf; 3498 3499 /* prevent management frames from being sent if we're not ready */ 3500 if (!(ifp->if_flags & IFF_RUNNING)) { 3501 m_freem(m); 3502 ieee80211_free_node(ni); 3503 return (ENETDOWN); 3504 } 3505 URTWN_LOCK(sc); 3506 bf = urtwn_getbuf(sc); 3507 if (bf == NULL) { 3508 ieee80211_free_node(ni); 3509 m_freem(m); 3510 URTWN_UNLOCK(sc); 3511 return (ENOBUFS); 3512 } 3513 3514 ifp->if_opackets++; 3515 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3516 ieee80211_free_node(ni); 3517 ifp->if_oerrors++; 3518 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3519 URTWN_UNLOCK(sc); 3520 return (EIO); 3521 } 3522 URTWN_UNLOCK(sc); 3523 3524 sc->sc_txtimer = 5; 3525 return (0); 3526 } 3527 3528 static void 3529 urtwn_ms_delay(struct urtwn_softc *sc) 3530 { 3531 usb_pause_ls(&sc->sc_lock, &wlan_global_serializer, hz / 100); 3532 } 3533 3534 static device_method_t urtwn_methods[] = { 3535 /* Device interface */ 3536 DEVMETHOD(device_probe, urtwn_match), 3537 DEVMETHOD(device_attach, urtwn_attach), 3538 DEVMETHOD(device_detach, urtwn_detach), 3539 3540 DEVMETHOD_END 3541 }; 3542 3543 static driver_t urtwn_driver = { 3544 "urtwn", 3545 urtwn_methods, 3546 sizeof(struct urtwn_softc) 3547 }; 3548 3549 static devclass_t urtwn_devclass; 3550 3551 DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3552 MODULE_DEPEND(urtwn, usb, 1, 1, 1); 3553 MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3554 MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3555 MODULE_VERSION(urtwn, 1); 3556