1 /* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2015 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __FBSDID("$FreeBSD$"); 23 24 /* 25 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 26 */ 27 28 #include "opt_wlan.h" 29 #include "opt_urtwn.h" 30 31 #include <sys/param.h> 32 #include <sys/sockio.h> 33 #include <sys/sysctl.h> 34 #include <sys/lock.h> 35 #include <sys/condvar.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/linker.h> 45 #include <sys/firmware.h> 46 #if defined(__DragonFly__) 47 #else 48 #include <sys/kdb.h> 49 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #endif 53 54 #include <sys/rman.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_arp.h> 60 #include <net/ethernet.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 #include <net/if_types.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/in_var.h> 68 #include <netinet/if_ether.h> 69 #include <netinet/ip.h> 70 71 #include <netproto/802_11/ieee80211_var.h> 72 #include <netproto/802_11/ieee80211_regdomain.h> 73 #include <netproto/802_11/ieee80211_radiotap.h> 74 #include <netproto/802_11/ieee80211_ratectl.h> 75 #ifdef IEEE80211_SUPPORT_SUPERG 76 #include <netproto/802_11/ieee80211_superg.h> 77 #endif 78 79 #include <bus/u4b/usb.h> 80 #include <bus/u4b/usbdi.h> 81 #include <bus/u4b/usb_device.h> 82 #include "usbdevs.h" 83 84 #include <bus/u4b/usb_debug.h> 85 86 #include <bus/u4b/wlan/if_urtwnreg.h> 87 #include <bus/u4b/wlan/if_urtwnvar.h> 88 89 #ifdef USB_DEBUG 90 enum { 91 URTWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 92 URTWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 93 URTWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 94 URTWN_DEBUG_RA = 0x00000008, /* f/w rate adaptation setup */ 95 URTWN_DEBUG_USB = 0x00000010, /* usb requests */ 96 URTWN_DEBUG_FIRMWARE = 0x00000020, /* firmware(9) loading debug */ 97 URTWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 98 URTWN_DEBUG_INTR = 0x00000080, /* ISR */ 99 URTWN_DEBUG_TEMP = 0x00000100, /* temperature calibration */ 100 URTWN_DEBUG_ROM = 0x00000200, /* various ROM info */ 101 URTWN_DEBUG_KEY = 0x00000400, /* crypto keys management */ 102 URTWN_DEBUG_TXPWR = 0x00000800, /* dump Tx power values */ 103 URTWN_DEBUG_RSSI = 0x00001000, /* dump RSSI lookups */ 104 URTWN_DEBUG_ANY = 0xffffffff 105 }; 106 107 #define URTWN_DPRINTF(_sc, _m, ...) do { \ 108 if ((_sc)->sc_debug & (_m)) \ 109 device_printf((_sc)->sc_dev, __VA_ARGS__); \ 110 } while(0) 111 112 #else 113 #define URTWN_DPRINTF(_sc, _m, ...) do { (void) sc; } while (0) 114 #endif 115 116 #define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 117 118 static int urtwn_enable_11n = 1; 119 TUNABLE_INT("hw.usb.urtwn.enable_11n", &urtwn_enable_11n); 120 121 /* various supported device vendors/products */ 122 static const STRUCT_USB_HOST_ID urtwn_devs[] = { 123 #define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 124 #define URTWN_RTL8188E_DEV(v,p) \ 125 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 126 #define URTWN_RTL8188E 1 127 URTWN_DEV(ABOCOM, RTL8188CU_1), 128 URTWN_DEV(ABOCOM, RTL8188CU_2), 129 URTWN_DEV(ABOCOM, RTL8192CU), 130 URTWN_DEV(ASUS, RTL8192CU), 131 URTWN_DEV(ASUS, USBN10NANO), 132 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 133 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 134 URTWN_DEV(AZUREWAVE, RTL8188CU), 135 URTWN_DEV(BELKIN, F7D2102), 136 URTWN_DEV(BELKIN, RTL8188CU), 137 URTWN_DEV(BELKIN, RTL8192CU), 138 URTWN_DEV(CHICONY, RTL8188CUS_1), 139 URTWN_DEV(CHICONY, RTL8188CUS_2), 140 URTWN_DEV(CHICONY, RTL8188CUS_3), 141 URTWN_DEV(CHICONY, RTL8188CUS_4), 142 URTWN_DEV(CHICONY, RTL8188CUS_5), 143 URTWN_DEV(COREGA, RTL8192CU), 144 URTWN_DEV(DLINK, RTL8188CU), 145 URTWN_DEV(DLINK, RTL8192CU_1), 146 URTWN_DEV(DLINK, RTL8192CU_2), 147 URTWN_DEV(DLINK, RTL8192CU_3), 148 URTWN_DEV(DLINK, DWA131B), 149 URTWN_DEV(EDIMAX, EW7811UN), 150 URTWN_DEV(EDIMAX, RTL8192CU), 151 URTWN_DEV(FEIXUN, RTL8188CU), 152 URTWN_DEV(FEIXUN, RTL8192CU), 153 URTWN_DEV(GUILLEMOT, HWNUP150), 154 URTWN_DEV(HAWKING, RTL8192CU), 155 URTWN_DEV(HP3, RTL8188CU), 156 URTWN_DEV(NETGEAR, WNA1000M), 157 URTWN_DEV(NETGEAR, RTL8192CU), 158 URTWN_DEV(NETGEAR4, RTL8188CU), 159 URTWN_DEV(NOVATECH, RTL8188CU), 160 URTWN_DEV(PLANEX2, RTL8188CU_1), 161 URTWN_DEV(PLANEX2, RTL8188CU_2), 162 URTWN_DEV(PLANEX2, RTL8188CU_3), 163 URTWN_DEV(PLANEX2, RTL8188CU_4), 164 URTWN_DEV(PLANEX2, RTL8188CUS), 165 URTWN_DEV(PLANEX2, RTL8192CU), 166 URTWN_DEV(REALTEK, RTL8188CE_0), 167 URTWN_DEV(REALTEK, RTL8188CE_1), 168 URTWN_DEV(REALTEK, RTL8188CTV), 169 URTWN_DEV(REALTEK, RTL8188CU_0), 170 URTWN_DEV(REALTEK, RTL8188CU_1), 171 URTWN_DEV(REALTEK, RTL8188CU_2), 172 URTWN_DEV(REALTEK, RTL8188CU_3), 173 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 174 URTWN_DEV(REALTEK, RTL8188CUS), 175 URTWN_DEV(REALTEK, RTL8188RU_1), 176 URTWN_DEV(REALTEK, RTL8188RU_2), 177 URTWN_DEV(REALTEK, RTL8188RU_3), 178 URTWN_DEV(REALTEK, RTL8191CU), 179 URTWN_DEV(REALTEK, RTL8192CE), 180 URTWN_DEV(REALTEK, RTL8192CU), 181 URTWN_DEV(SITECOMEU, RTL8188CU_1), 182 URTWN_DEV(SITECOMEU, RTL8188CU_2), 183 URTWN_DEV(SITECOMEU, RTL8192CU), 184 URTWN_DEV(TRENDNET, RTL8188CU), 185 URTWN_DEV(TRENDNET, RTL8192CU), 186 URTWN_DEV(ZYXEL, RTL8192CU), 187 /* URTWN_RTL8188E */ 188 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 189 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 190 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 191 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 192 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 193 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 194 #undef URTWN_RTL8188E_DEV 195 #undef URTWN_DEV 196 }; 197 198 static device_probe_t urtwn_match; 199 static device_attach_t urtwn_attach; 200 static device_detach_t urtwn_detach; 201 202 static usb_callback_t urtwn_bulk_tx_callback; 203 static usb_callback_t urtwn_bulk_rx_callback; 204 205 static void urtwn_sysctlattach(struct urtwn_softc *); 206 static void urtwn_drain_mbufq(struct urtwn_softc *); 207 static usb_error_t urtwn_do_request(struct urtwn_softc *, 208 struct usb_device_request *, void *); 209 static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 210 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 211 const uint8_t [IEEE80211_ADDR_LEN], 212 const uint8_t [IEEE80211_ADDR_LEN]); 213 static void urtwn_vap_delete(struct ieee80211vap *); 214 static struct mbuf * urtwn_rx_copy_to_mbuf(struct urtwn_softc *, 215 struct r92c_rx_stat *, int); 216 static struct mbuf * urtwn_report_intr(struct usb_xfer *, 217 struct urtwn_data *); 218 static struct mbuf * urtwn_rxeof(struct urtwn_softc *, uint8_t *, int); 219 static void urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *, 220 void *); 221 static struct ieee80211_node *urtwn_rx_frame(struct urtwn_softc *, 222 struct mbuf *, int8_t *); 223 static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 224 int); 225 static int urtwn_alloc_list(struct urtwn_softc *, 226 struct urtwn_data[], int, int); 227 static int urtwn_alloc_rx_list(struct urtwn_softc *); 228 static int urtwn_alloc_tx_list(struct urtwn_softc *); 229 static void urtwn_free_list(struct urtwn_softc *, 230 struct urtwn_data data[], int); 231 static void urtwn_free_rx_list(struct urtwn_softc *); 232 static void urtwn_free_tx_list(struct urtwn_softc *); 233 static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 234 static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 235 static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 236 uint8_t *, int); 237 static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 238 static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 239 static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 240 static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 241 uint8_t *, int); 242 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 243 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 244 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 245 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 246 const void *, int); 247 static void urtwn_cmdq_cb(void *, int); 248 static int urtwn_cmd_sleepable(struct urtwn_softc *, const void *, 249 size_t, CMD_FUNC_PROTO); 250 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 251 uint8_t, uint32_t); 252 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 253 uint8_t, uint32_t); 254 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 255 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 256 uint32_t); 257 static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 258 static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 259 uint8_t, uint8_t); 260 #ifdef USB_DEBUG 261 static void urtwn_dump_rom_contents(struct urtwn_softc *, 262 uint8_t *, uint16_t); 263 #endif 264 static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 265 uint16_t); 266 static int urtwn_efuse_switch_power(struct urtwn_softc *); 267 static int urtwn_read_chipid(struct urtwn_softc *); 268 static int urtwn_read_rom(struct urtwn_softc *); 269 static int urtwn_r88e_read_rom(struct urtwn_softc *); 270 static int urtwn_ra_init(struct urtwn_softc *); 271 static void urtwn_init_beacon(struct urtwn_softc *, 272 struct urtwn_vap *); 273 static int urtwn_setup_beacon(struct urtwn_softc *, 274 struct ieee80211_node *); 275 static void urtwn_update_beacon(struct ieee80211vap *, int); 276 static int urtwn_tx_beacon(struct urtwn_softc *sc, 277 struct urtwn_vap *); 278 static int urtwn_key_alloc(struct ieee80211vap *, 279 struct ieee80211_key *, ieee80211_keyix *, 280 ieee80211_keyix *); 281 static void urtwn_key_set_cb(struct urtwn_softc *, 282 union sec_param *); 283 static void urtwn_key_del_cb(struct urtwn_softc *, 284 union sec_param *); 285 static int urtwn_key_set(struct ieee80211vap *, 286 const struct ieee80211_key *); 287 static int urtwn_key_delete(struct ieee80211vap *, 288 const struct ieee80211_key *); 289 static void urtwn_tsf_task_adhoc(void *, int); 290 static void urtwn_tsf_sync_enable(struct urtwn_softc *, 291 struct ieee80211vap *); 292 static void urtwn_get_tsf(struct urtwn_softc *, uint64_t *); 293 static void urtwn_set_led(struct urtwn_softc *, int, int); 294 static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 295 static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 296 struct mbuf *, int, 297 const struct ieee80211_rx_stats *, int, int); 298 static int urtwn_newstate(struct ieee80211vap *, 299 enum ieee80211_state, int); 300 static void urtwn_calib_to(void *); 301 static void urtwn_calib_cb(struct urtwn_softc *, 302 union sec_param *); 303 static void urtwn_watchdog(void *); 304 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 305 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 306 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 307 static int urtwn_tx_data(struct urtwn_softc *, 308 struct ieee80211_node *, struct mbuf *, 309 struct urtwn_data *); 310 static int urtwn_tx_raw(struct urtwn_softc *, 311 struct ieee80211_node *, struct mbuf *, 312 struct urtwn_data *, 313 const struct ieee80211_bpf_params *); 314 static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 315 uint8_t, struct urtwn_data *); 316 static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 317 static void urtwn_start(struct urtwn_softc *); 318 static void urtwn_parent(struct ieee80211com *); 319 static int urtwn_r92c_power_on(struct urtwn_softc *); 320 static int urtwn_r88e_power_on(struct urtwn_softc *); 321 static void urtwn_r92c_power_off(struct urtwn_softc *); 322 static void urtwn_r88e_power_off(struct urtwn_softc *); 323 static int urtwn_llt_init(struct urtwn_softc *); 324 #ifndef URTWN_WITHOUT_UCODE 325 static void urtwn_fw_reset(struct urtwn_softc *); 326 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 327 static int urtwn_fw_loadpage(struct urtwn_softc *, int, 328 const uint8_t *, int); 329 static int urtwn_load_firmware(struct urtwn_softc *); 330 #endif 331 static int urtwn_dma_init(struct urtwn_softc *); 332 static int urtwn_mac_init(struct urtwn_softc *); 333 static void urtwn_bb_init(struct urtwn_softc *); 334 static void urtwn_rf_init(struct urtwn_softc *); 335 static void urtwn_cam_init(struct urtwn_softc *); 336 static int urtwn_cam_write(struct urtwn_softc *, uint32_t, 337 uint32_t); 338 static void urtwn_pa_bias_init(struct urtwn_softc *); 339 static void urtwn_rxfilter_init(struct urtwn_softc *); 340 static void urtwn_edca_init(struct urtwn_softc *); 341 static void urtwn_write_txpower(struct urtwn_softc *, int, 342 uint16_t[]); 343 static void urtwn_get_txpower(struct urtwn_softc *, int, 344 struct ieee80211_channel *, 345 struct ieee80211_channel *, uint16_t[]); 346 static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 347 struct ieee80211_channel *, 348 struct ieee80211_channel *, uint16_t[]); 349 static void urtwn_set_txpower(struct urtwn_softc *, 350 struct ieee80211_channel *, 351 struct ieee80211_channel *); 352 static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 353 static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 354 static void urtwn_scan_start(struct ieee80211com *); 355 static void urtwn_scan_end(struct ieee80211com *); 356 static void urtwn_set_channel(struct ieee80211com *); 357 static int urtwn_wme_update(struct ieee80211com *); 358 static void urtwn_update_slot(struct ieee80211com *); 359 static void urtwn_update_slot_cb(struct urtwn_softc *, 360 union sec_param *); 361 static void urtwn_update_aifs(struct urtwn_softc *, uint8_t); 362 static uint8_t urtwn_get_multi_pos(const uint8_t[]); 363 static void urtwn_set_multi(struct urtwn_softc *); 364 static void urtwn_set_promisc(struct urtwn_softc *); 365 static void urtwn_update_promisc(struct ieee80211com *); 366 static void urtwn_update_mcast(struct ieee80211com *); 367 static struct ieee80211_node *urtwn_node_alloc(struct ieee80211vap *, 368 const uint8_t mac[IEEE80211_ADDR_LEN]); 369 static void urtwn_newassoc(struct ieee80211_node *, int); 370 static void urtwn_node_free(struct ieee80211_node *); 371 static void urtwn_set_chan(struct urtwn_softc *, 372 struct ieee80211_channel *, 373 struct ieee80211_channel *); 374 static void urtwn_iq_calib(struct urtwn_softc *); 375 static void urtwn_lc_calib(struct urtwn_softc *); 376 static void urtwn_temp_calib(struct urtwn_softc *); 377 static int urtwn_init(struct urtwn_softc *); 378 static void urtwn_stop(struct urtwn_softc *); 379 static void urtwn_abort_xfers(struct urtwn_softc *); 380 static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 381 const struct ieee80211_bpf_params *); 382 static void urtwn_ms_delay(struct urtwn_softc *); 383 384 /* Aliases. */ 385 #define urtwn_bb_write urtwn_write_4 386 #define urtwn_bb_read urtwn_read_4 387 388 static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 389 [URTWN_BULK_RX] = { 390 .type = UE_BULK, 391 .endpoint = UE_ADDR_ANY, 392 .direction = UE_DIR_IN, 393 .bufsize = URTWN_RXBUFSZ, 394 .flags = { 395 .pipe_bof = 1, 396 .short_xfer_ok = 1 397 }, 398 .callback = urtwn_bulk_rx_callback, 399 }, 400 [URTWN_BULK_TX_BE] = { 401 .type = UE_BULK, 402 .endpoint = 0x03, 403 .direction = UE_DIR_OUT, 404 .bufsize = URTWN_TXBUFSZ, 405 .flags = { 406 .ext_buffer = 1, 407 .pipe_bof = 1, 408 .force_short_xfer = 1 409 }, 410 .callback = urtwn_bulk_tx_callback, 411 .timeout = URTWN_TX_TIMEOUT, /* ms */ 412 }, 413 [URTWN_BULK_TX_BK] = { 414 .type = UE_BULK, 415 .endpoint = 0x03, 416 .direction = UE_DIR_OUT, 417 .bufsize = URTWN_TXBUFSZ, 418 .flags = { 419 .ext_buffer = 1, 420 .pipe_bof = 1, 421 .force_short_xfer = 1, 422 }, 423 .callback = urtwn_bulk_tx_callback, 424 .timeout = URTWN_TX_TIMEOUT, /* ms */ 425 }, 426 [URTWN_BULK_TX_VI] = { 427 .type = UE_BULK, 428 .endpoint = 0x02, 429 .direction = UE_DIR_OUT, 430 .bufsize = URTWN_TXBUFSZ, 431 .flags = { 432 .ext_buffer = 1, 433 .pipe_bof = 1, 434 .force_short_xfer = 1 435 }, 436 .callback = urtwn_bulk_tx_callback, 437 .timeout = URTWN_TX_TIMEOUT, /* ms */ 438 }, 439 [URTWN_BULK_TX_VO] = { 440 .type = UE_BULK, 441 .endpoint = 0x02, 442 .direction = UE_DIR_OUT, 443 .bufsize = URTWN_TXBUFSZ, 444 .flags = { 445 .ext_buffer = 1, 446 .pipe_bof = 1, 447 .force_short_xfer = 1 448 }, 449 .callback = urtwn_bulk_tx_callback, 450 .timeout = URTWN_TX_TIMEOUT, /* ms */ 451 }, 452 }; 453 454 static const struct wme_to_queue { 455 uint16_t reg; 456 uint8_t qid; 457 } wme2queue[WME_NUM_AC] = { 458 { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 459 { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 460 { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 461 { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 462 }; 463 464 static int 465 urtwn_match(device_t self) 466 { 467 struct usb_attach_arg *uaa = device_get_ivars(self); 468 469 if (uaa->usb_mode != USB_MODE_HOST) 470 return (ENXIO); 471 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 472 return (ENXIO); 473 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 474 return (ENXIO); 475 476 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 477 } 478 479 static void 480 urtwn_update_chw(struct ieee80211com *ic) 481 { 482 } 483 484 static int 485 urtwn_ampdu_enable(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 486 { 487 488 /* We're driving this ourselves (eventually); don't involve net80211 */ 489 return (0); 490 } 491 492 static int 493 urtwn_attach(device_t self) 494 { 495 struct usb_attach_arg *uaa = device_get_ivars(self); 496 struct urtwn_softc *sc = device_get_softc(self); 497 struct ieee80211com *ic = &sc->sc_ic; 498 uint8_t bands[IEEE80211_MODE_BYTES]; 499 int error; 500 501 device_set_usb_desc(self); 502 sc->sc_udev = uaa->device; 503 sc->sc_dev = self; 504 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 505 sc->chip |= URTWN_CHIP_88E; 506 507 #ifdef USB_DEBUG 508 int debug; 509 if (resource_int_value(device_get_name(sc->sc_dev), 510 device_get_unit(sc->sc_dev), "debug", &debug) == 0) 511 sc->sc_debug = debug; 512 #endif 513 514 #if defined(__DragonFly__) 515 lockinit(&sc->sc_mtx, device_get_nameunit(self), 0, 0); 516 #else 517 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 518 MTX_NETWORK_LOCK, MTX_DEF); 519 #endif 520 URTWN_CMDQ_LOCK_INIT(sc); 521 URTWN_NT_LOCK_INIT(sc); 522 #if defined(__DragonFly__) 523 callout_init(&sc->sc_calib_to); 524 callout_init(&sc->sc_watchdog_ch); 525 #else 526 callout_init(&sc->sc_calib_to, 0); 527 callout_init(&sc->sc_watchdog_ch, 0); 528 #endif 529 mbufq_init(&sc->sc_snd, ifqmaxlen); 530 531 sc->sc_iface_index = URTWN_IFACE_INDEX; 532 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 533 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 534 if (error) { 535 device_printf(self, "could not allocate USB transfers, " 536 "err=%s\n", usbd_errstr(error)); 537 goto detach; 538 } 539 540 URTWN_LOCK(sc); 541 542 error = urtwn_read_chipid(sc); 543 if (error) { 544 device_printf(sc->sc_dev, "unsupported test chip\n"); 545 URTWN_UNLOCK(sc); 546 goto detach; 547 } 548 549 /* Determine number of Tx/Rx chains. */ 550 if (sc->chip & URTWN_CHIP_92C) { 551 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 552 sc->nrxchains = 2; 553 } else { 554 sc->ntxchains = 1; 555 sc->nrxchains = 1; 556 } 557 558 if (sc->chip & URTWN_CHIP_88E) 559 error = urtwn_r88e_read_rom(sc); 560 else 561 error = urtwn_read_rom(sc); 562 if (error != 0) { 563 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 564 __func__, error); 565 URTWN_UNLOCK(sc); 566 goto detach; 567 } 568 569 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 570 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 571 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 572 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 573 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 574 "8188CUS", sc->ntxchains, sc->nrxchains); 575 576 URTWN_UNLOCK(sc); 577 578 ic->ic_softc = sc; 579 ic->ic_name = device_get_nameunit(self); 580 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 581 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 582 583 /* set device capabilities */ 584 ic->ic_caps = 585 IEEE80211_C_STA /* station mode */ 586 | IEEE80211_C_MONITOR /* monitor mode */ 587 | IEEE80211_C_IBSS /* adhoc mode */ 588 | IEEE80211_C_HOSTAP /* hostap mode */ 589 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 590 | IEEE80211_C_SHSLOT /* short slot time supported */ 591 #if 0 592 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 593 #endif 594 | IEEE80211_C_WPA /* 802.11i */ 595 | IEEE80211_C_WME /* 802.11e */ 596 | IEEE80211_C_SWAMSDUTX /* Do software A-MSDU TX */ 597 | IEEE80211_C_FF /* Atheros fast-frames */ 598 ; 599 600 ic->ic_cryptocaps = 601 IEEE80211_CRYPTO_WEP | 602 IEEE80211_CRYPTO_TKIP | 603 IEEE80211_CRYPTO_AES_CCM; 604 605 /* Assume they're all 11n capable for now */ 606 if (urtwn_enable_11n) { 607 device_printf(self, "enabling 11n\n"); 608 ic->ic_htcaps = IEEE80211_HTC_HT | 609 #if 0 610 IEEE80211_HTC_AMPDU | 611 #endif 612 IEEE80211_HTC_AMSDU | 613 IEEE80211_HTCAP_MAXAMSDU_3839 | 614 IEEE80211_HTCAP_SMPS_OFF; 615 /* no HT40 just yet */ 616 // ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40; 617 618 /* XXX TODO: verify chains versus streams for urtwn */ 619 ic->ic_txstream = sc->ntxchains; 620 ic->ic_rxstream = sc->nrxchains; 621 } 622 623 memset(bands, 0, sizeof(bands)); 624 setbit(bands, IEEE80211_MODE_11B); 625 setbit(bands, IEEE80211_MODE_11G); 626 if (urtwn_enable_11n) 627 setbit(bands, IEEE80211_MODE_11NG); 628 ieee80211_init_channels(ic, NULL, bands); 629 630 ieee80211_ifattach(ic); 631 ic->ic_raw_xmit = urtwn_raw_xmit; 632 ic->ic_scan_start = urtwn_scan_start; 633 ic->ic_scan_end = urtwn_scan_end; 634 ic->ic_set_channel = urtwn_set_channel; 635 ic->ic_transmit = urtwn_transmit; 636 ic->ic_parent = urtwn_parent; 637 ic->ic_vap_create = urtwn_vap_create; 638 ic->ic_vap_delete = urtwn_vap_delete; 639 ic->ic_wme.wme_update = urtwn_wme_update; 640 ic->ic_updateslot = urtwn_update_slot; 641 ic->ic_update_promisc = urtwn_update_promisc; 642 ic->ic_update_mcast = urtwn_update_mcast; 643 if (sc->chip & URTWN_CHIP_88E) { 644 ic->ic_node_alloc = urtwn_node_alloc; 645 ic->ic_newassoc = urtwn_newassoc; 646 sc->sc_node_free = ic->ic_node_free; 647 ic->ic_node_free = urtwn_node_free; 648 } 649 ic->ic_update_chw = urtwn_update_chw; 650 ic->ic_ampdu_enable = urtwn_ampdu_enable; 651 652 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 653 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 654 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 655 URTWN_RX_RADIOTAP_PRESENT); 656 657 TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc); 658 659 urtwn_sysctlattach(sc); 660 661 if (bootverbose) 662 ieee80211_announce(ic); 663 664 return (0); 665 666 detach: 667 urtwn_detach(self); 668 return (ENXIO); /* failure */ 669 } 670 671 static void 672 urtwn_sysctlattach(struct urtwn_softc *sc) 673 { 674 #ifdef USB_DEBUG 675 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 676 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 677 678 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 679 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 680 "control debugging printfs"); 681 #endif 682 } 683 684 static int 685 urtwn_detach(device_t self) 686 { 687 struct urtwn_softc *sc = device_get_softc(self); 688 struct ieee80211com *ic = &sc->sc_ic; 689 unsigned int x; 690 691 /* Prevent further ioctls. */ 692 URTWN_LOCK(sc); 693 sc->sc_flags |= URTWN_DETACHED; 694 URTWN_UNLOCK(sc); 695 696 urtwn_stop(sc); 697 698 callout_drain(&sc->sc_watchdog_ch); 699 callout_drain(&sc->sc_calib_to); 700 701 /* stop all USB transfers */ 702 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 703 704 /* Prevent further allocations from RX/TX data lists. */ 705 URTWN_LOCK(sc); 706 STAILQ_INIT(&sc->sc_tx_active); 707 STAILQ_INIT(&sc->sc_tx_inactive); 708 STAILQ_INIT(&sc->sc_tx_pending); 709 710 STAILQ_INIT(&sc->sc_rx_active); 711 STAILQ_INIT(&sc->sc_rx_inactive); 712 URTWN_UNLOCK(sc); 713 714 /* drain USB transfers */ 715 for (x = 0; x != URTWN_N_TRANSFER; x++) 716 usbd_transfer_drain(sc->sc_xfer[x]); 717 718 /* Free data buffers. */ 719 URTWN_LOCK(sc); 720 urtwn_free_tx_list(sc); 721 urtwn_free_rx_list(sc); 722 URTWN_UNLOCK(sc); 723 724 if (ic->ic_softc == sc) { 725 ieee80211_draintask(ic, &sc->cmdq_task); 726 ieee80211_ifdetach(ic); 727 } 728 729 URTWN_NT_LOCK_DESTROY(sc); 730 URTWN_CMDQ_LOCK_DESTROY(sc); 731 lockuninit(&sc->sc_mtx); 732 733 return (0); 734 } 735 736 static void 737 urtwn_drain_mbufq(struct urtwn_softc *sc) 738 { 739 struct mbuf *m; 740 struct ieee80211_node *ni; 741 URTWN_ASSERT_LOCKED(sc); 742 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 743 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 744 m->m_pkthdr.rcvif = NULL; 745 ieee80211_free_node(ni); 746 m_freem(m); 747 } 748 } 749 750 static usb_error_t 751 urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 752 void *data) 753 { 754 usb_error_t err; 755 int ntries = 10; 756 757 URTWN_ASSERT_LOCKED(sc); 758 759 err = 0; /* whack gcc warning */ 760 while (ntries--) { 761 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 762 req, data, 0, NULL, 250 /* ms */); 763 if (err == 0) 764 break; 765 766 URTWN_DPRINTF(sc, URTWN_DEBUG_USB, 767 "%s: control request failed, %s (retries left: %d)\n", 768 __func__, usbd_errstr(err), ntries); 769 usb_pause_mtx(&sc->sc_mtx, hz / 100); 770 } 771 return (err); 772 } 773 774 static struct ieee80211vap * 775 urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 776 enum ieee80211_opmode opmode, int flags, 777 const uint8_t bssid[IEEE80211_ADDR_LEN], 778 const uint8_t mac[IEEE80211_ADDR_LEN]) 779 { 780 struct urtwn_softc *sc = ic->ic_softc; 781 struct urtwn_vap *uvp; 782 struct ieee80211vap *vap; 783 784 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 785 return (NULL); 786 787 uvp = kmalloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 788 vap = &uvp->vap; 789 /* enable s/w bmiss handling for sta mode */ 790 791 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 792 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 793 /* out of memory */ 794 kfree(uvp, M_80211_VAP); 795 return (NULL); 796 } 797 798 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 799 urtwn_init_beacon(sc, uvp); 800 801 /* override state transition machine */ 802 uvp->newstate = vap->iv_newstate; 803 vap->iv_newstate = urtwn_newstate; 804 vap->iv_update_beacon = urtwn_update_beacon; 805 vap->iv_key_alloc = urtwn_key_alloc; 806 vap->iv_key_set = urtwn_key_set; 807 vap->iv_key_delete = urtwn_key_delete; 808 809 /* 802.11n parameters */ 810 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_16; 811 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 812 813 if (opmode == IEEE80211_M_IBSS) { 814 uvp->recv_mgmt = vap->iv_recv_mgmt; 815 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 816 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 817 } 818 819 if (URTWN_CHIP_HAS_RATECTL(sc)) 820 ieee80211_ratectl_init(vap); 821 /* complete setup */ 822 ieee80211_vap_attach(vap, ieee80211_media_change, 823 ieee80211_media_status, mac); 824 ic->ic_opmode = opmode; 825 return (vap); 826 } 827 828 static void 829 urtwn_vap_delete(struct ieee80211vap *vap) 830 { 831 struct ieee80211com *ic = vap->iv_ic; 832 struct urtwn_softc *sc = ic->ic_softc; 833 struct urtwn_vap *uvp = URTWN_VAP(vap); 834 835 if (uvp->bcn_mbuf != NULL) 836 m_freem(uvp->bcn_mbuf); 837 if (vap->iv_opmode == IEEE80211_M_IBSS) 838 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 839 if (URTWN_CHIP_HAS_RATECTL(sc)) 840 ieee80211_ratectl_deinit(vap); 841 ieee80211_vap_detach(vap); 842 kfree(uvp, M_80211_VAP); 843 } 844 845 static struct mbuf * 846 urtwn_rx_copy_to_mbuf(struct urtwn_softc *sc, struct r92c_rx_stat *stat, 847 int totlen) 848 { 849 /* ic is not used, remove to fix gcc warning */ 850 /* struct ieee80211com *ic = &sc->sc_ic; */ 851 struct mbuf *m; 852 uint32_t rxdw0; 853 int pktlen; 854 855 /* 856 * don't pass packets to the ieee80211 framework if the driver isn't 857 * RUNNING. 858 */ 859 if (!(sc->sc_flags & URTWN_RUNNING)) 860 return (NULL); 861 862 rxdw0 = le32toh(stat->rxdw0); 863 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 864 /* 865 * This should not happen since we setup our Rx filter 866 * to not receive these frames. 867 */ 868 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 869 "%s: RX flags error (%s)\n", __func__, 870 rxdw0 & R92C_RXDW0_CRCERR ? "CRC" : "ICV"); 871 goto fail; 872 } 873 874 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 875 if (pktlen < sizeof(struct ieee80211_frame_ack)) { 876 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 877 "%s: frame is too short: %d\n", __func__, pktlen); 878 goto fail; 879 } 880 881 if (__predict_false(totlen > MCLBYTES)) { 882 /* convert to m_getjcl if this happens */ 883 device_printf(sc->sc_dev, "%s: frame too long: %d (%d)\n", 884 __func__, pktlen, totlen); 885 goto fail; 886 } 887 888 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 889 if (__predict_false(m == NULL)) { 890 device_printf(sc->sc_dev, "%s: could not allocate RX mbuf\n", 891 __func__); 892 goto fail; 893 } 894 895 /* Finalize mbuf. */ 896 memcpy(mtod(m, uint8_t *), (uint8_t *)stat, totlen); 897 m->m_pkthdr.len = m->m_len = totlen; 898 899 return (m); 900 fail: 901 #if defined(__DragonFly__) 902 /* unimplemented */ 903 #else 904 counter_u64_add(ic->ic_ierrors, 1); 905 #endif 906 return (NULL); 907 } 908 909 static struct mbuf * 910 urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data) 911 { 912 struct urtwn_softc *sc = data->sc; 913 /* ic not used, remove to fix gcc error */ 914 /* struct ieee80211com *ic = &sc->sc_ic;*/ 915 struct r92c_rx_stat *stat; 916 uint8_t *buf; 917 int len; 918 919 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 920 921 if (len < sizeof(*stat)) { 922 #if defined(__DragonFly__) 923 /* unimplemented */ 924 #else 925 counter_u64_add(ic->ic_ierrors, 1); 926 #endif 927 return (NULL); 928 } 929 930 buf = data->buf; 931 stat = (struct r92c_rx_stat *)buf; 932 933 /* 934 * For 88E chips we can tie the FF flushing here; 935 * this is where we do know exactly how deep the 936 * transmit queue is. 937 * 938 * But it won't work for R92 chips, so we can't 939 * take the easy way out. 940 */ 941 942 if (sc->chip & URTWN_CHIP_88E) { 943 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT); 944 945 switch (report_sel) { 946 case R88E_RXDW3_RPT_RX: 947 return (urtwn_rxeof(sc, buf, len)); 948 case R88E_RXDW3_RPT_TX1: 949 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]); 950 break; 951 default: 952 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, 953 "%s: case %d was not handled\n", __func__, 954 report_sel); 955 break; 956 } 957 } else 958 return (urtwn_rxeof(sc, buf, len)); 959 960 return (NULL); 961 } 962 963 static struct mbuf * 964 urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len) 965 { 966 struct r92c_rx_stat *stat; 967 struct mbuf *m, *m0 = NULL, *prevm = NULL; 968 uint32_t rxdw0; 969 int totlen, pktlen, infosz, npkts; 970 971 /* Get the number of encapsulated frames. */ 972 stat = (struct r92c_rx_stat *)buf; 973 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 974 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 975 "%s: Rx %d frames in one chunk\n", __func__, npkts); 976 977 /* Process all of them. */ 978 while (npkts-- > 0) { 979 if (len < sizeof(*stat)) 980 break; 981 stat = (struct r92c_rx_stat *)buf; 982 rxdw0 = le32toh(stat->rxdw0); 983 984 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 985 if (pktlen == 0) 986 break; 987 988 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 989 990 /* Make sure everything fits in xfer. */ 991 totlen = sizeof(*stat) + infosz + pktlen; 992 if (totlen > len) 993 break; 994 995 m = urtwn_rx_copy_to_mbuf(sc, stat, totlen); 996 if (m0 == NULL) 997 m0 = m; 998 if (prevm == NULL) 999 prevm = m; 1000 else { 1001 prevm->m_next = m; 1002 prevm = m; 1003 } 1004 1005 /* Next chunk is 128-byte aligned. */ 1006 totlen = (totlen + 127) & ~127; 1007 buf += totlen; 1008 len -= totlen; 1009 } 1010 1011 return (m0); 1012 } 1013 1014 static void 1015 urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg) 1016 { 1017 struct r88e_tx_rpt_ccx *rpt = arg; 1018 struct ieee80211vap *vap; 1019 struct ieee80211_node *ni; 1020 uint8_t macid; 1021 int ntries; 1022 1023 macid = MS(rpt->rptb1, R88E_RPTB1_MACID); 1024 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT); 1025 1026 URTWN_NT_LOCK(sc); 1027 ni = sc->node_list[macid]; 1028 if (ni != NULL) { 1029 vap = ni->ni_vap; 1030 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: frame for macid %d was" 1031 "%s sent (%d retries)\n", __func__, macid, 1032 (rpt->rptb1 & R88E_RPTB1_PKT_OK) ? "" : " not", 1033 ntries); 1034 1035 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) { 1036 ieee80211_ratectl_tx_complete(vap, ni, 1037 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL); 1038 } else { 1039 ieee80211_ratectl_tx_complete(vap, ni, 1040 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL); 1041 } 1042 } else { 1043 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: macid %d, ni is NULL\n", 1044 __func__, macid); 1045 } 1046 URTWN_NT_UNLOCK(sc); 1047 } 1048 1049 static struct ieee80211_node * 1050 urtwn_rx_frame(struct urtwn_softc *sc, struct mbuf *m, int8_t *rssi_p) 1051 { 1052 struct ieee80211com *ic = &sc->sc_ic; 1053 struct ieee80211_frame_min *wh; 1054 struct r92c_rx_stat *stat; 1055 uint32_t rxdw0, rxdw3; 1056 uint8_t rate, cipher; 1057 int8_t rssi = -127; 1058 int infosz; 1059 1060 stat = mtod(m, struct r92c_rx_stat *); 1061 rxdw0 = le32toh(stat->rxdw0); 1062 rxdw3 = le32toh(stat->rxdw3); 1063 1064 rate = MS(rxdw3, R92C_RXDW3_RATE); 1065 cipher = MS(rxdw0, R92C_RXDW0_CIPHER); 1066 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1067 1068 /* Get RSSI from PHY status descriptor if present. */ 1069 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1070 if (sc->chip & URTWN_CHIP_88E) 1071 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 1072 else 1073 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 1074 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: rssi=%d\n", __func__, rssi); 1075 /* Update our average RSSI. */ 1076 urtwn_update_avgrssi(sc, rate, rssi); 1077 } 1078 1079 if (ieee80211_radiotap_active(ic)) { 1080 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1081 1082 tap->wr_flags = 0; 1083 1084 urtwn_get_tsf(sc, &tap->wr_tsft); 1085 if (__predict_false(le32toh((uint32_t)tap->wr_tsft) < 1086 le32toh(stat->rxdw5))) { 1087 tap->wr_tsft = le32toh(tap->wr_tsft >> 32) - 1; 1088 tap->wr_tsft = (uint64_t)htole32(tap->wr_tsft) << 32; 1089 } else 1090 tap->wr_tsft &= 0xffffffff00000000; 1091 tap->wr_tsft += stat->rxdw5; 1092 1093 /* XXX 20/40? */ 1094 /* XXX shortgi? */ 1095 1096 /* Map HW rate index to 802.11 rate. */ 1097 if (!(rxdw3 & R92C_RXDW3_HT)) { 1098 tap->wr_rate = ridx2rate[rate]; 1099 } else if (rate >= 12) { /* MCS0~15. */ 1100 /* Bit 7 set means HT MCS instead of rate. */ 1101 tap->wr_rate = 0x80 | (rate - 12); 1102 } 1103 1104 /* XXX TODO: this isn't right; should use the last good RSSI */ 1105 tap->wr_dbm_antsignal = rssi; 1106 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 1107 } 1108 1109 *rssi_p = rssi; 1110 1111 /* Drop descriptor. */ 1112 m_adj(m, sizeof(*stat) + infosz); 1113 wh = mtod(m, struct ieee80211_frame_min *); 1114 1115 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1116 cipher != R92C_CAM_ALGO_NONE) { 1117 m->m_flags |= M_WEP; 1118 } 1119 1120 if (m->m_len >= sizeof(*wh)) 1121 return (ieee80211_find_rxnode(ic, wh)); 1122 1123 return (NULL); 1124 } 1125 1126 static void 1127 urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 1128 { 1129 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1130 struct ieee80211com *ic = &sc->sc_ic; 1131 struct ieee80211_node *ni; 1132 struct mbuf *m = NULL, *next; 1133 struct urtwn_data *data; 1134 int8_t nf, rssi; 1135 1136 URTWN_ASSERT_LOCKED(sc); 1137 1138 switch (USB_GET_STATE(xfer)) { 1139 case USB_ST_TRANSFERRED: 1140 data = STAILQ_FIRST(&sc->sc_rx_active); 1141 if (data == NULL) 1142 goto tr_setup; 1143 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1144 m = urtwn_report_intr(xfer, data); 1145 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1146 /* FALLTHROUGH */ 1147 case USB_ST_SETUP: 1148 tr_setup: 1149 data = STAILQ_FIRST(&sc->sc_rx_inactive); 1150 if (data == NULL) { 1151 KASSERT(m == NULL, ("mbuf isn't NULL")); 1152 goto finish; 1153 } 1154 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 1155 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 1156 usbd_xfer_set_frame_data(xfer, 0, data->buf, 1157 usbd_xfer_max_len(xfer)); 1158 usbd_transfer_submit(xfer); 1159 1160 /* 1161 * To avoid LOR we should unlock our private mutex here to call 1162 * ieee80211_input() because here is at the end of a USB 1163 * callback and safe to unlock. 1164 */ 1165 while (m != NULL) { 1166 next = m->m_next; 1167 m->m_next = NULL; 1168 1169 ni = urtwn_rx_frame(sc, m, &rssi); 1170 1171 /* Store a global last-good RSSI */ 1172 if (rssi != -127) 1173 sc->last_rssi = rssi; 1174 1175 URTWN_UNLOCK(sc); 1176 1177 nf = URTWN_NOISE_FLOOR; 1178 if (ni != NULL) { 1179 if (rssi != -127) 1180 URTWN_NODE(ni)->last_rssi = rssi; 1181 if (ni->ni_flags & IEEE80211_NODE_HT) 1182 m->m_flags |= M_AMPDU; 1183 (void)ieee80211_input(ni, m, 1184 URTWN_NODE(ni)->last_rssi - nf, nf); 1185 ieee80211_free_node(ni); 1186 } else { 1187 /* Use last good global RSSI */ 1188 (void)ieee80211_input_all(ic, m, 1189 sc->last_rssi - nf, nf); 1190 } 1191 URTWN_LOCK(sc); 1192 m = next; 1193 } 1194 break; 1195 default: 1196 /* needs it to the inactive queue due to a error. */ 1197 data = STAILQ_FIRST(&sc->sc_rx_active); 1198 if (data != NULL) { 1199 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1200 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1201 } 1202 if (error != USB_ERR_CANCELLED) { 1203 usbd_xfer_set_stall(xfer); 1204 #if defined(__DragonFly__) 1205 /* unimplemented */ 1206 #else 1207 counter_u64_add(ic->ic_ierrors, 1); 1208 #endif 1209 goto tr_setup; 1210 } 1211 break; 1212 } 1213 finish: 1214 /* Finished receive; age anything left on the FF queue by a little bump */ 1215 /* 1216 * XXX TODO: just make this a callout timer schedule so we can 1217 * flush the FF staging queue if we're approaching idle. 1218 */ 1219 #ifdef IEEE80211_SUPPORT_SUPERG 1220 URTWN_UNLOCK(sc); 1221 ieee80211_ff_age_all(ic, 1); 1222 URTWN_LOCK(sc); 1223 #endif 1224 1225 /* Kick-start more transmit in case we stalled */ 1226 urtwn_start(sc); 1227 } 1228 1229 static void 1230 urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 1231 { 1232 1233 URTWN_ASSERT_LOCKED(sc); 1234 1235 if (data->ni != NULL) /* not a beacon frame */ 1236 ieee80211_tx_complete(data->ni, data->m, status); 1237 1238 if (sc->sc_tx_n_active > 0) 1239 sc->sc_tx_n_active--; 1240 1241 data->ni = NULL; 1242 data->m = NULL; 1243 1244 sc->sc_txtimer = 0; 1245 1246 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 1247 } 1248 1249 static int 1250 urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1251 int ndata, int maxsz) 1252 { 1253 int i, error; 1254 1255 for (i = 0; i < ndata; i++) { 1256 struct urtwn_data *dp = &data[i]; 1257 dp->sc = sc; 1258 dp->m = NULL; 1259 dp->buf = kmalloc(maxsz, M_USBDEV, M_INTWAIT); 1260 if (dp->buf == NULL) { 1261 device_printf(sc->sc_dev, 1262 "could not allocate buffer\n"); 1263 error = ENOMEM; 1264 goto fail; 1265 } 1266 dp->ni = NULL; 1267 } 1268 1269 return (0); 1270 fail: 1271 urtwn_free_list(sc, data, ndata); 1272 return (error); 1273 } 1274 1275 static int 1276 urtwn_alloc_rx_list(struct urtwn_softc *sc) 1277 { 1278 int error, i; 1279 1280 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1281 URTWN_RXBUFSZ); 1282 if (error != 0) 1283 return (error); 1284 1285 STAILQ_INIT(&sc->sc_rx_active); 1286 STAILQ_INIT(&sc->sc_rx_inactive); 1287 1288 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1289 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1290 1291 return (0); 1292 } 1293 1294 static int 1295 urtwn_alloc_tx_list(struct urtwn_softc *sc) 1296 { 1297 int error, i; 1298 1299 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1300 URTWN_TXBUFSZ); 1301 if (error != 0) 1302 return (error); 1303 1304 STAILQ_INIT(&sc->sc_tx_active); 1305 STAILQ_INIT(&sc->sc_tx_inactive); 1306 STAILQ_INIT(&sc->sc_tx_pending); 1307 1308 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1309 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1310 1311 return (0); 1312 } 1313 1314 static void 1315 urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 1316 { 1317 int i; 1318 1319 for (i = 0; i < ndata; i++) { 1320 struct urtwn_data *dp = &data[i]; 1321 1322 if (dp->buf != NULL) { 1323 kfree(dp->buf, M_USBDEV); 1324 dp->buf = NULL; 1325 } 1326 if (dp->ni != NULL) { 1327 ieee80211_free_node(dp->ni); 1328 dp->ni = NULL; 1329 } 1330 } 1331 } 1332 1333 static void 1334 urtwn_free_rx_list(struct urtwn_softc *sc) 1335 { 1336 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 1337 } 1338 1339 static void 1340 urtwn_free_tx_list(struct urtwn_softc *sc) 1341 { 1342 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 1343 } 1344 1345 static void 1346 urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1347 { 1348 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1349 #ifdef IEEE80211_SUPPORT_SUPERG 1350 struct ieee80211com *ic = &sc->sc_ic; 1351 #endif 1352 struct urtwn_data *data; 1353 1354 URTWN_ASSERT_LOCKED(sc); 1355 1356 switch (USB_GET_STATE(xfer)){ 1357 case USB_ST_TRANSFERRED: 1358 data = STAILQ_FIRST(&sc->sc_tx_active); 1359 if (data == NULL) 1360 goto tr_setup; 1361 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1362 urtwn_txeof(sc, data, 0); 1363 /* FALLTHROUGH */ 1364 case USB_ST_SETUP: 1365 tr_setup: 1366 data = STAILQ_FIRST(&sc->sc_tx_pending); 1367 if (data == NULL) { 1368 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1369 "%s: empty pending queue\n", __func__); 1370 sc->sc_tx_n_active = 0; 1371 goto finish; 1372 } 1373 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1374 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1375 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1376 usbd_transfer_submit(xfer); 1377 sc->sc_tx_n_active++; 1378 break; 1379 default: 1380 data = STAILQ_FIRST(&sc->sc_tx_active); 1381 if (data == NULL) 1382 goto tr_setup; 1383 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1384 urtwn_txeof(sc, data, 1); 1385 if (error != USB_ERR_CANCELLED) { 1386 usbd_xfer_set_stall(xfer); 1387 goto tr_setup; 1388 } 1389 break; 1390 } 1391 finish: 1392 #ifdef IEEE80211_SUPPORT_SUPERG 1393 /* 1394 * If the TX active queue drops below a certain 1395 * threshold, ensure we age fast-frames out so they're 1396 * transmitted. 1397 */ 1398 if (sc->sc_tx_n_active <= 1) { 1399 /* XXX ew - net80211 should defer this for us! */ 1400 1401 /* 1402 * Note: this sc_tx_n_active currently tracks 1403 * the number of pending transmit submissions 1404 * and not the actual depth of the TX frames 1405 * pending to the hardware. That means that 1406 * we're going to end up with some sub-optimal 1407 * aggregation behaviour. 1408 */ 1409 /* 1410 * XXX TODO: just make this a callout timer schedule so we can 1411 * flush the FF staging queue if we're approaching idle. 1412 */ 1413 URTWN_UNLOCK(sc); 1414 ieee80211_ff_flush(ic, WME_AC_VO); 1415 ieee80211_ff_flush(ic, WME_AC_VI); 1416 ieee80211_ff_flush(ic, WME_AC_BE); 1417 ieee80211_ff_flush(ic, WME_AC_BK); 1418 URTWN_LOCK(sc); 1419 } 1420 #endif 1421 /* Kick-start more transmit */ 1422 urtwn_start(sc); 1423 } 1424 1425 static struct urtwn_data * 1426 _urtwn_getbuf(struct urtwn_softc *sc) 1427 { 1428 struct urtwn_data *bf; 1429 1430 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1431 if (bf != NULL) 1432 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1433 else { 1434 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1435 "%s: out of xmit buffers\n", __func__); 1436 } 1437 return (bf); 1438 } 1439 1440 static struct urtwn_data * 1441 urtwn_getbuf(struct urtwn_softc *sc) 1442 { 1443 struct urtwn_data *bf; 1444 1445 URTWN_ASSERT_LOCKED(sc); 1446 1447 bf = _urtwn_getbuf(sc); 1448 if (bf == NULL) { 1449 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: stop queue\n", 1450 __func__); 1451 } 1452 return (bf); 1453 } 1454 1455 static usb_error_t 1456 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1457 int len) 1458 { 1459 usb_device_request_t req; 1460 1461 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1462 req.bRequest = R92C_REQ_REGS; 1463 USETW(req.wValue, addr); 1464 USETW(req.wIndex, 0); 1465 USETW(req.wLength, len); 1466 return (urtwn_do_request(sc, &req, buf)); 1467 } 1468 1469 static usb_error_t 1470 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1471 { 1472 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1473 } 1474 1475 static usb_error_t 1476 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1477 { 1478 val = htole16(val); 1479 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1480 } 1481 1482 static usb_error_t 1483 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1484 { 1485 val = htole32(val); 1486 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1487 } 1488 1489 static usb_error_t 1490 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1491 int len) 1492 { 1493 usb_device_request_t req; 1494 1495 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1496 req.bRequest = R92C_REQ_REGS; 1497 USETW(req.wValue, addr); 1498 USETW(req.wIndex, 0); 1499 USETW(req.wLength, len); 1500 return (urtwn_do_request(sc, &req, buf)); 1501 } 1502 1503 static uint8_t 1504 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1505 { 1506 uint8_t val; 1507 1508 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1509 return (0xff); 1510 return (val); 1511 } 1512 1513 static uint16_t 1514 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1515 { 1516 uint16_t val; 1517 1518 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1519 return (0xffff); 1520 return (le16toh(val)); 1521 } 1522 1523 static uint32_t 1524 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1525 { 1526 uint32_t val; 1527 1528 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1529 return (0xffffffff); 1530 return (le32toh(val)); 1531 } 1532 1533 static int 1534 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1535 { 1536 struct r92c_fw_cmd cmd; 1537 usb_error_t error; 1538 int ntries; 1539 1540 if (!(sc->sc_flags & URTWN_FW_LOADED)) { 1541 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, "%s: firmware " 1542 "was not loaded; command (id %d) will be discarded\n", 1543 __func__, id); 1544 return (0); 1545 } 1546 1547 /* Wait for current FW box to be empty. */ 1548 for (ntries = 0; ntries < 100; ntries++) { 1549 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1550 break; 1551 urtwn_ms_delay(sc); 1552 } 1553 if (ntries == 100) { 1554 device_printf(sc->sc_dev, 1555 "could not send firmware command\n"); 1556 return (ETIMEDOUT); 1557 } 1558 memset(&cmd, 0, sizeof(cmd)); 1559 cmd.id = id; 1560 if (len > 3) 1561 cmd.id |= R92C_CMD_FLAG_EXT; 1562 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1563 memcpy(cmd.msg, buf, len); 1564 1565 /* Write the first word last since that will trigger the FW. */ 1566 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1567 (uint8_t *)&cmd + 4, 2); 1568 if (error != USB_ERR_NORMAL_COMPLETION) 1569 return (EIO); 1570 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1571 (uint8_t *)&cmd + 0, 4); 1572 if (error != USB_ERR_NORMAL_COMPLETION) 1573 return (EIO); 1574 1575 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1576 return (0); 1577 } 1578 1579 static void 1580 urtwn_cmdq_cb(void *arg, int pending) 1581 { 1582 struct urtwn_softc *sc = arg; 1583 struct urtwn_cmdq *item; 1584 1585 /* 1586 * Device must be powered on (via urtwn_power_on()) 1587 * before any command may be sent. 1588 */ 1589 URTWN_LOCK(sc); 1590 if (!(sc->sc_flags & URTWN_RUNNING)) { 1591 URTWN_UNLOCK(sc); 1592 return; 1593 } 1594 1595 URTWN_CMDQ_LOCK(sc); 1596 while (sc->cmdq[sc->cmdq_first].func != NULL) { 1597 item = &sc->cmdq[sc->cmdq_first]; 1598 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE; 1599 URTWN_CMDQ_UNLOCK(sc); 1600 1601 item->func(sc, &item->data); 1602 1603 URTWN_CMDQ_LOCK(sc); 1604 memset(item, 0, sizeof (*item)); 1605 } 1606 URTWN_CMDQ_UNLOCK(sc); 1607 URTWN_UNLOCK(sc); 1608 } 1609 1610 static int 1611 urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len, 1612 CMD_FUNC_PROTO) 1613 { 1614 struct ieee80211com *ic = &sc->sc_ic; 1615 1616 KASSERT(len <= sizeof(union sec_param), ("buffer overflow")); 1617 1618 URTWN_CMDQ_LOCK(sc); 1619 if (sc->cmdq[sc->cmdq_last].func != NULL) { 1620 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__); 1621 URTWN_CMDQ_UNLOCK(sc); 1622 1623 return (EAGAIN); 1624 } 1625 1626 if (ptr != NULL) 1627 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len); 1628 sc->cmdq[sc->cmdq_last].func = func; 1629 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE; 1630 URTWN_CMDQ_UNLOCK(sc); 1631 1632 ieee80211_runtask(ic, &sc->cmdq_task); 1633 1634 return (0); 1635 } 1636 1637 static __inline void 1638 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1639 { 1640 1641 sc->sc_rf_write(sc, chain, addr, val); 1642 } 1643 1644 static void 1645 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1646 uint32_t val) 1647 { 1648 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1649 SM(R92C_LSSI_PARAM_ADDR, addr) | 1650 SM(R92C_LSSI_PARAM_DATA, val)); 1651 } 1652 1653 static void 1654 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1655 uint32_t val) 1656 { 1657 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1658 SM(R88E_LSSI_PARAM_ADDR, addr) | 1659 SM(R92C_LSSI_PARAM_DATA, val)); 1660 } 1661 1662 static uint32_t 1663 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1664 { 1665 uint32_t reg[R92C_MAX_CHAINS], val; 1666 1667 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1668 if (chain != 0) 1669 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1670 1671 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1672 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1673 urtwn_ms_delay(sc); 1674 1675 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1676 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1677 R92C_HSSI_PARAM2_READ_EDGE); 1678 urtwn_ms_delay(sc); 1679 1680 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1681 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1682 urtwn_ms_delay(sc); 1683 1684 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1685 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1686 else 1687 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1688 return (MS(val, R92C_LSSI_READBACK_DATA)); 1689 } 1690 1691 static int 1692 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1693 { 1694 usb_error_t error; 1695 int ntries; 1696 1697 error = urtwn_write_4(sc, R92C_LLT_INIT, 1698 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1699 SM(R92C_LLT_INIT_ADDR, addr) | 1700 SM(R92C_LLT_INIT_DATA, data)); 1701 if (error != USB_ERR_NORMAL_COMPLETION) 1702 return (EIO); 1703 /* Wait for write operation to complete. */ 1704 for (ntries = 0; ntries < 20; ntries++) { 1705 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1706 R92C_LLT_INIT_OP_NO_ACTIVE) 1707 return (0); 1708 urtwn_ms_delay(sc); 1709 } 1710 return (ETIMEDOUT); 1711 } 1712 1713 static int 1714 urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1715 { 1716 uint32_t reg; 1717 usb_error_t error; 1718 int ntries; 1719 1720 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1721 return (EFAULT); 1722 1723 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1724 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1725 reg &= ~R92C_EFUSE_CTRL_VALID; 1726 1727 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1728 if (error != USB_ERR_NORMAL_COMPLETION) 1729 return (EIO); 1730 /* Wait for read operation to complete. */ 1731 for (ntries = 0; ntries < 100; ntries++) { 1732 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1733 if (reg & R92C_EFUSE_CTRL_VALID) 1734 break; 1735 urtwn_ms_delay(sc); 1736 } 1737 if (ntries == 100) { 1738 device_printf(sc->sc_dev, 1739 "could not read efuse byte at address 0x%x\n", 1740 sc->last_rom_addr); 1741 return (ETIMEDOUT); 1742 } 1743 1744 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1745 sc->last_rom_addr++; 1746 1747 return (0); 1748 } 1749 1750 static int 1751 urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1752 uint8_t msk) 1753 { 1754 uint8_t reg; 1755 int i, error; 1756 1757 for (i = 0; i < 4; i++) { 1758 if (msk & (1 << i)) 1759 continue; 1760 error = urtwn_efuse_read_next(sc, ®); 1761 if (error != 0) 1762 return (error); 1763 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1764 off * 8 + i * 2, reg); 1765 rom[off * 8 + i * 2 + 0] = reg; 1766 1767 error = urtwn_efuse_read_next(sc, ®); 1768 if (error != 0) 1769 return (error); 1770 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1771 off * 8 + i * 2 + 1, reg); 1772 rom[off * 8 + i * 2 + 1] = reg; 1773 } 1774 1775 return (0); 1776 } 1777 1778 #ifdef USB_DEBUG 1779 static void 1780 urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1781 { 1782 int i; 1783 1784 /* Dump ROM contents. */ 1785 device_printf(sc->sc_dev, "%s:", __func__); 1786 for (i = 0; i < size; i++) { 1787 if (i % 32 == 0) 1788 kprintf("\n%03X: ", i); 1789 else if (i % 4 == 0) 1790 kprintf(" "); 1791 1792 kprintf("%02X", rom[i]); 1793 } 1794 kprintf("\n"); 1795 } 1796 #endif 1797 1798 static int 1799 urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1800 { 1801 #define URTWN_CHK(res) do { \ 1802 if ((error = res) != 0) \ 1803 goto end; \ 1804 } while(0) 1805 uint8_t msk, off, reg; 1806 int error; 1807 1808 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1809 1810 /* Read full ROM image. */ 1811 sc->last_rom_addr = 0; 1812 memset(rom, 0xff, size); 1813 1814 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1815 while (reg != 0xff) { 1816 /* check for extended header */ 1817 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1818 off = reg >> 5; 1819 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1820 1821 if ((reg & 0x0f) != 0x0f) 1822 off = ((reg & 0xf0) >> 1) | off; 1823 else 1824 continue; 1825 } else 1826 off = reg >> 4; 1827 msk = reg & 0xf; 1828 1829 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1830 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1831 } 1832 1833 end: 1834 1835 #ifdef USB_DEBUG 1836 if (sc->sc_debug & URTWN_DEBUG_ROM) 1837 urtwn_dump_rom_contents(sc, rom, size); 1838 #endif 1839 1840 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1841 1842 if (error != 0) { 1843 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1844 __func__); 1845 } 1846 1847 return (error); 1848 #undef URTWN_CHK 1849 } 1850 1851 static int 1852 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1853 { 1854 usb_error_t error; 1855 uint32_t reg; 1856 1857 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1858 if (error != USB_ERR_NORMAL_COMPLETION) 1859 return (EIO); 1860 1861 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1862 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1863 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1864 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1865 if (error != USB_ERR_NORMAL_COMPLETION) 1866 return (EIO); 1867 } 1868 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1869 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1870 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1871 reg | R92C_SYS_FUNC_EN_ELDR); 1872 if (error != USB_ERR_NORMAL_COMPLETION) 1873 return (EIO); 1874 } 1875 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1876 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1877 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1878 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1879 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1880 if (error != USB_ERR_NORMAL_COMPLETION) 1881 return (EIO); 1882 } 1883 1884 return (0); 1885 } 1886 1887 static int 1888 urtwn_read_chipid(struct urtwn_softc *sc) 1889 { 1890 uint32_t reg; 1891 1892 if (sc->chip & URTWN_CHIP_88E) 1893 return (0); 1894 1895 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1896 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1897 return (EIO); 1898 1899 if (reg & R92C_SYS_CFG_TYPE_92C) { 1900 sc->chip |= URTWN_CHIP_92C; 1901 /* Check if it is a castrated 8192C. */ 1902 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1903 R92C_HPON_FSM_CHIP_BONDING_ID) == 1904 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1905 sc->chip |= URTWN_CHIP_92C_1T2R; 1906 } 1907 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1908 sc->chip |= URTWN_CHIP_UMC; 1909 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1910 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1911 } 1912 return (0); 1913 } 1914 1915 static int 1916 urtwn_read_rom(struct urtwn_softc *sc) 1917 { 1918 struct r92c_rom *rom = &sc->rom.r92c_rom; 1919 int error; 1920 1921 /* Read full ROM image. */ 1922 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1923 if (error != 0) 1924 return (error); 1925 1926 /* XXX Weird but this is what the vendor driver does. */ 1927 sc->last_rom_addr = 0x1fa; 1928 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1929 if (error != 0) 1930 return (error); 1931 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: PA setting=0x%x\n", __func__, 1932 sc->pa_setting); 1933 1934 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1935 1936 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1937 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type=%d\n", 1938 __func__, sc->regulatory); 1939 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1940 1941 sc->sc_rf_write = urtwn_r92c_rf_write; 1942 sc->sc_power_on = urtwn_r92c_power_on; 1943 sc->sc_power_off = urtwn_r92c_power_off; 1944 1945 return (0); 1946 } 1947 1948 static int 1949 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1950 { 1951 struct r88e_rom *rom = &sc->rom.r88e_rom; 1952 int error; 1953 1954 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(sc->rom.r88e_rom)); 1955 if (error != 0) 1956 return (error); 1957 1958 sc->bw20_tx_pwr_diff = (rom->tx_pwr_diff >> 4); 1959 if (sc->bw20_tx_pwr_diff & 0x08) 1960 sc->bw20_tx_pwr_diff |= 0xf0; 1961 sc->ofdm_tx_pwr_diff = (rom->tx_pwr_diff & 0xf); 1962 if (sc->ofdm_tx_pwr_diff & 0x08) 1963 sc->ofdm_tx_pwr_diff |= 0xf0; 1964 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 1965 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type %d\n", 1966 __func__,sc->regulatory); 1967 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1968 1969 sc->sc_rf_write = urtwn_r88e_rf_write; 1970 sc->sc_power_on = urtwn_r88e_power_on; 1971 sc->sc_power_off = urtwn_r88e_power_off; 1972 1973 return (0); 1974 } 1975 1976 static __inline uint8_t 1977 rate2ridx(uint8_t rate) 1978 { 1979 if (rate & IEEE80211_RATE_MCS) { 1980 /* 11n rates start at idx 12 */ 1981 return ((rate & 0xf) + 12); 1982 } 1983 switch (rate) { 1984 /* 11g */ 1985 case 12: return 4; 1986 case 18: return 5; 1987 case 24: return 6; 1988 case 36: return 7; 1989 case 48: return 8; 1990 case 72: return 9; 1991 case 96: return 10; 1992 case 108: return 11; 1993 /* 11b */ 1994 case 2: return 0; 1995 case 4: return 1; 1996 case 11: return 2; 1997 case 22: return 3; 1998 default: return URTWN_RIDX_UNKNOWN; 1999 } 2000 } 2001 2002 /* 2003 * Initialize rate adaptation in firmware. 2004 */ 2005 static int 2006 urtwn_ra_init(struct urtwn_softc *sc) 2007 { 2008 struct ieee80211com *ic = &sc->sc_ic; 2009 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2010 struct ieee80211_node *ni; 2011 struct ieee80211_rateset *rs, *rs_ht; 2012 struct r92c_fw_cmd_macid_cfg cmd; 2013 uint32_t rates, basicrates; 2014 uint8_t mode, ridx; 2015 int maxrate, maxbasicrate, error, i; 2016 2017 ni = ieee80211_ref_node(vap->iv_bss); 2018 rs = &ni->ni_rates; 2019 rs_ht = (struct ieee80211_rateset *) &ni->ni_htrates; 2020 2021 /* Get normal and basic rates mask. */ 2022 rates = basicrates = 0; 2023 maxrate = maxbasicrate = 0; 2024 2025 /* This is for 11bg */ 2026 for (i = 0; i < rs->rs_nrates; i++) { 2027 /* Convert 802.11 rate to HW rate index. */ 2028 ridx = rate2ridx(IEEE80211_RV(rs->rs_rates[i])); 2029 if (ridx == URTWN_RIDX_UNKNOWN) /* Unknown rate, skip. */ 2030 continue; 2031 rates |= 1 << ridx; 2032 if (ridx > maxrate) 2033 maxrate = ridx; 2034 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 2035 basicrates |= 1 << ridx; 2036 if (ridx > maxbasicrate) 2037 maxbasicrate = ridx; 2038 } 2039 } 2040 2041 /* If we're doing 11n, enable 11n rates */ 2042 if (ni->ni_flags & IEEE80211_NODE_HT) { 2043 for (i = 0; i < rs_ht->rs_nrates; i++) { 2044 if ((rs_ht->rs_rates[i] & 0x7f) > 0xf) 2045 continue; 2046 /* 11n rates start at index 12 */ 2047 ridx = ((rs_ht->rs_rates[i]) & 0xf) + 12; 2048 rates |= (1 << ridx); 2049 2050 /* Guard against the rate table being oddly ordered */ 2051 if (ridx > maxrate) 2052 maxrate = ridx; 2053 } 2054 } 2055 2056 #if 0 2057 if (ic->ic_curmode == IEEE80211_MODE_11NG) 2058 raid = R92C_RAID_11GN; 2059 #endif 2060 /* NB: group addressed frames are done at 11bg rates for now */ 2061 if (ic->ic_curmode == IEEE80211_MODE_11B) 2062 mode = R92C_RAID_11B; 2063 else 2064 mode = R92C_RAID_11BG; 2065 /* XXX misleading 'mode' value here for unicast frames */ 2066 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, 2067 "%s: mode 0x%x, rates 0x%08x, basicrates 0x%08x\n", __func__, 2068 mode, rates, basicrates); 2069 2070 /* Set rates mask for group addressed frames. */ 2071 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 2072 cmd.mask = htole32(mode << 28 | basicrates); 2073 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 2074 if (error != 0) { 2075 ieee80211_free_node(ni); 2076 device_printf(sc->sc_dev, 2077 "could not add broadcast station\n"); 2078 return (error); 2079 } 2080 2081 /* Set initial MRR rate. */ 2082 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxbasicrate %d\n", __func__, 2083 maxbasicrate); 2084 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 2085 maxbasicrate); 2086 2087 /* Set rates mask for unicast frames. */ 2088 if (ni->ni_flags & IEEE80211_NODE_HT) 2089 mode = R92C_RAID_11GN; 2090 else if (ic->ic_curmode == IEEE80211_MODE_11B) 2091 mode = R92C_RAID_11B; 2092 else 2093 mode = R92C_RAID_11BG; 2094 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 2095 cmd.mask = htole32(mode << 28 | rates); 2096 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 2097 if (error != 0) { 2098 ieee80211_free_node(ni); 2099 device_printf(sc->sc_dev, "could not add BSS station\n"); 2100 return (error); 2101 } 2102 /* Set initial MRR rate. */ 2103 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxrate %d\n", __func__, 2104 maxrate); 2105 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 2106 maxrate); 2107 2108 /* Indicate highest supported rate. */ 2109 if (ni->ni_flags & IEEE80211_NODE_HT) 2110 ni->ni_txrate = rs_ht->rs_rates[rs_ht->rs_nrates - 1] 2111 | IEEE80211_RATE_MCS; 2112 else 2113 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 2114 ieee80211_free_node(ni); 2115 2116 return (0); 2117 } 2118 2119 static void 2120 urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2121 { 2122 struct r92c_tx_desc *txd = &uvp->bcn_desc; 2123 2124 txd->txdw0 = htole32( 2125 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 2126 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2127 txd->txdw1 = htole32( 2128 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 2129 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2130 2131 if (sc->chip & URTWN_CHIP_88E) { 2132 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 2133 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 2134 } else { 2135 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 2136 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2137 } 2138 2139 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 2140 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 2141 } 2142 2143 static int 2144 urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 2145 { 2146 struct ieee80211vap *vap = ni->ni_vap; 2147 struct urtwn_vap *uvp = URTWN_VAP(vap); 2148 struct mbuf *m; 2149 int error; 2150 2151 URTWN_ASSERT_LOCKED(sc); 2152 2153 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 2154 return (EINVAL); 2155 2156 m = ieee80211_beacon_alloc(ni); 2157 if (m == NULL) { 2158 device_printf(sc->sc_dev, 2159 "%s: could not allocate beacon frame\n", __func__); 2160 return (ENOMEM); 2161 } 2162 2163 if (uvp->bcn_mbuf != NULL) 2164 m_freem(uvp->bcn_mbuf); 2165 2166 uvp->bcn_mbuf = m; 2167 2168 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 2169 return (error); 2170 2171 /* XXX bcnq stuck workaround */ 2172 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 2173 return (error); 2174 2175 URTWN_DPRINTF(sc, URTWN_DEBUG_BEACON, "%s: beacon was %srecognized\n", 2176 __func__, urtwn_read_1(sc, R92C_TDECTRL + 2) & 2177 (R92C_TDECTRL_BCN_VALID >> 16) ? "" : "not "); 2178 2179 return (0); 2180 } 2181 2182 static void 2183 urtwn_update_beacon(struct ieee80211vap *vap, int item) 2184 { 2185 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2186 struct urtwn_vap *uvp = URTWN_VAP(vap); 2187 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 2188 struct ieee80211_node *ni = vap->iv_bss; 2189 int mcast = 0; 2190 2191 URTWN_LOCK(sc); 2192 if (uvp->bcn_mbuf == NULL) { 2193 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 2194 if (uvp->bcn_mbuf == NULL) { 2195 device_printf(sc->sc_dev, 2196 "%s: could not allocate beacon frame\n", __func__); 2197 URTWN_UNLOCK(sc); 2198 return; 2199 } 2200 } 2201 URTWN_UNLOCK(sc); 2202 2203 if (item == IEEE80211_BEACON_TIM) 2204 mcast = 1; /* XXX */ 2205 2206 setbit(bo->bo_flags, item); 2207 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 2208 2209 URTWN_LOCK(sc); 2210 urtwn_tx_beacon(sc, uvp); 2211 URTWN_UNLOCK(sc); 2212 } 2213 2214 /* 2215 * Push a beacon frame into the chip. Beacon will 2216 * be repeated by the chip every R92C_BCN_INTERVAL. 2217 */ 2218 static int 2219 urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2220 { 2221 struct r92c_tx_desc *desc = &uvp->bcn_desc; 2222 struct urtwn_data *bf; 2223 2224 URTWN_ASSERT_LOCKED(sc); 2225 2226 bf = urtwn_getbuf(sc); 2227 if (bf == NULL) 2228 return (ENOMEM); 2229 2230 memcpy(bf->buf, desc, sizeof(*desc)); 2231 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 2232 2233 sc->sc_txtimer = 5; 2234 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2235 2236 return (0); 2237 } 2238 2239 static int 2240 urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2241 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2242 { 2243 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2244 uint8_t i; 2245 2246 if (!(&vap->iv_nw_keys[0] <= k && 2247 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2248 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2249 URTWN_LOCK(sc); 2250 /* 2251 * First 4 slots for group keys, 2252 * what is left - for pairwise. 2253 * XXX incompatible with IBSS RSN. 2254 */ 2255 for (i = IEEE80211_WEP_NKID; 2256 i < R92C_CAM_ENTRY_COUNT; i++) { 2257 if ((sc->keys_bmap & (1 << i)) == 0) { 2258 sc->keys_bmap |= 1 << i; 2259 *keyix = i; 2260 break; 2261 } 2262 } 2263 URTWN_UNLOCK(sc); 2264 if (i == R92C_CAM_ENTRY_COUNT) { 2265 device_printf(sc->sc_dev, 2266 "%s: no free space in the key table\n", 2267 __func__); 2268 return 0; 2269 } 2270 } else 2271 *keyix = 0; 2272 } else { 2273 *keyix = k - vap->iv_nw_keys; 2274 } 2275 *rxkeyix = *keyix; 2276 return 1; 2277 } 2278 2279 static void 2280 urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data) 2281 { 2282 struct ieee80211_key *k = &data->key; 2283 uint8_t algo, keyid; 2284 int i, error; 2285 2286 if (k->wk_keyix < IEEE80211_WEP_NKID) 2287 keyid = k->wk_keyix; 2288 else 2289 keyid = 0; 2290 2291 /* Map net80211 cipher to HW crypto algorithm. */ 2292 switch (k->wk_cipher->ic_cipher) { 2293 case IEEE80211_CIPHER_WEP: 2294 if (k->wk_keylen < 8) 2295 algo = R92C_CAM_ALGO_WEP40; 2296 else 2297 algo = R92C_CAM_ALGO_WEP104; 2298 break; 2299 case IEEE80211_CIPHER_TKIP: 2300 algo = R92C_CAM_ALGO_TKIP; 2301 break; 2302 case IEEE80211_CIPHER_AES_CCM: 2303 algo = R92C_CAM_ALGO_AES; 2304 break; 2305 default: 2306 device_printf(sc->sc_dev, "%s: undefined cipher %d\n", 2307 __func__, k->wk_cipher->ic_cipher); 2308 return; 2309 } 2310 2311 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2312 "%s: keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, " 2313 "macaddr %s\n", __func__, k->wk_keyix, keyid, 2314 k->wk_cipher->ic_cipher, algo, k->wk_flags, k->wk_keylen, 2315 ether_sprintf(k->wk_macaddr)); 2316 2317 /* Write key. */ 2318 for (i = 0; i < 4; i++) { 2319 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 2320 le32dec(&k->wk_key[i * 4])); 2321 if (error != 0) 2322 goto fail; 2323 } 2324 2325 /* Write CTL0 last since that will validate the CAM entry. */ 2326 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 2327 le32dec(&k->wk_macaddr[2])); 2328 if (error != 0) 2329 goto fail; 2330 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 2331 SM(R92C_CAM_ALGO, algo) | 2332 SM(R92C_CAM_KEYID, keyid) | 2333 SM(R92C_CAM_MACLO, le16dec(&k->wk_macaddr[0])) | 2334 R92C_CAM_VALID); 2335 if (error != 0) 2336 goto fail; 2337 2338 return; 2339 2340 fail: 2341 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error); 2342 } 2343 2344 static void 2345 urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data) 2346 { 2347 struct ieee80211_key *k = &data->key; 2348 int i; 2349 2350 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2351 "%s: keyix %d, flags %04X, macaddr %s\n", __func__, 2352 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr)); 2353 2354 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0); 2355 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0); 2356 2357 /* Clear key. */ 2358 for (i = 0; i < 4; i++) 2359 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0); 2360 sc->keys_bmap &= ~(1 << k->wk_keyix); 2361 } 2362 2363 static int 2364 urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k) 2365 { 2366 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2367 2368 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2369 /* Not for us. */ 2370 return (1); 2371 } 2372 2373 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb)); 2374 } 2375 2376 static int 2377 urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2378 { 2379 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2380 2381 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2382 /* Not for us. */ 2383 return (1); 2384 } 2385 2386 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb)); 2387 } 2388 2389 static void 2390 urtwn_tsf_task_adhoc(void *arg, int pending) 2391 { 2392 struct ieee80211vap *vap = arg; 2393 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2394 struct ieee80211_node *ni; 2395 uint32_t reg; 2396 2397 URTWN_LOCK(sc); 2398 ni = ieee80211_ref_node(vap->iv_bss); 2399 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 2400 2401 /* Accept beacons with the same BSSID. */ 2402 urtwn_set_rx_bssid_all(sc, 0); 2403 2404 /* Enable synchronization. */ 2405 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 2406 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2407 2408 /* Synchronize. */ 2409 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 2410 2411 /* Disable synchronization. */ 2412 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 2413 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2414 2415 /* Remove beacon filter. */ 2416 urtwn_set_rx_bssid_all(sc, 1); 2417 2418 /* Enable beaconing. */ 2419 urtwn_write_1(sc, R92C_MBID_NUM, 2420 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2421 reg |= R92C_BCN_CTRL_EN_BCN; 2422 2423 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2424 ieee80211_free_node(ni); 2425 URTWN_UNLOCK(sc); 2426 } 2427 2428 static void 2429 urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 2430 { 2431 struct ieee80211com *ic = &sc->sc_ic; 2432 struct urtwn_vap *uvp = URTWN_VAP(vap); 2433 2434 /* Reset TSF. */ 2435 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2436 2437 switch (vap->iv_opmode) { 2438 case IEEE80211_M_STA: 2439 /* Enable TSF synchronization. */ 2440 urtwn_write_1(sc, R92C_BCN_CTRL, 2441 urtwn_read_1(sc, R92C_BCN_CTRL) & 2442 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 2443 break; 2444 case IEEE80211_M_IBSS: 2445 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 2446 break; 2447 case IEEE80211_M_HOSTAP: 2448 /* Enable beaconing. */ 2449 urtwn_write_1(sc, R92C_MBID_NUM, 2450 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2451 urtwn_write_1(sc, R92C_BCN_CTRL, 2452 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 2453 break; 2454 default: 2455 device_printf(sc->sc_dev, "undefined opmode %d\n", 2456 vap->iv_opmode); 2457 return; 2458 } 2459 } 2460 2461 static void 2462 urtwn_get_tsf(struct urtwn_softc *sc, uint64_t *buf) 2463 { 2464 urtwn_read_region_1(sc, R92C_TSFTR, (uint8_t *)buf, sizeof(*buf)); 2465 } 2466 2467 static void 2468 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 2469 { 2470 uint8_t reg; 2471 2472 if (led == URTWN_LED_LINK) { 2473 if (sc->chip & URTWN_CHIP_88E) { 2474 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 2475 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 2476 if (!on) { 2477 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 2478 urtwn_write_1(sc, R92C_LEDCFG2, 2479 reg | R92C_LEDCFG0_DIS); 2480 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 2481 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 2482 0xfe); 2483 } 2484 } else { 2485 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 2486 if (!on) 2487 reg |= R92C_LEDCFG0_DIS; 2488 urtwn_write_1(sc, R92C_LEDCFG0, reg); 2489 } 2490 sc->ledlink = on; /* Save LED state. */ 2491 } 2492 } 2493 2494 static void 2495 urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 2496 { 2497 uint8_t reg; 2498 2499 reg = urtwn_read_1(sc, R92C_MSR); 2500 reg = (reg & ~R92C_MSR_MASK) | mode; 2501 urtwn_write_1(sc, R92C_MSR, reg); 2502 } 2503 2504 static void 2505 urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 2506 const struct ieee80211_rx_stats *rxs, 2507 int rssi, int nf) 2508 { 2509 struct ieee80211vap *vap = ni->ni_vap; 2510 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2511 struct urtwn_vap *uvp = URTWN_VAP(vap); 2512 uint64_t ni_tstamp, curr_tstamp; 2513 2514 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 2515 2516 if (vap->iv_state == IEEE80211_S_RUN && 2517 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 2518 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 2519 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 2520 URTWN_LOCK(sc); 2521 urtwn_get_tsf(sc, &curr_tstamp); 2522 URTWN_UNLOCK(sc); 2523 curr_tstamp = le64toh(curr_tstamp); 2524 2525 if (ni_tstamp >= curr_tstamp) 2526 (void) ieee80211_ibss_merge(ni); 2527 } 2528 } 2529 2530 static int 2531 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2532 { 2533 struct urtwn_vap *uvp = URTWN_VAP(vap); 2534 struct ieee80211com *ic = vap->iv_ic; 2535 struct urtwn_softc *sc = ic->ic_softc; 2536 struct ieee80211_node *ni; 2537 enum ieee80211_state ostate; 2538 uint32_t reg; 2539 uint8_t mode; 2540 int error = 0; 2541 2542 ostate = vap->iv_state; 2543 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s -> %s\n", 2544 ieee80211_state_name[ostate], ieee80211_state_name[nstate]); 2545 2546 IEEE80211_UNLOCK(ic); 2547 URTWN_LOCK(sc); 2548 callout_stop(&sc->sc_watchdog_ch); 2549 2550 if (ostate == IEEE80211_S_RUN) { 2551 /* Stop calibration. */ 2552 callout_stop(&sc->sc_calib_to); 2553 2554 /* Turn link LED off. */ 2555 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2556 2557 /* Set media status to 'No Link'. */ 2558 urtwn_set_mode(sc, R92C_MSR_NOLINK); 2559 2560 /* Stop Rx of data frames. */ 2561 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2562 2563 /* Disable TSF synchronization. */ 2564 urtwn_write_1(sc, R92C_BCN_CTRL, 2565 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 2566 R92C_BCN_CTRL_DIS_TSF_UDT0); 2567 2568 /* Disable beaconing. */ 2569 urtwn_write_1(sc, R92C_MBID_NUM, 2570 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 2571 2572 /* Reset TSF. */ 2573 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2574 2575 /* Reset EDCA parameters. */ 2576 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2577 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2578 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2579 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2580 } 2581 2582 switch (nstate) { 2583 case IEEE80211_S_INIT: 2584 /* Turn link LED off. */ 2585 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2586 break; 2587 case IEEE80211_S_SCAN: 2588 /* Pause AC Tx queues. */ 2589 urtwn_write_1(sc, R92C_TXPAUSE, 2590 urtwn_read_1(sc, R92C_TXPAUSE) | R92C_TX_QUEUE_AC); 2591 break; 2592 case IEEE80211_S_AUTH: 2593 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2594 break; 2595 case IEEE80211_S_RUN: 2596 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2597 /* Turn link LED on. */ 2598 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2599 break; 2600 } 2601 2602 ni = ieee80211_ref_node(vap->iv_bss); 2603 2604 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 2605 ni->ni_chan == IEEE80211_CHAN_ANYC) { 2606 device_printf(sc->sc_dev, 2607 "%s: could not move to RUN state\n", __func__); 2608 error = EINVAL; 2609 goto end_run; 2610 } 2611 2612 switch (vap->iv_opmode) { 2613 case IEEE80211_M_STA: 2614 mode = R92C_MSR_INFRA; 2615 break; 2616 case IEEE80211_M_IBSS: 2617 mode = R92C_MSR_ADHOC; 2618 break; 2619 case IEEE80211_M_HOSTAP: 2620 mode = R92C_MSR_AP; 2621 break; 2622 default: 2623 device_printf(sc->sc_dev, "undefined opmode %d\n", 2624 vap->iv_opmode); 2625 error = EINVAL; 2626 goto end_run; 2627 } 2628 2629 /* Set media status to 'Associated'. */ 2630 urtwn_set_mode(sc, mode); 2631 2632 /* Set BSSID. */ 2633 urtwn_write_4(sc, R92C_BSSID + 0, le32dec(&ni->ni_bssid[0])); 2634 urtwn_write_4(sc, R92C_BSSID + 4, le16dec(&ni->ni_bssid[4])); 2635 2636 if (ic->ic_curmode == IEEE80211_MODE_11B) 2637 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2638 else /* 802.11b/g */ 2639 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2640 2641 /* Enable Rx of data frames. */ 2642 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2643 2644 /* Flush all AC queues. */ 2645 urtwn_write_1(sc, R92C_TXPAUSE, 0); 2646 2647 /* Set beacon interval. */ 2648 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2649 2650 /* Allow Rx from our BSSID only. */ 2651 if (ic->ic_promisc == 0) { 2652 reg = urtwn_read_4(sc, R92C_RCR); 2653 2654 if (vap->iv_opmode != IEEE80211_M_HOSTAP) 2655 reg |= R92C_RCR_CBSSID_DATA; 2656 if (vap->iv_opmode != IEEE80211_M_IBSS) 2657 reg |= R92C_RCR_CBSSID_BCN; 2658 2659 urtwn_write_4(sc, R92C_RCR, reg); 2660 } 2661 2662 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 2663 vap->iv_opmode == IEEE80211_M_IBSS) { 2664 error = urtwn_setup_beacon(sc, ni); 2665 if (error != 0) { 2666 device_printf(sc->sc_dev, 2667 "unable to push beacon into the chip, " 2668 "error %d\n", error); 2669 goto end_run; 2670 } 2671 } 2672 2673 /* Enable TSF synchronization. */ 2674 urtwn_tsf_sync_enable(sc, vap); 2675 2676 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2677 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2678 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2679 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2680 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2681 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2682 2683 /* Intialize rate adaptation. */ 2684 if (!(sc->chip & URTWN_CHIP_88E)) 2685 urtwn_ra_init(sc); 2686 /* Turn link LED on. */ 2687 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2688 2689 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2690 /* Reset temperature calibration state machine. */ 2691 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 2692 sc->thcal_lctemp = 0; 2693 /* Start periodic calibration. */ 2694 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2695 2696 end_run: 2697 ieee80211_free_node(ni); 2698 break; 2699 default: 2700 break; 2701 } 2702 2703 URTWN_UNLOCK(sc); 2704 IEEE80211_LOCK(ic); 2705 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2706 } 2707 2708 static void 2709 urtwn_calib_to(void *arg) 2710 { 2711 struct urtwn_softc *sc = arg; 2712 2713 /* Do it in a process context. */ 2714 urtwn_cmd_sleepable(sc, NULL, 0, urtwn_calib_cb); 2715 } 2716 2717 static void 2718 urtwn_calib_cb(struct urtwn_softc *sc, union sec_param *data) 2719 { 2720 /* Do temperature compensation. */ 2721 urtwn_temp_calib(sc); 2722 2723 if ((urtwn_read_1(sc, R92C_MSR) & R92C_MSR_MASK) != R92C_MSR_NOLINK) 2724 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2725 } 2726 2727 static void 2728 urtwn_watchdog(void *arg) 2729 { 2730 struct urtwn_softc *sc = arg; 2731 2732 if (sc->sc_txtimer > 0) { 2733 if (--sc->sc_txtimer == 0) { 2734 device_printf(sc->sc_dev, "device timeout\n"); 2735 #if defined(__DragonFly__) 2736 /* unimplemented */ 2737 #else 2738 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2739 #endif 2740 return; 2741 } 2742 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2743 } 2744 } 2745 2746 static void 2747 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2748 { 2749 int pwdb; 2750 2751 /* Convert antenna signal to percentage. */ 2752 if (rssi <= -100 || rssi >= 20) 2753 pwdb = 0; 2754 else if (rssi >= 0) 2755 pwdb = 100; 2756 else 2757 pwdb = 100 + rssi; 2758 if (!(sc->chip & URTWN_CHIP_88E)) { 2759 if (rate <= URTWN_RIDX_CCK11) { 2760 /* CCK gain is smaller than OFDM/MCS gain. */ 2761 pwdb += 6; 2762 if (pwdb > 100) 2763 pwdb = 100; 2764 if (pwdb <= 14) 2765 pwdb -= 4; 2766 else if (pwdb <= 26) 2767 pwdb -= 8; 2768 else if (pwdb <= 34) 2769 pwdb -= 6; 2770 else if (pwdb <= 42) 2771 pwdb -= 2; 2772 } 2773 } 2774 if (sc->avg_pwdb == -1) /* Init. */ 2775 sc->avg_pwdb = pwdb; 2776 else if (sc->avg_pwdb < pwdb) 2777 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2778 else 2779 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2780 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: PWDB %d, EMA %d\n", __func__, 2781 pwdb, sc->avg_pwdb); 2782 } 2783 2784 static int8_t 2785 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2786 { 2787 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2788 struct r92c_rx_phystat *phy; 2789 struct r92c_rx_cck *cck; 2790 uint8_t rpt; 2791 int8_t rssi; 2792 2793 if (rate <= URTWN_RIDX_CCK11) { 2794 cck = (struct r92c_rx_cck *)physt; 2795 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2796 rpt = (cck->agc_rpt >> 5) & 0x3; 2797 rssi = (cck->agc_rpt & 0x1f) << 1; 2798 } else { 2799 rpt = (cck->agc_rpt >> 6) & 0x3; 2800 rssi = cck->agc_rpt & 0x3e; 2801 } 2802 rssi = cckoff[rpt] - rssi; 2803 } else { /* OFDM/HT. */ 2804 phy = (struct r92c_rx_phystat *)physt; 2805 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2806 } 2807 return (rssi); 2808 } 2809 2810 static int8_t 2811 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2812 { 2813 struct r92c_rx_phystat *phy; 2814 struct r88e_rx_cck *cck; 2815 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2816 int8_t rssi; 2817 2818 rssi = 0; 2819 if (rate <= URTWN_RIDX_CCK11) { 2820 cck = (struct r88e_rx_cck *)physt; 2821 cck_agc_rpt = cck->agc_rpt; 2822 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2823 vga_idx = cck_agc_rpt & 0x1f; 2824 switch (lna_idx) { 2825 case 7: 2826 if (vga_idx <= 27) 2827 rssi = -100 + 2* (27 - vga_idx); 2828 else 2829 rssi = -100; 2830 break; 2831 case 6: 2832 rssi = -48 + 2 * (2 - vga_idx); 2833 break; 2834 case 5: 2835 rssi = -42 + 2 * (7 - vga_idx); 2836 break; 2837 case 4: 2838 rssi = -36 + 2 * (7 - vga_idx); 2839 break; 2840 case 3: 2841 rssi = -24 + 2 * (7 - vga_idx); 2842 break; 2843 case 2: 2844 rssi = -12 + 2 * (5 - vga_idx); 2845 break; 2846 case 1: 2847 rssi = 8 - (2 * vga_idx); 2848 break; 2849 case 0: 2850 rssi = 14 - (2 * vga_idx); 2851 break; 2852 } 2853 rssi += 6; 2854 } else { /* OFDM/HT. */ 2855 phy = (struct r92c_rx_phystat *)physt; 2856 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2857 } 2858 return (rssi); 2859 } 2860 2861 static int 2862 urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2863 struct mbuf *m, struct urtwn_data *data) 2864 { 2865 const struct ieee80211_txparam *tp; 2866 struct ieee80211com *ic = &sc->sc_ic; 2867 struct ieee80211vap *vap = ni->ni_vap; 2868 struct ieee80211_key *k = NULL; 2869 struct ieee80211_channel *chan; 2870 struct ieee80211_frame *wh; 2871 struct r92c_tx_desc *txd; 2872 uint8_t macid, raid, rate, ridx, subtype, type, tid, qsel; 2873 int hasqos, ismcast; 2874 2875 URTWN_ASSERT_LOCKED(sc); 2876 2877 /* 2878 * Software crypto. 2879 */ 2880 wh = mtod(m, struct ieee80211_frame *); 2881 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2882 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2883 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2884 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2885 2886 /* Select TX ring for this frame. */ 2887 if (hasqos) { 2888 tid = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2889 tid &= IEEE80211_QOS_TID; 2890 } else 2891 tid = 0; 2892 2893 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ? 2894 ni->ni_chan : ic->ic_curchan; 2895 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)]; 2896 2897 /* Choose a TX rate index. */ 2898 if (type == IEEE80211_FC0_TYPE_MGT) 2899 rate = tp->mgmtrate; 2900 else if (ismcast) 2901 rate = tp->mcastrate; 2902 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2903 rate = tp->ucastrate; 2904 else if (m->m_flags & M_EAPOL) 2905 rate = tp->mgmtrate; 2906 else { 2907 if (URTWN_CHIP_HAS_RATECTL(sc)) { 2908 /* XXX pass pktlen */ 2909 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2910 rate = ni->ni_txrate; 2911 } else { 2912 /* XXX TODO: drop the default rate for 11b/11g? */ 2913 if (ni->ni_flags & IEEE80211_NODE_HT) 2914 rate = IEEE80211_RATE_MCS | 0x4; /* MCS4 */ 2915 else if (ic->ic_curmode != IEEE80211_MODE_11B) 2916 rate = 108; 2917 else 2918 rate = 22; 2919 } 2920 } 2921 2922 /* 2923 * XXX TODO: this should be per-node, for 11b versus 11bg 2924 * nodes in hostap mode 2925 */ 2926 ridx = rate2ridx(rate); 2927 if (ni->ni_flags & IEEE80211_NODE_HT) 2928 raid = R92C_RAID_11GN; 2929 else if (ic->ic_curmode != IEEE80211_MODE_11B) 2930 raid = R92C_RAID_11BG; 2931 else 2932 raid = R92C_RAID_11B; 2933 2934 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2935 k = ieee80211_crypto_encap(ni, m); 2936 if (k == NULL) { 2937 device_printf(sc->sc_dev, 2938 "ieee80211_crypto_encap returns NULL.\n"); 2939 return (ENOBUFS); 2940 } 2941 2942 /* in case packet header moved, reset pointer */ 2943 wh = mtod(m, struct ieee80211_frame *); 2944 } 2945 2946 /* Fill Tx descriptor. */ 2947 txd = (struct r92c_tx_desc *)data->buf; 2948 memset(txd, 0, sizeof(*txd)); 2949 2950 txd->txdw0 |= htole32( 2951 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2952 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2953 if (ismcast) 2954 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2955 2956 if (!ismcast) { 2957 if (sc->chip & URTWN_CHIP_88E) { 2958 struct urtwn_node *un = URTWN_NODE(ni); 2959 macid = un->id; 2960 } else 2961 macid = URTWN_MACID_BSS; 2962 2963 if (type == IEEE80211_FC0_TYPE_DATA) { 2964 qsel = tid % URTWN_MAX_TID; 2965 2966 if (sc->chip & URTWN_CHIP_88E) { 2967 txd->txdw2 |= htole32( 2968 R88E_TXDW2_AGGBK | 2969 R88E_TXDW2_CCX_RPT); 2970 } else 2971 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2972 2973 /* protmode, non-HT */ 2974 /* XXX TODO: noack frames? */ 2975 if ((rate & 0x80) == 0 && 2976 (ic->ic_flags & IEEE80211_F_USEPROT)) { 2977 switch (ic->ic_protmode) { 2978 case IEEE80211_PROT_CTSONLY: 2979 txd->txdw4 |= htole32( 2980 R92C_TXDW4_CTS2SELF | 2981 R92C_TXDW4_HWRTSEN); 2982 break; 2983 case IEEE80211_PROT_RTSCTS: 2984 txd->txdw4 |= htole32( 2985 R92C_TXDW4_RTSEN | 2986 R92C_TXDW4_HWRTSEN); 2987 break; 2988 default: 2989 break; 2990 } 2991 } 2992 2993 /* protmode, HT */ 2994 /* XXX TODO: noack frames? */ 2995 if ((rate & 0x80) && 2996 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) { 2997 txd->txdw4 |= htole32( 2998 R92C_TXDW4_RTSEN | 2999 R92C_TXDW4_HWRTSEN); 3000 } 3001 3002 /* XXX TODO: rtsrate is configurable? 24mbit may 3003 * be a bit high for RTS rate? */ 3004 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 3005 URTWN_RIDX_OFDM24)); 3006 3007 txd->txdw5 |= htole32(0x0001ff00); 3008 } else /* IEEE80211_FC0_TYPE_MGT */ 3009 qsel = R92C_TXDW1_QSEL_MGNT; 3010 } else { 3011 macid = URTWN_MACID_BC; 3012 qsel = R92C_TXDW1_QSEL_MGNT; 3013 } 3014 3015 txd->txdw1 |= htole32( 3016 SM(R92C_TXDW1_QSEL, qsel) | 3017 SM(R92C_TXDW1_RAID, raid)); 3018 3019 /* XXX TODO: 40MHZ flag? */ 3020 /* XXX TODO: AMPDU flag? (AGG_ENABLE or AGG_BREAK?) Density shift? */ 3021 /* XXX Short preamble? */ 3022 /* XXX Short-GI? */ 3023 3024 if (sc->chip & URTWN_CHIP_88E) 3025 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 3026 else 3027 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 3028 3029 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 3030 3031 /* Force this rate if needed. */ 3032 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast || 3033 (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) || 3034 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 3035 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3036 3037 if (!hasqos) { 3038 /* Use HW sequence numbering for non-QoS frames. */ 3039 if (sc->chip & URTWN_CHIP_88E) 3040 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 3041 else 3042 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 3043 } else { 3044 /* Set sequence number. */ 3045 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 3046 } 3047 3048 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 3049 uint8_t cipher; 3050 3051 switch (k->wk_cipher->ic_cipher) { 3052 case IEEE80211_CIPHER_WEP: 3053 case IEEE80211_CIPHER_TKIP: 3054 cipher = R92C_TXDW1_CIPHER_RC4; 3055 break; 3056 case IEEE80211_CIPHER_AES_CCM: 3057 cipher = R92C_TXDW1_CIPHER_AES; 3058 break; 3059 default: 3060 device_printf(sc->sc_dev, "%s: unknown cipher %d\n", 3061 __func__, k->wk_cipher->ic_cipher); 3062 return (EINVAL); 3063 } 3064 3065 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 3066 } 3067 3068 if (ieee80211_radiotap_active_vap(vap)) { 3069 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3070 3071 tap->wt_flags = 0; 3072 if (k != NULL) 3073 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3074 ieee80211_radiotap_tx(vap, m); 3075 } 3076 3077 data->ni = ni; 3078 3079 urtwn_tx_start(sc, m, type, data); 3080 3081 return (0); 3082 } 3083 3084 static int 3085 urtwn_tx_raw(struct urtwn_softc *sc, struct ieee80211_node *ni, 3086 struct mbuf *m, struct urtwn_data *data, 3087 const struct ieee80211_bpf_params *params) 3088 { 3089 struct ieee80211vap *vap = ni->ni_vap; 3090 struct ieee80211_key *k = NULL; 3091 struct ieee80211_frame *wh; 3092 struct r92c_tx_desc *txd; 3093 uint8_t cipher, ridx, type; 3094 3095 /* Encrypt the frame if need be. */ 3096 cipher = R92C_TXDW1_CIPHER_NONE; 3097 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) { 3098 /* Retrieve key for TX. */ 3099 k = ieee80211_crypto_encap(ni, m); 3100 if (k == NULL) 3101 return (ENOBUFS); 3102 3103 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 3104 switch (k->wk_cipher->ic_cipher) { 3105 case IEEE80211_CIPHER_WEP: 3106 case IEEE80211_CIPHER_TKIP: 3107 cipher = R92C_TXDW1_CIPHER_RC4; 3108 break; 3109 case IEEE80211_CIPHER_AES_CCM: 3110 cipher = R92C_TXDW1_CIPHER_AES; 3111 break; 3112 default: 3113 device_printf(sc->sc_dev, 3114 "%s: unknown cipher %d\n", 3115 __func__, k->wk_cipher->ic_cipher); 3116 return (EINVAL); 3117 } 3118 } 3119 } 3120 3121 /* XXX TODO: 11n checks, matching urtwn_tx_data() */ 3122 3123 wh = mtod(m, struct ieee80211_frame *); 3124 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3125 3126 /* Fill Tx descriptor. */ 3127 txd = (struct r92c_tx_desc *)data->buf; 3128 memset(txd, 0, sizeof(*txd)); 3129 3130 txd->txdw0 |= htole32( 3131 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 3132 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 3133 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3134 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 3135 3136 if (params->ibp_flags & IEEE80211_BPF_RTS) 3137 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN); 3138 if (params->ibp_flags & IEEE80211_BPF_CTS) 3139 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF); 3140 if (txd->txdw4 & htole32(R92C_TXDW4_RTSEN | R92C_TXDW4_CTS2SELF)) { 3141 txd->txdw4 |= htole32(R92C_TXDW4_HWRTSEN); 3142 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 3143 URTWN_RIDX_OFDM24)); 3144 } 3145 3146 if (sc->chip & URTWN_CHIP_88E) 3147 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 3148 else 3149 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 3150 3151 /* XXX TODO: rate index/config (RAID) for 11n? */ 3152 txd->txdw1 |= htole32(SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT)); 3153 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 3154 3155 /* Choose a TX rate index. */ 3156 ridx = rate2ridx(params->ibp_rate0); 3157 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 3158 txd->txdw5 |= htole32(0x0001ff00); 3159 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3160 3161 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 3162 /* Use HW sequence numbering for non-QoS frames. */ 3163 if (sc->chip & URTWN_CHIP_88E) 3164 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 3165 else 3166 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 3167 } else { 3168 /* Set sequence number. */ 3169 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 3170 } 3171 3172 if (ieee80211_radiotap_active_vap(vap)) { 3173 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3174 3175 tap->wt_flags = 0; 3176 if (k != NULL) 3177 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3178 ieee80211_radiotap_tx(vap, m); 3179 } 3180 3181 data->ni = ni; 3182 3183 urtwn_tx_start(sc, m, type, data); 3184 3185 return (0); 3186 } 3187 3188 static void 3189 urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 3190 struct urtwn_data *data) 3191 { 3192 struct usb_xfer *xfer; 3193 struct r92c_tx_desc *txd; 3194 uint16_t ac, sum; 3195 int i, xferlen; 3196 3197 URTWN_ASSERT_LOCKED(sc); 3198 3199 ac = M_WME_GETAC(m); 3200 3201 switch (type) { 3202 case IEEE80211_FC0_TYPE_CTL: 3203 case IEEE80211_FC0_TYPE_MGT: 3204 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 3205 break; 3206 default: 3207 xfer = sc->sc_xfer[wme2queue[ac].qid]; 3208 break; 3209 } 3210 3211 txd = (struct r92c_tx_desc *)data->buf; 3212 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 3213 3214 /* Compute Tx descriptor checksum. */ 3215 sum = 0; 3216 for (i = 0; i < sizeof(*txd) / 2; i++) 3217 sum ^= ((uint16_t *)txd)[i]; 3218 txd->txdsum = sum; /* NB: already little endian. */ 3219 3220 xferlen = sizeof(*txd) + m->m_pkthdr.len; 3221 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 3222 3223 data->buflen = xferlen; 3224 data->m = m; 3225 3226 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 3227 usbd_transfer_start(xfer); 3228 } 3229 3230 static int 3231 urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 3232 { 3233 struct urtwn_softc *sc = ic->ic_softc; 3234 int error; 3235 3236 URTWN_LOCK(sc); 3237 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 3238 URTWN_UNLOCK(sc); 3239 return (ENXIO); 3240 } 3241 error = mbufq_enqueue(&sc->sc_snd, m); 3242 if (error) { 3243 URTWN_UNLOCK(sc); 3244 return (error); 3245 } 3246 urtwn_start(sc); 3247 URTWN_UNLOCK(sc); 3248 3249 return (0); 3250 } 3251 3252 static void 3253 urtwn_start(struct urtwn_softc *sc) 3254 { 3255 struct ieee80211_node *ni; 3256 struct mbuf *m; 3257 struct urtwn_data *bf; 3258 3259 URTWN_ASSERT_LOCKED(sc); 3260 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 3261 bf = urtwn_getbuf(sc); 3262 if (bf == NULL) { 3263 mbufq_prepend(&sc->sc_snd, m); 3264 break; 3265 } 3266 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3267 m->m_pkthdr.rcvif = NULL; 3268 3269 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n", 3270 __func__, 3271 m); 3272 3273 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 3274 if_inc_counter(ni->ni_vap->iv_ifp, 3275 IFCOUNTER_OERRORS, 1); 3276 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3277 m_freem(m); 3278 ieee80211_free_node(ni); 3279 break; 3280 } 3281 sc->sc_txtimer = 5; 3282 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3283 } 3284 } 3285 3286 static void 3287 urtwn_parent(struct ieee80211com *ic) 3288 { 3289 struct urtwn_softc *sc = ic->ic_softc; 3290 3291 URTWN_LOCK(sc); 3292 if (sc->sc_flags & URTWN_DETACHED) { 3293 URTWN_UNLOCK(sc); 3294 return; 3295 } 3296 URTWN_UNLOCK(sc); 3297 3298 if (ic->ic_nrunning > 0) { 3299 if (urtwn_init(sc) != 0) { 3300 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3301 if (vap != NULL) 3302 ieee80211_stop(vap); 3303 } else 3304 ieee80211_start_all(ic); 3305 } else 3306 urtwn_stop(sc); 3307 } 3308 3309 static __inline int 3310 urtwn_power_on(struct urtwn_softc *sc) 3311 { 3312 3313 return sc->sc_power_on(sc); 3314 } 3315 3316 static int 3317 urtwn_r92c_power_on(struct urtwn_softc *sc) 3318 { 3319 uint32_t reg; 3320 usb_error_t error; 3321 int ntries; 3322 3323 /* Wait for autoload done bit. */ 3324 for (ntries = 0; ntries < 1000; ntries++) { 3325 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3326 break; 3327 urtwn_ms_delay(sc); 3328 } 3329 if (ntries == 1000) { 3330 device_printf(sc->sc_dev, 3331 "timeout waiting for chip autoload\n"); 3332 return (ETIMEDOUT); 3333 } 3334 3335 /* Unlock ISO/CLK/Power control register. */ 3336 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3337 if (error != USB_ERR_NORMAL_COMPLETION) 3338 return (EIO); 3339 /* Move SPS into PWM mode. */ 3340 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3341 if (error != USB_ERR_NORMAL_COMPLETION) 3342 return (EIO); 3343 urtwn_ms_delay(sc); 3344 3345 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3346 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3347 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3348 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3349 if (error != USB_ERR_NORMAL_COMPLETION) 3350 return (EIO); 3351 urtwn_ms_delay(sc); 3352 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3353 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3354 ~R92C_SYS_ISO_CTRL_MD2PP); 3355 if (error != USB_ERR_NORMAL_COMPLETION) 3356 return (EIO); 3357 } 3358 3359 /* Auto enable WLAN. */ 3360 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3361 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3362 if (error != USB_ERR_NORMAL_COMPLETION) 3363 return (EIO); 3364 for (ntries = 0; ntries < 1000; ntries++) { 3365 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3366 R92C_APS_FSMCO_APFM_ONMAC)) 3367 break; 3368 urtwn_ms_delay(sc); 3369 } 3370 if (ntries == 1000) { 3371 device_printf(sc->sc_dev, 3372 "timeout waiting for MAC auto ON\n"); 3373 return (ETIMEDOUT); 3374 } 3375 3376 /* Enable radio, GPIO and LED functions. */ 3377 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3378 R92C_APS_FSMCO_AFSM_HSUS | 3379 R92C_APS_FSMCO_PDN_EN | 3380 R92C_APS_FSMCO_PFM_ALDN); 3381 if (error != USB_ERR_NORMAL_COMPLETION) 3382 return (EIO); 3383 /* Release RF digital isolation. */ 3384 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3385 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3386 if (error != USB_ERR_NORMAL_COMPLETION) 3387 return (EIO); 3388 3389 /* Initialize MAC. */ 3390 error = urtwn_write_1(sc, R92C_APSD_CTRL, 3391 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3392 if (error != USB_ERR_NORMAL_COMPLETION) 3393 return (EIO); 3394 for (ntries = 0; ntries < 200; ntries++) { 3395 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3396 R92C_APSD_CTRL_OFF_STATUS)) 3397 break; 3398 urtwn_ms_delay(sc); 3399 } 3400 if (ntries == 200) { 3401 device_printf(sc->sc_dev, 3402 "timeout waiting for MAC initialization\n"); 3403 return (ETIMEDOUT); 3404 } 3405 3406 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3407 reg = urtwn_read_2(sc, R92C_CR); 3408 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3409 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3410 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3411 R92C_CR_ENSEC; 3412 error = urtwn_write_2(sc, R92C_CR, reg); 3413 if (error != USB_ERR_NORMAL_COMPLETION) 3414 return (EIO); 3415 3416 error = urtwn_write_1(sc, 0xfe10, 0x19); 3417 if (error != USB_ERR_NORMAL_COMPLETION) 3418 return (EIO); 3419 return (0); 3420 } 3421 3422 static int 3423 urtwn_r88e_power_on(struct urtwn_softc *sc) 3424 { 3425 uint32_t reg; 3426 usb_error_t error; 3427 int ntries; 3428 3429 /* Wait for power ready bit. */ 3430 for (ntries = 0; ntries < 5000; ntries++) { 3431 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 3432 break; 3433 urtwn_ms_delay(sc); 3434 } 3435 if (ntries == 5000) { 3436 device_printf(sc->sc_dev, 3437 "timeout waiting for chip power up\n"); 3438 return (ETIMEDOUT); 3439 } 3440 3441 /* Reset BB. */ 3442 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3443 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3444 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3445 if (error != USB_ERR_NORMAL_COMPLETION) 3446 return (EIO); 3447 3448 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3449 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3450 if (error != USB_ERR_NORMAL_COMPLETION) 3451 return (EIO); 3452 3453 /* Disable HWPDN. */ 3454 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3455 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3456 if (error != USB_ERR_NORMAL_COMPLETION) 3457 return (EIO); 3458 3459 /* Disable WL suspend. */ 3460 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3461 urtwn_read_2(sc, R92C_APS_FSMCO) & 3462 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 3463 if (error != USB_ERR_NORMAL_COMPLETION) 3464 return (EIO); 3465 3466 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3467 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3468 if (error != USB_ERR_NORMAL_COMPLETION) 3469 return (EIO); 3470 for (ntries = 0; ntries < 5000; ntries++) { 3471 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3472 R92C_APS_FSMCO_APFM_ONMAC)) 3473 break; 3474 urtwn_ms_delay(sc); 3475 } 3476 if (ntries == 5000) 3477 return (ETIMEDOUT); 3478 3479 /* Enable LDO normal mode. */ 3480 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 3481 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~R92C_LPLDO_CTRL_SLEEP); 3482 if (error != USB_ERR_NORMAL_COMPLETION) 3483 return (EIO); 3484 3485 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3486 error = urtwn_write_2(sc, R92C_CR, 0); 3487 if (error != USB_ERR_NORMAL_COMPLETION) 3488 return (EIO); 3489 reg = urtwn_read_2(sc, R92C_CR); 3490 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3491 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3492 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3493 error = urtwn_write_2(sc, R92C_CR, reg); 3494 if (error != USB_ERR_NORMAL_COMPLETION) 3495 return (EIO); 3496 3497 return (0); 3498 } 3499 3500 static __inline void 3501 urtwn_power_off(struct urtwn_softc *sc) 3502 { 3503 3504 return sc->sc_power_off(sc); 3505 } 3506 3507 static void 3508 urtwn_r92c_power_off(struct urtwn_softc *sc) 3509 { 3510 uint32_t reg; 3511 3512 /* Block all Tx queues. */ 3513 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3514 3515 /* Disable RF */ 3516 urtwn_rf_write(sc, 0, 0, 0); 3517 3518 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 3519 3520 /* Reset BB state machine */ 3521 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3522 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA | 3523 R92C_SYS_FUNC_EN_BB_GLB_RST); 3524 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3525 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 3526 3527 /* 3528 * Reset digital sequence 3529 */ 3530 #ifndef URTWN_WITHOUT_UCODE 3531 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 3532 /* Reset MCU ready status */ 3533 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3534 3535 /* If firmware in ram code, do reset */ 3536 urtwn_fw_reset(sc); 3537 } 3538 #endif 3539 3540 /* Reset MAC and Enable 8051 */ 3541 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 3542 (R92C_SYS_FUNC_EN_CPUEN | 3543 R92C_SYS_FUNC_EN_ELDR | 3544 R92C_SYS_FUNC_EN_HWPDN) >> 8); 3545 3546 /* Reset MCU ready status */ 3547 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3548 3549 /* Disable MAC clock */ 3550 urtwn_write_2(sc, R92C_SYS_CLKR, 3551 R92C_SYS_CLKR_ANAD16V_EN | 3552 R92C_SYS_CLKR_ANA8M | 3553 R92C_SYS_CLKR_LOADER_EN | 3554 R92C_SYS_CLKR_80M_SSC_DIS | 3555 R92C_SYS_CLKR_SYS_EN | 3556 R92C_SYS_CLKR_RING_EN | 3557 0x4000); 3558 3559 /* Disable AFE PLL */ 3560 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 3561 3562 /* Gated AFE DIG_CLOCK */ 3563 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 3564 3565 /* Isolated digital to PON */ 3566 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3567 R92C_SYS_ISO_CTRL_MD2PP | 3568 R92C_SYS_ISO_CTRL_PA2PCIE | 3569 R92C_SYS_ISO_CTRL_PD2CORE | 3570 R92C_SYS_ISO_CTRL_IP2MAC | 3571 R92C_SYS_ISO_CTRL_DIOP | 3572 R92C_SYS_ISO_CTRL_DIOE); 3573 3574 /* 3575 * Pull GPIO PIN to balance level and LED control 3576 */ 3577 /* 1. Disable GPIO[7:0] */ 3578 urtwn_write_2(sc, R92C_GPIO_IOSEL, 0x0000); 3579 3580 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 3581 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 3582 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 3583 3584 /* Disable GPIO[10:8] */ 3585 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x00); 3586 3587 reg = urtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0; 3588 reg |= (((reg & 0x000f) << 4) | 0x0780); 3589 urtwn_write_2(sc, R92C_GPIO_IO_SEL, reg); 3590 3591 /* Disable LED0 & 1 */ 3592 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 3593 3594 /* 3595 * Reset digital sequence 3596 */ 3597 /* Disable ELDR clock */ 3598 urtwn_write_2(sc, R92C_SYS_CLKR, 3599 R92C_SYS_CLKR_ANAD16V_EN | 3600 R92C_SYS_CLKR_ANA8M | 3601 R92C_SYS_CLKR_LOADER_EN | 3602 R92C_SYS_CLKR_80M_SSC_DIS | 3603 R92C_SYS_CLKR_SYS_EN | 3604 R92C_SYS_CLKR_RING_EN | 3605 0x4000); 3606 3607 /* Isolated ELDR to PON */ 3608 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 3609 (R92C_SYS_ISO_CTRL_DIOR | 3610 R92C_SYS_ISO_CTRL_PWC_EV12V) >> 8); 3611 3612 /* 3613 * Disable analog sequence 3614 */ 3615 /* Disable A15 power */ 3616 urtwn_write_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_OBUF); 3617 /* Disable digital core power */ 3618 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3619 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 3620 ~R92C_LDOV12D_CTRL_LDV12_EN); 3621 3622 /* Enter PFM mode */ 3623 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 3624 3625 /* Set USB suspend */ 3626 urtwn_write_2(sc, R92C_APS_FSMCO, 3627 R92C_APS_FSMCO_APDM_HOST | 3628 R92C_APS_FSMCO_AFSM_HSUS | 3629 R92C_APS_FSMCO_PFM_ALDN); 3630 3631 /* Lock ISO/CLK/Power control register. */ 3632 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 3633 } 3634 3635 static void 3636 urtwn_r88e_power_off(struct urtwn_softc *sc) 3637 { 3638 uint8_t reg; 3639 int ntries; 3640 3641 /* Disable any kind of TX reports. */ 3642 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 3643 urtwn_read_1(sc, R88E_TX_RPT_CTRL) & 3644 ~(R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA)); 3645 3646 /* Stop Rx. */ 3647 urtwn_write_1(sc, R92C_CR, 0); 3648 3649 /* Move card to Low Power State. */ 3650 /* Block all Tx queues. */ 3651 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3652 3653 for (ntries = 0; ntries < 20; ntries++) { 3654 /* Should be zero if no packet is transmitting. */ 3655 if (urtwn_read_4(sc, R88E_SCH_TXCMD) == 0) 3656 break; 3657 3658 urtwn_ms_delay(sc); 3659 } 3660 if (ntries == 20) { 3661 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", 3662 __func__); 3663 return; 3664 } 3665 3666 /* CCK and OFDM are disabled, and clock are gated. */ 3667 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3668 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_BBRSTB); 3669 3670 urtwn_ms_delay(sc); 3671 3672 /* Reset MAC TRX */ 3673 urtwn_write_1(sc, R92C_CR, 3674 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3675 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | 3676 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN); 3677 3678 /* check if removed later */ 3679 urtwn_write_1(sc, R92C_CR + 1, 3680 urtwn_read_1(sc, R92C_CR + 1) & ~(R92C_CR_ENSEC >> 8)); 3681 3682 /* Respond TxOK to scheduler */ 3683 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 3684 urtwn_read_1(sc, R92C_DUAL_TSF_RST) | 0x20); 3685 3686 /* If firmware in ram code, do reset. */ 3687 #ifndef URTWN_WITHOUT_UCODE 3688 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) 3689 urtwn_r88e_fw_reset(sc); 3690 #endif 3691 3692 /* Reset MCU ready status. */ 3693 urtwn_write_1(sc, R92C_MCUFWDL, 0x00); 3694 3695 /* Disable 32k. */ 3696 urtwn_write_1(sc, R88E_32K_CTRL, 3697 urtwn_read_1(sc, R88E_32K_CTRL) & ~0x01); 3698 3699 /* Move card to Disabled state. */ 3700 /* Turn off RF. */ 3701 urtwn_write_1(sc, R92C_RF_CTRL, 0); 3702 3703 /* LDO Sleep mode. */ 3704 urtwn_write_1(sc, R92C_LPLDO_CTRL, 3705 urtwn_read_1(sc, R92C_LPLDO_CTRL) | R92C_LPLDO_CTRL_SLEEP); 3706 3707 /* Turn off MAC by HW state machine */ 3708 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3709 urtwn_read_1(sc, R92C_APS_FSMCO + 1) | 3710 (R92C_APS_FSMCO_APFM_OFF >> 8)); 3711 3712 for (ntries = 0; ntries < 20; ntries++) { 3713 /* Wait until it will be disabled. */ 3714 if ((urtwn_read_1(sc, R92C_APS_FSMCO + 1) & 3715 (R92C_APS_FSMCO_APFM_OFF >> 8)) == 0) 3716 break; 3717 3718 urtwn_ms_delay(sc); 3719 } 3720 if (ntries == 20) { 3721 device_printf(sc->sc_dev, "%s: could not turn off MAC\n", 3722 __func__); 3723 return; 3724 } 3725 3726 /* schmit trigger */ 3727 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3728 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3729 3730 /* Enable WL suspend. */ 3731 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3732 (urtwn_read_1(sc, R92C_APS_FSMCO + 1) & ~0x10) | 0x08); 3733 3734 /* Enable bandgap mbias in suspend. */ 3735 urtwn_write_1(sc, R92C_APS_FSMCO + 3, 0); 3736 3737 /* Clear SIC_EN register. */ 3738 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 1, 3739 urtwn_read_1(sc, R92C_GPIO_MUXCFG + 1) & ~0x10); 3740 3741 /* Set USB suspend enable local register */ 3742 urtwn_write_1(sc, R92C_USB_SUSPEND, 3743 urtwn_read_1(sc, R92C_USB_SUSPEND) | 0x10); 3744 3745 /* Reset MCU IO Wrapper. */ 3746 reg = urtwn_read_1(sc, R92C_RSV_CTRL + 1); 3747 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08); 3748 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08); 3749 3750 /* marked as 'For Power Consumption' code. */ 3751 urtwn_write_1(sc, R92C_GPIO_OUT, urtwn_read_1(sc, R92C_GPIO_IN)); 3752 urtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff); 3753 3754 urtwn_write_1(sc, R92C_GPIO_IO_SEL, 3755 urtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4); 3756 urtwn_write_1(sc, R92C_GPIO_MOD, 3757 urtwn_read_1(sc, R92C_GPIO_MOD) | 0x0f); 3758 3759 /* Set LNA, TRSW, EX_PA Pin to output mode. */ 3760 urtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808); 3761 } 3762 3763 static int 3764 urtwn_llt_init(struct urtwn_softc *sc) 3765 { 3766 int i, error, page_count, pktbuf_count; 3767 3768 page_count = (sc->chip & URTWN_CHIP_88E) ? 3769 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 3770 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 3771 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 3772 3773 /* Reserve pages [0; page_count]. */ 3774 for (i = 0; i < page_count; i++) { 3775 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3776 return (error); 3777 } 3778 /* NB: 0xff indicates end-of-list. */ 3779 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3780 return (error); 3781 /* 3782 * Use pages [page_count + 1; pktbuf_count - 1] 3783 * as ring buffer. 3784 */ 3785 for (++i; i < pktbuf_count - 1; i++) { 3786 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3787 return (error); 3788 } 3789 /* Make the last page point to the beginning of the ring buffer. */ 3790 error = urtwn_llt_write(sc, i, page_count + 1); 3791 return (error); 3792 } 3793 3794 #ifndef URTWN_WITHOUT_UCODE 3795 static void 3796 urtwn_fw_reset(struct urtwn_softc *sc) 3797 { 3798 uint16_t reg; 3799 int ntries; 3800 3801 /* Tell 8051 to reset itself. */ 3802 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3803 3804 /* Wait until 8051 resets by itself. */ 3805 for (ntries = 0; ntries < 100; ntries++) { 3806 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3807 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3808 return; 3809 urtwn_ms_delay(sc); 3810 } 3811 /* Force 8051 reset. */ 3812 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3813 } 3814 3815 static void 3816 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3817 { 3818 uint16_t reg; 3819 3820 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3821 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3822 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3823 } 3824 3825 static int 3826 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 3827 { 3828 uint32_t reg; 3829 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 3830 int off, mlen; 3831 3832 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3833 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3834 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3835 3836 off = R92C_FW_START_ADDR; 3837 while (len > 0) { 3838 if (len > 196) 3839 mlen = 196; 3840 else if (len > 4) 3841 mlen = 4; 3842 else 3843 mlen = 1; 3844 /* XXX fix this deconst */ 3845 error = urtwn_write_region_1(sc, off, 3846 __DECONST(uint8_t *, buf), mlen); 3847 if (error != USB_ERR_NORMAL_COMPLETION) 3848 break; 3849 off += mlen; 3850 buf += mlen; 3851 len -= mlen; 3852 } 3853 return (error); 3854 } 3855 3856 static int 3857 urtwn_load_firmware(struct urtwn_softc *sc) 3858 { 3859 const struct firmware *fw; 3860 const struct r92c_fw_hdr *hdr; 3861 const char *imagename; 3862 const u_char *ptr; 3863 size_t len; 3864 uint32_t reg; 3865 int mlen, ntries, page, error; 3866 3867 URTWN_UNLOCK(sc); 3868 /* Read firmware image from the filesystem. */ 3869 if (sc->chip & URTWN_CHIP_88E) 3870 imagename = "urtwn-rtl8188eufw"; 3871 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3872 URTWN_CHIP_UMC_A_CUT) 3873 imagename = "urtwn-rtl8192cfwU"; 3874 else 3875 imagename = "urtwn-rtl8192cfwT"; 3876 3877 fw = firmware_get(imagename); 3878 URTWN_LOCK(sc); 3879 if (fw == NULL) { 3880 device_printf(sc->sc_dev, 3881 "failed loadfirmware of file %s\n", imagename); 3882 return (ENOENT); 3883 } 3884 3885 len = fw->datasize; 3886 3887 if (len < sizeof(*hdr)) { 3888 device_printf(sc->sc_dev, "firmware too short\n"); 3889 error = EINVAL; 3890 goto fail; 3891 } 3892 ptr = fw->data; 3893 hdr = (const struct r92c_fw_hdr *)ptr; 3894 /* Check if there is a valid FW header and skip it. */ 3895 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3896 (le16toh(hdr->signature) >> 4) == 0x88e || 3897 (le16toh(hdr->signature) >> 4) == 0x92c) { 3898 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, 3899 "FW V%d.%d %02d-%02d %02d:%02d\n", 3900 le16toh(hdr->version), le16toh(hdr->subversion), 3901 hdr->month, hdr->date, hdr->hour, hdr->minute); 3902 ptr += sizeof(*hdr); 3903 len -= sizeof(*hdr); 3904 } 3905 3906 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3907 if (sc->chip & URTWN_CHIP_88E) 3908 urtwn_r88e_fw_reset(sc); 3909 else 3910 urtwn_fw_reset(sc); 3911 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3912 } 3913 3914 if (!(sc->chip & URTWN_CHIP_88E)) { 3915 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3916 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3917 R92C_SYS_FUNC_EN_CPUEN); 3918 } 3919 urtwn_write_1(sc, R92C_MCUFWDL, 3920 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3921 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3922 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3923 3924 /* Reset the FWDL checksum. */ 3925 urtwn_write_1(sc, R92C_MCUFWDL, 3926 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3927 3928 for (page = 0; len > 0; page++) { 3929 mlen = min(len, R92C_FW_PAGE_SIZE); 3930 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3931 if (error != 0) { 3932 device_printf(sc->sc_dev, 3933 "could not load firmware page\n"); 3934 goto fail; 3935 } 3936 ptr += mlen; 3937 len -= mlen; 3938 } 3939 urtwn_write_1(sc, R92C_MCUFWDL, 3940 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3941 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3942 3943 /* Wait for checksum report. */ 3944 for (ntries = 0; ntries < 1000; ntries++) { 3945 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3946 break; 3947 urtwn_ms_delay(sc); 3948 } 3949 if (ntries == 1000) { 3950 device_printf(sc->sc_dev, 3951 "timeout waiting for checksum report\n"); 3952 error = ETIMEDOUT; 3953 goto fail; 3954 } 3955 3956 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3957 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3958 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3959 if (sc->chip & URTWN_CHIP_88E) 3960 urtwn_r88e_fw_reset(sc); 3961 /* Wait for firmware readiness. */ 3962 for (ntries = 0; ntries < 1000; ntries++) { 3963 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3964 break; 3965 urtwn_ms_delay(sc); 3966 } 3967 if (ntries == 1000) { 3968 device_printf(sc->sc_dev, 3969 "timeout waiting for firmware readiness\n"); 3970 error = ETIMEDOUT; 3971 goto fail; 3972 } 3973 fail: 3974 firmware_put(fw, FIRMWARE_UNLOAD); 3975 return (error); 3976 } 3977 #endif 3978 3979 static int 3980 urtwn_dma_init(struct urtwn_softc *sc) 3981 { 3982 struct usb_endpoint *ep, *ep_end; 3983 usb_error_t usb_err; 3984 uint32_t reg; 3985 int hashq, hasnq, haslq, nqueues, ntx; 3986 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 3987 3988 /* Initialize LLT table. */ 3989 error = urtwn_llt_init(sc); 3990 if (error != 0) 3991 return (error); 3992 3993 /* Determine the number of bulk-out pipes. */ 3994 ntx = 0; 3995 ep = sc->sc_udev->endpoints; 3996 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 3997 for (; ep != ep_end; ep++) { 3998 if ((ep->edesc == NULL) || 3999 (ep->iface_index != sc->sc_iface_index)) 4000 continue; 4001 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 4002 ntx++; 4003 } 4004 if (ntx == 0) { 4005 device_printf(sc->sc_dev, 4006 "%d: invalid number of Tx bulk pipes\n", ntx); 4007 return (EIO); 4008 } 4009 4010 /* Get Tx queues to USB endpoints mapping. */ 4011 hashq = hasnq = haslq = nqueues = 0; 4012 switch (ntx) { 4013 case 1: hashq = 1; break; 4014 case 2: hashq = hasnq = 1; break; 4015 case 3: case 4: hashq = hasnq = haslq = 1; break; 4016 } 4017 nqueues = hashq + hasnq + haslq; 4018 if (nqueues == 0) 4019 return (EIO); 4020 4021 npubqpages = nqpages = nrempages = pagecount = 0; 4022 if (sc->chip & URTWN_CHIP_88E) 4023 tx_boundary = R88E_TX_PAGE_BOUNDARY; 4024 else { 4025 pagecount = R92C_TX_PAGE_COUNT; 4026 npubqpages = R92C_PUBQ_NPAGES; 4027 tx_boundary = R92C_TX_PAGE_BOUNDARY; 4028 } 4029 4030 /* Set number of pages for normal priority queue. */ 4031 if (sc->chip & URTWN_CHIP_88E) { 4032 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 4033 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4034 return (EIO); 4035 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 4036 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4037 return (EIO); 4038 } else { 4039 /* Get the number of pages for each queue. */ 4040 nqpages = (pagecount - npubqpages) / nqueues; 4041 /* 4042 * The remaining pages are assigned to the high priority 4043 * queue. 4044 */ 4045 nrempages = (pagecount - npubqpages) % nqueues; 4046 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 4047 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4048 return (EIO); 4049 usb_err = urtwn_write_4(sc, R92C_RQPN, 4050 /* Set number of pages for public queue. */ 4051 SM(R92C_RQPN_PUBQ, npubqpages) | 4052 /* Set number of pages for high priority queue. */ 4053 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 4054 /* Set number of pages for low priority queue. */ 4055 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 4056 /* Load values. */ 4057 R92C_RQPN_LD); 4058 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4059 return (EIO); 4060 } 4061 4062 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 4063 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4064 return (EIO); 4065 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 4066 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4067 return (EIO); 4068 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 4069 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4070 return (EIO); 4071 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 4072 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4073 return (EIO); 4074 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 4075 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4076 return (EIO); 4077 4078 /* Set queue to USB pipe mapping. */ 4079 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4080 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4081 if (nqueues == 1) { 4082 if (hashq) 4083 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 4084 else if (hasnq) 4085 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 4086 else 4087 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4088 } else if (nqueues == 2) { 4089 /* 4090 * All 2-endpoints configs have high and normal 4091 * priority queues. 4092 */ 4093 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4094 } else 4095 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4096 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4097 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4098 return (EIO); 4099 4100 /* Set Tx/Rx transfer page boundary. */ 4101 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 4102 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 4103 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4104 return (EIO); 4105 4106 /* Set Tx/Rx transfer page size. */ 4107 usb_err = urtwn_write_1(sc, R92C_PBP, 4108 SM(R92C_PBP_PSRX, R92C_PBP_128) | 4109 SM(R92C_PBP_PSTX, R92C_PBP_128)); 4110 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4111 return (EIO); 4112 4113 return (0); 4114 } 4115 4116 static int 4117 urtwn_mac_init(struct urtwn_softc *sc) 4118 { 4119 usb_error_t error; 4120 int i; 4121 4122 /* Write MAC initialization values. */ 4123 if (sc->chip & URTWN_CHIP_88E) { 4124 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 4125 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 4126 rtl8188eu_mac[i].val); 4127 if (error != USB_ERR_NORMAL_COMPLETION) 4128 return (EIO); 4129 } 4130 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 4131 } else { 4132 for (i = 0; i < nitems(rtl8192cu_mac); i++) { 4133 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 4134 rtl8192cu_mac[i].val); 4135 if (error != USB_ERR_NORMAL_COMPLETION) 4136 return (EIO); 4137 } 4138 } 4139 4140 return (0); 4141 } 4142 4143 static void 4144 urtwn_bb_init(struct urtwn_softc *sc) 4145 { 4146 const struct urtwn_bb_prog *prog; 4147 uint32_t reg; 4148 uint8_t crystalcap; 4149 int i; 4150 4151 /* Enable BB and RF. */ 4152 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4153 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4154 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 4155 R92C_SYS_FUNC_EN_DIO_RF); 4156 4157 if (!(sc->chip & URTWN_CHIP_88E)) 4158 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 4159 4160 urtwn_write_1(sc, R92C_RF_CTRL, 4161 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 4162 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4163 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 4164 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 4165 4166 if (!(sc->chip & URTWN_CHIP_88E)) { 4167 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 4168 urtwn_write_1(sc, 0x15, 0xe9); 4169 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 4170 } 4171 4172 /* Select BB programming based on board type. */ 4173 if (sc->chip & URTWN_CHIP_88E) 4174 prog = &rtl8188eu_bb_prog; 4175 else if (!(sc->chip & URTWN_CHIP_92C)) { 4176 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4177 prog = &rtl8188ce_bb_prog; 4178 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4179 prog = &rtl8188ru_bb_prog; 4180 else 4181 prog = &rtl8188cu_bb_prog; 4182 } else { 4183 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4184 prog = &rtl8192ce_bb_prog; 4185 else 4186 prog = &rtl8192cu_bb_prog; 4187 } 4188 /* Write BB initialization values. */ 4189 for (i = 0; i < prog->count; i++) { 4190 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 4191 urtwn_ms_delay(sc); 4192 } 4193 4194 if (sc->chip & URTWN_CHIP_92C_1T2R) { 4195 /* 8192C 1T only configuration. */ 4196 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 4197 reg = (reg & ~0x00000003) | 0x2; 4198 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 4199 4200 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 4201 reg = (reg & ~0x00300033) | 0x00200022; 4202 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 4203 4204 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 4205 reg = (reg & ~0xff000000) | 0x45 << 24; 4206 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 4207 4208 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4209 reg = (reg & ~0x000000ff) | 0x23; 4210 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 4211 4212 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 4213 reg = (reg & ~0x00000030) | 1 << 4; 4214 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 4215 4216 reg = urtwn_bb_read(sc, 0xe74); 4217 reg = (reg & ~0x0c000000) | 2 << 26; 4218 urtwn_bb_write(sc, 0xe74, reg); 4219 reg = urtwn_bb_read(sc, 0xe78); 4220 reg = (reg & ~0x0c000000) | 2 << 26; 4221 urtwn_bb_write(sc, 0xe78, reg); 4222 reg = urtwn_bb_read(sc, 0xe7c); 4223 reg = (reg & ~0x0c000000) | 2 << 26; 4224 urtwn_bb_write(sc, 0xe7c, reg); 4225 reg = urtwn_bb_read(sc, 0xe80); 4226 reg = (reg & ~0x0c000000) | 2 << 26; 4227 urtwn_bb_write(sc, 0xe80, reg); 4228 reg = urtwn_bb_read(sc, 0xe88); 4229 reg = (reg & ~0x0c000000) | 2 << 26; 4230 urtwn_bb_write(sc, 0xe88, reg); 4231 } 4232 4233 /* Write AGC values. */ 4234 for (i = 0; i < prog->agccount; i++) { 4235 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 4236 prog->agcvals[i]); 4237 urtwn_ms_delay(sc); 4238 } 4239 4240 if (sc->chip & URTWN_CHIP_88E) { 4241 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 4242 urtwn_ms_delay(sc); 4243 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 4244 urtwn_ms_delay(sc); 4245 4246 crystalcap = sc->rom.r88e_rom.crystalcap; 4247 if (crystalcap == 0xff) 4248 crystalcap = 0x20; 4249 crystalcap &= 0x3f; 4250 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 4251 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 4252 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4253 crystalcap | crystalcap << 6)); 4254 } else { 4255 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 4256 R92C_HSSI_PARAM2_CCK_HIPWR) 4257 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 4258 } 4259 } 4260 4261 static void 4262 urtwn_rf_init(struct urtwn_softc *sc) 4263 { 4264 const struct urtwn_rf_prog *prog; 4265 uint32_t reg, type; 4266 int i, j, idx, off; 4267 4268 /* Select RF programming based on board type. */ 4269 if (sc->chip & URTWN_CHIP_88E) 4270 prog = rtl8188eu_rf_prog; 4271 else if (!(sc->chip & URTWN_CHIP_92C)) { 4272 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4273 prog = rtl8188ce_rf_prog; 4274 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4275 prog = rtl8188ru_rf_prog; 4276 else 4277 prog = rtl8188cu_rf_prog; 4278 } else 4279 prog = rtl8192ce_rf_prog; 4280 4281 for (i = 0; i < sc->nrxchains; i++) { 4282 /* Save RF_ENV control type. */ 4283 idx = i / 2; 4284 off = (i % 2) * 16; 4285 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4286 type = (reg >> off) & 0x10; 4287 4288 /* Set RF_ENV enable. */ 4289 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4290 reg |= 0x100000; 4291 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4292 urtwn_ms_delay(sc); 4293 /* Set RF_ENV output high. */ 4294 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4295 reg |= 0x10; 4296 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4297 urtwn_ms_delay(sc); 4298 /* Set address and data lengths of RF registers. */ 4299 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4300 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4301 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4302 urtwn_ms_delay(sc); 4303 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4304 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4305 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4306 urtwn_ms_delay(sc); 4307 4308 /* Write RF initialization values for this chain. */ 4309 for (j = 0; j < prog[i].count; j++) { 4310 if (prog[i].regs[j] >= 0xf9 && 4311 prog[i].regs[j] <= 0xfe) { 4312 /* 4313 * These are fake RF registers offsets that 4314 * indicate a delay is required. 4315 */ 4316 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 4317 continue; 4318 } 4319 urtwn_rf_write(sc, i, prog[i].regs[j], 4320 prog[i].vals[j]); 4321 urtwn_ms_delay(sc); 4322 } 4323 4324 /* Restore RF_ENV control type. */ 4325 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4326 reg &= ~(0x10 << off) | (type << off); 4327 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 4328 4329 /* Cache RF register CHNLBW. */ 4330 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4331 } 4332 4333 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4334 URTWN_CHIP_UMC_A_CUT) { 4335 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4336 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4337 } 4338 } 4339 4340 static void 4341 urtwn_cam_init(struct urtwn_softc *sc) 4342 { 4343 /* Invalidate all CAM entries. */ 4344 urtwn_write_4(sc, R92C_CAMCMD, 4345 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4346 } 4347 4348 static int 4349 urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 4350 { 4351 usb_error_t error; 4352 4353 error = urtwn_write_4(sc, R92C_CAMWRITE, data); 4354 if (error != USB_ERR_NORMAL_COMPLETION) 4355 return (EIO); 4356 error = urtwn_write_4(sc, R92C_CAMCMD, 4357 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 4358 SM(R92C_CAMCMD_ADDR, addr)); 4359 if (error != USB_ERR_NORMAL_COMPLETION) 4360 return (EIO); 4361 4362 return (0); 4363 } 4364 4365 static void 4366 urtwn_pa_bias_init(struct urtwn_softc *sc) 4367 { 4368 uint8_t reg; 4369 int i; 4370 4371 for (i = 0; i < sc->nrxchains; i++) { 4372 if (sc->pa_setting & (1 << i)) 4373 continue; 4374 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4375 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4376 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4377 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4378 } 4379 if (!(sc->pa_setting & 0x10)) { 4380 reg = urtwn_read_1(sc, 0x16); 4381 reg = (reg & ~0xf0) | 0x90; 4382 urtwn_write_1(sc, 0x16, reg); 4383 } 4384 } 4385 4386 static void 4387 urtwn_rxfilter_init(struct urtwn_softc *sc) 4388 { 4389 struct ieee80211com *ic = &sc->sc_ic; 4390 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4391 uint32_t rcr; 4392 uint16_t filter; 4393 4394 URTWN_ASSERT_LOCKED(sc); 4395 4396 /* Setup multicast filter. */ 4397 urtwn_set_multi(sc); 4398 4399 /* Filter for management frames. */ 4400 filter = 0x7f3f; 4401 switch (vap->iv_opmode) { 4402 case IEEE80211_M_STA: 4403 filter &= ~( 4404 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 4405 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 4406 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 4407 break; 4408 case IEEE80211_M_HOSTAP: 4409 filter &= ~( 4410 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 4411 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP)); 4412 break; 4413 case IEEE80211_M_MONITOR: 4414 case IEEE80211_M_IBSS: 4415 break; 4416 default: 4417 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4418 __func__, vap->iv_opmode); 4419 break; 4420 } 4421 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 4422 4423 /* Reject all control frames. */ 4424 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4425 4426 /* Reject all data frames. */ 4427 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 4428 4429 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 4430 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 4431 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 4432 4433 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 4434 /* Accept all frames. */ 4435 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 4436 R92C_RCR_AAP; 4437 } 4438 4439 /* Set Rx filter. */ 4440 urtwn_write_4(sc, R92C_RCR, rcr); 4441 4442 if (ic->ic_promisc != 0) { 4443 /* Update Rx filter. */ 4444 urtwn_set_promisc(sc); 4445 } 4446 } 4447 4448 static void 4449 urtwn_edca_init(struct urtwn_softc *sc) 4450 { 4451 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4452 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4453 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4454 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4455 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4456 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4457 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4458 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4459 } 4460 4461 static void 4462 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4463 uint16_t power[URTWN_RIDX_COUNT]) 4464 { 4465 uint32_t reg; 4466 4467 /* Write per-CCK rate Tx power. */ 4468 if (chain == 0) { 4469 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4470 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4471 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4472 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4473 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4474 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4475 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4476 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4477 } else { 4478 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4479 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4480 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4481 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4482 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4483 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4484 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4485 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4486 } 4487 /* Write per-OFDM rate Tx power. */ 4488 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4489 SM(R92C_TXAGC_RATE06, power[ 4]) | 4490 SM(R92C_TXAGC_RATE09, power[ 5]) | 4491 SM(R92C_TXAGC_RATE12, power[ 6]) | 4492 SM(R92C_TXAGC_RATE18, power[ 7])); 4493 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4494 SM(R92C_TXAGC_RATE24, power[ 8]) | 4495 SM(R92C_TXAGC_RATE36, power[ 9]) | 4496 SM(R92C_TXAGC_RATE48, power[10]) | 4497 SM(R92C_TXAGC_RATE54, power[11])); 4498 /* Write per-MCS Tx power. */ 4499 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4500 SM(R92C_TXAGC_MCS00, power[12]) | 4501 SM(R92C_TXAGC_MCS01, power[13]) | 4502 SM(R92C_TXAGC_MCS02, power[14]) | 4503 SM(R92C_TXAGC_MCS03, power[15])); 4504 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4505 SM(R92C_TXAGC_MCS04, power[16]) | 4506 SM(R92C_TXAGC_MCS05, power[17]) | 4507 SM(R92C_TXAGC_MCS06, power[18]) | 4508 SM(R92C_TXAGC_MCS07, power[19])); 4509 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4510 SM(R92C_TXAGC_MCS08, power[20]) | 4511 SM(R92C_TXAGC_MCS09, power[21]) | 4512 SM(R92C_TXAGC_MCS10, power[22]) | 4513 SM(R92C_TXAGC_MCS11, power[23])); 4514 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4515 SM(R92C_TXAGC_MCS12, power[24]) | 4516 SM(R92C_TXAGC_MCS13, power[25]) | 4517 SM(R92C_TXAGC_MCS14, power[26]) | 4518 SM(R92C_TXAGC_MCS15, power[27])); 4519 } 4520 4521 static void 4522 urtwn_get_txpower(struct urtwn_softc *sc, int chain, 4523 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4524 uint16_t power[URTWN_RIDX_COUNT]) 4525 { 4526 struct ieee80211com *ic = &sc->sc_ic; 4527 struct r92c_rom *rom = &sc->rom.r92c_rom; 4528 uint16_t cckpow, ofdmpow, htpow, diff, max; 4529 const struct urtwn_txpwr *base; 4530 int ridx, chan, group; 4531 4532 /* Determine channel group. */ 4533 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4534 if (chan <= 3) 4535 group = 0; 4536 else if (chan <= 9) 4537 group = 1; 4538 else 4539 group = 2; 4540 4541 /* Get original Tx power based on board type and RF chain. */ 4542 if (!(sc->chip & URTWN_CHIP_92C)) { 4543 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4544 base = &rtl8188ru_txagc[chain]; 4545 else 4546 base = &rtl8192cu_txagc[chain]; 4547 } else 4548 base = &rtl8192cu_txagc[chain]; 4549 4550 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4551 if (sc->regulatory == 0) { 4552 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4553 power[ridx] = base->pwr[0][ridx]; 4554 } 4555 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4556 if (sc->regulatory == 3) { 4557 power[ridx] = base->pwr[0][ridx]; 4558 /* Apply vendor limits. */ 4559 if (extc != NULL) 4560 max = rom->ht40_max_pwr[group]; 4561 else 4562 max = rom->ht20_max_pwr[group]; 4563 max = (max >> (chain * 4)) & 0xf; 4564 if (power[ridx] > max) 4565 power[ridx] = max; 4566 } else if (sc->regulatory == 1) { 4567 if (extc == NULL) 4568 power[ridx] = base->pwr[group][ridx]; 4569 } else if (sc->regulatory != 2) 4570 power[ridx] = base->pwr[0][ridx]; 4571 } 4572 4573 /* Compute per-CCK rate Tx power. */ 4574 cckpow = rom->cck_tx_pwr[chain][group]; 4575 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4576 power[ridx] += cckpow; 4577 if (power[ridx] > R92C_MAX_TX_PWR) 4578 power[ridx] = R92C_MAX_TX_PWR; 4579 } 4580 4581 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4582 if (sc->ntxchains > 1) { 4583 /* Apply reduction for 2 spatial streams. */ 4584 diff = rom->ht40_2s_tx_pwr_diff[group]; 4585 diff = (diff >> (chain * 4)) & 0xf; 4586 htpow = (htpow > diff) ? htpow - diff : 0; 4587 } 4588 4589 /* Compute per-OFDM rate Tx power. */ 4590 diff = rom->ofdm_tx_pwr_diff[group]; 4591 diff = (diff >> (chain * 4)) & 0xf; 4592 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4593 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4594 power[ridx] += ofdmpow; 4595 if (power[ridx] > R92C_MAX_TX_PWR) 4596 power[ridx] = R92C_MAX_TX_PWR; 4597 } 4598 4599 /* Compute per-MCS Tx power. */ 4600 if (extc == NULL) { 4601 diff = rom->ht20_tx_pwr_diff[group]; 4602 diff = (diff >> (chain * 4)) & 0xf; 4603 htpow += diff; /* HT40->HT20 correction. */ 4604 } 4605 for (ridx = 12; ridx <= 27; ridx++) { 4606 power[ridx] += htpow; 4607 if (power[ridx] > R92C_MAX_TX_PWR) 4608 power[ridx] = R92C_MAX_TX_PWR; 4609 } 4610 #ifdef USB_DEBUG 4611 if (sc->sc_debug & URTWN_DEBUG_TXPWR) { 4612 /* Dump per-rate Tx power values. */ 4613 kprintf("Tx power for chain %d:\n", chain); 4614 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 4615 kprintf("Rate %d = %u\n", ridx, power[ridx]); 4616 } 4617 #endif 4618 } 4619 4620 static void 4621 urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 4622 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4623 uint16_t power[URTWN_RIDX_COUNT]) 4624 { 4625 struct ieee80211com *ic = &sc->sc_ic; 4626 struct r88e_rom *rom = &sc->rom.r88e_rom; 4627 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4628 const struct urtwn_r88e_txpwr *base; 4629 int ridx, chan, group; 4630 4631 /* Determine channel group. */ 4632 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4633 if (chan <= 2) 4634 group = 0; 4635 else if (chan <= 5) 4636 group = 1; 4637 else if (chan <= 8) 4638 group = 2; 4639 else if (chan <= 11) 4640 group = 3; 4641 else if (chan <= 13) 4642 group = 4; 4643 else 4644 group = 5; 4645 4646 /* Get original Tx power based on board type and RF chain. */ 4647 base = &rtl8188eu_txagc[chain]; 4648 4649 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4650 if (sc->regulatory == 0) { 4651 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4652 power[ridx] = base->pwr[0][ridx]; 4653 } 4654 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4655 if (sc->regulatory == 3) 4656 power[ridx] = base->pwr[0][ridx]; 4657 else if (sc->regulatory == 1) { 4658 if (extc == NULL) 4659 power[ridx] = base->pwr[group][ridx]; 4660 } else if (sc->regulatory != 2) 4661 power[ridx] = base->pwr[0][ridx]; 4662 } 4663 4664 /* Compute per-CCK rate Tx power. */ 4665 cckpow = rom->cck_tx_pwr[group]; 4666 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4667 power[ridx] += cckpow; 4668 if (power[ridx] > R92C_MAX_TX_PWR) 4669 power[ridx] = R92C_MAX_TX_PWR; 4670 } 4671 4672 htpow = rom->ht40_tx_pwr[group]; 4673 4674 /* Compute per-OFDM rate Tx power. */ 4675 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4676 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4677 power[ridx] += ofdmpow; 4678 if (power[ridx] > R92C_MAX_TX_PWR) 4679 power[ridx] = R92C_MAX_TX_PWR; 4680 } 4681 4682 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4683 for (ridx = 12; ridx <= 27; ridx++) { 4684 power[ridx] += bw20pow; 4685 if (power[ridx] > R92C_MAX_TX_PWR) 4686 power[ridx] = R92C_MAX_TX_PWR; 4687 } 4688 } 4689 4690 static void 4691 urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 4692 struct ieee80211_channel *extc) 4693 { 4694 uint16_t power[URTWN_RIDX_COUNT]; 4695 int i; 4696 4697 for (i = 0; i < sc->ntxchains; i++) { 4698 /* Compute per-rate Tx power values. */ 4699 if (sc->chip & URTWN_CHIP_88E) 4700 urtwn_r88e_get_txpower(sc, i, c, extc, power); 4701 else 4702 urtwn_get_txpower(sc, i, c, extc, power); 4703 /* Write per-rate Tx power values to hardware. */ 4704 urtwn_write_txpower(sc, i, power); 4705 } 4706 } 4707 4708 static void 4709 urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 4710 { 4711 uint32_t reg; 4712 4713 reg = urtwn_read_4(sc, R92C_RCR); 4714 if (enable) 4715 reg &= ~R92C_RCR_CBSSID_BCN; 4716 else 4717 reg |= R92C_RCR_CBSSID_BCN; 4718 urtwn_write_4(sc, R92C_RCR, reg); 4719 } 4720 4721 static void 4722 urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 4723 { 4724 uint32_t reg; 4725 4726 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 4727 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4728 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 4729 4730 if (!(sc->chip & URTWN_CHIP_88E)) { 4731 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 4732 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4733 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 4734 } 4735 } 4736 4737 static void 4738 urtwn_scan_start(struct ieee80211com *ic) 4739 { 4740 struct urtwn_softc *sc = ic->ic_softc; 4741 4742 URTWN_LOCK(sc); 4743 /* Receive beacons / probe responses from any BSSID. */ 4744 if (ic->ic_opmode != IEEE80211_M_IBSS) 4745 urtwn_set_rx_bssid_all(sc, 1); 4746 4747 /* Set gain for scanning. */ 4748 urtwn_set_gain(sc, 0x20); 4749 URTWN_UNLOCK(sc); 4750 } 4751 4752 static void 4753 urtwn_scan_end(struct ieee80211com *ic) 4754 { 4755 struct urtwn_softc *sc = ic->ic_softc; 4756 4757 URTWN_LOCK(sc); 4758 /* Restore limitations. */ 4759 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 4760 urtwn_set_rx_bssid_all(sc, 0); 4761 4762 /* Set gain under link. */ 4763 urtwn_set_gain(sc, 0x32); 4764 URTWN_UNLOCK(sc); 4765 } 4766 4767 static void 4768 urtwn_set_channel(struct ieee80211com *ic) 4769 { 4770 struct urtwn_softc *sc = ic->ic_softc; 4771 struct ieee80211_channel *c = ic->ic_curchan; 4772 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4773 4774 URTWN_LOCK(sc); 4775 if (vap->iv_state == IEEE80211_S_SCAN) { 4776 /* Make link LED blink during scan. */ 4777 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 4778 } 4779 urtwn_set_chan(sc, c, NULL); 4780 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 4781 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 4782 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 4783 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 4784 URTWN_UNLOCK(sc); 4785 } 4786 4787 static int 4788 urtwn_wme_update(struct ieee80211com *ic) 4789 { 4790 const struct wmeParams *wmep = 4791 ic->ic_wme.wme_chanParams.cap_wmeParams; 4792 struct urtwn_softc *sc = ic->ic_softc; 4793 uint8_t aifs, acm, slottime; 4794 int ac; 4795 4796 acm = 0; 4797 slottime = IEEE80211_GET_SLOTTIME(ic); 4798 4799 URTWN_LOCK(sc); 4800 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4801 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4802 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4803 urtwn_write_4(sc, wme2queue[ac].reg, 4804 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 4805 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 4806 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 4807 SM(R92C_EDCA_PARAM_AIFS, aifs)); 4808 if (ac != WME_AC_BE) 4809 acm |= wmep[ac].wmep_acm << ac; 4810 } 4811 4812 if (acm != 0) 4813 acm |= R92C_ACMHWCTRL_EN; 4814 urtwn_write_1(sc, R92C_ACMHWCTRL, 4815 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 4816 acm); 4817 4818 URTWN_UNLOCK(sc); 4819 4820 return 0; 4821 } 4822 4823 static void 4824 urtwn_update_slot(struct ieee80211com *ic) 4825 { 4826 urtwn_cmd_sleepable(ic->ic_softc, NULL, 0, urtwn_update_slot_cb); 4827 } 4828 4829 static void 4830 urtwn_update_slot_cb(struct urtwn_softc *sc, union sec_param *data) 4831 { 4832 struct ieee80211com *ic = &sc->sc_ic; 4833 uint8_t slottime; 4834 4835 slottime = IEEE80211_GET_SLOTTIME(ic); 4836 4837 URTWN_DPRINTF(sc, URTWN_DEBUG_ANY, "%s: setting slot time to %uus\n", 4838 __func__, slottime); 4839 4840 urtwn_write_1(sc, R92C_SLOT, slottime); 4841 urtwn_update_aifs(sc, slottime); 4842 } 4843 4844 static void 4845 urtwn_update_aifs(struct urtwn_softc *sc, uint8_t slottime) 4846 { 4847 const struct wmeParams *wmep = 4848 sc->sc_ic.ic_wme.wme_chanParams.cap_wmeParams; 4849 uint8_t aifs, ac; 4850 4851 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4852 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4853 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4854 urtwn_write_1(sc, wme2queue[ac].reg, aifs); 4855 } 4856 } 4857 4858 static uint8_t 4859 urtwn_get_multi_pos(const uint8_t maddr[]) 4860 { 4861 uint64_t mask = 0x00004d101df481b4; 4862 uint8_t pos = 0x27; /* initial value */ 4863 int i, j; 4864 4865 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 4866 for (j = (i == 0) ? 1 : 0; j < 8; j++) 4867 if ((maddr[i] >> j) & 1) 4868 pos ^= (mask >> (i * 8 + j - 1)); 4869 4870 pos &= 0x3f; 4871 4872 return (pos); 4873 } 4874 4875 static void 4876 urtwn_set_multi(struct urtwn_softc *sc) 4877 { 4878 struct ieee80211com *ic = &sc->sc_ic; 4879 uint32_t mfilt[2]; 4880 4881 URTWN_ASSERT_LOCKED(sc); 4882 4883 /* general structure was copied from ath(4). */ 4884 if (ic->ic_allmulti == 0) { 4885 struct ieee80211vap *vap; 4886 struct ifnet *ifp; 4887 struct ifmultiaddr *ifma; 4888 4889 /* 4890 * Merge multicast addresses to form the hardware filter. 4891 */ 4892 mfilt[0] = mfilt[1] = 0; 4893 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 4894 ifp = vap->iv_ifp; 4895 #if defined(__DragonFly__) 4896 /* XXX not implemented */ 4897 #else 4898 if_maddr_rlock(ifp); 4899 #endif 4900 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4901 caddr_t dl; 4902 uint8_t pos; 4903 4904 dl = LLADDR((struct sockaddr_dl *) 4905 ifma->ifma_addr); 4906 pos = urtwn_get_multi_pos(dl); 4907 4908 mfilt[pos / 32] |= (1 << (pos % 32)); 4909 } 4910 #if defined(__DragonFly__) 4911 /* XXX not implemented */ 4912 #else 4913 if_maddr_runlock(ifp); 4914 #endif 4915 } 4916 } else 4917 mfilt[0] = mfilt[1] = ~0; 4918 4919 4920 urtwn_write_4(sc, R92C_MAR + 0, mfilt[0]); 4921 urtwn_write_4(sc, R92C_MAR + 4, mfilt[1]); 4922 4923 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s: MC filter %08x:%08x\n", 4924 __func__, mfilt[0], mfilt[1]); 4925 } 4926 4927 static void 4928 urtwn_set_promisc(struct urtwn_softc *sc) 4929 { 4930 struct ieee80211com *ic = &sc->sc_ic; 4931 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4932 uint32_t rcr, mask1, mask2; 4933 4934 URTWN_ASSERT_LOCKED(sc); 4935 4936 if (vap->iv_opmode == IEEE80211_M_MONITOR) 4937 return; 4938 4939 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 4940 mask2 = R92C_RCR_APM; 4941 4942 if (vap->iv_state == IEEE80211_S_RUN) { 4943 switch (vap->iv_opmode) { 4944 case IEEE80211_M_STA: 4945 mask2 |= R92C_RCR_CBSSID_DATA; 4946 /* FALLTHROUGH */ 4947 case IEEE80211_M_HOSTAP: 4948 mask2 |= R92C_RCR_CBSSID_BCN; 4949 break; 4950 case IEEE80211_M_IBSS: 4951 mask2 |= R92C_RCR_CBSSID_DATA; 4952 break; 4953 default: 4954 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4955 __func__, vap->iv_opmode); 4956 return; 4957 } 4958 } 4959 4960 rcr = urtwn_read_4(sc, R92C_RCR); 4961 if (ic->ic_promisc == 0) 4962 rcr = (rcr & ~mask1) | mask2; 4963 else 4964 rcr = (rcr & ~mask2) | mask1; 4965 urtwn_write_4(sc, R92C_RCR, rcr); 4966 } 4967 4968 static void 4969 urtwn_update_promisc(struct ieee80211com *ic) 4970 { 4971 struct urtwn_softc *sc = ic->ic_softc; 4972 4973 URTWN_LOCK(sc); 4974 if (sc->sc_flags & URTWN_RUNNING) 4975 urtwn_set_promisc(sc); 4976 URTWN_UNLOCK(sc); 4977 } 4978 4979 static void 4980 urtwn_update_mcast(struct ieee80211com *ic) 4981 { 4982 struct urtwn_softc *sc = ic->ic_softc; 4983 4984 URTWN_LOCK(sc); 4985 if (sc->sc_flags & URTWN_RUNNING) 4986 urtwn_set_multi(sc); 4987 URTWN_UNLOCK(sc); 4988 } 4989 4990 static struct ieee80211_node * 4991 urtwn_node_alloc(struct ieee80211vap *vap, 4992 const uint8_t mac[IEEE80211_ADDR_LEN]) 4993 { 4994 struct urtwn_node *un; 4995 4996 un = kmalloc(sizeof (struct urtwn_node), M_80211_NODE, 4997 M_INTWAIT | M_ZERO); 4998 4999 if (un == NULL) 5000 return NULL; 5001 5002 un->id = URTWN_MACID_UNDEFINED; 5003 5004 return &un->ni; 5005 } 5006 5007 static void 5008 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 5009 { 5010 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 5011 struct urtwn_node *un = URTWN_NODE(ni); 5012 uint8_t id; 5013 5014 /* Only do this bit for R88E chips */ 5015 if (! (sc->chip & URTWN_CHIP_88E)) 5016 return; 5017 5018 if (!isnew) 5019 return; 5020 5021 URTWN_NT_LOCK(sc); 5022 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) { 5023 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) { 5024 un->id = id; 5025 sc->node_list[id] = ni; 5026 break; 5027 } 5028 } 5029 URTWN_NT_UNLOCK(sc); 5030 5031 if (id > URTWN_MACID_MAX(sc)) { 5032 device_printf(sc->sc_dev, "%s: node table is full\n", 5033 __func__); 5034 } 5035 } 5036 5037 static void 5038 urtwn_node_free(struct ieee80211_node *ni) 5039 { 5040 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 5041 struct urtwn_node *un = URTWN_NODE(ni); 5042 5043 URTWN_NT_LOCK(sc); 5044 if (un->id != URTWN_MACID_UNDEFINED) 5045 sc->node_list[un->id] = NULL; 5046 URTWN_NT_UNLOCK(sc); 5047 5048 sc->sc_node_free(ni); 5049 } 5050 5051 static void 5052 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 5053 struct ieee80211_channel *extc) 5054 { 5055 struct ieee80211com *ic = &sc->sc_ic; 5056 uint32_t reg; 5057 u_int chan; 5058 int i; 5059 5060 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 5061 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 5062 device_printf(sc->sc_dev, 5063 "%s: invalid channel %x\n", __func__, chan); 5064 return; 5065 } 5066 5067 /* Set Tx power for this new channel. */ 5068 urtwn_set_txpower(sc, c, extc); 5069 5070 for (i = 0; i < sc->nrxchains; i++) { 5071 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 5072 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 5073 } 5074 #ifndef IEEE80211_NO_HT 5075 if (extc != NULL) { 5076 /* Is secondary channel below or above primary? */ 5077 int prichlo = c->ic_freq < extc->ic_freq; 5078 5079 urtwn_write_1(sc, R92C_BWOPMODE, 5080 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 5081 5082 reg = urtwn_read_1(sc, R92C_RRSR + 2); 5083 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 5084 urtwn_write_1(sc, R92C_RRSR + 2, reg); 5085 5086 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5087 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 5088 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5089 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 5090 5091 /* Set CCK side band. */ 5092 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 5093 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 5094 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 5095 5096 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 5097 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 5098 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 5099 5100 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5101 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 5102 ~R92C_FPGA0_ANAPARAM2_CBW20); 5103 5104 reg = urtwn_bb_read(sc, 0x818); 5105 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 5106 urtwn_bb_write(sc, 0x818, reg); 5107 5108 /* Select 40MHz bandwidth. */ 5109 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5110 (sc->rf_chnlbw[0] & ~0xfff) | chan); 5111 } else 5112 #endif 5113 { 5114 urtwn_write_1(sc, R92C_BWOPMODE, 5115 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 5116 5117 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5118 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 5119 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5120 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 5121 5122 if (!(sc->chip & URTWN_CHIP_88E)) { 5123 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5124 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 5125 R92C_FPGA0_ANAPARAM2_CBW20); 5126 } 5127 5128 /* Select 20MHz bandwidth. */ 5129 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5130 (sc->rf_chnlbw[0] & ~0xfff) | chan | 5131 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 5132 R92C_RF_CHNLBW_BW20)); 5133 } 5134 } 5135 5136 static void 5137 urtwn_iq_calib(struct urtwn_softc *sc) 5138 { 5139 /* TODO */ 5140 } 5141 5142 static void 5143 urtwn_lc_calib(struct urtwn_softc *sc) 5144 { 5145 uint32_t rf_ac[2]; 5146 uint8_t txmode; 5147 int i; 5148 5149 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 5150 if ((txmode & 0x70) != 0) { 5151 /* Disable all continuous Tx. */ 5152 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 5153 5154 /* Set RF mode to standby mode. */ 5155 for (i = 0; i < sc->nrxchains; i++) { 5156 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 5157 urtwn_rf_write(sc, i, R92C_RF_AC, 5158 RW(rf_ac[i], R92C_RF_AC_MODE, 5159 R92C_RF_AC_MODE_STANDBY)); 5160 } 5161 } else { 5162 /* Block all Tx queues. */ 5163 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 5164 } 5165 /* Start calibration. */ 5166 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5167 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 5168 5169 /* Give calibration the time to complete. */ 5170 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 5171 5172 /* Restore configuration. */ 5173 if ((txmode & 0x70) != 0) { 5174 /* Restore Tx mode. */ 5175 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 5176 /* Restore RF mode. */ 5177 for (i = 0; i < sc->nrxchains; i++) 5178 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 5179 } else { 5180 /* Unblock all Tx queues. */ 5181 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 5182 } 5183 } 5184 5185 static void 5186 urtwn_temp_calib(struct urtwn_softc *sc) 5187 { 5188 uint8_t temp; 5189 5190 URTWN_ASSERT_LOCKED(sc); 5191 5192 if (!(sc->sc_flags & URTWN_TEMP_MEASURED)) { 5193 /* Start measuring temperature. */ 5194 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5195 "%s: start measuring temperature\n", __func__); 5196 if (sc->chip & URTWN_CHIP_88E) { 5197 urtwn_rf_write(sc, 0, R88E_RF_T_METER, 5198 R88E_RF_T_METER_START); 5199 } else { 5200 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 5201 R92C_RF_T_METER_START); 5202 } 5203 sc->sc_flags |= URTWN_TEMP_MEASURED; 5204 return; 5205 } 5206 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 5207 5208 /* Read measured temperature. */ 5209 if (sc->chip & URTWN_CHIP_88E) { 5210 temp = MS(urtwn_rf_read(sc, 0, R88E_RF_T_METER), 5211 R88E_RF_T_METER_VAL); 5212 } else { 5213 temp = MS(urtwn_rf_read(sc, 0, R92C_RF_T_METER), 5214 R92C_RF_T_METER_VAL); 5215 } 5216 if (temp == 0) { /* Read failed, skip. */ 5217 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5218 "%s: temperature read failed, skipping\n", __func__); 5219 return; 5220 } 5221 5222 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5223 "%s: temperature: previous %u, current %u\n", 5224 __func__, sc->thcal_lctemp, temp); 5225 5226 /* 5227 * Redo LC calibration if temperature changed significantly since 5228 * last calibration. 5229 */ 5230 if (sc->thcal_lctemp == 0) { 5231 /* First LC calibration is performed in urtwn_init(). */ 5232 sc->thcal_lctemp = temp; 5233 } else if (abs(temp - sc->thcal_lctemp) > 1) { 5234 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5235 "%s: LC calib triggered by temp: %u -> %u\n", 5236 __func__, sc->thcal_lctemp, temp); 5237 urtwn_lc_calib(sc); 5238 /* Record temperature of last LC calibration. */ 5239 sc->thcal_lctemp = temp; 5240 } 5241 } 5242 5243 static int 5244 urtwn_init(struct urtwn_softc *sc) 5245 { 5246 struct ieee80211com *ic = &sc->sc_ic; 5247 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5248 uint8_t macaddr[IEEE80211_ADDR_LEN]; 5249 uint32_t reg; 5250 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 5251 int error; 5252 5253 URTWN_LOCK(sc); 5254 if (sc->sc_flags & URTWN_RUNNING) { 5255 URTWN_UNLOCK(sc); 5256 return (0); 5257 } 5258 5259 /* Init firmware commands ring. */ 5260 sc->fwcur = 0; 5261 5262 /* Allocate Tx/Rx buffers. */ 5263 error = urtwn_alloc_rx_list(sc); 5264 if (error != 0) 5265 goto fail; 5266 5267 error = urtwn_alloc_tx_list(sc); 5268 if (error != 0) 5269 goto fail; 5270 5271 /* Power on adapter. */ 5272 error = urtwn_power_on(sc); 5273 if (error != 0) 5274 goto fail; 5275 5276 /* Initialize DMA. */ 5277 error = urtwn_dma_init(sc); 5278 if (error != 0) 5279 goto fail; 5280 5281 /* Set info size in Rx descriptors (in 64-bit words). */ 5282 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 5283 5284 /* Init interrupts. */ 5285 if (sc->chip & URTWN_CHIP_88E) { 5286 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 5287 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5288 goto fail; 5289 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 5290 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 5291 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5292 goto fail; 5293 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 5294 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 5295 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5296 goto fail; 5297 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5298 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5299 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 5300 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5301 goto fail; 5302 } else { 5303 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 5304 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5305 goto fail; 5306 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 5307 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5308 goto fail; 5309 } 5310 5311 /* Set MAC address. */ 5312 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 5313 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 5314 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5315 goto fail; 5316 5317 /* Set initial network type. */ 5318 urtwn_set_mode(sc, R92C_MSR_INFRA); 5319 5320 /* Initialize Rx filter. */ 5321 urtwn_rxfilter_init(sc); 5322 5323 /* Set response rate. */ 5324 reg = urtwn_read_4(sc, R92C_RRSR); 5325 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 5326 urtwn_write_4(sc, R92C_RRSR, reg); 5327 5328 /* Set short/long retry limits. */ 5329 urtwn_write_2(sc, R92C_RL, 5330 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 5331 5332 /* Initialize EDCA parameters. */ 5333 urtwn_edca_init(sc); 5334 5335 /* Setup rate fallback. */ 5336 if (!(sc->chip & URTWN_CHIP_88E)) { 5337 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 5338 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 5339 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 5340 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 5341 } 5342 5343 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 5344 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 5345 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 5346 /* Set ACK timeout. */ 5347 urtwn_write_1(sc, R92C_ACKTO, 0x40); 5348 5349 /* Setup USB aggregation. */ 5350 reg = urtwn_read_4(sc, R92C_TDECTRL); 5351 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 5352 urtwn_write_4(sc, R92C_TDECTRL, reg); 5353 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 5354 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 5355 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 5356 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 5357 if (sc->chip & URTWN_CHIP_88E) 5358 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 5359 else { 5360 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 5361 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5362 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5363 R92C_USB_SPECIAL_OPTION_AGG_EN); 5364 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 5365 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 5366 } 5367 5368 /* Initialize beacon parameters. */ 5369 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 5370 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 5371 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 5372 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 5373 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 5374 5375 if (!(sc->chip & URTWN_CHIP_88E)) { 5376 /* Setup AMPDU aggregation. */ 5377 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 5378 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 5379 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 5380 5381 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 5382 } 5383 5384 #ifndef URTWN_WITHOUT_UCODE 5385 /* Load 8051 microcode. */ 5386 error = urtwn_load_firmware(sc); 5387 if (error == 0) 5388 sc->sc_flags |= URTWN_FW_LOADED; 5389 #endif 5390 5391 /* Initialize MAC/BB/RF blocks. */ 5392 error = urtwn_mac_init(sc); 5393 if (error != 0) { 5394 device_printf(sc->sc_dev, 5395 "%s: error while initializing MAC block\n", __func__); 5396 goto fail; 5397 } 5398 urtwn_bb_init(sc); 5399 urtwn_rf_init(sc); 5400 5401 /* Reinitialize Rx filter (D3845 is not committed yet). */ 5402 urtwn_rxfilter_init(sc); 5403 5404 if (sc->chip & URTWN_CHIP_88E) { 5405 urtwn_write_2(sc, R92C_CR, 5406 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 5407 R92C_CR_MACRXEN); 5408 } 5409 5410 /* Turn CCK and OFDM blocks on. */ 5411 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5412 reg |= R92C_RFMOD_CCK_EN; 5413 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5414 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5415 goto fail; 5416 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5417 reg |= R92C_RFMOD_OFDM_EN; 5418 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5419 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5420 goto fail; 5421 5422 /* Clear per-station keys table. */ 5423 urtwn_cam_init(sc); 5424 5425 /* Enable decryption / encryption. */ 5426 urtwn_write_2(sc, R92C_SECCFG, 5427 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 5428 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA | 5429 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 5430 5431 /* 5432 * Install static keys (if any). 5433 * Must be called after urtwn_cam_init(). 5434 */ 5435 ieee80211_runtask(ic, &sc->cmdq_task); 5436 5437 /* Enable hardware sequence numbering. */ 5438 urtwn_write_1(sc, R92C_HWSEQ_CTRL, R92C_TX_QUEUE_ALL); 5439 5440 /* Enable per-packet TX report. */ 5441 if (sc->chip & URTWN_CHIP_88E) { 5442 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 5443 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA); 5444 } 5445 5446 /* Perform LO and IQ calibrations. */ 5447 urtwn_iq_calib(sc); 5448 /* Perform LC calibration. */ 5449 urtwn_lc_calib(sc); 5450 5451 /* Fix USB interference issue. */ 5452 if (!(sc->chip & URTWN_CHIP_88E)) { 5453 urtwn_write_1(sc, 0xfe40, 0xe0); 5454 urtwn_write_1(sc, 0xfe41, 0x8d); 5455 urtwn_write_1(sc, 0xfe42, 0x80); 5456 5457 urtwn_pa_bias_init(sc); 5458 } 5459 5460 /* Initialize GPIO setting. */ 5461 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5462 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5463 5464 /* Fix for lower temperature. */ 5465 if (!(sc->chip & URTWN_CHIP_88E)) 5466 urtwn_write_1(sc, 0x15, 0xe9); 5467 5468 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 5469 5470 sc->sc_flags |= URTWN_RUNNING; 5471 5472 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5473 fail: 5474 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5475 error = EIO; 5476 5477 URTWN_UNLOCK(sc); 5478 5479 return (error); 5480 } 5481 5482 static void 5483 urtwn_stop(struct urtwn_softc *sc) 5484 { 5485 5486 URTWN_LOCK(sc); 5487 if (!(sc->sc_flags & URTWN_RUNNING)) { 5488 URTWN_UNLOCK(sc); 5489 return; 5490 } 5491 5492 sc->sc_flags &= ~(URTWN_RUNNING | URTWN_FW_LOADED | 5493 URTWN_TEMP_MEASURED); 5494 sc->thcal_lctemp = 0; 5495 callout_stop(&sc->sc_watchdog_ch); 5496 5497 urtwn_abort_xfers(sc); 5498 urtwn_drain_mbufq(sc); 5499 urtwn_power_off(sc); 5500 URTWN_UNLOCK(sc); 5501 } 5502 5503 static void 5504 urtwn_abort_xfers(struct urtwn_softc *sc) 5505 { 5506 int i; 5507 5508 URTWN_ASSERT_LOCKED(sc); 5509 5510 /* abort any pending transfers */ 5511 for (i = 0; i < URTWN_N_TRANSFER; i++) 5512 usbd_transfer_stop(sc->sc_xfer[i]); 5513 } 5514 5515 static int 5516 urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 5517 const struct ieee80211_bpf_params *params) 5518 { 5519 struct ieee80211com *ic = ni->ni_ic; 5520 struct urtwn_softc *sc = ic->ic_softc; 5521 struct urtwn_data *bf; 5522 int error; 5523 5524 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n", 5525 __func__, 5526 m); 5527 5528 /* prevent management frames from being sent if we're not ready */ 5529 URTWN_LOCK(sc); 5530 if (!(sc->sc_flags & URTWN_RUNNING)) { 5531 error = ENETDOWN; 5532 goto end; 5533 } 5534 5535 bf = urtwn_getbuf(sc); 5536 if (bf == NULL) { 5537 error = ENOBUFS; 5538 goto end; 5539 } 5540 5541 if (params == NULL) { 5542 /* 5543 * Legacy path; interpret frame contents to decide 5544 * precisely how to send the frame. 5545 */ 5546 error = urtwn_tx_data(sc, ni, m, bf); 5547 } else { 5548 /* 5549 * Caller supplied explicit parameters to use in 5550 * sending the frame. 5551 */ 5552 error = urtwn_tx_raw(sc, ni, m, bf, params); 5553 } 5554 if (error != 0) { 5555 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 5556 goto end; 5557 } 5558 5559 sc->sc_txtimer = 5; 5560 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5561 5562 end: 5563 if (error != 0) 5564 m_freem(m); 5565 5566 URTWN_UNLOCK(sc); 5567 5568 return (error); 5569 } 5570 5571 static void 5572 urtwn_ms_delay(struct urtwn_softc *sc) 5573 { 5574 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 5575 } 5576 5577 static device_method_t urtwn_methods[] = { 5578 /* Device interface */ 5579 DEVMETHOD(device_probe, urtwn_match), 5580 DEVMETHOD(device_attach, urtwn_attach), 5581 DEVMETHOD(device_detach, urtwn_detach), 5582 5583 DEVMETHOD_END 5584 }; 5585 5586 static driver_t urtwn_driver = { 5587 "urtwn", 5588 urtwn_methods, 5589 sizeof(struct urtwn_softc) 5590 }; 5591 5592 static devclass_t urtwn_devclass; 5593 5594 DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 5595 MODULE_DEPEND(urtwn, usb, 1, 1, 1); 5596 MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 5597 #ifndef URTWN_WITHOUT_UCODE 5598 MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 5599 #endif 5600 MODULE_VERSION(urtwn, 1); 5601 #if defined(__DragonFly__) 5602 /* USB_PNP_HOST_INFO() not implemented */ 5603 #else 5604 USB_PNP_HOST_INFO(urtwn_devs); 5605 #endif 5606