1 /* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2015 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __FBSDID("$FreeBSD$"); 23 24 /* 25 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 26 */ 27 28 #include "opt_wlan.h" 29 #include "opt_urtwn.h" 30 31 #include <sys/param.h> 32 #include <sys/sockio.h> 33 #include <sys/sysctl.h> 34 #include <sys/lock.h> 35 #include <sys/condvar.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/linker.h> 45 #include <sys/firmware.h> 46 #if defined(__DragonFly__) 47 #else 48 #include <sys/kdb.h> 49 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #endif 53 54 #include <sys/rman.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_arp.h> 60 #include <net/ethernet.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 #include <net/if_types.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/in_var.h> 68 #include <netinet/if_ether.h> 69 #include <netinet/ip.h> 70 71 #include <netproto/802_11/ieee80211_var.h> 72 #include <netproto/802_11/ieee80211_regdomain.h> 73 #include <netproto/802_11/ieee80211_radiotap.h> 74 #include <netproto/802_11/ieee80211_ratectl.h> 75 #ifdef IEEE80211_SUPPORT_SUPERG 76 #include <netproto/802_11/ieee80211_superg.h> 77 #endif 78 79 #include <bus/u4b/usb.h> 80 #include <bus/u4b/usbdi.h> 81 #include <bus/u4b/usb_device.h> 82 #include "usbdevs.h" 83 84 #include <bus/u4b/usb_debug.h> 85 86 #include <bus/u4b/wlan/if_urtwnreg.h> 87 #include <bus/u4b/wlan/if_urtwnvar.h> 88 89 #ifdef USB_DEBUG 90 enum { 91 URTWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 92 URTWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 93 URTWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 94 URTWN_DEBUG_RA = 0x00000008, /* f/w rate adaptation setup */ 95 URTWN_DEBUG_USB = 0x00000010, /* usb requests */ 96 URTWN_DEBUG_FIRMWARE = 0x00000020, /* firmware(9) loading debug */ 97 URTWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 98 URTWN_DEBUG_INTR = 0x00000080, /* ISR */ 99 URTWN_DEBUG_TEMP = 0x00000100, /* temperature calibration */ 100 URTWN_DEBUG_ROM = 0x00000200, /* various ROM info */ 101 URTWN_DEBUG_KEY = 0x00000400, /* crypto keys management */ 102 URTWN_DEBUG_TXPWR = 0x00000800, /* dump Tx power values */ 103 URTWN_DEBUG_RSSI = 0x00001000, /* dump RSSI lookups */ 104 URTWN_DEBUG_ANY = 0xffffffff 105 }; 106 107 #define URTWN_DPRINTF(_sc, _m, ...) do { \ 108 if ((_sc)->sc_debug & (_m)) \ 109 device_printf((_sc)->sc_dev, __VA_ARGS__); \ 110 } while(0) 111 112 #else 113 #define URTWN_DPRINTF(_sc, _m, ...) do { (void) sc; } while (0) 114 #endif 115 116 #define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 117 118 static int urtwn_enable_11n = 1; 119 TUNABLE_INT("hw.usb.urtwn.enable_11n", &urtwn_enable_11n); 120 121 /* various supported device vendors/products */ 122 static const STRUCT_USB_HOST_ID urtwn_devs[] = { 123 #define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 124 #define URTWN_RTL8188E_DEV(v,p) \ 125 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 126 #define URTWN_RTL8188E 1 127 URTWN_DEV(ABOCOM, RTL8188CU_1), 128 URTWN_DEV(ABOCOM, RTL8188CU_2), 129 URTWN_DEV(ABOCOM, RTL8192CU), 130 URTWN_DEV(ASUS, RTL8192CU), 131 URTWN_DEV(ASUS, USBN10NANO), 132 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 133 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 134 URTWN_DEV(AZUREWAVE, RTL8188CU), 135 URTWN_DEV(BELKIN, F7D2102), 136 URTWN_DEV(BELKIN, RTL8188CU), 137 URTWN_DEV(BELKIN, RTL8192CU), 138 URTWN_DEV(CHICONY, RTL8188CUS_1), 139 URTWN_DEV(CHICONY, RTL8188CUS_2), 140 URTWN_DEV(CHICONY, RTL8188CUS_3), 141 URTWN_DEV(CHICONY, RTL8188CUS_4), 142 URTWN_DEV(CHICONY, RTL8188CUS_5), 143 URTWN_DEV(COREGA, RTL8192CU), 144 URTWN_DEV(DLINK, RTL8188CU), 145 URTWN_DEV(DLINK, RTL8192CU_1), 146 URTWN_DEV(DLINK, RTL8192CU_2), 147 URTWN_DEV(DLINK, RTL8192CU_3), 148 URTWN_DEV(DLINK, DWA131B), 149 URTWN_DEV(EDIMAX, EW7811UN), 150 URTWN_DEV(EDIMAX, RTL8192CU), 151 URTWN_DEV(FEIXUN, RTL8188CU), 152 URTWN_DEV(FEIXUN, RTL8192CU), 153 URTWN_DEV(GUILLEMOT, HWNUP150), 154 URTWN_DEV(HAWKING, RTL8192CU), 155 URTWN_DEV(HP3, RTL8188CU), 156 URTWN_DEV(NETGEAR, WNA1000M), 157 URTWN_DEV(NETGEAR, RTL8192CU), 158 URTWN_DEV(NETGEAR4, RTL8188CU), 159 URTWN_DEV(NOVATECH, RTL8188CU), 160 URTWN_DEV(PLANEX2, RTL8188CU_1), 161 URTWN_DEV(PLANEX2, RTL8188CU_2), 162 URTWN_DEV(PLANEX2, RTL8188CU_3), 163 URTWN_DEV(PLANEX2, RTL8188CU_4), 164 URTWN_DEV(PLANEX2, RTL8188CUS), 165 URTWN_DEV(PLANEX2, RTL8192CU), 166 URTWN_DEV(REALTEK, RTL8188CE_0), 167 URTWN_DEV(REALTEK, RTL8188CE_1), 168 URTWN_DEV(REALTEK, RTL8188CTV), 169 URTWN_DEV(REALTEK, RTL8188CU_0), 170 URTWN_DEV(REALTEK, RTL8188CU_1), 171 URTWN_DEV(REALTEK, RTL8188CU_2), 172 URTWN_DEV(REALTEK, RTL8188CU_3), 173 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 174 URTWN_DEV(REALTEK, RTL8188CUS), 175 URTWN_DEV(REALTEK, RTL8188RU_1), 176 URTWN_DEV(REALTEK, RTL8188RU_2), 177 URTWN_DEV(REALTEK, RTL8188RU_3), 178 URTWN_DEV(REALTEK, RTL8191CU), 179 URTWN_DEV(REALTEK, RTL8192CE), 180 URTWN_DEV(REALTEK, RTL8192CU), 181 URTWN_DEV(SITECOMEU, RTL8188CU_1), 182 URTWN_DEV(SITECOMEU, RTL8188CU_2), 183 URTWN_DEV(SITECOMEU, RTL8192CU), 184 URTWN_DEV(TRENDNET, RTL8188CU), 185 URTWN_DEV(TRENDNET, RTL8192CU), 186 URTWN_DEV(ZYXEL, RTL8192CU), 187 /* URTWN_RTL8188E */ 188 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 189 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 190 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 191 URTWN_RTL8188E_DEV(EDIMAX, EW7811UN_V2), 192 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 193 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 194 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 195 URTWN_RTL8188E_DEV(MERCUSYS, MW150US), 196 #undef URTWN_RTL8188E_DEV 197 #undef URTWN_DEV 198 }; 199 200 static device_probe_t urtwn_match; 201 static device_attach_t urtwn_attach; 202 static device_detach_t urtwn_detach; 203 204 static usb_callback_t urtwn_bulk_tx_callback; 205 static usb_callback_t urtwn_bulk_rx_callback; 206 207 static void urtwn_sysctlattach(struct urtwn_softc *); 208 static void urtwn_drain_mbufq(struct urtwn_softc *); 209 static usb_error_t urtwn_do_request(struct urtwn_softc *, 210 struct usb_device_request *, void *); 211 static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 212 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 213 const uint8_t [IEEE80211_ADDR_LEN], 214 const uint8_t [IEEE80211_ADDR_LEN]); 215 static void urtwn_vap_delete(struct ieee80211vap *); 216 static struct mbuf * urtwn_rx_copy_to_mbuf(struct urtwn_softc *, 217 struct r92c_rx_stat *, int); 218 static struct mbuf * urtwn_report_intr(struct usb_xfer *, 219 struct urtwn_data *); 220 static struct mbuf * urtwn_rxeof(struct urtwn_softc *, uint8_t *, int); 221 static void urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *, 222 void *); 223 static struct ieee80211_node *urtwn_rx_frame(struct urtwn_softc *, 224 struct mbuf *, int8_t *); 225 static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 226 int); 227 static int urtwn_alloc_list(struct urtwn_softc *, 228 struct urtwn_data[], int, int); 229 static int urtwn_alloc_rx_list(struct urtwn_softc *); 230 static int urtwn_alloc_tx_list(struct urtwn_softc *); 231 static void urtwn_free_list(struct urtwn_softc *, 232 struct urtwn_data data[], int); 233 static void urtwn_free_rx_list(struct urtwn_softc *); 234 static void urtwn_free_tx_list(struct urtwn_softc *); 235 static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 236 static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 237 static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 238 uint8_t *, int); 239 static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 240 static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 241 static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 242 static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 243 uint8_t *, int); 244 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 245 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 246 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 247 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 248 const void *, int); 249 static void urtwn_cmdq_cb(void *, int); 250 static int urtwn_cmd_sleepable(struct urtwn_softc *, const void *, 251 size_t, CMD_FUNC_PROTO); 252 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 253 uint8_t, uint32_t); 254 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 255 uint8_t, uint32_t); 256 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 257 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 258 uint32_t); 259 static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 260 static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 261 uint8_t, uint8_t); 262 #ifdef USB_DEBUG 263 static void urtwn_dump_rom_contents(struct urtwn_softc *, 264 uint8_t *, uint16_t); 265 #endif 266 static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 267 uint16_t); 268 static int urtwn_efuse_switch_power(struct urtwn_softc *); 269 static int urtwn_read_chipid(struct urtwn_softc *); 270 static int urtwn_read_rom(struct urtwn_softc *); 271 static int urtwn_r88e_read_rom(struct urtwn_softc *); 272 static int urtwn_ra_init(struct urtwn_softc *); 273 static void urtwn_init_beacon(struct urtwn_softc *, 274 struct urtwn_vap *); 275 static int urtwn_setup_beacon(struct urtwn_softc *, 276 struct ieee80211_node *); 277 static void urtwn_update_beacon(struct ieee80211vap *, int); 278 static int urtwn_tx_beacon(struct urtwn_softc *sc, 279 struct urtwn_vap *); 280 static int urtwn_key_alloc(struct ieee80211vap *, 281 struct ieee80211_key *, ieee80211_keyix *, 282 ieee80211_keyix *); 283 static void urtwn_key_set_cb(struct urtwn_softc *, 284 union sec_param *); 285 static void urtwn_key_del_cb(struct urtwn_softc *, 286 union sec_param *); 287 static int urtwn_key_set(struct ieee80211vap *, 288 const struct ieee80211_key *); 289 static int urtwn_key_delete(struct ieee80211vap *, 290 const struct ieee80211_key *); 291 static void urtwn_tsf_task_adhoc(void *, int); 292 static void urtwn_tsf_sync_enable(struct urtwn_softc *, 293 struct ieee80211vap *); 294 static void urtwn_get_tsf(struct urtwn_softc *, uint64_t *); 295 static void urtwn_set_led(struct urtwn_softc *, int, int); 296 static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 297 static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 298 struct mbuf *, int, 299 const struct ieee80211_rx_stats *, int, int); 300 static int urtwn_newstate(struct ieee80211vap *, 301 enum ieee80211_state, int); 302 static void urtwn_calib_to(void *); 303 static void urtwn_calib_cb(struct urtwn_softc *, 304 union sec_param *); 305 static void urtwn_watchdog(void *); 306 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 307 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 308 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 309 static int urtwn_tx_data(struct urtwn_softc *, 310 struct ieee80211_node *, struct mbuf *, 311 struct urtwn_data *); 312 static int urtwn_tx_raw(struct urtwn_softc *, 313 struct ieee80211_node *, struct mbuf *, 314 struct urtwn_data *, 315 const struct ieee80211_bpf_params *); 316 static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 317 uint8_t, struct urtwn_data *); 318 static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 319 static void urtwn_start(struct urtwn_softc *); 320 static void urtwn_parent(struct ieee80211com *); 321 static int urtwn_r92c_power_on(struct urtwn_softc *); 322 static int urtwn_r88e_power_on(struct urtwn_softc *); 323 static void urtwn_r92c_power_off(struct urtwn_softc *); 324 static void urtwn_r88e_power_off(struct urtwn_softc *); 325 static int urtwn_llt_init(struct urtwn_softc *); 326 #ifndef URTWN_WITHOUT_UCODE 327 static void urtwn_fw_reset(struct urtwn_softc *); 328 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 329 static int urtwn_fw_loadpage(struct urtwn_softc *, int, 330 const uint8_t *, int); 331 static int urtwn_load_firmware(struct urtwn_softc *); 332 #endif 333 static int urtwn_dma_init(struct urtwn_softc *); 334 static int urtwn_mac_init(struct urtwn_softc *); 335 static void urtwn_bb_init(struct urtwn_softc *); 336 static void urtwn_rf_init(struct urtwn_softc *); 337 static void urtwn_cam_init(struct urtwn_softc *); 338 static int urtwn_cam_write(struct urtwn_softc *, uint32_t, 339 uint32_t); 340 static void urtwn_pa_bias_init(struct urtwn_softc *); 341 static void urtwn_rxfilter_init(struct urtwn_softc *); 342 static void urtwn_edca_init(struct urtwn_softc *); 343 static void urtwn_write_txpower(struct urtwn_softc *, int, 344 uint16_t[]); 345 static void urtwn_get_txpower(struct urtwn_softc *, int, 346 struct ieee80211_channel *, 347 struct ieee80211_channel *, uint16_t[]); 348 static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 349 struct ieee80211_channel *, 350 struct ieee80211_channel *, uint16_t[]); 351 static void urtwn_set_txpower(struct urtwn_softc *, 352 struct ieee80211_channel *, 353 struct ieee80211_channel *); 354 static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 355 static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 356 static void urtwn_scan_start(struct ieee80211com *); 357 static void urtwn_scan_end(struct ieee80211com *); 358 static void urtwn_set_channel(struct ieee80211com *); 359 static int urtwn_wme_update(struct ieee80211com *); 360 static void urtwn_update_slot(struct ieee80211com *); 361 static void urtwn_update_slot_cb(struct urtwn_softc *, 362 union sec_param *); 363 static void urtwn_update_aifs(struct urtwn_softc *, uint8_t); 364 static uint8_t urtwn_get_multi_pos(const uint8_t[]); 365 static void urtwn_set_multi(struct urtwn_softc *); 366 static void urtwn_set_promisc(struct urtwn_softc *); 367 static void urtwn_update_promisc(struct ieee80211com *); 368 static void urtwn_update_mcast(struct ieee80211com *); 369 static struct ieee80211_node *urtwn_node_alloc(struct ieee80211vap *, 370 const uint8_t mac[IEEE80211_ADDR_LEN]); 371 static void urtwn_newassoc(struct ieee80211_node *, int); 372 static void urtwn_node_free(struct ieee80211_node *); 373 static void urtwn_set_chan(struct urtwn_softc *, 374 struct ieee80211_channel *, 375 struct ieee80211_channel *); 376 static void urtwn_iq_calib(struct urtwn_softc *); 377 static void urtwn_lc_calib(struct urtwn_softc *); 378 static void urtwn_temp_calib(struct urtwn_softc *); 379 static int urtwn_init(struct urtwn_softc *); 380 static void urtwn_stop(struct urtwn_softc *); 381 static void urtwn_abort_xfers(struct urtwn_softc *); 382 static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 383 const struct ieee80211_bpf_params *); 384 static void urtwn_ms_delay(struct urtwn_softc *); 385 386 /* Aliases. */ 387 #define urtwn_bb_write urtwn_write_4 388 #define urtwn_bb_read urtwn_read_4 389 390 static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 391 [URTWN_BULK_RX] = { 392 .type = UE_BULK, 393 .endpoint = UE_ADDR_ANY, 394 .direction = UE_DIR_IN, 395 .bufsize = URTWN_RXBUFSZ, 396 .flags = { 397 .pipe_bof = 1, 398 .short_xfer_ok = 1 399 }, 400 .callback = urtwn_bulk_rx_callback, 401 }, 402 [URTWN_BULK_TX_BE] = { 403 .type = UE_BULK, 404 .endpoint = 0x03, 405 .direction = UE_DIR_OUT, 406 .bufsize = URTWN_TXBUFSZ, 407 .flags = { 408 .ext_buffer = 1, 409 .pipe_bof = 1, 410 .force_short_xfer = 1 411 }, 412 .callback = urtwn_bulk_tx_callback, 413 .timeout = URTWN_TX_TIMEOUT, /* ms */ 414 }, 415 [URTWN_BULK_TX_BK] = { 416 .type = UE_BULK, 417 .endpoint = 0x03, 418 .direction = UE_DIR_OUT, 419 .bufsize = URTWN_TXBUFSZ, 420 .flags = { 421 .ext_buffer = 1, 422 .pipe_bof = 1, 423 .force_short_xfer = 1, 424 }, 425 .callback = urtwn_bulk_tx_callback, 426 .timeout = URTWN_TX_TIMEOUT, /* ms */ 427 }, 428 [URTWN_BULK_TX_VI] = { 429 .type = UE_BULK, 430 .endpoint = 0x02, 431 .direction = UE_DIR_OUT, 432 .bufsize = URTWN_TXBUFSZ, 433 .flags = { 434 .ext_buffer = 1, 435 .pipe_bof = 1, 436 .force_short_xfer = 1 437 }, 438 .callback = urtwn_bulk_tx_callback, 439 .timeout = URTWN_TX_TIMEOUT, /* ms */ 440 }, 441 [URTWN_BULK_TX_VO] = { 442 .type = UE_BULK, 443 .endpoint = 0x02, 444 .direction = UE_DIR_OUT, 445 .bufsize = URTWN_TXBUFSZ, 446 .flags = { 447 .ext_buffer = 1, 448 .pipe_bof = 1, 449 .force_short_xfer = 1 450 }, 451 .callback = urtwn_bulk_tx_callback, 452 .timeout = URTWN_TX_TIMEOUT, /* ms */ 453 }, 454 }; 455 456 static const struct wme_to_queue { 457 uint16_t reg; 458 uint8_t qid; 459 } wme2queue[WME_NUM_AC] = { 460 { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 461 { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 462 { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 463 { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 464 }; 465 466 static int 467 urtwn_match(device_t self) 468 { 469 struct usb_attach_arg *uaa = device_get_ivars(self); 470 471 if (uaa->usb_mode != USB_MODE_HOST) 472 return (ENXIO); 473 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 474 return (ENXIO); 475 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 476 return (ENXIO); 477 478 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 479 } 480 481 static void 482 urtwn_update_chw(struct ieee80211com *ic) 483 { 484 } 485 486 static int 487 urtwn_ampdu_enable(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 488 { 489 490 /* We're driving this ourselves (eventually); don't involve net80211 */ 491 return (0); 492 } 493 494 static int 495 urtwn_attach(device_t self) 496 { 497 struct usb_attach_arg *uaa = device_get_ivars(self); 498 struct urtwn_softc *sc = device_get_softc(self); 499 struct ieee80211com *ic = &sc->sc_ic; 500 uint8_t bands[IEEE80211_MODE_BYTES]; 501 int error; 502 503 device_set_usb_desc(self); 504 sc->sc_udev = uaa->device; 505 sc->sc_dev = self; 506 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 507 sc->chip |= URTWN_CHIP_88E; 508 509 #ifdef USB_DEBUG 510 int debug; 511 if (resource_int_value(device_get_name(sc->sc_dev), 512 device_get_unit(sc->sc_dev), "debug", &debug) == 0) 513 sc->sc_debug = debug; 514 #endif 515 516 #if defined(__DragonFly__) 517 lockinit(&sc->sc_mtx, device_get_nameunit(self), 0, 0); 518 #else 519 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 520 MTX_NETWORK_LOCK, MTX_DEF); 521 #endif 522 URTWN_CMDQ_LOCK_INIT(sc); 523 URTWN_NT_LOCK_INIT(sc); 524 #if defined(__DragonFly__) 525 callout_init(&sc->sc_calib_to); 526 callout_init(&sc->sc_watchdog_ch); 527 #else 528 callout_init(&sc->sc_calib_to, 0); 529 callout_init(&sc->sc_watchdog_ch, 0); 530 #endif 531 mbufq_init(&sc->sc_snd, ifqmaxlen); 532 533 sc->sc_iface_index = URTWN_IFACE_INDEX; 534 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 535 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 536 if (error) { 537 device_printf(self, "could not allocate USB transfers, " 538 "err=%s\n", usbd_errstr(error)); 539 goto detach; 540 } 541 542 URTWN_LOCK(sc); 543 544 error = urtwn_read_chipid(sc); 545 if (error) { 546 device_printf(sc->sc_dev, "unsupported test chip\n"); 547 URTWN_UNLOCK(sc); 548 goto detach; 549 } 550 551 /* Determine number of Tx/Rx chains. */ 552 if (sc->chip & URTWN_CHIP_92C) { 553 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 554 sc->nrxchains = 2; 555 } else { 556 sc->ntxchains = 1; 557 sc->nrxchains = 1; 558 } 559 560 if (sc->chip & URTWN_CHIP_88E) 561 error = urtwn_r88e_read_rom(sc); 562 else 563 error = urtwn_read_rom(sc); 564 if (error != 0) { 565 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 566 __func__, error); 567 URTWN_UNLOCK(sc); 568 goto detach; 569 } 570 571 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 572 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 573 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 574 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 575 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 576 "8188CUS", sc->ntxchains, sc->nrxchains); 577 578 URTWN_UNLOCK(sc); 579 580 ic->ic_softc = sc; 581 ic->ic_name = device_get_nameunit(self); 582 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 583 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 584 585 /* set device capabilities */ 586 ic->ic_caps = 587 IEEE80211_C_STA /* station mode */ 588 | IEEE80211_C_MONITOR /* monitor mode */ 589 | IEEE80211_C_IBSS /* adhoc mode */ 590 | IEEE80211_C_HOSTAP /* hostap mode */ 591 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 592 | IEEE80211_C_SHSLOT /* short slot time supported */ 593 #if 0 594 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 595 #endif 596 | IEEE80211_C_WPA /* 802.11i */ 597 | IEEE80211_C_WME /* 802.11e */ 598 | IEEE80211_C_SWAMSDUTX /* Do software A-MSDU TX */ 599 | IEEE80211_C_FF /* Atheros fast-frames */ 600 ; 601 602 ic->ic_cryptocaps = 603 IEEE80211_CRYPTO_WEP | 604 IEEE80211_CRYPTO_TKIP | 605 IEEE80211_CRYPTO_AES_CCM; 606 607 /* Assume they're all 11n capable for now */ 608 if (urtwn_enable_11n) { 609 device_printf(self, "enabling 11n\n"); 610 ic->ic_htcaps = IEEE80211_HTC_HT | 611 #if 0 612 IEEE80211_HTC_AMPDU | 613 #endif 614 IEEE80211_HTC_AMSDU | 615 IEEE80211_HTCAP_MAXAMSDU_3839 | 616 IEEE80211_HTCAP_SMPS_OFF; 617 /* no HT40 just yet */ 618 // ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40; 619 620 /* XXX TODO: verify chains versus streams for urtwn */ 621 ic->ic_txstream = sc->ntxchains; 622 ic->ic_rxstream = sc->nrxchains; 623 } 624 625 memset(bands, 0, sizeof(bands)); 626 setbit(bands, IEEE80211_MODE_11B); 627 setbit(bands, IEEE80211_MODE_11G); 628 if (urtwn_enable_11n) 629 setbit(bands, IEEE80211_MODE_11NG); 630 ieee80211_init_channels(ic, NULL, bands); 631 632 ieee80211_ifattach(ic); 633 ic->ic_raw_xmit = urtwn_raw_xmit; 634 ic->ic_scan_start = urtwn_scan_start; 635 ic->ic_scan_end = urtwn_scan_end; 636 ic->ic_set_channel = urtwn_set_channel; 637 ic->ic_transmit = urtwn_transmit; 638 ic->ic_parent = urtwn_parent; 639 ic->ic_vap_create = urtwn_vap_create; 640 ic->ic_vap_delete = urtwn_vap_delete; 641 ic->ic_wme.wme_update = urtwn_wme_update; 642 ic->ic_updateslot = urtwn_update_slot; 643 ic->ic_update_promisc = urtwn_update_promisc; 644 ic->ic_update_mcast = urtwn_update_mcast; 645 if (sc->chip & URTWN_CHIP_88E) { 646 ic->ic_node_alloc = urtwn_node_alloc; 647 ic->ic_newassoc = urtwn_newassoc; 648 sc->sc_node_free = ic->ic_node_free; 649 ic->ic_node_free = urtwn_node_free; 650 } 651 ic->ic_update_chw = urtwn_update_chw; 652 ic->ic_ampdu_enable = urtwn_ampdu_enable; 653 654 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 655 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 656 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 657 URTWN_RX_RADIOTAP_PRESENT); 658 659 TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc); 660 661 urtwn_sysctlattach(sc); 662 663 if (bootverbose) 664 ieee80211_announce(ic); 665 666 return (0); 667 668 detach: 669 urtwn_detach(self); 670 return (ENXIO); /* failure */ 671 } 672 673 static void 674 urtwn_sysctlattach(struct urtwn_softc *sc) 675 { 676 #ifdef USB_DEBUG 677 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 678 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 679 680 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 681 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 682 "control debugging printfs"); 683 #endif 684 } 685 686 static int 687 urtwn_detach(device_t self) 688 { 689 struct urtwn_softc *sc = device_get_softc(self); 690 struct ieee80211com *ic = &sc->sc_ic; 691 unsigned int x; 692 693 /* Prevent further ioctls. */ 694 URTWN_LOCK(sc); 695 sc->sc_flags |= URTWN_DETACHED; 696 URTWN_UNLOCK(sc); 697 698 urtwn_stop(sc); 699 700 callout_drain(&sc->sc_watchdog_ch); 701 callout_drain(&sc->sc_calib_to); 702 703 /* stop all USB transfers */ 704 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 705 706 /* Prevent further allocations from RX/TX data lists. */ 707 URTWN_LOCK(sc); 708 STAILQ_INIT(&sc->sc_tx_active); 709 STAILQ_INIT(&sc->sc_tx_inactive); 710 STAILQ_INIT(&sc->sc_tx_pending); 711 712 STAILQ_INIT(&sc->sc_rx_active); 713 STAILQ_INIT(&sc->sc_rx_inactive); 714 URTWN_UNLOCK(sc); 715 716 /* drain USB transfers */ 717 for (x = 0; x != URTWN_N_TRANSFER; x++) 718 usbd_transfer_drain(sc->sc_xfer[x]); 719 720 /* Free data buffers. */ 721 URTWN_LOCK(sc); 722 urtwn_free_tx_list(sc); 723 urtwn_free_rx_list(sc); 724 URTWN_UNLOCK(sc); 725 726 if (ic->ic_softc == sc) { 727 ieee80211_draintask(ic, &sc->cmdq_task); 728 ieee80211_ifdetach(ic); 729 } 730 731 URTWN_NT_LOCK_DESTROY(sc); 732 URTWN_CMDQ_LOCK_DESTROY(sc); 733 lockuninit(&sc->sc_mtx); 734 735 return (0); 736 } 737 738 static void 739 urtwn_drain_mbufq(struct urtwn_softc *sc) 740 { 741 struct mbuf *m; 742 struct ieee80211_node *ni; 743 URTWN_ASSERT_LOCKED(sc); 744 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 745 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 746 m->m_pkthdr.rcvif = NULL; 747 ieee80211_free_node(ni); 748 m_freem(m); 749 } 750 } 751 752 static usb_error_t 753 urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 754 void *data) 755 { 756 usb_error_t err; 757 int ntries = 10; 758 759 URTWN_ASSERT_LOCKED(sc); 760 761 err = 0; /* whack gcc warning */ 762 while (ntries--) { 763 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 764 req, data, 0, NULL, 250 /* ms */); 765 if (err == 0) 766 break; 767 768 URTWN_DPRINTF(sc, URTWN_DEBUG_USB, 769 "%s: control request failed, %s (retries left: %d)\n", 770 __func__, usbd_errstr(err), ntries); 771 usb_pause_mtx(&sc->sc_mtx, hz / 100); 772 } 773 return (err); 774 } 775 776 static struct ieee80211vap * 777 urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 778 enum ieee80211_opmode opmode, int flags, 779 const uint8_t bssid[IEEE80211_ADDR_LEN], 780 const uint8_t mac[IEEE80211_ADDR_LEN]) 781 { 782 struct urtwn_softc *sc = ic->ic_softc; 783 struct urtwn_vap *uvp; 784 struct ieee80211vap *vap; 785 786 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 787 return (NULL); 788 789 uvp = kmalloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 790 vap = &uvp->vap; 791 /* enable s/w bmiss handling for sta mode */ 792 793 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 794 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 795 /* out of memory */ 796 kfree(uvp, M_80211_VAP); 797 return (NULL); 798 } 799 800 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 801 urtwn_init_beacon(sc, uvp); 802 803 /* override state transition machine */ 804 uvp->newstate = vap->iv_newstate; 805 vap->iv_newstate = urtwn_newstate; 806 vap->iv_update_beacon = urtwn_update_beacon; 807 vap->iv_key_alloc = urtwn_key_alloc; 808 vap->iv_key_set = urtwn_key_set; 809 vap->iv_key_delete = urtwn_key_delete; 810 811 /* 802.11n parameters */ 812 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_16; 813 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 814 815 if (opmode == IEEE80211_M_IBSS) { 816 uvp->recv_mgmt = vap->iv_recv_mgmt; 817 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 818 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 819 } 820 821 if (URTWN_CHIP_HAS_RATECTL(sc)) 822 ieee80211_ratectl_init(vap); 823 /* complete setup */ 824 ieee80211_vap_attach(vap, ieee80211_media_change, 825 ieee80211_media_status, mac); 826 ic->ic_opmode = opmode; 827 return (vap); 828 } 829 830 static void 831 urtwn_vap_delete(struct ieee80211vap *vap) 832 { 833 struct ieee80211com *ic = vap->iv_ic; 834 struct urtwn_softc *sc = ic->ic_softc; 835 struct urtwn_vap *uvp = URTWN_VAP(vap); 836 837 if (uvp->bcn_mbuf != NULL) 838 m_freem(uvp->bcn_mbuf); 839 if (vap->iv_opmode == IEEE80211_M_IBSS) 840 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 841 if (URTWN_CHIP_HAS_RATECTL(sc)) 842 ieee80211_ratectl_deinit(vap); 843 ieee80211_vap_detach(vap); 844 kfree(uvp, M_80211_VAP); 845 } 846 847 static struct mbuf * 848 urtwn_rx_copy_to_mbuf(struct urtwn_softc *sc, struct r92c_rx_stat *stat, 849 int totlen) 850 { 851 /* ic is not used, remove to fix gcc warning */ 852 /* struct ieee80211com *ic = &sc->sc_ic; */ 853 struct mbuf *m; 854 uint32_t rxdw0; 855 int pktlen; 856 857 /* 858 * don't pass packets to the ieee80211 framework if the driver isn't 859 * RUNNING. 860 */ 861 if (!(sc->sc_flags & URTWN_RUNNING)) 862 return (NULL); 863 864 rxdw0 = le32toh(stat->rxdw0); 865 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 866 /* 867 * This should not happen since we setup our Rx filter 868 * to not receive these frames. 869 */ 870 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 871 "%s: RX flags error (%s)\n", __func__, 872 rxdw0 & R92C_RXDW0_CRCERR ? "CRC" : "ICV"); 873 goto fail; 874 } 875 876 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 877 if (pktlen < sizeof(struct ieee80211_frame_ack)) { 878 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 879 "%s: frame is too short: %d\n", __func__, pktlen); 880 goto fail; 881 } 882 883 if (__predict_false(totlen > MCLBYTES)) { 884 /* convert to m_getjcl if this happens */ 885 device_printf(sc->sc_dev, "%s: frame too long: %d (%d)\n", 886 __func__, pktlen, totlen); 887 goto fail; 888 } 889 890 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 891 if (__predict_false(m == NULL)) { 892 device_printf(sc->sc_dev, "%s: could not allocate RX mbuf\n", 893 __func__); 894 goto fail; 895 } 896 897 /* Finalize mbuf. */ 898 memcpy(mtod(m, uint8_t *), (uint8_t *)stat, totlen); 899 m->m_pkthdr.len = m->m_len = totlen; 900 901 return (m); 902 fail: 903 #if defined(__DragonFly__) 904 /* unimplemented */ 905 #else 906 counter_u64_add(ic->ic_ierrors, 1); 907 #endif 908 return (NULL); 909 } 910 911 static struct mbuf * 912 urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data) 913 { 914 struct urtwn_softc *sc = data->sc; 915 /* ic not used, remove to fix gcc error */ 916 /* struct ieee80211com *ic = &sc->sc_ic;*/ 917 struct r92c_rx_stat *stat; 918 uint8_t *buf; 919 int len; 920 921 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 922 923 if (len < sizeof(*stat)) { 924 #if defined(__DragonFly__) 925 /* unimplemented */ 926 #else 927 counter_u64_add(ic->ic_ierrors, 1); 928 #endif 929 return (NULL); 930 } 931 932 buf = data->buf; 933 stat = (struct r92c_rx_stat *)buf; 934 935 /* 936 * For 88E chips we can tie the FF flushing here; 937 * this is where we do know exactly how deep the 938 * transmit queue is. 939 * 940 * But it won't work for R92 chips, so we can't 941 * take the easy way out. 942 */ 943 944 if (sc->chip & URTWN_CHIP_88E) { 945 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT); 946 947 switch (report_sel) { 948 case R88E_RXDW3_RPT_RX: 949 return (urtwn_rxeof(sc, buf, len)); 950 case R88E_RXDW3_RPT_TX1: 951 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]); 952 break; 953 default: 954 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, 955 "%s: case %d was not handled\n", __func__, 956 report_sel); 957 break; 958 } 959 } else 960 return (urtwn_rxeof(sc, buf, len)); 961 962 return (NULL); 963 } 964 965 static struct mbuf * 966 urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len) 967 { 968 struct r92c_rx_stat *stat; 969 struct mbuf *m, *m0 = NULL, *prevm = NULL; 970 uint32_t rxdw0; 971 int totlen, pktlen, infosz, npkts; 972 973 /* Get the number of encapsulated frames. */ 974 stat = (struct r92c_rx_stat *)buf; 975 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 976 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 977 "%s: Rx %d frames in one chunk\n", __func__, npkts); 978 979 /* Process all of them. */ 980 while (npkts-- > 0) { 981 if (len < sizeof(*stat)) 982 break; 983 stat = (struct r92c_rx_stat *)buf; 984 rxdw0 = le32toh(stat->rxdw0); 985 986 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 987 if (pktlen == 0) 988 break; 989 990 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 991 992 /* Make sure everything fits in xfer. */ 993 totlen = sizeof(*stat) + infosz + pktlen; 994 if (totlen > len) 995 break; 996 997 m = urtwn_rx_copy_to_mbuf(sc, stat, totlen); 998 if (m0 == NULL) 999 m0 = m; 1000 if (prevm == NULL) 1001 prevm = m; 1002 else { 1003 prevm->m_next = m; 1004 prevm = m; 1005 } 1006 1007 /* Next chunk is 128-byte aligned. */ 1008 totlen = (totlen + 127) & ~127; 1009 buf += totlen; 1010 len -= totlen; 1011 } 1012 1013 return (m0); 1014 } 1015 1016 static void 1017 urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg) 1018 { 1019 struct r88e_tx_rpt_ccx *rpt = arg; 1020 struct ieee80211vap *vap; 1021 struct ieee80211_node *ni; 1022 uint8_t macid; 1023 int ntries; 1024 1025 macid = MS(rpt->rptb1, R88E_RPTB1_MACID); 1026 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT); 1027 1028 URTWN_NT_LOCK(sc); 1029 ni = sc->node_list[macid]; 1030 if (ni != NULL) { 1031 vap = ni->ni_vap; 1032 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: frame for macid %d was" 1033 "%s sent (%d retries)\n", __func__, macid, 1034 (rpt->rptb1 & R88E_RPTB1_PKT_OK) ? "" : " not", 1035 ntries); 1036 1037 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) { 1038 ieee80211_ratectl_tx_complete(vap, ni, 1039 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL); 1040 } else { 1041 ieee80211_ratectl_tx_complete(vap, ni, 1042 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL); 1043 } 1044 } else { 1045 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: macid %d, ni is NULL\n", 1046 __func__, macid); 1047 } 1048 URTWN_NT_UNLOCK(sc); 1049 } 1050 1051 static struct ieee80211_node * 1052 urtwn_rx_frame(struct urtwn_softc *sc, struct mbuf *m, int8_t *rssi_p) 1053 { 1054 struct ieee80211com *ic = &sc->sc_ic; 1055 struct ieee80211_frame_min *wh; 1056 struct r92c_rx_stat *stat; 1057 uint32_t rxdw0, rxdw3; 1058 uint8_t rate, cipher; 1059 int8_t rssi = -127; 1060 int infosz; 1061 1062 stat = mtod(m, struct r92c_rx_stat *); 1063 rxdw0 = le32toh(stat->rxdw0); 1064 rxdw3 = le32toh(stat->rxdw3); 1065 1066 rate = MS(rxdw3, R92C_RXDW3_RATE); 1067 cipher = MS(rxdw0, R92C_RXDW0_CIPHER); 1068 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1069 1070 /* Get RSSI from PHY status descriptor if present. */ 1071 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1072 if (sc->chip & URTWN_CHIP_88E) 1073 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 1074 else 1075 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 1076 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: rssi=%d\n", __func__, rssi); 1077 /* Update our average RSSI. */ 1078 urtwn_update_avgrssi(sc, rate, rssi); 1079 } 1080 1081 if (ieee80211_radiotap_active(ic)) { 1082 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1083 1084 tap->wr_flags = 0; 1085 1086 urtwn_get_tsf(sc, &tap->wr_tsft); 1087 if (__predict_false(le32toh((uint32_t)tap->wr_tsft) < 1088 le32toh(stat->rxdw5))) { 1089 tap->wr_tsft = le32toh(tap->wr_tsft >> 32) - 1; 1090 tap->wr_tsft = (uint64_t)htole32(tap->wr_tsft) << 32; 1091 } else 1092 tap->wr_tsft &= 0xffffffff00000000; 1093 tap->wr_tsft += stat->rxdw5; 1094 1095 /* XXX 20/40? */ 1096 /* XXX shortgi? */ 1097 1098 /* Map HW rate index to 802.11 rate. */ 1099 if (!(rxdw3 & R92C_RXDW3_HT)) { 1100 tap->wr_rate = ridx2rate[rate]; 1101 } else if (rate >= 12) { /* MCS0~15. */ 1102 /* Bit 7 set means HT MCS instead of rate. */ 1103 tap->wr_rate = 0x80 | (rate - 12); 1104 } 1105 1106 /* XXX TODO: this isn't right; should use the last good RSSI */ 1107 tap->wr_dbm_antsignal = rssi; 1108 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 1109 } 1110 1111 *rssi_p = rssi; 1112 1113 /* Drop descriptor. */ 1114 m_adj(m, sizeof(*stat) + infosz); 1115 wh = mtod(m, struct ieee80211_frame_min *); 1116 1117 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1118 cipher != R92C_CAM_ALGO_NONE) { 1119 m->m_flags |= M_WEP; 1120 } 1121 1122 if (m->m_len >= sizeof(*wh)) 1123 return (ieee80211_find_rxnode(ic, wh)); 1124 1125 return (NULL); 1126 } 1127 1128 static void 1129 urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 1130 { 1131 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1132 struct ieee80211com *ic = &sc->sc_ic; 1133 struct ieee80211_node *ni; 1134 struct mbuf *m = NULL, *next; 1135 struct urtwn_data *data; 1136 int8_t nf, rssi; 1137 1138 URTWN_ASSERT_LOCKED(sc); 1139 1140 switch (USB_GET_STATE(xfer)) { 1141 case USB_ST_TRANSFERRED: 1142 data = STAILQ_FIRST(&sc->sc_rx_active); 1143 if (data == NULL) 1144 goto tr_setup; 1145 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1146 m = urtwn_report_intr(xfer, data); 1147 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1148 /* FALLTHROUGH */ 1149 case USB_ST_SETUP: 1150 tr_setup: 1151 data = STAILQ_FIRST(&sc->sc_rx_inactive); 1152 if (data == NULL) { 1153 KASSERT(m == NULL, ("mbuf isn't NULL")); 1154 goto finish; 1155 } 1156 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 1157 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 1158 usbd_xfer_set_frame_data(xfer, 0, data->buf, 1159 usbd_xfer_max_len(xfer)); 1160 usbd_transfer_submit(xfer); 1161 1162 /* 1163 * To avoid LOR we should unlock our private mutex here to call 1164 * ieee80211_input() because here is at the end of a USB 1165 * callback and safe to unlock. 1166 */ 1167 while (m != NULL) { 1168 next = m->m_next; 1169 m->m_next = NULL; 1170 1171 ni = urtwn_rx_frame(sc, m, &rssi); 1172 1173 /* Store a global last-good RSSI */ 1174 if (rssi != -127) 1175 sc->last_rssi = rssi; 1176 1177 URTWN_UNLOCK(sc); 1178 1179 nf = URTWN_NOISE_FLOOR; 1180 if (ni != NULL) { 1181 if (rssi != -127) 1182 URTWN_NODE(ni)->last_rssi = rssi; 1183 if (ni->ni_flags & IEEE80211_NODE_HT) 1184 m->m_flags |= M_AMPDU; 1185 (void)ieee80211_input(ni, m, 1186 URTWN_NODE(ni)->last_rssi - nf, nf); 1187 ieee80211_free_node(ni); 1188 } else { 1189 /* Use last good global RSSI */ 1190 (void)ieee80211_input_all(ic, m, 1191 sc->last_rssi - nf, nf); 1192 } 1193 URTWN_LOCK(sc); 1194 m = next; 1195 } 1196 break; 1197 default: 1198 /* needs it to the inactive queue due to a error. */ 1199 data = STAILQ_FIRST(&sc->sc_rx_active); 1200 if (data != NULL) { 1201 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1202 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1203 } 1204 if (error != USB_ERR_CANCELLED) { 1205 usbd_xfer_set_stall(xfer); 1206 #if defined(__DragonFly__) 1207 /* unimplemented */ 1208 #else 1209 counter_u64_add(ic->ic_ierrors, 1); 1210 #endif 1211 goto tr_setup; 1212 } 1213 break; 1214 } 1215 finish: 1216 /* Finished receive; age anything left on the FF queue by a little bump */ 1217 /* 1218 * XXX TODO: just make this a callout timer schedule so we can 1219 * flush the FF staging queue if we're approaching idle. 1220 */ 1221 #ifdef IEEE80211_SUPPORT_SUPERG 1222 URTWN_UNLOCK(sc); 1223 ieee80211_ff_age_all(ic, 1); 1224 URTWN_LOCK(sc); 1225 #endif 1226 1227 /* Kick-start more transmit in case we stalled */ 1228 urtwn_start(sc); 1229 } 1230 1231 static void 1232 urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 1233 { 1234 1235 URTWN_ASSERT_LOCKED(sc); 1236 1237 if (data->ni != NULL) /* not a beacon frame */ 1238 ieee80211_tx_complete(data->ni, data->m, status); 1239 1240 if (sc->sc_tx_n_active > 0) 1241 sc->sc_tx_n_active--; 1242 1243 data->ni = NULL; 1244 data->m = NULL; 1245 1246 sc->sc_txtimer = 0; 1247 1248 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 1249 } 1250 1251 static int 1252 urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1253 int ndata, int maxsz) 1254 { 1255 int i, error; 1256 1257 for (i = 0; i < ndata; i++) { 1258 struct urtwn_data *dp = &data[i]; 1259 dp->sc = sc; 1260 dp->m = NULL; 1261 dp->buf = kmalloc(maxsz, M_USBDEV, M_INTWAIT); 1262 if (dp->buf == NULL) { 1263 device_printf(sc->sc_dev, 1264 "could not allocate buffer\n"); 1265 error = ENOMEM; 1266 goto fail; 1267 } 1268 dp->ni = NULL; 1269 } 1270 1271 return (0); 1272 fail: 1273 urtwn_free_list(sc, data, ndata); 1274 return (error); 1275 } 1276 1277 static int 1278 urtwn_alloc_rx_list(struct urtwn_softc *sc) 1279 { 1280 int error, i; 1281 1282 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1283 URTWN_RXBUFSZ); 1284 if (error != 0) 1285 return (error); 1286 1287 STAILQ_INIT(&sc->sc_rx_active); 1288 STAILQ_INIT(&sc->sc_rx_inactive); 1289 1290 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1291 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1292 1293 return (0); 1294 } 1295 1296 static int 1297 urtwn_alloc_tx_list(struct urtwn_softc *sc) 1298 { 1299 int error, i; 1300 1301 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1302 URTWN_TXBUFSZ); 1303 if (error != 0) 1304 return (error); 1305 1306 STAILQ_INIT(&sc->sc_tx_active); 1307 STAILQ_INIT(&sc->sc_tx_inactive); 1308 STAILQ_INIT(&sc->sc_tx_pending); 1309 1310 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1311 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1312 1313 return (0); 1314 } 1315 1316 static void 1317 urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 1318 { 1319 int i; 1320 1321 for (i = 0; i < ndata; i++) { 1322 struct urtwn_data *dp = &data[i]; 1323 1324 if (dp->buf != NULL) { 1325 kfree(dp->buf, M_USBDEV); 1326 dp->buf = NULL; 1327 } 1328 if (dp->ni != NULL) { 1329 ieee80211_free_node(dp->ni); 1330 dp->ni = NULL; 1331 } 1332 } 1333 } 1334 1335 static void 1336 urtwn_free_rx_list(struct urtwn_softc *sc) 1337 { 1338 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 1339 } 1340 1341 static void 1342 urtwn_free_tx_list(struct urtwn_softc *sc) 1343 { 1344 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 1345 } 1346 1347 static void 1348 urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1349 { 1350 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1351 #ifdef IEEE80211_SUPPORT_SUPERG 1352 struct ieee80211com *ic = &sc->sc_ic; 1353 #endif 1354 struct urtwn_data *data; 1355 1356 URTWN_ASSERT_LOCKED(sc); 1357 1358 switch (USB_GET_STATE(xfer)){ 1359 case USB_ST_TRANSFERRED: 1360 data = STAILQ_FIRST(&sc->sc_tx_active); 1361 if (data == NULL) 1362 goto tr_setup; 1363 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1364 urtwn_txeof(sc, data, 0); 1365 /* FALLTHROUGH */ 1366 case USB_ST_SETUP: 1367 tr_setup: 1368 data = STAILQ_FIRST(&sc->sc_tx_pending); 1369 if (data == NULL) { 1370 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1371 "%s: empty pending queue\n", __func__); 1372 sc->sc_tx_n_active = 0; 1373 goto finish; 1374 } 1375 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1376 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1377 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1378 usbd_transfer_submit(xfer); 1379 sc->sc_tx_n_active++; 1380 break; 1381 default: 1382 data = STAILQ_FIRST(&sc->sc_tx_active); 1383 if (data == NULL) 1384 goto tr_setup; 1385 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1386 urtwn_txeof(sc, data, 1); 1387 if (error != USB_ERR_CANCELLED) { 1388 usbd_xfer_set_stall(xfer); 1389 goto tr_setup; 1390 } 1391 break; 1392 } 1393 finish: 1394 #ifdef IEEE80211_SUPPORT_SUPERG 1395 /* 1396 * If the TX active queue drops below a certain 1397 * threshold, ensure we age fast-frames out so they're 1398 * transmitted. 1399 */ 1400 if (sc->sc_tx_n_active <= 1) { 1401 /* XXX ew - net80211 should defer this for us! */ 1402 1403 /* 1404 * Note: this sc_tx_n_active currently tracks 1405 * the number of pending transmit submissions 1406 * and not the actual depth of the TX frames 1407 * pending to the hardware. That means that 1408 * we're going to end up with some sub-optimal 1409 * aggregation behaviour. 1410 */ 1411 /* 1412 * XXX TODO: just make this a callout timer schedule so we can 1413 * flush the FF staging queue if we're approaching idle. 1414 */ 1415 URTWN_UNLOCK(sc); 1416 ieee80211_ff_flush(ic, WME_AC_VO); 1417 ieee80211_ff_flush(ic, WME_AC_VI); 1418 ieee80211_ff_flush(ic, WME_AC_BE); 1419 ieee80211_ff_flush(ic, WME_AC_BK); 1420 URTWN_LOCK(sc); 1421 } 1422 #endif 1423 /* Kick-start more transmit */ 1424 urtwn_start(sc); 1425 } 1426 1427 static struct urtwn_data * 1428 _urtwn_getbuf(struct urtwn_softc *sc) 1429 { 1430 struct urtwn_data *bf; 1431 1432 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1433 if (bf != NULL) 1434 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1435 else { 1436 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1437 "%s: out of xmit buffers\n", __func__); 1438 } 1439 return (bf); 1440 } 1441 1442 static struct urtwn_data * 1443 urtwn_getbuf(struct urtwn_softc *sc) 1444 { 1445 struct urtwn_data *bf; 1446 1447 URTWN_ASSERT_LOCKED(sc); 1448 1449 bf = _urtwn_getbuf(sc); 1450 if (bf == NULL) { 1451 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: stop queue\n", 1452 __func__); 1453 } 1454 return (bf); 1455 } 1456 1457 static usb_error_t 1458 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1459 int len) 1460 { 1461 usb_device_request_t req; 1462 1463 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1464 req.bRequest = R92C_REQ_REGS; 1465 USETW(req.wValue, addr); 1466 USETW(req.wIndex, 0); 1467 USETW(req.wLength, len); 1468 return (urtwn_do_request(sc, &req, buf)); 1469 } 1470 1471 static usb_error_t 1472 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1473 { 1474 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1475 } 1476 1477 static usb_error_t 1478 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1479 { 1480 val = htole16(val); 1481 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1482 } 1483 1484 static usb_error_t 1485 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1486 { 1487 val = htole32(val); 1488 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1489 } 1490 1491 static usb_error_t 1492 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1493 int len) 1494 { 1495 usb_device_request_t req; 1496 1497 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1498 req.bRequest = R92C_REQ_REGS; 1499 USETW(req.wValue, addr); 1500 USETW(req.wIndex, 0); 1501 USETW(req.wLength, len); 1502 return (urtwn_do_request(sc, &req, buf)); 1503 } 1504 1505 static uint8_t 1506 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1507 { 1508 uint8_t val; 1509 1510 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1511 return (0xff); 1512 return (val); 1513 } 1514 1515 static uint16_t 1516 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1517 { 1518 uint16_t val; 1519 1520 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1521 return (0xffff); 1522 return (le16toh(val)); 1523 } 1524 1525 static uint32_t 1526 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1527 { 1528 uint32_t val; 1529 1530 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1531 return (0xffffffff); 1532 return (le32toh(val)); 1533 } 1534 1535 static int 1536 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1537 { 1538 struct r92c_fw_cmd cmd; 1539 usb_error_t error; 1540 int ntries; 1541 1542 if (!(sc->sc_flags & URTWN_FW_LOADED)) { 1543 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, "%s: firmware " 1544 "was not loaded; command (id %d) will be discarded\n", 1545 __func__, id); 1546 return (0); 1547 } 1548 1549 /* Wait for current FW box to be empty. */ 1550 for (ntries = 0; ntries < 100; ntries++) { 1551 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1552 break; 1553 urtwn_ms_delay(sc); 1554 } 1555 if (ntries == 100) { 1556 device_printf(sc->sc_dev, 1557 "could not send firmware command\n"); 1558 return (ETIMEDOUT); 1559 } 1560 memset(&cmd, 0, sizeof(cmd)); 1561 cmd.id = id; 1562 if (len > 3) 1563 cmd.id |= R92C_CMD_FLAG_EXT; 1564 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1565 memcpy(cmd.msg, buf, len); 1566 1567 /* Write the first word last since that will trigger the FW. */ 1568 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1569 (uint8_t *)&cmd + 4, 2); 1570 if (error != USB_ERR_NORMAL_COMPLETION) 1571 return (EIO); 1572 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1573 (uint8_t *)&cmd + 0, 4); 1574 if (error != USB_ERR_NORMAL_COMPLETION) 1575 return (EIO); 1576 1577 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1578 return (0); 1579 } 1580 1581 static void 1582 urtwn_cmdq_cb(void *arg, int pending) 1583 { 1584 struct urtwn_softc *sc = arg; 1585 struct urtwn_cmdq *item; 1586 1587 /* 1588 * Device must be powered on (via urtwn_power_on()) 1589 * before any command may be sent. 1590 */ 1591 URTWN_LOCK(sc); 1592 if (!(sc->sc_flags & URTWN_RUNNING)) { 1593 URTWN_UNLOCK(sc); 1594 return; 1595 } 1596 1597 URTWN_CMDQ_LOCK(sc); 1598 while (sc->cmdq[sc->cmdq_first].func != NULL) { 1599 item = &sc->cmdq[sc->cmdq_first]; 1600 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE; 1601 URTWN_CMDQ_UNLOCK(sc); 1602 1603 item->func(sc, &item->data); 1604 1605 URTWN_CMDQ_LOCK(sc); 1606 memset(item, 0, sizeof (*item)); 1607 } 1608 URTWN_CMDQ_UNLOCK(sc); 1609 URTWN_UNLOCK(sc); 1610 } 1611 1612 static int 1613 urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len, 1614 CMD_FUNC_PROTO) 1615 { 1616 struct ieee80211com *ic = &sc->sc_ic; 1617 1618 KASSERT(len <= sizeof(union sec_param), ("buffer overflow")); 1619 1620 URTWN_CMDQ_LOCK(sc); 1621 if (sc->cmdq[sc->cmdq_last].func != NULL) { 1622 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__); 1623 URTWN_CMDQ_UNLOCK(sc); 1624 1625 return (EAGAIN); 1626 } 1627 1628 if (ptr != NULL) 1629 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len); 1630 sc->cmdq[sc->cmdq_last].func = func; 1631 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE; 1632 URTWN_CMDQ_UNLOCK(sc); 1633 1634 ieee80211_runtask(ic, &sc->cmdq_task); 1635 1636 return (0); 1637 } 1638 1639 static __inline void 1640 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1641 { 1642 1643 sc->sc_rf_write(sc, chain, addr, val); 1644 } 1645 1646 static void 1647 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1648 uint32_t val) 1649 { 1650 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1651 SM(R92C_LSSI_PARAM_ADDR, addr) | 1652 SM(R92C_LSSI_PARAM_DATA, val)); 1653 } 1654 1655 static void 1656 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1657 uint32_t val) 1658 { 1659 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1660 SM(R88E_LSSI_PARAM_ADDR, addr) | 1661 SM(R92C_LSSI_PARAM_DATA, val)); 1662 } 1663 1664 static uint32_t 1665 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1666 { 1667 uint32_t reg[R92C_MAX_CHAINS], val; 1668 1669 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1670 if (chain != 0) 1671 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1672 1673 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1674 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1675 urtwn_ms_delay(sc); 1676 1677 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1678 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1679 R92C_HSSI_PARAM2_READ_EDGE); 1680 urtwn_ms_delay(sc); 1681 1682 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1683 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1684 urtwn_ms_delay(sc); 1685 1686 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1687 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1688 else 1689 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1690 return (MS(val, R92C_LSSI_READBACK_DATA)); 1691 } 1692 1693 static int 1694 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1695 { 1696 usb_error_t error; 1697 int ntries; 1698 1699 error = urtwn_write_4(sc, R92C_LLT_INIT, 1700 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1701 SM(R92C_LLT_INIT_ADDR, addr) | 1702 SM(R92C_LLT_INIT_DATA, data)); 1703 if (error != USB_ERR_NORMAL_COMPLETION) 1704 return (EIO); 1705 /* Wait for write operation to complete. */ 1706 for (ntries = 0; ntries < 20; ntries++) { 1707 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1708 R92C_LLT_INIT_OP_NO_ACTIVE) 1709 return (0); 1710 urtwn_ms_delay(sc); 1711 } 1712 return (ETIMEDOUT); 1713 } 1714 1715 static int 1716 urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1717 { 1718 uint32_t reg; 1719 usb_error_t error; 1720 int ntries; 1721 1722 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1723 return (EFAULT); 1724 1725 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1726 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1727 reg &= ~R92C_EFUSE_CTRL_VALID; 1728 1729 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1730 if (error != USB_ERR_NORMAL_COMPLETION) 1731 return (EIO); 1732 /* Wait for read operation to complete. */ 1733 for (ntries = 0; ntries < 100; ntries++) { 1734 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1735 if (reg & R92C_EFUSE_CTRL_VALID) 1736 break; 1737 urtwn_ms_delay(sc); 1738 } 1739 if (ntries == 100) { 1740 device_printf(sc->sc_dev, 1741 "could not read efuse byte at address 0x%x\n", 1742 sc->last_rom_addr); 1743 return (ETIMEDOUT); 1744 } 1745 1746 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1747 sc->last_rom_addr++; 1748 1749 return (0); 1750 } 1751 1752 static int 1753 urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1754 uint8_t msk) 1755 { 1756 uint8_t reg; 1757 int i, error; 1758 1759 for (i = 0; i < 4; i++) { 1760 if (msk & (1 << i)) 1761 continue; 1762 error = urtwn_efuse_read_next(sc, ®); 1763 if (error != 0) 1764 return (error); 1765 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1766 off * 8 + i * 2, reg); 1767 rom[off * 8 + i * 2 + 0] = reg; 1768 1769 error = urtwn_efuse_read_next(sc, ®); 1770 if (error != 0) 1771 return (error); 1772 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1773 off * 8 + i * 2 + 1, reg); 1774 rom[off * 8 + i * 2 + 1] = reg; 1775 } 1776 1777 return (0); 1778 } 1779 1780 #ifdef USB_DEBUG 1781 static void 1782 urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1783 { 1784 int i; 1785 1786 /* Dump ROM contents. */ 1787 device_printf(sc->sc_dev, "%s:", __func__); 1788 for (i = 0; i < size; i++) { 1789 if (i % 32 == 0) 1790 kprintf("\n%03X: ", i); 1791 else if (i % 4 == 0) 1792 kprintf(" "); 1793 1794 kprintf("%02X", rom[i]); 1795 } 1796 kprintf("\n"); 1797 } 1798 #endif 1799 1800 static int 1801 urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1802 { 1803 #define URTWN_CHK(res) do { \ 1804 if ((error = res) != 0) \ 1805 goto end; \ 1806 } while(0) 1807 uint8_t msk, off, reg; 1808 int error; 1809 1810 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1811 1812 /* Read full ROM image. */ 1813 sc->last_rom_addr = 0; 1814 memset(rom, 0xff, size); 1815 1816 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1817 while (reg != 0xff) { 1818 /* check for extended header */ 1819 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1820 off = reg >> 5; 1821 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1822 1823 if ((reg & 0x0f) != 0x0f) 1824 off = ((reg & 0xf0) >> 1) | off; 1825 else 1826 continue; 1827 } else 1828 off = reg >> 4; 1829 msk = reg & 0xf; 1830 1831 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1832 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1833 } 1834 1835 end: 1836 1837 #ifdef USB_DEBUG 1838 if (sc->sc_debug & URTWN_DEBUG_ROM) 1839 urtwn_dump_rom_contents(sc, rom, size); 1840 #endif 1841 1842 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1843 1844 if (error != 0) { 1845 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1846 __func__); 1847 } 1848 1849 return (error); 1850 #undef URTWN_CHK 1851 } 1852 1853 static int 1854 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1855 { 1856 usb_error_t error; 1857 uint32_t reg; 1858 1859 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1860 if (error != USB_ERR_NORMAL_COMPLETION) 1861 return (EIO); 1862 1863 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1864 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1865 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1866 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1867 if (error != USB_ERR_NORMAL_COMPLETION) 1868 return (EIO); 1869 } 1870 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1871 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1872 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1873 reg | R92C_SYS_FUNC_EN_ELDR); 1874 if (error != USB_ERR_NORMAL_COMPLETION) 1875 return (EIO); 1876 } 1877 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1878 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1879 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1880 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1881 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1882 if (error != USB_ERR_NORMAL_COMPLETION) 1883 return (EIO); 1884 } 1885 1886 return (0); 1887 } 1888 1889 static int 1890 urtwn_read_chipid(struct urtwn_softc *sc) 1891 { 1892 uint32_t reg; 1893 1894 if (sc->chip & URTWN_CHIP_88E) 1895 return (0); 1896 1897 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1898 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1899 return (EIO); 1900 1901 if (reg & R92C_SYS_CFG_TYPE_92C) { 1902 sc->chip |= URTWN_CHIP_92C; 1903 /* Check if it is a castrated 8192C. */ 1904 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1905 R92C_HPON_FSM_CHIP_BONDING_ID) == 1906 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1907 sc->chip |= URTWN_CHIP_92C_1T2R; 1908 } 1909 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1910 sc->chip |= URTWN_CHIP_UMC; 1911 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1912 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1913 } 1914 return (0); 1915 } 1916 1917 static int 1918 urtwn_read_rom(struct urtwn_softc *sc) 1919 { 1920 struct r92c_rom *rom = &sc->rom.r92c_rom; 1921 int error; 1922 1923 /* Read full ROM image. */ 1924 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1925 if (error != 0) 1926 return (error); 1927 1928 /* XXX Weird but this is what the vendor driver does. */ 1929 sc->last_rom_addr = 0x1fa; 1930 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1931 if (error != 0) 1932 return (error); 1933 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: PA setting=0x%x\n", __func__, 1934 sc->pa_setting); 1935 1936 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1937 1938 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1939 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type=%d\n", 1940 __func__, sc->regulatory); 1941 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1942 1943 sc->sc_rf_write = urtwn_r92c_rf_write; 1944 sc->sc_power_on = urtwn_r92c_power_on; 1945 sc->sc_power_off = urtwn_r92c_power_off; 1946 1947 return (0); 1948 } 1949 1950 static int 1951 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1952 { 1953 struct r88e_rom *rom = &sc->rom.r88e_rom; 1954 int error; 1955 1956 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(sc->rom.r88e_rom)); 1957 if (error != 0) 1958 return (error); 1959 1960 sc->bw20_tx_pwr_diff = (rom->tx_pwr_diff >> 4); 1961 if (sc->bw20_tx_pwr_diff & 0x08) 1962 sc->bw20_tx_pwr_diff |= 0xf0; 1963 sc->ofdm_tx_pwr_diff = (rom->tx_pwr_diff & 0xf); 1964 if (sc->ofdm_tx_pwr_diff & 0x08) 1965 sc->ofdm_tx_pwr_diff |= 0xf0; 1966 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 1967 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type %d\n", 1968 __func__,sc->regulatory); 1969 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1970 1971 sc->sc_rf_write = urtwn_r88e_rf_write; 1972 sc->sc_power_on = urtwn_r88e_power_on; 1973 sc->sc_power_off = urtwn_r88e_power_off; 1974 1975 return (0); 1976 } 1977 1978 static __inline uint8_t 1979 rate2ridx(uint8_t rate) 1980 { 1981 if (rate & IEEE80211_RATE_MCS) { 1982 /* 11n rates start at idx 12 */ 1983 return ((rate & 0xf) + 12); 1984 } 1985 switch (rate) { 1986 /* 11g */ 1987 case 12: return 4; 1988 case 18: return 5; 1989 case 24: return 6; 1990 case 36: return 7; 1991 case 48: return 8; 1992 case 72: return 9; 1993 case 96: return 10; 1994 case 108: return 11; 1995 /* 11b */ 1996 case 2: return 0; 1997 case 4: return 1; 1998 case 11: return 2; 1999 case 22: return 3; 2000 default: return URTWN_RIDX_UNKNOWN; 2001 } 2002 } 2003 2004 /* 2005 * Initialize rate adaptation in firmware. 2006 */ 2007 static int 2008 urtwn_ra_init(struct urtwn_softc *sc) 2009 { 2010 struct ieee80211com *ic = &sc->sc_ic; 2011 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2012 struct ieee80211_node *ni; 2013 struct ieee80211_rateset *rs, *rs_ht; 2014 struct r92c_fw_cmd_macid_cfg cmd; 2015 uint32_t rates, basicrates; 2016 uint8_t mode, ridx; 2017 int maxrate, maxbasicrate, error, i; 2018 2019 ni = ieee80211_ref_node(vap->iv_bss); 2020 rs = &ni->ni_rates; 2021 rs_ht = (struct ieee80211_rateset *) &ni->ni_htrates; 2022 2023 /* Get normal and basic rates mask. */ 2024 rates = basicrates = 0; 2025 maxrate = maxbasicrate = 0; 2026 2027 /* This is for 11bg */ 2028 for (i = 0; i < rs->rs_nrates; i++) { 2029 /* Convert 802.11 rate to HW rate index. */ 2030 ridx = rate2ridx(IEEE80211_RV(rs->rs_rates[i])); 2031 if (ridx == URTWN_RIDX_UNKNOWN) /* Unknown rate, skip. */ 2032 continue; 2033 rates |= 1 << ridx; 2034 if (ridx > maxrate) 2035 maxrate = ridx; 2036 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 2037 basicrates |= 1 << ridx; 2038 if (ridx > maxbasicrate) 2039 maxbasicrate = ridx; 2040 } 2041 } 2042 2043 /* If we're doing 11n, enable 11n rates */ 2044 if (ni->ni_flags & IEEE80211_NODE_HT) { 2045 for (i = 0; i < rs_ht->rs_nrates; i++) { 2046 if ((rs_ht->rs_rates[i] & 0x7f) > 0xf) 2047 continue; 2048 /* 11n rates start at index 12 */ 2049 ridx = ((rs_ht->rs_rates[i]) & 0xf) + 12; 2050 rates |= (1 << ridx); 2051 2052 /* Guard against the rate table being oddly ordered */ 2053 if (ridx > maxrate) 2054 maxrate = ridx; 2055 } 2056 } 2057 2058 #if 0 2059 if (ic->ic_curmode == IEEE80211_MODE_11NG) 2060 raid = R92C_RAID_11GN; 2061 #endif 2062 /* NB: group addressed frames are done at 11bg rates for now */ 2063 if (ic->ic_curmode == IEEE80211_MODE_11B) 2064 mode = R92C_RAID_11B; 2065 else 2066 mode = R92C_RAID_11BG; 2067 /* XXX misleading 'mode' value here for unicast frames */ 2068 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, 2069 "%s: mode 0x%x, rates 0x%08x, basicrates 0x%08x\n", __func__, 2070 mode, rates, basicrates); 2071 2072 /* Set rates mask for group addressed frames. */ 2073 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 2074 cmd.mask = htole32(mode << 28 | basicrates); 2075 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 2076 if (error != 0) { 2077 ieee80211_free_node(ni); 2078 device_printf(sc->sc_dev, 2079 "could not add broadcast station\n"); 2080 return (error); 2081 } 2082 2083 /* Set initial MRR rate. */ 2084 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxbasicrate %d\n", __func__, 2085 maxbasicrate); 2086 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 2087 maxbasicrate); 2088 2089 /* Set rates mask for unicast frames. */ 2090 if (ni->ni_flags & IEEE80211_NODE_HT) 2091 mode = R92C_RAID_11GN; 2092 else if (ic->ic_curmode == IEEE80211_MODE_11B) 2093 mode = R92C_RAID_11B; 2094 else 2095 mode = R92C_RAID_11BG; 2096 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 2097 cmd.mask = htole32(mode << 28 | rates); 2098 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 2099 if (error != 0) { 2100 ieee80211_free_node(ni); 2101 device_printf(sc->sc_dev, "could not add BSS station\n"); 2102 return (error); 2103 } 2104 /* Set initial MRR rate. */ 2105 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxrate %d\n", __func__, 2106 maxrate); 2107 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 2108 maxrate); 2109 2110 /* Indicate highest supported rate. */ 2111 if (ni->ni_flags & IEEE80211_NODE_HT) 2112 ni->ni_txrate = rs_ht->rs_rates[rs_ht->rs_nrates - 1] 2113 | IEEE80211_RATE_MCS; 2114 else 2115 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 2116 ieee80211_free_node(ni); 2117 2118 return (0); 2119 } 2120 2121 static void 2122 urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2123 { 2124 struct r92c_tx_desc *txd = &uvp->bcn_desc; 2125 2126 txd->txdw0 = htole32( 2127 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 2128 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2129 txd->txdw1 = htole32( 2130 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 2131 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2132 2133 if (sc->chip & URTWN_CHIP_88E) { 2134 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 2135 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 2136 } else { 2137 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 2138 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2139 } 2140 2141 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 2142 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 2143 } 2144 2145 static int 2146 urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 2147 { 2148 struct ieee80211vap *vap = ni->ni_vap; 2149 struct urtwn_vap *uvp = URTWN_VAP(vap); 2150 struct mbuf *m; 2151 int error; 2152 2153 URTWN_ASSERT_LOCKED(sc); 2154 2155 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 2156 return (EINVAL); 2157 2158 m = ieee80211_beacon_alloc(ni); 2159 if (m == NULL) { 2160 device_printf(sc->sc_dev, 2161 "%s: could not allocate beacon frame\n", __func__); 2162 return (ENOMEM); 2163 } 2164 2165 if (uvp->bcn_mbuf != NULL) 2166 m_freem(uvp->bcn_mbuf); 2167 2168 uvp->bcn_mbuf = m; 2169 2170 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 2171 return (error); 2172 2173 /* XXX bcnq stuck workaround */ 2174 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 2175 return (error); 2176 2177 URTWN_DPRINTF(sc, URTWN_DEBUG_BEACON, "%s: beacon was %srecognized\n", 2178 __func__, urtwn_read_1(sc, R92C_TDECTRL + 2) & 2179 (R92C_TDECTRL_BCN_VALID >> 16) ? "" : "not "); 2180 2181 return (0); 2182 } 2183 2184 static void 2185 urtwn_update_beacon(struct ieee80211vap *vap, int item) 2186 { 2187 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2188 struct urtwn_vap *uvp = URTWN_VAP(vap); 2189 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 2190 struct ieee80211_node *ni = vap->iv_bss; 2191 int mcast = 0; 2192 2193 URTWN_LOCK(sc); 2194 if (uvp->bcn_mbuf == NULL) { 2195 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 2196 if (uvp->bcn_mbuf == NULL) { 2197 device_printf(sc->sc_dev, 2198 "%s: could not allocate beacon frame\n", __func__); 2199 URTWN_UNLOCK(sc); 2200 return; 2201 } 2202 } 2203 URTWN_UNLOCK(sc); 2204 2205 if (item == IEEE80211_BEACON_TIM) 2206 mcast = 1; /* XXX */ 2207 2208 setbit(bo->bo_flags, item); 2209 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 2210 2211 URTWN_LOCK(sc); 2212 urtwn_tx_beacon(sc, uvp); 2213 URTWN_UNLOCK(sc); 2214 } 2215 2216 /* 2217 * Push a beacon frame into the chip. Beacon will 2218 * be repeated by the chip every R92C_BCN_INTERVAL. 2219 */ 2220 static int 2221 urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2222 { 2223 struct r92c_tx_desc *desc = &uvp->bcn_desc; 2224 struct urtwn_data *bf; 2225 2226 URTWN_ASSERT_LOCKED(sc); 2227 2228 bf = urtwn_getbuf(sc); 2229 if (bf == NULL) 2230 return (ENOMEM); 2231 2232 memcpy(bf->buf, desc, sizeof(*desc)); 2233 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 2234 2235 sc->sc_txtimer = 5; 2236 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2237 2238 return (0); 2239 } 2240 2241 static int 2242 urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2243 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2244 { 2245 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2246 uint8_t i; 2247 2248 if (!(&vap->iv_nw_keys[0] <= k && 2249 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2250 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2251 URTWN_LOCK(sc); 2252 /* 2253 * First 4 slots for group keys, 2254 * what is left - for pairwise. 2255 * XXX incompatible with IBSS RSN. 2256 */ 2257 for (i = IEEE80211_WEP_NKID; 2258 i < R92C_CAM_ENTRY_COUNT; i++) { 2259 if ((sc->keys_bmap & (1 << i)) == 0) { 2260 sc->keys_bmap |= 1 << i; 2261 *keyix = i; 2262 break; 2263 } 2264 } 2265 URTWN_UNLOCK(sc); 2266 if (i == R92C_CAM_ENTRY_COUNT) { 2267 device_printf(sc->sc_dev, 2268 "%s: no free space in the key table\n", 2269 __func__); 2270 return 0; 2271 } 2272 } else 2273 *keyix = 0; 2274 } else { 2275 *keyix = k - vap->iv_nw_keys; 2276 } 2277 *rxkeyix = *keyix; 2278 return 1; 2279 } 2280 2281 static void 2282 urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data) 2283 { 2284 struct ieee80211_key *k = &data->key; 2285 uint8_t algo, keyid; 2286 int i, error; 2287 2288 if (k->wk_keyix < IEEE80211_WEP_NKID) 2289 keyid = k->wk_keyix; 2290 else 2291 keyid = 0; 2292 2293 /* Map net80211 cipher to HW crypto algorithm. */ 2294 switch (k->wk_cipher->ic_cipher) { 2295 case IEEE80211_CIPHER_WEP: 2296 if (k->wk_keylen < 8) 2297 algo = R92C_CAM_ALGO_WEP40; 2298 else 2299 algo = R92C_CAM_ALGO_WEP104; 2300 break; 2301 case IEEE80211_CIPHER_TKIP: 2302 algo = R92C_CAM_ALGO_TKIP; 2303 break; 2304 case IEEE80211_CIPHER_AES_CCM: 2305 algo = R92C_CAM_ALGO_AES; 2306 break; 2307 default: 2308 device_printf(sc->sc_dev, "%s: undefined cipher %d\n", 2309 __func__, k->wk_cipher->ic_cipher); 2310 return; 2311 } 2312 2313 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2314 "%s: keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, " 2315 "macaddr %s\n", __func__, k->wk_keyix, keyid, 2316 k->wk_cipher->ic_cipher, algo, k->wk_flags, k->wk_keylen, 2317 ether_sprintf(k->wk_macaddr)); 2318 2319 /* Write key. */ 2320 for (i = 0; i < 4; i++) { 2321 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 2322 le32dec(&k->wk_key[i * 4])); 2323 if (error != 0) 2324 goto fail; 2325 } 2326 2327 /* Write CTL0 last since that will validate the CAM entry. */ 2328 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 2329 le32dec(&k->wk_macaddr[2])); 2330 if (error != 0) 2331 goto fail; 2332 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 2333 SM(R92C_CAM_ALGO, algo) | 2334 SM(R92C_CAM_KEYID, keyid) | 2335 SM(R92C_CAM_MACLO, le16dec(&k->wk_macaddr[0])) | 2336 R92C_CAM_VALID); 2337 if (error != 0) 2338 goto fail; 2339 2340 return; 2341 2342 fail: 2343 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error); 2344 } 2345 2346 static void 2347 urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data) 2348 { 2349 struct ieee80211_key *k = &data->key; 2350 int i; 2351 2352 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2353 "%s: keyix %d, flags %04X, macaddr %s\n", __func__, 2354 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr)); 2355 2356 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0); 2357 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0); 2358 2359 /* Clear key. */ 2360 for (i = 0; i < 4; i++) 2361 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0); 2362 sc->keys_bmap &= ~(1 << k->wk_keyix); 2363 } 2364 2365 static int 2366 urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k) 2367 { 2368 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2369 2370 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2371 /* Not for us. */ 2372 return (1); 2373 } 2374 2375 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb)); 2376 } 2377 2378 static int 2379 urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2380 { 2381 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2382 2383 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2384 /* Not for us. */ 2385 return (1); 2386 } 2387 2388 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb)); 2389 } 2390 2391 static void 2392 urtwn_tsf_task_adhoc(void *arg, int pending) 2393 { 2394 struct ieee80211vap *vap = arg; 2395 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2396 struct ieee80211_node *ni; 2397 uint32_t reg; 2398 2399 URTWN_LOCK(sc); 2400 ni = ieee80211_ref_node(vap->iv_bss); 2401 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 2402 2403 /* Accept beacons with the same BSSID. */ 2404 urtwn_set_rx_bssid_all(sc, 0); 2405 2406 /* Enable synchronization. */ 2407 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 2408 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2409 2410 /* Synchronize. */ 2411 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 2412 2413 /* Disable synchronization. */ 2414 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 2415 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2416 2417 /* Remove beacon filter. */ 2418 urtwn_set_rx_bssid_all(sc, 1); 2419 2420 /* Enable beaconing. */ 2421 urtwn_write_1(sc, R92C_MBID_NUM, 2422 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2423 reg |= R92C_BCN_CTRL_EN_BCN; 2424 2425 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2426 ieee80211_free_node(ni); 2427 URTWN_UNLOCK(sc); 2428 } 2429 2430 static void 2431 urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 2432 { 2433 struct ieee80211com *ic = &sc->sc_ic; 2434 struct urtwn_vap *uvp = URTWN_VAP(vap); 2435 2436 /* Reset TSF. */ 2437 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2438 2439 switch (vap->iv_opmode) { 2440 case IEEE80211_M_STA: 2441 /* Enable TSF synchronization. */ 2442 urtwn_write_1(sc, R92C_BCN_CTRL, 2443 urtwn_read_1(sc, R92C_BCN_CTRL) & 2444 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 2445 break; 2446 case IEEE80211_M_IBSS: 2447 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 2448 break; 2449 case IEEE80211_M_HOSTAP: 2450 /* Enable beaconing. */ 2451 urtwn_write_1(sc, R92C_MBID_NUM, 2452 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2453 urtwn_write_1(sc, R92C_BCN_CTRL, 2454 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 2455 break; 2456 default: 2457 device_printf(sc->sc_dev, "undefined opmode %d\n", 2458 vap->iv_opmode); 2459 return; 2460 } 2461 } 2462 2463 static void 2464 urtwn_get_tsf(struct urtwn_softc *sc, uint64_t *buf) 2465 { 2466 urtwn_read_region_1(sc, R92C_TSFTR, (uint8_t *)buf, sizeof(*buf)); 2467 } 2468 2469 static void 2470 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 2471 { 2472 uint8_t reg; 2473 2474 if (led == URTWN_LED_LINK) { 2475 if (sc->chip & URTWN_CHIP_88E) { 2476 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 2477 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 2478 if (!on) { 2479 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 2480 urtwn_write_1(sc, R92C_LEDCFG2, 2481 reg | R92C_LEDCFG0_DIS); 2482 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 2483 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 2484 0xfe); 2485 } 2486 } else { 2487 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 2488 if (!on) 2489 reg |= R92C_LEDCFG0_DIS; 2490 urtwn_write_1(sc, R92C_LEDCFG0, reg); 2491 } 2492 sc->ledlink = on; /* Save LED state. */ 2493 } 2494 } 2495 2496 static void 2497 urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 2498 { 2499 uint8_t reg; 2500 2501 reg = urtwn_read_1(sc, R92C_MSR); 2502 reg = (reg & ~R92C_MSR_MASK) | mode; 2503 urtwn_write_1(sc, R92C_MSR, reg); 2504 } 2505 2506 static void 2507 urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 2508 const struct ieee80211_rx_stats *rxs, 2509 int rssi, int nf) 2510 { 2511 struct ieee80211vap *vap = ni->ni_vap; 2512 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2513 struct urtwn_vap *uvp = URTWN_VAP(vap); 2514 uint64_t ni_tstamp, curr_tstamp; 2515 2516 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 2517 2518 if (vap->iv_state == IEEE80211_S_RUN && 2519 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 2520 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 2521 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 2522 URTWN_LOCK(sc); 2523 urtwn_get_tsf(sc, &curr_tstamp); 2524 URTWN_UNLOCK(sc); 2525 curr_tstamp = le64toh(curr_tstamp); 2526 2527 if (ni_tstamp >= curr_tstamp) 2528 (void) ieee80211_ibss_merge(ni); 2529 } 2530 } 2531 2532 static int 2533 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2534 { 2535 struct urtwn_vap *uvp = URTWN_VAP(vap); 2536 struct ieee80211com *ic = vap->iv_ic; 2537 struct urtwn_softc *sc = ic->ic_softc; 2538 struct ieee80211_node *ni; 2539 enum ieee80211_state ostate; 2540 uint32_t reg; 2541 uint8_t mode; 2542 int error = 0; 2543 2544 ostate = vap->iv_state; 2545 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s -> %s\n", 2546 ieee80211_state_name[ostate], ieee80211_state_name[nstate]); 2547 2548 IEEE80211_UNLOCK(ic); 2549 URTWN_LOCK(sc); 2550 callout_stop(&sc->sc_watchdog_ch); 2551 2552 if (ostate == IEEE80211_S_RUN) { 2553 /* Stop calibration. */ 2554 callout_stop(&sc->sc_calib_to); 2555 2556 /* Turn link LED off. */ 2557 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2558 2559 /* Set media status to 'No Link'. */ 2560 urtwn_set_mode(sc, R92C_MSR_NOLINK); 2561 2562 /* Stop Rx of data frames. */ 2563 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2564 2565 /* Disable TSF synchronization. */ 2566 urtwn_write_1(sc, R92C_BCN_CTRL, 2567 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 2568 R92C_BCN_CTRL_DIS_TSF_UDT0); 2569 2570 /* Disable beaconing. */ 2571 urtwn_write_1(sc, R92C_MBID_NUM, 2572 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 2573 2574 /* Reset TSF. */ 2575 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2576 2577 /* Reset EDCA parameters. */ 2578 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2579 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2580 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2581 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2582 } 2583 2584 switch (nstate) { 2585 case IEEE80211_S_INIT: 2586 /* Turn link LED off. */ 2587 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2588 break; 2589 case IEEE80211_S_SCAN: 2590 /* Pause AC Tx queues. */ 2591 urtwn_write_1(sc, R92C_TXPAUSE, 2592 urtwn_read_1(sc, R92C_TXPAUSE) | R92C_TX_QUEUE_AC); 2593 break; 2594 case IEEE80211_S_AUTH: 2595 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2596 break; 2597 case IEEE80211_S_RUN: 2598 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2599 /* Turn link LED on. */ 2600 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2601 break; 2602 } 2603 2604 ni = ieee80211_ref_node(vap->iv_bss); 2605 2606 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 2607 ni->ni_chan == IEEE80211_CHAN_ANYC) { 2608 device_printf(sc->sc_dev, 2609 "%s: could not move to RUN state\n", __func__); 2610 error = EINVAL; 2611 goto end_run; 2612 } 2613 2614 switch (vap->iv_opmode) { 2615 case IEEE80211_M_STA: 2616 mode = R92C_MSR_INFRA; 2617 break; 2618 case IEEE80211_M_IBSS: 2619 mode = R92C_MSR_ADHOC; 2620 break; 2621 case IEEE80211_M_HOSTAP: 2622 mode = R92C_MSR_AP; 2623 break; 2624 default: 2625 device_printf(sc->sc_dev, "undefined opmode %d\n", 2626 vap->iv_opmode); 2627 error = EINVAL; 2628 goto end_run; 2629 } 2630 2631 /* Set media status to 'Associated'. */ 2632 urtwn_set_mode(sc, mode); 2633 2634 /* Set BSSID. */ 2635 urtwn_write_4(sc, R92C_BSSID + 0, le32dec(&ni->ni_bssid[0])); 2636 urtwn_write_4(sc, R92C_BSSID + 4, le16dec(&ni->ni_bssid[4])); 2637 2638 if (ic->ic_curmode == IEEE80211_MODE_11B) 2639 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2640 else /* 802.11b/g */ 2641 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2642 2643 /* Enable Rx of data frames. */ 2644 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2645 2646 /* Flush all AC queues. */ 2647 urtwn_write_1(sc, R92C_TXPAUSE, 0); 2648 2649 /* Set beacon interval. */ 2650 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2651 2652 /* Allow Rx from our BSSID only. */ 2653 if (ic->ic_promisc == 0) { 2654 reg = urtwn_read_4(sc, R92C_RCR); 2655 2656 if (vap->iv_opmode != IEEE80211_M_HOSTAP) 2657 reg |= R92C_RCR_CBSSID_DATA; 2658 if (vap->iv_opmode != IEEE80211_M_IBSS) 2659 reg |= R92C_RCR_CBSSID_BCN; 2660 2661 urtwn_write_4(sc, R92C_RCR, reg); 2662 } 2663 2664 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 2665 vap->iv_opmode == IEEE80211_M_IBSS) { 2666 error = urtwn_setup_beacon(sc, ni); 2667 if (error != 0) { 2668 device_printf(sc->sc_dev, 2669 "unable to push beacon into the chip, " 2670 "error %d\n", error); 2671 goto end_run; 2672 } 2673 } 2674 2675 /* Enable TSF synchronization. */ 2676 urtwn_tsf_sync_enable(sc, vap); 2677 2678 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2679 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2680 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2681 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2682 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2683 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2684 2685 /* Intialize rate adaptation. */ 2686 if (!(sc->chip & URTWN_CHIP_88E)) 2687 urtwn_ra_init(sc); 2688 /* Turn link LED on. */ 2689 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2690 2691 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2692 /* Reset temperature calibration state machine. */ 2693 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 2694 sc->thcal_lctemp = 0; 2695 /* Start periodic calibration. */ 2696 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2697 2698 end_run: 2699 ieee80211_free_node(ni); 2700 break; 2701 default: 2702 break; 2703 } 2704 2705 URTWN_UNLOCK(sc); 2706 IEEE80211_LOCK(ic); 2707 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2708 } 2709 2710 static void 2711 urtwn_calib_to(void *arg) 2712 { 2713 struct urtwn_softc *sc = arg; 2714 2715 /* Do it in a process context. */ 2716 urtwn_cmd_sleepable(sc, NULL, 0, urtwn_calib_cb); 2717 } 2718 2719 static void 2720 urtwn_calib_cb(struct urtwn_softc *sc, union sec_param *data) 2721 { 2722 /* Do temperature compensation. */ 2723 urtwn_temp_calib(sc); 2724 2725 if ((urtwn_read_1(sc, R92C_MSR) & R92C_MSR_MASK) != R92C_MSR_NOLINK) 2726 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2727 } 2728 2729 static void 2730 urtwn_watchdog(void *arg) 2731 { 2732 struct urtwn_softc *sc = arg; 2733 2734 if (sc->sc_txtimer > 0) { 2735 if (--sc->sc_txtimer == 0) { 2736 device_printf(sc->sc_dev, "device timeout\n"); 2737 #if defined(__DragonFly__) 2738 /* unimplemented */ 2739 #else 2740 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2741 #endif 2742 return; 2743 } 2744 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2745 } 2746 } 2747 2748 static void 2749 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2750 { 2751 int pwdb; 2752 2753 /* Convert antenna signal to percentage. */ 2754 if (rssi <= -100 || rssi >= 20) 2755 pwdb = 0; 2756 else if (rssi >= 0) 2757 pwdb = 100; 2758 else 2759 pwdb = 100 + rssi; 2760 if (!(sc->chip & URTWN_CHIP_88E)) { 2761 if (rate <= URTWN_RIDX_CCK11) { 2762 /* CCK gain is smaller than OFDM/MCS gain. */ 2763 pwdb += 6; 2764 if (pwdb > 100) 2765 pwdb = 100; 2766 if (pwdb <= 14) 2767 pwdb -= 4; 2768 else if (pwdb <= 26) 2769 pwdb -= 8; 2770 else if (pwdb <= 34) 2771 pwdb -= 6; 2772 else if (pwdb <= 42) 2773 pwdb -= 2; 2774 } 2775 } 2776 if (sc->avg_pwdb == -1) /* Init. */ 2777 sc->avg_pwdb = pwdb; 2778 else if (sc->avg_pwdb < pwdb) 2779 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2780 else 2781 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2782 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: PWDB %d, EMA %d\n", __func__, 2783 pwdb, sc->avg_pwdb); 2784 } 2785 2786 static int8_t 2787 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2788 { 2789 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2790 struct r92c_rx_phystat *phy; 2791 struct r92c_rx_cck *cck; 2792 uint8_t rpt; 2793 int8_t rssi; 2794 2795 if (rate <= URTWN_RIDX_CCK11) { 2796 cck = (struct r92c_rx_cck *)physt; 2797 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2798 rpt = (cck->agc_rpt >> 5) & 0x3; 2799 rssi = (cck->agc_rpt & 0x1f) << 1; 2800 } else { 2801 rpt = (cck->agc_rpt >> 6) & 0x3; 2802 rssi = cck->agc_rpt & 0x3e; 2803 } 2804 rssi = cckoff[rpt] - rssi; 2805 } else { /* OFDM/HT. */ 2806 phy = (struct r92c_rx_phystat *)physt; 2807 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2808 } 2809 return (rssi); 2810 } 2811 2812 static int8_t 2813 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2814 { 2815 struct r92c_rx_phystat *phy; 2816 struct r88e_rx_cck *cck; 2817 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2818 int8_t rssi; 2819 2820 rssi = 0; 2821 if (rate <= URTWN_RIDX_CCK11) { 2822 cck = (struct r88e_rx_cck *)physt; 2823 cck_agc_rpt = cck->agc_rpt; 2824 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2825 vga_idx = cck_agc_rpt & 0x1f; 2826 switch (lna_idx) { 2827 case 7: 2828 if (vga_idx <= 27) 2829 rssi = -100 + 2* (27 - vga_idx); 2830 else 2831 rssi = -100; 2832 break; 2833 case 6: 2834 rssi = -48 + 2 * (2 - vga_idx); 2835 break; 2836 case 5: 2837 rssi = -42 + 2 * (7 - vga_idx); 2838 break; 2839 case 4: 2840 rssi = -36 + 2 * (7 - vga_idx); 2841 break; 2842 case 3: 2843 rssi = -24 + 2 * (7 - vga_idx); 2844 break; 2845 case 2: 2846 rssi = -12 + 2 * (5 - vga_idx); 2847 break; 2848 case 1: 2849 rssi = 8 - (2 * vga_idx); 2850 break; 2851 case 0: 2852 rssi = 14 - (2 * vga_idx); 2853 break; 2854 } 2855 rssi += 6; 2856 } else { /* OFDM/HT. */ 2857 phy = (struct r92c_rx_phystat *)physt; 2858 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2859 } 2860 return (rssi); 2861 } 2862 2863 static int 2864 urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2865 struct mbuf *m, struct urtwn_data *data) 2866 { 2867 const struct ieee80211_txparam *tp; 2868 struct ieee80211com *ic = &sc->sc_ic; 2869 struct ieee80211vap *vap = ni->ni_vap; 2870 struct ieee80211_key *k = NULL; 2871 struct ieee80211_channel *chan; 2872 struct ieee80211_frame *wh; 2873 struct r92c_tx_desc *txd; 2874 uint8_t macid, raid, rate, ridx, subtype, type, tid, qsel; 2875 int hasqos, ismcast; 2876 2877 URTWN_ASSERT_LOCKED(sc); 2878 2879 /* 2880 * Software crypto. 2881 */ 2882 wh = mtod(m, struct ieee80211_frame *); 2883 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2884 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2885 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2886 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2887 2888 /* Select TX ring for this frame. */ 2889 if (hasqos) { 2890 tid = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2891 tid &= IEEE80211_QOS_TID; 2892 } else 2893 tid = 0; 2894 2895 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ? 2896 ni->ni_chan : ic->ic_curchan; 2897 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)]; 2898 2899 /* Choose a TX rate index. */ 2900 if (type == IEEE80211_FC0_TYPE_MGT) 2901 rate = tp->mgmtrate; 2902 else if (ismcast) 2903 rate = tp->mcastrate; 2904 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2905 rate = tp->ucastrate; 2906 else if (m->m_flags & M_EAPOL) 2907 rate = tp->mgmtrate; 2908 else { 2909 if (URTWN_CHIP_HAS_RATECTL(sc)) { 2910 /* XXX pass pktlen */ 2911 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2912 rate = ni->ni_txrate; 2913 } else { 2914 /* XXX TODO: drop the default rate for 11b/11g? */ 2915 if (ni->ni_flags & IEEE80211_NODE_HT) 2916 rate = IEEE80211_RATE_MCS | 0x4; /* MCS4 */ 2917 else if (ic->ic_curmode != IEEE80211_MODE_11B) 2918 rate = 108; 2919 else 2920 rate = 22; 2921 } 2922 } 2923 2924 /* 2925 * XXX TODO: this should be per-node, for 11b versus 11bg 2926 * nodes in hostap mode 2927 */ 2928 ridx = rate2ridx(rate); 2929 if (ni->ni_flags & IEEE80211_NODE_HT) 2930 raid = R92C_RAID_11GN; 2931 else if (ic->ic_curmode != IEEE80211_MODE_11B) 2932 raid = R92C_RAID_11BG; 2933 else 2934 raid = R92C_RAID_11B; 2935 2936 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2937 k = ieee80211_crypto_encap(ni, m); 2938 if (k == NULL) { 2939 device_printf(sc->sc_dev, 2940 "ieee80211_crypto_encap returns NULL.\n"); 2941 return (ENOBUFS); 2942 } 2943 2944 /* in case packet header moved, reset pointer */ 2945 wh = mtod(m, struct ieee80211_frame *); 2946 } 2947 2948 /* Fill Tx descriptor. */ 2949 txd = (struct r92c_tx_desc *)data->buf; 2950 memset(txd, 0, sizeof(*txd)); 2951 2952 txd->txdw0 |= htole32( 2953 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2954 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2955 if (ismcast) 2956 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2957 2958 if (!ismcast) { 2959 if (sc->chip & URTWN_CHIP_88E) { 2960 struct urtwn_node *un = URTWN_NODE(ni); 2961 macid = un->id; 2962 } else 2963 macid = URTWN_MACID_BSS; 2964 2965 if (type == IEEE80211_FC0_TYPE_DATA) { 2966 qsel = tid % URTWN_MAX_TID; 2967 2968 if (sc->chip & URTWN_CHIP_88E) { 2969 txd->txdw2 |= htole32( 2970 R88E_TXDW2_AGGBK | 2971 R88E_TXDW2_CCX_RPT); 2972 } else 2973 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2974 2975 /* protmode, non-HT */ 2976 /* XXX TODO: noack frames? */ 2977 if ((rate & 0x80) == 0 && 2978 (ic->ic_flags & IEEE80211_F_USEPROT)) { 2979 switch (ic->ic_protmode) { 2980 case IEEE80211_PROT_CTSONLY: 2981 txd->txdw4 |= htole32( 2982 R92C_TXDW4_CTS2SELF | 2983 R92C_TXDW4_HWRTSEN); 2984 break; 2985 case IEEE80211_PROT_RTSCTS: 2986 txd->txdw4 |= htole32( 2987 R92C_TXDW4_RTSEN | 2988 R92C_TXDW4_HWRTSEN); 2989 break; 2990 default: 2991 break; 2992 } 2993 } 2994 2995 /* protmode, HT */ 2996 /* XXX TODO: noack frames? */ 2997 if ((rate & 0x80) && 2998 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) { 2999 txd->txdw4 |= htole32( 3000 R92C_TXDW4_RTSEN | 3001 R92C_TXDW4_HWRTSEN); 3002 } 3003 3004 /* XXX TODO: rtsrate is configurable? 24mbit may 3005 * be a bit high for RTS rate? */ 3006 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 3007 URTWN_RIDX_OFDM24)); 3008 3009 txd->txdw5 |= htole32(0x0001ff00); 3010 } else /* IEEE80211_FC0_TYPE_MGT */ 3011 qsel = R92C_TXDW1_QSEL_MGNT; 3012 } else { 3013 macid = URTWN_MACID_BC; 3014 qsel = R92C_TXDW1_QSEL_MGNT; 3015 } 3016 3017 txd->txdw1 |= htole32( 3018 SM(R92C_TXDW1_QSEL, qsel) | 3019 SM(R92C_TXDW1_RAID, raid)); 3020 3021 /* XXX TODO: 40MHZ flag? */ 3022 /* XXX TODO: AMPDU flag? (AGG_ENABLE or AGG_BREAK?) Density shift? */ 3023 /* XXX Short preamble? */ 3024 /* XXX Short-GI? */ 3025 3026 if (sc->chip & URTWN_CHIP_88E) 3027 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 3028 else 3029 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 3030 3031 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 3032 3033 /* Force this rate if needed. */ 3034 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast || 3035 (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) || 3036 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 3037 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3038 3039 if (!hasqos) { 3040 /* Use HW sequence numbering for non-QoS frames. */ 3041 if (sc->chip & URTWN_CHIP_88E) 3042 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 3043 else 3044 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 3045 } else { 3046 /* Set sequence number. */ 3047 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 3048 } 3049 3050 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 3051 uint8_t cipher; 3052 3053 switch (k->wk_cipher->ic_cipher) { 3054 case IEEE80211_CIPHER_WEP: 3055 case IEEE80211_CIPHER_TKIP: 3056 cipher = R92C_TXDW1_CIPHER_RC4; 3057 break; 3058 case IEEE80211_CIPHER_AES_CCM: 3059 cipher = R92C_TXDW1_CIPHER_AES; 3060 break; 3061 default: 3062 device_printf(sc->sc_dev, "%s: unknown cipher %d\n", 3063 __func__, k->wk_cipher->ic_cipher); 3064 return (EINVAL); 3065 } 3066 3067 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 3068 } 3069 3070 if (ieee80211_radiotap_active_vap(vap)) { 3071 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3072 3073 tap->wt_flags = 0; 3074 if (k != NULL) 3075 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3076 ieee80211_radiotap_tx(vap, m); 3077 } 3078 3079 data->ni = ni; 3080 3081 urtwn_tx_start(sc, m, type, data); 3082 3083 return (0); 3084 } 3085 3086 static int 3087 urtwn_tx_raw(struct urtwn_softc *sc, struct ieee80211_node *ni, 3088 struct mbuf *m, struct urtwn_data *data, 3089 const struct ieee80211_bpf_params *params) 3090 { 3091 struct ieee80211vap *vap = ni->ni_vap; 3092 struct ieee80211_key *k = NULL; 3093 struct ieee80211_frame *wh; 3094 struct r92c_tx_desc *txd; 3095 uint8_t cipher, ridx, type; 3096 3097 /* Encrypt the frame if need be. */ 3098 cipher = R92C_TXDW1_CIPHER_NONE; 3099 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) { 3100 /* Retrieve key for TX. */ 3101 k = ieee80211_crypto_encap(ni, m); 3102 if (k == NULL) 3103 return (ENOBUFS); 3104 3105 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 3106 switch (k->wk_cipher->ic_cipher) { 3107 case IEEE80211_CIPHER_WEP: 3108 case IEEE80211_CIPHER_TKIP: 3109 cipher = R92C_TXDW1_CIPHER_RC4; 3110 break; 3111 case IEEE80211_CIPHER_AES_CCM: 3112 cipher = R92C_TXDW1_CIPHER_AES; 3113 break; 3114 default: 3115 device_printf(sc->sc_dev, 3116 "%s: unknown cipher %d\n", 3117 __func__, k->wk_cipher->ic_cipher); 3118 return (EINVAL); 3119 } 3120 } 3121 } 3122 3123 /* XXX TODO: 11n checks, matching urtwn_tx_data() */ 3124 3125 wh = mtod(m, struct ieee80211_frame *); 3126 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3127 3128 /* Fill Tx descriptor. */ 3129 txd = (struct r92c_tx_desc *)data->buf; 3130 memset(txd, 0, sizeof(*txd)); 3131 3132 txd->txdw0 |= htole32( 3133 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 3134 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 3135 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3136 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 3137 3138 if (params->ibp_flags & IEEE80211_BPF_RTS) 3139 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN); 3140 if (params->ibp_flags & IEEE80211_BPF_CTS) 3141 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF); 3142 if (txd->txdw4 & htole32(R92C_TXDW4_RTSEN | R92C_TXDW4_CTS2SELF)) { 3143 txd->txdw4 |= htole32(R92C_TXDW4_HWRTSEN); 3144 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 3145 URTWN_RIDX_OFDM24)); 3146 } 3147 3148 if (sc->chip & URTWN_CHIP_88E) 3149 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 3150 else 3151 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 3152 3153 /* XXX TODO: rate index/config (RAID) for 11n? */ 3154 txd->txdw1 |= htole32(SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT)); 3155 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 3156 3157 /* Choose a TX rate index. */ 3158 ridx = rate2ridx(params->ibp_rate0); 3159 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 3160 txd->txdw5 |= htole32(0x0001ff00); 3161 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3162 3163 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 3164 /* Use HW sequence numbering for non-QoS frames. */ 3165 if (sc->chip & URTWN_CHIP_88E) 3166 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 3167 else 3168 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 3169 } else { 3170 /* Set sequence number. */ 3171 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 3172 } 3173 3174 if (ieee80211_radiotap_active_vap(vap)) { 3175 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3176 3177 tap->wt_flags = 0; 3178 if (k != NULL) 3179 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3180 ieee80211_radiotap_tx(vap, m); 3181 } 3182 3183 data->ni = ni; 3184 3185 urtwn_tx_start(sc, m, type, data); 3186 3187 return (0); 3188 } 3189 3190 static void 3191 urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 3192 struct urtwn_data *data) 3193 { 3194 struct usb_xfer *xfer; 3195 struct r92c_tx_desc *txd; 3196 uint16_t ac, sum; 3197 int i, xferlen; 3198 3199 URTWN_ASSERT_LOCKED(sc); 3200 3201 ac = M_WME_GETAC(m); 3202 3203 switch (type) { 3204 case IEEE80211_FC0_TYPE_CTL: 3205 case IEEE80211_FC0_TYPE_MGT: 3206 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 3207 break; 3208 default: 3209 xfer = sc->sc_xfer[wme2queue[ac].qid]; 3210 break; 3211 } 3212 3213 txd = (struct r92c_tx_desc *)data->buf; 3214 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 3215 3216 /* Compute Tx descriptor checksum. */ 3217 sum = 0; 3218 for (i = 0; i < sizeof(*txd) / 2; i++) 3219 sum ^= ((uint16_t *)txd)[i]; 3220 txd->txdsum = sum; /* NB: already little endian. */ 3221 3222 xferlen = sizeof(*txd) + m->m_pkthdr.len; 3223 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 3224 3225 data->buflen = xferlen; 3226 data->m = m; 3227 3228 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 3229 usbd_transfer_start(xfer); 3230 } 3231 3232 static int 3233 urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 3234 { 3235 struct urtwn_softc *sc = ic->ic_softc; 3236 int error; 3237 3238 URTWN_LOCK(sc); 3239 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 3240 URTWN_UNLOCK(sc); 3241 return (ENXIO); 3242 } 3243 error = mbufq_enqueue(&sc->sc_snd, m); 3244 if (error) { 3245 URTWN_UNLOCK(sc); 3246 return (error); 3247 } 3248 urtwn_start(sc); 3249 URTWN_UNLOCK(sc); 3250 3251 return (0); 3252 } 3253 3254 static void 3255 urtwn_start(struct urtwn_softc *sc) 3256 { 3257 struct ieee80211_node *ni; 3258 struct mbuf *m; 3259 struct urtwn_data *bf; 3260 3261 URTWN_ASSERT_LOCKED(sc); 3262 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 3263 bf = urtwn_getbuf(sc); 3264 if (bf == NULL) { 3265 mbufq_prepend(&sc->sc_snd, m); 3266 break; 3267 } 3268 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3269 m->m_pkthdr.rcvif = NULL; 3270 3271 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n", 3272 __func__, 3273 m); 3274 3275 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 3276 if_inc_counter(ni->ni_vap->iv_ifp, 3277 IFCOUNTER_OERRORS, 1); 3278 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3279 m_freem(m); 3280 ieee80211_free_node(ni); 3281 break; 3282 } 3283 sc->sc_txtimer = 5; 3284 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3285 } 3286 } 3287 3288 static void 3289 urtwn_parent(struct ieee80211com *ic) 3290 { 3291 struct urtwn_softc *sc = ic->ic_softc; 3292 3293 URTWN_LOCK(sc); 3294 if (sc->sc_flags & URTWN_DETACHED) { 3295 URTWN_UNLOCK(sc); 3296 return; 3297 } 3298 URTWN_UNLOCK(sc); 3299 3300 if (ic->ic_nrunning > 0) { 3301 if (urtwn_init(sc) != 0) { 3302 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3303 if (vap != NULL) 3304 ieee80211_stop(vap); 3305 } else 3306 ieee80211_start_all(ic); 3307 } else 3308 urtwn_stop(sc); 3309 } 3310 3311 static __inline int 3312 urtwn_power_on(struct urtwn_softc *sc) 3313 { 3314 3315 return sc->sc_power_on(sc); 3316 } 3317 3318 static int 3319 urtwn_r92c_power_on(struct urtwn_softc *sc) 3320 { 3321 uint32_t reg; 3322 usb_error_t error; 3323 int ntries; 3324 3325 /* Wait for autoload done bit. */ 3326 for (ntries = 0; ntries < 1000; ntries++) { 3327 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3328 break; 3329 urtwn_ms_delay(sc); 3330 } 3331 if (ntries == 1000) { 3332 device_printf(sc->sc_dev, 3333 "timeout waiting for chip autoload\n"); 3334 return (ETIMEDOUT); 3335 } 3336 3337 /* Unlock ISO/CLK/Power control register. */ 3338 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3339 if (error != USB_ERR_NORMAL_COMPLETION) 3340 return (EIO); 3341 /* Move SPS into PWM mode. */ 3342 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3343 if (error != USB_ERR_NORMAL_COMPLETION) 3344 return (EIO); 3345 urtwn_ms_delay(sc); 3346 3347 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3348 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3349 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3350 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3351 if (error != USB_ERR_NORMAL_COMPLETION) 3352 return (EIO); 3353 urtwn_ms_delay(sc); 3354 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3355 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3356 ~R92C_SYS_ISO_CTRL_MD2PP); 3357 if (error != USB_ERR_NORMAL_COMPLETION) 3358 return (EIO); 3359 } 3360 3361 /* Auto enable WLAN. */ 3362 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3363 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3364 if (error != USB_ERR_NORMAL_COMPLETION) 3365 return (EIO); 3366 for (ntries = 0; ntries < 1000; ntries++) { 3367 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3368 R92C_APS_FSMCO_APFM_ONMAC)) 3369 break; 3370 urtwn_ms_delay(sc); 3371 } 3372 if (ntries == 1000) { 3373 device_printf(sc->sc_dev, 3374 "timeout waiting for MAC auto ON\n"); 3375 return (ETIMEDOUT); 3376 } 3377 3378 /* Enable radio, GPIO and LED functions. */ 3379 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3380 R92C_APS_FSMCO_AFSM_HSUS | 3381 R92C_APS_FSMCO_PDN_EN | 3382 R92C_APS_FSMCO_PFM_ALDN); 3383 if (error != USB_ERR_NORMAL_COMPLETION) 3384 return (EIO); 3385 /* Release RF digital isolation. */ 3386 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3387 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3388 if (error != USB_ERR_NORMAL_COMPLETION) 3389 return (EIO); 3390 3391 /* Initialize MAC. */ 3392 error = urtwn_write_1(sc, R92C_APSD_CTRL, 3393 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3394 if (error != USB_ERR_NORMAL_COMPLETION) 3395 return (EIO); 3396 for (ntries = 0; ntries < 200; ntries++) { 3397 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3398 R92C_APSD_CTRL_OFF_STATUS)) 3399 break; 3400 urtwn_ms_delay(sc); 3401 } 3402 if (ntries == 200) { 3403 device_printf(sc->sc_dev, 3404 "timeout waiting for MAC initialization\n"); 3405 return (ETIMEDOUT); 3406 } 3407 3408 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3409 reg = urtwn_read_2(sc, R92C_CR); 3410 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3411 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3412 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3413 R92C_CR_ENSEC; 3414 error = urtwn_write_2(sc, R92C_CR, reg); 3415 if (error != USB_ERR_NORMAL_COMPLETION) 3416 return (EIO); 3417 3418 error = urtwn_write_1(sc, 0xfe10, 0x19); 3419 if (error != USB_ERR_NORMAL_COMPLETION) 3420 return (EIO); 3421 return (0); 3422 } 3423 3424 static int 3425 urtwn_r88e_power_on(struct urtwn_softc *sc) 3426 { 3427 uint32_t reg; 3428 usb_error_t error; 3429 int ntries; 3430 3431 /* Wait for power ready bit. */ 3432 for (ntries = 0; ntries < 5000; ntries++) { 3433 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 3434 break; 3435 urtwn_ms_delay(sc); 3436 } 3437 if (ntries == 5000) { 3438 device_printf(sc->sc_dev, 3439 "timeout waiting for chip power up\n"); 3440 return (ETIMEDOUT); 3441 } 3442 3443 /* Reset BB. */ 3444 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3445 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3446 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3447 if (error != USB_ERR_NORMAL_COMPLETION) 3448 return (EIO); 3449 3450 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3451 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3452 if (error != USB_ERR_NORMAL_COMPLETION) 3453 return (EIO); 3454 3455 /* Disable HWPDN. */ 3456 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3457 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3458 if (error != USB_ERR_NORMAL_COMPLETION) 3459 return (EIO); 3460 3461 /* Disable WL suspend. */ 3462 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3463 urtwn_read_2(sc, R92C_APS_FSMCO) & 3464 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 3465 if (error != USB_ERR_NORMAL_COMPLETION) 3466 return (EIO); 3467 3468 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3469 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3470 if (error != USB_ERR_NORMAL_COMPLETION) 3471 return (EIO); 3472 for (ntries = 0; ntries < 5000; ntries++) { 3473 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3474 R92C_APS_FSMCO_APFM_ONMAC)) 3475 break; 3476 urtwn_ms_delay(sc); 3477 } 3478 if (ntries == 5000) 3479 return (ETIMEDOUT); 3480 3481 /* Enable LDO normal mode. */ 3482 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 3483 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~R92C_LPLDO_CTRL_SLEEP); 3484 if (error != USB_ERR_NORMAL_COMPLETION) 3485 return (EIO); 3486 3487 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3488 error = urtwn_write_2(sc, R92C_CR, 0); 3489 if (error != USB_ERR_NORMAL_COMPLETION) 3490 return (EIO); 3491 reg = urtwn_read_2(sc, R92C_CR); 3492 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3493 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3494 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3495 error = urtwn_write_2(sc, R92C_CR, reg); 3496 if (error != USB_ERR_NORMAL_COMPLETION) 3497 return (EIO); 3498 3499 return (0); 3500 } 3501 3502 static __inline void 3503 urtwn_power_off(struct urtwn_softc *sc) 3504 { 3505 3506 return sc->sc_power_off(sc); 3507 } 3508 3509 static void 3510 urtwn_r92c_power_off(struct urtwn_softc *sc) 3511 { 3512 uint32_t reg; 3513 3514 /* Block all Tx queues. */ 3515 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3516 3517 /* Disable RF */ 3518 urtwn_rf_write(sc, 0, 0, 0); 3519 3520 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 3521 3522 /* Reset BB state machine */ 3523 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3524 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA | 3525 R92C_SYS_FUNC_EN_BB_GLB_RST); 3526 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3527 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 3528 3529 /* 3530 * Reset digital sequence 3531 */ 3532 #ifndef URTWN_WITHOUT_UCODE 3533 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 3534 /* Reset MCU ready status */ 3535 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3536 3537 /* If firmware in ram code, do reset */ 3538 urtwn_fw_reset(sc); 3539 } 3540 #endif 3541 3542 /* Reset MAC and Enable 8051 */ 3543 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 3544 (R92C_SYS_FUNC_EN_CPUEN | 3545 R92C_SYS_FUNC_EN_ELDR | 3546 R92C_SYS_FUNC_EN_HWPDN) >> 8); 3547 3548 /* Reset MCU ready status */ 3549 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3550 3551 /* Disable MAC clock */ 3552 urtwn_write_2(sc, R92C_SYS_CLKR, 3553 R92C_SYS_CLKR_ANAD16V_EN | 3554 R92C_SYS_CLKR_ANA8M | 3555 R92C_SYS_CLKR_LOADER_EN | 3556 R92C_SYS_CLKR_80M_SSC_DIS | 3557 R92C_SYS_CLKR_SYS_EN | 3558 R92C_SYS_CLKR_RING_EN | 3559 0x4000); 3560 3561 /* Disable AFE PLL */ 3562 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 3563 3564 /* Gated AFE DIG_CLOCK */ 3565 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 3566 3567 /* Isolated digital to PON */ 3568 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3569 R92C_SYS_ISO_CTRL_MD2PP | 3570 R92C_SYS_ISO_CTRL_PA2PCIE | 3571 R92C_SYS_ISO_CTRL_PD2CORE | 3572 R92C_SYS_ISO_CTRL_IP2MAC | 3573 R92C_SYS_ISO_CTRL_DIOP | 3574 R92C_SYS_ISO_CTRL_DIOE); 3575 3576 /* 3577 * Pull GPIO PIN to balance level and LED control 3578 */ 3579 /* 1. Disable GPIO[7:0] */ 3580 urtwn_write_2(sc, R92C_GPIO_IOSEL, 0x0000); 3581 3582 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 3583 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 3584 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 3585 3586 /* Disable GPIO[10:8] */ 3587 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x00); 3588 3589 reg = urtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0; 3590 reg |= (((reg & 0x000f) << 4) | 0x0780); 3591 urtwn_write_2(sc, R92C_GPIO_IO_SEL, reg); 3592 3593 /* Disable LED0 & 1 */ 3594 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 3595 3596 /* 3597 * Reset digital sequence 3598 */ 3599 /* Disable ELDR clock */ 3600 urtwn_write_2(sc, R92C_SYS_CLKR, 3601 R92C_SYS_CLKR_ANAD16V_EN | 3602 R92C_SYS_CLKR_ANA8M | 3603 R92C_SYS_CLKR_LOADER_EN | 3604 R92C_SYS_CLKR_80M_SSC_DIS | 3605 R92C_SYS_CLKR_SYS_EN | 3606 R92C_SYS_CLKR_RING_EN | 3607 0x4000); 3608 3609 /* Isolated ELDR to PON */ 3610 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 3611 (R92C_SYS_ISO_CTRL_DIOR | 3612 R92C_SYS_ISO_CTRL_PWC_EV12V) >> 8); 3613 3614 /* 3615 * Disable analog sequence 3616 */ 3617 /* Disable A15 power */ 3618 urtwn_write_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_OBUF); 3619 /* Disable digital core power */ 3620 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3621 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 3622 ~R92C_LDOV12D_CTRL_LDV12_EN); 3623 3624 /* Enter PFM mode */ 3625 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 3626 3627 /* Set USB suspend */ 3628 urtwn_write_2(sc, R92C_APS_FSMCO, 3629 R92C_APS_FSMCO_APDM_HOST | 3630 R92C_APS_FSMCO_AFSM_HSUS | 3631 R92C_APS_FSMCO_PFM_ALDN); 3632 3633 /* Lock ISO/CLK/Power control register. */ 3634 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 3635 } 3636 3637 static void 3638 urtwn_r88e_power_off(struct urtwn_softc *sc) 3639 { 3640 uint8_t reg; 3641 int ntries; 3642 3643 /* Disable any kind of TX reports. */ 3644 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 3645 urtwn_read_1(sc, R88E_TX_RPT_CTRL) & 3646 ~(R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA)); 3647 3648 /* Stop Rx. */ 3649 urtwn_write_1(sc, R92C_CR, 0); 3650 3651 /* Move card to Low Power State. */ 3652 /* Block all Tx queues. */ 3653 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3654 3655 for (ntries = 0; ntries < 20; ntries++) { 3656 /* Should be zero if no packet is transmitting. */ 3657 if (urtwn_read_4(sc, R88E_SCH_TXCMD) == 0) 3658 break; 3659 3660 urtwn_ms_delay(sc); 3661 } 3662 if (ntries == 20) { 3663 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", 3664 __func__); 3665 return; 3666 } 3667 3668 /* CCK and OFDM are disabled, and clock are gated. */ 3669 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3670 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_BBRSTB); 3671 3672 urtwn_ms_delay(sc); 3673 3674 /* Reset MAC TRX */ 3675 urtwn_write_1(sc, R92C_CR, 3676 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3677 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | 3678 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN); 3679 3680 /* check if removed later */ 3681 urtwn_write_1(sc, R92C_CR + 1, 3682 urtwn_read_1(sc, R92C_CR + 1) & ~(R92C_CR_ENSEC >> 8)); 3683 3684 /* Respond TxOK to scheduler */ 3685 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 3686 urtwn_read_1(sc, R92C_DUAL_TSF_RST) | 0x20); 3687 3688 /* If firmware in ram code, do reset. */ 3689 #ifndef URTWN_WITHOUT_UCODE 3690 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) 3691 urtwn_r88e_fw_reset(sc); 3692 #endif 3693 3694 /* Reset MCU ready status. */ 3695 urtwn_write_1(sc, R92C_MCUFWDL, 0x00); 3696 3697 /* Disable 32k. */ 3698 urtwn_write_1(sc, R88E_32K_CTRL, 3699 urtwn_read_1(sc, R88E_32K_CTRL) & ~0x01); 3700 3701 /* Move card to Disabled state. */ 3702 /* Turn off RF. */ 3703 urtwn_write_1(sc, R92C_RF_CTRL, 0); 3704 3705 /* LDO Sleep mode. */ 3706 urtwn_write_1(sc, R92C_LPLDO_CTRL, 3707 urtwn_read_1(sc, R92C_LPLDO_CTRL) | R92C_LPLDO_CTRL_SLEEP); 3708 3709 /* Turn off MAC by HW state machine */ 3710 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3711 urtwn_read_1(sc, R92C_APS_FSMCO + 1) | 3712 (R92C_APS_FSMCO_APFM_OFF >> 8)); 3713 3714 for (ntries = 0; ntries < 20; ntries++) { 3715 /* Wait until it will be disabled. */ 3716 if ((urtwn_read_1(sc, R92C_APS_FSMCO + 1) & 3717 (R92C_APS_FSMCO_APFM_OFF >> 8)) == 0) 3718 break; 3719 3720 urtwn_ms_delay(sc); 3721 } 3722 if (ntries == 20) { 3723 device_printf(sc->sc_dev, "%s: could not turn off MAC\n", 3724 __func__); 3725 return; 3726 } 3727 3728 /* schmit trigger */ 3729 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3730 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3731 3732 /* Enable WL suspend. */ 3733 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3734 (urtwn_read_1(sc, R92C_APS_FSMCO + 1) & ~0x10) | 0x08); 3735 3736 /* Enable bandgap mbias in suspend. */ 3737 urtwn_write_1(sc, R92C_APS_FSMCO + 3, 0); 3738 3739 /* Clear SIC_EN register. */ 3740 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 1, 3741 urtwn_read_1(sc, R92C_GPIO_MUXCFG + 1) & ~0x10); 3742 3743 /* Set USB suspend enable local register */ 3744 urtwn_write_1(sc, R92C_USB_SUSPEND, 3745 urtwn_read_1(sc, R92C_USB_SUSPEND) | 0x10); 3746 3747 /* Reset MCU IO Wrapper. */ 3748 reg = urtwn_read_1(sc, R92C_RSV_CTRL + 1); 3749 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08); 3750 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08); 3751 3752 /* marked as 'For Power Consumption' code. */ 3753 urtwn_write_1(sc, R92C_GPIO_OUT, urtwn_read_1(sc, R92C_GPIO_IN)); 3754 urtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff); 3755 3756 urtwn_write_1(sc, R92C_GPIO_IO_SEL, 3757 urtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4); 3758 urtwn_write_1(sc, R92C_GPIO_MOD, 3759 urtwn_read_1(sc, R92C_GPIO_MOD) | 0x0f); 3760 3761 /* Set LNA, TRSW, EX_PA Pin to output mode. */ 3762 urtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808); 3763 } 3764 3765 static int 3766 urtwn_llt_init(struct urtwn_softc *sc) 3767 { 3768 int i, error, page_count, pktbuf_count; 3769 3770 page_count = (sc->chip & URTWN_CHIP_88E) ? 3771 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 3772 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 3773 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 3774 3775 /* Reserve pages [0; page_count]. */ 3776 for (i = 0; i < page_count; i++) { 3777 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3778 return (error); 3779 } 3780 /* NB: 0xff indicates end-of-list. */ 3781 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3782 return (error); 3783 /* 3784 * Use pages [page_count + 1; pktbuf_count - 1] 3785 * as ring buffer. 3786 */ 3787 for (++i; i < pktbuf_count - 1; i++) { 3788 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3789 return (error); 3790 } 3791 /* Make the last page point to the beginning of the ring buffer. */ 3792 error = urtwn_llt_write(sc, i, page_count + 1); 3793 return (error); 3794 } 3795 3796 #ifndef URTWN_WITHOUT_UCODE 3797 static void 3798 urtwn_fw_reset(struct urtwn_softc *sc) 3799 { 3800 uint16_t reg; 3801 int ntries; 3802 3803 /* Tell 8051 to reset itself. */ 3804 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3805 3806 /* Wait until 8051 resets by itself. */ 3807 for (ntries = 0; ntries < 100; ntries++) { 3808 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3809 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3810 return; 3811 urtwn_ms_delay(sc); 3812 } 3813 /* Force 8051 reset. */ 3814 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3815 } 3816 3817 static void 3818 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3819 { 3820 uint16_t reg; 3821 3822 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3823 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3824 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3825 } 3826 3827 static int 3828 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 3829 { 3830 uint32_t reg; 3831 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 3832 int off, mlen; 3833 3834 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3835 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3836 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3837 3838 off = R92C_FW_START_ADDR; 3839 while (len > 0) { 3840 if (len > 196) 3841 mlen = 196; 3842 else if (len > 4) 3843 mlen = 4; 3844 else 3845 mlen = 1; 3846 /* XXX fix this deconst */ 3847 error = urtwn_write_region_1(sc, off, 3848 __DECONST(uint8_t *, buf), mlen); 3849 if (error != USB_ERR_NORMAL_COMPLETION) 3850 break; 3851 off += mlen; 3852 buf += mlen; 3853 len -= mlen; 3854 } 3855 return (error); 3856 } 3857 3858 static int 3859 urtwn_load_firmware(struct urtwn_softc *sc) 3860 { 3861 const struct firmware *fw; 3862 const struct r92c_fw_hdr *hdr; 3863 const char *imagename; 3864 const u_char *ptr; 3865 size_t len; 3866 uint32_t reg; 3867 int mlen, ntries, page, error; 3868 3869 URTWN_UNLOCK(sc); 3870 /* Read firmware image from the filesystem. */ 3871 if (sc->chip & URTWN_CHIP_88E) 3872 imagename = "urtwn-rtl8188eufw"; 3873 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3874 URTWN_CHIP_UMC_A_CUT) 3875 imagename = "urtwn-rtl8192cfwU"; 3876 else 3877 imagename = "urtwn-rtl8192cfwT"; 3878 3879 fw = firmware_get(imagename); 3880 URTWN_LOCK(sc); 3881 if (fw == NULL) { 3882 device_printf(sc->sc_dev, 3883 "failed loadfirmware of file %s\n", imagename); 3884 return (ENOENT); 3885 } 3886 3887 len = fw->datasize; 3888 3889 if (len < sizeof(*hdr)) { 3890 device_printf(sc->sc_dev, "firmware too short\n"); 3891 error = EINVAL; 3892 goto fail; 3893 } 3894 ptr = fw->data; 3895 hdr = (const struct r92c_fw_hdr *)ptr; 3896 /* Check if there is a valid FW header and skip it. */ 3897 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3898 (le16toh(hdr->signature) >> 4) == 0x88e || 3899 (le16toh(hdr->signature) >> 4) == 0x92c) { 3900 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, 3901 "FW V%d.%d %02d-%02d %02d:%02d\n", 3902 le16toh(hdr->version), le16toh(hdr->subversion), 3903 hdr->month, hdr->date, hdr->hour, hdr->minute); 3904 ptr += sizeof(*hdr); 3905 len -= sizeof(*hdr); 3906 } 3907 3908 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3909 if (sc->chip & URTWN_CHIP_88E) 3910 urtwn_r88e_fw_reset(sc); 3911 else 3912 urtwn_fw_reset(sc); 3913 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3914 } 3915 3916 if (!(sc->chip & URTWN_CHIP_88E)) { 3917 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3918 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3919 R92C_SYS_FUNC_EN_CPUEN); 3920 } 3921 urtwn_write_1(sc, R92C_MCUFWDL, 3922 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3923 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3924 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3925 3926 /* Reset the FWDL checksum. */ 3927 urtwn_write_1(sc, R92C_MCUFWDL, 3928 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3929 3930 for (page = 0; len > 0; page++) { 3931 mlen = min(len, R92C_FW_PAGE_SIZE); 3932 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3933 if (error != 0) { 3934 device_printf(sc->sc_dev, 3935 "could not load firmware page\n"); 3936 goto fail; 3937 } 3938 ptr += mlen; 3939 len -= mlen; 3940 } 3941 urtwn_write_1(sc, R92C_MCUFWDL, 3942 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3943 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3944 3945 /* Wait for checksum report. */ 3946 for (ntries = 0; ntries < 1000; ntries++) { 3947 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3948 break; 3949 urtwn_ms_delay(sc); 3950 } 3951 if (ntries == 1000) { 3952 device_printf(sc->sc_dev, 3953 "timeout waiting for checksum report\n"); 3954 error = ETIMEDOUT; 3955 goto fail; 3956 } 3957 3958 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3959 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3960 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3961 if (sc->chip & URTWN_CHIP_88E) 3962 urtwn_r88e_fw_reset(sc); 3963 /* Wait for firmware readiness. */ 3964 for (ntries = 0; ntries < 1000; ntries++) { 3965 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3966 break; 3967 urtwn_ms_delay(sc); 3968 } 3969 if (ntries == 1000) { 3970 device_printf(sc->sc_dev, 3971 "timeout waiting for firmware readiness\n"); 3972 error = ETIMEDOUT; 3973 goto fail; 3974 } 3975 fail: 3976 firmware_put(fw, FIRMWARE_UNLOAD); 3977 return (error); 3978 } 3979 #endif 3980 3981 static int 3982 urtwn_dma_init(struct urtwn_softc *sc) 3983 { 3984 struct usb_endpoint *ep, *ep_end; 3985 usb_error_t usb_err; 3986 uint32_t reg; 3987 int hashq, hasnq, haslq, nqueues, ntx; 3988 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 3989 3990 /* Initialize LLT table. */ 3991 error = urtwn_llt_init(sc); 3992 if (error != 0) 3993 return (error); 3994 3995 /* Determine the number of bulk-out pipes. */ 3996 ntx = 0; 3997 ep = sc->sc_udev->endpoints; 3998 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 3999 for (; ep != ep_end; ep++) { 4000 if ((ep->edesc == NULL) || 4001 (ep->iface_index != sc->sc_iface_index)) 4002 continue; 4003 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 4004 ntx++; 4005 } 4006 if (ntx == 0) { 4007 device_printf(sc->sc_dev, 4008 "%d: invalid number of Tx bulk pipes\n", ntx); 4009 return (EIO); 4010 } 4011 4012 /* Get Tx queues to USB endpoints mapping. */ 4013 hashq = hasnq = haslq = nqueues = 0; 4014 switch (ntx) { 4015 case 1: hashq = 1; break; 4016 case 2: hashq = hasnq = 1; break; 4017 case 3: case 4: hashq = hasnq = haslq = 1; break; 4018 } 4019 nqueues = hashq + hasnq + haslq; 4020 if (nqueues == 0) 4021 return (EIO); 4022 4023 npubqpages = nqpages = nrempages = pagecount = 0; 4024 if (sc->chip & URTWN_CHIP_88E) 4025 tx_boundary = R88E_TX_PAGE_BOUNDARY; 4026 else { 4027 pagecount = R92C_TX_PAGE_COUNT; 4028 npubqpages = R92C_PUBQ_NPAGES; 4029 tx_boundary = R92C_TX_PAGE_BOUNDARY; 4030 } 4031 4032 /* Set number of pages for normal priority queue. */ 4033 if (sc->chip & URTWN_CHIP_88E) { 4034 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 4035 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4036 return (EIO); 4037 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 4038 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4039 return (EIO); 4040 } else { 4041 /* Get the number of pages for each queue. */ 4042 nqpages = (pagecount - npubqpages) / nqueues; 4043 /* 4044 * The remaining pages are assigned to the high priority 4045 * queue. 4046 */ 4047 nrempages = (pagecount - npubqpages) % nqueues; 4048 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 4049 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4050 return (EIO); 4051 usb_err = urtwn_write_4(sc, R92C_RQPN, 4052 /* Set number of pages for public queue. */ 4053 SM(R92C_RQPN_PUBQ, npubqpages) | 4054 /* Set number of pages for high priority queue. */ 4055 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 4056 /* Set number of pages for low priority queue. */ 4057 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 4058 /* Load values. */ 4059 R92C_RQPN_LD); 4060 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4061 return (EIO); 4062 } 4063 4064 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 4065 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4066 return (EIO); 4067 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 4068 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4069 return (EIO); 4070 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 4071 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4072 return (EIO); 4073 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 4074 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4075 return (EIO); 4076 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 4077 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4078 return (EIO); 4079 4080 /* Set queue to USB pipe mapping. */ 4081 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4082 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4083 if (nqueues == 1) { 4084 if (hashq) 4085 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 4086 else if (hasnq) 4087 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 4088 else 4089 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4090 } else if (nqueues == 2) { 4091 /* 4092 * All 2-endpoints configs have high and normal 4093 * priority queues. 4094 */ 4095 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4096 } else 4097 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4098 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4099 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4100 return (EIO); 4101 4102 /* Set Tx/Rx transfer page boundary. */ 4103 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 4104 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 4105 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4106 return (EIO); 4107 4108 /* Set Tx/Rx transfer page size. */ 4109 usb_err = urtwn_write_1(sc, R92C_PBP, 4110 SM(R92C_PBP_PSRX, R92C_PBP_128) | 4111 SM(R92C_PBP_PSTX, R92C_PBP_128)); 4112 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4113 return (EIO); 4114 4115 return (0); 4116 } 4117 4118 static int 4119 urtwn_mac_init(struct urtwn_softc *sc) 4120 { 4121 usb_error_t error; 4122 int i; 4123 4124 /* Write MAC initialization values. */ 4125 if (sc->chip & URTWN_CHIP_88E) { 4126 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 4127 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 4128 rtl8188eu_mac[i].val); 4129 if (error != USB_ERR_NORMAL_COMPLETION) 4130 return (EIO); 4131 } 4132 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 4133 } else { 4134 for (i = 0; i < nitems(rtl8192cu_mac); i++) { 4135 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 4136 rtl8192cu_mac[i].val); 4137 if (error != USB_ERR_NORMAL_COMPLETION) 4138 return (EIO); 4139 } 4140 } 4141 4142 return (0); 4143 } 4144 4145 static void 4146 urtwn_bb_init(struct urtwn_softc *sc) 4147 { 4148 const struct urtwn_bb_prog *prog; 4149 uint32_t reg; 4150 uint8_t crystalcap; 4151 int i; 4152 4153 /* Enable BB and RF. */ 4154 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4155 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4156 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 4157 R92C_SYS_FUNC_EN_DIO_RF); 4158 4159 if (!(sc->chip & URTWN_CHIP_88E)) 4160 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 4161 4162 urtwn_write_1(sc, R92C_RF_CTRL, 4163 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 4164 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4165 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 4166 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 4167 4168 if (!(sc->chip & URTWN_CHIP_88E)) { 4169 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 4170 urtwn_write_1(sc, 0x15, 0xe9); 4171 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 4172 } 4173 4174 /* Select BB programming based on board type. */ 4175 if (sc->chip & URTWN_CHIP_88E) 4176 prog = &rtl8188eu_bb_prog; 4177 else if (!(sc->chip & URTWN_CHIP_92C)) { 4178 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4179 prog = &rtl8188ce_bb_prog; 4180 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4181 prog = &rtl8188ru_bb_prog; 4182 else 4183 prog = &rtl8188cu_bb_prog; 4184 } else { 4185 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4186 prog = &rtl8192ce_bb_prog; 4187 else 4188 prog = &rtl8192cu_bb_prog; 4189 } 4190 /* Write BB initialization values. */ 4191 for (i = 0; i < prog->count; i++) { 4192 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 4193 urtwn_ms_delay(sc); 4194 } 4195 4196 if (sc->chip & URTWN_CHIP_92C_1T2R) { 4197 /* 8192C 1T only configuration. */ 4198 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 4199 reg = (reg & ~0x00000003) | 0x2; 4200 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 4201 4202 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 4203 reg = (reg & ~0x00300033) | 0x00200022; 4204 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 4205 4206 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 4207 reg = (reg & ~0xff000000) | 0x45 << 24; 4208 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 4209 4210 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4211 reg = (reg & ~0x000000ff) | 0x23; 4212 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 4213 4214 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 4215 reg = (reg & ~0x00000030) | 1 << 4; 4216 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 4217 4218 reg = urtwn_bb_read(sc, 0xe74); 4219 reg = (reg & ~0x0c000000) | 2 << 26; 4220 urtwn_bb_write(sc, 0xe74, reg); 4221 reg = urtwn_bb_read(sc, 0xe78); 4222 reg = (reg & ~0x0c000000) | 2 << 26; 4223 urtwn_bb_write(sc, 0xe78, reg); 4224 reg = urtwn_bb_read(sc, 0xe7c); 4225 reg = (reg & ~0x0c000000) | 2 << 26; 4226 urtwn_bb_write(sc, 0xe7c, reg); 4227 reg = urtwn_bb_read(sc, 0xe80); 4228 reg = (reg & ~0x0c000000) | 2 << 26; 4229 urtwn_bb_write(sc, 0xe80, reg); 4230 reg = urtwn_bb_read(sc, 0xe88); 4231 reg = (reg & ~0x0c000000) | 2 << 26; 4232 urtwn_bb_write(sc, 0xe88, reg); 4233 } 4234 4235 /* Write AGC values. */ 4236 for (i = 0; i < prog->agccount; i++) { 4237 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 4238 prog->agcvals[i]); 4239 urtwn_ms_delay(sc); 4240 } 4241 4242 if (sc->chip & URTWN_CHIP_88E) { 4243 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 4244 urtwn_ms_delay(sc); 4245 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 4246 urtwn_ms_delay(sc); 4247 4248 crystalcap = sc->rom.r88e_rom.crystalcap; 4249 if (crystalcap == 0xff) 4250 crystalcap = 0x20; 4251 crystalcap &= 0x3f; 4252 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 4253 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 4254 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4255 crystalcap | crystalcap << 6)); 4256 } else { 4257 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 4258 R92C_HSSI_PARAM2_CCK_HIPWR) 4259 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 4260 } 4261 } 4262 4263 static void 4264 urtwn_rf_init(struct urtwn_softc *sc) 4265 { 4266 const struct urtwn_rf_prog *prog; 4267 uint32_t reg, type; 4268 int i, j, idx, off; 4269 4270 /* Select RF programming based on board type. */ 4271 if (sc->chip & URTWN_CHIP_88E) 4272 prog = rtl8188eu_rf_prog; 4273 else if (!(sc->chip & URTWN_CHIP_92C)) { 4274 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4275 prog = rtl8188ce_rf_prog; 4276 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4277 prog = rtl8188ru_rf_prog; 4278 else 4279 prog = rtl8188cu_rf_prog; 4280 } else 4281 prog = rtl8192ce_rf_prog; 4282 4283 for (i = 0; i < sc->nrxchains; i++) { 4284 /* Save RF_ENV control type. */ 4285 idx = i / 2; 4286 off = (i % 2) * 16; 4287 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4288 type = (reg >> off) & 0x10; 4289 4290 /* Set RF_ENV enable. */ 4291 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4292 reg |= 0x100000; 4293 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4294 urtwn_ms_delay(sc); 4295 /* Set RF_ENV output high. */ 4296 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4297 reg |= 0x10; 4298 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4299 urtwn_ms_delay(sc); 4300 /* Set address and data lengths of RF registers. */ 4301 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4302 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4303 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4304 urtwn_ms_delay(sc); 4305 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4306 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4307 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4308 urtwn_ms_delay(sc); 4309 4310 /* Write RF initialization values for this chain. */ 4311 for (j = 0; j < prog[i].count; j++) { 4312 if (prog[i].regs[j] >= 0xf9 && 4313 prog[i].regs[j] <= 0xfe) { 4314 /* 4315 * These are fake RF registers offsets that 4316 * indicate a delay is required. 4317 */ 4318 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 4319 continue; 4320 } 4321 urtwn_rf_write(sc, i, prog[i].regs[j], 4322 prog[i].vals[j]); 4323 urtwn_ms_delay(sc); 4324 } 4325 4326 /* Restore RF_ENV control type. */ 4327 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4328 reg &= ~(0x10 << off) | (type << off); 4329 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 4330 4331 /* Cache RF register CHNLBW. */ 4332 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4333 } 4334 4335 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4336 URTWN_CHIP_UMC_A_CUT) { 4337 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4338 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4339 } 4340 } 4341 4342 static void 4343 urtwn_cam_init(struct urtwn_softc *sc) 4344 { 4345 /* Invalidate all CAM entries. */ 4346 urtwn_write_4(sc, R92C_CAMCMD, 4347 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4348 } 4349 4350 static int 4351 urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 4352 { 4353 usb_error_t error; 4354 4355 error = urtwn_write_4(sc, R92C_CAMWRITE, data); 4356 if (error != USB_ERR_NORMAL_COMPLETION) 4357 return (EIO); 4358 error = urtwn_write_4(sc, R92C_CAMCMD, 4359 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 4360 SM(R92C_CAMCMD_ADDR, addr)); 4361 if (error != USB_ERR_NORMAL_COMPLETION) 4362 return (EIO); 4363 4364 return (0); 4365 } 4366 4367 static void 4368 urtwn_pa_bias_init(struct urtwn_softc *sc) 4369 { 4370 uint8_t reg; 4371 int i; 4372 4373 for (i = 0; i < sc->nrxchains; i++) { 4374 if (sc->pa_setting & (1 << i)) 4375 continue; 4376 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4377 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4378 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4379 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4380 } 4381 if (!(sc->pa_setting & 0x10)) { 4382 reg = urtwn_read_1(sc, 0x16); 4383 reg = (reg & ~0xf0) | 0x90; 4384 urtwn_write_1(sc, 0x16, reg); 4385 } 4386 } 4387 4388 static void 4389 urtwn_rxfilter_init(struct urtwn_softc *sc) 4390 { 4391 struct ieee80211com *ic = &sc->sc_ic; 4392 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4393 uint32_t rcr; 4394 uint16_t filter; 4395 4396 URTWN_ASSERT_LOCKED(sc); 4397 4398 /* Setup multicast filter. */ 4399 urtwn_set_multi(sc); 4400 4401 /* Filter for management frames. */ 4402 filter = 0x7f3f; 4403 switch (vap->iv_opmode) { 4404 case IEEE80211_M_STA: 4405 filter &= ~( 4406 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 4407 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 4408 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 4409 break; 4410 case IEEE80211_M_HOSTAP: 4411 filter &= ~( 4412 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 4413 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP)); 4414 break; 4415 case IEEE80211_M_MONITOR: 4416 case IEEE80211_M_IBSS: 4417 break; 4418 default: 4419 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4420 __func__, vap->iv_opmode); 4421 break; 4422 } 4423 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 4424 4425 /* Reject all control frames. */ 4426 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4427 4428 /* Reject all data frames. */ 4429 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 4430 4431 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 4432 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 4433 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 4434 4435 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 4436 /* Accept all frames. */ 4437 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 4438 R92C_RCR_AAP; 4439 } 4440 4441 /* Set Rx filter. */ 4442 urtwn_write_4(sc, R92C_RCR, rcr); 4443 4444 if (ic->ic_promisc != 0) { 4445 /* Update Rx filter. */ 4446 urtwn_set_promisc(sc); 4447 } 4448 } 4449 4450 static void 4451 urtwn_edca_init(struct urtwn_softc *sc) 4452 { 4453 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4454 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4455 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4456 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4457 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4458 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4459 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4460 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4461 } 4462 4463 static void 4464 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4465 uint16_t power[URTWN_RIDX_COUNT]) 4466 { 4467 uint32_t reg; 4468 4469 /* Write per-CCK rate Tx power. */ 4470 if (chain == 0) { 4471 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4472 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4473 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4474 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4475 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4476 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4477 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4478 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4479 } else { 4480 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4481 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4482 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4483 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4484 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4485 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4486 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4487 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4488 } 4489 /* Write per-OFDM rate Tx power. */ 4490 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4491 SM(R92C_TXAGC_RATE06, power[ 4]) | 4492 SM(R92C_TXAGC_RATE09, power[ 5]) | 4493 SM(R92C_TXAGC_RATE12, power[ 6]) | 4494 SM(R92C_TXAGC_RATE18, power[ 7])); 4495 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4496 SM(R92C_TXAGC_RATE24, power[ 8]) | 4497 SM(R92C_TXAGC_RATE36, power[ 9]) | 4498 SM(R92C_TXAGC_RATE48, power[10]) | 4499 SM(R92C_TXAGC_RATE54, power[11])); 4500 /* Write per-MCS Tx power. */ 4501 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4502 SM(R92C_TXAGC_MCS00, power[12]) | 4503 SM(R92C_TXAGC_MCS01, power[13]) | 4504 SM(R92C_TXAGC_MCS02, power[14]) | 4505 SM(R92C_TXAGC_MCS03, power[15])); 4506 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4507 SM(R92C_TXAGC_MCS04, power[16]) | 4508 SM(R92C_TXAGC_MCS05, power[17]) | 4509 SM(R92C_TXAGC_MCS06, power[18]) | 4510 SM(R92C_TXAGC_MCS07, power[19])); 4511 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4512 SM(R92C_TXAGC_MCS08, power[20]) | 4513 SM(R92C_TXAGC_MCS09, power[21]) | 4514 SM(R92C_TXAGC_MCS10, power[22]) | 4515 SM(R92C_TXAGC_MCS11, power[23])); 4516 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4517 SM(R92C_TXAGC_MCS12, power[24]) | 4518 SM(R92C_TXAGC_MCS13, power[25]) | 4519 SM(R92C_TXAGC_MCS14, power[26]) | 4520 SM(R92C_TXAGC_MCS15, power[27])); 4521 } 4522 4523 static void 4524 urtwn_get_txpower(struct urtwn_softc *sc, int chain, 4525 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4526 uint16_t power[URTWN_RIDX_COUNT]) 4527 { 4528 struct ieee80211com *ic = &sc->sc_ic; 4529 struct r92c_rom *rom = &sc->rom.r92c_rom; 4530 uint16_t cckpow, ofdmpow, htpow, diff, max; 4531 const struct urtwn_txpwr *base; 4532 int ridx, chan, group; 4533 4534 /* Determine channel group. */ 4535 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4536 if (chan <= 3) 4537 group = 0; 4538 else if (chan <= 9) 4539 group = 1; 4540 else 4541 group = 2; 4542 4543 /* Get original Tx power based on board type and RF chain. */ 4544 if (!(sc->chip & URTWN_CHIP_92C)) { 4545 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4546 base = &rtl8188ru_txagc[chain]; 4547 else 4548 base = &rtl8192cu_txagc[chain]; 4549 } else 4550 base = &rtl8192cu_txagc[chain]; 4551 4552 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4553 if (sc->regulatory == 0) { 4554 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4555 power[ridx] = base->pwr[0][ridx]; 4556 } 4557 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4558 if (sc->regulatory == 3) { 4559 power[ridx] = base->pwr[0][ridx]; 4560 /* Apply vendor limits. */ 4561 if (extc != NULL) 4562 max = rom->ht40_max_pwr[group]; 4563 else 4564 max = rom->ht20_max_pwr[group]; 4565 max = (max >> (chain * 4)) & 0xf; 4566 if (power[ridx] > max) 4567 power[ridx] = max; 4568 } else if (sc->regulatory == 1) { 4569 if (extc == NULL) 4570 power[ridx] = base->pwr[group][ridx]; 4571 } else if (sc->regulatory != 2) 4572 power[ridx] = base->pwr[0][ridx]; 4573 } 4574 4575 /* Compute per-CCK rate Tx power. */ 4576 cckpow = rom->cck_tx_pwr[chain][group]; 4577 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4578 power[ridx] += cckpow; 4579 if (power[ridx] > R92C_MAX_TX_PWR) 4580 power[ridx] = R92C_MAX_TX_PWR; 4581 } 4582 4583 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4584 if (sc->ntxchains > 1) { 4585 /* Apply reduction for 2 spatial streams. */ 4586 diff = rom->ht40_2s_tx_pwr_diff[group]; 4587 diff = (diff >> (chain * 4)) & 0xf; 4588 htpow = (htpow > diff) ? htpow - diff : 0; 4589 } 4590 4591 /* Compute per-OFDM rate Tx power. */ 4592 diff = rom->ofdm_tx_pwr_diff[group]; 4593 diff = (diff >> (chain * 4)) & 0xf; 4594 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4595 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4596 power[ridx] += ofdmpow; 4597 if (power[ridx] > R92C_MAX_TX_PWR) 4598 power[ridx] = R92C_MAX_TX_PWR; 4599 } 4600 4601 /* Compute per-MCS Tx power. */ 4602 if (extc == NULL) { 4603 diff = rom->ht20_tx_pwr_diff[group]; 4604 diff = (diff >> (chain * 4)) & 0xf; 4605 htpow += diff; /* HT40->HT20 correction. */ 4606 } 4607 for (ridx = 12; ridx <= 27; ridx++) { 4608 power[ridx] += htpow; 4609 if (power[ridx] > R92C_MAX_TX_PWR) 4610 power[ridx] = R92C_MAX_TX_PWR; 4611 } 4612 #ifdef USB_DEBUG 4613 if (sc->sc_debug & URTWN_DEBUG_TXPWR) { 4614 /* Dump per-rate Tx power values. */ 4615 kprintf("Tx power for chain %d:\n", chain); 4616 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 4617 kprintf("Rate %d = %u\n", ridx, power[ridx]); 4618 } 4619 #endif 4620 } 4621 4622 static void 4623 urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 4624 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4625 uint16_t power[URTWN_RIDX_COUNT]) 4626 { 4627 struct ieee80211com *ic = &sc->sc_ic; 4628 struct r88e_rom *rom = &sc->rom.r88e_rom; 4629 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4630 const struct urtwn_r88e_txpwr *base; 4631 int ridx, chan, group; 4632 4633 /* Determine channel group. */ 4634 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4635 if (chan <= 2) 4636 group = 0; 4637 else if (chan <= 5) 4638 group = 1; 4639 else if (chan <= 8) 4640 group = 2; 4641 else if (chan <= 11) 4642 group = 3; 4643 else if (chan <= 13) 4644 group = 4; 4645 else 4646 group = 5; 4647 4648 /* Get original Tx power based on board type and RF chain. */ 4649 base = &rtl8188eu_txagc[chain]; 4650 4651 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4652 if (sc->regulatory == 0) { 4653 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4654 power[ridx] = base->pwr[0][ridx]; 4655 } 4656 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4657 if (sc->regulatory == 3) 4658 power[ridx] = base->pwr[0][ridx]; 4659 else if (sc->regulatory == 1) { 4660 if (extc == NULL) 4661 power[ridx] = base->pwr[group][ridx]; 4662 } else if (sc->regulatory != 2) 4663 power[ridx] = base->pwr[0][ridx]; 4664 } 4665 4666 /* Compute per-CCK rate Tx power. */ 4667 cckpow = rom->cck_tx_pwr[group]; 4668 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4669 power[ridx] += cckpow; 4670 if (power[ridx] > R92C_MAX_TX_PWR) 4671 power[ridx] = R92C_MAX_TX_PWR; 4672 } 4673 4674 htpow = rom->ht40_tx_pwr[group]; 4675 4676 /* Compute per-OFDM rate Tx power. */ 4677 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4678 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4679 power[ridx] += ofdmpow; 4680 if (power[ridx] > R92C_MAX_TX_PWR) 4681 power[ridx] = R92C_MAX_TX_PWR; 4682 } 4683 4684 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4685 for (ridx = 12; ridx <= 27; ridx++) { 4686 power[ridx] += bw20pow; 4687 if (power[ridx] > R92C_MAX_TX_PWR) 4688 power[ridx] = R92C_MAX_TX_PWR; 4689 } 4690 } 4691 4692 static void 4693 urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 4694 struct ieee80211_channel *extc) 4695 { 4696 uint16_t power[URTWN_RIDX_COUNT]; 4697 int i; 4698 4699 for (i = 0; i < sc->ntxchains; i++) { 4700 /* Compute per-rate Tx power values. */ 4701 if (sc->chip & URTWN_CHIP_88E) 4702 urtwn_r88e_get_txpower(sc, i, c, extc, power); 4703 else 4704 urtwn_get_txpower(sc, i, c, extc, power); 4705 /* Write per-rate Tx power values to hardware. */ 4706 urtwn_write_txpower(sc, i, power); 4707 } 4708 } 4709 4710 static void 4711 urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 4712 { 4713 uint32_t reg; 4714 4715 reg = urtwn_read_4(sc, R92C_RCR); 4716 if (enable) 4717 reg &= ~R92C_RCR_CBSSID_BCN; 4718 else 4719 reg |= R92C_RCR_CBSSID_BCN; 4720 urtwn_write_4(sc, R92C_RCR, reg); 4721 } 4722 4723 static void 4724 urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 4725 { 4726 uint32_t reg; 4727 4728 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 4729 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4730 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 4731 4732 if (!(sc->chip & URTWN_CHIP_88E)) { 4733 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 4734 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4735 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 4736 } 4737 } 4738 4739 static void 4740 urtwn_scan_start(struct ieee80211com *ic) 4741 { 4742 struct urtwn_softc *sc = ic->ic_softc; 4743 4744 URTWN_LOCK(sc); 4745 /* Receive beacons / probe responses from any BSSID. */ 4746 if (ic->ic_opmode != IEEE80211_M_IBSS) 4747 urtwn_set_rx_bssid_all(sc, 1); 4748 4749 /* Set gain for scanning. */ 4750 urtwn_set_gain(sc, 0x20); 4751 URTWN_UNLOCK(sc); 4752 } 4753 4754 static void 4755 urtwn_scan_end(struct ieee80211com *ic) 4756 { 4757 struct urtwn_softc *sc = ic->ic_softc; 4758 4759 URTWN_LOCK(sc); 4760 /* Restore limitations. */ 4761 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 4762 urtwn_set_rx_bssid_all(sc, 0); 4763 4764 /* Set gain under link. */ 4765 urtwn_set_gain(sc, 0x32); 4766 URTWN_UNLOCK(sc); 4767 } 4768 4769 static void 4770 urtwn_set_channel(struct ieee80211com *ic) 4771 { 4772 struct urtwn_softc *sc = ic->ic_softc; 4773 struct ieee80211_channel *c = ic->ic_curchan; 4774 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4775 4776 URTWN_LOCK(sc); 4777 if (vap->iv_state == IEEE80211_S_SCAN) { 4778 /* Make link LED blink during scan. */ 4779 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 4780 } 4781 urtwn_set_chan(sc, c, NULL); 4782 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 4783 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 4784 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 4785 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 4786 URTWN_UNLOCK(sc); 4787 } 4788 4789 static int 4790 urtwn_wme_update(struct ieee80211com *ic) 4791 { 4792 const struct wmeParams *wmep = 4793 ic->ic_wme.wme_chanParams.cap_wmeParams; 4794 struct urtwn_softc *sc = ic->ic_softc; 4795 uint8_t aifs, acm, slottime; 4796 int ac; 4797 4798 acm = 0; 4799 slottime = IEEE80211_GET_SLOTTIME(ic); 4800 4801 URTWN_LOCK(sc); 4802 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4803 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4804 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4805 urtwn_write_4(sc, wme2queue[ac].reg, 4806 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 4807 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 4808 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 4809 SM(R92C_EDCA_PARAM_AIFS, aifs)); 4810 if (ac != WME_AC_BE) 4811 acm |= wmep[ac].wmep_acm << ac; 4812 } 4813 4814 if (acm != 0) 4815 acm |= R92C_ACMHWCTRL_EN; 4816 urtwn_write_1(sc, R92C_ACMHWCTRL, 4817 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 4818 acm); 4819 4820 URTWN_UNLOCK(sc); 4821 4822 return 0; 4823 } 4824 4825 static void 4826 urtwn_update_slot(struct ieee80211com *ic) 4827 { 4828 urtwn_cmd_sleepable(ic->ic_softc, NULL, 0, urtwn_update_slot_cb); 4829 } 4830 4831 static void 4832 urtwn_update_slot_cb(struct urtwn_softc *sc, union sec_param *data) 4833 { 4834 struct ieee80211com *ic = &sc->sc_ic; 4835 uint8_t slottime; 4836 4837 slottime = IEEE80211_GET_SLOTTIME(ic); 4838 4839 URTWN_DPRINTF(sc, URTWN_DEBUG_ANY, "%s: setting slot time to %uus\n", 4840 __func__, slottime); 4841 4842 urtwn_write_1(sc, R92C_SLOT, slottime); 4843 urtwn_update_aifs(sc, slottime); 4844 } 4845 4846 static void 4847 urtwn_update_aifs(struct urtwn_softc *sc, uint8_t slottime) 4848 { 4849 const struct wmeParams *wmep = 4850 sc->sc_ic.ic_wme.wme_chanParams.cap_wmeParams; 4851 uint8_t aifs, ac; 4852 4853 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4854 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4855 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4856 urtwn_write_1(sc, wme2queue[ac].reg, aifs); 4857 } 4858 } 4859 4860 static uint8_t 4861 urtwn_get_multi_pos(const uint8_t maddr[]) 4862 { 4863 uint64_t mask = 0x00004d101df481b4; 4864 uint8_t pos = 0x27; /* initial value */ 4865 int i, j; 4866 4867 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 4868 for (j = (i == 0) ? 1 : 0; j < 8; j++) 4869 if ((maddr[i] >> j) & 1) 4870 pos ^= (mask >> (i * 8 + j - 1)); 4871 4872 pos &= 0x3f; 4873 4874 return (pos); 4875 } 4876 4877 static void 4878 urtwn_set_multi(struct urtwn_softc *sc) 4879 { 4880 struct ieee80211com *ic = &sc->sc_ic; 4881 uint32_t mfilt[2]; 4882 4883 URTWN_ASSERT_LOCKED(sc); 4884 4885 /* general structure was copied from ath(4). */ 4886 if (ic->ic_allmulti == 0) { 4887 struct ieee80211vap *vap; 4888 struct ifnet *ifp; 4889 struct ifmultiaddr *ifma; 4890 4891 /* 4892 * Merge multicast addresses to form the hardware filter. 4893 */ 4894 mfilt[0] = mfilt[1] = 0; 4895 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 4896 ifp = vap->iv_ifp; 4897 #if defined(__DragonFly__) 4898 /* XXX not implemented */ 4899 #else 4900 if_maddr_rlock(ifp); 4901 #endif 4902 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4903 caddr_t dl; 4904 uint8_t pos; 4905 4906 dl = LLADDR((struct sockaddr_dl *) 4907 ifma->ifma_addr); 4908 pos = urtwn_get_multi_pos(dl); 4909 4910 mfilt[pos / 32] |= (1 << (pos % 32)); 4911 } 4912 #if defined(__DragonFly__) 4913 /* XXX not implemented */ 4914 #else 4915 if_maddr_runlock(ifp); 4916 #endif 4917 } 4918 } else 4919 mfilt[0] = mfilt[1] = ~0; 4920 4921 4922 urtwn_write_4(sc, R92C_MAR + 0, mfilt[0]); 4923 urtwn_write_4(sc, R92C_MAR + 4, mfilt[1]); 4924 4925 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s: MC filter %08x:%08x\n", 4926 __func__, mfilt[0], mfilt[1]); 4927 } 4928 4929 static void 4930 urtwn_set_promisc(struct urtwn_softc *sc) 4931 { 4932 struct ieee80211com *ic = &sc->sc_ic; 4933 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4934 uint32_t rcr, mask1, mask2; 4935 4936 URTWN_ASSERT_LOCKED(sc); 4937 4938 if (vap->iv_opmode == IEEE80211_M_MONITOR) 4939 return; 4940 4941 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 4942 mask2 = R92C_RCR_APM; 4943 4944 if (vap->iv_state == IEEE80211_S_RUN) { 4945 switch (vap->iv_opmode) { 4946 case IEEE80211_M_STA: 4947 mask2 |= R92C_RCR_CBSSID_DATA; 4948 /* FALLTHROUGH */ 4949 case IEEE80211_M_HOSTAP: 4950 mask2 |= R92C_RCR_CBSSID_BCN; 4951 break; 4952 case IEEE80211_M_IBSS: 4953 mask2 |= R92C_RCR_CBSSID_DATA; 4954 break; 4955 default: 4956 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4957 __func__, vap->iv_opmode); 4958 return; 4959 } 4960 } 4961 4962 rcr = urtwn_read_4(sc, R92C_RCR); 4963 if (ic->ic_promisc == 0) 4964 rcr = (rcr & ~mask1) | mask2; 4965 else 4966 rcr = (rcr & ~mask2) | mask1; 4967 urtwn_write_4(sc, R92C_RCR, rcr); 4968 } 4969 4970 static void 4971 urtwn_update_promisc(struct ieee80211com *ic) 4972 { 4973 struct urtwn_softc *sc = ic->ic_softc; 4974 4975 URTWN_LOCK(sc); 4976 if (sc->sc_flags & URTWN_RUNNING) 4977 urtwn_set_promisc(sc); 4978 URTWN_UNLOCK(sc); 4979 } 4980 4981 static void 4982 urtwn_update_mcast(struct ieee80211com *ic) 4983 { 4984 struct urtwn_softc *sc = ic->ic_softc; 4985 4986 URTWN_LOCK(sc); 4987 if (sc->sc_flags & URTWN_RUNNING) 4988 urtwn_set_multi(sc); 4989 URTWN_UNLOCK(sc); 4990 } 4991 4992 static struct ieee80211_node * 4993 urtwn_node_alloc(struct ieee80211vap *vap, 4994 const uint8_t mac[IEEE80211_ADDR_LEN]) 4995 { 4996 struct urtwn_node *un; 4997 4998 un = kmalloc(sizeof (struct urtwn_node), M_80211_NODE, 4999 M_INTWAIT | M_ZERO); 5000 5001 if (un == NULL) 5002 return NULL; 5003 5004 un->id = URTWN_MACID_UNDEFINED; 5005 5006 return &un->ni; 5007 } 5008 5009 static void 5010 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 5011 { 5012 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 5013 struct urtwn_node *un = URTWN_NODE(ni); 5014 uint8_t id; 5015 5016 /* Only do this bit for R88E chips */ 5017 if (! (sc->chip & URTWN_CHIP_88E)) 5018 return; 5019 5020 if (!isnew) 5021 return; 5022 5023 URTWN_NT_LOCK(sc); 5024 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) { 5025 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) { 5026 un->id = id; 5027 sc->node_list[id] = ni; 5028 break; 5029 } 5030 } 5031 URTWN_NT_UNLOCK(sc); 5032 5033 if (id > URTWN_MACID_MAX(sc)) { 5034 device_printf(sc->sc_dev, "%s: node table is full\n", 5035 __func__); 5036 } 5037 } 5038 5039 static void 5040 urtwn_node_free(struct ieee80211_node *ni) 5041 { 5042 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 5043 struct urtwn_node *un = URTWN_NODE(ni); 5044 5045 URTWN_NT_LOCK(sc); 5046 if (un->id != URTWN_MACID_UNDEFINED) 5047 sc->node_list[un->id] = NULL; 5048 URTWN_NT_UNLOCK(sc); 5049 5050 sc->sc_node_free(ni); 5051 } 5052 5053 static void 5054 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 5055 struct ieee80211_channel *extc) 5056 { 5057 struct ieee80211com *ic = &sc->sc_ic; 5058 uint32_t reg; 5059 u_int chan; 5060 int i; 5061 5062 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 5063 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 5064 device_printf(sc->sc_dev, 5065 "%s: invalid channel %x\n", __func__, chan); 5066 return; 5067 } 5068 5069 /* Set Tx power for this new channel. */ 5070 urtwn_set_txpower(sc, c, extc); 5071 5072 for (i = 0; i < sc->nrxchains; i++) { 5073 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 5074 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 5075 } 5076 #ifndef IEEE80211_NO_HT 5077 if (extc != NULL) { 5078 /* Is secondary channel below or above primary? */ 5079 int prichlo = c->ic_freq < extc->ic_freq; 5080 5081 urtwn_write_1(sc, R92C_BWOPMODE, 5082 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 5083 5084 reg = urtwn_read_1(sc, R92C_RRSR + 2); 5085 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 5086 urtwn_write_1(sc, R92C_RRSR + 2, reg); 5087 5088 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5089 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 5090 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5091 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 5092 5093 /* Set CCK side band. */ 5094 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 5095 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 5096 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 5097 5098 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 5099 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 5100 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 5101 5102 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5103 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 5104 ~R92C_FPGA0_ANAPARAM2_CBW20); 5105 5106 reg = urtwn_bb_read(sc, 0x818); 5107 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 5108 urtwn_bb_write(sc, 0x818, reg); 5109 5110 /* Select 40MHz bandwidth. */ 5111 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5112 (sc->rf_chnlbw[0] & ~0xfff) | chan); 5113 } else 5114 #endif 5115 { 5116 urtwn_write_1(sc, R92C_BWOPMODE, 5117 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 5118 5119 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5120 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 5121 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5122 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 5123 5124 if (!(sc->chip & URTWN_CHIP_88E)) { 5125 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5126 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 5127 R92C_FPGA0_ANAPARAM2_CBW20); 5128 } 5129 5130 /* Select 20MHz bandwidth. */ 5131 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5132 (sc->rf_chnlbw[0] & ~0xfff) | chan | 5133 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 5134 R92C_RF_CHNLBW_BW20)); 5135 } 5136 } 5137 5138 static void 5139 urtwn_iq_calib(struct urtwn_softc *sc) 5140 { 5141 /* TODO */ 5142 } 5143 5144 static void 5145 urtwn_lc_calib(struct urtwn_softc *sc) 5146 { 5147 uint32_t rf_ac[2]; 5148 uint8_t txmode; 5149 int i; 5150 5151 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 5152 if ((txmode & 0x70) != 0) { 5153 /* Disable all continuous Tx. */ 5154 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 5155 5156 /* Set RF mode to standby mode. */ 5157 for (i = 0; i < sc->nrxchains; i++) { 5158 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 5159 urtwn_rf_write(sc, i, R92C_RF_AC, 5160 RW(rf_ac[i], R92C_RF_AC_MODE, 5161 R92C_RF_AC_MODE_STANDBY)); 5162 } 5163 } else { 5164 /* Block all Tx queues. */ 5165 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 5166 } 5167 /* Start calibration. */ 5168 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5169 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 5170 5171 /* Give calibration the time to complete. */ 5172 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 5173 5174 /* Restore configuration. */ 5175 if ((txmode & 0x70) != 0) { 5176 /* Restore Tx mode. */ 5177 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 5178 /* Restore RF mode. */ 5179 for (i = 0; i < sc->nrxchains; i++) 5180 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 5181 } else { 5182 /* Unblock all Tx queues. */ 5183 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 5184 } 5185 } 5186 5187 static void 5188 urtwn_temp_calib(struct urtwn_softc *sc) 5189 { 5190 uint8_t temp; 5191 5192 URTWN_ASSERT_LOCKED(sc); 5193 5194 if (!(sc->sc_flags & URTWN_TEMP_MEASURED)) { 5195 /* Start measuring temperature. */ 5196 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5197 "%s: start measuring temperature\n", __func__); 5198 if (sc->chip & URTWN_CHIP_88E) { 5199 urtwn_rf_write(sc, 0, R88E_RF_T_METER, 5200 R88E_RF_T_METER_START); 5201 } else { 5202 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 5203 R92C_RF_T_METER_START); 5204 } 5205 sc->sc_flags |= URTWN_TEMP_MEASURED; 5206 return; 5207 } 5208 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 5209 5210 /* Read measured temperature. */ 5211 if (sc->chip & URTWN_CHIP_88E) { 5212 temp = MS(urtwn_rf_read(sc, 0, R88E_RF_T_METER), 5213 R88E_RF_T_METER_VAL); 5214 } else { 5215 temp = MS(urtwn_rf_read(sc, 0, R92C_RF_T_METER), 5216 R92C_RF_T_METER_VAL); 5217 } 5218 if (temp == 0) { /* Read failed, skip. */ 5219 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5220 "%s: temperature read failed, skipping\n", __func__); 5221 return; 5222 } 5223 5224 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5225 "%s: temperature: previous %u, current %u\n", 5226 __func__, sc->thcal_lctemp, temp); 5227 5228 /* 5229 * Redo LC calibration if temperature changed significantly since 5230 * last calibration. 5231 */ 5232 if (sc->thcal_lctemp == 0) { 5233 /* First LC calibration is performed in urtwn_init(). */ 5234 sc->thcal_lctemp = temp; 5235 } else if (abs(temp - sc->thcal_lctemp) > 1) { 5236 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5237 "%s: LC calib triggered by temp: %u -> %u\n", 5238 __func__, sc->thcal_lctemp, temp); 5239 urtwn_lc_calib(sc); 5240 /* Record temperature of last LC calibration. */ 5241 sc->thcal_lctemp = temp; 5242 } 5243 } 5244 5245 static int 5246 urtwn_init(struct urtwn_softc *sc) 5247 { 5248 struct ieee80211com *ic = &sc->sc_ic; 5249 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5250 uint8_t macaddr[IEEE80211_ADDR_LEN]; 5251 uint32_t reg; 5252 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 5253 int error; 5254 5255 URTWN_LOCK(sc); 5256 if (sc->sc_flags & URTWN_RUNNING) { 5257 URTWN_UNLOCK(sc); 5258 return (0); 5259 } 5260 5261 /* Init firmware commands ring. */ 5262 sc->fwcur = 0; 5263 5264 /* Allocate Tx/Rx buffers. */ 5265 error = urtwn_alloc_rx_list(sc); 5266 if (error != 0) 5267 goto fail; 5268 5269 error = urtwn_alloc_tx_list(sc); 5270 if (error != 0) 5271 goto fail; 5272 5273 /* Power on adapter. */ 5274 error = urtwn_power_on(sc); 5275 if (error != 0) 5276 goto fail; 5277 5278 /* Initialize DMA. */ 5279 error = urtwn_dma_init(sc); 5280 if (error != 0) 5281 goto fail; 5282 5283 /* Set info size in Rx descriptors (in 64-bit words). */ 5284 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 5285 5286 /* Init interrupts. */ 5287 if (sc->chip & URTWN_CHIP_88E) { 5288 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 5289 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5290 goto fail; 5291 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 5292 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 5293 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5294 goto fail; 5295 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 5296 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 5297 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5298 goto fail; 5299 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5300 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5301 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 5302 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5303 goto fail; 5304 } else { 5305 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 5306 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5307 goto fail; 5308 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 5309 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5310 goto fail; 5311 } 5312 5313 /* Set MAC address. */ 5314 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 5315 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 5316 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5317 goto fail; 5318 5319 /* Set initial network type. */ 5320 urtwn_set_mode(sc, R92C_MSR_INFRA); 5321 5322 /* Initialize Rx filter. */ 5323 urtwn_rxfilter_init(sc); 5324 5325 /* Set response rate. */ 5326 reg = urtwn_read_4(sc, R92C_RRSR); 5327 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 5328 urtwn_write_4(sc, R92C_RRSR, reg); 5329 5330 /* Set short/long retry limits. */ 5331 urtwn_write_2(sc, R92C_RL, 5332 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 5333 5334 /* Initialize EDCA parameters. */ 5335 urtwn_edca_init(sc); 5336 5337 /* Setup rate fallback. */ 5338 if (!(sc->chip & URTWN_CHIP_88E)) { 5339 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 5340 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 5341 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 5342 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 5343 } 5344 5345 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 5346 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 5347 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 5348 /* Set ACK timeout. */ 5349 urtwn_write_1(sc, R92C_ACKTO, 0x40); 5350 5351 /* Setup USB aggregation. */ 5352 reg = urtwn_read_4(sc, R92C_TDECTRL); 5353 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 5354 urtwn_write_4(sc, R92C_TDECTRL, reg); 5355 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 5356 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 5357 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 5358 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 5359 if (sc->chip & URTWN_CHIP_88E) 5360 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 5361 else { 5362 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 5363 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5364 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5365 R92C_USB_SPECIAL_OPTION_AGG_EN); 5366 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 5367 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 5368 } 5369 5370 /* Initialize beacon parameters. */ 5371 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 5372 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 5373 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 5374 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 5375 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 5376 5377 if (!(sc->chip & URTWN_CHIP_88E)) { 5378 /* Setup AMPDU aggregation. */ 5379 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 5380 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 5381 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 5382 5383 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 5384 } 5385 5386 #ifndef URTWN_WITHOUT_UCODE 5387 /* Load 8051 microcode. */ 5388 error = urtwn_load_firmware(sc); 5389 if (error == 0) 5390 sc->sc_flags |= URTWN_FW_LOADED; 5391 #endif 5392 5393 /* Initialize MAC/BB/RF blocks. */ 5394 error = urtwn_mac_init(sc); 5395 if (error != 0) { 5396 device_printf(sc->sc_dev, 5397 "%s: error while initializing MAC block\n", __func__); 5398 goto fail; 5399 } 5400 urtwn_bb_init(sc); 5401 urtwn_rf_init(sc); 5402 5403 /* Reinitialize Rx filter (D3845 is not committed yet). */ 5404 urtwn_rxfilter_init(sc); 5405 5406 if (sc->chip & URTWN_CHIP_88E) { 5407 urtwn_write_2(sc, R92C_CR, 5408 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 5409 R92C_CR_MACRXEN); 5410 } 5411 5412 /* Turn CCK and OFDM blocks on. */ 5413 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5414 reg |= R92C_RFMOD_CCK_EN; 5415 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5416 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5417 goto fail; 5418 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5419 reg |= R92C_RFMOD_OFDM_EN; 5420 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5421 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5422 goto fail; 5423 5424 /* Clear per-station keys table. */ 5425 urtwn_cam_init(sc); 5426 5427 /* Enable decryption / encryption. */ 5428 urtwn_write_2(sc, R92C_SECCFG, 5429 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 5430 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA | 5431 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 5432 5433 /* 5434 * Install static keys (if any). 5435 * Must be called after urtwn_cam_init(). 5436 */ 5437 ieee80211_runtask(ic, &sc->cmdq_task); 5438 5439 /* Enable hardware sequence numbering. */ 5440 urtwn_write_1(sc, R92C_HWSEQ_CTRL, R92C_TX_QUEUE_ALL); 5441 5442 /* Enable per-packet TX report. */ 5443 if (sc->chip & URTWN_CHIP_88E) { 5444 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 5445 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA); 5446 } 5447 5448 /* Perform LO and IQ calibrations. */ 5449 urtwn_iq_calib(sc); 5450 /* Perform LC calibration. */ 5451 urtwn_lc_calib(sc); 5452 5453 /* Fix USB interference issue. */ 5454 if (!(sc->chip & URTWN_CHIP_88E)) { 5455 urtwn_write_1(sc, 0xfe40, 0xe0); 5456 urtwn_write_1(sc, 0xfe41, 0x8d); 5457 urtwn_write_1(sc, 0xfe42, 0x80); 5458 5459 urtwn_pa_bias_init(sc); 5460 } 5461 5462 /* Initialize GPIO setting. */ 5463 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5464 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5465 5466 /* Fix for lower temperature. */ 5467 if (!(sc->chip & URTWN_CHIP_88E)) 5468 urtwn_write_1(sc, 0x15, 0xe9); 5469 5470 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 5471 5472 sc->sc_flags |= URTWN_RUNNING; 5473 5474 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5475 fail: 5476 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5477 error = EIO; 5478 5479 URTWN_UNLOCK(sc); 5480 5481 return (error); 5482 } 5483 5484 static void 5485 urtwn_stop(struct urtwn_softc *sc) 5486 { 5487 5488 URTWN_LOCK(sc); 5489 if (!(sc->sc_flags & URTWN_RUNNING)) { 5490 URTWN_UNLOCK(sc); 5491 return; 5492 } 5493 5494 sc->sc_flags &= ~(URTWN_RUNNING | URTWN_FW_LOADED | 5495 URTWN_TEMP_MEASURED); 5496 sc->thcal_lctemp = 0; 5497 callout_stop(&sc->sc_watchdog_ch); 5498 5499 urtwn_abort_xfers(sc); 5500 urtwn_drain_mbufq(sc); 5501 urtwn_power_off(sc); 5502 URTWN_UNLOCK(sc); 5503 } 5504 5505 static void 5506 urtwn_abort_xfers(struct urtwn_softc *sc) 5507 { 5508 int i; 5509 5510 URTWN_ASSERT_LOCKED(sc); 5511 5512 /* abort any pending transfers */ 5513 for (i = 0; i < URTWN_N_TRANSFER; i++) 5514 usbd_transfer_stop(sc->sc_xfer[i]); 5515 } 5516 5517 static int 5518 urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 5519 const struct ieee80211_bpf_params *params) 5520 { 5521 struct ieee80211com *ic = ni->ni_ic; 5522 struct urtwn_softc *sc = ic->ic_softc; 5523 struct urtwn_data *bf; 5524 int error; 5525 5526 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n", 5527 __func__, 5528 m); 5529 5530 /* prevent management frames from being sent if we're not ready */ 5531 URTWN_LOCK(sc); 5532 if (!(sc->sc_flags & URTWN_RUNNING)) { 5533 error = ENETDOWN; 5534 goto end; 5535 } 5536 5537 bf = urtwn_getbuf(sc); 5538 if (bf == NULL) { 5539 error = ENOBUFS; 5540 goto end; 5541 } 5542 5543 if (params == NULL) { 5544 /* 5545 * Legacy path; interpret frame contents to decide 5546 * precisely how to send the frame. 5547 */ 5548 error = urtwn_tx_data(sc, ni, m, bf); 5549 } else { 5550 /* 5551 * Caller supplied explicit parameters to use in 5552 * sending the frame. 5553 */ 5554 error = urtwn_tx_raw(sc, ni, m, bf, params); 5555 } 5556 if (error != 0) { 5557 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 5558 goto end; 5559 } 5560 5561 sc->sc_txtimer = 5; 5562 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5563 5564 end: 5565 if (error != 0) 5566 m_freem(m); 5567 5568 URTWN_UNLOCK(sc); 5569 5570 return (error); 5571 } 5572 5573 static void 5574 urtwn_ms_delay(struct urtwn_softc *sc) 5575 { 5576 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 5577 } 5578 5579 static device_method_t urtwn_methods[] = { 5580 /* Device interface */ 5581 DEVMETHOD(device_probe, urtwn_match), 5582 DEVMETHOD(device_attach, urtwn_attach), 5583 DEVMETHOD(device_detach, urtwn_detach), 5584 5585 DEVMETHOD_END 5586 }; 5587 5588 static driver_t urtwn_driver = { 5589 "urtwn", 5590 urtwn_methods, 5591 sizeof(struct urtwn_softc) 5592 }; 5593 5594 static devclass_t urtwn_devclass; 5595 5596 DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 5597 MODULE_DEPEND(urtwn, usb, 1, 1, 1); 5598 MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 5599 #ifndef URTWN_WITHOUT_UCODE 5600 MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 5601 #endif 5602 MODULE_VERSION(urtwn, 1); 5603 #if defined(__DragonFly__) 5604 /* USB_PNP_HOST_INFO() not implemented */ 5605 #else 5606 USB_PNP_HOST_INFO(urtwn_devs); 5607 #endif 5608