1 /* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2015 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __FBSDID("$FreeBSD$"); 23 24 /* 25 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 26 */ 27 28 #include "opt_wlan.h" 29 #include "opt_urtwn.h" 30 31 #include <sys/param.h> 32 #include <sys/sockio.h> 33 #include <sys/sysctl.h> 34 #include <sys/lock.h> 35 #include <sys/condvar.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/linker.h> 45 #include <sys/firmware.h> 46 #if defined(__DragonFly__) 47 #else 48 #include <sys/kdb.h> 49 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #endif 53 54 #include <sys/rman.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_arp.h> 60 #include <net/ethernet.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 #include <net/if_types.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/in_var.h> 68 #include <netinet/if_ether.h> 69 #include <netinet/ip.h> 70 71 #include <netproto/802_11/ieee80211_var.h> 72 #include <netproto/802_11/ieee80211_regdomain.h> 73 #include <netproto/802_11/ieee80211_radiotap.h> 74 #include <netproto/802_11/ieee80211_ratectl.h> 75 #ifdef IEEE80211_SUPPORT_SUPERG 76 #include <netproto/802_11/ieee80211_superg.h> 77 #endif 78 79 #include <bus/u4b/usb.h> 80 #include <bus/u4b/usbdi.h> 81 #include <bus/u4b/usb_device.h> 82 #include "usbdevs.h" 83 84 #include <bus/u4b/usb_debug.h> 85 86 #include <bus/u4b/wlan/if_urtwnreg.h> 87 #include <bus/u4b/wlan/if_urtwnvar.h> 88 89 #ifdef USB_DEBUG 90 enum { 91 URTWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 92 URTWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 93 URTWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 94 URTWN_DEBUG_RA = 0x00000008, /* f/w rate adaptation setup */ 95 URTWN_DEBUG_USB = 0x00000010, /* usb requests */ 96 URTWN_DEBUG_FIRMWARE = 0x00000020, /* firmware(9) loading debug */ 97 URTWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 98 URTWN_DEBUG_INTR = 0x00000080, /* ISR */ 99 URTWN_DEBUG_TEMP = 0x00000100, /* temperature calibration */ 100 URTWN_DEBUG_ROM = 0x00000200, /* various ROM info */ 101 URTWN_DEBUG_KEY = 0x00000400, /* crypto keys management */ 102 URTWN_DEBUG_TXPWR = 0x00000800, /* dump Tx power values */ 103 URTWN_DEBUG_RSSI = 0x00001000, /* dump RSSI lookups */ 104 URTWN_DEBUG_ANY = 0xffffffff 105 }; 106 107 #define URTWN_DPRINTF(_sc, _m, ...) do { \ 108 if ((_sc)->sc_debug & (_m)) \ 109 device_printf((_sc)->sc_dev, __VA_ARGS__); \ 110 } while(0) 111 112 #else 113 #define URTWN_DPRINTF(_sc, _m, ...) do { (void) sc; } while (0) 114 #endif 115 116 #define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 117 118 static int urtwn_enable_11n = 1; 119 TUNABLE_INT("hw.usb.urtwn.enable_11n", &urtwn_enable_11n); 120 121 /* various supported device vendors/products */ 122 static const STRUCT_USB_HOST_ID urtwn_devs[] = { 123 #define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 124 #define URTWN_RTL8188E_DEV(v,p) \ 125 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 126 #define URTWN_RTL8188E 1 127 URTWN_DEV(ABOCOM, RTL8188CU_1), 128 URTWN_DEV(ABOCOM, RTL8188CU_2), 129 URTWN_DEV(ABOCOM, RTL8192CU), 130 URTWN_DEV(ASUS, RTL8192CU), 131 URTWN_DEV(ASUS, USBN10NANO), 132 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 133 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 134 URTWN_DEV(AZUREWAVE, RTL8188CU), 135 URTWN_DEV(BELKIN, F7D2102), 136 URTWN_DEV(BELKIN, RTL8188CU), 137 URTWN_DEV(BELKIN, RTL8192CU), 138 URTWN_DEV(CHICONY, RTL8188CUS_1), 139 URTWN_DEV(CHICONY, RTL8188CUS_2), 140 URTWN_DEV(CHICONY, RTL8188CUS_3), 141 URTWN_DEV(CHICONY, RTL8188CUS_4), 142 URTWN_DEV(CHICONY, RTL8188CUS_5), 143 URTWN_DEV(COREGA, RTL8192CU), 144 URTWN_DEV(DLINK, RTL8188CU), 145 URTWN_DEV(DLINK, RTL8192CU_1), 146 URTWN_DEV(DLINK, RTL8192CU_2), 147 URTWN_DEV(DLINK, RTL8192CU_3), 148 URTWN_DEV(DLINK, DWA131B), 149 URTWN_DEV(EDIMAX, EW7811UN), 150 URTWN_DEV(EDIMAX, RTL8192CU), 151 URTWN_DEV(FEIXUN, RTL8188CU), 152 URTWN_DEV(FEIXUN, RTL8192CU), 153 URTWN_DEV(GUILLEMOT, HWNUP150), 154 URTWN_DEV(HAWKING, RTL8192CU), 155 URTWN_DEV(HP3, RTL8188CU), 156 URTWN_DEV(NETGEAR, WNA1000M), 157 URTWN_DEV(NETGEAR, RTL8192CU), 158 URTWN_DEV(NETGEAR4, RTL8188CU), 159 URTWN_DEV(NOVATECH, RTL8188CU), 160 URTWN_DEV(PLANEX2, RTL8188CU_1), 161 URTWN_DEV(PLANEX2, RTL8188CU_2), 162 URTWN_DEV(PLANEX2, RTL8188CU_3), 163 URTWN_DEV(PLANEX2, RTL8188CU_4), 164 URTWN_DEV(PLANEX2, RTL8188CUS), 165 URTWN_DEV(PLANEX2, RTL8192CU), 166 URTWN_DEV(REALTEK, RTL8188CE_0), 167 URTWN_DEV(REALTEK, RTL8188CE_1), 168 URTWN_DEV(REALTEK, RTL8188CTV), 169 URTWN_DEV(REALTEK, RTL8188CU_0), 170 URTWN_DEV(REALTEK, RTL8188CU_1), 171 URTWN_DEV(REALTEK, RTL8188CU_2), 172 URTWN_DEV(REALTEK, RTL8188CU_3), 173 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 174 URTWN_DEV(REALTEK, RTL8188CUS), 175 URTWN_DEV(REALTEK, RTL8188RU_1), 176 URTWN_DEV(REALTEK, RTL8188RU_2), 177 URTWN_DEV(REALTEK, RTL8188RU_3), 178 URTWN_DEV(REALTEK, RTL8191CU), 179 URTWN_DEV(REALTEK, RTL8192CE), 180 URTWN_DEV(REALTEK, RTL8192CU), 181 URTWN_DEV(SITECOMEU, RTL8188CU_1), 182 URTWN_DEV(SITECOMEU, RTL8188CU_2), 183 URTWN_DEV(SITECOMEU, RTL8192CU), 184 URTWN_DEV(TRENDNET, RTL8188CU), 185 URTWN_DEV(TRENDNET, RTL8192CU), 186 URTWN_DEV(ZYXEL, RTL8192CU), 187 /* URTWN_RTL8188E */ 188 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 189 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 190 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 191 URTWN_RTL8188E_DEV(EDIMAX, EW7811UN_V2), 192 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 193 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 194 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 195 #undef URTWN_RTL8188E_DEV 196 #undef URTWN_DEV 197 }; 198 199 static device_probe_t urtwn_match; 200 static device_attach_t urtwn_attach; 201 static device_detach_t urtwn_detach; 202 203 static usb_callback_t urtwn_bulk_tx_callback; 204 static usb_callback_t urtwn_bulk_rx_callback; 205 206 static void urtwn_sysctlattach(struct urtwn_softc *); 207 static void urtwn_drain_mbufq(struct urtwn_softc *); 208 static usb_error_t urtwn_do_request(struct urtwn_softc *, 209 struct usb_device_request *, void *); 210 static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 211 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 212 const uint8_t [IEEE80211_ADDR_LEN], 213 const uint8_t [IEEE80211_ADDR_LEN]); 214 static void urtwn_vap_delete(struct ieee80211vap *); 215 static struct mbuf * urtwn_rx_copy_to_mbuf(struct urtwn_softc *, 216 struct r92c_rx_stat *, int); 217 static struct mbuf * urtwn_report_intr(struct usb_xfer *, 218 struct urtwn_data *); 219 static struct mbuf * urtwn_rxeof(struct urtwn_softc *, uint8_t *, int); 220 static void urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *, 221 void *); 222 static struct ieee80211_node *urtwn_rx_frame(struct urtwn_softc *, 223 struct mbuf *, int8_t *); 224 static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 225 int); 226 static int urtwn_alloc_list(struct urtwn_softc *, 227 struct urtwn_data[], int, int); 228 static int urtwn_alloc_rx_list(struct urtwn_softc *); 229 static int urtwn_alloc_tx_list(struct urtwn_softc *); 230 static void urtwn_free_list(struct urtwn_softc *, 231 struct urtwn_data data[], int); 232 static void urtwn_free_rx_list(struct urtwn_softc *); 233 static void urtwn_free_tx_list(struct urtwn_softc *); 234 static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 235 static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 236 static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 237 uint8_t *, int); 238 static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 239 static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 240 static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 241 static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 242 uint8_t *, int); 243 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 244 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 245 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 246 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 247 const void *, int); 248 static void urtwn_cmdq_cb(void *, int); 249 static int urtwn_cmd_sleepable(struct urtwn_softc *, const void *, 250 size_t, CMD_FUNC_PROTO); 251 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 252 uint8_t, uint32_t); 253 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 254 uint8_t, uint32_t); 255 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 256 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 257 uint32_t); 258 static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 259 static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 260 uint8_t, uint8_t); 261 #ifdef USB_DEBUG 262 static void urtwn_dump_rom_contents(struct urtwn_softc *, 263 uint8_t *, uint16_t); 264 #endif 265 static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 266 uint16_t); 267 static int urtwn_efuse_switch_power(struct urtwn_softc *); 268 static int urtwn_read_chipid(struct urtwn_softc *); 269 static int urtwn_read_rom(struct urtwn_softc *); 270 static int urtwn_r88e_read_rom(struct urtwn_softc *); 271 static int urtwn_ra_init(struct urtwn_softc *); 272 static void urtwn_init_beacon(struct urtwn_softc *, 273 struct urtwn_vap *); 274 static int urtwn_setup_beacon(struct urtwn_softc *, 275 struct ieee80211_node *); 276 static void urtwn_update_beacon(struct ieee80211vap *, int); 277 static int urtwn_tx_beacon(struct urtwn_softc *sc, 278 struct urtwn_vap *); 279 static int urtwn_key_alloc(struct ieee80211vap *, 280 struct ieee80211_key *, ieee80211_keyix *, 281 ieee80211_keyix *); 282 static void urtwn_key_set_cb(struct urtwn_softc *, 283 union sec_param *); 284 static void urtwn_key_del_cb(struct urtwn_softc *, 285 union sec_param *); 286 static int urtwn_key_set(struct ieee80211vap *, 287 const struct ieee80211_key *); 288 static int urtwn_key_delete(struct ieee80211vap *, 289 const struct ieee80211_key *); 290 static void urtwn_tsf_task_adhoc(void *, int); 291 static void urtwn_tsf_sync_enable(struct urtwn_softc *, 292 struct ieee80211vap *); 293 static void urtwn_get_tsf(struct urtwn_softc *, uint64_t *); 294 static void urtwn_set_led(struct urtwn_softc *, int, int); 295 static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 296 static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 297 struct mbuf *, int, 298 const struct ieee80211_rx_stats *, int, int); 299 static int urtwn_newstate(struct ieee80211vap *, 300 enum ieee80211_state, int); 301 static void urtwn_calib_to(void *); 302 static void urtwn_calib_cb(struct urtwn_softc *, 303 union sec_param *); 304 static void urtwn_watchdog(void *); 305 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 306 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 307 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 308 static int urtwn_tx_data(struct urtwn_softc *, 309 struct ieee80211_node *, struct mbuf *, 310 struct urtwn_data *); 311 static int urtwn_tx_raw(struct urtwn_softc *, 312 struct ieee80211_node *, struct mbuf *, 313 struct urtwn_data *, 314 const struct ieee80211_bpf_params *); 315 static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 316 uint8_t, struct urtwn_data *); 317 static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 318 static void urtwn_start(struct urtwn_softc *); 319 static void urtwn_parent(struct ieee80211com *); 320 static int urtwn_r92c_power_on(struct urtwn_softc *); 321 static int urtwn_r88e_power_on(struct urtwn_softc *); 322 static void urtwn_r92c_power_off(struct urtwn_softc *); 323 static void urtwn_r88e_power_off(struct urtwn_softc *); 324 static int urtwn_llt_init(struct urtwn_softc *); 325 #ifndef URTWN_WITHOUT_UCODE 326 static void urtwn_fw_reset(struct urtwn_softc *); 327 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 328 static int urtwn_fw_loadpage(struct urtwn_softc *, int, 329 const uint8_t *, int); 330 static int urtwn_load_firmware(struct urtwn_softc *); 331 #endif 332 static int urtwn_dma_init(struct urtwn_softc *); 333 static int urtwn_mac_init(struct urtwn_softc *); 334 static void urtwn_bb_init(struct urtwn_softc *); 335 static void urtwn_rf_init(struct urtwn_softc *); 336 static void urtwn_cam_init(struct urtwn_softc *); 337 static int urtwn_cam_write(struct urtwn_softc *, uint32_t, 338 uint32_t); 339 static void urtwn_pa_bias_init(struct urtwn_softc *); 340 static void urtwn_rxfilter_init(struct urtwn_softc *); 341 static void urtwn_edca_init(struct urtwn_softc *); 342 static void urtwn_write_txpower(struct urtwn_softc *, int, 343 uint16_t[]); 344 static void urtwn_get_txpower(struct urtwn_softc *, int, 345 struct ieee80211_channel *, 346 struct ieee80211_channel *, uint16_t[]); 347 static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 348 struct ieee80211_channel *, 349 struct ieee80211_channel *, uint16_t[]); 350 static void urtwn_set_txpower(struct urtwn_softc *, 351 struct ieee80211_channel *, 352 struct ieee80211_channel *); 353 static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 354 static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 355 static void urtwn_scan_start(struct ieee80211com *); 356 static void urtwn_scan_end(struct ieee80211com *); 357 static void urtwn_set_channel(struct ieee80211com *); 358 static int urtwn_wme_update(struct ieee80211com *); 359 static void urtwn_update_slot(struct ieee80211com *); 360 static void urtwn_update_slot_cb(struct urtwn_softc *, 361 union sec_param *); 362 static void urtwn_update_aifs(struct urtwn_softc *, uint8_t); 363 static uint8_t urtwn_get_multi_pos(const uint8_t[]); 364 static void urtwn_set_multi(struct urtwn_softc *); 365 static void urtwn_set_promisc(struct urtwn_softc *); 366 static void urtwn_update_promisc(struct ieee80211com *); 367 static void urtwn_update_mcast(struct ieee80211com *); 368 static struct ieee80211_node *urtwn_node_alloc(struct ieee80211vap *, 369 const uint8_t mac[IEEE80211_ADDR_LEN]); 370 static void urtwn_newassoc(struct ieee80211_node *, int); 371 static void urtwn_node_free(struct ieee80211_node *); 372 static void urtwn_set_chan(struct urtwn_softc *, 373 struct ieee80211_channel *, 374 struct ieee80211_channel *); 375 static void urtwn_iq_calib(struct urtwn_softc *); 376 static void urtwn_lc_calib(struct urtwn_softc *); 377 static void urtwn_temp_calib(struct urtwn_softc *); 378 static int urtwn_init(struct urtwn_softc *); 379 static void urtwn_stop(struct urtwn_softc *); 380 static void urtwn_abort_xfers(struct urtwn_softc *); 381 static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 382 const struct ieee80211_bpf_params *); 383 static void urtwn_ms_delay(struct urtwn_softc *); 384 385 /* Aliases. */ 386 #define urtwn_bb_write urtwn_write_4 387 #define urtwn_bb_read urtwn_read_4 388 389 static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 390 [URTWN_BULK_RX] = { 391 .type = UE_BULK, 392 .endpoint = UE_ADDR_ANY, 393 .direction = UE_DIR_IN, 394 .bufsize = URTWN_RXBUFSZ, 395 .flags = { 396 .pipe_bof = 1, 397 .short_xfer_ok = 1 398 }, 399 .callback = urtwn_bulk_rx_callback, 400 }, 401 [URTWN_BULK_TX_BE] = { 402 .type = UE_BULK, 403 .endpoint = 0x03, 404 .direction = UE_DIR_OUT, 405 .bufsize = URTWN_TXBUFSZ, 406 .flags = { 407 .ext_buffer = 1, 408 .pipe_bof = 1, 409 .force_short_xfer = 1 410 }, 411 .callback = urtwn_bulk_tx_callback, 412 .timeout = URTWN_TX_TIMEOUT, /* ms */ 413 }, 414 [URTWN_BULK_TX_BK] = { 415 .type = UE_BULK, 416 .endpoint = 0x03, 417 .direction = UE_DIR_OUT, 418 .bufsize = URTWN_TXBUFSZ, 419 .flags = { 420 .ext_buffer = 1, 421 .pipe_bof = 1, 422 .force_short_xfer = 1, 423 }, 424 .callback = urtwn_bulk_tx_callback, 425 .timeout = URTWN_TX_TIMEOUT, /* ms */ 426 }, 427 [URTWN_BULK_TX_VI] = { 428 .type = UE_BULK, 429 .endpoint = 0x02, 430 .direction = UE_DIR_OUT, 431 .bufsize = URTWN_TXBUFSZ, 432 .flags = { 433 .ext_buffer = 1, 434 .pipe_bof = 1, 435 .force_short_xfer = 1 436 }, 437 .callback = urtwn_bulk_tx_callback, 438 .timeout = URTWN_TX_TIMEOUT, /* ms */ 439 }, 440 [URTWN_BULK_TX_VO] = { 441 .type = UE_BULK, 442 .endpoint = 0x02, 443 .direction = UE_DIR_OUT, 444 .bufsize = URTWN_TXBUFSZ, 445 .flags = { 446 .ext_buffer = 1, 447 .pipe_bof = 1, 448 .force_short_xfer = 1 449 }, 450 .callback = urtwn_bulk_tx_callback, 451 .timeout = URTWN_TX_TIMEOUT, /* ms */ 452 }, 453 }; 454 455 static const struct wme_to_queue { 456 uint16_t reg; 457 uint8_t qid; 458 } wme2queue[WME_NUM_AC] = { 459 { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 460 { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 461 { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 462 { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 463 }; 464 465 static int 466 urtwn_match(device_t self) 467 { 468 struct usb_attach_arg *uaa = device_get_ivars(self); 469 470 if (uaa->usb_mode != USB_MODE_HOST) 471 return (ENXIO); 472 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 473 return (ENXIO); 474 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 475 return (ENXIO); 476 477 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 478 } 479 480 static void 481 urtwn_update_chw(struct ieee80211com *ic) 482 { 483 } 484 485 static int 486 urtwn_ampdu_enable(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 487 { 488 489 /* We're driving this ourselves (eventually); don't involve net80211 */ 490 return (0); 491 } 492 493 static int 494 urtwn_attach(device_t self) 495 { 496 struct usb_attach_arg *uaa = device_get_ivars(self); 497 struct urtwn_softc *sc = device_get_softc(self); 498 struct ieee80211com *ic = &sc->sc_ic; 499 uint8_t bands[IEEE80211_MODE_BYTES]; 500 int error; 501 502 device_set_usb_desc(self); 503 sc->sc_udev = uaa->device; 504 sc->sc_dev = self; 505 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 506 sc->chip |= URTWN_CHIP_88E; 507 508 #ifdef USB_DEBUG 509 int debug; 510 if (resource_int_value(device_get_name(sc->sc_dev), 511 device_get_unit(sc->sc_dev), "debug", &debug) == 0) 512 sc->sc_debug = debug; 513 #endif 514 515 #if defined(__DragonFly__) 516 lockinit(&sc->sc_mtx, device_get_nameunit(self), 0, 0); 517 #else 518 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 519 MTX_NETWORK_LOCK, MTX_DEF); 520 #endif 521 URTWN_CMDQ_LOCK_INIT(sc); 522 URTWN_NT_LOCK_INIT(sc); 523 #if defined(__DragonFly__) 524 callout_init(&sc->sc_calib_to); 525 callout_init(&sc->sc_watchdog_ch); 526 #else 527 callout_init(&sc->sc_calib_to, 0); 528 callout_init(&sc->sc_watchdog_ch, 0); 529 #endif 530 mbufq_init(&sc->sc_snd, ifqmaxlen); 531 532 sc->sc_iface_index = URTWN_IFACE_INDEX; 533 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 534 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 535 if (error) { 536 device_printf(self, "could not allocate USB transfers, " 537 "err=%s\n", usbd_errstr(error)); 538 goto detach; 539 } 540 541 URTWN_LOCK(sc); 542 543 error = urtwn_read_chipid(sc); 544 if (error) { 545 device_printf(sc->sc_dev, "unsupported test chip\n"); 546 URTWN_UNLOCK(sc); 547 goto detach; 548 } 549 550 /* Determine number of Tx/Rx chains. */ 551 if (sc->chip & URTWN_CHIP_92C) { 552 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 553 sc->nrxchains = 2; 554 } else { 555 sc->ntxchains = 1; 556 sc->nrxchains = 1; 557 } 558 559 if (sc->chip & URTWN_CHIP_88E) 560 error = urtwn_r88e_read_rom(sc); 561 else 562 error = urtwn_read_rom(sc); 563 if (error != 0) { 564 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 565 __func__, error); 566 URTWN_UNLOCK(sc); 567 goto detach; 568 } 569 570 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 571 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 572 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 573 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 574 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 575 "8188CUS", sc->ntxchains, sc->nrxchains); 576 577 URTWN_UNLOCK(sc); 578 579 ic->ic_softc = sc; 580 ic->ic_name = device_get_nameunit(self); 581 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 582 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 583 584 /* set device capabilities */ 585 ic->ic_caps = 586 IEEE80211_C_STA /* station mode */ 587 | IEEE80211_C_MONITOR /* monitor mode */ 588 | IEEE80211_C_IBSS /* adhoc mode */ 589 | IEEE80211_C_HOSTAP /* hostap mode */ 590 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 591 | IEEE80211_C_SHSLOT /* short slot time supported */ 592 #if 0 593 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 594 #endif 595 | IEEE80211_C_WPA /* 802.11i */ 596 | IEEE80211_C_WME /* 802.11e */ 597 | IEEE80211_C_SWAMSDUTX /* Do software A-MSDU TX */ 598 | IEEE80211_C_FF /* Atheros fast-frames */ 599 ; 600 601 ic->ic_cryptocaps = 602 IEEE80211_CRYPTO_WEP | 603 IEEE80211_CRYPTO_TKIP | 604 IEEE80211_CRYPTO_AES_CCM; 605 606 /* Assume they're all 11n capable for now */ 607 if (urtwn_enable_11n) { 608 device_printf(self, "enabling 11n\n"); 609 ic->ic_htcaps = IEEE80211_HTC_HT | 610 #if 0 611 IEEE80211_HTC_AMPDU | 612 #endif 613 IEEE80211_HTC_AMSDU | 614 IEEE80211_HTCAP_MAXAMSDU_3839 | 615 IEEE80211_HTCAP_SMPS_OFF; 616 /* no HT40 just yet */ 617 // ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40; 618 619 /* XXX TODO: verify chains versus streams for urtwn */ 620 ic->ic_txstream = sc->ntxchains; 621 ic->ic_rxstream = sc->nrxchains; 622 } 623 624 memset(bands, 0, sizeof(bands)); 625 setbit(bands, IEEE80211_MODE_11B); 626 setbit(bands, IEEE80211_MODE_11G); 627 if (urtwn_enable_11n) 628 setbit(bands, IEEE80211_MODE_11NG); 629 ieee80211_init_channels(ic, NULL, bands); 630 631 ieee80211_ifattach(ic); 632 ic->ic_raw_xmit = urtwn_raw_xmit; 633 ic->ic_scan_start = urtwn_scan_start; 634 ic->ic_scan_end = urtwn_scan_end; 635 ic->ic_set_channel = urtwn_set_channel; 636 ic->ic_transmit = urtwn_transmit; 637 ic->ic_parent = urtwn_parent; 638 ic->ic_vap_create = urtwn_vap_create; 639 ic->ic_vap_delete = urtwn_vap_delete; 640 ic->ic_wme.wme_update = urtwn_wme_update; 641 ic->ic_updateslot = urtwn_update_slot; 642 ic->ic_update_promisc = urtwn_update_promisc; 643 ic->ic_update_mcast = urtwn_update_mcast; 644 if (sc->chip & URTWN_CHIP_88E) { 645 ic->ic_node_alloc = urtwn_node_alloc; 646 ic->ic_newassoc = urtwn_newassoc; 647 sc->sc_node_free = ic->ic_node_free; 648 ic->ic_node_free = urtwn_node_free; 649 } 650 ic->ic_update_chw = urtwn_update_chw; 651 ic->ic_ampdu_enable = urtwn_ampdu_enable; 652 653 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 654 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 655 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 656 URTWN_RX_RADIOTAP_PRESENT); 657 658 TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc); 659 660 urtwn_sysctlattach(sc); 661 662 if (bootverbose) 663 ieee80211_announce(ic); 664 665 return (0); 666 667 detach: 668 urtwn_detach(self); 669 return (ENXIO); /* failure */ 670 } 671 672 static void 673 urtwn_sysctlattach(struct urtwn_softc *sc) 674 { 675 #ifdef USB_DEBUG 676 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 677 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 678 679 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 680 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 681 "control debugging printfs"); 682 #endif 683 } 684 685 static int 686 urtwn_detach(device_t self) 687 { 688 struct urtwn_softc *sc = device_get_softc(self); 689 struct ieee80211com *ic = &sc->sc_ic; 690 unsigned int x; 691 692 /* Prevent further ioctls. */ 693 URTWN_LOCK(sc); 694 sc->sc_flags |= URTWN_DETACHED; 695 URTWN_UNLOCK(sc); 696 697 urtwn_stop(sc); 698 699 callout_drain(&sc->sc_watchdog_ch); 700 callout_drain(&sc->sc_calib_to); 701 702 /* stop all USB transfers */ 703 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 704 705 /* Prevent further allocations from RX/TX data lists. */ 706 URTWN_LOCK(sc); 707 STAILQ_INIT(&sc->sc_tx_active); 708 STAILQ_INIT(&sc->sc_tx_inactive); 709 STAILQ_INIT(&sc->sc_tx_pending); 710 711 STAILQ_INIT(&sc->sc_rx_active); 712 STAILQ_INIT(&sc->sc_rx_inactive); 713 URTWN_UNLOCK(sc); 714 715 /* drain USB transfers */ 716 for (x = 0; x != URTWN_N_TRANSFER; x++) 717 usbd_transfer_drain(sc->sc_xfer[x]); 718 719 /* Free data buffers. */ 720 URTWN_LOCK(sc); 721 urtwn_free_tx_list(sc); 722 urtwn_free_rx_list(sc); 723 URTWN_UNLOCK(sc); 724 725 if (ic->ic_softc == sc) { 726 ieee80211_draintask(ic, &sc->cmdq_task); 727 ieee80211_ifdetach(ic); 728 } 729 730 URTWN_NT_LOCK_DESTROY(sc); 731 URTWN_CMDQ_LOCK_DESTROY(sc); 732 lockuninit(&sc->sc_mtx); 733 734 return (0); 735 } 736 737 static void 738 urtwn_drain_mbufq(struct urtwn_softc *sc) 739 { 740 struct mbuf *m; 741 struct ieee80211_node *ni; 742 URTWN_ASSERT_LOCKED(sc); 743 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 744 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 745 m->m_pkthdr.rcvif = NULL; 746 ieee80211_free_node(ni); 747 m_freem(m); 748 } 749 } 750 751 static usb_error_t 752 urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 753 void *data) 754 { 755 usb_error_t err; 756 int ntries = 10; 757 758 URTWN_ASSERT_LOCKED(sc); 759 760 err = 0; /* whack gcc warning */ 761 while (ntries--) { 762 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 763 req, data, 0, NULL, 250 /* ms */); 764 if (err == 0) 765 break; 766 767 URTWN_DPRINTF(sc, URTWN_DEBUG_USB, 768 "%s: control request failed, %s (retries left: %d)\n", 769 __func__, usbd_errstr(err), ntries); 770 usb_pause_mtx(&sc->sc_mtx, hz / 100); 771 } 772 return (err); 773 } 774 775 static struct ieee80211vap * 776 urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 777 enum ieee80211_opmode opmode, int flags, 778 const uint8_t bssid[IEEE80211_ADDR_LEN], 779 const uint8_t mac[IEEE80211_ADDR_LEN]) 780 { 781 struct urtwn_softc *sc = ic->ic_softc; 782 struct urtwn_vap *uvp; 783 struct ieee80211vap *vap; 784 785 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 786 return (NULL); 787 788 uvp = kmalloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 789 vap = &uvp->vap; 790 /* enable s/w bmiss handling for sta mode */ 791 792 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 793 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 794 /* out of memory */ 795 kfree(uvp, M_80211_VAP); 796 return (NULL); 797 } 798 799 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 800 urtwn_init_beacon(sc, uvp); 801 802 /* override state transition machine */ 803 uvp->newstate = vap->iv_newstate; 804 vap->iv_newstate = urtwn_newstate; 805 vap->iv_update_beacon = urtwn_update_beacon; 806 vap->iv_key_alloc = urtwn_key_alloc; 807 vap->iv_key_set = urtwn_key_set; 808 vap->iv_key_delete = urtwn_key_delete; 809 810 /* 802.11n parameters */ 811 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_16; 812 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 813 814 if (opmode == IEEE80211_M_IBSS) { 815 uvp->recv_mgmt = vap->iv_recv_mgmt; 816 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 817 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 818 } 819 820 if (URTWN_CHIP_HAS_RATECTL(sc)) 821 ieee80211_ratectl_init(vap); 822 /* complete setup */ 823 ieee80211_vap_attach(vap, ieee80211_media_change, 824 ieee80211_media_status, mac); 825 ic->ic_opmode = opmode; 826 return (vap); 827 } 828 829 static void 830 urtwn_vap_delete(struct ieee80211vap *vap) 831 { 832 struct ieee80211com *ic = vap->iv_ic; 833 struct urtwn_softc *sc = ic->ic_softc; 834 struct urtwn_vap *uvp = URTWN_VAP(vap); 835 836 if (uvp->bcn_mbuf != NULL) 837 m_freem(uvp->bcn_mbuf); 838 if (vap->iv_opmode == IEEE80211_M_IBSS) 839 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 840 if (URTWN_CHIP_HAS_RATECTL(sc)) 841 ieee80211_ratectl_deinit(vap); 842 ieee80211_vap_detach(vap); 843 kfree(uvp, M_80211_VAP); 844 } 845 846 static struct mbuf * 847 urtwn_rx_copy_to_mbuf(struct urtwn_softc *sc, struct r92c_rx_stat *stat, 848 int totlen) 849 { 850 /* ic is not used, remove to fix gcc warning */ 851 /* struct ieee80211com *ic = &sc->sc_ic; */ 852 struct mbuf *m; 853 uint32_t rxdw0; 854 int pktlen; 855 856 /* 857 * don't pass packets to the ieee80211 framework if the driver isn't 858 * RUNNING. 859 */ 860 if (!(sc->sc_flags & URTWN_RUNNING)) 861 return (NULL); 862 863 rxdw0 = le32toh(stat->rxdw0); 864 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 865 /* 866 * This should not happen since we setup our Rx filter 867 * to not receive these frames. 868 */ 869 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 870 "%s: RX flags error (%s)\n", __func__, 871 rxdw0 & R92C_RXDW0_CRCERR ? "CRC" : "ICV"); 872 goto fail; 873 } 874 875 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 876 if (pktlen < sizeof(struct ieee80211_frame_ack)) { 877 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 878 "%s: frame is too short: %d\n", __func__, pktlen); 879 goto fail; 880 } 881 882 if (__predict_false(totlen > MCLBYTES)) { 883 /* convert to m_getjcl if this happens */ 884 device_printf(sc->sc_dev, "%s: frame too long: %d (%d)\n", 885 __func__, pktlen, totlen); 886 goto fail; 887 } 888 889 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 890 if (__predict_false(m == NULL)) { 891 device_printf(sc->sc_dev, "%s: could not allocate RX mbuf\n", 892 __func__); 893 goto fail; 894 } 895 896 /* Finalize mbuf. */ 897 memcpy(mtod(m, uint8_t *), (uint8_t *)stat, totlen); 898 m->m_pkthdr.len = m->m_len = totlen; 899 900 return (m); 901 fail: 902 #if defined(__DragonFly__) 903 /* unimplemented */ 904 #else 905 counter_u64_add(ic->ic_ierrors, 1); 906 #endif 907 return (NULL); 908 } 909 910 static struct mbuf * 911 urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data) 912 { 913 struct urtwn_softc *sc = data->sc; 914 /* ic not used, remove to fix gcc error */ 915 /* struct ieee80211com *ic = &sc->sc_ic;*/ 916 struct r92c_rx_stat *stat; 917 uint8_t *buf; 918 int len; 919 920 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 921 922 if (len < sizeof(*stat)) { 923 #if defined(__DragonFly__) 924 /* unimplemented */ 925 #else 926 counter_u64_add(ic->ic_ierrors, 1); 927 #endif 928 return (NULL); 929 } 930 931 buf = data->buf; 932 stat = (struct r92c_rx_stat *)buf; 933 934 /* 935 * For 88E chips we can tie the FF flushing here; 936 * this is where we do know exactly how deep the 937 * transmit queue is. 938 * 939 * But it won't work for R92 chips, so we can't 940 * take the easy way out. 941 */ 942 943 if (sc->chip & URTWN_CHIP_88E) { 944 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT); 945 946 switch (report_sel) { 947 case R88E_RXDW3_RPT_RX: 948 return (urtwn_rxeof(sc, buf, len)); 949 case R88E_RXDW3_RPT_TX1: 950 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]); 951 break; 952 default: 953 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, 954 "%s: case %d was not handled\n", __func__, 955 report_sel); 956 break; 957 } 958 } else 959 return (urtwn_rxeof(sc, buf, len)); 960 961 return (NULL); 962 } 963 964 static struct mbuf * 965 urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len) 966 { 967 struct r92c_rx_stat *stat; 968 struct mbuf *m, *m0 = NULL, *prevm = NULL; 969 uint32_t rxdw0; 970 int totlen, pktlen, infosz, npkts; 971 972 /* Get the number of encapsulated frames. */ 973 stat = (struct r92c_rx_stat *)buf; 974 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 975 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 976 "%s: Rx %d frames in one chunk\n", __func__, npkts); 977 978 /* Process all of them. */ 979 while (npkts-- > 0) { 980 if (len < sizeof(*stat)) 981 break; 982 stat = (struct r92c_rx_stat *)buf; 983 rxdw0 = le32toh(stat->rxdw0); 984 985 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 986 if (pktlen == 0) 987 break; 988 989 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 990 991 /* Make sure everything fits in xfer. */ 992 totlen = sizeof(*stat) + infosz + pktlen; 993 if (totlen > len) 994 break; 995 996 m = urtwn_rx_copy_to_mbuf(sc, stat, totlen); 997 if (m0 == NULL) 998 m0 = m; 999 if (prevm == NULL) 1000 prevm = m; 1001 else { 1002 prevm->m_next = m; 1003 prevm = m; 1004 } 1005 1006 /* Next chunk is 128-byte aligned. */ 1007 totlen = (totlen + 127) & ~127; 1008 buf += totlen; 1009 len -= totlen; 1010 } 1011 1012 return (m0); 1013 } 1014 1015 static void 1016 urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg) 1017 { 1018 struct r88e_tx_rpt_ccx *rpt = arg; 1019 struct ieee80211vap *vap; 1020 struct ieee80211_node *ni; 1021 uint8_t macid; 1022 int ntries; 1023 1024 macid = MS(rpt->rptb1, R88E_RPTB1_MACID); 1025 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT); 1026 1027 URTWN_NT_LOCK(sc); 1028 ni = sc->node_list[macid]; 1029 if (ni != NULL) { 1030 vap = ni->ni_vap; 1031 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: frame for macid %d was" 1032 "%s sent (%d retries)\n", __func__, macid, 1033 (rpt->rptb1 & R88E_RPTB1_PKT_OK) ? "" : " not", 1034 ntries); 1035 1036 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) { 1037 ieee80211_ratectl_tx_complete(vap, ni, 1038 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL); 1039 } else { 1040 ieee80211_ratectl_tx_complete(vap, ni, 1041 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL); 1042 } 1043 } else { 1044 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: macid %d, ni is NULL\n", 1045 __func__, macid); 1046 } 1047 URTWN_NT_UNLOCK(sc); 1048 } 1049 1050 static struct ieee80211_node * 1051 urtwn_rx_frame(struct urtwn_softc *sc, struct mbuf *m, int8_t *rssi_p) 1052 { 1053 struct ieee80211com *ic = &sc->sc_ic; 1054 struct ieee80211_frame_min *wh; 1055 struct r92c_rx_stat *stat; 1056 uint32_t rxdw0, rxdw3; 1057 uint8_t rate, cipher; 1058 int8_t rssi = -127; 1059 int infosz; 1060 1061 stat = mtod(m, struct r92c_rx_stat *); 1062 rxdw0 = le32toh(stat->rxdw0); 1063 rxdw3 = le32toh(stat->rxdw3); 1064 1065 rate = MS(rxdw3, R92C_RXDW3_RATE); 1066 cipher = MS(rxdw0, R92C_RXDW0_CIPHER); 1067 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1068 1069 /* Get RSSI from PHY status descriptor if present. */ 1070 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1071 if (sc->chip & URTWN_CHIP_88E) 1072 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 1073 else 1074 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 1075 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: rssi=%d\n", __func__, rssi); 1076 /* Update our average RSSI. */ 1077 urtwn_update_avgrssi(sc, rate, rssi); 1078 } 1079 1080 if (ieee80211_radiotap_active(ic)) { 1081 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1082 1083 tap->wr_flags = 0; 1084 1085 urtwn_get_tsf(sc, &tap->wr_tsft); 1086 if (__predict_false(le32toh((uint32_t)tap->wr_tsft) < 1087 le32toh(stat->rxdw5))) { 1088 tap->wr_tsft = le32toh(tap->wr_tsft >> 32) - 1; 1089 tap->wr_tsft = (uint64_t)htole32(tap->wr_tsft) << 32; 1090 } else 1091 tap->wr_tsft &= 0xffffffff00000000; 1092 tap->wr_tsft += stat->rxdw5; 1093 1094 /* XXX 20/40? */ 1095 /* XXX shortgi? */ 1096 1097 /* Map HW rate index to 802.11 rate. */ 1098 if (!(rxdw3 & R92C_RXDW3_HT)) { 1099 tap->wr_rate = ridx2rate[rate]; 1100 } else if (rate >= 12) { /* MCS0~15. */ 1101 /* Bit 7 set means HT MCS instead of rate. */ 1102 tap->wr_rate = 0x80 | (rate - 12); 1103 } 1104 1105 /* XXX TODO: this isn't right; should use the last good RSSI */ 1106 tap->wr_dbm_antsignal = rssi; 1107 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 1108 } 1109 1110 *rssi_p = rssi; 1111 1112 /* Drop descriptor. */ 1113 m_adj(m, sizeof(*stat) + infosz); 1114 wh = mtod(m, struct ieee80211_frame_min *); 1115 1116 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1117 cipher != R92C_CAM_ALGO_NONE) { 1118 m->m_flags |= M_WEP; 1119 } 1120 1121 if (m->m_len >= sizeof(*wh)) 1122 return (ieee80211_find_rxnode(ic, wh)); 1123 1124 return (NULL); 1125 } 1126 1127 static void 1128 urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 1129 { 1130 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1131 struct ieee80211com *ic = &sc->sc_ic; 1132 struct ieee80211_node *ni; 1133 struct mbuf *m = NULL, *next; 1134 struct urtwn_data *data; 1135 int8_t nf, rssi; 1136 1137 URTWN_ASSERT_LOCKED(sc); 1138 1139 switch (USB_GET_STATE(xfer)) { 1140 case USB_ST_TRANSFERRED: 1141 data = STAILQ_FIRST(&sc->sc_rx_active); 1142 if (data == NULL) 1143 goto tr_setup; 1144 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1145 m = urtwn_report_intr(xfer, data); 1146 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1147 /* FALLTHROUGH */ 1148 case USB_ST_SETUP: 1149 tr_setup: 1150 data = STAILQ_FIRST(&sc->sc_rx_inactive); 1151 if (data == NULL) { 1152 KASSERT(m == NULL, ("mbuf isn't NULL")); 1153 goto finish; 1154 } 1155 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 1156 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 1157 usbd_xfer_set_frame_data(xfer, 0, data->buf, 1158 usbd_xfer_max_len(xfer)); 1159 usbd_transfer_submit(xfer); 1160 1161 /* 1162 * To avoid LOR we should unlock our private mutex here to call 1163 * ieee80211_input() because here is at the end of a USB 1164 * callback and safe to unlock. 1165 */ 1166 while (m != NULL) { 1167 next = m->m_next; 1168 m->m_next = NULL; 1169 1170 ni = urtwn_rx_frame(sc, m, &rssi); 1171 1172 /* Store a global last-good RSSI */ 1173 if (rssi != -127) 1174 sc->last_rssi = rssi; 1175 1176 URTWN_UNLOCK(sc); 1177 1178 nf = URTWN_NOISE_FLOOR; 1179 if (ni != NULL) { 1180 if (rssi != -127) 1181 URTWN_NODE(ni)->last_rssi = rssi; 1182 if (ni->ni_flags & IEEE80211_NODE_HT) 1183 m->m_flags |= M_AMPDU; 1184 (void)ieee80211_input(ni, m, 1185 URTWN_NODE(ni)->last_rssi - nf, nf); 1186 ieee80211_free_node(ni); 1187 } else { 1188 /* Use last good global RSSI */ 1189 (void)ieee80211_input_all(ic, m, 1190 sc->last_rssi - nf, nf); 1191 } 1192 URTWN_LOCK(sc); 1193 m = next; 1194 } 1195 break; 1196 default: 1197 /* needs it to the inactive queue due to a error. */ 1198 data = STAILQ_FIRST(&sc->sc_rx_active); 1199 if (data != NULL) { 1200 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1201 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1202 } 1203 if (error != USB_ERR_CANCELLED) { 1204 usbd_xfer_set_stall(xfer); 1205 #if defined(__DragonFly__) 1206 /* unimplemented */ 1207 #else 1208 counter_u64_add(ic->ic_ierrors, 1); 1209 #endif 1210 goto tr_setup; 1211 } 1212 break; 1213 } 1214 finish: 1215 /* Finished receive; age anything left on the FF queue by a little bump */ 1216 /* 1217 * XXX TODO: just make this a callout timer schedule so we can 1218 * flush the FF staging queue if we're approaching idle. 1219 */ 1220 #ifdef IEEE80211_SUPPORT_SUPERG 1221 URTWN_UNLOCK(sc); 1222 ieee80211_ff_age_all(ic, 1); 1223 URTWN_LOCK(sc); 1224 #endif 1225 1226 /* Kick-start more transmit in case we stalled */ 1227 urtwn_start(sc); 1228 } 1229 1230 static void 1231 urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 1232 { 1233 1234 URTWN_ASSERT_LOCKED(sc); 1235 1236 if (data->ni != NULL) /* not a beacon frame */ 1237 ieee80211_tx_complete(data->ni, data->m, status); 1238 1239 if (sc->sc_tx_n_active > 0) 1240 sc->sc_tx_n_active--; 1241 1242 data->ni = NULL; 1243 data->m = NULL; 1244 1245 sc->sc_txtimer = 0; 1246 1247 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 1248 } 1249 1250 static int 1251 urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1252 int ndata, int maxsz) 1253 { 1254 int i, error; 1255 1256 for (i = 0; i < ndata; i++) { 1257 struct urtwn_data *dp = &data[i]; 1258 dp->sc = sc; 1259 dp->m = NULL; 1260 dp->buf = kmalloc(maxsz, M_USBDEV, M_INTWAIT); 1261 if (dp->buf == NULL) { 1262 device_printf(sc->sc_dev, 1263 "could not allocate buffer\n"); 1264 error = ENOMEM; 1265 goto fail; 1266 } 1267 dp->ni = NULL; 1268 } 1269 1270 return (0); 1271 fail: 1272 urtwn_free_list(sc, data, ndata); 1273 return (error); 1274 } 1275 1276 static int 1277 urtwn_alloc_rx_list(struct urtwn_softc *sc) 1278 { 1279 int error, i; 1280 1281 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1282 URTWN_RXBUFSZ); 1283 if (error != 0) 1284 return (error); 1285 1286 STAILQ_INIT(&sc->sc_rx_active); 1287 STAILQ_INIT(&sc->sc_rx_inactive); 1288 1289 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1290 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1291 1292 return (0); 1293 } 1294 1295 static int 1296 urtwn_alloc_tx_list(struct urtwn_softc *sc) 1297 { 1298 int error, i; 1299 1300 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1301 URTWN_TXBUFSZ); 1302 if (error != 0) 1303 return (error); 1304 1305 STAILQ_INIT(&sc->sc_tx_active); 1306 STAILQ_INIT(&sc->sc_tx_inactive); 1307 STAILQ_INIT(&sc->sc_tx_pending); 1308 1309 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1310 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1311 1312 return (0); 1313 } 1314 1315 static void 1316 urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 1317 { 1318 int i; 1319 1320 for (i = 0; i < ndata; i++) { 1321 struct urtwn_data *dp = &data[i]; 1322 1323 if (dp->buf != NULL) { 1324 kfree(dp->buf, M_USBDEV); 1325 dp->buf = NULL; 1326 } 1327 if (dp->ni != NULL) { 1328 ieee80211_free_node(dp->ni); 1329 dp->ni = NULL; 1330 } 1331 } 1332 } 1333 1334 static void 1335 urtwn_free_rx_list(struct urtwn_softc *sc) 1336 { 1337 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 1338 } 1339 1340 static void 1341 urtwn_free_tx_list(struct urtwn_softc *sc) 1342 { 1343 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 1344 } 1345 1346 static void 1347 urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1348 { 1349 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1350 #ifdef IEEE80211_SUPPORT_SUPERG 1351 struct ieee80211com *ic = &sc->sc_ic; 1352 #endif 1353 struct urtwn_data *data; 1354 1355 URTWN_ASSERT_LOCKED(sc); 1356 1357 switch (USB_GET_STATE(xfer)){ 1358 case USB_ST_TRANSFERRED: 1359 data = STAILQ_FIRST(&sc->sc_tx_active); 1360 if (data == NULL) 1361 goto tr_setup; 1362 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1363 urtwn_txeof(sc, data, 0); 1364 /* FALLTHROUGH */ 1365 case USB_ST_SETUP: 1366 tr_setup: 1367 data = STAILQ_FIRST(&sc->sc_tx_pending); 1368 if (data == NULL) { 1369 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1370 "%s: empty pending queue\n", __func__); 1371 sc->sc_tx_n_active = 0; 1372 goto finish; 1373 } 1374 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1375 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1376 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1377 usbd_transfer_submit(xfer); 1378 sc->sc_tx_n_active++; 1379 break; 1380 default: 1381 data = STAILQ_FIRST(&sc->sc_tx_active); 1382 if (data == NULL) 1383 goto tr_setup; 1384 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1385 urtwn_txeof(sc, data, 1); 1386 if (error != USB_ERR_CANCELLED) { 1387 usbd_xfer_set_stall(xfer); 1388 goto tr_setup; 1389 } 1390 break; 1391 } 1392 finish: 1393 #ifdef IEEE80211_SUPPORT_SUPERG 1394 /* 1395 * If the TX active queue drops below a certain 1396 * threshold, ensure we age fast-frames out so they're 1397 * transmitted. 1398 */ 1399 if (sc->sc_tx_n_active <= 1) { 1400 /* XXX ew - net80211 should defer this for us! */ 1401 1402 /* 1403 * Note: this sc_tx_n_active currently tracks 1404 * the number of pending transmit submissions 1405 * and not the actual depth of the TX frames 1406 * pending to the hardware. That means that 1407 * we're going to end up with some sub-optimal 1408 * aggregation behaviour. 1409 */ 1410 /* 1411 * XXX TODO: just make this a callout timer schedule so we can 1412 * flush the FF staging queue if we're approaching idle. 1413 */ 1414 URTWN_UNLOCK(sc); 1415 ieee80211_ff_flush(ic, WME_AC_VO); 1416 ieee80211_ff_flush(ic, WME_AC_VI); 1417 ieee80211_ff_flush(ic, WME_AC_BE); 1418 ieee80211_ff_flush(ic, WME_AC_BK); 1419 URTWN_LOCK(sc); 1420 } 1421 #endif 1422 /* Kick-start more transmit */ 1423 urtwn_start(sc); 1424 } 1425 1426 static struct urtwn_data * 1427 _urtwn_getbuf(struct urtwn_softc *sc) 1428 { 1429 struct urtwn_data *bf; 1430 1431 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1432 if (bf != NULL) 1433 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1434 else { 1435 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1436 "%s: out of xmit buffers\n", __func__); 1437 } 1438 return (bf); 1439 } 1440 1441 static struct urtwn_data * 1442 urtwn_getbuf(struct urtwn_softc *sc) 1443 { 1444 struct urtwn_data *bf; 1445 1446 URTWN_ASSERT_LOCKED(sc); 1447 1448 bf = _urtwn_getbuf(sc); 1449 if (bf == NULL) { 1450 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: stop queue\n", 1451 __func__); 1452 } 1453 return (bf); 1454 } 1455 1456 static usb_error_t 1457 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1458 int len) 1459 { 1460 usb_device_request_t req; 1461 1462 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1463 req.bRequest = R92C_REQ_REGS; 1464 USETW(req.wValue, addr); 1465 USETW(req.wIndex, 0); 1466 USETW(req.wLength, len); 1467 return (urtwn_do_request(sc, &req, buf)); 1468 } 1469 1470 static usb_error_t 1471 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1472 { 1473 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1474 } 1475 1476 static usb_error_t 1477 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1478 { 1479 val = htole16(val); 1480 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1481 } 1482 1483 static usb_error_t 1484 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1485 { 1486 val = htole32(val); 1487 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1488 } 1489 1490 static usb_error_t 1491 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1492 int len) 1493 { 1494 usb_device_request_t req; 1495 1496 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1497 req.bRequest = R92C_REQ_REGS; 1498 USETW(req.wValue, addr); 1499 USETW(req.wIndex, 0); 1500 USETW(req.wLength, len); 1501 return (urtwn_do_request(sc, &req, buf)); 1502 } 1503 1504 static uint8_t 1505 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1506 { 1507 uint8_t val; 1508 1509 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1510 return (0xff); 1511 return (val); 1512 } 1513 1514 static uint16_t 1515 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1516 { 1517 uint16_t val; 1518 1519 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1520 return (0xffff); 1521 return (le16toh(val)); 1522 } 1523 1524 static uint32_t 1525 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1526 { 1527 uint32_t val; 1528 1529 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1530 return (0xffffffff); 1531 return (le32toh(val)); 1532 } 1533 1534 static int 1535 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1536 { 1537 struct r92c_fw_cmd cmd; 1538 usb_error_t error; 1539 int ntries; 1540 1541 if (!(sc->sc_flags & URTWN_FW_LOADED)) { 1542 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, "%s: firmware " 1543 "was not loaded; command (id %d) will be discarded\n", 1544 __func__, id); 1545 return (0); 1546 } 1547 1548 /* Wait for current FW box to be empty. */ 1549 for (ntries = 0; ntries < 100; ntries++) { 1550 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1551 break; 1552 urtwn_ms_delay(sc); 1553 } 1554 if (ntries == 100) { 1555 device_printf(sc->sc_dev, 1556 "could not send firmware command\n"); 1557 return (ETIMEDOUT); 1558 } 1559 memset(&cmd, 0, sizeof(cmd)); 1560 cmd.id = id; 1561 if (len > 3) 1562 cmd.id |= R92C_CMD_FLAG_EXT; 1563 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1564 memcpy(cmd.msg, buf, len); 1565 1566 /* Write the first word last since that will trigger the FW. */ 1567 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1568 (uint8_t *)&cmd + 4, 2); 1569 if (error != USB_ERR_NORMAL_COMPLETION) 1570 return (EIO); 1571 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1572 (uint8_t *)&cmd + 0, 4); 1573 if (error != USB_ERR_NORMAL_COMPLETION) 1574 return (EIO); 1575 1576 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1577 return (0); 1578 } 1579 1580 static void 1581 urtwn_cmdq_cb(void *arg, int pending) 1582 { 1583 struct urtwn_softc *sc = arg; 1584 struct urtwn_cmdq *item; 1585 1586 /* 1587 * Device must be powered on (via urtwn_power_on()) 1588 * before any command may be sent. 1589 */ 1590 URTWN_LOCK(sc); 1591 if (!(sc->sc_flags & URTWN_RUNNING)) { 1592 URTWN_UNLOCK(sc); 1593 return; 1594 } 1595 1596 URTWN_CMDQ_LOCK(sc); 1597 while (sc->cmdq[sc->cmdq_first].func != NULL) { 1598 item = &sc->cmdq[sc->cmdq_first]; 1599 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE; 1600 URTWN_CMDQ_UNLOCK(sc); 1601 1602 item->func(sc, &item->data); 1603 1604 URTWN_CMDQ_LOCK(sc); 1605 memset(item, 0, sizeof (*item)); 1606 } 1607 URTWN_CMDQ_UNLOCK(sc); 1608 URTWN_UNLOCK(sc); 1609 } 1610 1611 static int 1612 urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len, 1613 CMD_FUNC_PROTO) 1614 { 1615 struct ieee80211com *ic = &sc->sc_ic; 1616 1617 KASSERT(len <= sizeof(union sec_param), ("buffer overflow")); 1618 1619 URTWN_CMDQ_LOCK(sc); 1620 if (sc->cmdq[sc->cmdq_last].func != NULL) { 1621 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__); 1622 URTWN_CMDQ_UNLOCK(sc); 1623 1624 return (EAGAIN); 1625 } 1626 1627 if (ptr != NULL) 1628 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len); 1629 sc->cmdq[sc->cmdq_last].func = func; 1630 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE; 1631 URTWN_CMDQ_UNLOCK(sc); 1632 1633 ieee80211_runtask(ic, &sc->cmdq_task); 1634 1635 return (0); 1636 } 1637 1638 static __inline void 1639 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1640 { 1641 1642 sc->sc_rf_write(sc, chain, addr, val); 1643 } 1644 1645 static void 1646 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1647 uint32_t val) 1648 { 1649 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1650 SM(R92C_LSSI_PARAM_ADDR, addr) | 1651 SM(R92C_LSSI_PARAM_DATA, val)); 1652 } 1653 1654 static void 1655 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1656 uint32_t val) 1657 { 1658 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1659 SM(R88E_LSSI_PARAM_ADDR, addr) | 1660 SM(R92C_LSSI_PARAM_DATA, val)); 1661 } 1662 1663 static uint32_t 1664 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1665 { 1666 uint32_t reg[R92C_MAX_CHAINS], val; 1667 1668 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1669 if (chain != 0) 1670 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1671 1672 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1673 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1674 urtwn_ms_delay(sc); 1675 1676 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1677 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1678 R92C_HSSI_PARAM2_READ_EDGE); 1679 urtwn_ms_delay(sc); 1680 1681 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1682 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1683 urtwn_ms_delay(sc); 1684 1685 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1686 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1687 else 1688 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1689 return (MS(val, R92C_LSSI_READBACK_DATA)); 1690 } 1691 1692 static int 1693 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1694 { 1695 usb_error_t error; 1696 int ntries; 1697 1698 error = urtwn_write_4(sc, R92C_LLT_INIT, 1699 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1700 SM(R92C_LLT_INIT_ADDR, addr) | 1701 SM(R92C_LLT_INIT_DATA, data)); 1702 if (error != USB_ERR_NORMAL_COMPLETION) 1703 return (EIO); 1704 /* Wait for write operation to complete. */ 1705 for (ntries = 0; ntries < 20; ntries++) { 1706 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1707 R92C_LLT_INIT_OP_NO_ACTIVE) 1708 return (0); 1709 urtwn_ms_delay(sc); 1710 } 1711 return (ETIMEDOUT); 1712 } 1713 1714 static int 1715 urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1716 { 1717 uint32_t reg; 1718 usb_error_t error; 1719 int ntries; 1720 1721 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1722 return (EFAULT); 1723 1724 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1725 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1726 reg &= ~R92C_EFUSE_CTRL_VALID; 1727 1728 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1729 if (error != USB_ERR_NORMAL_COMPLETION) 1730 return (EIO); 1731 /* Wait for read operation to complete. */ 1732 for (ntries = 0; ntries < 100; ntries++) { 1733 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1734 if (reg & R92C_EFUSE_CTRL_VALID) 1735 break; 1736 urtwn_ms_delay(sc); 1737 } 1738 if (ntries == 100) { 1739 device_printf(sc->sc_dev, 1740 "could not read efuse byte at address 0x%x\n", 1741 sc->last_rom_addr); 1742 return (ETIMEDOUT); 1743 } 1744 1745 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1746 sc->last_rom_addr++; 1747 1748 return (0); 1749 } 1750 1751 static int 1752 urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1753 uint8_t msk) 1754 { 1755 uint8_t reg; 1756 int i, error; 1757 1758 for (i = 0; i < 4; i++) { 1759 if (msk & (1 << i)) 1760 continue; 1761 error = urtwn_efuse_read_next(sc, ®); 1762 if (error != 0) 1763 return (error); 1764 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1765 off * 8 + i * 2, reg); 1766 rom[off * 8 + i * 2 + 0] = reg; 1767 1768 error = urtwn_efuse_read_next(sc, ®); 1769 if (error != 0) 1770 return (error); 1771 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1772 off * 8 + i * 2 + 1, reg); 1773 rom[off * 8 + i * 2 + 1] = reg; 1774 } 1775 1776 return (0); 1777 } 1778 1779 #ifdef USB_DEBUG 1780 static void 1781 urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1782 { 1783 int i; 1784 1785 /* Dump ROM contents. */ 1786 device_printf(sc->sc_dev, "%s:", __func__); 1787 for (i = 0; i < size; i++) { 1788 if (i % 32 == 0) 1789 kprintf("\n%03X: ", i); 1790 else if (i % 4 == 0) 1791 kprintf(" "); 1792 1793 kprintf("%02X", rom[i]); 1794 } 1795 kprintf("\n"); 1796 } 1797 #endif 1798 1799 static int 1800 urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1801 { 1802 #define URTWN_CHK(res) do { \ 1803 if ((error = res) != 0) \ 1804 goto end; \ 1805 } while(0) 1806 uint8_t msk, off, reg; 1807 int error; 1808 1809 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1810 1811 /* Read full ROM image. */ 1812 sc->last_rom_addr = 0; 1813 memset(rom, 0xff, size); 1814 1815 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1816 while (reg != 0xff) { 1817 /* check for extended header */ 1818 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1819 off = reg >> 5; 1820 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1821 1822 if ((reg & 0x0f) != 0x0f) 1823 off = ((reg & 0xf0) >> 1) | off; 1824 else 1825 continue; 1826 } else 1827 off = reg >> 4; 1828 msk = reg & 0xf; 1829 1830 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1831 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1832 } 1833 1834 end: 1835 1836 #ifdef USB_DEBUG 1837 if (sc->sc_debug & URTWN_DEBUG_ROM) 1838 urtwn_dump_rom_contents(sc, rom, size); 1839 #endif 1840 1841 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1842 1843 if (error != 0) { 1844 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1845 __func__); 1846 } 1847 1848 return (error); 1849 #undef URTWN_CHK 1850 } 1851 1852 static int 1853 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1854 { 1855 usb_error_t error; 1856 uint32_t reg; 1857 1858 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1859 if (error != USB_ERR_NORMAL_COMPLETION) 1860 return (EIO); 1861 1862 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1863 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1864 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1865 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1866 if (error != USB_ERR_NORMAL_COMPLETION) 1867 return (EIO); 1868 } 1869 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1870 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1871 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1872 reg | R92C_SYS_FUNC_EN_ELDR); 1873 if (error != USB_ERR_NORMAL_COMPLETION) 1874 return (EIO); 1875 } 1876 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1877 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1878 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1879 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1880 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1881 if (error != USB_ERR_NORMAL_COMPLETION) 1882 return (EIO); 1883 } 1884 1885 return (0); 1886 } 1887 1888 static int 1889 urtwn_read_chipid(struct urtwn_softc *sc) 1890 { 1891 uint32_t reg; 1892 1893 if (sc->chip & URTWN_CHIP_88E) 1894 return (0); 1895 1896 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1897 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1898 return (EIO); 1899 1900 if (reg & R92C_SYS_CFG_TYPE_92C) { 1901 sc->chip |= URTWN_CHIP_92C; 1902 /* Check if it is a castrated 8192C. */ 1903 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1904 R92C_HPON_FSM_CHIP_BONDING_ID) == 1905 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1906 sc->chip |= URTWN_CHIP_92C_1T2R; 1907 } 1908 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1909 sc->chip |= URTWN_CHIP_UMC; 1910 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1911 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1912 } 1913 return (0); 1914 } 1915 1916 static int 1917 urtwn_read_rom(struct urtwn_softc *sc) 1918 { 1919 struct r92c_rom *rom = &sc->rom.r92c_rom; 1920 int error; 1921 1922 /* Read full ROM image. */ 1923 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1924 if (error != 0) 1925 return (error); 1926 1927 /* XXX Weird but this is what the vendor driver does. */ 1928 sc->last_rom_addr = 0x1fa; 1929 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1930 if (error != 0) 1931 return (error); 1932 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: PA setting=0x%x\n", __func__, 1933 sc->pa_setting); 1934 1935 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1936 1937 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1938 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type=%d\n", 1939 __func__, sc->regulatory); 1940 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1941 1942 sc->sc_rf_write = urtwn_r92c_rf_write; 1943 sc->sc_power_on = urtwn_r92c_power_on; 1944 sc->sc_power_off = urtwn_r92c_power_off; 1945 1946 return (0); 1947 } 1948 1949 static int 1950 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1951 { 1952 struct r88e_rom *rom = &sc->rom.r88e_rom; 1953 int error; 1954 1955 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(sc->rom.r88e_rom)); 1956 if (error != 0) 1957 return (error); 1958 1959 sc->bw20_tx_pwr_diff = (rom->tx_pwr_diff >> 4); 1960 if (sc->bw20_tx_pwr_diff & 0x08) 1961 sc->bw20_tx_pwr_diff |= 0xf0; 1962 sc->ofdm_tx_pwr_diff = (rom->tx_pwr_diff & 0xf); 1963 if (sc->ofdm_tx_pwr_diff & 0x08) 1964 sc->ofdm_tx_pwr_diff |= 0xf0; 1965 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 1966 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type %d\n", 1967 __func__,sc->regulatory); 1968 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1969 1970 sc->sc_rf_write = urtwn_r88e_rf_write; 1971 sc->sc_power_on = urtwn_r88e_power_on; 1972 sc->sc_power_off = urtwn_r88e_power_off; 1973 1974 return (0); 1975 } 1976 1977 static __inline uint8_t 1978 rate2ridx(uint8_t rate) 1979 { 1980 if (rate & IEEE80211_RATE_MCS) { 1981 /* 11n rates start at idx 12 */ 1982 return ((rate & 0xf) + 12); 1983 } 1984 switch (rate) { 1985 /* 11g */ 1986 case 12: return 4; 1987 case 18: return 5; 1988 case 24: return 6; 1989 case 36: return 7; 1990 case 48: return 8; 1991 case 72: return 9; 1992 case 96: return 10; 1993 case 108: return 11; 1994 /* 11b */ 1995 case 2: return 0; 1996 case 4: return 1; 1997 case 11: return 2; 1998 case 22: return 3; 1999 default: return URTWN_RIDX_UNKNOWN; 2000 } 2001 } 2002 2003 /* 2004 * Initialize rate adaptation in firmware. 2005 */ 2006 static int 2007 urtwn_ra_init(struct urtwn_softc *sc) 2008 { 2009 struct ieee80211com *ic = &sc->sc_ic; 2010 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2011 struct ieee80211_node *ni; 2012 struct ieee80211_rateset *rs, *rs_ht; 2013 struct r92c_fw_cmd_macid_cfg cmd; 2014 uint32_t rates, basicrates; 2015 uint8_t mode, ridx; 2016 int maxrate, maxbasicrate, error, i; 2017 2018 ni = ieee80211_ref_node(vap->iv_bss); 2019 rs = &ni->ni_rates; 2020 rs_ht = (struct ieee80211_rateset *) &ni->ni_htrates; 2021 2022 /* Get normal and basic rates mask. */ 2023 rates = basicrates = 0; 2024 maxrate = maxbasicrate = 0; 2025 2026 /* This is for 11bg */ 2027 for (i = 0; i < rs->rs_nrates; i++) { 2028 /* Convert 802.11 rate to HW rate index. */ 2029 ridx = rate2ridx(IEEE80211_RV(rs->rs_rates[i])); 2030 if (ridx == URTWN_RIDX_UNKNOWN) /* Unknown rate, skip. */ 2031 continue; 2032 rates |= 1 << ridx; 2033 if (ridx > maxrate) 2034 maxrate = ridx; 2035 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 2036 basicrates |= 1 << ridx; 2037 if (ridx > maxbasicrate) 2038 maxbasicrate = ridx; 2039 } 2040 } 2041 2042 /* If we're doing 11n, enable 11n rates */ 2043 if (ni->ni_flags & IEEE80211_NODE_HT) { 2044 for (i = 0; i < rs_ht->rs_nrates; i++) { 2045 if ((rs_ht->rs_rates[i] & 0x7f) > 0xf) 2046 continue; 2047 /* 11n rates start at index 12 */ 2048 ridx = ((rs_ht->rs_rates[i]) & 0xf) + 12; 2049 rates |= (1 << ridx); 2050 2051 /* Guard against the rate table being oddly ordered */ 2052 if (ridx > maxrate) 2053 maxrate = ridx; 2054 } 2055 } 2056 2057 #if 0 2058 if (ic->ic_curmode == IEEE80211_MODE_11NG) 2059 raid = R92C_RAID_11GN; 2060 #endif 2061 /* NB: group addressed frames are done at 11bg rates for now */ 2062 if (ic->ic_curmode == IEEE80211_MODE_11B) 2063 mode = R92C_RAID_11B; 2064 else 2065 mode = R92C_RAID_11BG; 2066 /* XXX misleading 'mode' value here for unicast frames */ 2067 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, 2068 "%s: mode 0x%x, rates 0x%08x, basicrates 0x%08x\n", __func__, 2069 mode, rates, basicrates); 2070 2071 /* Set rates mask for group addressed frames. */ 2072 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 2073 cmd.mask = htole32(mode << 28 | basicrates); 2074 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 2075 if (error != 0) { 2076 ieee80211_free_node(ni); 2077 device_printf(sc->sc_dev, 2078 "could not add broadcast station\n"); 2079 return (error); 2080 } 2081 2082 /* Set initial MRR rate. */ 2083 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxbasicrate %d\n", __func__, 2084 maxbasicrate); 2085 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 2086 maxbasicrate); 2087 2088 /* Set rates mask for unicast frames. */ 2089 if (ni->ni_flags & IEEE80211_NODE_HT) 2090 mode = R92C_RAID_11GN; 2091 else if (ic->ic_curmode == IEEE80211_MODE_11B) 2092 mode = R92C_RAID_11B; 2093 else 2094 mode = R92C_RAID_11BG; 2095 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 2096 cmd.mask = htole32(mode << 28 | rates); 2097 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 2098 if (error != 0) { 2099 ieee80211_free_node(ni); 2100 device_printf(sc->sc_dev, "could not add BSS station\n"); 2101 return (error); 2102 } 2103 /* Set initial MRR rate. */ 2104 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxrate %d\n", __func__, 2105 maxrate); 2106 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 2107 maxrate); 2108 2109 /* Indicate highest supported rate. */ 2110 if (ni->ni_flags & IEEE80211_NODE_HT) 2111 ni->ni_txrate = rs_ht->rs_rates[rs_ht->rs_nrates - 1] 2112 | IEEE80211_RATE_MCS; 2113 else 2114 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 2115 ieee80211_free_node(ni); 2116 2117 return (0); 2118 } 2119 2120 static void 2121 urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2122 { 2123 struct r92c_tx_desc *txd = &uvp->bcn_desc; 2124 2125 txd->txdw0 = htole32( 2126 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 2127 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2128 txd->txdw1 = htole32( 2129 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 2130 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2131 2132 if (sc->chip & URTWN_CHIP_88E) { 2133 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 2134 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 2135 } else { 2136 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 2137 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2138 } 2139 2140 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 2141 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 2142 } 2143 2144 static int 2145 urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 2146 { 2147 struct ieee80211vap *vap = ni->ni_vap; 2148 struct urtwn_vap *uvp = URTWN_VAP(vap); 2149 struct mbuf *m; 2150 int error; 2151 2152 URTWN_ASSERT_LOCKED(sc); 2153 2154 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 2155 return (EINVAL); 2156 2157 m = ieee80211_beacon_alloc(ni); 2158 if (m == NULL) { 2159 device_printf(sc->sc_dev, 2160 "%s: could not allocate beacon frame\n", __func__); 2161 return (ENOMEM); 2162 } 2163 2164 if (uvp->bcn_mbuf != NULL) 2165 m_freem(uvp->bcn_mbuf); 2166 2167 uvp->bcn_mbuf = m; 2168 2169 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 2170 return (error); 2171 2172 /* XXX bcnq stuck workaround */ 2173 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 2174 return (error); 2175 2176 URTWN_DPRINTF(sc, URTWN_DEBUG_BEACON, "%s: beacon was %srecognized\n", 2177 __func__, urtwn_read_1(sc, R92C_TDECTRL + 2) & 2178 (R92C_TDECTRL_BCN_VALID >> 16) ? "" : "not "); 2179 2180 return (0); 2181 } 2182 2183 static void 2184 urtwn_update_beacon(struct ieee80211vap *vap, int item) 2185 { 2186 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2187 struct urtwn_vap *uvp = URTWN_VAP(vap); 2188 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 2189 struct ieee80211_node *ni = vap->iv_bss; 2190 int mcast = 0; 2191 2192 URTWN_LOCK(sc); 2193 if (uvp->bcn_mbuf == NULL) { 2194 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 2195 if (uvp->bcn_mbuf == NULL) { 2196 device_printf(sc->sc_dev, 2197 "%s: could not allocate beacon frame\n", __func__); 2198 URTWN_UNLOCK(sc); 2199 return; 2200 } 2201 } 2202 URTWN_UNLOCK(sc); 2203 2204 if (item == IEEE80211_BEACON_TIM) 2205 mcast = 1; /* XXX */ 2206 2207 setbit(bo->bo_flags, item); 2208 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 2209 2210 URTWN_LOCK(sc); 2211 urtwn_tx_beacon(sc, uvp); 2212 URTWN_UNLOCK(sc); 2213 } 2214 2215 /* 2216 * Push a beacon frame into the chip. Beacon will 2217 * be repeated by the chip every R92C_BCN_INTERVAL. 2218 */ 2219 static int 2220 urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2221 { 2222 struct r92c_tx_desc *desc = &uvp->bcn_desc; 2223 struct urtwn_data *bf; 2224 2225 URTWN_ASSERT_LOCKED(sc); 2226 2227 bf = urtwn_getbuf(sc); 2228 if (bf == NULL) 2229 return (ENOMEM); 2230 2231 memcpy(bf->buf, desc, sizeof(*desc)); 2232 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 2233 2234 sc->sc_txtimer = 5; 2235 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2236 2237 return (0); 2238 } 2239 2240 static int 2241 urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2242 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2243 { 2244 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2245 uint8_t i; 2246 2247 if (!(&vap->iv_nw_keys[0] <= k && 2248 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2249 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2250 URTWN_LOCK(sc); 2251 /* 2252 * First 4 slots for group keys, 2253 * what is left - for pairwise. 2254 * XXX incompatible with IBSS RSN. 2255 */ 2256 for (i = IEEE80211_WEP_NKID; 2257 i < R92C_CAM_ENTRY_COUNT; i++) { 2258 if ((sc->keys_bmap & (1 << i)) == 0) { 2259 sc->keys_bmap |= 1 << i; 2260 *keyix = i; 2261 break; 2262 } 2263 } 2264 URTWN_UNLOCK(sc); 2265 if (i == R92C_CAM_ENTRY_COUNT) { 2266 device_printf(sc->sc_dev, 2267 "%s: no free space in the key table\n", 2268 __func__); 2269 return 0; 2270 } 2271 } else 2272 *keyix = 0; 2273 } else { 2274 *keyix = k - vap->iv_nw_keys; 2275 } 2276 *rxkeyix = *keyix; 2277 return 1; 2278 } 2279 2280 static void 2281 urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data) 2282 { 2283 struct ieee80211_key *k = &data->key; 2284 uint8_t algo, keyid; 2285 int i, error; 2286 2287 if (k->wk_keyix < IEEE80211_WEP_NKID) 2288 keyid = k->wk_keyix; 2289 else 2290 keyid = 0; 2291 2292 /* Map net80211 cipher to HW crypto algorithm. */ 2293 switch (k->wk_cipher->ic_cipher) { 2294 case IEEE80211_CIPHER_WEP: 2295 if (k->wk_keylen < 8) 2296 algo = R92C_CAM_ALGO_WEP40; 2297 else 2298 algo = R92C_CAM_ALGO_WEP104; 2299 break; 2300 case IEEE80211_CIPHER_TKIP: 2301 algo = R92C_CAM_ALGO_TKIP; 2302 break; 2303 case IEEE80211_CIPHER_AES_CCM: 2304 algo = R92C_CAM_ALGO_AES; 2305 break; 2306 default: 2307 device_printf(sc->sc_dev, "%s: undefined cipher %d\n", 2308 __func__, k->wk_cipher->ic_cipher); 2309 return; 2310 } 2311 2312 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2313 "%s: keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, " 2314 "macaddr %s\n", __func__, k->wk_keyix, keyid, 2315 k->wk_cipher->ic_cipher, algo, k->wk_flags, k->wk_keylen, 2316 ether_sprintf(k->wk_macaddr)); 2317 2318 /* Write key. */ 2319 for (i = 0; i < 4; i++) { 2320 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 2321 le32dec(&k->wk_key[i * 4])); 2322 if (error != 0) 2323 goto fail; 2324 } 2325 2326 /* Write CTL0 last since that will validate the CAM entry. */ 2327 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 2328 le32dec(&k->wk_macaddr[2])); 2329 if (error != 0) 2330 goto fail; 2331 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 2332 SM(R92C_CAM_ALGO, algo) | 2333 SM(R92C_CAM_KEYID, keyid) | 2334 SM(R92C_CAM_MACLO, le16dec(&k->wk_macaddr[0])) | 2335 R92C_CAM_VALID); 2336 if (error != 0) 2337 goto fail; 2338 2339 return; 2340 2341 fail: 2342 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error); 2343 } 2344 2345 static void 2346 urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data) 2347 { 2348 struct ieee80211_key *k = &data->key; 2349 int i; 2350 2351 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2352 "%s: keyix %d, flags %04X, macaddr %s\n", __func__, 2353 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr)); 2354 2355 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0); 2356 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0); 2357 2358 /* Clear key. */ 2359 for (i = 0; i < 4; i++) 2360 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0); 2361 sc->keys_bmap &= ~(1 << k->wk_keyix); 2362 } 2363 2364 static int 2365 urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k) 2366 { 2367 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2368 2369 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2370 /* Not for us. */ 2371 return (1); 2372 } 2373 2374 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb)); 2375 } 2376 2377 static int 2378 urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2379 { 2380 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2381 2382 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2383 /* Not for us. */ 2384 return (1); 2385 } 2386 2387 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb)); 2388 } 2389 2390 static void 2391 urtwn_tsf_task_adhoc(void *arg, int pending) 2392 { 2393 struct ieee80211vap *vap = arg; 2394 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2395 struct ieee80211_node *ni; 2396 uint32_t reg; 2397 2398 URTWN_LOCK(sc); 2399 ni = ieee80211_ref_node(vap->iv_bss); 2400 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 2401 2402 /* Accept beacons with the same BSSID. */ 2403 urtwn_set_rx_bssid_all(sc, 0); 2404 2405 /* Enable synchronization. */ 2406 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 2407 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2408 2409 /* Synchronize. */ 2410 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 2411 2412 /* Disable synchronization. */ 2413 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 2414 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2415 2416 /* Remove beacon filter. */ 2417 urtwn_set_rx_bssid_all(sc, 1); 2418 2419 /* Enable beaconing. */ 2420 urtwn_write_1(sc, R92C_MBID_NUM, 2421 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2422 reg |= R92C_BCN_CTRL_EN_BCN; 2423 2424 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2425 ieee80211_free_node(ni); 2426 URTWN_UNLOCK(sc); 2427 } 2428 2429 static void 2430 urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 2431 { 2432 struct ieee80211com *ic = &sc->sc_ic; 2433 struct urtwn_vap *uvp = URTWN_VAP(vap); 2434 2435 /* Reset TSF. */ 2436 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2437 2438 switch (vap->iv_opmode) { 2439 case IEEE80211_M_STA: 2440 /* Enable TSF synchronization. */ 2441 urtwn_write_1(sc, R92C_BCN_CTRL, 2442 urtwn_read_1(sc, R92C_BCN_CTRL) & 2443 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 2444 break; 2445 case IEEE80211_M_IBSS: 2446 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 2447 break; 2448 case IEEE80211_M_HOSTAP: 2449 /* Enable beaconing. */ 2450 urtwn_write_1(sc, R92C_MBID_NUM, 2451 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2452 urtwn_write_1(sc, R92C_BCN_CTRL, 2453 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 2454 break; 2455 default: 2456 device_printf(sc->sc_dev, "undefined opmode %d\n", 2457 vap->iv_opmode); 2458 return; 2459 } 2460 } 2461 2462 static void 2463 urtwn_get_tsf(struct urtwn_softc *sc, uint64_t *buf) 2464 { 2465 urtwn_read_region_1(sc, R92C_TSFTR, (uint8_t *)buf, sizeof(*buf)); 2466 } 2467 2468 static void 2469 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 2470 { 2471 uint8_t reg; 2472 2473 if (led == URTWN_LED_LINK) { 2474 if (sc->chip & URTWN_CHIP_88E) { 2475 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 2476 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 2477 if (!on) { 2478 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 2479 urtwn_write_1(sc, R92C_LEDCFG2, 2480 reg | R92C_LEDCFG0_DIS); 2481 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 2482 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 2483 0xfe); 2484 } 2485 } else { 2486 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 2487 if (!on) 2488 reg |= R92C_LEDCFG0_DIS; 2489 urtwn_write_1(sc, R92C_LEDCFG0, reg); 2490 } 2491 sc->ledlink = on; /* Save LED state. */ 2492 } 2493 } 2494 2495 static void 2496 urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 2497 { 2498 uint8_t reg; 2499 2500 reg = urtwn_read_1(sc, R92C_MSR); 2501 reg = (reg & ~R92C_MSR_MASK) | mode; 2502 urtwn_write_1(sc, R92C_MSR, reg); 2503 } 2504 2505 static void 2506 urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 2507 const struct ieee80211_rx_stats *rxs, 2508 int rssi, int nf) 2509 { 2510 struct ieee80211vap *vap = ni->ni_vap; 2511 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2512 struct urtwn_vap *uvp = URTWN_VAP(vap); 2513 uint64_t ni_tstamp, curr_tstamp; 2514 2515 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 2516 2517 if (vap->iv_state == IEEE80211_S_RUN && 2518 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 2519 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 2520 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 2521 URTWN_LOCK(sc); 2522 urtwn_get_tsf(sc, &curr_tstamp); 2523 URTWN_UNLOCK(sc); 2524 curr_tstamp = le64toh(curr_tstamp); 2525 2526 if (ni_tstamp >= curr_tstamp) 2527 (void) ieee80211_ibss_merge(ni); 2528 } 2529 } 2530 2531 static int 2532 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2533 { 2534 struct urtwn_vap *uvp = URTWN_VAP(vap); 2535 struct ieee80211com *ic = vap->iv_ic; 2536 struct urtwn_softc *sc = ic->ic_softc; 2537 struct ieee80211_node *ni; 2538 enum ieee80211_state ostate; 2539 uint32_t reg; 2540 uint8_t mode; 2541 int error = 0; 2542 2543 ostate = vap->iv_state; 2544 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s -> %s\n", 2545 ieee80211_state_name[ostate], ieee80211_state_name[nstate]); 2546 2547 IEEE80211_UNLOCK(ic); 2548 URTWN_LOCK(sc); 2549 callout_stop(&sc->sc_watchdog_ch); 2550 2551 if (ostate == IEEE80211_S_RUN) { 2552 /* Stop calibration. */ 2553 callout_stop(&sc->sc_calib_to); 2554 2555 /* Turn link LED off. */ 2556 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2557 2558 /* Set media status to 'No Link'. */ 2559 urtwn_set_mode(sc, R92C_MSR_NOLINK); 2560 2561 /* Stop Rx of data frames. */ 2562 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2563 2564 /* Disable TSF synchronization. */ 2565 urtwn_write_1(sc, R92C_BCN_CTRL, 2566 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 2567 R92C_BCN_CTRL_DIS_TSF_UDT0); 2568 2569 /* Disable beaconing. */ 2570 urtwn_write_1(sc, R92C_MBID_NUM, 2571 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 2572 2573 /* Reset TSF. */ 2574 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2575 2576 /* Reset EDCA parameters. */ 2577 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2578 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2579 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2580 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2581 } 2582 2583 switch (nstate) { 2584 case IEEE80211_S_INIT: 2585 /* Turn link LED off. */ 2586 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2587 break; 2588 case IEEE80211_S_SCAN: 2589 /* Pause AC Tx queues. */ 2590 urtwn_write_1(sc, R92C_TXPAUSE, 2591 urtwn_read_1(sc, R92C_TXPAUSE) | R92C_TX_QUEUE_AC); 2592 break; 2593 case IEEE80211_S_AUTH: 2594 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2595 break; 2596 case IEEE80211_S_RUN: 2597 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2598 /* Turn link LED on. */ 2599 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2600 break; 2601 } 2602 2603 ni = ieee80211_ref_node(vap->iv_bss); 2604 2605 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 2606 ni->ni_chan == IEEE80211_CHAN_ANYC) { 2607 device_printf(sc->sc_dev, 2608 "%s: could not move to RUN state\n", __func__); 2609 error = EINVAL; 2610 goto end_run; 2611 } 2612 2613 switch (vap->iv_opmode) { 2614 case IEEE80211_M_STA: 2615 mode = R92C_MSR_INFRA; 2616 break; 2617 case IEEE80211_M_IBSS: 2618 mode = R92C_MSR_ADHOC; 2619 break; 2620 case IEEE80211_M_HOSTAP: 2621 mode = R92C_MSR_AP; 2622 break; 2623 default: 2624 device_printf(sc->sc_dev, "undefined opmode %d\n", 2625 vap->iv_opmode); 2626 error = EINVAL; 2627 goto end_run; 2628 } 2629 2630 /* Set media status to 'Associated'. */ 2631 urtwn_set_mode(sc, mode); 2632 2633 /* Set BSSID. */ 2634 urtwn_write_4(sc, R92C_BSSID + 0, le32dec(&ni->ni_bssid[0])); 2635 urtwn_write_4(sc, R92C_BSSID + 4, le16dec(&ni->ni_bssid[4])); 2636 2637 if (ic->ic_curmode == IEEE80211_MODE_11B) 2638 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2639 else /* 802.11b/g */ 2640 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2641 2642 /* Enable Rx of data frames. */ 2643 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2644 2645 /* Flush all AC queues. */ 2646 urtwn_write_1(sc, R92C_TXPAUSE, 0); 2647 2648 /* Set beacon interval. */ 2649 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2650 2651 /* Allow Rx from our BSSID only. */ 2652 if (ic->ic_promisc == 0) { 2653 reg = urtwn_read_4(sc, R92C_RCR); 2654 2655 if (vap->iv_opmode != IEEE80211_M_HOSTAP) 2656 reg |= R92C_RCR_CBSSID_DATA; 2657 if (vap->iv_opmode != IEEE80211_M_IBSS) 2658 reg |= R92C_RCR_CBSSID_BCN; 2659 2660 urtwn_write_4(sc, R92C_RCR, reg); 2661 } 2662 2663 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 2664 vap->iv_opmode == IEEE80211_M_IBSS) { 2665 error = urtwn_setup_beacon(sc, ni); 2666 if (error != 0) { 2667 device_printf(sc->sc_dev, 2668 "unable to push beacon into the chip, " 2669 "error %d\n", error); 2670 goto end_run; 2671 } 2672 } 2673 2674 /* Enable TSF synchronization. */ 2675 urtwn_tsf_sync_enable(sc, vap); 2676 2677 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2678 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2679 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2680 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2681 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2682 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2683 2684 /* Intialize rate adaptation. */ 2685 if (!(sc->chip & URTWN_CHIP_88E)) 2686 urtwn_ra_init(sc); 2687 /* Turn link LED on. */ 2688 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2689 2690 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2691 /* Reset temperature calibration state machine. */ 2692 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 2693 sc->thcal_lctemp = 0; 2694 /* Start periodic calibration. */ 2695 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2696 2697 end_run: 2698 ieee80211_free_node(ni); 2699 break; 2700 default: 2701 break; 2702 } 2703 2704 URTWN_UNLOCK(sc); 2705 IEEE80211_LOCK(ic); 2706 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2707 } 2708 2709 static void 2710 urtwn_calib_to(void *arg) 2711 { 2712 struct urtwn_softc *sc = arg; 2713 2714 /* Do it in a process context. */ 2715 urtwn_cmd_sleepable(sc, NULL, 0, urtwn_calib_cb); 2716 } 2717 2718 static void 2719 urtwn_calib_cb(struct urtwn_softc *sc, union sec_param *data) 2720 { 2721 /* Do temperature compensation. */ 2722 urtwn_temp_calib(sc); 2723 2724 if ((urtwn_read_1(sc, R92C_MSR) & R92C_MSR_MASK) != R92C_MSR_NOLINK) 2725 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2726 } 2727 2728 static void 2729 urtwn_watchdog(void *arg) 2730 { 2731 struct urtwn_softc *sc = arg; 2732 2733 if (sc->sc_txtimer > 0) { 2734 if (--sc->sc_txtimer == 0) { 2735 device_printf(sc->sc_dev, "device timeout\n"); 2736 #if defined(__DragonFly__) 2737 /* unimplemented */ 2738 #else 2739 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2740 #endif 2741 return; 2742 } 2743 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2744 } 2745 } 2746 2747 static void 2748 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2749 { 2750 int pwdb; 2751 2752 /* Convert antenna signal to percentage. */ 2753 if (rssi <= -100 || rssi >= 20) 2754 pwdb = 0; 2755 else if (rssi >= 0) 2756 pwdb = 100; 2757 else 2758 pwdb = 100 + rssi; 2759 if (!(sc->chip & URTWN_CHIP_88E)) { 2760 if (rate <= URTWN_RIDX_CCK11) { 2761 /* CCK gain is smaller than OFDM/MCS gain. */ 2762 pwdb += 6; 2763 if (pwdb > 100) 2764 pwdb = 100; 2765 if (pwdb <= 14) 2766 pwdb -= 4; 2767 else if (pwdb <= 26) 2768 pwdb -= 8; 2769 else if (pwdb <= 34) 2770 pwdb -= 6; 2771 else if (pwdb <= 42) 2772 pwdb -= 2; 2773 } 2774 } 2775 if (sc->avg_pwdb == -1) /* Init. */ 2776 sc->avg_pwdb = pwdb; 2777 else if (sc->avg_pwdb < pwdb) 2778 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2779 else 2780 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2781 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: PWDB %d, EMA %d\n", __func__, 2782 pwdb, sc->avg_pwdb); 2783 } 2784 2785 static int8_t 2786 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2787 { 2788 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2789 struct r92c_rx_phystat *phy; 2790 struct r92c_rx_cck *cck; 2791 uint8_t rpt; 2792 int8_t rssi; 2793 2794 if (rate <= URTWN_RIDX_CCK11) { 2795 cck = (struct r92c_rx_cck *)physt; 2796 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2797 rpt = (cck->agc_rpt >> 5) & 0x3; 2798 rssi = (cck->agc_rpt & 0x1f) << 1; 2799 } else { 2800 rpt = (cck->agc_rpt >> 6) & 0x3; 2801 rssi = cck->agc_rpt & 0x3e; 2802 } 2803 rssi = cckoff[rpt] - rssi; 2804 } else { /* OFDM/HT. */ 2805 phy = (struct r92c_rx_phystat *)physt; 2806 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2807 } 2808 return (rssi); 2809 } 2810 2811 static int8_t 2812 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2813 { 2814 struct r92c_rx_phystat *phy; 2815 struct r88e_rx_cck *cck; 2816 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2817 int8_t rssi; 2818 2819 rssi = 0; 2820 if (rate <= URTWN_RIDX_CCK11) { 2821 cck = (struct r88e_rx_cck *)physt; 2822 cck_agc_rpt = cck->agc_rpt; 2823 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2824 vga_idx = cck_agc_rpt & 0x1f; 2825 switch (lna_idx) { 2826 case 7: 2827 if (vga_idx <= 27) 2828 rssi = -100 + 2* (27 - vga_idx); 2829 else 2830 rssi = -100; 2831 break; 2832 case 6: 2833 rssi = -48 + 2 * (2 - vga_idx); 2834 break; 2835 case 5: 2836 rssi = -42 + 2 * (7 - vga_idx); 2837 break; 2838 case 4: 2839 rssi = -36 + 2 * (7 - vga_idx); 2840 break; 2841 case 3: 2842 rssi = -24 + 2 * (7 - vga_idx); 2843 break; 2844 case 2: 2845 rssi = -12 + 2 * (5 - vga_idx); 2846 break; 2847 case 1: 2848 rssi = 8 - (2 * vga_idx); 2849 break; 2850 case 0: 2851 rssi = 14 - (2 * vga_idx); 2852 break; 2853 } 2854 rssi += 6; 2855 } else { /* OFDM/HT. */ 2856 phy = (struct r92c_rx_phystat *)physt; 2857 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2858 } 2859 return (rssi); 2860 } 2861 2862 static int 2863 urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2864 struct mbuf *m, struct urtwn_data *data) 2865 { 2866 const struct ieee80211_txparam *tp; 2867 struct ieee80211com *ic = &sc->sc_ic; 2868 struct ieee80211vap *vap = ni->ni_vap; 2869 struct ieee80211_key *k = NULL; 2870 struct ieee80211_channel *chan; 2871 struct ieee80211_frame *wh; 2872 struct r92c_tx_desc *txd; 2873 uint8_t macid, raid, rate, ridx, subtype, type, tid, qsel; 2874 int hasqos, ismcast; 2875 2876 URTWN_ASSERT_LOCKED(sc); 2877 2878 /* 2879 * Software crypto. 2880 */ 2881 wh = mtod(m, struct ieee80211_frame *); 2882 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2883 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2884 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2885 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2886 2887 /* Select TX ring for this frame. */ 2888 if (hasqos) { 2889 tid = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2890 tid &= IEEE80211_QOS_TID; 2891 } else 2892 tid = 0; 2893 2894 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ? 2895 ni->ni_chan : ic->ic_curchan; 2896 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)]; 2897 2898 /* Choose a TX rate index. */ 2899 if (type == IEEE80211_FC0_TYPE_MGT) 2900 rate = tp->mgmtrate; 2901 else if (ismcast) 2902 rate = tp->mcastrate; 2903 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2904 rate = tp->ucastrate; 2905 else if (m->m_flags & M_EAPOL) 2906 rate = tp->mgmtrate; 2907 else { 2908 if (URTWN_CHIP_HAS_RATECTL(sc)) { 2909 /* XXX pass pktlen */ 2910 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2911 rate = ni->ni_txrate; 2912 } else { 2913 /* XXX TODO: drop the default rate for 11b/11g? */ 2914 if (ni->ni_flags & IEEE80211_NODE_HT) 2915 rate = IEEE80211_RATE_MCS | 0x4; /* MCS4 */ 2916 else if (ic->ic_curmode != IEEE80211_MODE_11B) 2917 rate = 108; 2918 else 2919 rate = 22; 2920 } 2921 } 2922 2923 /* 2924 * XXX TODO: this should be per-node, for 11b versus 11bg 2925 * nodes in hostap mode 2926 */ 2927 ridx = rate2ridx(rate); 2928 if (ni->ni_flags & IEEE80211_NODE_HT) 2929 raid = R92C_RAID_11GN; 2930 else if (ic->ic_curmode != IEEE80211_MODE_11B) 2931 raid = R92C_RAID_11BG; 2932 else 2933 raid = R92C_RAID_11B; 2934 2935 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2936 k = ieee80211_crypto_encap(ni, m); 2937 if (k == NULL) { 2938 device_printf(sc->sc_dev, 2939 "ieee80211_crypto_encap returns NULL.\n"); 2940 return (ENOBUFS); 2941 } 2942 2943 /* in case packet header moved, reset pointer */ 2944 wh = mtod(m, struct ieee80211_frame *); 2945 } 2946 2947 /* Fill Tx descriptor. */ 2948 txd = (struct r92c_tx_desc *)data->buf; 2949 memset(txd, 0, sizeof(*txd)); 2950 2951 txd->txdw0 |= htole32( 2952 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2953 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2954 if (ismcast) 2955 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2956 2957 if (!ismcast) { 2958 if (sc->chip & URTWN_CHIP_88E) { 2959 struct urtwn_node *un = URTWN_NODE(ni); 2960 macid = un->id; 2961 } else 2962 macid = URTWN_MACID_BSS; 2963 2964 if (type == IEEE80211_FC0_TYPE_DATA) { 2965 qsel = tid % URTWN_MAX_TID; 2966 2967 if (sc->chip & URTWN_CHIP_88E) { 2968 txd->txdw2 |= htole32( 2969 R88E_TXDW2_AGGBK | 2970 R88E_TXDW2_CCX_RPT); 2971 } else 2972 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2973 2974 /* protmode, non-HT */ 2975 /* XXX TODO: noack frames? */ 2976 if ((rate & 0x80) == 0 && 2977 (ic->ic_flags & IEEE80211_F_USEPROT)) { 2978 switch (ic->ic_protmode) { 2979 case IEEE80211_PROT_CTSONLY: 2980 txd->txdw4 |= htole32( 2981 R92C_TXDW4_CTS2SELF | 2982 R92C_TXDW4_HWRTSEN); 2983 break; 2984 case IEEE80211_PROT_RTSCTS: 2985 txd->txdw4 |= htole32( 2986 R92C_TXDW4_RTSEN | 2987 R92C_TXDW4_HWRTSEN); 2988 break; 2989 default: 2990 break; 2991 } 2992 } 2993 2994 /* protmode, HT */ 2995 /* XXX TODO: noack frames? */ 2996 if ((rate & 0x80) && 2997 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) { 2998 txd->txdw4 |= htole32( 2999 R92C_TXDW4_RTSEN | 3000 R92C_TXDW4_HWRTSEN); 3001 } 3002 3003 /* XXX TODO: rtsrate is configurable? 24mbit may 3004 * be a bit high for RTS rate? */ 3005 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 3006 URTWN_RIDX_OFDM24)); 3007 3008 txd->txdw5 |= htole32(0x0001ff00); 3009 } else /* IEEE80211_FC0_TYPE_MGT */ 3010 qsel = R92C_TXDW1_QSEL_MGNT; 3011 } else { 3012 macid = URTWN_MACID_BC; 3013 qsel = R92C_TXDW1_QSEL_MGNT; 3014 } 3015 3016 txd->txdw1 |= htole32( 3017 SM(R92C_TXDW1_QSEL, qsel) | 3018 SM(R92C_TXDW1_RAID, raid)); 3019 3020 /* XXX TODO: 40MHZ flag? */ 3021 /* XXX TODO: AMPDU flag? (AGG_ENABLE or AGG_BREAK?) Density shift? */ 3022 /* XXX Short preamble? */ 3023 /* XXX Short-GI? */ 3024 3025 if (sc->chip & URTWN_CHIP_88E) 3026 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 3027 else 3028 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 3029 3030 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 3031 3032 /* Force this rate if needed. */ 3033 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast || 3034 (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) || 3035 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 3036 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3037 3038 if (!hasqos) { 3039 /* Use HW sequence numbering for non-QoS frames. */ 3040 if (sc->chip & URTWN_CHIP_88E) 3041 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 3042 else 3043 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 3044 } else { 3045 /* Set sequence number. */ 3046 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 3047 } 3048 3049 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 3050 uint8_t cipher; 3051 3052 switch (k->wk_cipher->ic_cipher) { 3053 case IEEE80211_CIPHER_WEP: 3054 case IEEE80211_CIPHER_TKIP: 3055 cipher = R92C_TXDW1_CIPHER_RC4; 3056 break; 3057 case IEEE80211_CIPHER_AES_CCM: 3058 cipher = R92C_TXDW1_CIPHER_AES; 3059 break; 3060 default: 3061 device_printf(sc->sc_dev, "%s: unknown cipher %d\n", 3062 __func__, k->wk_cipher->ic_cipher); 3063 return (EINVAL); 3064 } 3065 3066 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 3067 } 3068 3069 if (ieee80211_radiotap_active_vap(vap)) { 3070 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3071 3072 tap->wt_flags = 0; 3073 if (k != NULL) 3074 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3075 ieee80211_radiotap_tx(vap, m); 3076 } 3077 3078 data->ni = ni; 3079 3080 urtwn_tx_start(sc, m, type, data); 3081 3082 return (0); 3083 } 3084 3085 static int 3086 urtwn_tx_raw(struct urtwn_softc *sc, struct ieee80211_node *ni, 3087 struct mbuf *m, struct urtwn_data *data, 3088 const struct ieee80211_bpf_params *params) 3089 { 3090 struct ieee80211vap *vap = ni->ni_vap; 3091 struct ieee80211_key *k = NULL; 3092 struct ieee80211_frame *wh; 3093 struct r92c_tx_desc *txd; 3094 uint8_t cipher, ridx, type; 3095 3096 /* Encrypt the frame if need be. */ 3097 cipher = R92C_TXDW1_CIPHER_NONE; 3098 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) { 3099 /* Retrieve key for TX. */ 3100 k = ieee80211_crypto_encap(ni, m); 3101 if (k == NULL) 3102 return (ENOBUFS); 3103 3104 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 3105 switch (k->wk_cipher->ic_cipher) { 3106 case IEEE80211_CIPHER_WEP: 3107 case IEEE80211_CIPHER_TKIP: 3108 cipher = R92C_TXDW1_CIPHER_RC4; 3109 break; 3110 case IEEE80211_CIPHER_AES_CCM: 3111 cipher = R92C_TXDW1_CIPHER_AES; 3112 break; 3113 default: 3114 device_printf(sc->sc_dev, 3115 "%s: unknown cipher %d\n", 3116 __func__, k->wk_cipher->ic_cipher); 3117 return (EINVAL); 3118 } 3119 } 3120 } 3121 3122 /* XXX TODO: 11n checks, matching urtwn_tx_data() */ 3123 3124 wh = mtod(m, struct ieee80211_frame *); 3125 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3126 3127 /* Fill Tx descriptor. */ 3128 txd = (struct r92c_tx_desc *)data->buf; 3129 memset(txd, 0, sizeof(*txd)); 3130 3131 txd->txdw0 |= htole32( 3132 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 3133 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 3134 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3135 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 3136 3137 if (params->ibp_flags & IEEE80211_BPF_RTS) 3138 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN); 3139 if (params->ibp_flags & IEEE80211_BPF_CTS) 3140 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF); 3141 if (txd->txdw4 & htole32(R92C_TXDW4_RTSEN | R92C_TXDW4_CTS2SELF)) { 3142 txd->txdw4 |= htole32(R92C_TXDW4_HWRTSEN); 3143 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 3144 URTWN_RIDX_OFDM24)); 3145 } 3146 3147 if (sc->chip & URTWN_CHIP_88E) 3148 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 3149 else 3150 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 3151 3152 /* XXX TODO: rate index/config (RAID) for 11n? */ 3153 txd->txdw1 |= htole32(SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT)); 3154 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 3155 3156 /* Choose a TX rate index. */ 3157 ridx = rate2ridx(params->ibp_rate0); 3158 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 3159 txd->txdw5 |= htole32(0x0001ff00); 3160 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3161 3162 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 3163 /* Use HW sequence numbering for non-QoS frames. */ 3164 if (sc->chip & URTWN_CHIP_88E) 3165 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 3166 else 3167 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 3168 } else { 3169 /* Set sequence number. */ 3170 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 3171 } 3172 3173 if (ieee80211_radiotap_active_vap(vap)) { 3174 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3175 3176 tap->wt_flags = 0; 3177 if (k != NULL) 3178 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3179 ieee80211_radiotap_tx(vap, m); 3180 } 3181 3182 data->ni = ni; 3183 3184 urtwn_tx_start(sc, m, type, data); 3185 3186 return (0); 3187 } 3188 3189 static void 3190 urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 3191 struct urtwn_data *data) 3192 { 3193 struct usb_xfer *xfer; 3194 struct r92c_tx_desc *txd; 3195 uint16_t ac, sum; 3196 int i, xferlen; 3197 3198 URTWN_ASSERT_LOCKED(sc); 3199 3200 ac = M_WME_GETAC(m); 3201 3202 switch (type) { 3203 case IEEE80211_FC0_TYPE_CTL: 3204 case IEEE80211_FC0_TYPE_MGT: 3205 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 3206 break; 3207 default: 3208 xfer = sc->sc_xfer[wme2queue[ac].qid]; 3209 break; 3210 } 3211 3212 txd = (struct r92c_tx_desc *)data->buf; 3213 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 3214 3215 /* Compute Tx descriptor checksum. */ 3216 sum = 0; 3217 for (i = 0; i < sizeof(*txd) / 2; i++) 3218 sum ^= ((uint16_t *)txd)[i]; 3219 txd->txdsum = sum; /* NB: already little endian. */ 3220 3221 xferlen = sizeof(*txd) + m->m_pkthdr.len; 3222 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 3223 3224 data->buflen = xferlen; 3225 data->m = m; 3226 3227 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 3228 usbd_transfer_start(xfer); 3229 } 3230 3231 static int 3232 urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 3233 { 3234 struct urtwn_softc *sc = ic->ic_softc; 3235 int error; 3236 3237 URTWN_LOCK(sc); 3238 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 3239 URTWN_UNLOCK(sc); 3240 return (ENXIO); 3241 } 3242 error = mbufq_enqueue(&sc->sc_snd, m); 3243 if (error) { 3244 URTWN_UNLOCK(sc); 3245 return (error); 3246 } 3247 urtwn_start(sc); 3248 URTWN_UNLOCK(sc); 3249 3250 return (0); 3251 } 3252 3253 static void 3254 urtwn_start(struct urtwn_softc *sc) 3255 { 3256 struct ieee80211_node *ni; 3257 struct mbuf *m; 3258 struct urtwn_data *bf; 3259 3260 URTWN_ASSERT_LOCKED(sc); 3261 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 3262 bf = urtwn_getbuf(sc); 3263 if (bf == NULL) { 3264 mbufq_prepend(&sc->sc_snd, m); 3265 break; 3266 } 3267 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3268 m->m_pkthdr.rcvif = NULL; 3269 3270 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n", 3271 __func__, 3272 m); 3273 3274 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 3275 if_inc_counter(ni->ni_vap->iv_ifp, 3276 IFCOUNTER_OERRORS, 1); 3277 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3278 m_freem(m); 3279 ieee80211_free_node(ni); 3280 break; 3281 } 3282 sc->sc_txtimer = 5; 3283 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3284 } 3285 } 3286 3287 static void 3288 urtwn_parent(struct ieee80211com *ic) 3289 { 3290 struct urtwn_softc *sc = ic->ic_softc; 3291 3292 URTWN_LOCK(sc); 3293 if (sc->sc_flags & URTWN_DETACHED) { 3294 URTWN_UNLOCK(sc); 3295 return; 3296 } 3297 URTWN_UNLOCK(sc); 3298 3299 if (ic->ic_nrunning > 0) { 3300 if (urtwn_init(sc) != 0) { 3301 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3302 if (vap != NULL) 3303 ieee80211_stop(vap); 3304 } else 3305 ieee80211_start_all(ic); 3306 } else 3307 urtwn_stop(sc); 3308 } 3309 3310 static __inline int 3311 urtwn_power_on(struct urtwn_softc *sc) 3312 { 3313 3314 return sc->sc_power_on(sc); 3315 } 3316 3317 static int 3318 urtwn_r92c_power_on(struct urtwn_softc *sc) 3319 { 3320 uint32_t reg; 3321 usb_error_t error; 3322 int ntries; 3323 3324 /* Wait for autoload done bit. */ 3325 for (ntries = 0; ntries < 1000; ntries++) { 3326 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3327 break; 3328 urtwn_ms_delay(sc); 3329 } 3330 if (ntries == 1000) { 3331 device_printf(sc->sc_dev, 3332 "timeout waiting for chip autoload\n"); 3333 return (ETIMEDOUT); 3334 } 3335 3336 /* Unlock ISO/CLK/Power control register. */ 3337 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3338 if (error != USB_ERR_NORMAL_COMPLETION) 3339 return (EIO); 3340 /* Move SPS into PWM mode. */ 3341 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3342 if (error != USB_ERR_NORMAL_COMPLETION) 3343 return (EIO); 3344 urtwn_ms_delay(sc); 3345 3346 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3347 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3348 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3349 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3350 if (error != USB_ERR_NORMAL_COMPLETION) 3351 return (EIO); 3352 urtwn_ms_delay(sc); 3353 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3354 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3355 ~R92C_SYS_ISO_CTRL_MD2PP); 3356 if (error != USB_ERR_NORMAL_COMPLETION) 3357 return (EIO); 3358 } 3359 3360 /* Auto enable WLAN. */ 3361 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3362 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3363 if (error != USB_ERR_NORMAL_COMPLETION) 3364 return (EIO); 3365 for (ntries = 0; ntries < 1000; ntries++) { 3366 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3367 R92C_APS_FSMCO_APFM_ONMAC)) 3368 break; 3369 urtwn_ms_delay(sc); 3370 } 3371 if (ntries == 1000) { 3372 device_printf(sc->sc_dev, 3373 "timeout waiting for MAC auto ON\n"); 3374 return (ETIMEDOUT); 3375 } 3376 3377 /* Enable radio, GPIO and LED functions. */ 3378 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3379 R92C_APS_FSMCO_AFSM_HSUS | 3380 R92C_APS_FSMCO_PDN_EN | 3381 R92C_APS_FSMCO_PFM_ALDN); 3382 if (error != USB_ERR_NORMAL_COMPLETION) 3383 return (EIO); 3384 /* Release RF digital isolation. */ 3385 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3386 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3387 if (error != USB_ERR_NORMAL_COMPLETION) 3388 return (EIO); 3389 3390 /* Initialize MAC. */ 3391 error = urtwn_write_1(sc, R92C_APSD_CTRL, 3392 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3393 if (error != USB_ERR_NORMAL_COMPLETION) 3394 return (EIO); 3395 for (ntries = 0; ntries < 200; ntries++) { 3396 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3397 R92C_APSD_CTRL_OFF_STATUS)) 3398 break; 3399 urtwn_ms_delay(sc); 3400 } 3401 if (ntries == 200) { 3402 device_printf(sc->sc_dev, 3403 "timeout waiting for MAC initialization\n"); 3404 return (ETIMEDOUT); 3405 } 3406 3407 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3408 reg = urtwn_read_2(sc, R92C_CR); 3409 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3410 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3411 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3412 R92C_CR_ENSEC; 3413 error = urtwn_write_2(sc, R92C_CR, reg); 3414 if (error != USB_ERR_NORMAL_COMPLETION) 3415 return (EIO); 3416 3417 error = urtwn_write_1(sc, 0xfe10, 0x19); 3418 if (error != USB_ERR_NORMAL_COMPLETION) 3419 return (EIO); 3420 return (0); 3421 } 3422 3423 static int 3424 urtwn_r88e_power_on(struct urtwn_softc *sc) 3425 { 3426 uint32_t reg; 3427 usb_error_t error; 3428 int ntries; 3429 3430 /* Wait for power ready bit. */ 3431 for (ntries = 0; ntries < 5000; ntries++) { 3432 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 3433 break; 3434 urtwn_ms_delay(sc); 3435 } 3436 if (ntries == 5000) { 3437 device_printf(sc->sc_dev, 3438 "timeout waiting for chip power up\n"); 3439 return (ETIMEDOUT); 3440 } 3441 3442 /* Reset BB. */ 3443 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3444 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3445 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3446 if (error != USB_ERR_NORMAL_COMPLETION) 3447 return (EIO); 3448 3449 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3450 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3451 if (error != USB_ERR_NORMAL_COMPLETION) 3452 return (EIO); 3453 3454 /* Disable HWPDN. */ 3455 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3456 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3457 if (error != USB_ERR_NORMAL_COMPLETION) 3458 return (EIO); 3459 3460 /* Disable WL suspend. */ 3461 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3462 urtwn_read_2(sc, R92C_APS_FSMCO) & 3463 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 3464 if (error != USB_ERR_NORMAL_COMPLETION) 3465 return (EIO); 3466 3467 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3468 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3469 if (error != USB_ERR_NORMAL_COMPLETION) 3470 return (EIO); 3471 for (ntries = 0; ntries < 5000; ntries++) { 3472 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3473 R92C_APS_FSMCO_APFM_ONMAC)) 3474 break; 3475 urtwn_ms_delay(sc); 3476 } 3477 if (ntries == 5000) 3478 return (ETIMEDOUT); 3479 3480 /* Enable LDO normal mode. */ 3481 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 3482 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~R92C_LPLDO_CTRL_SLEEP); 3483 if (error != USB_ERR_NORMAL_COMPLETION) 3484 return (EIO); 3485 3486 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3487 error = urtwn_write_2(sc, R92C_CR, 0); 3488 if (error != USB_ERR_NORMAL_COMPLETION) 3489 return (EIO); 3490 reg = urtwn_read_2(sc, R92C_CR); 3491 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3492 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3493 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3494 error = urtwn_write_2(sc, R92C_CR, reg); 3495 if (error != USB_ERR_NORMAL_COMPLETION) 3496 return (EIO); 3497 3498 return (0); 3499 } 3500 3501 static __inline void 3502 urtwn_power_off(struct urtwn_softc *sc) 3503 { 3504 3505 return sc->sc_power_off(sc); 3506 } 3507 3508 static void 3509 urtwn_r92c_power_off(struct urtwn_softc *sc) 3510 { 3511 uint32_t reg; 3512 3513 /* Block all Tx queues. */ 3514 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3515 3516 /* Disable RF */ 3517 urtwn_rf_write(sc, 0, 0, 0); 3518 3519 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 3520 3521 /* Reset BB state machine */ 3522 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3523 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA | 3524 R92C_SYS_FUNC_EN_BB_GLB_RST); 3525 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3526 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 3527 3528 /* 3529 * Reset digital sequence 3530 */ 3531 #ifndef URTWN_WITHOUT_UCODE 3532 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 3533 /* Reset MCU ready status */ 3534 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3535 3536 /* If firmware in ram code, do reset */ 3537 urtwn_fw_reset(sc); 3538 } 3539 #endif 3540 3541 /* Reset MAC and Enable 8051 */ 3542 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 3543 (R92C_SYS_FUNC_EN_CPUEN | 3544 R92C_SYS_FUNC_EN_ELDR | 3545 R92C_SYS_FUNC_EN_HWPDN) >> 8); 3546 3547 /* Reset MCU ready status */ 3548 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3549 3550 /* Disable MAC clock */ 3551 urtwn_write_2(sc, R92C_SYS_CLKR, 3552 R92C_SYS_CLKR_ANAD16V_EN | 3553 R92C_SYS_CLKR_ANA8M | 3554 R92C_SYS_CLKR_LOADER_EN | 3555 R92C_SYS_CLKR_80M_SSC_DIS | 3556 R92C_SYS_CLKR_SYS_EN | 3557 R92C_SYS_CLKR_RING_EN | 3558 0x4000); 3559 3560 /* Disable AFE PLL */ 3561 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 3562 3563 /* Gated AFE DIG_CLOCK */ 3564 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 3565 3566 /* Isolated digital to PON */ 3567 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3568 R92C_SYS_ISO_CTRL_MD2PP | 3569 R92C_SYS_ISO_CTRL_PA2PCIE | 3570 R92C_SYS_ISO_CTRL_PD2CORE | 3571 R92C_SYS_ISO_CTRL_IP2MAC | 3572 R92C_SYS_ISO_CTRL_DIOP | 3573 R92C_SYS_ISO_CTRL_DIOE); 3574 3575 /* 3576 * Pull GPIO PIN to balance level and LED control 3577 */ 3578 /* 1. Disable GPIO[7:0] */ 3579 urtwn_write_2(sc, R92C_GPIO_IOSEL, 0x0000); 3580 3581 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 3582 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 3583 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 3584 3585 /* Disable GPIO[10:8] */ 3586 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x00); 3587 3588 reg = urtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0; 3589 reg |= (((reg & 0x000f) << 4) | 0x0780); 3590 urtwn_write_2(sc, R92C_GPIO_IO_SEL, reg); 3591 3592 /* Disable LED0 & 1 */ 3593 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 3594 3595 /* 3596 * Reset digital sequence 3597 */ 3598 /* Disable ELDR clock */ 3599 urtwn_write_2(sc, R92C_SYS_CLKR, 3600 R92C_SYS_CLKR_ANAD16V_EN | 3601 R92C_SYS_CLKR_ANA8M | 3602 R92C_SYS_CLKR_LOADER_EN | 3603 R92C_SYS_CLKR_80M_SSC_DIS | 3604 R92C_SYS_CLKR_SYS_EN | 3605 R92C_SYS_CLKR_RING_EN | 3606 0x4000); 3607 3608 /* Isolated ELDR to PON */ 3609 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 3610 (R92C_SYS_ISO_CTRL_DIOR | 3611 R92C_SYS_ISO_CTRL_PWC_EV12V) >> 8); 3612 3613 /* 3614 * Disable analog sequence 3615 */ 3616 /* Disable A15 power */ 3617 urtwn_write_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_OBUF); 3618 /* Disable digital core power */ 3619 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3620 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 3621 ~R92C_LDOV12D_CTRL_LDV12_EN); 3622 3623 /* Enter PFM mode */ 3624 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 3625 3626 /* Set USB suspend */ 3627 urtwn_write_2(sc, R92C_APS_FSMCO, 3628 R92C_APS_FSMCO_APDM_HOST | 3629 R92C_APS_FSMCO_AFSM_HSUS | 3630 R92C_APS_FSMCO_PFM_ALDN); 3631 3632 /* Lock ISO/CLK/Power control register. */ 3633 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 3634 } 3635 3636 static void 3637 urtwn_r88e_power_off(struct urtwn_softc *sc) 3638 { 3639 uint8_t reg; 3640 int ntries; 3641 3642 /* Disable any kind of TX reports. */ 3643 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 3644 urtwn_read_1(sc, R88E_TX_RPT_CTRL) & 3645 ~(R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA)); 3646 3647 /* Stop Rx. */ 3648 urtwn_write_1(sc, R92C_CR, 0); 3649 3650 /* Move card to Low Power State. */ 3651 /* Block all Tx queues. */ 3652 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3653 3654 for (ntries = 0; ntries < 20; ntries++) { 3655 /* Should be zero if no packet is transmitting. */ 3656 if (urtwn_read_4(sc, R88E_SCH_TXCMD) == 0) 3657 break; 3658 3659 urtwn_ms_delay(sc); 3660 } 3661 if (ntries == 20) { 3662 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", 3663 __func__); 3664 return; 3665 } 3666 3667 /* CCK and OFDM are disabled, and clock are gated. */ 3668 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3669 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_BBRSTB); 3670 3671 urtwn_ms_delay(sc); 3672 3673 /* Reset MAC TRX */ 3674 urtwn_write_1(sc, R92C_CR, 3675 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3676 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | 3677 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN); 3678 3679 /* check if removed later */ 3680 urtwn_write_1(sc, R92C_CR + 1, 3681 urtwn_read_1(sc, R92C_CR + 1) & ~(R92C_CR_ENSEC >> 8)); 3682 3683 /* Respond TxOK to scheduler */ 3684 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 3685 urtwn_read_1(sc, R92C_DUAL_TSF_RST) | 0x20); 3686 3687 /* If firmware in ram code, do reset. */ 3688 #ifndef URTWN_WITHOUT_UCODE 3689 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) 3690 urtwn_r88e_fw_reset(sc); 3691 #endif 3692 3693 /* Reset MCU ready status. */ 3694 urtwn_write_1(sc, R92C_MCUFWDL, 0x00); 3695 3696 /* Disable 32k. */ 3697 urtwn_write_1(sc, R88E_32K_CTRL, 3698 urtwn_read_1(sc, R88E_32K_CTRL) & ~0x01); 3699 3700 /* Move card to Disabled state. */ 3701 /* Turn off RF. */ 3702 urtwn_write_1(sc, R92C_RF_CTRL, 0); 3703 3704 /* LDO Sleep mode. */ 3705 urtwn_write_1(sc, R92C_LPLDO_CTRL, 3706 urtwn_read_1(sc, R92C_LPLDO_CTRL) | R92C_LPLDO_CTRL_SLEEP); 3707 3708 /* Turn off MAC by HW state machine */ 3709 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3710 urtwn_read_1(sc, R92C_APS_FSMCO + 1) | 3711 (R92C_APS_FSMCO_APFM_OFF >> 8)); 3712 3713 for (ntries = 0; ntries < 20; ntries++) { 3714 /* Wait until it will be disabled. */ 3715 if ((urtwn_read_1(sc, R92C_APS_FSMCO + 1) & 3716 (R92C_APS_FSMCO_APFM_OFF >> 8)) == 0) 3717 break; 3718 3719 urtwn_ms_delay(sc); 3720 } 3721 if (ntries == 20) { 3722 device_printf(sc->sc_dev, "%s: could not turn off MAC\n", 3723 __func__); 3724 return; 3725 } 3726 3727 /* schmit trigger */ 3728 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3729 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3730 3731 /* Enable WL suspend. */ 3732 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3733 (urtwn_read_1(sc, R92C_APS_FSMCO + 1) & ~0x10) | 0x08); 3734 3735 /* Enable bandgap mbias in suspend. */ 3736 urtwn_write_1(sc, R92C_APS_FSMCO + 3, 0); 3737 3738 /* Clear SIC_EN register. */ 3739 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 1, 3740 urtwn_read_1(sc, R92C_GPIO_MUXCFG + 1) & ~0x10); 3741 3742 /* Set USB suspend enable local register */ 3743 urtwn_write_1(sc, R92C_USB_SUSPEND, 3744 urtwn_read_1(sc, R92C_USB_SUSPEND) | 0x10); 3745 3746 /* Reset MCU IO Wrapper. */ 3747 reg = urtwn_read_1(sc, R92C_RSV_CTRL + 1); 3748 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08); 3749 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08); 3750 3751 /* marked as 'For Power Consumption' code. */ 3752 urtwn_write_1(sc, R92C_GPIO_OUT, urtwn_read_1(sc, R92C_GPIO_IN)); 3753 urtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff); 3754 3755 urtwn_write_1(sc, R92C_GPIO_IO_SEL, 3756 urtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4); 3757 urtwn_write_1(sc, R92C_GPIO_MOD, 3758 urtwn_read_1(sc, R92C_GPIO_MOD) | 0x0f); 3759 3760 /* Set LNA, TRSW, EX_PA Pin to output mode. */ 3761 urtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808); 3762 } 3763 3764 static int 3765 urtwn_llt_init(struct urtwn_softc *sc) 3766 { 3767 int i, error, page_count, pktbuf_count; 3768 3769 page_count = (sc->chip & URTWN_CHIP_88E) ? 3770 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 3771 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 3772 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 3773 3774 /* Reserve pages [0; page_count]. */ 3775 for (i = 0; i < page_count; i++) { 3776 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3777 return (error); 3778 } 3779 /* NB: 0xff indicates end-of-list. */ 3780 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3781 return (error); 3782 /* 3783 * Use pages [page_count + 1; pktbuf_count - 1] 3784 * as ring buffer. 3785 */ 3786 for (++i; i < pktbuf_count - 1; i++) { 3787 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3788 return (error); 3789 } 3790 /* Make the last page point to the beginning of the ring buffer. */ 3791 error = urtwn_llt_write(sc, i, page_count + 1); 3792 return (error); 3793 } 3794 3795 #ifndef URTWN_WITHOUT_UCODE 3796 static void 3797 urtwn_fw_reset(struct urtwn_softc *sc) 3798 { 3799 uint16_t reg; 3800 int ntries; 3801 3802 /* Tell 8051 to reset itself. */ 3803 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3804 3805 /* Wait until 8051 resets by itself. */ 3806 for (ntries = 0; ntries < 100; ntries++) { 3807 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3808 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3809 return; 3810 urtwn_ms_delay(sc); 3811 } 3812 /* Force 8051 reset. */ 3813 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3814 } 3815 3816 static void 3817 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3818 { 3819 uint16_t reg; 3820 3821 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3822 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3823 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3824 } 3825 3826 static int 3827 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 3828 { 3829 uint32_t reg; 3830 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 3831 int off, mlen; 3832 3833 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3834 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3835 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3836 3837 off = R92C_FW_START_ADDR; 3838 while (len > 0) { 3839 if (len > 196) 3840 mlen = 196; 3841 else if (len > 4) 3842 mlen = 4; 3843 else 3844 mlen = 1; 3845 /* XXX fix this deconst */ 3846 error = urtwn_write_region_1(sc, off, 3847 __DECONST(uint8_t *, buf), mlen); 3848 if (error != USB_ERR_NORMAL_COMPLETION) 3849 break; 3850 off += mlen; 3851 buf += mlen; 3852 len -= mlen; 3853 } 3854 return (error); 3855 } 3856 3857 static int 3858 urtwn_load_firmware(struct urtwn_softc *sc) 3859 { 3860 const struct firmware *fw; 3861 const struct r92c_fw_hdr *hdr; 3862 const char *imagename; 3863 const u_char *ptr; 3864 size_t len; 3865 uint32_t reg; 3866 int mlen, ntries, page, error; 3867 3868 URTWN_UNLOCK(sc); 3869 /* Read firmware image from the filesystem. */ 3870 if (sc->chip & URTWN_CHIP_88E) 3871 imagename = "urtwn-rtl8188eufw"; 3872 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3873 URTWN_CHIP_UMC_A_CUT) 3874 imagename = "urtwn-rtl8192cfwU"; 3875 else 3876 imagename = "urtwn-rtl8192cfwT"; 3877 3878 fw = firmware_get(imagename); 3879 URTWN_LOCK(sc); 3880 if (fw == NULL) { 3881 device_printf(sc->sc_dev, 3882 "failed loadfirmware of file %s\n", imagename); 3883 return (ENOENT); 3884 } 3885 3886 len = fw->datasize; 3887 3888 if (len < sizeof(*hdr)) { 3889 device_printf(sc->sc_dev, "firmware too short\n"); 3890 error = EINVAL; 3891 goto fail; 3892 } 3893 ptr = fw->data; 3894 hdr = (const struct r92c_fw_hdr *)ptr; 3895 /* Check if there is a valid FW header and skip it. */ 3896 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3897 (le16toh(hdr->signature) >> 4) == 0x88e || 3898 (le16toh(hdr->signature) >> 4) == 0x92c) { 3899 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, 3900 "FW V%d.%d %02d-%02d %02d:%02d\n", 3901 le16toh(hdr->version), le16toh(hdr->subversion), 3902 hdr->month, hdr->date, hdr->hour, hdr->minute); 3903 ptr += sizeof(*hdr); 3904 len -= sizeof(*hdr); 3905 } 3906 3907 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3908 if (sc->chip & URTWN_CHIP_88E) 3909 urtwn_r88e_fw_reset(sc); 3910 else 3911 urtwn_fw_reset(sc); 3912 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3913 } 3914 3915 if (!(sc->chip & URTWN_CHIP_88E)) { 3916 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3917 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3918 R92C_SYS_FUNC_EN_CPUEN); 3919 } 3920 urtwn_write_1(sc, R92C_MCUFWDL, 3921 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3922 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3923 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3924 3925 /* Reset the FWDL checksum. */ 3926 urtwn_write_1(sc, R92C_MCUFWDL, 3927 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3928 3929 for (page = 0; len > 0; page++) { 3930 mlen = min(len, R92C_FW_PAGE_SIZE); 3931 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3932 if (error != 0) { 3933 device_printf(sc->sc_dev, 3934 "could not load firmware page\n"); 3935 goto fail; 3936 } 3937 ptr += mlen; 3938 len -= mlen; 3939 } 3940 urtwn_write_1(sc, R92C_MCUFWDL, 3941 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3942 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3943 3944 /* Wait for checksum report. */ 3945 for (ntries = 0; ntries < 1000; ntries++) { 3946 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3947 break; 3948 urtwn_ms_delay(sc); 3949 } 3950 if (ntries == 1000) { 3951 device_printf(sc->sc_dev, 3952 "timeout waiting for checksum report\n"); 3953 error = ETIMEDOUT; 3954 goto fail; 3955 } 3956 3957 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3958 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3959 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3960 if (sc->chip & URTWN_CHIP_88E) 3961 urtwn_r88e_fw_reset(sc); 3962 /* Wait for firmware readiness. */ 3963 for (ntries = 0; ntries < 1000; ntries++) { 3964 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3965 break; 3966 urtwn_ms_delay(sc); 3967 } 3968 if (ntries == 1000) { 3969 device_printf(sc->sc_dev, 3970 "timeout waiting for firmware readiness\n"); 3971 error = ETIMEDOUT; 3972 goto fail; 3973 } 3974 fail: 3975 firmware_put(fw, FIRMWARE_UNLOAD); 3976 return (error); 3977 } 3978 #endif 3979 3980 static int 3981 urtwn_dma_init(struct urtwn_softc *sc) 3982 { 3983 struct usb_endpoint *ep, *ep_end; 3984 usb_error_t usb_err; 3985 uint32_t reg; 3986 int hashq, hasnq, haslq, nqueues, ntx; 3987 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 3988 3989 /* Initialize LLT table. */ 3990 error = urtwn_llt_init(sc); 3991 if (error != 0) 3992 return (error); 3993 3994 /* Determine the number of bulk-out pipes. */ 3995 ntx = 0; 3996 ep = sc->sc_udev->endpoints; 3997 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 3998 for (; ep != ep_end; ep++) { 3999 if ((ep->edesc == NULL) || 4000 (ep->iface_index != sc->sc_iface_index)) 4001 continue; 4002 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 4003 ntx++; 4004 } 4005 if (ntx == 0) { 4006 device_printf(sc->sc_dev, 4007 "%d: invalid number of Tx bulk pipes\n", ntx); 4008 return (EIO); 4009 } 4010 4011 /* Get Tx queues to USB endpoints mapping. */ 4012 hashq = hasnq = haslq = nqueues = 0; 4013 switch (ntx) { 4014 case 1: hashq = 1; break; 4015 case 2: hashq = hasnq = 1; break; 4016 case 3: case 4: hashq = hasnq = haslq = 1; break; 4017 } 4018 nqueues = hashq + hasnq + haslq; 4019 if (nqueues == 0) 4020 return (EIO); 4021 4022 npubqpages = nqpages = nrempages = pagecount = 0; 4023 if (sc->chip & URTWN_CHIP_88E) 4024 tx_boundary = R88E_TX_PAGE_BOUNDARY; 4025 else { 4026 pagecount = R92C_TX_PAGE_COUNT; 4027 npubqpages = R92C_PUBQ_NPAGES; 4028 tx_boundary = R92C_TX_PAGE_BOUNDARY; 4029 } 4030 4031 /* Set number of pages for normal priority queue. */ 4032 if (sc->chip & URTWN_CHIP_88E) { 4033 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 4034 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4035 return (EIO); 4036 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 4037 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4038 return (EIO); 4039 } else { 4040 /* Get the number of pages for each queue. */ 4041 nqpages = (pagecount - npubqpages) / nqueues; 4042 /* 4043 * The remaining pages are assigned to the high priority 4044 * queue. 4045 */ 4046 nrempages = (pagecount - npubqpages) % nqueues; 4047 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 4048 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4049 return (EIO); 4050 usb_err = urtwn_write_4(sc, R92C_RQPN, 4051 /* Set number of pages for public queue. */ 4052 SM(R92C_RQPN_PUBQ, npubqpages) | 4053 /* Set number of pages for high priority queue. */ 4054 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 4055 /* Set number of pages for low priority queue. */ 4056 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 4057 /* Load values. */ 4058 R92C_RQPN_LD); 4059 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4060 return (EIO); 4061 } 4062 4063 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 4064 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4065 return (EIO); 4066 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 4067 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4068 return (EIO); 4069 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 4070 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4071 return (EIO); 4072 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 4073 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4074 return (EIO); 4075 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 4076 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4077 return (EIO); 4078 4079 /* Set queue to USB pipe mapping. */ 4080 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4081 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4082 if (nqueues == 1) { 4083 if (hashq) 4084 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 4085 else if (hasnq) 4086 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 4087 else 4088 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4089 } else if (nqueues == 2) { 4090 /* 4091 * All 2-endpoints configs have high and normal 4092 * priority queues. 4093 */ 4094 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4095 } else 4096 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4097 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4098 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4099 return (EIO); 4100 4101 /* Set Tx/Rx transfer page boundary. */ 4102 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 4103 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 4104 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4105 return (EIO); 4106 4107 /* Set Tx/Rx transfer page size. */ 4108 usb_err = urtwn_write_1(sc, R92C_PBP, 4109 SM(R92C_PBP_PSRX, R92C_PBP_128) | 4110 SM(R92C_PBP_PSTX, R92C_PBP_128)); 4111 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4112 return (EIO); 4113 4114 return (0); 4115 } 4116 4117 static int 4118 urtwn_mac_init(struct urtwn_softc *sc) 4119 { 4120 usb_error_t error; 4121 int i; 4122 4123 /* Write MAC initialization values. */ 4124 if (sc->chip & URTWN_CHIP_88E) { 4125 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 4126 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 4127 rtl8188eu_mac[i].val); 4128 if (error != USB_ERR_NORMAL_COMPLETION) 4129 return (EIO); 4130 } 4131 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 4132 } else { 4133 for (i = 0; i < nitems(rtl8192cu_mac); i++) { 4134 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 4135 rtl8192cu_mac[i].val); 4136 if (error != USB_ERR_NORMAL_COMPLETION) 4137 return (EIO); 4138 } 4139 } 4140 4141 return (0); 4142 } 4143 4144 static void 4145 urtwn_bb_init(struct urtwn_softc *sc) 4146 { 4147 const struct urtwn_bb_prog *prog; 4148 uint32_t reg; 4149 uint8_t crystalcap; 4150 int i; 4151 4152 /* Enable BB and RF. */ 4153 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4154 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4155 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 4156 R92C_SYS_FUNC_EN_DIO_RF); 4157 4158 if (!(sc->chip & URTWN_CHIP_88E)) 4159 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 4160 4161 urtwn_write_1(sc, R92C_RF_CTRL, 4162 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 4163 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4164 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 4165 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 4166 4167 if (!(sc->chip & URTWN_CHIP_88E)) { 4168 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 4169 urtwn_write_1(sc, 0x15, 0xe9); 4170 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 4171 } 4172 4173 /* Select BB programming based on board type. */ 4174 if (sc->chip & URTWN_CHIP_88E) 4175 prog = &rtl8188eu_bb_prog; 4176 else if (!(sc->chip & URTWN_CHIP_92C)) { 4177 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4178 prog = &rtl8188ce_bb_prog; 4179 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4180 prog = &rtl8188ru_bb_prog; 4181 else 4182 prog = &rtl8188cu_bb_prog; 4183 } else { 4184 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4185 prog = &rtl8192ce_bb_prog; 4186 else 4187 prog = &rtl8192cu_bb_prog; 4188 } 4189 /* Write BB initialization values. */ 4190 for (i = 0; i < prog->count; i++) { 4191 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 4192 urtwn_ms_delay(sc); 4193 } 4194 4195 if (sc->chip & URTWN_CHIP_92C_1T2R) { 4196 /* 8192C 1T only configuration. */ 4197 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 4198 reg = (reg & ~0x00000003) | 0x2; 4199 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 4200 4201 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 4202 reg = (reg & ~0x00300033) | 0x00200022; 4203 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 4204 4205 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 4206 reg = (reg & ~0xff000000) | 0x45 << 24; 4207 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 4208 4209 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4210 reg = (reg & ~0x000000ff) | 0x23; 4211 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 4212 4213 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 4214 reg = (reg & ~0x00000030) | 1 << 4; 4215 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 4216 4217 reg = urtwn_bb_read(sc, 0xe74); 4218 reg = (reg & ~0x0c000000) | 2 << 26; 4219 urtwn_bb_write(sc, 0xe74, reg); 4220 reg = urtwn_bb_read(sc, 0xe78); 4221 reg = (reg & ~0x0c000000) | 2 << 26; 4222 urtwn_bb_write(sc, 0xe78, reg); 4223 reg = urtwn_bb_read(sc, 0xe7c); 4224 reg = (reg & ~0x0c000000) | 2 << 26; 4225 urtwn_bb_write(sc, 0xe7c, reg); 4226 reg = urtwn_bb_read(sc, 0xe80); 4227 reg = (reg & ~0x0c000000) | 2 << 26; 4228 urtwn_bb_write(sc, 0xe80, reg); 4229 reg = urtwn_bb_read(sc, 0xe88); 4230 reg = (reg & ~0x0c000000) | 2 << 26; 4231 urtwn_bb_write(sc, 0xe88, reg); 4232 } 4233 4234 /* Write AGC values. */ 4235 for (i = 0; i < prog->agccount; i++) { 4236 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 4237 prog->agcvals[i]); 4238 urtwn_ms_delay(sc); 4239 } 4240 4241 if (sc->chip & URTWN_CHIP_88E) { 4242 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 4243 urtwn_ms_delay(sc); 4244 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 4245 urtwn_ms_delay(sc); 4246 4247 crystalcap = sc->rom.r88e_rom.crystalcap; 4248 if (crystalcap == 0xff) 4249 crystalcap = 0x20; 4250 crystalcap &= 0x3f; 4251 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 4252 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 4253 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4254 crystalcap | crystalcap << 6)); 4255 } else { 4256 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 4257 R92C_HSSI_PARAM2_CCK_HIPWR) 4258 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 4259 } 4260 } 4261 4262 static void 4263 urtwn_rf_init(struct urtwn_softc *sc) 4264 { 4265 const struct urtwn_rf_prog *prog; 4266 uint32_t reg, type; 4267 int i, j, idx, off; 4268 4269 /* Select RF programming based on board type. */ 4270 if (sc->chip & URTWN_CHIP_88E) 4271 prog = rtl8188eu_rf_prog; 4272 else if (!(sc->chip & URTWN_CHIP_92C)) { 4273 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4274 prog = rtl8188ce_rf_prog; 4275 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4276 prog = rtl8188ru_rf_prog; 4277 else 4278 prog = rtl8188cu_rf_prog; 4279 } else 4280 prog = rtl8192ce_rf_prog; 4281 4282 for (i = 0; i < sc->nrxchains; i++) { 4283 /* Save RF_ENV control type. */ 4284 idx = i / 2; 4285 off = (i % 2) * 16; 4286 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4287 type = (reg >> off) & 0x10; 4288 4289 /* Set RF_ENV enable. */ 4290 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4291 reg |= 0x100000; 4292 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4293 urtwn_ms_delay(sc); 4294 /* Set RF_ENV output high. */ 4295 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4296 reg |= 0x10; 4297 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4298 urtwn_ms_delay(sc); 4299 /* Set address and data lengths of RF registers. */ 4300 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4301 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4302 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4303 urtwn_ms_delay(sc); 4304 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4305 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4306 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4307 urtwn_ms_delay(sc); 4308 4309 /* Write RF initialization values for this chain. */ 4310 for (j = 0; j < prog[i].count; j++) { 4311 if (prog[i].regs[j] >= 0xf9 && 4312 prog[i].regs[j] <= 0xfe) { 4313 /* 4314 * These are fake RF registers offsets that 4315 * indicate a delay is required. 4316 */ 4317 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 4318 continue; 4319 } 4320 urtwn_rf_write(sc, i, prog[i].regs[j], 4321 prog[i].vals[j]); 4322 urtwn_ms_delay(sc); 4323 } 4324 4325 /* Restore RF_ENV control type. */ 4326 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4327 reg &= ~(0x10 << off) | (type << off); 4328 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 4329 4330 /* Cache RF register CHNLBW. */ 4331 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4332 } 4333 4334 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4335 URTWN_CHIP_UMC_A_CUT) { 4336 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4337 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4338 } 4339 } 4340 4341 static void 4342 urtwn_cam_init(struct urtwn_softc *sc) 4343 { 4344 /* Invalidate all CAM entries. */ 4345 urtwn_write_4(sc, R92C_CAMCMD, 4346 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4347 } 4348 4349 static int 4350 urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 4351 { 4352 usb_error_t error; 4353 4354 error = urtwn_write_4(sc, R92C_CAMWRITE, data); 4355 if (error != USB_ERR_NORMAL_COMPLETION) 4356 return (EIO); 4357 error = urtwn_write_4(sc, R92C_CAMCMD, 4358 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 4359 SM(R92C_CAMCMD_ADDR, addr)); 4360 if (error != USB_ERR_NORMAL_COMPLETION) 4361 return (EIO); 4362 4363 return (0); 4364 } 4365 4366 static void 4367 urtwn_pa_bias_init(struct urtwn_softc *sc) 4368 { 4369 uint8_t reg; 4370 int i; 4371 4372 for (i = 0; i < sc->nrxchains; i++) { 4373 if (sc->pa_setting & (1 << i)) 4374 continue; 4375 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4376 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4377 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4378 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4379 } 4380 if (!(sc->pa_setting & 0x10)) { 4381 reg = urtwn_read_1(sc, 0x16); 4382 reg = (reg & ~0xf0) | 0x90; 4383 urtwn_write_1(sc, 0x16, reg); 4384 } 4385 } 4386 4387 static void 4388 urtwn_rxfilter_init(struct urtwn_softc *sc) 4389 { 4390 struct ieee80211com *ic = &sc->sc_ic; 4391 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4392 uint32_t rcr; 4393 uint16_t filter; 4394 4395 URTWN_ASSERT_LOCKED(sc); 4396 4397 /* Setup multicast filter. */ 4398 urtwn_set_multi(sc); 4399 4400 /* Filter for management frames. */ 4401 filter = 0x7f3f; 4402 switch (vap->iv_opmode) { 4403 case IEEE80211_M_STA: 4404 filter &= ~( 4405 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 4406 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 4407 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 4408 break; 4409 case IEEE80211_M_HOSTAP: 4410 filter &= ~( 4411 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 4412 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP)); 4413 break; 4414 case IEEE80211_M_MONITOR: 4415 case IEEE80211_M_IBSS: 4416 break; 4417 default: 4418 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4419 __func__, vap->iv_opmode); 4420 break; 4421 } 4422 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 4423 4424 /* Reject all control frames. */ 4425 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4426 4427 /* Reject all data frames. */ 4428 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 4429 4430 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 4431 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 4432 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 4433 4434 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 4435 /* Accept all frames. */ 4436 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 4437 R92C_RCR_AAP; 4438 } 4439 4440 /* Set Rx filter. */ 4441 urtwn_write_4(sc, R92C_RCR, rcr); 4442 4443 if (ic->ic_promisc != 0) { 4444 /* Update Rx filter. */ 4445 urtwn_set_promisc(sc); 4446 } 4447 } 4448 4449 static void 4450 urtwn_edca_init(struct urtwn_softc *sc) 4451 { 4452 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4453 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4454 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4455 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4456 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4457 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4458 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4459 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4460 } 4461 4462 static void 4463 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4464 uint16_t power[URTWN_RIDX_COUNT]) 4465 { 4466 uint32_t reg; 4467 4468 /* Write per-CCK rate Tx power. */ 4469 if (chain == 0) { 4470 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4471 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4472 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4473 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4474 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4475 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4476 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4477 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4478 } else { 4479 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4480 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4481 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4482 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4483 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4484 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4485 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4486 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4487 } 4488 /* Write per-OFDM rate Tx power. */ 4489 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4490 SM(R92C_TXAGC_RATE06, power[ 4]) | 4491 SM(R92C_TXAGC_RATE09, power[ 5]) | 4492 SM(R92C_TXAGC_RATE12, power[ 6]) | 4493 SM(R92C_TXAGC_RATE18, power[ 7])); 4494 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4495 SM(R92C_TXAGC_RATE24, power[ 8]) | 4496 SM(R92C_TXAGC_RATE36, power[ 9]) | 4497 SM(R92C_TXAGC_RATE48, power[10]) | 4498 SM(R92C_TXAGC_RATE54, power[11])); 4499 /* Write per-MCS Tx power. */ 4500 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4501 SM(R92C_TXAGC_MCS00, power[12]) | 4502 SM(R92C_TXAGC_MCS01, power[13]) | 4503 SM(R92C_TXAGC_MCS02, power[14]) | 4504 SM(R92C_TXAGC_MCS03, power[15])); 4505 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4506 SM(R92C_TXAGC_MCS04, power[16]) | 4507 SM(R92C_TXAGC_MCS05, power[17]) | 4508 SM(R92C_TXAGC_MCS06, power[18]) | 4509 SM(R92C_TXAGC_MCS07, power[19])); 4510 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4511 SM(R92C_TXAGC_MCS08, power[20]) | 4512 SM(R92C_TXAGC_MCS09, power[21]) | 4513 SM(R92C_TXAGC_MCS10, power[22]) | 4514 SM(R92C_TXAGC_MCS11, power[23])); 4515 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4516 SM(R92C_TXAGC_MCS12, power[24]) | 4517 SM(R92C_TXAGC_MCS13, power[25]) | 4518 SM(R92C_TXAGC_MCS14, power[26]) | 4519 SM(R92C_TXAGC_MCS15, power[27])); 4520 } 4521 4522 static void 4523 urtwn_get_txpower(struct urtwn_softc *sc, int chain, 4524 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4525 uint16_t power[URTWN_RIDX_COUNT]) 4526 { 4527 struct ieee80211com *ic = &sc->sc_ic; 4528 struct r92c_rom *rom = &sc->rom.r92c_rom; 4529 uint16_t cckpow, ofdmpow, htpow, diff, max; 4530 const struct urtwn_txpwr *base; 4531 int ridx, chan, group; 4532 4533 /* Determine channel group. */ 4534 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4535 if (chan <= 3) 4536 group = 0; 4537 else if (chan <= 9) 4538 group = 1; 4539 else 4540 group = 2; 4541 4542 /* Get original Tx power based on board type and RF chain. */ 4543 if (!(sc->chip & URTWN_CHIP_92C)) { 4544 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4545 base = &rtl8188ru_txagc[chain]; 4546 else 4547 base = &rtl8192cu_txagc[chain]; 4548 } else 4549 base = &rtl8192cu_txagc[chain]; 4550 4551 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4552 if (sc->regulatory == 0) { 4553 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4554 power[ridx] = base->pwr[0][ridx]; 4555 } 4556 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4557 if (sc->regulatory == 3) { 4558 power[ridx] = base->pwr[0][ridx]; 4559 /* Apply vendor limits. */ 4560 if (extc != NULL) 4561 max = rom->ht40_max_pwr[group]; 4562 else 4563 max = rom->ht20_max_pwr[group]; 4564 max = (max >> (chain * 4)) & 0xf; 4565 if (power[ridx] > max) 4566 power[ridx] = max; 4567 } else if (sc->regulatory == 1) { 4568 if (extc == NULL) 4569 power[ridx] = base->pwr[group][ridx]; 4570 } else if (sc->regulatory != 2) 4571 power[ridx] = base->pwr[0][ridx]; 4572 } 4573 4574 /* Compute per-CCK rate Tx power. */ 4575 cckpow = rom->cck_tx_pwr[chain][group]; 4576 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4577 power[ridx] += cckpow; 4578 if (power[ridx] > R92C_MAX_TX_PWR) 4579 power[ridx] = R92C_MAX_TX_PWR; 4580 } 4581 4582 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4583 if (sc->ntxchains > 1) { 4584 /* Apply reduction for 2 spatial streams. */ 4585 diff = rom->ht40_2s_tx_pwr_diff[group]; 4586 diff = (diff >> (chain * 4)) & 0xf; 4587 htpow = (htpow > diff) ? htpow - diff : 0; 4588 } 4589 4590 /* Compute per-OFDM rate Tx power. */ 4591 diff = rom->ofdm_tx_pwr_diff[group]; 4592 diff = (diff >> (chain * 4)) & 0xf; 4593 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4594 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4595 power[ridx] += ofdmpow; 4596 if (power[ridx] > R92C_MAX_TX_PWR) 4597 power[ridx] = R92C_MAX_TX_PWR; 4598 } 4599 4600 /* Compute per-MCS Tx power. */ 4601 if (extc == NULL) { 4602 diff = rom->ht20_tx_pwr_diff[group]; 4603 diff = (diff >> (chain * 4)) & 0xf; 4604 htpow += diff; /* HT40->HT20 correction. */ 4605 } 4606 for (ridx = 12; ridx <= 27; ridx++) { 4607 power[ridx] += htpow; 4608 if (power[ridx] > R92C_MAX_TX_PWR) 4609 power[ridx] = R92C_MAX_TX_PWR; 4610 } 4611 #ifdef USB_DEBUG 4612 if (sc->sc_debug & URTWN_DEBUG_TXPWR) { 4613 /* Dump per-rate Tx power values. */ 4614 kprintf("Tx power for chain %d:\n", chain); 4615 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 4616 kprintf("Rate %d = %u\n", ridx, power[ridx]); 4617 } 4618 #endif 4619 } 4620 4621 static void 4622 urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 4623 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4624 uint16_t power[URTWN_RIDX_COUNT]) 4625 { 4626 struct ieee80211com *ic = &sc->sc_ic; 4627 struct r88e_rom *rom = &sc->rom.r88e_rom; 4628 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4629 const struct urtwn_r88e_txpwr *base; 4630 int ridx, chan, group; 4631 4632 /* Determine channel group. */ 4633 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4634 if (chan <= 2) 4635 group = 0; 4636 else if (chan <= 5) 4637 group = 1; 4638 else if (chan <= 8) 4639 group = 2; 4640 else if (chan <= 11) 4641 group = 3; 4642 else if (chan <= 13) 4643 group = 4; 4644 else 4645 group = 5; 4646 4647 /* Get original Tx power based on board type and RF chain. */ 4648 base = &rtl8188eu_txagc[chain]; 4649 4650 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4651 if (sc->regulatory == 0) { 4652 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4653 power[ridx] = base->pwr[0][ridx]; 4654 } 4655 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4656 if (sc->regulatory == 3) 4657 power[ridx] = base->pwr[0][ridx]; 4658 else if (sc->regulatory == 1) { 4659 if (extc == NULL) 4660 power[ridx] = base->pwr[group][ridx]; 4661 } else if (sc->regulatory != 2) 4662 power[ridx] = base->pwr[0][ridx]; 4663 } 4664 4665 /* Compute per-CCK rate Tx power. */ 4666 cckpow = rom->cck_tx_pwr[group]; 4667 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4668 power[ridx] += cckpow; 4669 if (power[ridx] > R92C_MAX_TX_PWR) 4670 power[ridx] = R92C_MAX_TX_PWR; 4671 } 4672 4673 htpow = rom->ht40_tx_pwr[group]; 4674 4675 /* Compute per-OFDM rate Tx power. */ 4676 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4677 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4678 power[ridx] += ofdmpow; 4679 if (power[ridx] > R92C_MAX_TX_PWR) 4680 power[ridx] = R92C_MAX_TX_PWR; 4681 } 4682 4683 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4684 for (ridx = 12; ridx <= 27; ridx++) { 4685 power[ridx] += bw20pow; 4686 if (power[ridx] > R92C_MAX_TX_PWR) 4687 power[ridx] = R92C_MAX_TX_PWR; 4688 } 4689 } 4690 4691 static void 4692 urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 4693 struct ieee80211_channel *extc) 4694 { 4695 uint16_t power[URTWN_RIDX_COUNT]; 4696 int i; 4697 4698 for (i = 0; i < sc->ntxchains; i++) { 4699 /* Compute per-rate Tx power values. */ 4700 if (sc->chip & URTWN_CHIP_88E) 4701 urtwn_r88e_get_txpower(sc, i, c, extc, power); 4702 else 4703 urtwn_get_txpower(sc, i, c, extc, power); 4704 /* Write per-rate Tx power values to hardware. */ 4705 urtwn_write_txpower(sc, i, power); 4706 } 4707 } 4708 4709 static void 4710 urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 4711 { 4712 uint32_t reg; 4713 4714 reg = urtwn_read_4(sc, R92C_RCR); 4715 if (enable) 4716 reg &= ~R92C_RCR_CBSSID_BCN; 4717 else 4718 reg |= R92C_RCR_CBSSID_BCN; 4719 urtwn_write_4(sc, R92C_RCR, reg); 4720 } 4721 4722 static void 4723 urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 4724 { 4725 uint32_t reg; 4726 4727 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 4728 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4729 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 4730 4731 if (!(sc->chip & URTWN_CHIP_88E)) { 4732 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 4733 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4734 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 4735 } 4736 } 4737 4738 static void 4739 urtwn_scan_start(struct ieee80211com *ic) 4740 { 4741 struct urtwn_softc *sc = ic->ic_softc; 4742 4743 URTWN_LOCK(sc); 4744 /* Receive beacons / probe responses from any BSSID. */ 4745 if (ic->ic_opmode != IEEE80211_M_IBSS) 4746 urtwn_set_rx_bssid_all(sc, 1); 4747 4748 /* Set gain for scanning. */ 4749 urtwn_set_gain(sc, 0x20); 4750 URTWN_UNLOCK(sc); 4751 } 4752 4753 static void 4754 urtwn_scan_end(struct ieee80211com *ic) 4755 { 4756 struct urtwn_softc *sc = ic->ic_softc; 4757 4758 URTWN_LOCK(sc); 4759 /* Restore limitations. */ 4760 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 4761 urtwn_set_rx_bssid_all(sc, 0); 4762 4763 /* Set gain under link. */ 4764 urtwn_set_gain(sc, 0x32); 4765 URTWN_UNLOCK(sc); 4766 } 4767 4768 static void 4769 urtwn_set_channel(struct ieee80211com *ic) 4770 { 4771 struct urtwn_softc *sc = ic->ic_softc; 4772 struct ieee80211_channel *c = ic->ic_curchan; 4773 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4774 4775 URTWN_LOCK(sc); 4776 if (vap->iv_state == IEEE80211_S_SCAN) { 4777 /* Make link LED blink during scan. */ 4778 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 4779 } 4780 urtwn_set_chan(sc, c, NULL); 4781 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 4782 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 4783 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 4784 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 4785 URTWN_UNLOCK(sc); 4786 } 4787 4788 static int 4789 urtwn_wme_update(struct ieee80211com *ic) 4790 { 4791 const struct wmeParams *wmep = 4792 ic->ic_wme.wme_chanParams.cap_wmeParams; 4793 struct urtwn_softc *sc = ic->ic_softc; 4794 uint8_t aifs, acm, slottime; 4795 int ac; 4796 4797 acm = 0; 4798 slottime = IEEE80211_GET_SLOTTIME(ic); 4799 4800 URTWN_LOCK(sc); 4801 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4802 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4803 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4804 urtwn_write_4(sc, wme2queue[ac].reg, 4805 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 4806 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 4807 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 4808 SM(R92C_EDCA_PARAM_AIFS, aifs)); 4809 if (ac != WME_AC_BE) 4810 acm |= wmep[ac].wmep_acm << ac; 4811 } 4812 4813 if (acm != 0) 4814 acm |= R92C_ACMHWCTRL_EN; 4815 urtwn_write_1(sc, R92C_ACMHWCTRL, 4816 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 4817 acm); 4818 4819 URTWN_UNLOCK(sc); 4820 4821 return 0; 4822 } 4823 4824 static void 4825 urtwn_update_slot(struct ieee80211com *ic) 4826 { 4827 urtwn_cmd_sleepable(ic->ic_softc, NULL, 0, urtwn_update_slot_cb); 4828 } 4829 4830 static void 4831 urtwn_update_slot_cb(struct urtwn_softc *sc, union sec_param *data) 4832 { 4833 struct ieee80211com *ic = &sc->sc_ic; 4834 uint8_t slottime; 4835 4836 slottime = IEEE80211_GET_SLOTTIME(ic); 4837 4838 URTWN_DPRINTF(sc, URTWN_DEBUG_ANY, "%s: setting slot time to %uus\n", 4839 __func__, slottime); 4840 4841 urtwn_write_1(sc, R92C_SLOT, slottime); 4842 urtwn_update_aifs(sc, slottime); 4843 } 4844 4845 static void 4846 urtwn_update_aifs(struct urtwn_softc *sc, uint8_t slottime) 4847 { 4848 const struct wmeParams *wmep = 4849 sc->sc_ic.ic_wme.wme_chanParams.cap_wmeParams; 4850 uint8_t aifs, ac; 4851 4852 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4853 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4854 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4855 urtwn_write_1(sc, wme2queue[ac].reg, aifs); 4856 } 4857 } 4858 4859 static uint8_t 4860 urtwn_get_multi_pos(const uint8_t maddr[]) 4861 { 4862 uint64_t mask = 0x00004d101df481b4; 4863 uint8_t pos = 0x27; /* initial value */ 4864 int i, j; 4865 4866 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 4867 for (j = (i == 0) ? 1 : 0; j < 8; j++) 4868 if ((maddr[i] >> j) & 1) 4869 pos ^= (mask >> (i * 8 + j - 1)); 4870 4871 pos &= 0x3f; 4872 4873 return (pos); 4874 } 4875 4876 static void 4877 urtwn_set_multi(struct urtwn_softc *sc) 4878 { 4879 struct ieee80211com *ic = &sc->sc_ic; 4880 uint32_t mfilt[2]; 4881 4882 URTWN_ASSERT_LOCKED(sc); 4883 4884 /* general structure was copied from ath(4). */ 4885 if (ic->ic_allmulti == 0) { 4886 struct ieee80211vap *vap; 4887 struct ifnet *ifp; 4888 struct ifmultiaddr *ifma; 4889 4890 /* 4891 * Merge multicast addresses to form the hardware filter. 4892 */ 4893 mfilt[0] = mfilt[1] = 0; 4894 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 4895 ifp = vap->iv_ifp; 4896 #if defined(__DragonFly__) 4897 /* XXX not implemented */ 4898 #else 4899 if_maddr_rlock(ifp); 4900 #endif 4901 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4902 caddr_t dl; 4903 uint8_t pos; 4904 4905 dl = LLADDR((struct sockaddr_dl *) 4906 ifma->ifma_addr); 4907 pos = urtwn_get_multi_pos(dl); 4908 4909 mfilt[pos / 32] |= (1 << (pos % 32)); 4910 } 4911 #if defined(__DragonFly__) 4912 /* XXX not implemented */ 4913 #else 4914 if_maddr_runlock(ifp); 4915 #endif 4916 } 4917 } else 4918 mfilt[0] = mfilt[1] = ~0; 4919 4920 4921 urtwn_write_4(sc, R92C_MAR + 0, mfilt[0]); 4922 urtwn_write_4(sc, R92C_MAR + 4, mfilt[1]); 4923 4924 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s: MC filter %08x:%08x\n", 4925 __func__, mfilt[0], mfilt[1]); 4926 } 4927 4928 static void 4929 urtwn_set_promisc(struct urtwn_softc *sc) 4930 { 4931 struct ieee80211com *ic = &sc->sc_ic; 4932 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4933 uint32_t rcr, mask1, mask2; 4934 4935 URTWN_ASSERT_LOCKED(sc); 4936 4937 if (vap->iv_opmode == IEEE80211_M_MONITOR) 4938 return; 4939 4940 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 4941 mask2 = R92C_RCR_APM; 4942 4943 if (vap->iv_state == IEEE80211_S_RUN) { 4944 switch (vap->iv_opmode) { 4945 case IEEE80211_M_STA: 4946 mask2 |= R92C_RCR_CBSSID_DATA; 4947 /* FALLTHROUGH */ 4948 case IEEE80211_M_HOSTAP: 4949 mask2 |= R92C_RCR_CBSSID_BCN; 4950 break; 4951 case IEEE80211_M_IBSS: 4952 mask2 |= R92C_RCR_CBSSID_DATA; 4953 break; 4954 default: 4955 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4956 __func__, vap->iv_opmode); 4957 return; 4958 } 4959 } 4960 4961 rcr = urtwn_read_4(sc, R92C_RCR); 4962 if (ic->ic_promisc == 0) 4963 rcr = (rcr & ~mask1) | mask2; 4964 else 4965 rcr = (rcr & ~mask2) | mask1; 4966 urtwn_write_4(sc, R92C_RCR, rcr); 4967 } 4968 4969 static void 4970 urtwn_update_promisc(struct ieee80211com *ic) 4971 { 4972 struct urtwn_softc *sc = ic->ic_softc; 4973 4974 URTWN_LOCK(sc); 4975 if (sc->sc_flags & URTWN_RUNNING) 4976 urtwn_set_promisc(sc); 4977 URTWN_UNLOCK(sc); 4978 } 4979 4980 static void 4981 urtwn_update_mcast(struct ieee80211com *ic) 4982 { 4983 struct urtwn_softc *sc = ic->ic_softc; 4984 4985 URTWN_LOCK(sc); 4986 if (sc->sc_flags & URTWN_RUNNING) 4987 urtwn_set_multi(sc); 4988 URTWN_UNLOCK(sc); 4989 } 4990 4991 static struct ieee80211_node * 4992 urtwn_node_alloc(struct ieee80211vap *vap, 4993 const uint8_t mac[IEEE80211_ADDR_LEN]) 4994 { 4995 struct urtwn_node *un; 4996 4997 un = kmalloc(sizeof (struct urtwn_node), M_80211_NODE, 4998 M_INTWAIT | M_ZERO); 4999 5000 if (un == NULL) 5001 return NULL; 5002 5003 un->id = URTWN_MACID_UNDEFINED; 5004 5005 return &un->ni; 5006 } 5007 5008 static void 5009 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 5010 { 5011 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 5012 struct urtwn_node *un = URTWN_NODE(ni); 5013 uint8_t id; 5014 5015 /* Only do this bit for R88E chips */ 5016 if (! (sc->chip & URTWN_CHIP_88E)) 5017 return; 5018 5019 if (!isnew) 5020 return; 5021 5022 URTWN_NT_LOCK(sc); 5023 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) { 5024 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) { 5025 un->id = id; 5026 sc->node_list[id] = ni; 5027 break; 5028 } 5029 } 5030 URTWN_NT_UNLOCK(sc); 5031 5032 if (id > URTWN_MACID_MAX(sc)) { 5033 device_printf(sc->sc_dev, "%s: node table is full\n", 5034 __func__); 5035 } 5036 } 5037 5038 static void 5039 urtwn_node_free(struct ieee80211_node *ni) 5040 { 5041 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 5042 struct urtwn_node *un = URTWN_NODE(ni); 5043 5044 URTWN_NT_LOCK(sc); 5045 if (un->id != URTWN_MACID_UNDEFINED) 5046 sc->node_list[un->id] = NULL; 5047 URTWN_NT_UNLOCK(sc); 5048 5049 sc->sc_node_free(ni); 5050 } 5051 5052 static void 5053 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 5054 struct ieee80211_channel *extc) 5055 { 5056 struct ieee80211com *ic = &sc->sc_ic; 5057 uint32_t reg; 5058 u_int chan; 5059 int i; 5060 5061 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 5062 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 5063 device_printf(sc->sc_dev, 5064 "%s: invalid channel %x\n", __func__, chan); 5065 return; 5066 } 5067 5068 /* Set Tx power for this new channel. */ 5069 urtwn_set_txpower(sc, c, extc); 5070 5071 for (i = 0; i < sc->nrxchains; i++) { 5072 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 5073 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 5074 } 5075 #ifndef IEEE80211_NO_HT 5076 if (extc != NULL) { 5077 /* Is secondary channel below or above primary? */ 5078 int prichlo = c->ic_freq < extc->ic_freq; 5079 5080 urtwn_write_1(sc, R92C_BWOPMODE, 5081 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 5082 5083 reg = urtwn_read_1(sc, R92C_RRSR + 2); 5084 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 5085 urtwn_write_1(sc, R92C_RRSR + 2, reg); 5086 5087 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5088 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 5089 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5090 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 5091 5092 /* Set CCK side band. */ 5093 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 5094 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 5095 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 5096 5097 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 5098 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 5099 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 5100 5101 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5102 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 5103 ~R92C_FPGA0_ANAPARAM2_CBW20); 5104 5105 reg = urtwn_bb_read(sc, 0x818); 5106 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 5107 urtwn_bb_write(sc, 0x818, reg); 5108 5109 /* Select 40MHz bandwidth. */ 5110 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5111 (sc->rf_chnlbw[0] & ~0xfff) | chan); 5112 } else 5113 #endif 5114 { 5115 urtwn_write_1(sc, R92C_BWOPMODE, 5116 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 5117 5118 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5119 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 5120 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5121 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 5122 5123 if (!(sc->chip & URTWN_CHIP_88E)) { 5124 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5125 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 5126 R92C_FPGA0_ANAPARAM2_CBW20); 5127 } 5128 5129 /* Select 20MHz bandwidth. */ 5130 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5131 (sc->rf_chnlbw[0] & ~0xfff) | chan | 5132 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 5133 R92C_RF_CHNLBW_BW20)); 5134 } 5135 } 5136 5137 static void 5138 urtwn_iq_calib(struct urtwn_softc *sc) 5139 { 5140 /* TODO */ 5141 } 5142 5143 static void 5144 urtwn_lc_calib(struct urtwn_softc *sc) 5145 { 5146 uint32_t rf_ac[2]; 5147 uint8_t txmode; 5148 int i; 5149 5150 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 5151 if ((txmode & 0x70) != 0) { 5152 /* Disable all continuous Tx. */ 5153 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 5154 5155 /* Set RF mode to standby mode. */ 5156 for (i = 0; i < sc->nrxchains; i++) { 5157 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 5158 urtwn_rf_write(sc, i, R92C_RF_AC, 5159 RW(rf_ac[i], R92C_RF_AC_MODE, 5160 R92C_RF_AC_MODE_STANDBY)); 5161 } 5162 } else { 5163 /* Block all Tx queues. */ 5164 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 5165 } 5166 /* Start calibration. */ 5167 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5168 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 5169 5170 /* Give calibration the time to complete. */ 5171 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 5172 5173 /* Restore configuration. */ 5174 if ((txmode & 0x70) != 0) { 5175 /* Restore Tx mode. */ 5176 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 5177 /* Restore RF mode. */ 5178 for (i = 0; i < sc->nrxchains; i++) 5179 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 5180 } else { 5181 /* Unblock all Tx queues. */ 5182 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 5183 } 5184 } 5185 5186 static void 5187 urtwn_temp_calib(struct urtwn_softc *sc) 5188 { 5189 uint8_t temp; 5190 5191 URTWN_ASSERT_LOCKED(sc); 5192 5193 if (!(sc->sc_flags & URTWN_TEMP_MEASURED)) { 5194 /* Start measuring temperature. */ 5195 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5196 "%s: start measuring temperature\n", __func__); 5197 if (sc->chip & URTWN_CHIP_88E) { 5198 urtwn_rf_write(sc, 0, R88E_RF_T_METER, 5199 R88E_RF_T_METER_START); 5200 } else { 5201 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 5202 R92C_RF_T_METER_START); 5203 } 5204 sc->sc_flags |= URTWN_TEMP_MEASURED; 5205 return; 5206 } 5207 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 5208 5209 /* Read measured temperature. */ 5210 if (sc->chip & URTWN_CHIP_88E) { 5211 temp = MS(urtwn_rf_read(sc, 0, R88E_RF_T_METER), 5212 R88E_RF_T_METER_VAL); 5213 } else { 5214 temp = MS(urtwn_rf_read(sc, 0, R92C_RF_T_METER), 5215 R92C_RF_T_METER_VAL); 5216 } 5217 if (temp == 0) { /* Read failed, skip. */ 5218 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5219 "%s: temperature read failed, skipping\n", __func__); 5220 return; 5221 } 5222 5223 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5224 "%s: temperature: previous %u, current %u\n", 5225 __func__, sc->thcal_lctemp, temp); 5226 5227 /* 5228 * Redo LC calibration if temperature changed significantly since 5229 * last calibration. 5230 */ 5231 if (sc->thcal_lctemp == 0) { 5232 /* First LC calibration is performed in urtwn_init(). */ 5233 sc->thcal_lctemp = temp; 5234 } else if (abs(temp - sc->thcal_lctemp) > 1) { 5235 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5236 "%s: LC calib triggered by temp: %u -> %u\n", 5237 __func__, sc->thcal_lctemp, temp); 5238 urtwn_lc_calib(sc); 5239 /* Record temperature of last LC calibration. */ 5240 sc->thcal_lctemp = temp; 5241 } 5242 } 5243 5244 static int 5245 urtwn_init(struct urtwn_softc *sc) 5246 { 5247 struct ieee80211com *ic = &sc->sc_ic; 5248 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5249 uint8_t macaddr[IEEE80211_ADDR_LEN]; 5250 uint32_t reg; 5251 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 5252 int error; 5253 5254 URTWN_LOCK(sc); 5255 if (sc->sc_flags & URTWN_RUNNING) { 5256 URTWN_UNLOCK(sc); 5257 return (0); 5258 } 5259 5260 /* Init firmware commands ring. */ 5261 sc->fwcur = 0; 5262 5263 /* Allocate Tx/Rx buffers. */ 5264 error = urtwn_alloc_rx_list(sc); 5265 if (error != 0) 5266 goto fail; 5267 5268 error = urtwn_alloc_tx_list(sc); 5269 if (error != 0) 5270 goto fail; 5271 5272 /* Power on adapter. */ 5273 error = urtwn_power_on(sc); 5274 if (error != 0) 5275 goto fail; 5276 5277 /* Initialize DMA. */ 5278 error = urtwn_dma_init(sc); 5279 if (error != 0) 5280 goto fail; 5281 5282 /* Set info size in Rx descriptors (in 64-bit words). */ 5283 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 5284 5285 /* Init interrupts. */ 5286 if (sc->chip & URTWN_CHIP_88E) { 5287 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 5288 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5289 goto fail; 5290 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 5291 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 5292 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5293 goto fail; 5294 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 5295 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 5296 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5297 goto fail; 5298 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5299 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5300 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 5301 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5302 goto fail; 5303 } else { 5304 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 5305 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5306 goto fail; 5307 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 5308 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5309 goto fail; 5310 } 5311 5312 /* Set MAC address. */ 5313 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 5314 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 5315 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5316 goto fail; 5317 5318 /* Set initial network type. */ 5319 urtwn_set_mode(sc, R92C_MSR_INFRA); 5320 5321 /* Initialize Rx filter. */ 5322 urtwn_rxfilter_init(sc); 5323 5324 /* Set response rate. */ 5325 reg = urtwn_read_4(sc, R92C_RRSR); 5326 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 5327 urtwn_write_4(sc, R92C_RRSR, reg); 5328 5329 /* Set short/long retry limits. */ 5330 urtwn_write_2(sc, R92C_RL, 5331 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 5332 5333 /* Initialize EDCA parameters. */ 5334 urtwn_edca_init(sc); 5335 5336 /* Setup rate fallback. */ 5337 if (!(sc->chip & URTWN_CHIP_88E)) { 5338 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 5339 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 5340 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 5341 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 5342 } 5343 5344 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 5345 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 5346 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 5347 /* Set ACK timeout. */ 5348 urtwn_write_1(sc, R92C_ACKTO, 0x40); 5349 5350 /* Setup USB aggregation. */ 5351 reg = urtwn_read_4(sc, R92C_TDECTRL); 5352 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 5353 urtwn_write_4(sc, R92C_TDECTRL, reg); 5354 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 5355 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 5356 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 5357 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 5358 if (sc->chip & URTWN_CHIP_88E) 5359 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 5360 else { 5361 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 5362 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5363 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5364 R92C_USB_SPECIAL_OPTION_AGG_EN); 5365 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 5366 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 5367 } 5368 5369 /* Initialize beacon parameters. */ 5370 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 5371 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 5372 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 5373 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 5374 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 5375 5376 if (!(sc->chip & URTWN_CHIP_88E)) { 5377 /* Setup AMPDU aggregation. */ 5378 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 5379 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 5380 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 5381 5382 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 5383 } 5384 5385 #ifndef URTWN_WITHOUT_UCODE 5386 /* Load 8051 microcode. */ 5387 error = urtwn_load_firmware(sc); 5388 if (error == 0) 5389 sc->sc_flags |= URTWN_FW_LOADED; 5390 #endif 5391 5392 /* Initialize MAC/BB/RF blocks. */ 5393 error = urtwn_mac_init(sc); 5394 if (error != 0) { 5395 device_printf(sc->sc_dev, 5396 "%s: error while initializing MAC block\n", __func__); 5397 goto fail; 5398 } 5399 urtwn_bb_init(sc); 5400 urtwn_rf_init(sc); 5401 5402 /* Reinitialize Rx filter (D3845 is not committed yet). */ 5403 urtwn_rxfilter_init(sc); 5404 5405 if (sc->chip & URTWN_CHIP_88E) { 5406 urtwn_write_2(sc, R92C_CR, 5407 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 5408 R92C_CR_MACRXEN); 5409 } 5410 5411 /* Turn CCK and OFDM blocks on. */ 5412 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5413 reg |= R92C_RFMOD_CCK_EN; 5414 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5415 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5416 goto fail; 5417 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5418 reg |= R92C_RFMOD_OFDM_EN; 5419 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5420 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5421 goto fail; 5422 5423 /* Clear per-station keys table. */ 5424 urtwn_cam_init(sc); 5425 5426 /* Enable decryption / encryption. */ 5427 urtwn_write_2(sc, R92C_SECCFG, 5428 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 5429 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA | 5430 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 5431 5432 /* 5433 * Install static keys (if any). 5434 * Must be called after urtwn_cam_init(). 5435 */ 5436 ieee80211_runtask(ic, &sc->cmdq_task); 5437 5438 /* Enable hardware sequence numbering. */ 5439 urtwn_write_1(sc, R92C_HWSEQ_CTRL, R92C_TX_QUEUE_ALL); 5440 5441 /* Enable per-packet TX report. */ 5442 if (sc->chip & URTWN_CHIP_88E) { 5443 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 5444 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA); 5445 } 5446 5447 /* Perform LO and IQ calibrations. */ 5448 urtwn_iq_calib(sc); 5449 /* Perform LC calibration. */ 5450 urtwn_lc_calib(sc); 5451 5452 /* Fix USB interference issue. */ 5453 if (!(sc->chip & URTWN_CHIP_88E)) { 5454 urtwn_write_1(sc, 0xfe40, 0xe0); 5455 urtwn_write_1(sc, 0xfe41, 0x8d); 5456 urtwn_write_1(sc, 0xfe42, 0x80); 5457 5458 urtwn_pa_bias_init(sc); 5459 } 5460 5461 /* Initialize GPIO setting. */ 5462 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5463 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5464 5465 /* Fix for lower temperature. */ 5466 if (!(sc->chip & URTWN_CHIP_88E)) 5467 urtwn_write_1(sc, 0x15, 0xe9); 5468 5469 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 5470 5471 sc->sc_flags |= URTWN_RUNNING; 5472 5473 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5474 fail: 5475 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5476 error = EIO; 5477 5478 URTWN_UNLOCK(sc); 5479 5480 return (error); 5481 } 5482 5483 static void 5484 urtwn_stop(struct urtwn_softc *sc) 5485 { 5486 5487 URTWN_LOCK(sc); 5488 if (!(sc->sc_flags & URTWN_RUNNING)) { 5489 URTWN_UNLOCK(sc); 5490 return; 5491 } 5492 5493 sc->sc_flags &= ~(URTWN_RUNNING | URTWN_FW_LOADED | 5494 URTWN_TEMP_MEASURED); 5495 sc->thcal_lctemp = 0; 5496 callout_stop(&sc->sc_watchdog_ch); 5497 5498 urtwn_abort_xfers(sc); 5499 urtwn_drain_mbufq(sc); 5500 urtwn_power_off(sc); 5501 URTWN_UNLOCK(sc); 5502 } 5503 5504 static void 5505 urtwn_abort_xfers(struct urtwn_softc *sc) 5506 { 5507 int i; 5508 5509 URTWN_ASSERT_LOCKED(sc); 5510 5511 /* abort any pending transfers */ 5512 for (i = 0; i < URTWN_N_TRANSFER; i++) 5513 usbd_transfer_stop(sc->sc_xfer[i]); 5514 } 5515 5516 static int 5517 urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 5518 const struct ieee80211_bpf_params *params) 5519 { 5520 struct ieee80211com *ic = ni->ni_ic; 5521 struct urtwn_softc *sc = ic->ic_softc; 5522 struct urtwn_data *bf; 5523 int error; 5524 5525 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n", 5526 __func__, 5527 m); 5528 5529 /* prevent management frames from being sent if we're not ready */ 5530 URTWN_LOCK(sc); 5531 if (!(sc->sc_flags & URTWN_RUNNING)) { 5532 error = ENETDOWN; 5533 goto end; 5534 } 5535 5536 bf = urtwn_getbuf(sc); 5537 if (bf == NULL) { 5538 error = ENOBUFS; 5539 goto end; 5540 } 5541 5542 if (params == NULL) { 5543 /* 5544 * Legacy path; interpret frame contents to decide 5545 * precisely how to send the frame. 5546 */ 5547 error = urtwn_tx_data(sc, ni, m, bf); 5548 } else { 5549 /* 5550 * Caller supplied explicit parameters to use in 5551 * sending the frame. 5552 */ 5553 error = urtwn_tx_raw(sc, ni, m, bf, params); 5554 } 5555 if (error != 0) { 5556 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 5557 goto end; 5558 } 5559 5560 sc->sc_txtimer = 5; 5561 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5562 5563 end: 5564 if (error != 0) 5565 m_freem(m); 5566 5567 URTWN_UNLOCK(sc); 5568 5569 return (error); 5570 } 5571 5572 static void 5573 urtwn_ms_delay(struct urtwn_softc *sc) 5574 { 5575 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 5576 } 5577 5578 static device_method_t urtwn_methods[] = { 5579 /* Device interface */ 5580 DEVMETHOD(device_probe, urtwn_match), 5581 DEVMETHOD(device_attach, urtwn_attach), 5582 DEVMETHOD(device_detach, urtwn_detach), 5583 5584 DEVMETHOD_END 5585 }; 5586 5587 static driver_t urtwn_driver = { 5588 "urtwn", 5589 urtwn_methods, 5590 sizeof(struct urtwn_softc) 5591 }; 5592 5593 static devclass_t urtwn_devclass; 5594 5595 DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 5596 MODULE_DEPEND(urtwn, usb, 1, 1, 1); 5597 MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 5598 #ifndef URTWN_WITHOUT_UCODE 5599 MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 5600 #endif 5601 MODULE_VERSION(urtwn, 1); 5602 #if defined(__DragonFly__) 5603 /* USB_PNP_HOST_INFO() not implemented */ 5604 #else 5605 USB_PNP_HOST_INFO(urtwn_devs); 5606 #endif 5607