1 /*- 2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ 17 * $FreeBSD: head/sys/dev/usb/wlan/if_urtwnreg.h 264912 2014-04-25 08:01:22Z kevlo $ 18 */ 19 20 #define URTWN_CONFIG_INDEX 0 21 #define URTWN_IFACE_INDEX 0 22 23 #define URTWN_NOISE_FLOOR -95 24 25 #define R92C_MAX_CHAINS 2 26 27 /* Maximum number of output pipes is 3. */ 28 #define R92C_MAX_EPOUT 3 29 30 #define R92C_MAX_TX_PWR 0x3f 31 32 #define R92C_PUBQ_NPAGES 231 33 #define R92C_TXPKTBUF_COUNT 256 34 #define R92C_TX_PAGE_COUNT 248 35 #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 36 #define R88E_TXPKTBUF_COUNT 177 37 #define R88E_TX_PAGE_COUNT 169 38 #define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 39 40 #define R92C_H2C_NBOX 4 41 42 /* USB Requests. */ 43 #define R92C_REQ_REGS 0x05 44 45 /* 46 * MAC registers. 47 */ 48 /* System Configuration. */ 49 #define R92C_SYS_ISO_CTRL 0x000 50 #define R92C_SYS_FUNC_EN 0x002 51 #define R92C_APS_FSMCO 0x004 52 #define R92C_SYS_CLKR 0x008 53 #define R92C_AFE_MISC 0x010 54 #define R92C_SPS0_CTRL 0x011 55 #define R92C_SPS_OCP_CFG 0x018 56 #define R92C_RSV_CTRL 0x01c 57 #define R92C_RF_CTRL 0x01f 58 #define R92C_LDOA15_CTRL 0x020 59 #define R92C_LDOV12D_CTRL 0x021 60 #define R92C_LDOHCI12_CTRL 0x022 61 #define R92C_LPLDO_CTRL 0x023 62 #define R92C_AFE_XTAL_CTRL 0x024 63 #define R92C_AFE_PLL_CTRL 0x028 64 #define R92C_EFUSE_CTRL 0x030 65 #define R92C_EFUSE_TEST 0x034 66 #define R92C_PWR_DATA 0x038 67 #define R92C_CAL_TIMER 0x03c 68 #define R92C_ACLK_MON 0x03e 69 #define R92C_GPIO_MUXCFG 0x040 70 #define R92C_GPIO_IO_SEL 0x042 71 #define R92C_MAC_PINMUX_CFG 0x043 72 #define R92C_GPIO_PIN_CTRL 0x044 73 #define R92C_GPIO_INTM 0x048 74 #define R92C_LEDCFG0 0x04c 75 #define R92C_LEDCFG1 0x04d 76 #define R92C_LEDCFG2 0x04e 77 #define R92C_LEDCFG3 0x04f 78 #define R92C_FSIMR 0x050 79 #define R92C_FSISR 0x054 80 #define R92C_HSIMR 0x058 81 #define R92C_HSISR 0x05c 82 #define R92C_MCUFWDL 0x080 83 #define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 84 #define R88E_HIMR 0x0b0 85 #define R88E_HISR 0x0b4 86 #define R88E_HIMRE 0x0b8 87 #define R88E_HISRE 0x0bc 88 #define R92C_EFUSE_ACCESS 0x0cf 89 #define R92C_BIST_SCAN 0x0d0 90 #define R92C_BIST_RPT 0x0d4 91 #define R92C_BIST_ROM_RPT 0x0d8 92 #define R92C_USB_SIE_INTF 0x0e0 93 #define R92C_PCIE_MIO_INTF 0x0e4 94 #define R92C_PCIE_MIO_INTD 0x0e8 95 #define R92C_HPON_FSM 0x0ec 96 #define R92C_SYS_CFG 0x0f0 97 /* MAC General Configuration. */ 98 #define R92C_CR 0x100 99 #define R92C_PBP 0x104 100 #define R92C_TRXDMA_CTRL 0x10c 101 #define R92C_TRXFF_BNDY 0x114 102 #define R92C_TRXFF_STATUS 0x118 103 #define R92C_RXFF_PTR 0x11c 104 #define R92C_HIMR 0x120 105 #define R92C_HISR 0x124 106 #define R92C_HIMRE 0x128 107 #define R92C_HISRE 0x12c 108 #define R92C_CPWM 0x12f 109 #define R92C_FWIMR 0x130 110 #define R92C_FWISR 0x134 111 #define R92C_PKTBUF_DBG_CTRL 0x140 112 #define R92C_PKTBUF_DBG_DATA_L 0x144 113 #define R92C_PKTBUF_DBG_DATA_H 0x148 114 #define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 115 #define R92C_TCUNIT_BASE 0x164 116 #define R92C_MBIST_START 0x174 117 #define R92C_MBIST_DONE 0x178 118 #define R92C_MBIST_FAIL 0x17c 119 #define R92C_C2HEVT_MSG_NORMAL 0x1a0 120 #define R92C_C2HEVT_MSG_TEST 0x1b8 121 #define R92C_C2HEVT_CLEAR 0x1bf 122 #define R92C_MCUTST_1 0x1c0 123 #define R92C_FMETHR 0x1c8 124 #define R92C_HMETFR 0x1cc 125 #define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 126 #define R92C_LLT_INIT 0x1e0 127 #define R92C_BB_ACCESS_CTRL 0x1e8 128 #define R92C_BB_ACCESS_DATA 0x1ec 129 #define R88E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) 130 /* Tx DMA Configuration. */ 131 #define R92C_RQPN 0x200 132 #define R92C_FIFOPAGE 0x204 133 #define R92C_TDECTRL 0x208 134 #define R92C_TXDMA_OFFSET_CHK 0x20c 135 #define R92C_TXDMA_STATUS 0x210 136 #define R92C_RQPN_NPQ 0x214 137 /* Rx DMA Configuration. */ 138 #define R92C_RXDMA_AGG_PG_TH 0x280 139 #define R92C_RXPKT_NUM 0x284 140 #define R92C_RXDMA_STATUS 0x288 141 /* Protocol Configuration. */ 142 #define R92C_FWHW_TXQ_CTRL 0x420 143 #define R92C_HWSEQ_CTRL 0x423 144 #define R92C_TXPKTBUF_BCNQ_BDNY 0x424 145 #define R92C_TXPKTBUF_MGQ_BDNY 0x425 146 #define R92C_SPEC_SIFS 0x428 147 #define R92C_RL 0x42a 148 #define R92C_DARFRC 0x430 149 #define R92C_RARFRC 0x438 150 #define R92C_RRSR 0x440 151 #define R92C_ARFR(i) (0x444 + (i) * 4) 152 #define R92C_AGGLEN_LMT 0x458 153 #define R92C_AMPDU_MIN_SPACE 0x45c 154 #define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 155 #define R92C_FAST_EDCA_CTRL 0x460 156 #define R92C_RD_RESP_PKT_TH 0x463 157 #define R92C_INIRTS_RATE_SEL 0x480 158 #define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 159 #define R92C_MAX_AGGR_NUM 0x4ca 160 /* EDCA Configuration. */ 161 #define R92C_EDCA_VO_PARAM 0x500 162 #define R92C_EDCA_VI_PARAM 0x504 163 #define R92C_EDCA_BE_PARAM 0x508 164 #define R92C_EDCA_BK_PARAM 0x50c 165 #define R92C_BCNTCFG 0x510 166 #define R92C_PIFS 0x512 167 #define R92C_RDG_PIFS 0x513 168 #define R92C_SIFS_CCK 0x514 169 #define R92C_SIFS_OFDM 0x516 170 #define R92C_AGGR_BREAK_TIME 0x51a 171 #define R92C_SLOT 0x51b 172 #define R92C_TX_PTCL_CTRL 0x520 173 #define R92C_TXPAUSE 0x522 174 #define R92C_DIS_TXREQ_CLR 0x523 175 #define R92C_RD_CTRL 0x524 176 #define R92C_TBTT_PROHIBIT 0x540 177 #define R92C_RD_NAV_NXT 0x544 178 #define R92C_NAV_PROT_LEN 0x546 179 #define R92C_BCN_CTRL 0x550 180 #define R92C_USTIME_TSF 0x551 181 #define R92C_MBID_NUM 0x552 182 #define R92C_DUAL_TSF_RST 0x553 183 #define R92C_BCN_INTERVAL 0x554 184 #define R92C_DRVERLYINT 0x558 185 #define R92C_BCNDMATIM 0x559 186 #define R92C_ATIMWND 0x55a 187 #define R92C_BCN_MAX_ERR 0x55d 188 #define R92C_RXTSF_OFFSET_CCK 0x55e 189 #define R92C_RXTSF_OFFSET_OFDM 0x55f 190 #define R92C_TSFTR 0x560 191 #define R92C_INIT_TSFTR 0x564 192 #define R92C_PSTIMER 0x580 193 #define R92C_TIMER0 0x584 194 #define R92C_TIMER1 0x588 195 #define R92C_ACMHWCTRL 0x5c0 196 #define R92C_ACMRSTCTRL 0x5c1 197 #define R92C_ACMAVG 0x5c2 198 #define R92C_VO_ADMTIME 0x5c4 199 #define R92C_VI_ADMTIME 0x5c6 200 #define R92C_BE_ADMTIME 0x5c8 201 #define R92C_EDCA_RANDOM_GEN 0x5cc 202 #define R92C_SCH_TXCMD 0x5d0 203 /* WMAC Configuration. */ 204 #define R92C_APSD_CTRL 0x600 205 #define R92C_BWOPMODE 0x603 206 #define R92C_RCR 0x608 207 #define R92C_RX_DRVINFO_SZ 0x60f 208 #define R92C_MACID 0x610 209 #define R92C_BSSID 0x618 210 #define R92C_MAR 0x620 211 #define R92C_MAC_SPEC_SIFS 0x63a 212 #define R92C_R2T_SIFS 0x63c 213 #define R92C_T2T_SIFS 0x63e 214 #define R92C_ACKTO 0x640 215 #define R92C_CAMCMD 0x670 216 #define R92C_CAMWRITE 0x674 217 #define R92C_CAMREAD 0x678 218 #define R92C_CAMDBG 0x67c 219 #define R92C_SECCFG 0x680 220 #define R92C_RXFLTMAP0 0x6a0 221 #define R92C_RXFLTMAP1 0x6a2 222 #define R92C_RXFLTMAP2 0x6a4 223 224 /* Bits for R92C_SYS_ISO_CTRL. */ 225 #define R92C_SYS_ISO_CTRL_MD2PP 0x0001 226 #define R92C_SYS_ISO_CTRL_UA2USB 0x0002 227 #define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 228 #define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 229 #define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 230 #define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 231 #define R92C_SYS_ISO_CTRL_DIOP 0x0040 232 #define R92C_SYS_ISO_CTRL_DIOE 0x0080 233 #define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 234 #define R92C_SYS_ISO_CTRL_DIOR 0x0200 235 #define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 236 #define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 237 238 /* Bits for R92C_SYS_FUNC_EN. */ 239 #define R92C_SYS_FUNC_EN_BBRSTB 0x0001 240 #define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 241 #define R92C_SYS_FUNC_EN_USBA 0x0004 242 #define R92C_SYS_FUNC_EN_UPLL 0x0008 243 #define R92C_SYS_FUNC_EN_USBD 0x0010 244 #define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 245 #define R92C_SYS_FUNC_EN_PCIEA 0x0040 246 #define R92C_SYS_FUNC_EN_PPLL 0x0080 247 #define R92C_SYS_FUNC_EN_PCIED 0x0100 248 #define R92C_SYS_FUNC_EN_DIOE 0x0200 249 #define R92C_SYS_FUNC_EN_CPUEN 0x0400 250 #define R92C_SYS_FUNC_EN_DCORE 0x0800 251 #define R92C_SYS_FUNC_EN_ELDR 0x1000 252 #define R92C_SYS_FUNC_EN_DIO_RF 0x2000 253 #define R92C_SYS_FUNC_EN_HWPDN 0x4000 254 #define R92C_SYS_FUNC_EN_MREGEN 0x8000 255 256 /* Bits for R92C_APS_FSMCO. */ 257 #define R92C_APS_FSMCO_PFM_LDALL 0x00000001 258 #define R92C_APS_FSMCO_PFM_ALDN 0x00000002 259 #define R92C_APS_FSMCO_PFM_LDKP 0x00000004 260 #define R92C_APS_FSMCO_PFM_WOWL 0x00000008 261 #define R92C_APS_FSMCO_PDN_EN 0x00000010 262 #define R92C_APS_FSMCO_PDN_PL 0x00000020 263 #define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 264 #define R92C_APS_FSMCO_APFM_OFF 0x00000200 265 #define R92C_APS_FSMCO_APFM_RSM 0x00000400 266 #define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 267 #define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 268 #define R92C_APS_FSMCO_APDM_MAC 0x00002000 269 #define R92C_APS_FSMCO_APDM_HOST 0x00004000 270 #define R92C_APS_FSMCO_APDM_HPDN 0x00008000 271 #define R92C_APS_FSMCO_RDY_MACON 0x00010000 272 #define R92C_APS_FSMCO_SUS_HOST 0x00020000 273 #define R92C_APS_FSMCO_ROP_ALD 0x00100000 274 #define R92C_APS_FSMCO_ROP_PWR 0x00200000 275 #define R92C_APS_FSMCO_ROP_SPS 0x00400000 276 #define R92C_APS_FSMCO_SOP_MRST 0x02000000 277 #define R92C_APS_FSMCO_SOP_FUSE 0x04000000 278 #define R92C_APS_FSMCO_SOP_ABG 0x08000000 279 #define R92C_APS_FSMCO_SOP_AMB 0x10000000 280 #define R92C_APS_FSMCO_SOP_RCK 0x20000000 281 #define R92C_APS_FSMCO_SOP_A8M 0x40000000 282 #define R92C_APS_FSMCO_XOP_BTCK 0x80000000 283 284 /* Bits for R92C_SYS_CLKR. */ 285 #define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 286 #define R92C_SYS_CLKR_ANA8M 0x00000002 287 #define R92C_SYS_CLKR_MACSLP 0x00000010 288 #define R92C_SYS_CLKR_LOADER_EN 0x00000020 289 #define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 290 #define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 291 #define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 292 #define R92C_SYS_CLKR_SEC_EN 0x00000400 293 #define R92C_SYS_CLKR_MAC_EN 0x00000800 294 #define R92C_SYS_CLKR_SYS_EN 0x00001000 295 #define R92C_SYS_CLKR_RING_EN 0x00002000 296 297 /* Bits for R92C_RF_CTRL. */ 298 #define R92C_RF_CTRL_EN 0x01 299 #define R92C_RF_CTRL_RSTB 0x02 300 #define R92C_RF_CTRL_SDMRSTB 0x04 301 302 /* Bits for R92C_LDOV12D_CTRL. */ 303 #define R92C_LDOV12D_CTRL_LDV12_EN 0x01 304 305 /* Bits for R92C_AFE_XTAL_CTRL. */ 306 #define R92C_AFE_XTAL_CTRL_ADDR_M 0x007ff800 307 #define R92C_AFE_XTAL_CTRL_ADDR_S 11 308 309 /* Bits for R92C_EFUSE_CTRL. */ 310 #define R92C_EFUSE_CTRL_DATA_M 0x000000ff 311 #define R92C_EFUSE_CTRL_DATA_S 0 312 #define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 313 #define R92C_EFUSE_CTRL_ADDR_S 8 314 #define R92C_EFUSE_CTRL_VALID 0x80000000 315 316 /* Bits for R92C_GPIO_MUXCFG. */ 317 #define R92C_GPIO_MUXCFG_ENBT 0x0020 318 319 /* Bits for R92C_LEDCFG0. */ 320 #define R92C_LEDCFG0_DIS 0x08 321 322 /* Bits for R92C_MCUFWDL. */ 323 #define R92C_MCUFWDL_EN 0x00000001 324 #define R92C_MCUFWDL_RDY 0x00000002 325 #define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 326 #define R92C_MCUFWDL_MACINI_RDY 0x00000008 327 #define R92C_MCUFWDL_BBINI_RDY 0x00000010 328 #define R92C_MCUFWDL_RFINI_RDY 0x00000020 329 #define R92C_MCUFWDL_WINTINI_RDY 0x00000040 330 #define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 331 #define R92C_MCUFWDL_PAGE_M 0x00070000 332 #define R92C_MCUFWDL_PAGE_S 16 333 #define R92C_MCUFWDL_CPRST 0x00800000 334 335 /* Bits for R88E_HIMR. */ 336 #define R88E_HIMR_CPWM 0x00000100 337 #define R88E_HIMR_CPWM2 0x00000200 338 #define R88E_HIMR_TBDER 0x04000000 339 #define R88E_HIMR_PSTIMEOUT 0x20000000 340 341 /* Bits for R88E_HIMRE.*/ 342 #define R88E_HIMRE_RXFOVW 0x00000100 343 #define R88E_HIMRE_TXFOVW 0x00000200 344 #define R88E_HIMRE_RXERR 0x00000400 345 #define R88E_HIMRE_TXERR 0x00000800 346 347 /* Bits for R92C_EFUSE_ACCESS. */ 348 #define R92C_EFUSE_ACCESS_OFF 0x00 349 #define R92C_EFUSE_ACCESS_ON 0x69 350 351 /* Bits for R92C_HPON_FSM. */ 352 #define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 353 #define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 354 #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 355 356 /* Bits for R92C_SYS_CFG. */ 357 #define R92C_SYS_CFG_XCLK_VLD 0x00000001 358 #define R92C_SYS_CFG_ACLK_VLD 0x00000002 359 #define R92C_SYS_CFG_UCLK_VLD 0x00000004 360 #define R92C_SYS_CFG_PCLK_VLD 0x00000008 361 #define R92C_SYS_CFG_PCIRSTB 0x00000010 362 #define R92C_SYS_CFG_V15_VLD 0x00000020 363 #define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 364 #define R92C_SYS_CFG_SIC_IDLE 0x00000100 365 #define R92C_SYS_CFG_BD_MAC2 0x00000200 366 #define R92C_SYS_CFG_BD_MAC1 0x00000400 367 #define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 368 #define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 369 #define R92C_SYS_CFG_CHIP_VER_RTL_S 12 370 #define R92C_SYS_CFG_BT_FUNC 0x00010000 371 #define R92C_SYS_CFG_VENDOR_UMC 0x00080000 372 #define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 373 #define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 374 #define R92C_SYS_CFG_TRP_BT_EN 0x01000000 375 #define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 376 #define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 377 #define R92C_SYS_CFG_TYPE_92C 0x08000000 378 379 /* Bits for R92C_CR. */ 380 #define R92C_CR_HCI_TXDMA_EN 0x00000001 381 #define R92C_CR_HCI_RXDMA_EN 0x00000002 382 #define R92C_CR_TXDMA_EN 0x00000004 383 #define R92C_CR_RXDMA_EN 0x00000008 384 #define R92C_CR_PROTOCOL_EN 0x00000010 385 #define R92C_CR_SCHEDULE_EN 0x00000020 386 #define R92C_CR_MACTXEN 0x00000040 387 #define R92C_CR_MACRXEN 0x00000080 388 #define R92C_CR_ENSEC 0x00000200 389 #define R92C_CR_CALTMR_EN 0x00000400 390 #define R92C_CR_NETTYPE_S 16 391 #define R92C_CR_NETTYPE_M 0x00030000 392 #define R92C_CR_NETTYPE_NOLINK 0 393 #define R92C_CR_NETTYPE_ADHOC 1 394 #define R92C_CR_NETTYPE_INFRA 2 395 #define R92C_CR_NETTYPE_AP 3 396 397 /* Bits for R92C_PBP. */ 398 #define R92C_PBP_PSRX_M 0x0f 399 #define R92C_PBP_PSRX_S 0 400 #define R92C_PBP_PSTX_M 0xf0 401 #define R92C_PBP_PSTX_S 4 402 #define R92C_PBP_64 0 403 #define R92C_PBP_128 1 404 #define R92C_PBP_256 2 405 #define R92C_PBP_512 3 406 #define R92C_PBP_1024 4 407 408 /* Bits for R92C_TRXDMA_CTRL. */ 409 #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 410 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 411 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 412 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 413 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 414 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 415 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 416 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 417 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 418 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 419 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 420 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 421 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 422 #define R92C_TRXDMA_CTRL_QUEUE_LOW 1 423 #define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 424 #define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 425 #define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 426 /* Shortcuts. */ 427 #define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 428 #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 429 #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 430 #define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 431 #define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 432 #define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 433 434 /* Bits for R92C_LLT_INIT. */ 435 #define R92C_LLT_INIT_DATA_M 0x000000ff 436 #define R92C_LLT_INIT_DATA_S 0 437 #define R92C_LLT_INIT_ADDR_M 0x0000ff00 438 #define R92C_LLT_INIT_ADDR_S 8 439 #define R92C_LLT_INIT_OP_M 0xc0000000 440 #define R92C_LLT_INIT_OP_S 30 441 #define R92C_LLT_INIT_OP_NO_ACTIVE 0 442 #define R92C_LLT_INIT_OP_WRITE 1 443 444 /* Bits for R92C_RQPN. */ 445 #define R92C_RQPN_HPQ_M 0x000000ff 446 #define R92C_RQPN_HPQ_S 0 447 #define R92C_RQPN_LPQ_M 0x0000ff00 448 #define R92C_RQPN_LPQ_S 8 449 #define R92C_RQPN_PUBQ_M 0x00ff0000 450 #define R92C_RQPN_PUBQ_S 16 451 #define R92C_RQPN_LD 0x80000000 452 453 /* Bits for R92C_TDECTRL. */ 454 #define R92C_TDECTRL_BLK_DESC_NUM_M 0x0000000f 455 #define R92C_TDECTRL_BLK_DESC_NUM_S 4 456 457 /* Bits for R92C_FWHW_TXQ_CTRL. */ 458 #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 459 460 /* Bits for R92C_SPEC_SIFS. */ 461 #define R92C_SPEC_SIFS_CCK_M 0x00ff 462 #define R92C_SPEC_SIFS_CCK_S 0 463 #define R92C_SPEC_SIFS_OFDM_M 0xff00 464 #define R92C_SPEC_SIFS_OFDM_S 8 465 466 /* Bits for R92C_RL. */ 467 #define R92C_RL_LRL_M 0x003f 468 #define R92C_RL_LRL_S 0 469 #define R92C_RL_SRL_M 0x3f00 470 #define R92C_RL_SRL_S 8 471 472 /* Bits for R92C_RRSR. */ 473 #define R92C_RRSR_RATE_BITMAP_M 0x000fffff 474 #define R92C_RRSR_RATE_BITMAP_S 0 475 #define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 476 #define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 477 #define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 478 #define R92C_RRSR_SHORT 0x00800000 479 480 /* Bits for R92C_EDCA_XX_PARAM. */ 481 #define R92C_EDCA_PARAM_AIFS_M 0x000000ff 482 #define R92C_EDCA_PARAM_AIFS_S 0 483 #define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 484 #define R92C_EDCA_PARAM_ECWMIN_S 8 485 #define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 486 #define R92C_EDCA_PARAM_ECWMAX_S 12 487 #define R92C_EDCA_PARAM_TXOP_M 0xffff0000 488 #define R92C_EDCA_PARAM_TXOP_S 16 489 490 /* Bits for R92C_BCN_CTRL. */ 491 #define R92C_BCN_CTRL_EN_MBSSID 0x02 492 #define R92C_BCN_CTRL_TXBCN_RPT 0x04 493 #define R92C_BCN_CTRL_EN_BCN 0x08 494 #define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 495 496 /* Bits for R92C_APSD_CTRL. */ 497 #define R92C_APSD_CTRL_OFF 0x40 498 #define R92C_APSD_CTRL_OFF_STATUS 0x80 499 500 /* Bits for R92C_BWOPMODE. */ 501 #define R92C_BWOPMODE_11J 0x01 502 #define R92C_BWOPMODE_5G 0x02 503 #define R92C_BWOPMODE_20MHZ 0x04 504 505 /* Bits for R92C_RCR. */ 506 #define R92C_RCR_AAP 0x00000001 507 #define R92C_RCR_APM 0x00000002 508 #define R92C_RCR_AM 0x00000004 509 #define R92C_RCR_AB 0x00000008 510 #define R92C_RCR_ADD3 0x00000010 511 #define R92C_RCR_APWRMGT 0x00000020 512 #define R92C_RCR_CBSSID_DATA 0x00000040 513 #define R92C_RCR_CBSSID_BCN 0x00000080 514 #define R92C_RCR_ACRC32 0x00000100 515 #define R92C_RCR_AICV 0x00000200 516 #define R92C_RCR_ADF 0x00000800 517 #define R92C_RCR_ACF 0x00001000 518 #define R92C_RCR_AMF 0x00002000 519 #define R92C_RCR_HTC_LOC_CTRL 0x00004000 520 #define R92C_RCR_MFBEN 0x00400000 521 #define R92C_RCR_LSIGEN 0x00800000 522 #define R92C_RCR_ENMBID 0x01000000 523 #define R92C_RCR_APP_BA_SSN 0x08000000 524 #define R92C_RCR_APP_PHYSTS 0x10000000 525 #define R92C_RCR_APP_ICV 0x20000000 526 #define R92C_RCR_APP_MIC 0x40000000 527 #define R92C_RCR_APPFCS 0x80000000 528 529 /* Bits for R92C_CAMCMD. */ 530 #define R92C_CAMCMD_ADDR_M 0x0000ffff 531 #define R92C_CAMCMD_ADDR_S 0 532 #define R92C_CAMCMD_WRITE 0x00010000 533 #define R92C_CAMCMD_CLR 0x40000000 534 #define R92C_CAMCMD_POLLING 0x80000000 535 536 537 /* 538 * Baseband registers. 539 */ 540 #define R92C_FPGA0_RFMOD 0x800 541 #define R92C_FPGA0_TXINFO 0x804 542 #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 543 #define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 544 #define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 545 #define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 546 #define R92C_TXAGC_A_CCK1_MCS32 0xe08 547 #define R92C_TXAGC_B_CCK1_55_MCS32 0x838 548 #define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 549 #define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 550 #define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 551 #define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 552 #define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 553 #define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 554 #define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 555 #define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 556 #define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 557 #define R92C_FPGA0_ANAPARAM2 0x884 558 #define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 559 #define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 560 #define R92C_FPGA1_RFMOD 0x900 561 #define R92C_FPGA1_TXINFO 0x90c 562 #define R92C_CCK0_SYSTEM 0xa00 563 #define R92C_CCK0_AFESETTING 0xa04 564 #define R92C_OFDM0_TRXPATHENA 0xc04 565 #define R92C_OFDM0_TRMUXPAR 0xc08 566 #define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 567 #define R92C_OFDM0_AGCPARAM1 0xc70 568 #define R92C_OFDM0_AGCRSSITABLE 0xc78 569 #define R92C_OFDM1_LSTF 0xd00 570 571 /* Bits for R92C_FPGA[01]_RFMOD. */ 572 #define R92C_RFMOD_40MHZ 0x00000001 573 #define R92C_RFMOD_JAPAN 0x00000002 574 #define R92C_RFMOD_CCK_TXSC 0x00000030 575 #define R92C_RFMOD_CCK_EN 0x01000000 576 #define R92C_RFMOD_OFDM_EN 0x02000000 577 578 /* Bits for R92C_HSSI_PARAM1(i). */ 579 #define R92C_HSSI_PARAM1_PI 0x00000100 580 581 /* Bits for R92C_HSSI_PARAM2(i). */ 582 #define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 583 #define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 584 #define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 585 #define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 586 #define R92C_HSSI_PARAM2_READ_ADDR_S 23 587 #define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 588 589 /* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 590 #define R92C_TXAGC_A_CCK1_M 0x0000ff00 591 #define R92C_TXAGC_A_CCK1_S 8 592 593 /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 594 #define R92C_TXAGC_B_CCK11_M 0x000000ff 595 #define R92C_TXAGC_B_CCK11_S 0 596 #define R92C_TXAGC_A_CCK2_M 0x0000ff00 597 #define R92C_TXAGC_A_CCK2_S 8 598 #define R92C_TXAGC_A_CCK55_M 0x00ff0000 599 #define R92C_TXAGC_A_CCK55_S 16 600 #define R92C_TXAGC_A_CCK11_M 0xff000000 601 #define R92C_TXAGC_A_CCK11_S 24 602 603 /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 604 #define R92C_TXAGC_B_CCK1_M 0x0000ff00 605 #define R92C_TXAGC_B_CCK1_S 8 606 #define R92C_TXAGC_B_CCK2_M 0x00ff0000 607 #define R92C_TXAGC_B_CCK2_S 16 608 #define R92C_TXAGC_B_CCK55_M 0xff000000 609 #define R92C_TXAGC_B_CCK55_S 24 610 611 /* Bits for R92C_TXAGC_RATE18_06(x). */ 612 #define R92C_TXAGC_RATE06_M 0x000000ff 613 #define R92C_TXAGC_RATE06_S 0 614 #define R92C_TXAGC_RATE09_M 0x0000ff00 615 #define R92C_TXAGC_RATE09_S 8 616 #define R92C_TXAGC_RATE12_M 0x00ff0000 617 #define R92C_TXAGC_RATE12_S 16 618 #define R92C_TXAGC_RATE18_M 0xff000000 619 #define R92C_TXAGC_RATE18_S 24 620 621 /* Bits for R92C_TXAGC_RATE54_24(x). */ 622 #define R92C_TXAGC_RATE24_M 0x000000ff 623 #define R92C_TXAGC_RATE24_S 0 624 #define R92C_TXAGC_RATE36_M 0x0000ff00 625 #define R92C_TXAGC_RATE36_S 8 626 #define R92C_TXAGC_RATE48_M 0x00ff0000 627 #define R92C_TXAGC_RATE48_S 16 628 #define R92C_TXAGC_RATE54_M 0xff000000 629 #define R92C_TXAGC_RATE54_S 24 630 631 /* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 632 #define R92C_TXAGC_MCS00_M 0x000000ff 633 #define R92C_TXAGC_MCS00_S 0 634 #define R92C_TXAGC_MCS01_M 0x0000ff00 635 #define R92C_TXAGC_MCS01_S 8 636 #define R92C_TXAGC_MCS02_M 0x00ff0000 637 #define R92C_TXAGC_MCS02_S 16 638 #define R92C_TXAGC_MCS03_M 0xff000000 639 #define R92C_TXAGC_MCS03_S 24 640 641 /* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 642 #define R92C_TXAGC_MCS04_M 0x000000ff 643 #define R92C_TXAGC_MCS04_S 0 644 #define R92C_TXAGC_MCS05_M 0x0000ff00 645 #define R92C_TXAGC_MCS05_S 8 646 #define R92C_TXAGC_MCS06_M 0x00ff0000 647 #define R92C_TXAGC_MCS06_S 16 648 #define R92C_TXAGC_MCS07_M 0xff000000 649 #define R92C_TXAGC_MCS07_S 24 650 651 /* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 652 #define R92C_TXAGC_MCS08_M 0x000000ff 653 #define R92C_TXAGC_MCS08_S 0 654 #define R92C_TXAGC_MCS09_M 0x0000ff00 655 #define R92C_TXAGC_MCS09_S 8 656 #define R92C_TXAGC_MCS10_M 0x00ff0000 657 #define R92C_TXAGC_MCS10_S 16 658 #define R92C_TXAGC_MCS11_M 0xff000000 659 #define R92C_TXAGC_MCS11_S 24 660 661 /* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 662 #define R92C_TXAGC_MCS12_M 0x000000ff 663 #define R92C_TXAGC_MCS12_S 0 664 #define R92C_TXAGC_MCS13_M 0x0000ff00 665 #define R92C_TXAGC_MCS13_S 8 666 #define R92C_TXAGC_MCS14_M 0x00ff0000 667 #define R92C_TXAGC_MCS14_S 16 668 #define R92C_TXAGC_MCS15_M 0xff000000 669 #define R92C_TXAGC_MCS15_S 24 670 671 /* Bits for R92C_LSSI_PARAM(i). */ 672 #define R92C_LSSI_PARAM_DATA_M 0x000fffff 673 #define R92C_LSSI_PARAM_DATA_S 0 674 #define R92C_LSSI_PARAM_ADDR_M 0x03f00000 675 #define R92C_LSSI_PARAM_ADDR_S 20 676 #define R88E_LSSI_PARAM_ADDR_M 0x0ff00000 677 #define R88E_LSSI_PARAM_ADDR_S 20 678 679 /* Bits for R92C_FPGA0_ANAPARAM2. */ 680 #define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 681 682 /* Bits for R92C_LSSI_READBACK(i). */ 683 #define R92C_LSSI_READBACK_DATA_M 0x000fffff 684 #define R92C_LSSI_READBACK_DATA_S 0 685 686 /* Bits for R92C_OFDM0_AGCCORE1(i). */ 687 #define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 688 #define R92C_OFDM0_AGCCORE1_GAIN_S 0 689 690 691 /* 692 * USB registers. 693 */ 694 #define R92C_USB_INFO 0xfe17 695 #define R92C_USB_SPECIAL_OPTION 0xfe55 696 #define R92C_USB_HCPWM 0xfe57 697 #define R92C_USB_HRPWM 0xfe58 698 #define R92C_USB_DMA_AGG_TO 0xfe5b 699 #define R92C_USB_AGG_TO 0xfe5c 700 #define R92C_USB_AGG_TH 0xfe5d 701 #define R92C_USB_VID 0xfe60 702 #define R92C_USB_PID 0xfe62 703 #define R92C_USB_OPTIONAL 0xfe64 704 #define R92C_USB_EP 0xfe65 705 #define R92C_USB_PHY 0xfe68 706 #define R92C_USB_MAC_ADDR 0xfe70 707 #define R92C_USB_STRING 0xfe80 708 709 /* Bits for R92C_USB_SPECIAL_OPTION. */ 710 #define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 711 #define R92C_USB_SPECIAL_OPTION_INT_BULK_SEL 0x10 712 713 /* Bits for R92C_USB_EP. */ 714 #define R92C_USB_EP_HQ_M 0x000f 715 #define R92C_USB_EP_HQ_S 0 716 #define R92C_USB_EP_NQ_M 0x00f0 717 #define R92C_USB_EP_NQ_S 4 718 #define R92C_USB_EP_LQ_M 0x0f00 719 #define R92C_USB_EP_LQ_S 8 720 721 722 /* 723 * Firmware base address. 724 */ 725 #define R92C_FW_START_ADDR 0x1000 726 #define R92C_FW_PAGE_SIZE 4096 727 728 729 /* 730 * RF (6052) registers. 731 */ 732 #define R92C_RF_AC 0x00 733 #define R92C_RF_IQADJ_G(i) (0x01 + (i)) 734 #define R92C_RF_POW_TRSW 0x05 735 #define R92C_RF_GAIN_RX 0x06 736 #define R92C_RF_GAIN_TX 0x07 737 #define R92C_RF_TXM_IDAC 0x08 738 #define R92C_RF_BS_IQGEN 0x0f 739 #define R92C_RF_MODE1 0x10 740 #define R92C_RF_MODE2 0x11 741 #define R92C_RF_RX_AGC_HP 0x12 742 #define R92C_RF_TX_AGC 0x13 743 #define R92C_RF_BIAS 0x14 744 #define R92C_RF_IPA 0x15 745 #define R92C_RF_POW_ABILITY 0x17 746 #define R92C_RF_CHNLBW 0x18 747 #define R92C_RF_RX_G1 0x1a 748 #define R92C_RF_RX_G2 0x1b 749 #define R92C_RF_RX_BB2 0x1c 750 #define R92C_RF_RX_BB1 0x1d 751 #define R92C_RF_RCK1 0x1e 752 #define R92C_RF_RCK2 0x1f 753 #define R92C_RF_TX_G(i) (0x20 + (i)) 754 #define R92C_RF_TX_BB1 0x23 755 #define R92C_RF_T_METER 0x24 756 #define R92C_RF_SYN_G(i) (0x25 + (i)) 757 #define R92C_RF_RCK_OS 0x30 758 #define R92C_RF_TXPA_G(i) (0x31 + (i)) 759 760 /* Bits for R92C_RF_AC. */ 761 #define R92C_RF_AC_MODE_M 0x70000 762 #define R92C_RF_AC_MODE_S 16 763 #define R92C_RF_AC_MODE_STANDBY 1 764 765 /* Bits for R92C_RF_CHNLBW. */ 766 #define R92C_RF_CHNLBW_CHNL_M 0x003ff 767 #define R92C_RF_CHNLBW_CHNL_S 0 768 #define R92C_RF_CHNLBW_BW20 0x00400 769 #define R88E_RF_CHNLBW_BW20 0x00c00 770 #define R92C_RF_CHNLBW_LCSTART 0x08000 771 772 773 /* 774 * CAM entries. 775 */ 776 #define R92C_CAM_ENTRY_COUNT 32 777 778 #define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 779 #define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 780 #define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 781 782 /* Bits for R92C_CAM_CTL0(i). */ 783 #define R92C_CAM_KEYID_M 0x00000003 784 #define R92C_CAM_KEYID_S 0 785 #define R92C_CAM_ALGO_M 0x0000001c 786 #define R92C_CAM_ALGO_S 2 787 #define R92C_CAM_ALGO_NONE 0 788 #define R92C_CAM_ALGO_WEP40 1 789 #define R92C_CAM_ALGO_TKIP 2 790 #define R92C_CAM_ALGO_AES 4 791 #define R92C_CAM_ALGO_WEP104 5 792 #define R92C_CAM_VALID 0x00008000 793 #define R92C_CAM_MACLO_M 0xffff0000 794 #define R92C_CAM_MACLO_S 16 795 796 /* Rate adaptation modes. */ 797 #define R92C_RAID_11GN 1 798 #define R92C_RAID_11N 3 799 #define R92C_RAID_11BG 4 800 #define R92C_RAID_11G 5 /* "pure" 11g */ 801 #define R92C_RAID_11B 6 802 803 804 /* Macros to access unaligned little-endian memory. */ 805 #define LE_READ_2(x) ((x)[0] | (x)[1] << 8) 806 #define LE_READ_4(x) ((x)[0] | (x)[1] << 8 | (x)[2] << 16 | (x)[3] << 24) 807 808 /* 809 * Macros to access subfields in registers. 810 */ 811 /* Mask and Shift (getter). */ 812 #define MS(val, field) \ 813 (((val) & field##_M) >> field##_S) 814 815 /* Shift and Mask (setter). */ 816 #define SM(field, val) \ 817 (((val) << field##_S) & field##_M) 818 819 /* Rewrite. */ 820 #define RW(var, field, val) \ 821 (((var) & ~field##_M) | SM(field, val)) 822 823 /* 824 * Firmware image header. 825 */ 826 struct r92c_fw_hdr { 827 /* QWORD0 */ 828 uint16_t signature; 829 uint8_t category; 830 uint8_t function; 831 uint16_t version; 832 uint16_t subversion; 833 /* QWORD1 */ 834 uint8_t month; 835 uint8_t date; 836 uint8_t hour; 837 uint8_t minute; 838 uint16_t ramcodesize; 839 uint16_t reserved2; 840 /* QWORD2 */ 841 uint32_t svnidx; 842 uint32_t reserved3; 843 /* QWORD3 */ 844 uint32_t reserved4; 845 uint32_t reserved5; 846 } __packed; 847 848 /* 849 * Host to firmware commands. 850 */ 851 struct r92c_fw_cmd { 852 uint8_t id; 853 #define R92C_CMD_AP_OFFLOAD 0 854 #define R92C_CMD_SET_PWRMODE 1 855 #define R92C_CMD_JOINBSS_RPT 2 856 #define R92C_CMD_RSVD_PAGE 3 857 #define R92C_CMD_RSSI 4 858 #define R92C_CMD_RSSI_SETTING 5 859 #define R92C_CMD_MACID_CONFIG 6 860 #define R92C_CMD_MACID_PS_MODE 7 861 #define R92C_CMD_P2P_PS_OFFLOAD 8 862 #define R92C_CMD_SELECTIVE_SUSPEND 9 863 #define R92C_CMD_FLAG_EXT 0x80 864 865 uint8_t msg[5]; 866 } __packed; 867 868 /* Structure for R92C_CMD_RSSI_SETTING. */ 869 struct r92c_fw_cmd_rssi { 870 uint8_t macid; 871 uint8_t reserved; 872 uint8_t pwdb; 873 } __packed; 874 875 /* Structure for R92C_CMD_MACID_CONFIG. */ 876 struct r92c_fw_cmd_macid_cfg { 877 uint32_t mask; 878 uint8_t macid; 879 #define URTWN_MACID_BSS 0 880 #define URTWN_MACID_BC 4 /* Broadcast. */ 881 #define URTWN_MACID_VALID 0x80 882 } __packed; 883 884 /* 885 * RTL8192CU ROM image. 886 */ 887 struct r92c_rom { 888 uint16_t id; /* 0x8192 */ 889 uint8_t reserved1[5]; 890 uint8_t dbg_sel; 891 uint16_t reserved2; 892 uint16_t vid; 893 uint16_t pid; 894 uint8_t usb_opt; 895 uint8_t ep_setting; 896 uint16_t reserved3; 897 uint8_t usb_phy; 898 uint8_t reserved4[3]; 899 uint8_t macaddr[6]; 900 uint8_t string[61]; /* "Realtek" */ 901 uint8_t subcustomer_id; 902 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 903 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 904 uint8_t ht40_2s_tx_pwr_diff[3]; 905 uint8_t ht20_tx_pwr_diff[3]; 906 uint8_t ofdm_tx_pwr_diff[3]; 907 uint8_t ht40_max_pwr[3]; 908 uint8_t ht20_max_pwr[3]; 909 uint8_t xtal_calib; 910 uint8_t tssi[R92C_MAX_CHAINS]; 911 uint8_t thermal_meter; 912 uint8_t rf_opt1; 913 #define R92C_ROM_RF1_REGULATORY_M 0x07 914 #define R92C_ROM_RF1_REGULATORY_S 0 915 #define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 916 #define R92C_ROM_RF1_BOARD_TYPE_S 5 917 #define R92C_BOARD_TYPE_DONGLE 0 918 #define R92C_BOARD_TYPE_HIGHPA 1 919 #define R92C_BOARD_TYPE_MINICARD 2 920 #define R92C_BOARD_TYPE_SOLO 3 921 #define R92C_BOARD_TYPE_COMBO 4 922 923 uint8_t rf_opt2; 924 uint8_t rf_opt3; 925 uint8_t rf_opt4; 926 uint8_t channel_plan; 927 uint8_t version; 928 uint8_t curstomer_id; 929 } __packed; 930 931 /* Rx MAC descriptor. */ 932 struct r92c_rx_stat { 933 uint32_t rxdw0; 934 #define R92C_RXDW0_PKTLEN_M 0x00003fff 935 #define R92C_RXDW0_PKTLEN_S 0 936 #define R92C_RXDW0_CRCERR 0x00004000 937 #define R92C_RXDW0_ICVERR 0x00008000 938 #define R92C_RXDW0_INFOSZ_M 0x000f0000 939 #define R92C_RXDW0_INFOSZ_S 16 940 #define R92C_RXDW0_QOS 0x00800000 941 #define R92C_RXDW0_SHIFT_M 0x03000000 942 #define R92C_RXDW0_SHIFT_S 24 943 #define R92C_RXDW0_PHYST 0x04000000 944 #define R92C_RXDW0_DECRYPTED 0x08000000 945 946 uint32_t rxdw1; 947 uint32_t rxdw2; 948 #define R92C_RXDW2_PKTCNT_M 0x00ff0000 949 #define R92C_RXDW2_PKTCNT_S 16 950 951 uint32_t rxdw3; 952 #define R92C_RXDW3_RATE_M 0x0000003f 953 #define R92C_RXDW3_RATE_S 0 954 #define R92C_RXDW3_HT 0x00000040 955 #define R92C_RXDW3_HTC 0x00000400 956 957 uint32_t rxdw4; 958 uint32_t rxdw5; 959 } __packed __attribute__((aligned(4))); 960 961 /* Rx PHY descriptor. */ 962 struct r92c_rx_phystat { 963 uint32_t phydw0; 964 uint32_t phydw1; 965 uint32_t phydw2; 966 uint32_t phydw3; 967 uint32_t phydw4; 968 uint32_t phydw5; 969 uint32_t phydw6; 970 uint32_t phydw7; 971 } __packed __attribute__((aligned(4))); 972 973 /* Rx PHY CCK descriptor. */ 974 struct r92c_rx_cck { 975 uint8_t adc_pwdb[4]; 976 uint8_t sq_rpt; 977 uint8_t agc_rpt; 978 } __packed; 979 980 struct r88e_rx_cck { 981 uint8_t path_agc[2]; 982 uint8_t sig_qual; 983 uint8_t agc_rpt; 984 uint8_t rpt_b; 985 uint8_t reserved1; 986 uint8_t noise_power; 987 uint8_t path_cfotail[2]; 988 uint8_t pcts_mask[2]; 989 uint8_t stream_rxevm[2]; 990 uint8_t path_rxsnr[2]; 991 uint8_t noise_power_db_lsb; 992 uint8_t reserved2[3]; 993 uint8_t stream_csi[2]; 994 uint8_t stream_target_csi[2]; 995 uint8_t sig_evm; 996 uint8_t reserved3; 997 uint8_t reserved4; 998 } __packed; 999 1000 /* Tx MAC descriptor. */ 1001 struct r92c_tx_desc { 1002 uint32_t txdw0; 1003 #define R92C_TXDW0_PKTLEN_M 0x0000ffff 1004 #define R92C_TXDW0_PKTLEN_S 0 1005 #define R92C_TXDW0_OFFSET_M 0x00ff0000 1006 #define R92C_TXDW0_OFFSET_S 16 1007 #define R92C_TXDW0_BMCAST 0x01000000 1008 #define R92C_TXDW0_LSG 0x04000000 1009 #define R92C_TXDW0_FSG 0x08000000 1010 #define R92C_TXDW0_OWN 0x80000000 1011 1012 uint32_t txdw1; 1013 #define R92C_TXDW1_MACID_M 0x0000001f 1014 #define R92C_TXDW1_MACID_S 0 1015 #define R88E_TXDW1_MACID_M 0x0000003f 1016 #define R88E_TXDW1_MACID_S 0 1017 #define R92C_TXDW1_AGGEN 0x00000020 1018 #define R92C_TXDW1_AGGBK 0x00000040 1019 #define R92C_TXDW1_QSEL_M 0x00001f00 1020 #define R92C_TXDW1_QSEL_S 8 1021 #define R92C_TXDW1_QSEL_BE 0x00 1022 #define R92C_TXDW1_QSEL_MGNT 0x12 1023 #define R92C_TXDW1_RAID_M 0x000f0000 1024 #define R92C_TXDW1_RAID_S 16 1025 #define R92C_TXDW1_CIPHER_M 0x00c00000 1026 #define R92C_TXDW1_CIPHER_S 22 1027 #define R92C_TXDW1_CIPHER_NONE 0 1028 #define R92C_TXDW1_CIPHER_RC4 1 1029 #define R92C_TXDW1_CIPHER_AES 3 1030 #define R92C_TXDW1_PKTOFF_M 0x7c000000 1031 #define R92C_TXDW1_PKTOFF_S 26 1032 1033 uint32_t txdw2; 1034 #define R88E_TXDW2_AGGBK 0x00010000 1035 1036 uint16_t txdw3; 1037 uint16_t txdseq; 1038 1039 uint32_t txdw4; 1040 #define R92C_TXDW4_RTSRATE_M 0x0000003f 1041 #define R92C_TXDW4_RTSRATE_S 0 1042 #define R92C_TXDW4_QOS 0x00000040 1043 #define R92C_TXDW4_HWSEQ 0x00000080 1044 #define R92C_TXDW4_DRVRATE 0x00000100 1045 #define R92C_TXDW4_CTS2SELF 0x00000800 1046 #define R92C_TXDW4_RTSEN 0x00001000 1047 #define R92C_TXDW4_HWRTSEN 0x00002000 1048 #define R92C_TXDW4_SCO_M 0x003f0000 1049 #define R92C_TXDW4_SCO_S 20 1050 #define R92C_TXDW4_SCO_SCA 1 1051 #define R92C_TXDW4_SCO_SCB 2 1052 #define R92C_TXDW4_40MHZ 0x02000000 1053 1054 uint32_t txdw5; 1055 #define R92C_TXDW5_DATARATE_M 0x0000003f 1056 #define R92C_TXDW5_DATARATE_S 0 1057 #define R92C_TXDW5_SGI 0x00000040 1058 #define R92C_TXDW5_AGGNUM_M 0xff000000 1059 #define R92C_TXDW5_AGGNUM_S 24 1060 1061 uint32_t txdw6; 1062 uint16_t txdsum; 1063 uint16_t pad; 1064 } __packed __attribute__((aligned(4))); 1065 1066 1067 /* 1068 * Driver definitions. 1069 */ 1070 #define URTWN_RX_LIST_COUNT 1 1071 #define URTWN_TX_LIST_COUNT 8 1072 #define URTWN_HOST_CMD_RING_COUNT 32 1073 1074 #define URTWN_RXBUFSZ (16 * 1024) 1075 #define URTWN_TXBUFSZ (sizeof(struct r92c_tx_desc) + IEEE80211_MAX_LEN) 1076 #define URTWN_RX_DESC_SIZE (sizeof(struct r92c_rx_stat)) 1077 #define URTWN_TX_DESC_SIZE (sizeof(struct r92c_tx_desc)) 1078 1079 #define URTWN_RIDX_COUNT 28 1080 1081 #define URTWN_TX_TIMEOUT 5000 /* ms */ 1082 1083 #define URTWN_LED_LINK 0 1084 #define URTWN_LED_DATA 1 1085 1086 struct urtwn_rx_radiotap_header { 1087 struct ieee80211_radiotap_header wr_ihdr; 1088 uint8_t wr_flags; 1089 uint8_t wr_rate; 1090 uint16_t wr_chan_freq; 1091 uint16_t wr_chan_flags; 1092 uint8_t wr_dbm_antsignal; 1093 } __packed __aligned(8); 1094 1095 #define URTWN_RX_RADIOTAP_PRESENT \ 1096 (1 << IEEE80211_RADIOTAP_FLAGS | \ 1097 1 << IEEE80211_RADIOTAP_RATE | \ 1098 1 << IEEE80211_RADIOTAP_CHANNEL | \ 1099 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 1100 1101 struct urtwn_tx_radiotap_header { 1102 struct ieee80211_radiotap_header wt_ihdr; 1103 uint8_t wt_flags; 1104 uint16_t wt_chan_freq; 1105 uint16_t wt_chan_flags; 1106 } __packed __aligned(8); 1107 1108 #define URTWN_TX_RADIOTAP_PRESENT \ 1109 (1 << IEEE80211_RADIOTAP_FLAGS | \ 1110 1 << IEEE80211_RADIOTAP_CHANNEL) 1111 1112 struct urtwn_softc; 1113 1114 struct urtwn_data { 1115 struct urtwn_softc *sc; 1116 uint8_t *buf; 1117 uint16_t buflen; 1118 struct mbuf *m; 1119 struct ieee80211_node *ni; 1120 STAILQ_ENTRY(urtwn_data) next; 1121 }; 1122 typedef STAILQ_HEAD(, urtwn_data) urtwn_datahead; 1123 1124 struct urtwn_cmdq { 1125 void *arg0; 1126 void *arg1; 1127 void (*func)(void *); 1128 struct ieee80211_key *k; 1129 struct ieee80211_key key; 1130 uint8_t mac[IEEE80211_ADDR_LEN]; 1131 uint8_t wcid; 1132 }; 1133 1134 struct urtwn_fw_info { 1135 const uint8_t *data; 1136 size_t size; 1137 }; 1138 1139 struct urtwn_vap { 1140 struct ieee80211vap vap; 1141 struct ieee80211_beacon_offsets bo; 1142 1143 int (*newstate)(struct ieee80211vap *, 1144 enum ieee80211_state, int); 1145 }; 1146 #define URTWN_VAP(vap) ((struct urtwn_vap *)(vap)) 1147 1148 struct urtwn_host_cmd { 1149 void (*cb)(struct urtwn_softc *, void *); 1150 uint8_t data[256]; 1151 }; 1152 1153 struct urtwn_cmd_newstate { 1154 enum ieee80211_state state; 1155 int arg; 1156 }; 1157 1158 struct urtwn_cmd_key { 1159 struct ieee80211_key key; 1160 uint16_t associd; 1161 }; 1162 1163 enum { 1164 URTWN_BULK_RX, 1165 URTWN_BULK_TX_BE, /* = WME_AC_BE */ 1166 URTWN_BULK_TX_BK, /* = WME_AC_BK */ 1167 URTWN_BULK_TX_VI, /* = WME_AC_VI */ 1168 URTWN_BULK_TX_VO, /* = WME_AC_VI */ 1169 URTWN_N_TRANSFER = 5, 1170 }; 1171 1172 #define URTWN_EP_QUEUES URTWN_BULK_RX 1173 1174 struct urtwn_softc { 1175 struct ifnet *sc_ifp; 1176 device_t sc_dev; 1177 struct usb_device *sc_udev; 1178 1179 int ac2idx[WME_NUM_AC]; 1180 u_int sc_flags; 1181 #define URTWN_FLAG_CCK_HIPWR 0x01 1182 #define URTWN_DETACHED 0x02 1183 1184 u_int chip; 1185 #define URTWN_CHIP_92C 0x01 1186 #define URTWN_CHIP_92C_1T2R 0x02 1187 #define URTWN_CHIP_UMC 0x04 1188 #define URTWN_CHIP_UMC_A_CUT 0x08 1189 #define URTWN_CHIP_88E 0x10 1190 1191 void (*sc_rf_write)(struct urtwn_softc *, 1192 int, uint8_t, uint32_t); 1193 int (*sc_power_on)(struct urtwn_softc *); 1194 int (*sc_dma_init)(struct urtwn_softc *); 1195 1196 uint8_t board_type; 1197 uint8_t regulatory; 1198 uint8_t pa_setting; 1199 int avg_pwdb; 1200 int thcal_state; 1201 int thcal_lctemp; 1202 int ntxchains; 1203 int nrxchains; 1204 int ledlink; 1205 int sc_txtimer; 1206 1207 int fwcur; 1208 struct urtwn_data sc_rx[URTWN_RX_LIST_COUNT]; 1209 urtwn_datahead sc_rx_active; 1210 urtwn_datahead sc_rx_inactive; 1211 struct urtwn_data sc_tx[URTWN_TX_LIST_COUNT]; 1212 urtwn_datahead sc_tx_active; 1213 urtwn_datahead sc_tx_inactive; 1214 urtwn_datahead sc_tx_pending; 1215 1216 const char *fwname; 1217 const struct firmware *fw_fp; 1218 struct urtwn_fw_info fw; 1219 void *fw_virtaddr; 1220 1221 struct r92c_rom rom; 1222 uint8_t r88e_rom[512]; 1223 uint8_t cck_tx_pwr[6]; 1224 uint8_t ht40_tx_pwr[5]; 1225 int8_t bw20_tx_pwr_diff; 1226 int8_t ofdm_tx_pwr_diff; 1227 uint8_t sc_bssid[IEEE80211_ADDR_LEN]; 1228 1229 struct callout sc_watchdog_ch; 1230 struct lock sc_lock; 1231 1232 /* need to be power of 2, otherwise URTWN_CMDQ_GET fails */ 1233 #define URTWN_CMDQ_MAX 16 1234 #define URTWN_CMDQ_MASQ (URTWN_CMDQ_MAX - 1) 1235 struct urtwn_cmdq cmdq[URTWN_CMDQ_MAX]; 1236 struct task cmdq_task; 1237 uint32_t cmdq_store; 1238 uint8_t cmdq_exec; 1239 uint8_t cmdq_run; 1240 uint8_t cmdq_key_set; 1241 #define URTWN_CMDQ_ABORT 0 1242 #define URTWN_CMDQ_GO 1 1243 1244 uint32_t rf_chnlbw[R92C_MAX_CHAINS]; 1245 struct usb_xfer *sc_xfer[URTWN_N_TRANSFER]; 1246 1247 struct urtwn_rx_radiotap_header sc_rxtap; 1248 int sc_rxtap_len; 1249 1250 struct urtwn_tx_radiotap_header sc_txtap; 1251 int sc_txtap_len; 1252 }; 1253 1254 #define URTWN_LOCK(sc) lockmgr(&(sc)->sc_lock, LK_EXCLUSIVE) 1255 #define URTWN_UNLOCK(sc) lockmgr(&(sc)->sc_lock, LK_RELEASE) 1256 #define URTWN_ASSERT_LOCKED(sc) KKASSERT(lockstatus(&(sc)->sc_lock, curthread) != 0) 1257 1258 /* 1259 * MAC initialization values. 1260 */ 1261 static const struct { 1262 uint16_t reg; 1263 uint8_t val; 1264 } rtl8188eu_mac[] = { 1265 { 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a }, 1266 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 }, 1267 { 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 }, 1268 { 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 }, 1269 { 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 }, 1270 { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 }, 1271 { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 }, 1272 { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 }, 1273 { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff }, 1274 { 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 }, 1275 { 0x4d3, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, { 0x502, 0x2f }, 1276 { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, { 0x506, 0x5e }, 1277 { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, { 0x50a, 0x5e }, 1278 { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, { 0x50e, 0x00 }, 1279 { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, { 0x516, 0x0a }, 1280 { 0x525, 0x4f }, { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, 1281 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1282 { 0x620, 0xff }, { 0x621, 0xff }, { 0x622, 0xff }, { 0x623, 0xff }, 1283 { 0x624, 0xff }, { 0x625, 0xff }, { 0x626, 0xff }, { 0x627, 0xff }, 1284 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0a }, { 0x63e, 0x0e }, 1285 { 0x63f, 0x0e }, { 0x640, 0x40 }, { 0x66e, 0x05 }, { 0x700, 0x21 }, 1286 { 0x701, 0x43 }, { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, 1287 { 0x709, 0x43 }, { 0x70a, 0x65 }, { 0x70b, 0x87 } 1288 }, rtl8192cu_mac[] = { 1289 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1290 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1291 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1292 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1293 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1294 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1295 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1296 { 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 }, 1297 { 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff }, 1298 { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1299 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1300 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1301 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1302 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1303 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1304 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x40 }, { 0x547, 0x00 }, 1305 { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, { 0x55a, 0x02 }, 1306 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1307 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0e }, { 0x63e, 0x0a }, 1308 { 0x63f, 0x0e }, { 0x66e, 0x05 }, { 0x700, 0x21 }, { 0x701, 0x43 }, 1309 { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, 1310 { 0x70a, 0x65 }, { 0x70b, 0x87 } 1311 }; 1312 1313 /* 1314 * Baseband initialization values. 1315 */ 1316 struct urtwn_bb_prog { 1317 int count; 1318 const uint16_t *regs; 1319 const uint32_t *vals; 1320 int agccount; 1321 const uint32_t *agcvals; 1322 }; 1323 1324 /* 1325 * RTL8192CU and RTL8192CE-VAU. 1326 */ 1327 static const uint16_t rtl8192ce_bb_regs[] = { 1328 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 1329 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1330 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 1331 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 1332 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 1333 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 1334 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08, 1335 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 1336 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 1337 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 1338 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 1339 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1340 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 1341 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 1342 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 1343 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 1344 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 1345 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 1346 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 1347 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1348 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 1349 }; 1350 1351 static const uint32_t rtl8192ce_bb_vals[] = { 1352 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1353 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1354 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1355 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1356 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1357 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1358 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1359 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1360 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1361 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1362 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1363 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1364 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1365 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1366 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1367 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1368 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1369 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1370 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1371 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1372 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1373 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1374 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1375 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1376 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1377 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1378 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1379 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1380 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1381 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1382 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1383 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1384 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1385 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1386 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1387 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1388 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1389 0x00000000, 0x00000300 1390 }; 1391 1392 static const uint32_t rtl8192ce_agc_vals[] = { 1393 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1394 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1395 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1396 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1397 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1398 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1399 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1400 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1401 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1402 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1403 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1404 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1405 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1406 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1407 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1408 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1409 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1410 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1411 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1412 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1413 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1414 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1415 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1416 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1417 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1418 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1419 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1420 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1421 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1422 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1423 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1424 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1425 }; 1426 1427 static const struct urtwn_bb_prog rtl8192ce_bb_prog = { 1428 NELEM(rtl8192ce_bb_regs), 1429 rtl8192ce_bb_regs, 1430 rtl8192ce_bb_vals, 1431 NELEM(rtl8192ce_agc_vals), 1432 rtl8192ce_agc_vals 1433 }; 1434 1435 /* 1436 * RTL8188CU. 1437 */ 1438 static const uint32_t rtl8192cu_bb_vals[] = { 1439 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1440 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1441 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1442 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1443 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1444 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1445 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1446 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1447 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1448 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1449 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1450 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1451 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1452 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1453 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1454 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1455 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1456 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b, 1457 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100, 1458 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1459 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1460 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1461 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1462 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1463 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1464 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1465 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1466 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1467 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1468 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1469 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1470 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1471 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1472 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1473 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1474 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1475 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1476 0x00000000, 0x00000300 1477 }; 1478 1479 static const struct urtwn_bb_prog rtl8192cu_bb_prog = { 1480 NELEM(rtl8192ce_bb_regs), 1481 rtl8192ce_bb_regs, 1482 rtl8192cu_bb_vals, 1483 NELEM(rtl8192ce_agc_vals), 1484 rtl8192ce_agc_vals 1485 }; 1486 1487 /* 1488 * RTL8188CE-VAU. 1489 */ 1490 static const uint32_t rtl8188ce_bb_vals[] = { 1491 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1492 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1493 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1494 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1495 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1496 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1497 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1498 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1499 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1500 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1501 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1502 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1503 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1504 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1505 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1506 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1507 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1508 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1509 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1510 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1511 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1512 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1513 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1514 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1515 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1516 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1517 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1518 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1519 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1520 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1521 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1522 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1523 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1524 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1525 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1526 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1527 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1528 0x00000000, 0x00000300 1529 }; 1530 1531 static const uint32_t rtl8188ce_agc_vals[] = { 1532 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1533 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1534 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1535 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1536 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1537 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1538 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1539 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1540 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1541 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1542 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1543 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1544 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1545 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1546 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1547 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1548 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1549 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1550 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1551 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1552 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1553 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1554 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1555 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1556 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1557 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1558 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1559 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1560 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1561 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1562 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1563 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1564 }; 1565 1566 static const struct urtwn_bb_prog rtl8188ce_bb_prog = { 1567 NELEM(rtl8192ce_bb_regs), 1568 rtl8192ce_bb_regs, 1569 rtl8188ce_bb_vals, 1570 NELEM(rtl8188ce_agc_vals), 1571 rtl8188ce_agc_vals 1572 }; 1573 1574 static const uint32_t rtl8188cu_bb_vals[] = { 1575 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1576 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1577 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1578 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1579 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1580 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1581 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1582 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1583 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1584 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1585 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1586 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1587 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1588 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1589 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1590 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1591 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1592 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1593 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1594 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1595 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1596 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1597 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1598 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1599 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1600 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1601 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1602 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1603 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1604 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1605 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1606 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1607 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1608 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1609 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1610 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1611 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1612 0x00000000, 0x00000300 1613 }; 1614 1615 static const struct urtwn_bb_prog rtl8188cu_bb_prog = { 1616 NELEM(rtl8192ce_bb_regs), 1617 rtl8192ce_bb_regs, 1618 rtl8188cu_bb_vals, 1619 NELEM(rtl8188ce_agc_vals), 1620 rtl8188ce_agc_vals 1621 }; 1622 1623 /* 1624 * RTL8188EU. 1625 */ 1626 static const uint16_t rtl8188eu_bb_regs[] = { 1627 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 0x81c, 1628 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1629 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1630 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 1631 0x880, 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 1632 0x900, 0x904, 0x908, 0x90c, 0x910, 0x914, 0xa00, 0xa04, 1633 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 0xa20, 0xa24, 1634 0xa28, 0xa2c, 0xa70, 0xa74, 0xa78, 0xa7c, 0xa80, 0xb2c, 1635 0xc00, 0xc04, 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 1636 0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 1637 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 0xc54, 0xc58, 0xc5c, 1638 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 0xc7c, 1639 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 0xc9c, 1640 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1641 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1642 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 1643 0xd10, 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 1644 0xd40, 0xd44, 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 1645 0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 1646 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 0xe1c, 0xe28, 0xe30, 1647 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 0xe4c, 0xe50, 1648 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 0xe74, 1649 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1650 0xed8, 0xedc, 0xee0, 0xee8, 0xeec, 0xf14, 0xf4c, 0xf00 1651 }; 1652 1653 static const uint32_t rtl8188eu_bb_vals[] = { 1654 0x80040000, 0x00000003, 0x0000fc00, 0x0000000a, 0x10001331, 1655 0x020c3d10, 0x02200385, 0x00000000, 0x01000100, 0x00390204, 1656 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1657 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 1658 0x00000000, 0x00000000, 0x569a11a9, 0x01000014, 0x66f60110, 1659 0x061f0649, 0x00000000, 0x27272700, 0x07000760, 0x25004000, 1660 0x00000808, 0x00000000, 0xb0000c1c, 0x00000001, 0x00000000, 1661 0xccc000c0, 0x00000800, 0xfffffffe, 0x40302010, 0x00706050, 1662 0x00000000, 0x00000023, 0x00000000, 0x81121111, 0x00000002, 1663 0x00000201, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e7f120f, 1664 0x9500bb78, 0x1114d028, 0x00881117, 0x89140f00, 0x1a1b0000, 1665 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1666 0x00000900, 0x225b0606, 0x218075b1, 0x80000000, 0x48071d40, 1667 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 0x40000100, 1668 0x08800000, 0x40000100, 0x00000000, 0x00000000, 0x00000000, 1669 0x00000000, 0x69e9ac47, 0x469652af, 0x49795994, 0x0a97971c, 1670 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 0x69553420, 1671 0x43bc0094, 0x00013169, 0x00250492, 0x00000000, 0x7112848b, 1672 0x47c00bff, 0x00000036, 0x2c7f000d, 0x020610db, 0x0000001f, 1673 0x00b91612, 0x390000e4, 0x20f60000, 0x40000100, 0x20200000, 1674 0x00091521, 0x00000000, 0x00121820, 0x00007f7f, 0x00000000, 1675 0x000300a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1676 0x00000000, 0x28000000, 0x00000000, 0x00000000, 0x00000000, 1677 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 0x00766932, 1678 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 0x00000740, 1679 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 0x3333bc43, 1680 0x7a8f5b6f, 0xcc979975, 0x00000000, 0x80608000, 0x00000000, 1681 0x00127353, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1682 0x6437140a, 0x00000000, 0x00000282, 0x30032064, 0x4653de68, 1683 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 0x322c2220, 1684 0x000e3c24, 0x2d2d2d2d, 0x2d2d2d2d, 0x0390272d, 0x2d2d2d2d, 1685 0x2d2d2d2d, 0x2d2d2d2d, 0x2d2d2d2d, 0x00000000, 0x1000dc1f, 1686 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 0x01004800, 1687 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 0x02140102, 1688 0x28160d05, 0x00000008, 0x001b25a4, 0x00c00014, 0x00c00014, 1689 0x01000014, 0x01000014, 0x01000014, 0x01000014, 0x00c00014, 1690 0x01000014, 0x00c00014, 0x00c00014, 0x00c00014, 0x00c00014, 1691 0x00000014, 0x00000014, 0x21555448, 0x01c00014, 0x00000003, 1692 0x00000000, 0x00000300 1693 }; 1694 1695 static const uint32_t rtl8188eu_agc_vals[] = { 1696 0xfb000001, 0xfb010001, 0xfb020001, 0xfb030001, 0xfb040001, 1697 0xfb050001, 0xfa060001, 0xf9070001, 0xf8080001, 0xf7090001, 1698 0xf60a0001, 0xf50b0001, 0xf40c0001, 0xf30d0001, 0xf20e0001, 1699 0xf10f0001, 0xf0100001, 0xef110001, 0xee120001, 0xed130001, 1700 0xec140001, 0xeb150001, 0xea160001, 0xe9170001, 0xe8180001, 1701 0xe7190001, 0xe61a0001, 0xe51b0001, 0xe41c0001, 0xe31d0001, 1702 0xe21e0001, 0xe11f0001, 0x8a200001, 0x89210001, 0x88220001, 1703 0x87230001, 0x86240001, 0x85250001, 0x84260001, 0x83270001, 1704 0x82280001, 0x6b290001, 0x6a2a0001, 0x692b0001, 0x682c0001, 1705 0x672d0001, 0x662e0001, 0x652f0001, 0x64300001, 0x63310001, 1706 0x62320001, 0x61330001, 0x46340001, 0x45350001, 0x44360001, 1707 0x43370001, 0x42380001, 0x41390001, 0x403a0001, 0x403b0001, 1708 0x403c0001, 0x403d0001, 0x403e0001, 0x403f0001, 0xfb400001, 1709 0xfb410001, 0xfb420001, 0xfb430001, 0xfb440001, 0xfb450001, 1710 0xfb460001, 0xfb470001, 0xfb480001, 0xfa490001, 0xf94a0001, 1711 0xf84B0001, 0xf74c0001, 0xf64d0001, 0xf54e0001, 0xf44f0001, 1712 0xf3500001, 0xf2510001, 0xf1520001, 0xf0530001, 0xef540001, 1713 0xee550001, 0xed560001, 0xec570001, 0xeb580001, 0xea590001, 1714 0xe95a0001, 0xe85b0001, 0xe75c0001, 0xe65d0001, 0xe55e0001, 1715 0xe45f0001, 0xe3600001, 0xe2610001, 0xc3620001, 0xc2630001, 1716 0xc1640001, 0x8b650001, 0x8a660001, 0x89670001, 0x88680001, 1717 0x87690001, 0x866a0001, 0x856b0001, 0x846c0001, 0x676d0001, 1718 0x666e0001, 0x656f0001, 0x64700001, 0x63710001, 0x62720001, 1719 0x61730001, 0x60740001, 0x46750001, 0x45760001, 0x44770001, 1720 0x43780001, 0x42790001, 0x417a0001, 0x407b0001, 0x407c0001, 1721 0x407d0001, 0x407e0001, 0x407f0001 1722 }; 1723 1724 static const struct urtwn_bb_prog rtl8188eu_bb_prog = { 1725 NELEM(rtl8188eu_bb_regs), 1726 rtl8188eu_bb_regs, 1727 rtl8188eu_bb_vals, 1728 NELEM(rtl8188eu_agc_vals), 1729 rtl8188eu_agc_vals 1730 }; 1731 1732 /* 1733 * RTL8188RU. 1734 */ 1735 static const uint16_t rtl8188ru_bb_regs[] = { 1736 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 1737 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 1738 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1739 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 1740 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 1741 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 1742 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 1743 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 1744 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 1745 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 1746 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 1747 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 1748 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1749 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 1750 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 1751 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 1752 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 1753 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 1754 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 1755 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 1756 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00 1757 }; 1758 1759 static const uint32_t rtl8188ru_bb_vals[] = { 1760 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001, 1761 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 1762 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000, 1763 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, 1764 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1765 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 1766 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1, 1767 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 1768 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023, 1769 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 1770 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 1771 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00, 1772 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 1773 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000, 1774 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 1775 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 1776 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094, 1777 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d, 1778 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000, 1779 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820, 1780 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000, 1781 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000, 1782 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1783 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302, 1784 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 1785 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 1786 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000, 1787 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 1788 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 1789 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 1790 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 1791 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 1792 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 1793 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 1794 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1795 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 1796 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 1797 0x31555448, 0x00000003, 0x00000000, 0x00000300 1798 }; 1799 1800 static const uint32_t rtl8188ru_agc_vals[] = { 1801 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1802 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, 1803 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001, 1804 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001, 1805 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001, 1806 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001, 1807 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, 1808 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1809 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1810 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1811 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1812 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1813 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1814 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1815 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001, 1816 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001, 1817 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001, 1818 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001, 1819 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, 1820 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001, 1821 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1822 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1823 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1824 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1825 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1826 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1827 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1828 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1829 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1830 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1831 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1832 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1833 }; 1834 1835 static const struct urtwn_bb_prog rtl8188ru_bb_prog = { 1836 NELEM(rtl8188ru_bb_regs), 1837 rtl8188ru_bb_regs, 1838 rtl8188ru_bb_vals, 1839 NELEM(rtl8188ru_agc_vals), 1840 rtl8188ru_agc_vals 1841 }; 1842 1843 /* 1844 * RF initialization values. 1845 */ 1846 struct urtwn_rf_prog { 1847 int count; 1848 const uint8_t *regs; 1849 const uint32_t *vals; 1850 }; 1851 1852 /* 1853 * RTL8192CU and RTL8192CE-VAU. 1854 */ 1855 static const uint8_t rtl8192ce_rf1_regs[] = { 1856 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1857 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 1858 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, 1859 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1860 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 1861 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 1862 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 1863 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1864 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 1865 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 1866 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 1867 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, 1868 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 1869 }; 1870 1871 static const uint32_t rtl8192ce_rf1_vals[] = { 1872 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1873 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1874 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1875 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1876 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1877 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1878 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1879 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1880 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1881 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1882 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1883 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1884 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1885 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1886 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1887 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 1888 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 1889 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1890 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1891 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1892 0x30159 1893 }; 1894 1895 static const uint8_t rtl8192ce_rf2_regs[] = { 1896 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1897 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 1898 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 1899 0x15, 0x15, 0x16, 0x16, 0x16, 0x16 1900 }; 1901 1902 static const uint32_t rtl8192ce_rf2_vals[] = { 1903 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1904 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, 1905 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, 1906 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c, 1907 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, 1908 0xe0330, 0xa0330, 0x60330, 0x20330 1909 }; 1910 1911 static const struct urtwn_rf_prog rtl8192ce_rf_prog[] = { 1912 { 1913 NELEM(rtl8192ce_rf1_regs), 1914 rtl8192ce_rf1_regs, 1915 rtl8192ce_rf1_vals 1916 }, 1917 { 1918 NELEM(rtl8192ce_rf2_regs), 1919 rtl8192ce_rf2_regs, 1920 rtl8192ce_rf2_vals 1921 } 1922 }; 1923 1924 /* 1925 * RTL8188CE-VAU. 1926 */ 1927 static const uint32_t rtl8188ce_rf_vals[] = { 1928 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1929 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1930 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1931 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0, 1932 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1933 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1934 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1935 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1936 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1937 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1938 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1939 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1940 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1941 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1942 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1943 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1944 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1945 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1946 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1947 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1948 0x30159 1949 }; 1950 1951 static const struct urtwn_rf_prog rtl8188ce_rf_prog[] = { 1952 { 1953 NELEM(rtl8192ce_rf1_regs), 1954 rtl8192ce_rf1_regs, 1955 rtl8188ce_rf_vals 1956 } 1957 }; 1958 1959 1960 /* 1961 * RTL8188CU. 1962 */ 1963 static const uint32_t rtl8188cu_rf_vals[] = { 1964 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1965 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1966 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1967 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1968 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1969 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1970 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1971 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1972 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1973 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1974 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1975 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1976 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1977 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1978 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1979 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1980 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1981 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 1982 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1983 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1984 0x30159 1985 }; 1986 1987 static const struct urtwn_rf_prog rtl8188cu_rf_prog[] = { 1988 { 1989 NELEM(rtl8192ce_rf1_regs), 1990 rtl8192ce_rf1_regs, 1991 rtl8188cu_rf_vals 1992 } 1993 }; 1994 1995 /* 1996 * RTL8188EU. 1997 */ 1998 static const uint8_t rtl8188eu_rf_regs[] = { 1999 0x00, 0x08, 0x18, 0x19, 0x1e, 0x1f, 0x2f, 0x3f, 0x42, 0x57, 2000 0x58, 0x67, 0x83, 0xb0, 0xb1, 0xb2, 0xb4, 0xb6, 0xb7, 0xb8, 2001 0xb9, 0xba, 0xbb, 0xbf, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 2002 0xc8, 0xc9, 0xca, 0xdf, 0xef, 0x51, 0x52, 0x53, 0x56, 2003 0x35, 0x35, 0x35, 0x36, 0x36, 0x36, 0x36, 0xb6, 0x18, 0x5a, 2004 0x19, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 2005 0x34, 0x34, 0x00, 0x84, 0x86, 0x87, 0x8e, 0x8f, 0xef, 0x3b, 2006 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 2007 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0xef, 0x00, 0x18, 0xfe, 0xfe, 2008 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 2009 }; 2010 2011 static const uint32_t rtl8188eu_rf_vals[] = { 2012 0x30000, 0x84000, 0x00407, 0x00012, 0x80009, 0x00880, 0x1a060, 2013 0x00000, 0x060c0, 0xd0000, 0xbe180, 0x01552, 0x00000, 0xff8fc, 2014 0x54400, 0xccc19, 0x43003, 0x4953e, 0x1c718, 0x060ff, 0x80001, 2015 0x40000, 0x00400, 0xc0000, 0x02400, 0x00009, 0x40c91, 0x99999, 2016 0x000a3, 0x88820, 0x76c06, 0x00000, 0x80000, 0x00180, 0x001a0, 2017 0x6b27d, 0x7e49d, 0x00073, 0x51ff3, 0x00086, 0x00186, 2018 0x00286, 0x01c25, 0x09c25, 0x11c25, 0x19c25, 0x48538, 0x00c07, 2019 0x4bd00, 0x739d0, 0x0adf3, 0x09df0, 0x08ded, 0x07dea, 0x06de7, 2020 0x054ee, 0x044eb, 0x034e8, 0x0246b, 0x01468, 0x0006d, 0x30159, 2021 0x68200, 0x000ce, 0x48a00, 0x65540, 0x88000, 0x020a0, 0xf02b0, 2022 0xef7b0, 0xd4fb0, 0xcf060, 0xb0090, 0xa0080, 0x90080, 0x8f780, 2023 0x722b0, 0x6f7b0, 0x54fb0, 0x4f060, 0x30090, 0x20080, 0x10080, 2024 0x0f780, 0x000a0, 0x10159, 0x0f407, 0x00000, 0x00000, 0x80003, 2025 0x00000, 0x00000, 0x00001, 0x80000, 0x33e60 2026 }; 2027 2028 static const struct urtwn_rf_prog rtl8188eu_rf_prog[] = { 2029 { 2030 NELEM(rtl8188eu_rf_regs), 2031 rtl8188eu_rf_regs, 2032 rtl8188eu_rf_vals 2033 } 2034 }; 2035 2036 /* 2037 * RTL8188RU. 2038 */ 2039 static const uint32_t rtl8188ru_rf_vals[] = { 2040 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, 2041 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, 2042 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2043 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0, 2044 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2045 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2046 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2047 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2048 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2049 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2050 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2051 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2052 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2053 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2054 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000, 2055 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798, 2056 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, 2057 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 2058 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2059 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2060 0x30159 2061 }; 2062 2063 static const struct urtwn_rf_prog rtl8188ru_rf_prog[] = { 2064 { 2065 NELEM(rtl8192ce_rf1_regs), 2066 rtl8192ce_rf1_regs, 2067 rtl8188ru_rf_vals 2068 } 2069 }; 2070 2071 struct urtwn_txpwr { 2072 uint8_t pwr[3][28]; 2073 }; 2074 2075 struct urtwn_r88e_txpwr { 2076 uint8_t pwr[6][28]; 2077 }; 2078 2079 /* 2080 * Per RF chain/group/rate Tx gain values. 2081 */ 2082 static const struct urtwn_txpwr rtl8192cu_txagc[] = { 2083 { { /* Chain 0. */ 2084 { /* Group 0. */ 2085 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2086 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. */ 2087 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. */ 2088 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. */ 2089 }, 2090 { /* Group 1. */ 2091 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2092 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2093 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2094 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2095 }, 2096 { /* Group 2. */ 2097 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2098 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2099 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2100 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2101 } 2102 } }, 2103 { { /* Chain 1. */ 2104 { /* Group 0. */ 2105 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2106 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2107 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2108 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2109 }, 2110 { /* Group 1. */ 2111 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2112 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2113 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2114 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2115 }, 2116 { /* Group 2. */ 2117 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2118 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2119 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2120 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2121 } 2122 } } 2123 }; 2124 2125 static const struct urtwn_txpwr rtl8188ru_txagc[] = { 2126 { { /* Chain 0. */ 2127 { /* Group 0. */ 2128 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2129 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. */ 2130 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. */ 2131 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. */ 2132 }, 2133 { /* Group 1. */ 2134 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2136 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2137 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2138 }, 2139 { /* Group 2. */ 2140 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2141 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2142 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2143 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2144 } 2145 } } 2146 }; 2147 2148 static const struct urtwn_r88e_txpwr rtl8188eu_txagc[] = { 2149 { { /* Chain 0. */ 2150 { /* Group 0. */ 2151 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2152 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2153 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2154 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2155 }, 2156 { /* Group 1. */ 2157 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2158 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2159 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2160 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2161 }, 2162 { /* Group 2. */ 2163 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2164 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2165 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2166 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2167 }, 2168 { /* Group 3. */ 2169 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2170 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2171 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2172 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2173 }, 2174 { /* Group 4. */ 2175 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2176 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2177 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2178 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2179 }, 2180 { /* Group 5. */ 2181 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2183 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2185 } 2186 } } 2187 }; 2188