1 /****************************************************************************** 2 * 3 * Module Name: dmtbinfo1 - Table info for non-AML tables 4 * 5 *****************************************************************************/ 6 7 /****************************************************************************** 8 * 9 * 1. Copyright Notice 10 * 11 * Some or all of this work - Copyright (c) 1999 - 2021, Intel Corp. 12 * All rights reserved. 13 * 14 * 2. License 15 * 16 * 2.1. This is your license from Intel Corp. under its intellectual property 17 * rights. You may have additional license terms from the party that provided 18 * you this software, covering your right to use that party's intellectual 19 * property rights. 20 * 21 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a 22 * copy of the source code appearing in this file ("Covered Code") an 23 * irrevocable, perpetual, worldwide license under Intel's copyrights in the 24 * base code distributed originally by Intel ("Original Intel Code") to copy, 25 * make derivatives, distribute, use and display any portion of the Covered 26 * Code in any form, with the right to sublicense such rights; and 27 * 28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 29 * license (with the right to sublicense), under only those claims of Intel 30 * patents that are infringed by the Original Intel Code, to make, use, sell, 31 * offer to sell, and import the Covered Code and derivative works thereof 32 * solely to the minimum extent necessary to exercise the above copyright 33 * license, and in no event shall the patent license extend to any additions 34 * to or modifications of the Original Intel Code. No other license or right 35 * is granted directly or by implication, estoppel or otherwise; 36 * 37 * The above copyright and patent license is granted only if the following 38 * conditions are met: 39 * 40 * 3. Conditions 41 * 42 * 3.1. Redistribution of Source with Rights to Further Distribute Source. 43 * Redistribution of source code of any substantial portion of the Covered 44 * Code or modification with rights to further distribute source must include 45 * the above Copyright Notice, the above License, this list of Conditions, 46 * and the following Disclaimer and Export Compliance provision. In addition, 47 * Licensee must cause all Covered Code to which Licensee contributes to 48 * contain a file documenting the changes Licensee made to create that Covered 49 * Code and the date of any change. Licensee must include in that file the 50 * documentation of any changes made by any predecessor Licensee. Licensee 51 * must include a prominent statement that the modification is derived, 52 * directly or indirectly, from Original Intel Code. 53 * 54 * 3.2. Redistribution of Source with no Rights to Further Distribute Source. 55 * Redistribution of source code of any substantial portion of the Covered 56 * Code or modification without rights to further distribute source must 57 * include the following Disclaimer and Export Compliance provision in the 58 * documentation and/or other materials provided with distribution. In 59 * addition, Licensee may not authorize further sublicense of source of any 60 * portion of the Covered Code, and must include terms to the effect that the 61 * license from Licensee to its licensee is limited to the intellectual 62 * property embodied in the software Licensee provides to its licensee, and 63 * not to intellectual property embodied in modifications its licensee may 64 * make. 65 * 66 * 3.3. Redistribution of Executable. Redistribution in executable form of any 67 * substantial portion of the Covered Code or modification must reproduce the 68 * above Copyright Notice, and the following Disclaimer and Export Compliance 69 * provision in the documentation and/or other materials provided with the 70 * distribution. 71 * 72 * 3.4. Intel retains all right, title, and interest in and to the Original 73 * Intel Code. 74 * 75 * 3.5. Neither the name Intel nor any other trademark owned or controlled by 76 * Intel shall be used in advertising or otherwise to promote the sale, use or 77 * other dealings in products derived from or relating to the Covered Code 78 * without prior written authorization from Intel. 79 * 80 * 4. Disclaimer and Export Compliance 81 * 82 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED 83 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE 84 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, 85 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY 86 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY 87 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A 88 * PARTICULAR PURPOSE. 89 * 90 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES 91 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR 92 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, 93 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY 94 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL 95 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS 96 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY 97 * LIMITED REMEDY. 98 * 99 * 4.3. Licensee shall not export, either directly or indirectly, any of this 100 * software or system incorporating such software without first obtaining any 101 * required license or other approval from the U. S. Department of Commerce or 102 * any other agency or department of the United States Government. In the 103 * event Licensee exports any such software from the United States or 104 * re-exports any such software from a foreign destination, Licensee shall 105 * ensure that the distribution and export/re-export of the software is in 106 * compliance with all laws, regulations, orders, or other restrictions of the 107 * U.S. Export Administration Regulations. Licensee agrees that neither it nor 108 * any of its subsidiaries will export/re-export any technical data, process, 109 * software, or service, directly or indirectly, to any country for which the 110 * United States government or any agency thereof requires an export license, 111 * other governmental approval, or letter of assurance, without first obtaining 112 * such license, approval or letter. 113 * 114 ***************************************************************************** 115 * 116 * Alternatively, you may choose to be licensed under the terms of the 117 * following license: 118 * 119 * Redistribution and use in source and binary forms, with or without 120 * modification, are permitted provided that the following conditions 121 * are met: 122 * 1. Redistributions of source code must retain the above copyright 123 * notice, this list of conditions, and the following disclaimer, 124 * without modification. 125 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 126 * substantially similar to the "NO WARRANTY" disclaimer below 127 * ("Disclaimer") and any redistribution must be conditioned upon 128 * including a substantially similar Disclaimer requirement for further 129 * binary redistribution. 130 * 3. Neither the names of the above-listed copyright holders nor the names 131 * of any contributors may be used to endorse or promote products derived 132 * from this software without specific prior written permission. 133 * 134 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 135 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 136 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 137 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 138 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 139 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 140 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 141 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 142 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 143 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 144 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 145 * 146 * Alternatively, you may choose to be licensed under the terms of the 147 * GNU General Public License ("GPL") version 2 as published by the Free 148 * Software Foundation. 149 * 150 *****************************************************************************/ 151 152 #include "acpi.h" 153 #include "accommon.h" 154 #include "acdisasm.h" 155 #include "actbinfo.h" 156 157 /* This module used for application-level code only */ 158 159 #define _COMPONENT ACPI_CA_DISASSEMBLER 160 ACPI_MODULE_NAME ("dmtbinfo1") 161 162 /* 163 * How to add a new table: 164 * 165 * - Add the C table definition to the actbl1.h or actbl2.h header. 166 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below. 167 * - Define the table in this file (for the disassembler). If any 168 * new data types are required (ACPI_DMT_*), see below. 169 * - Add an external declaration for the new table definition (AcpiDmTableInfo*) 170 * in acdisam.h 171 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData) 172 * If a simple table (with no subtables), no disassembly code is needed. 173 * Otherwise, create the AcpiDmDump* function for to disassemble the table 174 * and add it to the dmtbdump.c file. 175 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h 176 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c 177 * - Create a template for the new table 178 * - Add data table compiler support 179 * 180 * How to add a new data type (ACPI_DMT_*): 181 * 182 * - Add new type at the end of the ACPI_DMT list in acdisasm.h 183 * - Add length and implementation cases in dmtable.c (disassembler) 184 * - Add type and length cases in dtutils.c (DT compiler) 185 */ 186 187 /* 188 * ACPI Table Information, used to dump formatted ACPI tables 189 * 190 * Each entry is of the form: <Field Type, Field Offset, Field Name> 191 */ 192 193 194 /******************************************************************************* 195 * 196 * AEST - ARM Error Source table. Conforms to: 197 * ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document Sep 2020 198 * 199 ******************************************************************************/ 200 201 /* Common Subtable header (one per Subtable) */ 202 203 ACPI_DMTABLE_INFO AcpiDmTableInfoAestHdr[] = 204 { 205 {ACPI_DMT_AEST, ACPI_AESTH_OFFSET (Type), "Subtable Type", 0}, 206 {ACPI_DMT_UINT16, ACPI_AESTH_OFFSET (Length), "Length", DT_LENGTH}, 207 {ACPI_DMT_UINT8, ACPI_AESTH_OFFSET (Reserved), "Reserved", 0}, 208 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeSpecificOffset), "Node Specific Offset", 0}, 209 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeInterfaceOffset), "Node Interface Offset", 0}, 210 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeInterruptOffset), "Node Interrupt Array Offset", 0}, 211 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeInterruptCount), "Node Interrupt Array Count", 0}, 212 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (TimestampRate), "Timestamp Rate", 0}, 213 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (Reserved1), "Reserved", 0}, 214 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (ErrorInjectionRate), "Error Injection Rate", 0}, 215 ACPI_DMT_TERMINATOR 216 }; 217 218 /* 219 * AEST subtables (nodes) 220 */ 221 222 /* 0: Processor Error */ 223 224 ACPI_DMTABLE_INFO AcpiDmTableInfoAestProcError[] = 225 { 226 {ACPI_DMT_UINT32, ACPI_AEST0_OFFSET (ProcessorId), "Processor ID", 0}, 227 {ACPI_DMT_AEST_RES, ACPI_AEST0_OFFSET (ResourceType), "Resource Type", 0}, 228 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Reserved), "Reserved", 0}, 229 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Flags), "Flags (decoded Below)", 0}, 230 {ACPI_DMT_FLAG0, ACPI_AEST0_FLAG_OFFSET (Flags, 0), "Global", 0}, 231 {ACPI_DMT_FLAG1, ACPI_AEST0_FLAG_OFFSET (Flags, 0), "Shared", 0}, 232 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Revision), "Revision", 0}, 233 {ACPI_DMT_UINT64, ACPI_AEST0_OFFSET (ProcessorAffinity), "Processor Affinity Structure", 0}, 234 ACPI_DMT_TERMINATOR 235 }; 236 237 /* 0RT: Processor Cache Resource */ 238 239 ACPI_DMTABLE_INFO AcpiDmTableInfoAestCacheRsrc[] = 240 { 241 {ACPI_DMT_UINT32, ACPI_AEST0A_OFFSET (CacheReference), "Cache Reference", 0}, 242 {ACPI_DMT_UINT32, ACPI_AEST0A_OFFSET (Reserved), "Reserved", 0}, 243 ACPI_DMT_TERMINATOR 244 }; 245 246 /* 1RT: ProcessorTLB Resource */ 247 248 ACPI_DMTABLE_INFO AcpiDmTableInfoAestTlbRsrc[] = 249 { 250 {ACPI_DMT_UINT32, ACPI_AEST0B_OFFSET (TlbLevel), "TLB Level", 0}, 251 {ACPI_DMT_UINT32, ACPI_AEST0B_OFFSET (Reserved), "Reserved", 0}, 252 ACPI_DMT_TERMINATOR 253 }; 254 255 /* 2RT: Processor Generic Resource */ 256 257 ACPI_DMTABLE_INFO AcpiDmTableInfoAestGenRsrc[] = 258 { 259 {ACPI_DMT_RAW_BUFFER, 0, "Resource", 0}, 260 ACPI_DMT_TERMINATOR 261 }; 262 263 /* 1: Memory Error */ 264 265 ACPI_DMTABLE_INFO AcpiDmTableInfoAestMemError[] = 266 { 267 {ACPI_DMT_UINT32, ACPI_AEST1_OFFSET (SratProximityDomain), "Srat Proximity Domain", 0}, 268 ACPI_DMT_TERMINATOR 269 }; 270 271 /* 2: Smmu Error */ 272 273 ACPI_DMTABLE_INFO AcpiDmTableInfoAestSmmuError[] = 274 { 275 {ACPI_DMT_UINT32, ACPI_AEST2_OFFSET (IortNodeReference), "Iort Node Reference", 0}, 276 {ACPI_DMT_UINT32, ACPI_AEST2_OFFSET (SubcomponentReference), "Subcomponent Reference", 0}, 277 ACPI_DMT_TERMINATOR 278 }; 279 280 /* 3: Vendor Defined */ 281 282 ACPI_DMTABLE_INFO AcpiDmTableInfoAestVendorError[] = 283 { 284 {ACPI_DMT_UINT32, ACPI_AEST3_OFFSET (AcpiHid), "ACPI HID", 0}, 285 {ACPI_DMT_UINT32, ACPI_AEST3_OFFSET (AcpiUid), "ACPI UID", 0}, 286 {ACPI_DMT_BUF16, ACPI_AEST3_OFFSET (VendorSpecificData), "Vendor Specific Data", 0}, 287 ACPI_DMT_TERMINATOR 288 }; 289 290 /* 4: Gic Error */ 291 292 ACPI_DMTABLE_INFO AcpiDmTableInfoAestGicError[] = 293 { 294 {ACPI_DMT_AEST_GIC, ACPI_AEST4_OFFSET (InterfaceType), "GIC Interface Type", 0}, 295 {ACPI_DMT_UINT32, ACPI_AEST4_OFFSET (InstanceId), "Instance ID", 0}, 296 ACPI_DMT_TERMINATOR 297 }; 298 299 /* AestXface: Node Interface Structure */ 300 301 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface[] = 302 { 303 {ACPI_DMT_AEST_XFACE, ACPI_AEST0D_OFFSET (Type), "Interface Type", 0}, 304 {ACPI_DMT_UINT24, ACPI_AEST0D_OFFSET (Reserved[0]), "Reserved", 0}, 305 {ACPI_DMT_UINT32, ACPI_AEST0D_OFFSET (Flags), "Flags (decoded below)", 0}, 306 {ACPI_DMT_FLAG0, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Shared Interface", 0}, 307 {ACPI_DMT_FLAG1, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Clear MISCx Registers", 0}, 308 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (Address), "Address", 0}, 309 {ACPI_DMT_UINT32, ACPI_AEST0D_OFFSET (ErrorRecordIndex), "Error Record Index", 0}, 310 {ACPI_DMT_UINT32, ACPI_AEST0D_OFFSET (ErrorRecordCount), "Error Record Count", 0}, 311 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (ErrorRecordImplemented),"Error Record Implemented", 0}, 312 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (ErrorStatusReporting), "Error Status Reporting", 0}, 313 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (AddressingMode), "Addressing Mode", 0}, 314 ACPI_DMT_TERMINATOR 315 }; 316 317 /* AestXrupt: Node Interrupt Structure */ 318 319 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXrupt[] = 320 { 321 {ACPI_DMT_AEST_XRUPT, ACPI_AEST0E_OFFSET (Type), "Interrupt Type", 0}, 322 {ACPI_DMT_UINT16, ACPI_AEST0E_OFFSET (Reserved), "Reserved", 0}, 323 {ACPI_DMT_UINT8, ACPI_AEST0E_OFFSET (Flags), "Flags (decoded below)", 0}, 324 {ACPI_DMT_FLAG0, ACPI_AEST0E_FLAG_OFFSET (Flags, 0), "Level Triggered", 0}, 325 {ACPI_DMT_UINT32, ACPI_AEST0E_OFFSET (Gsiv), "Gsiv", 0}, 326 {ACPI_DMT_UINT8, ACPI_AEST0E_OFFSET (IortId), "IortId", 0}, 327 {ACPI_DMT_UINT24, ACPI_AEST0E_OFFSET (Reserved1[0]), "Reserved", 0}, 328 ACPI_DMT_TERMINATOR 329 }; 330 331 332 /******************************************************************************* 333 * 334 * ASF - Alert Standard Format table (Signature "ASF!") 335 * 336 ******************************************************************************/ 337 338 /* Common Subtable header (one per Subtable) */ 339 340 ACPI_DMTABLE_INFO AcpiDmTableInfoAsfHdr[] = 341 { 342 {ACPI_DMT_ASF, ACPI_ASF0_OFFSET (Header.Type), "Subtable Type", 0}, 343 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Header.Reserved), "Reserved", 0}, 344 {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (Header.Length), "Length", DT_LENGTH}, 345 ACPI_DMT_TERMINATOR 346 }; 347 348 /* 0: ASF Information */ 349 350 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf0[] = 351 { 352 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinResetValue), "Minimum Reset Value", 0}, 353 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinPollInterval), "Minimum Polling Interval", 0}, 354 {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (SystemId), "System ID", 0}, 355 {ACPI_DMT_UINT32, ACPI_ASF0_OFFSET (MfgId), "Manufacturer ID", 0}, 356 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Flags), "Flags", 0}, 357 {ACPI_DMT_UINT24, ACPI_ASF0_OFFSET (Reserved2[0]), "Reserved", 0}, 358 ACPI_DMT_TERMINATOR 359 }; 360 361 /* 1: ASF Alerts */ 362 363 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1[] = 364 { 365 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (AssertMask), "AssertMask", 0}, 366 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DeassertMask), "DeassertMask", 0}, 367 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (Alerts), "Alert Count", 0}, 368 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DataLength), "Alert Data Length", 0}, 369 ACPI_DMT_TERMINATOR 370 }; 371 372 /* 1a: ASF Alert data */ 373 374 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1a[] = 375 { 376 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Address), "Address", 0}, 377 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Command), "Command", 0}, 378 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Mask), "Mask", 0}, 379 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Value), "Value", 0}, 380 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorType), "SensorType", 0}, 381 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Type), "Type", 0}, 382 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Offset), "Offset", 0}, 383 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SourceType), "SourceType", 0}, 384 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Severity), "Severity", 0}, 385 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorNumber), "SensorNumber", 0}, 386 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Entity), "Entity", 0}, 387 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Instance), "Instance", 0}, 388 ACPI_DMT_TERMINATOR 389 }; 390 391 /* 2: ASF Remote Control */ 392 393 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2[] = 394 { 395 {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (Controls), "Control Count", 0}, 396 {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (DataLength), "Control Data Length", 0}, 397 {ACPI_DMT_UINT16, ACPI_ASF2_OFFSET (Reserved2), "Reserved", 0}, 398 ACPI_DMT_TERMINATOR 399 }; 400 401 /* 2a: ASF Control data */ 402 403 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2a[] = 404 { 405 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Function), "Function", 0}, 406 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Address), "Address", 0}, 407 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Command), "Command", 0}, 408 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Value), "Value", 0}, 409 ACPI_DMT_TERMINATOR 410 }; 411 412 /* 3: ASF RMCP Boot Options */ 413 414 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf3[] = 415 { 416 {ACPI_DMT_BUF7, ACPI_ASF3_OFFSET (Capabilities[0]), "Capabilities", 0}, 417 {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (CompletionCode), "Completion Code", 0}, 418 {ACPI_DMT_UINT32, ACPI_ASF3_OFFSET (EnterpriseId), "Enterprise ID", 0}, 419 {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (Command), "Command", 0}, 420 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (Parameter), "Parameter", 0}, 421 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (BootOptions), "Boot Options", 0}, 422 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (OemParameters), "Oem Parameters", 0}, 423 ACPI_DMT_TERMINATOR 424 }; 425 426 /* 4: ASF Address */ 427 428 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf4[] = 429 { 430 {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (EpromAddress), "Eprom Address", 0}, 431 {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (Devices), "Device Count", DT_COUNT}, 432 ACPI_DMT_TERMINATOR 433 }; 434 435 436 /******************************************************************************* 437 * 438 * BDAT - BIOS Data ACPI Table 439 * 440 ******************************************************************************/ 441 442 ACPI_DMTABLE_INFO AcpiDmTableInfoBdat[] = 443 { 444 {ACPI_DMT_GAS, ACPI_BDAT_OFFSET (Gas), "BDAT Generic Address", 0}, 445 ACPI_DMT_TERMINATOR 446 }; 447 448 449 /******************************************************************************* 450 * 451 * BERT - Boot Error Record table 452 * 453 ******************************************************************************/ 454 455 ACPI_DMTABLE_INFO AcpiDmTableInfoBert[] = 456 { 457 {ACPI_DMT_UINT32, ACPI_BERT_OFFSET (RegionLength), "Boot Error Region Length", 0}, 458 {ACPI_DMT_UINT64, ACPI_BERT_OFFSET (Address), "Boot Error Region Address", 0}, 459 ACPI_DMT_TERMINATOR 460 }; 461 462 463 /******************************************************************************* 464 * 465 * BGRT - Boot Graphics Resource Table (ACPI 5.0) 466 * 467 ******************************************************************************/ 468 469 ACPI_DMTABLE_INFO AcpiDmTableInfoBgrt[] = 470 { 471 {ACPI_DMT_UINT16, ACPI_BGRT_OFFSET (Version), "Version", 0}, 472 {ACPI_DMT_UINT8, ACPI_BGRT_OFFSET (Status), "Status (decoded below)", DT_FLAG}, 473 {ACPI_DMT_FLAG0, ACPI_BGRT_FLAG_OFFSET (Status, 0), "Displayed", 0}, 474 {ACPI_DMT_FLAGS1, ACPI_BGRT_FLAG_OFFSET (Status, 0), "Orientation Offset", 0}, 475 476 {ACPI_DMT_UINT8, ACPI_BGRT_OFFSET (ImageType), "Image Type", 0}, 477 {ACPI_DMT_UINT64, ACPI_BGRT_OFFSET (ImageAddress), "Image Address", 0}, 478 {ACPI_DMT_UINT32, ACPI_BGRT_OFFSET (ImageOffsetX), "Image OffsetX", 0}, 479 {ACPI_DMT_UINT32, ACPI_BGRT_OFFSET (ImageOffsetY), "Image OffsetY", 0}, 480 ACPI_DMT_TERMINATOR 481 }; 482 483 484 /******************************************************************************* 485 * 486 * BOOT - Simple Boot Flag Table 487 * 488 ******************************************************************************/ 489 490 ACPI_DMTABLE_INFO AcpiDmTableInfoBoot[] = 491 { 492 {ACPI_DMT_UINT8, ACPI_BOOT_OFFSET (CmosIndex), "Boot Register Index", 0}, 493 {ACPI_DMT_UINT24, ACPI_BOOT_OFFSET (Reserved[0]), "Reserved", 0}, 494 ACPI_DMT_TERMINATOR 495 }; 496 497 498 /******************************************************************************* 499 * 500 * CEDT - CXL Early Discovery Table 501 * 502 ******************************************************************************/ 503 504 ACPI_DMTABLE_INFO AcpiDmTableInfoCedtHdr[] = 505 { 506 {ACPI_DMT_CEDT, ACPI_CEDT_OFFSET (Type), "Subtable Type", 0}, 507 {ACPI_DMT_UINT8, ACPI_CEDT_OFFSET (Reserved), "Reserved", 0}, 508 {ACPI_DMT_UINT16, ACPI_CEDT_OFFSET (Length), "Length", DT_LENGTH}, 509 ACPI_DMT_TERMINATOR 510 }; 511 512 /* 0: CXL Host Bridge Structure */ 513 514 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt0[] = 515 { 516 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (Uid), "Associated host bridge", 0}, 517 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (CxlVersion), "Specification version", 0}, 518 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (Reserved), "Reserved", 0}, 519 {ACPI_DMT_UINT64, ACPI_CEDT0_OFFSET (Base), "Register base", 0}, 520 {ACPI_DMT_UINT64, ACPI_CEDT0_OFFSET (Length), "Register length", 0}, 521 ACPI_DMT_TERMINATOR 522 }; 523 524 525 /******************************************************************************* 526 * 527 * CPEP - Corrected Platform Error Polling table 528 * 529 ******************************************************************************/ 530 531 ACPI_DMTABLE_INFO AcpiDmTableInfoCpep[] = 532 { 533 {ACPI_DMT_UINT64, ACPI_CPEP_OFFSET (Reserved), "Reserved", 0}, 534 ACPI_DMT_TERMINATOR 535 }; 536 537 ACPI_DMTABLE_INFO AcpiDmTableInfoCpep0[] = 538 { 539 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Header.Type), "Subtable Type", 0}, 540 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Header.Length), "Length", DT_LENGTH}, 541 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Id), "Processor ID", 0}, 542 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Eid), "Processor EID", 0}, 543 {ACPI_DMT_UINT32, ACPI_CPEP0_OFFSET (Interval), "Polling Interval", 0}, 544 ACPI_DMT_TERMINATOR 545 }; 546 547 548 /******************************************************************************* 549 * 550 * CSRT - Core System Resource Table 551 * 552 ******************************************************************************/ 553 554 /* Main table consists only of the standard ACPI table header */ 555 556 /* Resource Group subtable */ 557 558 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt0[] = 559 { 560 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (Length), "Length", DT_LENGTH}, 561 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (VendorId), "Vendor ID", 0}, 562 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (SubvendorId), "Subvendor ID", 0}, 563 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (DeviceId), "Device ID", 0}, 564 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (SubdeviceId), "Subdevice ID", 0}, 565 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (Revision), "Revision", 0}, 566 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (Reserved), "Reserved", 0}, 567 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (SharedInfoLength), "Shared Info Length", 0}, 568 ACPI_DMT_TERMINATOR 569 }; 570 571 /* Shared Info subtable */ 572 573 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt1[] = 574 { 575 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (MajorVersion), "Major Version", 0}, 576 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (MinorVersion), "Minor Version", 0}, 577 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MmioBaseLow), "MMIO Base Address Low", 0}, 578 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MmioBaseHigh), "MMIO Base Address High", 0}, 579 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (GsiInterrupt), "GSI Interrupt", 0}, 580 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (InterruptPolarity), "Interrupt Polarity", 0}, 581 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (InterruptMode), "Interrupt Mode", 0}, 582 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (NumChannels), "Num Channels", 0}, 583 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (DmaAddressWidth), "DMA Address Width", 0}, 584 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (BaseRequestLine), "Base Request Line", 0}, 585 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (NumHandshakeSignals), "Num Handshake Signals", 0}, 586 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MaxBlockSize), "Max Block Size", 0}, 587 ACPI_DMT_TERMINATOR 588 }; 589 590 /* Resource Descriptor subtable */ 591 592 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt2[] = 593 { 594 {ACPI_DMT_UINT32, ACPI_CSRT2_OFFSET (Length), "Length", DT_LENGTH}, 595 {ACPI_DMT_UINT16, ACPI_CSRT2_OFFSET (Type), "Type", 0}, 596 {ACPI_DMT_UINT16, ACPI_CSRT2_OFFSET (Subtype), "Subtype", 0}, 597 {ACPI_DMT_UINT32, ACPI_CSRT2_OFFSET (Uid), "UID", 0}, 598 ACPI_DMT_TERMINATOR 599 }; 600 601 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt2a[] = 602 { 603 {ACPI_DMT_RAW_BUFFER, 0, "ResourceInfo", DT_OPTIONAL}, 604 ACPI_DMT_TERMINATOR 605 }; 606 607 608 /******************************************************************************* 609 * 610 * DBG2 - Debug Port Table 2 611 * 612 ******************************************************************************/ 613 614 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2[] = 615 { 616 {ACPI_DMT_UINT32, ACPI_DBG2_OFFSET (InfoOffset), "Info Offset", 0}, 617 {ACPI_DMT_UINT32, ACPI_DBG2_OFFSET (InfoCount), "Info Count", 0}, 618 ACPI_DMT_TERMINATOR 619 }; 620 621 /* Debug Device Information Subtable */ 622 623 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Device[] = 624 { 625 {ACPI_DMT_UINT8, ACPI_DBG20_OFFSET (Revision), "Revision", 0}, 626 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (Length), "Length", DT_LENGTH}, 627 {ACPI_DMT_UINT8, ACPI_DBG20_OFFSET (RegisterCount), "Register Count", 0}, 628 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (NamepathLength), "Namepath Length", 0}, 629 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (NamepathOffset), "Namepath Offset", 0}, 630 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (OemDataLength), "OEM Data Length", DT_DESCRIBES_OPTIONAL}, 631 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (OemDataOffset), "OEM Data Offset", DT_DESCRIBES_OPTIONAL}, 632 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (PortType), "Port Type", 0}, 633 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (PortSubtype), "Port Subtype", 0}, 634 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (Reserved), "Reserved", 0}, 635 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (BaseAddressOffset), "Base Address Offset", 0}, 636 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (AddressSizeOffset), "Address Size Offset", 0}, 637 ACPI_DMT_TERMINATOR 638 }; 639 640 /* Variable-length data for the subtable */ 641 642 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Addr[] = 643 { 644 {ACPI_DMT_GAS, 0, "Base Address Register", 0}, 645 ACPI_DMT_TERMINATOR 646 }; 647 648 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Size[] = 649 { 650 {ACPI_DMT_UINT32, 0, "Address Size", 0}, 651 ACPI_DMT_TERMINATOR 652 }; 653 654 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Name[] = 655 { 656 {ACPI_DMT_STRING, 0, "Namepath", 0}, 657 ACPI_DMT_TERMINATOR 658 }; 659 660 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2OemData[] = 661 { 662 {ACPI_DMT_RAW_BUFFER, 0, "OEM Data", DT_OPTIONAL}, 663 ACPI_DMT_TERMINATOR 664 }; 665 666 667 /******************************************************************************* 668 * 669 * DBGP - Debug Port 670 * 671 ******************************************************************************/ 672 673 ACPI_DMTABLE_INFO AcpiDmTableInfoDbgp[] = 674 { 675 {ACPI_DMT_UINT8, ACPI_DBGP_OFFSET (Type), "Interface Type", 0}, 676 {ACPI_DMT_UINT24, ACPI_DBGP_OFFSET (Reserved[0]), "Reserved", 0}, 677 {ACPI_DMT_GAS, ACPI_DBGP_OFFSET (DebugPort), "Debug Port Register", 0}, 678 ACPI_DMT_TERMINATOR 679 }; 680 681 682 /******************************************************************************* 683 * 684 * DMAR - DMA Remapping table 685 * 686 ******************************************************************************/ 687 688 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar[] = 689 { 690 {ACPI_DMT_UINT8, ACPI_DMAR_OFFSET (Width), "Host Address Width", 0}, 691 {ACPI_DMT_UINT8, ACPI_DMAR_OFFSET (Flags), "Flags", 0}, 692 {ACPI_DMT_BUF10, ACPI_DMAR_OFFSET (Reserved[0]), "Reserved", 0}, 693 ACPI_DMT_TERMINATOR 694 }; 695 696 /* Common Subtable header (one per Subtable) */ 697 698 ACPI_DMTABLE_INFO AcpiDmTableInfoDmarHdr[] = 699 { 700 {ACPI_DMT_DMAR, ACPI_DMAR0_OFFSET (Header.Type), "Subtable Type", 0}, 701 {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Header.Length), "Length", DT_LENGTH}, 702 ACPI_DMT_TERMINATOR 703 }; 704 705 /* Common device scope entry */ 706 707 ACPI_DMTABLE_INFO AcpiDmTableInfoDmarScope[] = 708 { 709 {ACPI_DMT_DMAR_SCOPE, ACPI_DMARS_OFFSET (EntryType), "Device Scope Type", 0}, 710 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Length), "Entry Length", DT_LENGTH}, 711 {ACPI_DMT_UINT16, ACPI_DMARS_OFFSET (Reserved), "Reserved", 0}, 712 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (EnumerationId), "Enumeration ID", 0}, 713 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Bus), "PCI Bus Number", 0}, 714 ACPI_DMT_TERMINATOR 715 }; 716 717 /* DMAR Subtables */ 718 719 /* 0: Hardware Unit Definition */ 720 721 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar0[] = 722 { 723 {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Flags), "Flags", 0}, 724 {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Reserved), "Reserved", 0}, 725 {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Segment), "PCI Segment Number", 0}, 726 {ACPI_DMT_UINT64, ACPI_DMAR0_OFFSET (Address), "Register Base Address", 0}, 727 ACPI_DMT_TERMINATOR 728 }; 729 730 /* 1: Reserved Memory Definition */ 731 732 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar1[] = 733 { 734 {ACPI_DMT_UINT16, ACPI_DMAR1_OFFSET (Reserved), "Reserved", 0}, 735 {ACPI_DMT_UINT16, ACPI_DMAR1_OFFSET (Segment), "PCI Segment Number", 0}, 736 {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (BaseAddress), "Base Address", 0}, 737 {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (EndAddress), "End Address (limit)", 0}, 738 ACPI_DMT_TERMINATOR 739 }; 740 741 /* 2: Root Port ATS Capability Definition */ 742 743 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar2[] = 744 { 745 {ACPI_DMT_UINT8, ACPI_DMAR2_OFFSET (Flags), "Flags", 0}, 746 {ACPI_DMT_UINT8, ACPI_DMAR2_OFFSET (Reserved), "Reserved", 0}, 747 {ACPI_DMT_UINT16, ACPI_DMAR2_OFFSET (Segment), "PCI Segment Number", 0}, 748 ACPI_DMT_TERMINATOR 749 }; 750 751 /* 3: Remapping Hardware Static Affinity Structure */ 752 753 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar3[] = 754 { 755 {ACPI_DMT_UINT32, ACPI_DMAR3_OFFSET (Reserved), "Reserved", 0}, 756 {ACPI_DMT_UINT64, ACPI_DMAR3_OFFSET (BaseAddress), "Base Address", 0}, 757 {ACPI_DMT_UINT32, ACPI_DMAR3_OFFSET (ProximityDomain), "Proximity Domain", 0}, 758 ACPI_DMT_TERMINATOR 759 }; 760 761 /* 4: ACPI Namespace Device Declaration Structure */ 762 763 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar4[] = 764 { 765 {ACPI_DMT_UINT24, ACPI_DMAR4_OFFSET (Reserved[0]), "Reserved", 0}, 766 {ACPI_DMT_UINT8, ACPI_DMAR4_OFFSET (DeviceNumber), "Device Number", 0}, 767 {ACPI_DMT_STRING, ACPI_DMAR4_OFFSET (DeviceName[0]), "Device Name", 0}, 768 ACPI_DMT_TERMINATOR 769 }; 770 771 772 /******************************************************************************* 773 * 774 * DRTM - Dynamic Root of Trust for Measurement table 775 * 776 ******************************************************************************/ 777 778 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm[] = 779 { 780 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryBaseAddress), "Entry Base Address", 0}, 781 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryLength), "Entry Length", 0}, 782 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (EntryAddress32), "Entry 32", 0}, 783 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryAddress64), "Entry 64", 0}, 784 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (ExitAddress), "Exit Address", 0}, 785 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (LogAreaAddress), "Log Area Start", 0}, 786 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (LogAreaLength), "Log Area Length", 0}, 787 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (ArchDependentAddress), "Arch Dependent Address", 0}, 788 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (Flags), "Flags (decoded below)", 0}, 789 {ACPI_DMT_FLAG0, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Namespace in TCB", 0}, 790 {ACPI_DMT_FLAG1, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Gap Code on S3 Resume", 0}, 791 {ACPI_DMT_FLAG2, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Gap Code on DLME_Exit", 0}, 792 {ACPI_DMT_FLAG3, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "PCR_Authorities Changed", 0}, 793 ACPI_DMT_TERMINATOR 794 }; 795 796 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm0[] = 797 { 798 {ACPI_DMT_UINT32, ACPI_DRTM0_OFFSET (ValidatedTableCount), "Validated Table Count", DT_COUNT}, 799 ACPI_DMT_TERMINATOR 800 }; 801 802 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm0a[] = 803 { 804 {ACPI_DMT_UINT64, 0, "Table Address", DT_OPTIONAL}, 805 ACPI_DMT_TERMINATOR 806 }; 807 808 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm1[] = 809 { 810 {ACPI_DMT_UINT32, ACPI_DRTM1_OFFSET (ResourceCount), "Resource Count", DT_COUNT}, 811 ACPI_DMT_TERMINATOR 812 }; 813 814 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm1a[] = 815 { 816 {ACPI_DMT_UINT56, ACPI_DRTM1a_OFFSET (Size[0]), "Size", DT_OPTIONAL}, 817 {ACPI_DMT_UINT8, ACPI_DRTM1a_OFFSET (Type), "Type", 0}, 818 {ACPI_DMT_FLAG0, ACPI_DRTM1a_FLAG_OFFSET (Type, 0), "Resource Type", 0}, 819 {ACPI_DMT_FLAG7, ACPI_DRTM1a_FLAG_OFFSET (Type, 0), "Protections", 0}, 820 {ACPI_DMT_UINT64, ACPI_DRTM1a_OFFSET (Address), "Address", 0}, 821 ACPI_DMT_TERMINATOR 822 }; 823 824 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm2[] = 825 { 826 {ACPI_DMT_UINT32, ACPI_DRTM2_OFFSET (DpsIdLength), "DLME Platform Id Length", DT_COUNT}, 827 {ACPI_DMT_BUF16, ACPI_DRTM2_OFFSET (DpsId), "DLME Platform Id", DT_COUNT}, 828 ACPI_DMT_TERMINATOR 829 }; 830 831 832 /******************************************************************************* 833 * 834 * ECDT - Embedded Controller Boot Resources Table 835 * 836 ******************************************************************************/ 837 838 ACPI_DMTABLE_INFO AcpiDmTableInfoEcdt[] = 839 { 840 {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Control), "Command/Status Register", 0}, 841 {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Data), "Data Register", 0}, 842 {ACPI_DMT_UINT32, ACPI_ECDT_OFFSET (Uid), "UID", 0}, 843 {ACPI_DMT_UINT8, ACPI_ECDT_OFFSET (Gpe), "GPE Number", 0}, 844 {ACPI_DMT_STRING, ACPI_ECDT_OFFSET (Id[0]), "Namepath", 0}, 845 ACPI_DMT_TERMINATOR 846 }; 847 848 849 /******************************************************************************* 850 * 851 * EINJ - Error Injection table 852 * 853 ******************************************************************************/ 854 855 ACPI_DMTABLE_INFO AcpiDmTableInfoEinj[] = 856 { 857 {ACPI_DMT_UINT32, ACPI_EINJ_OFFSET (HeaderLength), "Injection Header Length", 0}, 858 {ACPI_DMT_UINT8, ACPI_EINJ_OFFSET (Flags), "Flags", 0}, 859 {ACPI_DMT_UINT24, ACPI_EINJ_OFFSET (Reserved[0]), "Reserved", 0}, 860 {ACPI_DMT_UINT32, ACPI_EINJ_OFFSET (Entries), "Injection Entry Count", 0}, 861 ACPI_DMT_TERMINATOR 862 }; 863 864 ACPI_DMTABLE_INFO AcpiDmTableInfoEinj0[] = 865 { 866 {ACPI_DMT_EINJACT, ACPI_EINJ0_OFFSET (Action), "Action", 0}, 867 {ACPI_DMT_EINJINST, ACPI_EINJ0_OFFSET (Instruction), "Instruction", 0}, 868 {ACPI_DMT_UINT8, ACPI_EINJ0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 869 {ACPI_DMT_FLAG0, ACPI_EINJ0_FLAG_OFFSET (Flags,0), "Preserve Register Bits", 0}, 870 871 {ACPI_DMT_UINT8, ACPI_EINJ0_OFFSET (Reserved), "Reserved", 0}, 872 {ACPI_DMT_GAS, ACPI_EINJ0_OFFSET (RegisterRegion), "Register Region", 0}, 873 {ACPI_DMT_UINT64, ACPI_EINJ0_OFFSET (Value), "Value", 0}, 874 {ACPI_DMT_UINT64, ACPI_EINJ0_OFFSET (Mask), "Mask", 0}, 875 ACPI_DMT_TERMINATOR 876 }; 877 878 879 /******************************************************************************* 880 * 881 * ERST - Error Record Serialization table 882 * 883 ******************************************************************************/ 884 885 ACPI_DMTABLE_INFO AcpiDmTableInfoErst[] = 886 { 887 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (HeaderLength), "Serialization Header Length", 0}, 888 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (Reserved), "Reserved", 0}, 889 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (Entries), "Instruction Entry Count", 0}, 890 ACPI_DMT_TERMINATOR 891 }; 892 893 ACPI_DMTABLE_INFO AcpiDmTableInfoErst0[] = 894 { 895 {ACPI_DMT_ERSTACT, ACPI_ERST0_OFFSET (Action), "Action", 0}, 896 {ACPI_DMT_ERSTINST, ACPI_ERST0_OFFSET (Instruction), "Instruction", 0}, 897 {ACPI_DMT_UINT8, ACPI_ERST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 898 {ACPI_DMT_FLAG0, ACPI_ERST0_FLAG_OFFSET (Flags,0), "Preserve Register Bits", 0}, 899 900 {ACPI_DMT_UINT8, ACPI_ERST0_OFFSET (Reserved), "Reserved", 0}, 901 {ACPI_DMT_GAS, ACPI_ERST0_OFFSET (RegisterRegion), "Register Region", 0}, 902 {ACPI_DMT_UINT64, ACPI_ERST0_OFFSET (Value), "Value", 0}, 903 {ACPI_DMT_UINT64, ACPI_ERST0_OFFSET (Mask), "Mask", 0}, 904 ACPI_DMT_TERMINATOR 905 }; 906 907 908 /******************************************************************************* 909 * 910 * FPDT - Firmware Performance Data Table (ACPI 5.0) 911 * 912 ******************************************************************************/ 913 914 /* Main table consists of only the standard ACPI header - subtables follow */ 915 916 /* FPDT subtable header */ 917 918 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdtHdr[] = 919 { 920 {ACPI_DMT_UINT16, ACPI_FPDTH_OFFSET (Type), "Subtable Type", 0}, 921 {ACPI_DMT_UINT8, ACPI_FPDTH_OFFSET (Length), "Length", DT_LENGTH}, 922 {ACPI_DMT_UINT8, ACPI_FPDTH_OFFSET (Revision), "Revision", 0}, 923 ACPI_DMT_TERMINATOR 924 }; 925 926 /* 0: Firmware Basic Boot Performance Record */ 927 928 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdt0[] = 929 { 930 {ACPI_DMT_UINT32, ACPI_FPDT0_OFFSET (Reserved), "Reserved", 0}, 931 {ACPI_DMT_UINT64, ACPI_FPDT1_OFFSET (Address), "FPDT Boot Record Address", 0}, 932 ACPI_DMT_TERMINATOR 933 }; 934 935 /* 1: S3 Performance Table Pointer Record */ 936 937 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdt1[] = 938 { 939 {ACPI_DMT_UINT32, ACPI_FPDT1_OFFSET (Reserved), "Reserved", 0}, 940 {ACPI_DMT_UINT64, ACPI_FPDT1_OFFSET (Address), "S3PT Record Address", 0}, 941 ACPI_DMT_TERMINATOR 942 }; 943 944 #if 0 945 /* Boot Performance Record, not supported at this time. */ 946 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ResetEnd), "Reset End", 0}, 947 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (LoadStart), "Load Image Start", 0}, 948 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (StartupStart), "Start Image Start", 0}, 949 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ExitServicesEntry), "Exit Services Entry", 0}, 950 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ExitServicesExit), "Exit Services Exit", 0}, 951 #endif 952 953 954 /******************************************************************************* 955 * 956 * GTDT - Generic Timer Description Table 957 * 958 ******************************************************************************/ 959 960 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt[] = 961 { 962 {ACPI_DMT_UINT64, ACPI_GTDT_OFFSET (CounterBlockAddresss), "Counter Block Address", 0}, 963 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (Reserved), "Reserved", 0}, 964 ACPI_DMT_NEW_LINE, 965 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (SecureEl1Interrupt), "Secure EL1 Interrupt", 0}, 966 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (SecureEl1Flags), "EL1 Flags (decoded below)", DT_FLAG}, 967 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Trigger Mode", 0}, 968 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Polarity", 0}, 969 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Always On", 0}, 970 ACPI_DMT_NEW_LINE, 971 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl1Interrupt), "Non-Secure EL1 Interrupt", 0}, 972 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl1Flags), "NEL1 Flags (decoded below)", DT_FLAG}, 973 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Trigger Mode", 0}, 974 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Polarity", 0}, 975 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Always On", 0}, 976 ACPI_DMT_NEW_LINE, 977 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (VirtualTimerInterrupt), "Virtual Timer Interrupt", 0}, 978 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (VirtualTimerFlags), "VT Flags (decoded below)", DT_FLAG}, 979 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Trigger Mode", 0}, 980 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Polarity", 0}, 981 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Always On", 0}, 982 ACPI_DMT_NEW_LINE, 983 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl2Interrupt), "Non-Secure EL2 Interrupt", 0}, 984 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl2Flags), "NEL2 Flags (decoded below)", DT_FLAG}, 985 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Trigger Mode", 0}, 986 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Polarity", 0}, 987 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Always On", 0}, 988 {ACPI_DMT_UINT64, ACPI_GTDT_OFFSET (CounterReadBlockAddress), "Counter Read Block Address", 0}, 989 ACPI_DMT_NEW_LINE, 990 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (PlatformTimerCount), "Platform Timer Count", 0}, 991 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (PlatformTimerOffset), "Platform Timer Offset", 0}, 992 ACPI_DMT_TERMINATOR 993 }; 994 995 /* GDTD EL2 timer info. This table is appended to AcpiDmTableInfoGtdt for rev 3 and later */ 996 997 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdtEl2[] = 998 { 999 {ACPI_DMT_UINT32, ACPI_GTDT_EL2_OFFSET (VirtualEL2TimerGsiv), "Virtual EL2 Timer GSIV", 0}, 1000 {ACPI_DMT_UINT32, ACPI_GTDT_EL2_OFFSET (VirtualEL2TimerFlags), "Virtual EL2 Timer Flags", 0}, 1001 ACPI_DMT_TERMINATOR 1002 }; 1003 1004 /* GTDT Subtable header (one per Subtable) */ 1005 1006 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdtHdr[] = 1007 { 1008 {ACPI_DMT_GTDT, ACPI_GTDTH_OFFSET (Type), "Subtable Type", 0}, 1009 {ACPI_DMT_UINT16, ACPI_GTDTH_OFFSET (Length), "Length", DT_LENGTH}, 1010 ACPI_DMT_TERMINATOR 1011 }; 1012 1013 /* GTDT Subtables */ 1014 1015 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt0[] = 1016 { 1017 {ACPI_DMT_UINT8, ACPI_GTDT0_OFFSET (Reserved), "Reserved", 0}, 1018 {ACPI_DMT_UINT64, ACPI_GTDT0_OFFSET (BlockAddress), "Block Address", 0}, 1019 {ACPI_DMT_UINT32, ACPI_GTDT0_OFFSET (TimerCount), "Timer Count", 0}, 1020 {ACPI_DMT_UINT32, ACPI_GTDT0_OFFSET (TimerOffset), "Timer Offset", 0}, 1021 ACPI_DMT_TERMINATOR 1022 }; 1023 1024 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt0a[] = 1025 { 1026 {ACPI_DMT_UINT8 , ACPI_GTDT0a_OFFSET (FrameNumber), "Frame Number", 0}, 1027 {ACPI_DMT_UINT24, ACPI_GTDT0a_OFFSET (Reserved[0]), "Reserved", 0}, 1028 {ACPI_DMT_UINT64, ACPI_GTDT0a_OFFSET (BaseAddress), "Base Address", 0}, 1029 {ACPI_DMT_UINT64, ACPI_GTDT0a_OFFSET (El0BaseAddress), "EL0 Base Address", 0}, 1030 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (TimerInterrupt), "Timer Interrupt", 0}, 1031 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (TimerFlags), "Timer Flags (decoded below)", 0}, 1032 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (TimerFlags,0), "Trigger Mode", 0}, 1033 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (TimerFlags,0), "Polarity", 0}, 1034 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (VirtualTimerInterrupt), "Virtual Timer Interrupt", 0}, 1035 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (VirtualTimerFlags), "Virtual Timer Flags (decoded below)", 0}, 1036 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (VirtualTimerFlags,0), "Trigger Mode", 0}, 1037 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (VirtualTimerFlags,0), "Polarity", 0}, 1038 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (CommonFlags), "Common Flags (decoded below)", 0}, 1039 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (CommonFlags,0), "Secure", 0}, 1040 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (CommonFlags,0), "Always On", 0}, 1041 ACPI_DMT_TERMINATOR 1042 }; 1043 1044 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt1[] = 1045 { 1046 {ACPI_DMT_UINT8, ACPI_GTDT1_OFFSET (Reserved), "Reserved", 0}, 1047 {ACPI_DMT_UINT64, ACPI_GTDT1_OFFSET (RefreshFrameAddress), "Refresh Frame Address", 0}, 1048 {ACPI_DMT_UINT64, ACPI_GTDT1_OFFSET (ControlFrameAddress), "Control Frame Address", 0}, 1049 {ACPI_DMT_UINT32, ACPI_GTDT1_OFFSET (TimerInterrupt), "Timer Interrupt", 0}, 1050 {ACPI_DMT_UINT32, ACPI_GTDT1_OFFSET (TimerFlags), "Timer Flags (decoded below)", DT_FLAG}, 1051 {ACPI_DMT_FLAG0, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Trigger Mode", 0}, 1052 {ACPI_DMT_FLAG1, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Polarity", 0}, 1053 {ACPI_DMT_FLAG2, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Security", 0}, 1054 ACPI_DMT_TERMINATOR 1055 }; 1056 1057 1058 /******************************************************************************* 1059 * 1060 * HEST - Hardware Error Source table 1061 * 1062 ******************************************************************************/ 1063 1064 ACPI_DMTABLE_INFO AcpiDmTableInfoHest[] = 1065 { 1066 {ACPI_DMT_UINT32, ACPI_HEST_OFFSET (ErrorSourceCount), "Error Source Count", 0}, 1067 ACPI_DMT_TERMINATOR 1068 }; 1069 1070 /* Common HEST structures for subtables */ 1071 1072 #define ACPI_DM_HEST_HEADER \ 1073 {ACPI_DMT_HEST, ACPI_HEST0_OFFSET (Header.Type), "Subtable Type", 0}, \ 1074 {ACPI_DMT_UINT16, ACPI_HEST0_OFFSET (Header.SourceId), "Source Id", 0} 1075 1076 #define ACPI_DM_HEST_AER \ 1077 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Reserved1), "Reserved", 0}, \ 1078 {ACPI_DMT_UINT8, ACPI_HEST6_OFFSET (Aer.Flags), "Flags (decoded below)", DT_FLAG}, \ 1079 {ACPI_DMT_FLAG0, ACPI_HEST6_FLAG_OFFSET (Aer.Flags,0), "Firmware First", 0}, \ 1080 {ACPI_DMT_FLAG0, ACPI_HEST6_FLAG_OFFSET (Aer.Flags,0), "Global", 0}, \ 1081 {ACPI_DMT_UINT8, ACPI_HEST6_OFFSET (Aer.Enabled), "Enabled", 0}, \ 1082 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.RecordsToPreallocate), "Records To Preallocate", 0}, \ 1083 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.MaxSectionsPerRecord), "Max Sections Per Record", 0}, \ 1084 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.Bus), "Bus", 0}, \ 1085 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Device), "Device", 0}, \ 1086 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Function), "Function", 0}, \ 1087 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.DeviceControl), "DeviceControl", 0}, \ 1088 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Reserved2), "Reserved", 0}, \ 1089 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.UncorrectableMask), "Uncorrectable Mask", 0}, \ 1090 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.UncorrectableSeverity), "Uncorrectable Severity", 0}, \ 1091 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.CorrectableMask), "Correctable Mask", 0}, \ 1092 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.AdvancedCapabilities), "Advanced Capabilities", 0} 1093 1094 1095 /* HEST Subtables */ 1096 1097 /* 0: IA32 Machine Check Exception */ 1098 1099 ACPI_DMTABLE_INFO AcpiDmTableInfoHest0[] = 1100 { 1101 ACPI_DM_HEST_HEADER, 1102 {ACPI_DMT_UINT16, ACPI_HEST0_OFFSET (Reserved1), "Reserved1", 0}, 1103 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1104 {ACPI_DMT_FLAG0, ACPI_HEST0_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1105 {ACPI_DMT_FLAG2, ACPI_HEST0_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1106 1107 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (Enabled), "Enabled", 0}, 1108 {ACPI_DMT_UINT32, ACPI_HEST0_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1109 {ACPI_DMT_UINT32, ACPI_HEST0_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1110 {ACPI_DMT_UINT64, ACPI_HEST0_OFFSET (GlobalCapabilityData), "Global Capability Data", 0}, 1111 {ACPI_DMT_UINT64, ACPI_HEST0_OFFSET (GlobalControlData), "Global Control Data", 0}, 1112 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1113 {ACPI_DMT_UINT56, ACPI_HEST0_OFFSET (Reserved3[0]), "Reserved2", 0}, 1114 ACPI_DMT_TERMINATOR 1115 }; 1116 1117 /* 1: IA32 Corrected Machine Check */ 1118 1119 ACPI_DMTABLE_INFO AcpiDmTableInfoHest1[] = 1120 { 1121 ACPI_DM_HEST_HEADER, 1122 {ACPI_DMT_UINT16, ACPI_HEST1_OFFSET (Reserved1), "Reserved1", 0}, 1123 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1124 {ACPI_DMT_FLAG0, ACPI_HEST1_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1125 {ACPI_DMT_FLAG2, ACPI_HEST1_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1126 1127 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (Enabled), "Enabled", 0}, 1128 {ACPI_DMT_UINT32, ACPI_HEST1_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1129 {ACPI_DMT_UINT32, ACPI_HEST1_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1130 {ACPI_DMT_HESTNTFY, ACPI_HEST1_OFFSET (Notify), "Notify", 0}, 1131 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1132 {ACPI_DMT_UINT24, ACPI_HEST1_OFFSET (Reserved2[0]), "Reserved2", 0}, 1133 ACPI_DMT_TERMINATOR 1134 }; 1135 1136 /* 2: IA32 Non-Maskable Interrupt */ 1137 1138 ACPI_DMTABLE_INFO AcpiDmTableInfoHest2[] = 1139 { 1140 ACPI_DM_HEST_HEADER, 1141 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (Reserved), "Reserved", 0}, 1142 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1143 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1144 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1145 ACPI_DMT_TERMINATOR 1146 }; 1147 1148 /* 6: PCI Express Root Port AER */ 1149 1150 ACPI_DMTABLE_INFO AcpiDmTableInfoHest6[] = 1151 { 1152 ACPI_DM_HEST_HEADER, 1153 ACPI_DM_HEST_AER, 1154 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (RootErrorCommand), "Root Error Command", 0}, 1155 ACPI_DMT_TERMINATOR 1156 }; 1157 1158 /* 7: PCI Express AER (AER Endpoint) */ 1159 1160 ACPI_DMTABLE_INFO AcpiDmTableInfoHest7[] = 1161 { 1162 ACPI_DM_HEST_HEADER, 1163 ACPI_DM_HEST_AER, 1164 ACPI_DMT_TERMINATOR 1165 }; 1166 1167 /* 8: PCI Express/PCI-X Bridge AER */ 1168 1169 ACPI_DMTABLE_INFO AcpiDmTableInfoHest8[] = 1170 { 1171 ACPI_DM_HEST_HEADER, 1172 ACPI_DM_HEST_AER, 1173 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (UncorrectableMask2), "2nd Uncorrectable Mask", 0}, 1174 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (UncorrectableSeverity2), "2nd Uncorrectable Severity", 0}, 1175 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (AdvancedCapabilities2), "2nd Advanced Capabilities", 0}, 1176 ACPI_DMT_TERMINATOR 1177 }; 1178 1179 /* 9: Generic Hardware Error Source */ 1180 1181 ACPI_DMTABLE_INFO AcpiDmTableInfoHest9[] = 1182 { 1183 ACPI_DM_HEST_HEADER, 1184 {ACPI_DMT_UINT16, ACPI_HEST9_OFFSET (RelatedSourceId), "Related Source Id", 0}, 1185 {ACPI_DMT_UINT8, ACPI_HEST9_OFFSET (Reserved), "Reserved", 0}, 1186 {ACPI_DMT_UINT8, ACPI_HEST9_OFFSET (Enabled), "Enabled", 0}, 1187 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1188 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1189 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1190 {ACPI_DMT_GAS, ACPI_HEST9_OFFSET (ErrorStatusAddress), "Error Status Address", 0}, 1191 {ACPI_DMT_HESTNTFY, ACPI_HEST9_OFFSET (Notify), "Notify", 0}, 1192 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (ErrorBlockLength), "Error Status Block Length", 0}, 1193 ACPI_DMT_TERMINATOR 1194 }; 1195 1196 /* 10: Generic Hardware Error Source - Version 2 */ 1197 1198 ACPI_DMTABLE_INFO AcpiDmTableInfoHest10[] = 1199 { 1200 ACPI_DM_HEST_HEADER, 1201 {ACPI_DMT_UINT16, ACPI_HEST10_OFFSET (RelatedSourceId), "Related Source Id", 0}, 1202 {ACPI_DMT_UINT8, ACPI_HEST10_OFFSET (Reserved), "Reserved", 0}, 1203 {ACPI_DMT_UINT8, ACPI_HEST10_OFFSET (Enabled), "Enabled", 0}, 1204 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1205 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1206 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1207 {ACPI_DMT_GAS, ACPI_HEST10_OFFSET (ErrorStatusAddress), "Error Status Address", 0}, 1208 {ACPI_DMT_HESTNTFY, ACPI_HEST10_OFFSET (Notify), "Notify", 0}, 1209 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (ErrorBlockLength), "Error Status Block Length", 0}, 1210 {ACPI_DMT_GAS, ACPI_HEST10_OFFSET (ReadAckRegister), "Read Ack Register", 0}, 1211 {ACPI_DMT_UINT64, ACPI_HEST10_OFFSET (ReadAckPreserve), "Read Ack Preserve", 0}, 1212 {ACPI_DMT_UINT64, ACPI_HEST10_OFFSET (ReadAckWrite), "Read Ack Write", 0}, 1213 ACPI_DMT_TERMINATOR 1214 }; 1215 1216 /* 11: IA32 Deferred Machine Check */ 1217 1218 ACPI_DMTABLE_INFO AcpiDmTableInfoHest11[] = 1219 { 1220 ACPI_DM_HEST_HEADER, 1221 {ACPI_DMT_UINT16, ACPI_HEST11_OFFSET (Reserved1), "Reserved1", 0}, 1222 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1223 {ACPI_DMT_FLAG0, ACPI_HEST11_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1224 {ACPI_DMT_FLAG2, ACPI_HEST11_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1225 1226 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (Enabled), "Enabled", 0}, 1227 {ACPI_DMT_UINT32, ACPI_HEST11_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1228 {ACPI_DMT_UINT32, ACPI_HEST11_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1229 {ACPI_DMT_HESTNTFY, ACPI_HEST11_OFFSET (Notify), "Notify", 0}, 1230 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1231 {ACPI_DMT_UINT24, ACPI_HEST11_OFFSET (Reserved2[0]), "Reserved2", 0}, 1232 ACPI_DMT_TERMINATOR 1233 }; 1234 1235 /* Notification Structure */ 1236 1237 ACPI_DMTABLE_INFO AcpiDmTableInfoHestNotify[] = 1238 { 1239 {ACPI_DMT_HESTNTYP, ACPI_HESTN_OFFSET (Type), "Notify Type", 0}, 1240 {ACPI_DMT_UINT8, ACPI_HESTN_OFFSET (Length), "Notify Length", DT_LENGTH}, 1241 {ACPI_DMT_UINT16, ACPI_HESTN_OFFSET (ConfigWriteEnable), "Configuration Write Enable", 0}, 1242 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollInterval), "PollInterval", 0}, 1243 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (Vector), "Vector", 0}, 1244 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollingThresholdValue), "Polling Threshold Value", 0}, 1245 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollingThresholdWindow), "Polling Threshold Window", 0}, 1246 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (ErrorThresholdValue), "Error Threshold Value", 0}, 1247 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (ErrorThresholdWindow), "Error Threshold Window", 0}, 1248 ACPI_DMT_TERMINATOR 1249 }; 1250 1251 1252 /* 1253 * IA32 Error Bank(s) - Follows the ACPI_HEST_IA_MACHINE_CHECK and 1254 * ACPI_HEST_IA_CORRECTED structures. 1255 */ 1256 ACPI_DMTABLE_INFO AcpiDmTableInfoHestBank[] = 1257 { 1258 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (BankNumber), "Bank Number", 0}, 1259 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (ClearStatusOnInit), "Clear Status On Init", 0}, 1260 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (StatusFormat), "Status Format", 0}, 1261 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (Reserved), "Reserved", 0}, 1262 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (ControlRegister), "Control Register", 0}, 1263 {ACPI_DMT_UINT64, ACPI_HESTB_OFFSET (ControlData), "Control Data", 0}, 1264 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (StatusRegister), "Status Register", 0}, 1265 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (AddressRegister), "Address Register", 0}, 1266 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (MiscRegister), "Misc Register", 0}, 1267 ACPI_DMT_TERMINATOR 1268 }; 1269 1270 1271 /******************************************************************************* 1272 * 1273 * HMAT - Heterogeneous Memory Attributes Table 1274 * 1275 ******************************************************************************/ 1276 1277 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat[] = 1278 { 1279 {ACPI_DMT_UINT32, ACPI_HMAT_OFFSET (Reserved), "Reserved", 0}, 1280 ACPI_DMT_TERMINATOR 1281 }; 1282 1283 /* Common HMAT structure header (one per Subtable) */ 1284 1285 ACPI_DMTABLE_INFO AcpiDmTableInfoHmatHdr[] = 1286 { 1287 {ACPI_DMT_HMAT, ACPI_HMATH_OFFSET (Type), "Structure Type", 0}, 1288 {ACPI_DMT_UINT16, ACPI_HMATH_OFFSET (Reserved), "Reserved", 0}, 1289 {ACPI_DMT_UINT32, ACPI_HMATH_OFFSET (Length), "Length", 0}, 1290 ACPI_DMT_TERMINATOR 1291 }; 1292 1293 /* HMAT subtables */ 1294 1295 /* 0x00: Memory proximity domain attributes */ 1296 1297 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat0[] = 1298 { 1299 {ACPI_DMT_UINT16, ACPI_HMAT0_OFFSET (Flags), "Flags (decoded below)", 0}, 1300 {ACPI_DMT_FLAG0, ACPI_HMAT0_FLAG_OFFSET (Flags,0), "Processor Proximity Domain Valid", 0}, 1301 {ACPI_DMT_UINT16, ACPI_HMAT0_OFFSET (Reserved1), "Reserved1", 0}, 1302 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (InitiatorPD), "Attached Initiator Proximity Domain", 0}, 1303 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (MemoryPD), "Memory Proximity Domain", 0}, 1304 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (Reserved2), "Reserved2", 0}, 1305 {ACPI_DMT_UINT64, ACPI_HMAT0_OFFSET (Reserved3), "Reserved3", 0}, 1306 {ACPI_DMT_UINT64, ACPI_HMAT0_OFFSET (Reserved4), "Reserved4", 0}, 1307 ACPI_DMT_TERMINATOR 1308 }; 1309 1310 /* 0x01: System Locality Latency and Bandwidth Information */ 1311 1312 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1[] = 1313 { 1314 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (Flags), "Flags (decoded below)", 0}, 1315 {ACPI_DMT_FLAGS4_0, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Memory Hierarchy", 0}, /* First 4 bits */ 1316 {ACPI_DMT_FLAG4, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Use Minimum Transfer Size", 0}, 1317 {ACPI_DMT_FLAG5, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Non-sequential Transfers", 0}, 1318 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (DataType), "Data Type", 0}, 1319 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (MinTransferSize), "Minimum Transfer Size", 0}, 1320 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (Reserved1), "Reserved1", 0}, 1321 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (NumberOfInitiatorPDs), "Initiator Proximity Domains #", 0}, 1322 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (NumberOfTargetPDs), "Target Proximity Domains #", 0}, 1323 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (Reserved2), "Reserved2", 0}, 1324 {ACPI_DMT_UINT64, ACPI_HMAT1_OFFSET (EntryBaseUnit), "Entry Base Unit", 0}, 1325 ACPI_DMT_TERMINATOR 1326 }; 1327 1328 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1a[] = 1329 { 1330 {ACPI_DMT_UINT32, 0, "Initiator Proximity Domain List", DT_OPTIONAL}, 1331 ACPI_DMT_TERMINATOR 1332 }; 1333 1334 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1b[] = 1335 { 1336 {ACPI_DMT_UINT32, 0, "Target Proximity Domain List", DT_OPTIONAL}, 1337 ACPI_DMT_TERMINATOR 1338 }; 1339 1340 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1c[] = 1341 { 1342 {ACPI_DMT_UINT16, 0, "Entry", DT_OPTIONAL}, 1343 ACPI_DMT_TERMINATOR 1344 }; 1345 1346 /* 0x02: Memory Side Cache Information */ 1347 1348 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat2[] = 1349 { 1350 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (MemoryPD), "Memory Proximity Domain", 0}, 1351 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (Reserved1), "Reserved1", 0}, 1352 {ACPI_DMT_UINT64, ACPI_HMAT2_OFFSET (CacheSize), "Memory Side Cache Size", 0}, 1353 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (CacheAttributes), "Cache Attributes (decoded below)", 0}, 1354 {ACPI_DMT_FLAGS4_0, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Total Cache Levels", 0}, 1355 {ACPI_DMT_FLAGS4_4, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Level", 0}, 1356 {ACPI_DMT_FLAGS4_8, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Associativity", 0}, 1357 {ACPI_DMT_FLAGS4_12, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Write Policy", 0}, 1358 {ACPI_DMT_FLAGS16_16, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Line Size", 0}, 1359 {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (Reserved2), "Reserved2", 0}, 1360 {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (NumberOfSMBIOSHandles), "SMBIOS Handle #", 0}, 1361 ACPI_DMT_TERMINATOR 1362 }; 1363 1364 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat2a[] = 1365 { 1366 {ACPI_DMT_UINT16, 0, "SMBIOS Handle", DT_OPTIONAL}, 1367 ACPI_DMT_TERMINATOR 1368 }; 1369 1370 1371 /******************************************************************************* 1372 * 1373 * HPET - High Precision Event Timer table 1374 * 1375 ******************************************************************************/ 1376 1377 ACPI_DMTABLE_INFO AcpiDmTableInfoHpet[] = 1378 { 1379 {ACPI_DMT_UINT32, ACPI_HPET_OFFSET (Id), "Hardware Block ID", 0}, 1380 {ACPI_DMT_GAS, ACPI_HPET_OFFSET (Address), "Timer Block Register", 0}, 1381 {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Sequence), "Sequence Number", 0}, 1382 {ACPI_DMT_UINT16, ACPI_HPET_OFFSET (MinimumTick), "Minimum Clock Ticks", 0}, 1383 {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1384 {ACPI_DMT_FLAG0, ACPI_HPET_FLAG_OFFSET (Flags,0), "4K Page Protect", 0}, 1385 {ACPI_DMT_FLAG1, ACPI_HPET_FLAG_OFFSET (Flags,0), "64K Page Protect", 0}, 1386 ACPI_DMT_TERMINATOR 1387 }; 1388 /*! [End] no source code translation !*/ 1389