1 /****************************************************************************** 2 * 3 * Module Name: dmtbinfo1 - Table info for non-AML tables 4 * 5 *****************************************************************************/ 6 7 /****************************************************************************** 8 * 9 * 1. Copyright Notice 10 * 11 * Some or all of this work - Copyright (c) 1999 - 2021, Intel Corp. 12 * All rights reserved. 13 * 14 * 2. License 15 * 16 * 2.1. This is your license from Intel Corp. under its intellectual property 17 * rights. You may have additional license terms from the party that provided 18 * you this software, covering your right to use that party's intellectual 19 * property rights. 20 * 21 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a 22 * copy of the source code appearing in this file ("Covered Code") an 23 * irrevocable, perpetual, worldwide license under Intel's copyrights in the 24 * base code distributed originally by Intel ("Original Intel Code") to copy, 25 * make derivatives, distribute, use and display any portion of the Covered 26 * Code in any form, with the right to sublicense such rights; and 27 * 28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 29 * license (with the right to sublicense), under only those claims of Intel 30 * patents that are infringed by the Original Intel Code, to make, use, sell, 31 * offer to sell, and import the Covered Code and derivative works thereof 32 * solely to the minimum extent necessary to exercise the above copyright 33 * license, and in no event shall the patent license extend to any additions 34 * to or modifications of the Original Intel Code. No other license or right 35 * is granted directly or by implication, estoppel or otherwise; 36 * 37 * The above copyright and patent license is granted only if the following 38 * conditions are met: 39 * 40 * 3. Conditions 41 * 42 * 3.1. Redistribution of Source with Rights to Further Distribute Source. 43 * Redistribution of source code of any substantial portion of the Covered 44 * Code or modification with rights to further distribute source must include 45 * the above Copyright Notice, the above License, this list of Conditions, 46 * and the following Disclaimer and Export Compliance provision. In addition, 47 * Licensee must cause all Covered Code to which Licensee contributes to 48 * contain a file documenting the changes Licensee made to create that Covered 49 * Code and the date of any change. Licensee must include in that file the 50 * documentation of any changes made by any predecessor Licensee. Licensee 51 * must include a prominent statement that the modification is derived, 52 * directly or indirectly, from Original Intel Code. 53 * 54 * 3.2. Redistribution of Source with no Rights to Further Distribute Source. 55 * Redistribution of source code of any substantial portion of the Covered 56 * Code or modification without rights to further distribute source must 57 * include the following Disclaimer and Export Compliance provision in the 58 * documentation and/or other materials provided with distribution. In 59 * addition, Licensee may not authorize further sublicense of source of any 60 * portion of the Covered Code, and must include terms to the effect that the 61 * license from Licensee to its licensee is limited to the intellectual 62 * property embodied in the software Licensee provides to its licensee, and 63 * not to intellectual property embodied in modifications its licensee may 64 * make. 65 * 66 * 3.3. Redistribution of Executable. Redistribution in executable form of any 67 * substantial portion of the Covered Code or modification must reproduce the 68 * above Copyright Notice, and the following Disclaimer and Export Compliance 69 * provision in the documentation and/or other materials provided with the 70 * distribution. 71 * 72 * 3.4. Intel retains all right, title, and interest in and to the Original 73 * Intel Code. 74 * 75 * 3.5. Neither the name Intel nor any other trademark owned or controlled by 76 * Intel shall be used in advertising or otherwise to promote the sale, use or 77 * other dealings in products derived from or relating to the Covered Code 78 * without prior written authorization from Intel. 79 * 80 * 4. Disclaimer and Export Compliance 81 * 82 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED 83 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE 84 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, 85 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY 86 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY 87 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A 88 * PARTICULAR PURPOSE. 89 * 90 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES 91 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR 92 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, 93 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY 94 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL 95 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS 96 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY 97 * LIMITED REMEDY. 98 * 99 * 4.3. Licensee shall not export, either directly or indirectly, any of this 100 * software or system incorporating such software without first obtaining any 101 * required license or other approval from the U. S. Department of Commerce or 102 * any other agency or department of the United States Government. In the 103 * event Licensee exports any such software from the United States or 104 * re-exports any such software from a foreign destination, Licensee shall 105 * ensure that the distribution and export/re-export of the software is in 106 * compliance with all laws, regulations, orders, or other restrictions of the 107 * U.S. Export Administration Regulations. Licensee agrees that neither it nor 108 * any of its subsidiaries will export/re-export any technical data, process, 109 * software, or service, directly or indirectly, to any country for which the 110 * United States government or any agency thereof requires an export license, 111 * other governmental approval, or letter of assurance, without first obtaining 112 * such license, approval or letter. 113 * 114 ***************************************************************************** 115 * 116 * Alternatively, you may choose to be licensed under the terms of the 117 * following license: 118 * 119 * Redistribution and use in source and binary forms, with or without 120 * modification, are permitted provided that the following conditions 121 * are met: 122 * 1. Redistributions of source code must retain the above copyright 123 * notice, this list of conditions, and the following disclaimer, 124 * without modification. 125 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 126 * substantially similar to the "NO WARRANTY" disclaimer below 127 * ("Disclaimer") and any redistribution must be conditioned upon 128 * including a substantially similar Disclaimer requirement for further 129 * binary redistribution. 130 * 3. Neither the names of the above-listed copyright holders nor the names 131 * of any contributors may be used to endorse or promote products derived 132 * from this software without specific prior written permission. 133 * 134 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 135 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 136 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 137 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 138 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 139 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 140 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 141 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 142 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 143 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 144 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 145 * 146 * Alternatively, you may choose to be licensed under the terms of the 147 * GNU General Public License ("GPL") version 2 as published by the Free 148 * Software Foundation. 149 * 150 *****************************************************************************/ 151 152 #include "acpi.h" 153 #include "accommon.h" 154 #include "acdisasm.h" 155 #include "actbinfo.h" 156 157 /* This module used for application-level code only */ 158 159 #define _COMPONENT ACPI_CA_DISASSEMBLER 160 ACPI_MODULE_NAME ("dmtbinfo1") 161 162 /* 163 * How to add a new table: 164 * 165 * - Add the C table definition to the actbl1.h or actbl2.h header. 166 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below. 167 * - Define the table in this file (for the disassembler). If any 168 * new data types are required (ACPI_DMT_*), see below. 169 * - Add an external declaration for the new table definition (AcpiDmTableInfo*) 170 * in acdisam.h 171 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData) 172 * If a simple table (with no subtables), no disassembly code is needed. 173 * Otherwise, create the AcpiDmDump* function for to disassemble the table 174 * and add it to the dmtbdump.c file. 175 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h 176 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c 177 * - Create a template for the new table 178 * - Add data table compiler support 179 * 180 * How to add a new data type (ACPI_DMT_*): 181 * 182 * - Add new type at the end of the ACPI_DMT list in acdisasm.h 183 * - Add length and implementation cases in dmtable.c (disassembler) 184 * - Add type and length cases in dtutils.c (DT compiler) 185 */ 186 187 /* 188 * ACPI Table Information, used to dump formatted ACPI tables 189 * 190 * Each entry is of the form: <Field Type, Field Offset, Field Name> 191 */ 192 193 194 /******************************************************************************* 195 * 196 * ASF - Alert Standard Format table (Signature "ASF!") 197 * 198 ******************************************************************************/ 199 200 /* Common Subtable header (one per Subtable) */ 201 202 ACPI_DMTABLE_INFO AcpiDmTableInfoAsfHdr[] = 203 { 204 {ACPI_DMT_ASF, ACPI_ASF0_OFFSET (Header.Type), "Subtable Type", 0}, 205 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Header.Reserved), "Reserved", 0}, 206 {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (Header.Length), "Length", DT_LENGTH}, 207 ACPI_DMT_TERMINATOR 208 }; 209 210 /* 0: ASF Information */ 211 212 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf0[] = 213 { 214 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinResetValue), "Minimum Reset Value", 0}, 215 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinPollInterval), "Minimum Polling Interval", 0}, 216 {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (SystemId), "System ID", 0}, 217 {ACPI_DMT_UINT32, ACPI_ASF0_OFFSET (MfgId), "Manufacturer ID", 0}, 218 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Flags), "Flags", 0}, 219 {ACPI_DMT_UINT24, ACPI_ASF0_OFFSET (Reserved2[0]), "Reserved", 0}, 220 ACPI_DMT_TERMINATOR 221 }; 222 223 /* 1: ASF Alerts */ 224 225 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1[] = 226 { 227 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (AssertMask), "AssertMask", 0}, 228 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DeassertMask), "DeassertMask", 0}, 229 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (Alerts), "Alert Count", 0}, 230 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DataLength), "Alert Data Length", 0}, 231 ACPI_DMT_TERMINATOR 232 }; 233 234 /* 1a: ASF Alert data */ 235 236 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1a[] = 237 { 238 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Address), "Address", 0}, 239 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Command), "Command", 0}, 240 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Mask), "Mask", 0}, 241 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Value), "Value", 0}, 242 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorType), "SensorType", 0}, 243 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Type), "Type", 0}, 244 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Offset), "Offset", 0}, 245 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SourceType), "SourceType", 0}, 246 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Severity), "Severity", 0}, 247 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorNumber), "SensorNumber", 0}, 248 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Entity), "Entity", 0}, 249 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Instance), "Instance", 0}, 250 ACPI_DMT_TERMINATOR 251 }; 252 253 /* 2: ASF Remote Control */ 254 255 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2[] = 256 { 257 {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (Controls), "Control Count", 0}, 258 {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (DataLength), "Control Data Length", 0}, 259 {ACPI_DMT_UINT16, ACPI_ASF2_OFFSET (Reserved2), "Reserved", 0}, 260 ACPI_DMT_TERMINATOR 261 }; 262 263 /* 2a: ASF Control data */ 264 265 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2a[] = 266 { 267 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Function), "Function", 0}, 268 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Address), "Address", 0}, 269 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Command), "Command", 0}, 270 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Value), "Value", 0}, 271 ACPI_DMT_TERMINATOR 272 }; 273 274 /* 3: ASF RMCP Boot Options */ 275 276 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf3[] = 277 { 278 {ACPI_DMT_BUF7, ACPI_ASF3_OFFSET (Capabilities[0]), "Capabilities", 0}, 279 {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (CompletionCode), "Completion Code", 0}, 280 {ACPI_DMT_UINT32, ACPI_ASF3_OFFSET (EnterpriseId), "Enterprise ID", 0}, 281 {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (Command), "Command", 0}, 282 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (Parameter), "Parameter", 0}, 283 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (BootOptions), "Boot Options", 0}, 284 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (OemParameters), "Oem Parameters", 0}, 285 ACPI_DMT_TERMINATOR 286 }; 287 288 /* 4: ASF Address */ 289 290 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf4[] = 291 { 292 {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (EpromAddress), "Eprom Address", 0}, 293 {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (Devices), "Device Count", DT_COUNT}, 294 ACPI_DMT_TERMINATOR 295 }; 296 297 298 /******************************************************************************* 299 * 300 * BDAT - BIOS Data ACPI Table 301 * 302 ******************************************************************************/ 303 304 ACPI_DMTABLE_INFO AcpiDmTableInfoBdat[] = 305 { 306 {ACPI_DMT_GAS, ACPI_BDAT_OFFSET (Gas), "BDAT Generic Address", 0}, 307 ACPI_DMT_TERMINATOR 308 }; 309 310 311 /******************************************************************************* 312 * 313 * BERT - Boot Error Record table 314 * 315 ******************************************************************************/ 316 317 ACPI_DMTABLE_INFO AcpiDmTableInfoBert[] = 318 { 319 {ACPI_DMT_UINT32, ACPI_BERT_OFFSET (RegionLength), "Boot Error Region Length", 0}, 320 {ACPI_DMT_UINT64, ACPI_BERT_OFFSET (Address), "Boot Error Region Address", 0}, 321 ACPI_DMT_TERMINATOR 322 }; 323 324 325 /******************************************************************************* 326 * 327 * BGRT - Boot Graphics Resource Table (ACPI 5.0) 328 * 329 ******************************************************************************/ 330 331 ACPI_DMTABLE_INFO AcpiDmTableInfoBgrt[] = 332 { 333 {ACPI_DMT_UINT16, ACPI_BGRT_OFFSET (Version), "Version", 0}, 334 {ACPI_DMT_UINT8, ACPI_BGRT_OFFSET (Status), "Status (decoded below)", DT_FLAG}, 335 {ACPI_DMT_FLAG0, ACPI_BGRT_FLAG_OFFSET (Status, 0), "Displayed", 0}, 336 {ACPI_DMT_FLAGS1, ACPI_BGRT_FLAG_OFFSET (Status, 0), "Orientation Offset", 0}, 337 338 {ACPI_DMT_UINT8, ACPI_BGRT_OFFSET (ImageType), "Image Type", 0}, 339 {ACPI_DMT_UINT64, ACPI_BGRT_OFFSET (ImageAddress), "Image Address", 0}, 340 {ACPI_DMT_UINT32, ACPI_BGRT_OFFSET (ImageOffsetX), "Image OffsetX", 0}, 341 {ACPI_DMT_UINT32, ACPI_BGRT_OFFSET (ImageOffsetY), "Image OffsetY", 0}, 342 ACPI_DMT_TERMINATOR 343 }; 344 345 346 /******************************************************************************* 347 * 348 * BOOT - Simple Boot Flag Table 349 * 350 ******************************************************************************/ 351 352 ACPI_DMTABLE_INFO AcpiDmTableInfoBoot[] = 353 { 354 {ACPI_DMT_UINT8, ACPI_BOOT_OFFSET (CmosIndex), "Boot Register Index", 0}, 355 {ACPI_DMT_UINT24, ACPI_BOOT_OFFSET (Reserved[0]), "Reserved", 0}, 356 ACPI_DMT_TERMINATOR 357 }; 358 359 360 /******************************************************************************* 361 * 362 * CEDT - CXL Early Discovery Table 363 * 364 ******************************************************************************/ 365 366 ACPI_DMTABLE_INFO AcpiDmTableInfoCedtHdr[] = 367 { 368 {ACPI_DMT_CEDT, ACPI_CEDT_OFFSET (Type), "Subtable Type", 0}, 369 {ACPI_DMT_UINT8, ACPI_CEDT_OFFSET (Reserved), "Reserved", 0}, 370 {ACPI_DMT_UINT16, ACPI_CEDT_OFFSET (Length), "Length", DT_LENGTH}, 371 ACPI_DMT_TERMINATOR 372 }; 373 374 /* 0: CXL Host Bridge Structure */ 375 376 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt0[] = 377 { 378 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (Uid), "Associated host bridge", 0}, 379 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (CxlVersion), "Specification version", 0}, 380 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (Reserved), "Reserved", 0}, 381 {ACPI_DMT_UINT64, ACPI_CEDT0_OFFSET (Base), "Register base", 0}, 382 {ACPI_DMT_UINT64, ACPI_CEDT0_OFFSET (Length), "Register length", 0}, 383 ACPI_DMT_TERMINATOR 384 }; 385 386 387 /******************************************************************************* 388 * 389 * CPEP - Corrected Platform Error Polling table 390 * 391 ******************************************************************************/ 392 393 ACPI_DMTABLE_INFO AcpiDmTableInfoCpep[] = 394 { 395 {ACPI_DMT_UINT64, ACPI_CPEP_OFFSET (Reserved), "Reserved", 0}, 396 ACPI_DMT_TERMINATOR 397 }; 398 399 ACPI_DMTABLE_INFO AcpiDmTableInfoCpep0[] = 400 { 401 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Header.Type), "Subtable Type", 0}, 402 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Header.Length), "Length", DT_LENGTH}, 403 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Id), "Processor ID", 0}, 404 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Eid), "Processor EID", 0}, 405 {ACPI_DMT_UINT32, ACPI_CPEP0_OFFSET (Interval), "Polling Interval", 0}, 406 ACPI_DMT_TERMINATOR 407 }; 408 409 410 /******************************************************************************* 411 * 412 * CSRT - Core System Resource Table 413 * 414 ******************************************************************************/ 415 416 /* Main table consists only of the standard ACPI table header */ 417 418 /* Resource Group subtable */ 419 420 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt0[] = 421 { 422 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (Length), "Length", DT_LENGTH}, 423 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (VendorId), "Vendor ID", 0}, 424 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (SubvendorId), "Subvendor ID", 0}, 425 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (DeviceId), "Device ID", 0}, 426 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (SubdeviceId), "Subdevice ID", 0}, 427 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (Revision), "Revision", 0}, 428 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (Reserved), "Reserved", 0}, 429 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (SharedInfoLength), "Shared Info Length", 0}, 430 ACPI_DMT_TERMINATOR 431 }; 432 433 /* Shared Info subtable */ 434 435 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt1[] = 436 { 437 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (MajorVersion), "Major Version", 0}, 438 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (MinorVersion), "Minor Version", 0}, 439 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MmioBaseLow), "MMIO Base Address Low", 0}, 440 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MmioBaseHigh), "MMIO Base Address High", 0}, 441 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (GsiInterrupt), "GSI Interrupt", 0}, 442 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (InterruptPolarity), "Interrupt Polarity", 0}, 443 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (InterruptMode), "Interrupt Mode", 0}, 444 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (NumChannels), "Num Channels", 0}, 445 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (DmaAddressWidth), "DMA Address Width", 0}, 446 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (BaseRequestLine), "Base Request Line", 0}, 447 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (NumHandshakeSignals), "Num Handshake Signals", 0}, 448 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MaxBlockSize), "Max Block Size", 0}, 449 ACPI_DMT_TERMINATOR 450 }; 451 452 /* Resource Descriptor subtable */ 453 454 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt2[] = 455 { 456 {ACPI_DMT_UINT32, ACPI_CSRT2_OFFSET (Length), "Length", DT_LENGTH}, 457 {ACPI_DMT_UINT16, ACPI_CSRT2_OFFSET (Type), "Type", 0}, 458 {ACPI_DMT_UINT16, ACPI_CSRT2_OFFSET (Subtype), "Subtype", 0}, 459 {ACPI_DMT_UINT32, ACPI_CSRT2_OFFSET (Uid), "UID", 0}, 460 ACPI_DMT_TERMINATOR 461 }; 462 463 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt2a[] = 464 { 465 {ACPI_DMT_RAW_BUFFER, 0, "ResourceInfo", DT_OPTIONAL}, 466 ACPI_DMT_TERMINATOR 467 }; 468 469 470 /******************************************************************************* 471 * 472 * DBG2 - Debug Port Table 2 473 * 474 ******************************************************************************/ 475 476 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2[] = 477 { 478 {ACPI_DMT_UINT32, ACPI_DBG2_OFFSET (InfoOffset), "Info Offset", 0}, 479 {ACPI_DMT_UINT32, ACPI_DBG2_OFFSET (InfoCount), "Info Count", 0}, 480 ACPI_DMT_TERMINATOR 481 }; 482 483 /* Debug Device Information Subtable */ 484 485 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Device[] = 486 { 487 {ACPI_DMT_UINT8, ACPI_DBG20_OFFSET (Revision), "Revision", 0}, 488 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (Length), "Length", DT_LENGTH}, 489 {ACPI_DMT_UINT8, ACPI_DBG20_OFFSET (RegisterCount), "Register Count", 0}, 490 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (NamepathLength), "Namepath Length", 0}, 491 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (NamepathOffset), "Namepath Offset", 0}, 492 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (OemDataLength), "OEM Data Length", DT_DESCRIBES_OPTIONAL}, 493 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (OemDataOffset), "OEM Data Offset", DT_DESCRIBES_OPTIONAL}, 494 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (PortType), "Port Type", 0}, 495 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (PortSubtype), "Port Subtype", 0}, 496 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (Reserved), "Reserved", 0}, 497 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (BaseAddressOffset), "Base Address Offset", 0}, 498 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (AddressSizeOffset), "Address Size Offset", 0}, 499 ACPI_DMT_TERMINATOR 500 }; 501 502 /* Variable-length data for the subtable */ 503 504 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Addr[] = 505 { 506 {ACPI_DMT_GAS, 0, "Base Address Register", 0}, 507 ACPI_DMT_TERMINATOR 508 }; 509 510 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Size[] = 511 { 512 {ACPI_DMT_UINT32, 0, "Address Size", 0}, 513 ACPI_DMT_TERMINATOR 514 }; 515 516 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Name[] = 517 { 518 {ACPI_DMT_STRING, 0, "Namepath", 0}, 519 ACPI_DMT_TERMINATOR 520 }; 521 522 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2OemData[] = 523 { 524 {ACPI_DMT_RAW_BUFFER, 0, "OEM Data", DT_OPTIONAL}, 525 ACPI_DMT_TERMINATOR 526 }; 527 528 529 /******************************************************************************* 530 * 531 * DBGP - Debug Port 532 * 533 ******************************************************************************/ 534 535 ACPI_DMTABLE_INFO AcpiDmTableInfoDbgp[] = 536 { 537 {ACPI_DMT_UINT8, ACPI_DBGP_OFFSET (Type), "Interface Type", 0}, 538 {ACPI_DMT_UINT24, ACPI_DBGP_OFFSET (Reserved[0]), "Reserved", 0}, 539 {ACPI_DMT_GAS, ACPI_DBGP_OFFSET (DebugPort), "Debug Port Register", 0}, 540 ACPI_DMT_TERMINATOR 541 }; 542 543 544 /******************************************************************************* 545 * 546 * DMAR - DMA Remapping table 547 * 548 ******************************************************************************/ 549 550 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar[] = 551 { 552 {ACPI_DMT_UINT8, ACPI_DMAR_OFFSET (Width), "Host Address Width", 0}, 553 {ACPI_DMT_UINT8, ACPI_DMAR_OFFSET (Flags), "Flags", 0}, 554 {ACPI_DMT_BUF10, ACPI_DMAR_OFFSET (Reserved[0]), "Reserved", 0}, 555 ACPI_DMT_TERMINATOR 556 }; 557 558 /* Common Subtable header (one per Subtable) */ 559 560 ACPI_DMTABLE_INFO AcpiDmTableInfoDmarHdr[] = 561 { 562 {ACPI_DMT_DMAR, ACPI_DMAR0_OFFSET (Header.Type), "Subtable Type", 0}, 563 {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Header.Length), "Length", DT_LENGTH}, 564 ACPI_DMT_TERMINATOR 565 }; 566 567 /* Common device scope entry */ 568 569 ACPI_DMTABLE_INFO AcpiDmTableInfoDmarScope[] = 570 { 571 {ACPI_DMT_DMAR_SCOPE, ACPI_DMARS_OFFSET (EntryType), "Device Scope Type", 0}, 572 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Length), "Entry Length", DT_LENGTH}, 573 {ACPI_DMT_UINT16, ACPI_DMARS_OFFSET (Reserved), "Reserved", 0}, 574 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (EnumerationId), "Enumeration ID", 0}, 575 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Bus), "PCI Bus Number", 0}, 576 ACPI_DMT_TERMINATOR 577 }; 578 579 /* DMAR Subtables */ 580 581 /* 0: Hardware Unit Definition */ 582 583 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar0[] = 584 { 585 {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Flags), "Flags", 0}, 586 {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Reserved), "Reserved", 0}, 587 {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Segment), "PCI Segment Number", 0}, 588 {ACPI_DMT_UINT64, ACPI_DMAR0_OFFSET (Address), "Register Base Address", 0}, 589 ACPI_DMT_TERMINATOR 590 }; 591 592 /* 1: Reserved Memory Definition */ 593 594 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar1[] = 595 { 596 {ACPI_DMT_UINT16, ACPI_DMAR1_OFFSET (Reserved), "Reserved", 0}, 597 {ACPI_DMT_UINT16, ACPI_DMAR1_OFFSET (Segment), "PCI Segment Number", 0}, 598 {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (BaseAddress), "Base Address", 0}, 599 {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (EndAddress), "End Address (limit)", 0}, 600 ACPI_DMT_TERMINATOR 601 }; 602 603 /* 2: Root Port ATS Capability Definition */ 604 605 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar2[] = 606 { 607 {ACPI_DMT_UINT8, ACPI_DMAR2_OFFSET (Flags), "Flags", 0}, 608 {ACPI_DMT_UINT8, ACPI_DMAR2_OFFSET (Reserved), "Reserved", 0}, 609 {ACPI_DMT_UINT16, ACPI_DMAR2_OFFSET (Segment), "PCI Segment Number", 0}, 610 ACPI_DMT_TERMINATOR 611 }; 612 613 /* 3: Remapping Hardware Static Affinity Structure */ 614 615 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar3[] = 616 { 617 {ACPI_DMT_UINT32, ACPI_DMAR3_OFFSET (Reserved), "Reserved", 0}, 618 {ACPI_DMT_UINT64, ACPI_DMAR3_OFFSET (BaseAddress), "Base Address", 0}, 619 {ACPI_DMT_UINT32, ACPI_DMAR3_OFFSET (ProximityDomain), "Proximity Domain", 0}, 620 ACPI_DMT_TERMINATOR 621 }; 622 623 /* 4: ACPI Namespace Device Declaration Structure */ 624 625 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar4[] = 626 { 627 {ACPI_DMT_UINT24, ACPI_DMAR4_OFFSET (Reserved[0]), "Reserved", 0}, 628 {ACPI_DMT_UINT8, ACPI_DMAR4_OFFSET (DeviceNumber), "Device Number", 0}, 629 {ACPI_DMT_STRING, ACPI_DMAR4_OFFSET (DeviceName[0]), "Device Name", 0}, 630 ACPI_DMT_TERMINATOR 631 }; 632 633 634 /******************************************************************************* 635 * 636 * DRTM - Dynamic Root of Trust for Measurement table 637 * 638 ******************************************************************************/ 639 640 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm[] = 641 { 642 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryBaseAddress), "Entry Base Address", 0}, 643 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryLength), "Entry Length", 0}, 644 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (EntryAddress32), "Entry 32", 0}, 645 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryAddress64), "Entry 64", 0}, 646 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (ExitAddress), "Exit Address", 0}, 647 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (LogAreaAddress), "Log Area Start", 0}, 648 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (LogAreaLength), "Log Area Length", 0}, 649 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (ArchDependentAddress), "Arch Dependent Address", 0}, 650 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (Flags), "Flags (decoded below)", 0}, 651 {ACPI_DMT_FLAG0, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Namespace in TCB", 0}, 652 {ACPI_DMT_FLAG1, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Gap Code on S3 Resume", 0}, 653 {ACPI_DMT_FLAG2, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Gap Code on DLME_Exit", 0}, 654 {ACPI_DMT_FLAG3, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "PCR_Authorities Changed", 0}, 655 ACPI_DMT_TERMINATOR 656 }; 657 658 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm0[] = 659 { 660 {ACPI_DMT_UINT32, ACPI_DRTM0_OFFSET (ValidatedTableCount), "Validated Table Count", DT_COUNT}, 661 ACPI_DMT_TERMINATOR 662 }; 663 664 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm0a[] = 665 { 666 {ACPI_DMT_UINT64, 0, "Table Address", DT_OPTIONAL}, 667 ACPI_DMT_TERMINATOR 668 }; 669 670 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm1[] = 671 { 672 {ACPI_DMT_UINT32, ACPI_DRTM1_OFFSET (ResourceCount), "Resource Count", DT_COUNT}, 673 ACPI_DMT_TERMINATOR 674 }; 675 676 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm1a[] = 677 { 678 {ACPI_DMT_UINT56, ACPI_DRTM1a_OFFSET (Size[0]), "Size", DT_OPTIONAL}, 679 {ACPI_DMT_UINT8, ACPI_DRTM1a_OFFSET (Type), "Type", 0}, 680 {ACPI_DMT_FLAG0, ACPI_DRTM1a_FLAG_OFFSET (Type, 0), "Resource Type", 0}, 681 {ACPI_DMT_FLAG7, ACPI_DRTM1a_FLAG_OFFSET (Type, 0), "Protections", 0}, 682 {ACPI_DMT_UINT64, ACPI_DRTM1a_OFFSET (Address), "Address", 0}, 683 ACPI_DMT_TERMINATOR 684 }; 685 686 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm2[] = 687 { 688 {ACPI_DMT_UINT32, ACPI_DRTM2_OFFSET (DpsIdLength), "DLME Platform Id Length", DT_COUNT}, 689 {ACPI_DMT_BUF16, ACPI_DRTM2_OFFSET (DpsId), "DLME Platform Id", DT_COUNT}, 690 ACPI_DMT_TERMINATOR 691 }; 692 693 694 /******************************************************************************* 695 * 696 * ECDT - Embedded Controller Boot Resources Table 697 * 698 ******************************************************************************/ 699 700 ACPI_DMTABLE_INFO AcpiDmTableInfoEcdt[] = 701 { 702 {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Control), "Command/Status Register", 0}, 703 {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Data), "Data Register", 0}, 704 {ACPI_DMT_UINT32, ACPI_ECDT_OFFSET (Uid), "UID", 0}, 705 {ACPI_DMT_UINT8, ACPI_ECDT_OFFSET (Gpe), "GPE Number", 0}, 706 {ACPI_DMT_STRING, ACPI_ECDT_OFFSET (Id[0]), "Namepath", 0}, 707 ACPI_DMT_TERMINATOR 708 }; 709 710 711 /******************************************************************************* 712 * 713 * EINJ - Error Injection table 714 * 715 ******************************************************************************/ 716 717 ACPI_DMTABLE_INFO AcpiDmTableInfoEinj[] = 718 { 719 {ACPI_DMT_UINT32, ACPI_EINJ_OFFSET (HeaderLength), "Injection Header Length", 0}, 720 {ACPI_DMT_UINT8, ACPI_EINJ_OFFSET (Flags), "Flags", 0}, 721 {ACPI_DMT_UINT24, ACPI_EINJ_OFFSET (Reserved[0]), "Reserved", 0}, 722 {ACPI_DMT_UINT32, ACPI_EINJ_OFFSET (Entries), "Injection Entry Count", 0}, 723 ACPI_DMT_TERMINATOR 724 }; 725 726 ACPI_DMTABLE_INFO AcpiDmTableInfoEinj0[] = 727 { 728 {ACPI_DMT_EINJACT, ACPI_EINJ0_OFFSET (Action), "Action", 0}, 729 {ACPI_DMT_EINJINST, ACPI_EINJ0_OFFSET (Instruction), "Instruction", 0}, 730 {ACPI_DMT_UINT8, ACPI_EINJ0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 731 {ACPI_DMT_FLAG0, ACPI_EINJ0_FLAG_OFFSET (Flags,0), "Preserve Register Bits", 0}, 732 733 {ACPI_DMT_UINT8, ACPI_EINJ0_OFFSET (Reserved), "Reserved", 0}, 734 {ACPI_DMT_GAS, ACPI_EINJ0_OFFSET (RegisterRegion), "Register Region", 0}, 735 {ACPI_DMT_UINT64, ACPI_EINJ0_OFFSET (Value), "Value", 0}, 736 {ACPI_DMT_UINT64, ACPI_EINJ0_OFFSET (Mask), "Mask", 0}, 737 ACPI_DMT_TERMINATOR 738 }; 739 740 741 /******************************************************************************* 742 * 743 * ERST - Error Record Serialization table 744 * 745 ******************************************************************************/ 746 747 ACPI_DMTABLE_INFO AcpiDmTableInfoErst[] = 748 { 749 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (HeaderLength), "Serialization Header Length", 0}, 750 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (Reserved), "Reserved", 0}, 751 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (Entries), "Instruction Entry Count", 0}, 752 ACPI_DMT_TERMINATOR 753 }; 754 755 ACPI_DMTABLE_INFO AcpiDmTableInfoErst0[] = 756 { 757 {ACPI_DMT_ERSTACT, ACPI_ERST0_OFFSET (Action), "Action", 0}, 758 {ACPI_DMT_ERSTINST, ACPI_ERST0_OFFSET (Instruction), "Instruction", 0}, 759 {ACPI_DMT_UINT8, ACPI_ERST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 760 {ACPI_DMT_FLAG0, ACPI_ERST0_FLAG_OFFSET (Flags,0), "Preserve Register Bits", 0}, 761 762 {ACPI_DMT_UINT8, ACPI_ERST0_OFFSET (Reserved), "Reserved", 0}, 763 {ACPI_DMT_GAS, ACPI_ERST0_OFFSET (RegisterRegion), "Register Region", 0}, 764 {ACPI_DMT_UINT64, ACPI_ERST0_OFFSET (Value), "Value", 0}, 765 {ACPI_DMT_UINT64, ACPI_ERST0_OFFSET (Mask), "Mask", 0}, 766 ACPI_DMT_TERMINATOR 767 }; 768 769 770 /******************************************************************************* 771 * 772 * FPDT - Firmware Performance Data Table (ACPI 5.0) 773 * 774 ******************************************************************************/ 775 776 /* Main table consists of only the standard ACPI header - subtables follow */ 777 778 /* FPDT subtable header */ 779 780 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdtHdr[] = 781 { 782 {ACPI_DMT_UINT16, ACPI_FPDTH_OFFSET (Type), "Subtable Type", 0}, 783 {ACPI_DMT_UINT8, ACPI_FPDTH_OFFSET (Length), "Length", DT_LENGTH}, 784 {ACPI_DMT_UINT8, ACPI_FPDTH_OFFSET (Revision), "Revision", 0}, 785 ACPI_DMT_TERMINATOR 786 }; 787 788 /* 0: Firmware Basic Boot Performance Record */ 789 790 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdt0[] = 791 { 792 {ACPI_DMT_UINT32, ACPI_FPDT0_OFFSET (Reserved), "Reserved", 0}, 793 {ACPI_DMT_UINT64, ACPI_FPDT1_OFFSET (Address), "FPDT Boot Record Address", 0}, 794 ACPI_DMT_TERMINATOR 795 }; 796 797 /* 1: S3 Performance Table Pointer Record */ 798 799 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdt1[] = 800 { 801 {ACPI_DMT_UINT32, ACPI_FPDT1_OFFSET (Reserved), "Reserved", 0}, 802 {ACPI_DMT_UINT64, ACPI_FPDT1_OFFSET (Address), "S3PT Record Address", 0}, 803 ACPI_DMT_TERMINATOR 804 }; 805 806 #if 0 807 /* Boot Performance Record, not supported at this time. */ 808 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ResetEnd), "Reset End", 0}, 809 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (LoadStart), "Load Image Start", 0}, 810 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (StartupStart), "Start Image Start", 0}, 811 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ExitServicesEntry), "Exit Services Entry", 0}, 812 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ExitServicesExit), "Exit Services Exit", 0}, 813 #endif 814 815 816 /******************************************************************************* 817 * 818 * GTDT - Generic Timer Description Table 819 * 820 ******************************************************************************/ 821 822 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt[] = 823 { 824 {ACPI_DMT_UINT64, ACPI_GTDT_OFFSET (CounterBlockAddresss), "Counter Block Address", 0}, 825 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (Reserved), "Reserved", 0}, 826 ACPI_DMT_NEW_LINE, 827 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (SecureEl1Interrupt), "Secure EL1 Interrupt", 0}, 828 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (SecureEl1Flags), "EL1 Flags (decoded below)", DT_FLAG}, 829 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Trigger Mode", 0}, 830 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Polarity", 0}, 831 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Always On", 0}, 832 ACPI_DMT_NEW_LINE, 833 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl1Interrupt), "Non-Secure EL1 Interrupt", 0}, 834 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl1Flags), "NEL1 Flags (decoded below)", DT_FLAG}, 835 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Trigger Mode", 0}, 836 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Polarity", 0}, 837 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Always On", 0}, 838 ACPI_DMT_NEW_LINE, 839 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (VirtualTimerInterrupt), "Virtual Timer Interrupt", 0}, 840 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (VirtualTimerFlags), "VT Flags (decoded below)", DT_FLAG}, 841 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Trigger Mode", 0}, 842 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Polarity", 0}, 843 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Always On", 0}, 844 ACPI_DMT_NEW_LINE, 845 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl2Interrupt), "Non-Secure EL2 Interrupt", 0}, 846 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl2Flags), "NEL2 Flags (decoded below)", DT_FLAG}, 847 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Trigger Mode", 0}, 848 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Polarity", 0}, 849 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Always On", 0}, 850 {ACPI_DMT_UINT64, ACPI_GTDT_OFFSET (CounterReadBlockAddress), "Counter Read Block Address", 0}, 851 ACPI_DMT_NEW_LINE, 852 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (PlatformTimerCount), "Platform Timer Count", 0}, 853 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (PlatformTimerOffset), "Platform Timer Offset", 0}, 854 ACPI_DMT_TERMINATOR 855 }; 856 857 /* GDTD EL2 timer info. This table is appended to AcpiDmTableInfoGtdt for rev 3 and later */ 858 859 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdtEl2[] = 860 { 861 {ACPI_DMT_UINT32, ACPI_GTDT_EL2_OFFSET (VirtualEL2TimerGsiv), "Virtual EL2 Timer GSIV", 0}, 862 {ACPI_DMT_UINT32, ACPI_GTDT_EL2_OFFSET (VirtualEL2TimerFlags), "Virtual EL2 Timer Flags", 0}, 863 ACPI_DMT_TERMINATOR 864 }; 865 866 /* GTDT Subtable header (one per Subtable) */ 867 868 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdtHdr[] = 869 { 870 {ACPI_DMT_GTDT, ACPI_GTDTH_OFFSET (Type), "Subtable Type", 0}, 871 {ACPI_DMT_UINT16, ACPI_GTDTH_OFFSET (Length), "Length", DT_LENGTH}, 872 ACPI_DMT_TERMINATOR 873 }; 874 875 /* GTDT Subtables */ 876 877 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt0[] = 878 { 879 {ACPI_DMT_UINT8, ACPI_GTDT0_OFFSET (Reserved), "Reserved", 0}, 880 {ACPI_DMT_UINT64, ACPI_GTDT0_OFFSET (BlockAddress), "Block Address", 0}, 881 {ACPI_DMT_UINT32, ACPI_GTDT0_OFFSET (TimerCount), "Timer Count", 0}, 882 {ACPI_DMT_UINT32, ACPI_GTDT0_OFFSET (TimerOffset), "Timer Offset", 0}, 883 ACPI_DMT_TERMINATOR 884 }; 885 886 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt0a[] = 887 { 888 {ACPI_DMT_UINT8 , ACPI_GTDT0a_OFFSET (FrameNumber), "Frame Number", 0}, 889 {ACPI_DMT_UINT24, ACPI_GTDT0a_OFFSET (Reserved[0]), "Reserved", 0}, 890 {ACPI_DMT_UINT64, ACPI_GTDT0a_OFFSET (BaseAddress), "Base Address", 0}, 891 {ACPI_DMT_UINT64, ACPI_GTDT0a_OFFSET (El0BaseAddress), "EL0 Base Address", 0}, 892 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (TimerInterrupt), "Timer Interrupt", 0}, 893 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (TimerFlags), "Timer Flags (decoded below)", 0}, 894 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (TimerFlags,0), "Trigger Mode", 0}, 895 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (TimerFlags,0), "Polarity", 0}, 896 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (VirtualTimerInterrupt), "Virtual Timer Interrupt", 0}, 897 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (VirtualTimerFlags), "Virtual Timer Flags (decoded below)", 0}, 898 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (VirtualTimerFlags,0), "Trigger Mode", 0}, 899 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (VirtualTimerFlags,0), "Polarity", 0}, 900 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (CommonFlags), "Common Flags (decoded below)", 0}, 901 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (CommonFlags,0), "Secure", 0}, 902 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (CommonFlags,0), "Always On", 0}, 903 ACPI_DMT_TERMINATOR 904 }; 905 906 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt1[] = 907 { 908 {ACPI_DMT_UINT8, ACPI_GTDT1_OFFSET (Reserved), "Reserved", 0}, 909 {ACPI_DMT_UINT64, ACPI_GTDT1_OFFSET (RefreshFrameAddress), "Refresh Frame Address", 0}, 910 {ACPI_DMT_UINT64, ACPI_GTDT1_OFFSET (ControlFrameAddress), "Control Frame Address", 0}, 911 {ACPI_DMT_UINT32, ACPI_GTDT1_OFFSET (TimerInterrupt), "Timer Interrupt", 0}, 912 {ACPI_DMT_UINT32, ACPI_GTDT1_OFFSET (TimerFlags), "Timer Flags (decoded below)", DT_FLAG}, 913 {ACPI_DMT_FLAG0, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Trigger Mode", 0}, 914 {ACPI_DMT_FLAG1, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Polarity", 0}, 915 {ACPI_DMT_FLAG2, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Security", 0}, 916 ACPI_DMT_TERMINATOR 917 }; 918 919 920 /******************************************************************************* 921 * 922 * HEST - Hardware Error Source table 923 * 924 ******************************************************************************/ 925 926 ACPI_DMTABLE_INFO AcpiDmTableInfoHest[] = 927 { 928 {ACPI_DMT_UINT32, ACPI_HEST_OFFSET (ErrorSourceCount), "Error Source Count", 0}, 929 ACPI_DMT_TERMINATOR 930 }; 931 932 /* Common HEST structures for subtables */ 933 934 #define ACPI_DM_HEST_HEADER \ 935 {ACPI_DMT_HEST, ACPI_HEST0_OFFSET (Header.Type), "Subtable Type", 0}, \ 936 {ACPI_DMT_UINT16, ACPI_HEST0_OFFSET (Header.SourceId), "Source Id", 0} 937 938 #define ACPI_DM_HEST_AER \ 939 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Reserved1), "Reserved", 0}, \ 940 {ACPI_DMT_UINT8, ACPI_HEST6_OFFSET (Aer.Flags), "Flags (decoded below)", DT_FLAG}, \ 941 {ACPI_DMT_FLAG0, ACPI_HEST6_FLAG_OFFSET (Aer.Flags,0), "Firmware First", 0}, \ 942 {ACPI_DMT_FLAG0, ACPI_HEST6_FLAG_OFFSET (Aer.Flags,0), "Global", 0}, \ 943 {ACPI_DMT_UINT8, ACPI_HEST6_OFFSET (Aer.Enabled), "Enabled", 0}, \ 944 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.RecordsToPreallocate), "Records To Preallocate", 0}, \ 945 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.MaxSectionsPerRecord), "Max Sections Per Record", 0}, \ 946 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.Bus), "Bus", 0}, \ 947 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Device), "Device", 0}, \ 948 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Function), "Function", 0}, \ 949 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.DeviceControl), "DeviceControl", 0}, \ 950 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Reserved2), "Reserved", 0}, \ 951 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.UncorrectableMask), "Uncorrectable Mask", 0}, \ 952 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.UncorrectableSeverity), "Uncorrectable Severity", 0}, \ 953 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.CorrectableMask), "Correctable Mask", 0}, \ 954 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.AdvancedCapabilities), "Advanced Capabilities", 0} 955 956 957 /* HEST Subtables */ 958 959 /* 0: IA32 Machine Check Exception */ 960 961 ACPI_DMTABLE_INFO AcpiDmTableInfoHest0[] = 962 { 963 ACPI_DM_HEST_HEADER, 964 {ACPI_DMT_UINT16, ACPI_HEST0_OFFSET (Reserved1), "Reserved1", 0}, 965 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 966 {ACPI_DMT_FLAG0, ACPI_HEST0_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 967 {ACPI_DMT_FLAG2, ACPI_HEST0_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 968 969 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (Enabled), "Enabled", 0}, 970 {ACPI_DMT_UINT32, ACPI_HEST0_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 971 {ACPI_DMT_UINT32, ACPI_HEST0_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 972 {ACPI_DMT_UINT64, ACPI_HEST0_OFFSET (GlobalCapabilityData), "Global Capability Data", 0}, 973 {ACPI_DMT_UINT64, ACPI_HEST0_OFFSET (GlobalControlData), "Global Control Data", 0}, 974 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 975 {ACPI_DMT_UINT56, ACPI_HEST0_OFFSET (Reserved3[0]), "Reserved2", 0}, 976 ACPI_DMT_TERMINATOR 977 }; 978 979 /* 1: IA32 Corrected Machine Check */ 980 981 ACPI_DMTABLE_INFO AcpiDmTableInfoHest1[] = 982 { 983 ACPI_DM_HEST_HEADER, 984 {ACPI_DMT_UINT16, ACPI_HEST1_OFFSET (Reserved1), "Reserved1", 0}, 985 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 986 {ACPI_DMT_FLAG0, ACPI_HEST1_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 987 {ACPI_DMT_FLAG2, ACPI_HEST1_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 988 989 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (Enabled), "Enabled", 0}, 990 {ACPI_DMT_UINT32, ACPI_HEST1_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 991 {ACPI_DMT_UINT32, ACPI_HEST1_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 992 {ACPI_DMT_HESTNTFY, ACPI_HEST1_OFFSET (Notify), "Notify", 0}, 993 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 994 {ACPI_DMT_UINT24, ACPI_HEST1_OFFSET (Reserved2[0]), "Reserved2", 0}, 995 ACPI_DMT_TERMINATOR 996 }; 997 998 /* 2: IA32 Non-Maskable Interrupt */ 999 1000 ACPI_DMTABLE_INFO AcpiDmTableInfoHest2[] = 1001 { 1002 ACPI_DM_HEST_HEADER, 1003 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (Reserved), "Reserved", 0}, 1004 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1005 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1006 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1007 ACPI_DMT_TERMINATOR 1008 }; 1009 1010 /* 6: PCI Express Root Port AER */ 1011 1012 ACPI_DMTABLE_INFO AcpiDmTableInfoHest6[] = 1013 { 1014 ACPI_DM_HEST_HEADER, 1015 ACPI_DM_HEST_AER, 1016 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (RootErrorCommand), "Root Error Command", 0}, 1017 ACPI_DMT_TERMINATOR 1018 }; 1019 1020 /* 7: PCI Express AER (AER Endpoint) */ 1021 1022 ACPI_DMTABLE_INFO AcpiDmTableInfoHest7[] = 1023 { 1024 ACPI_DM_HEST_HEADER, 1025 ACPI_DM_HEST_AER, 1026 ACPI_DMT_TERMINATOR 1027 }; 1028 1029 /* 8: PCI Express/PCI-X Bridge AER */ 1030 1031 ACPI_DMTABLE_INFO AcpiDmTableInfoHest8[] = 1032 { 1033 ACPI_DM_HEST_HEADER, 1034 ACPI_DM_HEST_AER, 1035 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (UncorrectableMask2), "2nd Uncorrectable Mask", 0}, 1036 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (UncorrectableSeverity2), "2nd Uncorrectable Severity", 0}, 1037 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (AdvancedCapabilities2), "2nd Advanced Capabilities", 0}, 1038 ACPI_DMT_TERMINATOR 1039 }; 1040 1041 /* 9: Generic Hardware Error Source */ 1042 1043 ACPI_DMTABLE_INFO AcpiDmTableInfoHest9[] = 1044 { 1045 ACPI_DM_HEST_HEADER, 1046 {ACPI_DMT_UINT16, ACPI_HEST9_OFFSET (RelatedSourceId), "Related Source Id", 0}, 1047 {ACPI_DMT_UINT8, ACPI_HEST9_OFFSET (Reserved), "Reserved", 0}, 1048 {ACPI_DMT_UINT8, ACPI_HEST9_OFFSET (Enabled), "Enabled", 0}, 1049 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1050 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1051 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1052 {ACPI_DMT_GAS, ACPI_HEST9_OFFSET (ErrorStatusAddress), "Error Status Address", 0}, 1053 {ACPI_DMT_HESTNTFY, ACPI_HEST9_OFFSET (Notify), "Notify", 0}, 1054 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (ErrorBlockLength), "Error Status Block Length", 0}, 1055 ACPI_DMT_TERMINATOR 1056 }; 1057 1058 /* 10: Generic Hardware Error Source - Version 2 */ 1059 1060 ACPI_DMTABLE_INFO AcpiDmTableInfoHest10[] = 1061 { 1062 ACPI_DM_HEST_HEADER, 1063 {ACPI_DMT_UINT16, ACPI_HEST10_OFFSET (RelatedSourceId), "Related Source Id", 0}, 1064 {ACPI_DMT_UINT8, ACPI_HEST10_OFFSET (Reserved), "Reserved", 0}, 1065 {ACPI_DMT_UINT8, ACPI_HEST10_OFFSET (Enabled), "Enabled", 0}, 1066 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1067 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1068 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1069 {ACPI_DMT_GAS, ACPI_HEST10_OFFSET (ErrorStatusAddress), "Error Status Address", 0}, 1070 {ACPI_DMT_HESTNTFY, ACPI_HEST10_OFFSET (Notify), "Notify", 0}, 1071 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (ErrorBlockLength), "Error Status Block Length", 0}, 1072 {ACPI_DMT_GAS, ACPI_HEST10_OFFSET (ReadAckRegister), "Read Ack Register", 0}, 1073 {ACPI_DMT_UINT64, ACPI_HEST10_OFFSET (ReadAckPreserve), "Read Ack Preserve", 0}, 1074 {ACPI_DMT_UINT64, ACPI_HEST10_OFFSET (ReadAckWrite), "Read Ack Write", 0}, 1075 ACPI_DMT_TERMINATOR 1076 }; 1077 1078 /* 11: IA32 Deferred Machine Check */ 1079 1080 ACPI_DMTABLE_INFO AcpiDmTableInfoHest11[] = 1081 { 1082 ACPI_DM_HEST_HEADER, 1083 {ACPI_DMT_UINT16, ACPI_HEST11_OFFSET (Reserved1), "Reserved1", 0}, 1084 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1085 {ACPI_DMT_FLAG0, ACPI_HEST11_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1086 {ACPI_DMT_FLAG2, ACPI_HEST11_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1087 1088 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (Enabled), "Enabled", 0}, 1089 {ACPI_DMT_UINT32, ACPI_HEST11_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1090 {ACPI_DMT_UINT32, ACPI_HEST11_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1091 {ACPI_DMT_HESTNTFY, ACPI_HEST11_OFFSET (Notify), "Notify", 0}, 1092 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1093 {ACPI_DMT_UINT24, ACPI_HEST11_OFFSET (Reserved2[0]), "Reserved2", 0}, 1094 ACPI_DMT_TERMINATOR 1095 }; 1096 1097 /* Notification Structure */ 1098 1099 ACPI_DMTABLE_INFO AcpiDmTableInfoHestNotify[] = 1100 { 1101 {ACPI_DMT_HESTNTYP, ACPI_HESTN_OFFSET (Type), "Notify Type", 0}, 1102 {ACPI_DMT_UINT8, ACPI_HESTN_OFFSET (Length), "Notify Length", DT_LENGTH}, 1103 {ACPI_DMT_UINT16, ACPI_HESTN_OFFSET (ConfigWriteEnable), "Configuration Write Enable", 0}, 1104 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollInterval), "PollInterval", 0}, 1105 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (Vector), "Vector", 0}, 1106 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollingThresholdValue), "Polling Threshold Value", 0}, 1107 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollingThresholdWindow), "Polling Threshold Window", 0}, 1108 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (ErrorThresholdValue), "Error Threshold Value", 0}, 1109 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (ErrorThresholdWindow), "Error Threshold Window", 0}, 1110 ACPI_DMT_TERMINATOR 1111 }; 1112 1113 1114 /* 1115 * IA32 Error Bank(s) - Follows the ACPI_HEST_IA_MACHINE_CHECK and 1116 * ACPI_HEST_IA_CORRECTED structures. 1117 */ 1118 ACPI_DMTABLE_INFO AcpiDmTableInfoHestBank[] = 1119 { 1120 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (BankNumber), "Bank Number", 0}, 1121 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (ClearStatusOnInit), "Clear Status On Init", 0}, 1122 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (StatusFormat), "Status Format", 0}, 1123 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (Reserved), "Reserved", 0}, 1124 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (ControlRegister), "Control Register", 0}, 1125 {ACPI_DMT_UINT64, ACPI_HESTB_OFFSET (ControlData), "Control Data", 0}, 1126 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (StatusRegister), "Status Register", 0}, 1127 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (AddressRegister), "Address Register", 0}, 1128 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (MiscRegister), "Misc Register", 0}, 1129 ACPI_DMT_TERMINATOR 1130 }; 1131 1132 1133 /******************************************************************************* 1134 * 1135 * HMAT - Heterogeneous Memory Attributes Table 1136 * 1137 ******************************************************************************/ 1138 1139 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat[] = 1140 { 1141 {ACPI_DMT_UINT32, ACPI_HMAT_OFFSET (Reserved), "Reserved", 0}, 1142 ACPI_DMT_TERMINATOR 1143 }; 1144 1145 /* Common HMAT structure header (one per Subtable) */ 1146 1147 ACPI_DMTABLE_INFO AcpiDmTableInfoHmatHdr[] = 1148 { 1149 {ACPI_DMT_HMAT, ACPI_HMATH_OFFSET (Type), "Structure Type", 0}, 1150 {ACPI_DMT_UINT16, ACPI_HMATH_OFFSET (Reserved), "Reserved", 0}, 1151 {ACPI_DMT_UINT32, ACPI_HMATH_OFFSET (Length), "Length", 0}, 1152 ACPI_DMT_TERMINATOR 1153 }; 1154 1155 /* HMAT subtables */ 1156 1157 /* 0x00: Memory proximity domain attributes */ 1158 1159 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat0[] = 1160 { 1161 {ACPI_DMT_UINT16, ACPI_HMAT0_OFFSET (Flags), "Flags (decoded below)", 0}, 1162 {ACPI_DMT_FLAG0, ACPI_HMAT0_FLAG_OFFSET (Flags,0), "Processor Proximity Domain Valid", 0}, 1163 {ACPI_DMT_UINT16, ACPI_HMAT0_OFFSET (Reserved1), "Reserved1", 0}, 1164 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (InitiatorPD), "Attached Initiator Proximity Domain", 0}, 1165 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (MemoryPD), "Memory Proximity Domain", 0}, 1166 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (Reserved2), "Reserved2", 0}, 1167 {ACPI_DMT_UINT64, ACPI_HMAT0_OFFSET (Reserved3), "Reserved3", 0}, 1168 {ACPI_DMT_UINT64, ACPI_HMAT0_OFFSET (Reserved4), "Reserved4", 0}, 1169 ACPI_DMT_TERMINATOR 1170 }; 1171 1172 /* 0x01: System Locality Latency and Bandwidth Information */ 1173 1174 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1[] = 1175 { 1176 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (Flags), "Flags (decoded below)", 0}, 1177 {ACPI_DMT_FLAGS4_0, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Memory Hierarchy", 0}, /* First 4 bits */ 1178 {ACPI_DMT_FLAG4, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Use Minimum Transfer Size", 0}, 1179 {ACPI_DMT_FLAG5, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Non-sequential Transfers", 0}, 1180 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (DataType), "Data Type", 0}, 1181 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (MinTransferSize), "Minimum Transfer Size", 0}, 1182 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (Reserved1), "Reserved1", 0}, 1183 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (NumberOfInitiatorPDs), "Initiator Proximity Domains #", 0}, 1184 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (NumberOfTargetPDs), "Target Proximity Domains #", 0}, 1185 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (Reserved2), "Reserved2", 0}, 1186 {ACPI_DMT_UINT64, ACPI_HMAT1_OFFSET (EntryBaseUnit), "Entry Base Unit", 0}, 1187 ACPI_DMT_TERMINATOR 1188 }; 1189 1190 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1a[] = 1191 { 1192 {ACPI_DMT_UINT32, 0, "Initiator Proximity Domain List", DT_OPTIONAL}, 1193 ACPI_DMT_TERMINATOR 1194 }; 1195 1196 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1b[] = 1197 { 1198 {ACPI_DMT_UINT32, 0, "Target Proximity Domain List", DT_OPTIONAL}, 1199 ACPI_DMT_TERMINATOR 1200 }; 1201 1202 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1c[] = 1203 { 1204 {ACPI_DMT_UINT16, 0, "Entry", DT_OPTIONAL}, 1205 ACPI_DMT_TERMINATOR 1206 }; 1207 1208 /* 0x02: Memory Side Cache Information */ 1209 1210 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat2[] = 1211 { 1212 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (MemoryPD), "Memory Proximity Domain", 0}, 1213 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (Reserved1), "Reserved1", 0}, 1214 {ACPI_DMT_UINT64, ACPI_HMAT2_OFFSET (CacheSize), "Memory Side Cache Size", 0}, 1215 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (CacheAttributes), "Cache Attributes (decoded below)", 0}, 1216 {ACPI_DMT_FLAGS4_0, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Total Cache Levels", 0}, 1217 {ACPI_DMT_FLAGS4_4, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Level", 0}, 1218 {ACPI_DMT_FLAGS4_8, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Associativity", 0}, 1219 {ACPI_DMT_FLAGS4_12, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Write Policy", 0}, 1220 {ACPI_DMT_FLAGS16_16, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Line Size", 0}, 1221 {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (Reserved2), "Reserved2", 0}, 1222 {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (NumberOfSMBIOSHandles), "SMBIOS Handle #", 0}, 1223 ACPI_DMT_TERMINATOR 1224 }; 1225 1226 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat2a[] = 1227 { 1228 {ACPI_DMT_UINT16, 0, "SMBIOS Handle", DT_OPTIONAL}, 1229 ACPI_DMT_TERMINATOR 1230 }; 1231 1232 1233 /******************************************************************************* 1234 * 1235 * HPET - High Precision Event Timer table 1236 * 1237 ******************************************************************************/ 1238 1239 ACPI_DMTABLE_INFO AcpiDmTableInfoHpet[] = 1240 { 1241 {ACPI_DMT_UINT32, ACPI_HPET_OFFSET (Id), "Hardware Block ID", 0}, 1242 {ACPI_DMT_GAS, ACPI_HPET_OFFSET (Address), "Timer Block Register", 0}, 1243 {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Sequence), "Sequence Number", 0}, 1244 {ACPI_DMT_UINT16, ACPI_HPET_OFFSET (MinimumTick), "Minimum Clock Ticks", 0}, 1245 {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1246 {ACPI_DMT_FLAG0, ACPI_HPET_FLAG_OFFSET (Flags,0), "4K Page Protect", 0}, 1247 {ACPI_DMT_FLAG1, ACPI_HPET_FLAG_OFFSET (Flags,0), "64K Page Protect", 0}, 1248 ACPI_DMT_TERMINATOR 1249 }; 1250 /*! [End] no source code translation !*/ 1251