1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "opt_ah.h" 18 19 #include "ah.h" 20 #include "ah_internal.h" 21 #include "ah_devid.h" 22 23 #include "ar9300/ar9300desc.h" 24 #include "ar9300/ar9300.h" 25 #include "ar9300/ar9300reg.h" 26 #include "ar9300/ar9300phy.h" 27 #include "ar9300/ar9300paprd.h" 28 29 #include "ar9300/ar9300_stub.h" 30 #include "ar9300/ar9300_stub_funcs.h" 31 32 33 /* Add static register initialization vectors */ 34 #include "ar9300/ar9300_osprey22.ini" 35 #include "ar9300/ar9330_11.ini" 36 #include "ar9300/ar9330_12.ini" 37 #include "ar9300/ar9340.ini" 38 #include "ar9300/ar9485.ini" 39 #include "ar9300/ar9485_1_1.ini" 40 #include "ar9300/ar9300_jupiter10.ini" 41 #include "ar9300/ar9300_jupiter20.ini" 42 #include "ar9300/ar9580.ini" 43 #include "ar9300/ar955x.ini" 44 #include "ar9300/ar9300_aphrodite10.ini" 45 46 47 /* Include various freebsd specific HAL methods */ 48 #include "ar9300/ar9300_freebsd.h" 49 50 /* XXX duplicate in ar9300_radio.c ? */ 51 static HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah, 52 struct ieee80211_channel *chan); 53 54 static inline HAL_STATUS ar9300_init_mac_addr(struct ath_hal *ah); 55 static inline HAL_STATUS ar9300_hw_attach(struct ath_hal *ah); 56 static inline void ar9300_hw_detach(struct ath_hal *ah); 57 static int16_t ar9300_get_nf_adjust(struct ath_hal *ah, 58 const HAL_CHANNEL_INTERNAL *c); 59 #if 0 60 int ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 61 HAL_CAL_QUERY query); 62 #endif 63 64 #if ATH_TRAFFIC_FAST_RECOVER 65 unsigned long ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah); 66 #endif 67 static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid); 68 69 70 static void 71 ar9300_disable_pcie_phy(struct ath_hal *ah); 72 73 static const HAL_PERCAL_DATA iq_cal_single_sample = 74 {IQ_MISMATCH_CAL, 75 MIN_CAL_SAMPLES, 76 PER_MAX_LOG_COUNT, 77 ar9300_iq_cal_collect, 78 ar9300_iq_calibration}; 79 80 #if 0 81 static HAL_CALIBRATION_TIMER ar9300_cals[] = 82 { {IQ_MISMATCH_CAL, /* Cal type */ 83 1200000, /* Cal interval */ 84 0 /* Cal timestamp */ 85 }, 86 {TEMP_COMP_CAL, 87 5000, 88 0 89 }, 90 }; 91 #endif 92 93 #if ATH_PCIE_ERROR_MONITOR 94 95 int ar9300_start_pcie_error_monitor(struct ath_hal *ah, int b_auto_stop) 96 { 97 u_int32_t val; 98 99 /* Clear the counters */ 100 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR0, 0); 101 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR1, 0); 102 103 /* Read the previous value */ 104 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 105 106 /* Set auto_stop */ 107 if (b_auto_stop) { 108 val |= 109 RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 110 BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 111 RPLY_NUM_RO_ERR_CTR_AUTO_STOP; 112 } else { 113 val &= ~( 114 RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 115 BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 116 RPLY_NUM_RO_ERR_CTR_AUTO_STOP); 117 } 118 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 119 120 /* 121 * Start to run. 122 * This has to be done separately from the above auto_stop flag setting, 123 * to avoid a HW race condition. 124 */ 125 val |= 126 RCVD_ERR_CTR_RUN | BAD_TLP_ERR_CTR_RUN | BAD_DLLP_ERR_CTR_RUN | 127 RPLY_TO_ERR_CTR_RUN | RPLY_NUM_RO_ERR_CTR_RUN; 128 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val); 129 130 return 0; 131 } 132 133 int ar9300_read_pcie_error_monitor(struct ath_hal *ah, void* p_read_counters) 134 { 135 u_int32_t val; 136 ar_pcie_error_moniter_counters *p_counters = 137 (ar_pcie_error_moniter_counters*) p_read_counters; 138 139 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR0); 140 141 p_counters->uc_receiver_errors = MS(val, RCVD_ERR_MASK); 142 p_counters->uc_bad_tlp_errors = MS(val, BAD_TLP_ERR_MASK); 143 p_counters->uc_bad_dllp_errors = MS(val, BAD_DLLP_ERR_MASK); 144 145 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR1); 146 147 p_counters->uc_replay_timeout_errors = MS(val, RPLY_TO_ERR_MASK); 148 p_counters->uc_replay_number_rollover_errors= MS(val, RPLY_NUM_RO_ERR_MASK); 149 150 return 0; 151 } 152 153 int ar9300_stop_pcie_error_monitor(struct ath_hal *ah) 154 { 155 u_int32_t val; 156 157 /* Read the previous value */ 158 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 159 160 val &= ~( 161 RCVD_ERR_CTR_RUN | 162 BAD_TLP_ERR_CTR_RUN | 163 BAD_DLLP_ERR_CTR_RUN | 164 RPLY_TO_ERR_CTR_RUN | 165 RPLY_NUM_RO_ERR_CTR_RUN); 166 167 /* Start to stop */ 168 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 169 170 return 0; 171 } 172 173 #endif /* ATH_PCIE_ERROR_MONITOR */ 174 175 #if 0 176 /* WIN32 does not support C99 */ 177 static const struct ath_hal_private ar9300hal = { 178 { 179 ar9300_get_rate_table, /* ah_get_rate_table */ 180 ar9300_detach, /* ah_detach */ 181 182 /* Reset Functions */ 183 ar9300_reset, /* ah_reset */ 184 ar9300_phy_disable, /* ah_phy_disable */ 185 ar9300_disable, /* ah_disable */ 186 ar9300_config_pci_power_save, /* ah_config_pci_power_save */ 187 ar9300_set_pcu_config, /* ah_set_pcu_config */ 188 ar9300_calibration, /* ah_per_calibration */ 189 ar9300_reset_cal_valid, /* ah_reset_cal_valid */ 190 ar9300_set_tx_power_limit, /* ah_set_tx_power_limit */ 191 192 #if ATH_ANT_DIV_COMB 193 ar9300_ant_ctrl_set_lna_div_use_bt_ant, /* ah_ant_ctrl_set_lna_div_use_bt_ant */ 194 #endif /* ATH_ANT_DIV_COMB */ 195 #ifdef ATH_SUPPORT_DFS 196 ar9300_radar_wait, /* ah_radar_wait */ 197 198 /* New DFS functions */ 199 ar9300_check_dfs, /* ah_ar_check_dfs */ 200 ar9300_dfs_found, /* ah_ar_dfs_found */ 201 ar9300_enable_dfs, /* ah_ar_enable_dfs */ 202 ar9300_get_dfs_thresh, /* ah_ar_get_dfs_thresh */ 203 ar9300_get_dfs_radars, /* ah_ar_get_dfs_radars */ 204 ar9300_adjust_difs, /* ah_adjust_difs */ 205 ar9300_dfs_config_fft, /* ah_dfs_config_fft */ 206 ar9300_dfs_cac_war, /* ah_dfs_cac_war */ 207 ar9300_cac_tx_quiet, /* ah_cac_tx_quiet */ 208 #endif 209 ar9300_get_extension_channel, /* ah_get_extension_channel */ 210 ar9300_is_fast_clock_enabled, /* ah_is_fast_clock_enabled */ 211 212 /* Transmit functions */ 213 ar9300_update_tx_trig_level, /* ah_update_tx_trig_level */ 214 ar9300_get_tx_trig_level, /* ah_get_tx_trig_level */ 215 ar9300_setup_tx_queue, /* ah_setup_tx_queue */ 216 ar9300_set_tx_queue_props, /* ah_set_tx_queue_props */ 217 ar9300_get_tx_queue_props, /* ah_get_tx_queue_props */ 218 ar9300_release_tx_queue, /* ah_release_tx_queue */ 219 ar9300_reset_tx_queue, /* ah_reset_tx_queue */ 220 ar9300_get_tx_dp, /* ah_get_tx_dp */ 221 ar9300_set_tx_dp, /* ah_set_tx_dp */ 222 ar9300_num_tx_pending, /* ah_num_tx_pending */ 223 ar9300_start_tx_dma, /* ah_start_tx_dma */ 224 ar9300_stop_tx_dma, /* ah_stop_tx_dma */ 225 ar9300_stop_tx_dma_indv_que, /* ah_stop_tx_dma_indv_que */ 226 ar9300_abort_tx_dma, /* ah_abort_tx_dma */ 227 ar9300_fill_tx_desc, /* ah_fill_tx_desc */ 228 ar9300_set_desc_link, /* ah_set_desc_link */ 229 ar9300_get_desc_link_ptr, /* ah_get_desc_link_ptr */ 230 ar9300_clear_tx_desc_status, /* ah_clear_tx_desc_status */ 231 #ifdef ATH_SWRETRY 232 ar9300_clear_dest_mask, /* ah_clear_dest_mask */ 233 #endif 234 ar9300_proc_tx_desc, /* ah_proc_tx_desc */ 235 ar9300_get_raw_tx_desc, /* ah_get_raw_tx_desc */ 236 ar9300_get_tx_rate_code, /* ah_get_tx_rate_code */ 237 AH_NULL, /* ah_get_tx_intr_queue */ 238 ar9300_tx_req_intr_desc, /* ah_req_tx_intr_desc */ 239 ar9300_calc_tx_airtime, /* ah_calc_tx_airtime */ 240 ar9300_setup_tx_status_ring, /* ah_setup_tx_status_ring */ 241 242 /* RX Functions */ 243 ar9300_get_rx_dp, /* ah_get_rx_dp */ 244 ar9300_set_rx_dp, /* ah_set_rx_dp */ 245 ar9300_enable_receive, /* ah_enable_receive */ 246 ar9300_stop_dma_receive, /* ah_stop_dma_receive */ 247 ar9300_start_pcu_receive, /* ah_start_pcu_receive */ 248 ar9300_stop_pcu_receive, /* ah_stop_pcu_receive */ 249 ar9300_set_multicast_filter, /* ah_set_multicast_filter */ 250 ar9300_get_rx_filter, /* ah_get_rx_filter */ 251 ar9300_set_rx_filter, /* ah_set_rx_filter */ 252 ar9300_set_rx_sel_evm, /* ah_set_rx_sel_evm */ 253 ar9300_set_rx_abort, /* ah_set_rx_abort */ 254 AH_NULL, /* ah_setup_rx_desc */ 255 ar9300_proc_rx_desc, /* ah_proc_rx_desc */ 256 ar9300_get_rx_key_idx, /* ah_get_rx_key_idx */ 257 ar9300_proc_rx_desc_fast, /* ah_proc_rx_desc_fast */ 258 ar9300_ani_ar_poll, /* ah_rx_monitor */ 259 ar9300_process_mib_intr, /* ah_proc_mib_event */ 260 261 /* Misc Functions */ 262 ar9300_get_capability, /* ah_get_capability */ 263 ar9300_set_capability, /* ah_set_capability */ 264 ar9300_get_diag_state, /* ah_get_diag_state */ 265 ar9300_get_mac_address, /* ah_get_mac_address */ 266 ar9300_set_mac_address, /* ah_set_mac_address */ 267 ar9300_get_bss_id_mask, /* ah_get_bss_id_mask */ 268 ar9300_set_bss_id_mask, /* ah_set_bss_id_mask */ 269 ar9300_set_regulatory_domain, /* ah_set_regulatory_domain */ 270 ar9300_set_led_state, /* ah_set_led_state */ 271 ar9300_set_power_led_state, /* ah_setpowerledstate */ 272 ar9300_set_network_led_state, /* ah_setnetworkledstate */ 273 ar9300_write_associd, /* ah_write_associd */ 274 ar9300_force_tsf_sync, /* ah_force_tsf_sync */ 275 ar9300_gpio_cfg_input, /* ah_gpio_cfg_input */ 276 ar9300_gpio_cfg_output, /* ah_gpio_cfg_output */ 277 ar9300_gpio_cfg_output_led_off, /* ah_gpio_cfg_output_led_off */ 278 ar9300_gpio_get, /* ah_gpio_get */ 279 ar9300_gpio_set, /* ah_gpio_set */ 280 ar9300_gpio_get_intr, /* ah_gpio_get_intr */ 281 ar9300_gpio_set_intr, /* ah_gpio_set_intr */ 282 ar9300_gpio_get_polarity, /* ah_gpio_get_polarity */ 283 ar9300_gpio_set_polarity, /* ah_gpio_set_polarity */ 284 ar9300_gpio_get_mask, /* ah_gpio_get_mask */ 285 ar9300_gpio_set_mask, /* ah_gpio_set_mask */ 286 ar9300_get_tsf32, /* ah_get_tsf32 */ 287 ar9300_get_tsf64, /* ah_get_tsf64 */ 288 ar9300_get_tsf2_32, /* ah_get_tsf2_32 */ 289 ar9300_reset_tsf, /* ah_reset_tsf */ 290 ar9300_detect_card_present, /* ah_detect_card_present */ 291 ar9300_update_mib_mac_stats, /* ah_update_mib_mac_stats */ 292 ar9300_get_mib_mac_stats, /* ah_get_mib_mac_stats */ 293 ar9300_get_rfgain, /* ah_get_rf_gain */ 294 ar9300_get_def_antenna, /* ah_get_def_antenna */ 295 ar9300_set_def_antenna, /* ah_set_def_antenna */ 296 ar9300_set_slot_time, /* ah_set_slot_time */ 297 ar9300_set_ack_timeout, /* ah_set_ack_timeout */ 298 ar9300_get_ack_timeout, /* ah_get_ack_timeout */ 299 ar9300_set_coverage_class, /* ah_set_coverage_class */ 300 ar9300_set_quiet, /* ah_set_quiet */ 301 ar9300_set_antenna_switch, /* ah_set_antenna_switch */ 302 ar9300_get_desc_info, /* ah_get_desc_info */ 303 ar9300_select_ant_config, /* ah_select_ant_config */ 304 ar9300_ant_ctrl_common_get, /* ah_ant_ctrl_common_get */ 305 ar9300_enable_tpc, /* ah_enable_tpc */ 306 AH_NULL, /* ah_olpc_temp_compensation */ 307 #if ATH_SUPPORT_CRDC 308 ar9300_chain_rssi_diff_compensation,/*ah_chain_rssi_diff_compensation*/ 309 #endif 310 ar9300_disable_phy_restart, /* ah_disable_phy_restart */ 311 ar9300_enable_keysearch_always, 312 ar9300_interference_is_present, /* ah_interference_is_present */ 313 ar9300_disp_tpc_tables, /* ah_disp_tpc_tables */ 314 ar9300_get_tpc_tables, /* ah_get_tpc_tables */ 315 /* Key Cache Functions */ 316 ar9300_get_key_cache_size, /* ah_get_key_cache_size */ 317 ar9300_reset_key_cache_entry, /* ah_reset_key_cache_entry */ 318 ar9300_is_key_cache_entry_valid, /* ah_is_key_cache_entry_valid */ 319 ar9300_set_key_cache_entry, /* ah_set_key_cache_entry */ 320 ar9300_set_key_cache_entry_mac, /* ah_set_key_cache_entry_mac */ 321 ar9300_print_keycache, /* ah_print_key_cache */ 322 323 /* Power Management Functions */ 324 ar9300_set_power_mode, /* ah_set_power_mode */ 325 ar9300_set_sm_power_mode, /* ah_set_sm_ps_mode */ 326 #if ATH_WOW 327 ar9300_wow_apply_pattern, /* ah_wow_apply_pattern */ 328 ar9300_wow_enable, /* ah_wow_enable */ 329 ar9300_wow_wake_up, /* ah_wow_wake_up */ 330 #if ATH_WOW_OFFLOAD 331 ar9300_wowoffload_prep, /* ah_wow_offload_prep */ 332 ar9300_wowoffload_post, /* ah_wow_offload_post */ 333 ar9300_wowoffload_download_rekey_data, /* ah_wow_offload_download_rekey_data */ 334 ar9300_wowoffload_retrieve_data, /* ah_wow_offload_retrieve_data */ 335 ar9300_wowoffload_download_acer_magic, /* ah_wow_offload_download_acer_magic */ 336 ar9300_wowoffload_download_acer_swka, /* ah_wow_offload_download_acer_swka */ 337 ar9300_wowoffload_download_arp_info, /* ah_wow_offload_download_arp_info */ 338 ar9300_wowoffload_download_ns_info, /* ah_wow_offload_download_ns_info */ 339 #endif /* ATH_WOW_OFFLOAD */ 340 #endif 341 342 /* Get Channel Noise */ 343 ath_hal_get_chan_noise, /* ah_get_chan_noise */ 344 ar9300_chain_noise_floor, /* ah_get_chain_noise_floor */ 345 346 /* Beacon Functions */ 347 ar9300_beacon_init, /* ah_beacon_init */ 348 ar9300_set_sta_beacon_timers, /* ah_set_station_beacon_timers */ 349 350 /* Interrupt Functions */ 351 ar9300_is_interrupt_pending, /* ah_is_interrupt_pending */ 352 ar9300_get_pending_interrupts, /* ah_get_pending_interrupts */ 353 ar9300_get_interrupts, /* ah_get_interrupts */ 354 ar9300_set_interrupts, /* ah_set_interrupts */ 355 ar9300_set_intr_mitigation_timer, /* ah_set_intr_mitigation_timer */ 356 ar9300_get_intr_mitigation_timer, /* ah_get_intr_mitigation_timer */ 357 ar9300ForceVCS, 358 ar9300SetDfs3StreamFix, 359 ar9300Get3StreamSignature, 360 361 /* 11n specific functions (NOT applicable to ar9300) */ 362 ar9300_set_11n_tx_desc, /* ah_set_11n_tx_desc */ 363 /* Update rxchain */ 364 ar9300_set_rx_chainmask, /*ah_set_rx_chainmask*/ 365 /*Updating locationing register */ 366 ar9300_update_loc_ctl_reg, /*ah_update_loc_ctl_reg*/ 367 /* Start PAPRD functions */ 368 ar9300_set_paprd_tx_desc, /* ah_set_paprd_tx_desc */ 369 ar9300_paprd_init_table, /* ah_paprd_init_table */ 370 ar9300_paprd_setup_gain_table, /* ah_paprd_setup_gain_table */ 371 ar9300_paprd_create_curve, /* ah_paprd_create_curve */ 372 ar9300_paprd_is_done, /* ah_paprd_is_done */ 373 ar9300_enable_paprd, /* ah_PAPRDEnable */ 374 ar9300_populate_paprd_single_table,/* ah_paprd_populate_table */ 375 ar9300_is_tx_done, /* ah_is_tx_done */ 376 ar9300_paprd_dec_tx_pwr, /* ah_paprd_dec_tx_pwr*/ 377 ar9300_paprd_thermal_send, /* ah_paprd_thermal_send */ 378 /* End PAPRD functions */ 379 ar9300_set_11n_rate_scenario, /* ah_set_11n_rate_scenario */ 380 ar9300_set_11n_aggr_first, /* ah_set_11n_aggr_first */ 381 ar9300_set_11n_aggr_middle, /* ah_set_11n_aggr_middle */ 382 ar9300_set_11n_aggr_last, /* ah_set_11n_aggr_last */ 383 ar9300_clr_11n_aggr, /* ah_clr_11n_aggr */ 384 ar9300_set_11n_rifs_burst_middle, /* ah_set_11n_rifs_burst_middle */ 385 ar9300_set_11n_rifs_burst_last, /* ah_set_11n_rifs_burst_last */ 386 ar9300_clr_11n_rifs_burst, /* ah_clr_11n_rifs_burst */ 387 ar9300_set_11n_aggr_rifs_burst, /* ah_set_11n_aggr_rifs_burst */ 388 ar9300_set_11n_rx_rifs, /* ah_set_11n_rx_rifs */ 389 ar9300_set_smart_antenna, /* ah_setSmartAntenna */ 390 ar9300_detect_bb_hang, /* ah_detect_bb_hang */ 391 ar9300_detect_mac_hang, /* ah_detect_mac_hang */ 392 ar9300_set_immunity, /* ah_immunity */ 393 ar9300_get_hw_hangs, /* ah_get_hang_types */ 394 ar9300_set_11n_burst_duration, /* ah_set_11n_burst_duration */ 395 ar9300_set_11n_virtual_more_frag, /* ah_set_11n_virtual_more_frag */ 396 ar9300_get_11n_ext_busy, /* ah_get_11n_ext_busy */ 397 ar9300_set_11n_mac2040, /* ah_set_11n_mac2040 */ 398 ar9300_get_11n_rx_clear, /* ah_get_11n_rx_clear */ 399 ar9300_set_11n_rx_clear, /* ah_set_11n_rx_clear */ 400 ar9300_get_mib_cycle_counts_pct, /* ah_get_mib_cycle_counts_pct */ 401 ar9300_dma_reg_dump, /* ah_dma_reg_dump */ 402 403 /* force_ppm specific functions */ 404 ar9300_ppm_get_rssi_dump, /* ah_ppm_get_rssi_dump */ 405 ar9300_ppm_arm_trigger, /* ah_ppm_arm_trigger */ 406 ar9300_ppm_get_trigger, /* ah_ppm_get_trigger */ 407 ar9300_ppm_force, /* ah_ppm_force */ 408 ar9300_ppm_un_force, /* ah_ppm_un_force */ 409 ar9300_ppm_get_force_state, /* ah_ppm_get_force_state */ 410 411 ar9300_get_spur_info, /* ah_get_spur_info */ 412 ar9300_set_spur_info, /* ah_get_spur_info */ 413 414 ar9300_get_min_cca_pwr, /* ah_ar_get_noise_floor_val */ 415 416 ar9300_green_ap_ps_on_off, /* ah_set_rx_green_ap_ps_on_off */ 417 ar9300_is_single_ant_power_save_possible, /* ah_is_single_ant_power_save_possible */ 418 419 /* radio measurement specific functions */ 420 ar9300_get_mib_cycle_counts, /* ah_get_mib_cycle_counts */ 421 ar9300_get_vow_stats, /* ah_get_vow_stats */ 422 ar9300_clear_mib_counters, /* ah_clear_mib_counters */ 423 #if ATH_GEN_RANDOMNESS 424 ar9300_get_rssi_chain0, /* ah_get_rssi_chain0 */ 425 #endif 426 #ifdef ATH_BT_COEX 427 /* Bluetooth Coexistence functions */ 428 ar9300_set_bt_coex_info, /* ah_set_bt_coex_info */ 429 ar9300_bt_coex_config, /* ah_bt_coex_config */ 430 ar9300_bt_coex_set_qcu_thresh, /* ah_bt_coex_set_qcu_thresh */ 431 ar9300_bt_coex_set_weights, /* ah_bt_coex_set_weights */ 432 ar9300_bt_coex_setup_bmiss_thresh, /* ah_bt_coex_set_bmiss_thresh */ 433 ar9300_bt_coex_set_parameter, /* ah_bt_coex_set_parameter */ 434 ar9300_bt_coex_disable, /* ah_bt_coex_disable */ 435 ar9300_bt_coex_enable, /* ah_bt_coex_enable */ 436 ar9300_get_bt_active_gpio, /* ah_bt_coex_info*/ 437 ar9300_get_wlan_active_gpio, /* ah__coex_wlan_info*/ 438 #endif 439 /* Generic Timer functions */ 440 ar9300_alloc_generic_timer, /* ah_gentimer_alloc */ 441 ar9300_free_generic_timer, /* ah_gentimer_free */ 442 ar9300_start_generic_timer, /* ah_gentimer_start */ 443 ar9300_stop_generic_timer, /* ah_gentimer_stop */ 444 ar9300_get_gen_timer_interrupts, /* ah_gentimer_get_intr */ 445 446 ar9300_set_dcs_mode, /* ah_set_dcs_mode */ 447 ar9300_get_dcs_mode, /* ah_get_dcs_mode */ 448 449 #if ATH_ANT_DIV_COMB 450 ar9300_ant_div_comb_get_config, /* ah_get_ant_dvi_comb_conf */ 451 ar9300_ant_div_comb_set_config, /* ah_set_ant_dvi_comb_conf */ 452 #endif 453 454 ar9300_get_bb_panic_info, /* ah_get_bb_panic_info */ 455 ar9300_handle_radar_bb_panic, /* ah_handle_radar_bb_panic */ 456 ar9300_set_hal_reset_reason, /* ah_set_hal_reset_reason */ 457 458 #if ATH_PCIE_ERROR_MONITOR 459 ar9300_start_pcie_error_monitor, /* ah_start_pcie_error_monitor */ 460 ar9300_read_pcie_error_monitor, /* ah_read_pcie_error_monitor*/ 461 ar9300_stop_pcie_error_monitor, /* ah_stop_pcie_error_monitor*/ 462 #endif /* ATH_PCIE_ERROR_MONITOR */ 463 464 #if ATH_SUPPORT_SPECTRAL 465 /* Spectral scan */ 466 ar9300_configure_spectral_scan, /* ah_ar_configure_spectral */ 467 ar9300_get_spectral_params, /* ah_ar_get_spectral_config */ 468 ar9300_start_spectral_scan, /* ah_ar_start_spectral_scan */ 469 ar9300_stop_spectral_scan, /* ah_ar_stop_spectral_scan */ 470 ar9300_is_spectral_enabled, /* ah_ar_is_spectral_enabled */ 471 ar9300_is_spectral_active, /* ah_ar_is_spectral_active */ 472 ar9300_get_ctl_chan_nf, /* ah_ar_get_ctl_nf */ 473 ar9300_get_ext_chan_nf, /* ah_ar_get_ext_nf */ 474 #endif /* ATH_SUPPORT_SPECTRAL */ 475 476 477 ar9300_promisc_mode, /* ah_promisc_mode */ 478 ar9300_read_pktlog_reg, /* ah_read_pktlog_reg */ 479 ar9300_write_pktlog_reg, /* ah_write_pktlog_reg */ 480 ar9300_set_proxy_sta, /* ah_set_proxy_sta */ 481 ar9300_get_cal_intervals, /* ah_get_cal_intervals */ 482 #if ATH_TRAFFIC_FAST_RECOVER 483 ar9300_get_pll3_sqsum_dvc, /* ah_get_pll3_sqsum_dvc */ 484 #endif 485 #ifdef ATH_SUPPORT_HTC 486 AH_NULL, 487 #endif 488 489 #ifdef ATH_TX99_DIAG 490 /* Tx99 functions */ 491 #ifdef ATH_SUPPORT_HTC 492 AH_NULL, 493 AH_NULL, 494 AH_NULL, 495 AH_NULL, 496 AH_NULL, 497 AH_NULL, 498 AH_NULL, 499 #else 500 AH_NULL, 501 AH_NULL, 502 ar9300TX99TgtChannelPwrUpdate, /* ah_tx99channelpwrupdate */ 503 ar9300TX99TgtStart, /* ah_tx99start */ 504 ar9300TX99TgtStop, /* ah_tx99stop */ 505 ar9300TX99TgtChainmskSetup, /* ah_tx99_chainmsk_setup */ 506 ar9300TX99SetSingleCarrier, /* ah_tx99_set_single_carrier */ 507 #endif 508 #endif 509 ar9300_chk_rssi_update_tx_pwr, 510 ar9300_is_skip_paprd_by_greentx, /* ah_is_skip_paprd_by_greentx */ 511 ar9300_hwgreentx_set_pal_spare, /* ah_hwgreentx_set_pal_spare */ 512 #if ATH_SUPPORT_MCI 513 /* MCI Coexistence Functions */ 514 ar9300_mci_setup, /* ah_mci_setup */ 515 ar9300_mci_send_message, /* ah_mci_send_message */ 516 ar9300_mci_get_interrupt, /* ah_mci_get_interrupt */ 517 ar9300_mci_state, /* ah_mci_state */ 518 ar9300_mci_detach, /* ah_mci_detach */ 519 #endif 520 ar9300_reset_hw_beacon_proc_crc, /* ah_reset_hw_beacon_proc_crc */ 521 ar9300_get_hw_beacon_rssi, /* ah_get_hw_beacon_rssi */ 522 ar9300_set_hw_beacon_rssi_threshold,/*ah_set_hw_beacon_rssi_threshold*/ 523 ar9300_reset_hw_beacon_rssi, /* ah_reset_hw_beacon_rssi */ 524 ar9300_mat_enable, /* ah_mat_enable */ 525 ar9300_dump_keycache, /* ah_dump_keycache */ 526 ar9300_is_ani_noise_spur, /* ah_is_ani_noise_spur */ 527 ar9300_set_hw_beacon_proc, /* ah_set_hw_beacon_proc */ 528 }, 529 530 ar9300_get_channel_edges, /* ah_get_channel_edges */ 531 ar9300_get_wireless_modes, /* ah_get_wireless_modes */ 532 ar9300_eeprom_read_word, /* ah_eeprom_read */ 533 AH_NULL, 534 ar9300_eeprom_dump_support, /* ah_eeprom_dump */ 535 ar9300_get_chip_power_limits, /* ah_get_chip_power_limits */ 536 537 ar9300_get_nf_adjust, /* ah_get_nf_adjust */ 538 /* rest is zero'd by compiler */ 539 }; 540 #endif 541 542 /* 543 * Read MAC version/revision information from Chip registers and initialize 544 * local data structures. 545 */ 546 void 547 ar9300_read_revisions(struct ath_hal *ah) 548 { 549 u_int32_t val; 550 551 /* XXX verify if this is the correct way to read revision on Osprey */ 552 /* new SREV format for Sowl and later */ 553 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 554 555 if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9340) { 556 /* XXX: AR_SREV register in Wasp reads 0 */ 557 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_WASP; 558 } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA955X) { 559 /* XXX: AR_SREV register in Scorpion reads 0 */ 560 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION; 561 } else { 562 /* 563 * Include 6-bit Chip Type (masked to 0) 564 * to differentiate from pre-Sowl versions 565 */ 566 AH_PRIVATE(ah)->ah_macVersion = 567 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 568 } 569 570 571 572 573 574 #ifdef AH_SUPPORT_HORNET 575 /* 576 * EV74984, due to Hornet 1.1 didn't update WMAC revision, 577 * so that have to read SoC's revision ID instead 578 */ 579 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_HORNET) { 580 #define AR_SOC_RST_REVISION_ID 0xB8060090 581 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 582 if ((REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_HORNET_11_MASK) 583 == AR_SREV_REVISION_HORNET_11) 584 { 585 AH_PRIVATE(ah)->ah_macRev = AR_SREV_REVISION_HORNET_11; 586 } else { 587 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 588 } 589 #undef REG_READ 590 #undef AR_SOC_RST_REVISION_ID 591 } else 592 #endif 593 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_WASP) 594 { 595 #define AR_SOC_RST_REVISION_ID 0xB8060090 596 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 597 598 AH_PRIVATE(ah)->ah_macRev = 599 REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_WASP_MASK; 600 #undef REG_READ 601 #undef AR_SOC_RST_REVISION_ID 602 } 603 else 604 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 605 606 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 607 AH_PRIVATE(ah)->ah_ispcie = AH_TRUE; 608 } 609 else { 610 AH_PRIVATE(ah)->ah_ispcie = 611 (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 612 } 613 614 } 615 616 /* 617 * Attach for an AR9300 part. 618 */ 619 struct ath_hal * 620 ar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, 621 HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_STATUS *status) 622 { 623 struct ath_hal_9300 *ahp; 624 struct ath_hal *ah; 625 struct ath_hal_private *ahpriv; 626 HAL_STATUS ecode; 627 628 HAL_NO_INTERSPERSED_READS; 629 630 /* NB: memory is returned zero'd */ 631 ahp = ar9300_new_state(devid, sc, st, sh, eepromdata, status); 632 if (ahp == AH_NULL) { 633 return AH_NULL; 634 } 635 ah = &ahp->ah_priv.h; 636 ar9300_init_offsets(ah, devid); 637 ahpriv = AH_PRIVATE(ah); 638 // AH_PRIVATE(ah)->ah_bustype = bustype; 639 640 /* FreeBSD: to make OTP work for now, provide this.. */ 641 AH9300(ah)->ah_cal_mem = ath_hal_malloc(HOST_CALDATA_SIZE); 642 if (AH9300(ah)->ah_cal_mem == NULL) { 643 ath_hal_printf(ah, "%s: caldata malloc failed!\n", __func__); 644 ecode = HAL_EIO; 645 goto bad; 646 } 647 648 /* 649 * If eepromdata is not NULL, copy it it into ah_cal_mem. 650 */ 651 if (eepromdata != NULL) 652 OS_MEMCPY(AH9300(ah)->ah_cal_mem, eepromdata, HOST_CALDATA_SIZE); 653 654 /* XXX FreeBSD: enable RX mitigation */ 655 ah->ah_config.ath_hal_intr_mitigation_rx = 1; 656 657 /* 658 * XXX what's this do? Check in the qcamain driver code 659 * as to what it does. 660 */ 661 ah->ah_config.ath_hal_ext_atten_margin_cfg = 0; 662 663 /* interrupt mitigation */ 664 #ifdef AR5416_INT_MITIGATION 665 if (ah->ah_config.ath_hal_intr_mitigation_rx != 0) { 666 ahp->ah_intr_mitigation_rx = AH_TRUE; 667 } 668 #else 669 /* Enable Rx mitigation (default) */ 670 ahp->ah_intr_mitigation_rx = AH_TRUE; 671 ah->ah_config.ath_hal_intr_mitigation_rx = 1; 672 673 #endif 674 #ifdef HOST_OFFLOAD 675 /* Reset default Rx mitigation values for Hornet */ 676 if (AR_SREV_HORNET(ah)) { 677 ahp->ah_intr_mitigation_rx = AH_FALSE; 678 #ifdef AR5416_INT_MITIGATION 679 ah->ah_config.ath_hal_intr_mitigation_rx = 0; 680 #endif 681 } 682 #endif 683 684 if (ah->ah_config.ath_hal_intr_mitigation_tx != 0) { 685 ahp->ah_intr_mitigation_tx = AH_TRUE; 686 } 687 688 /* 689 * Read back AR_WA into a permanent copy and set bits 14 and 17. 690 * We need to do this to avoid RMW of this register. 691 * Do this before calling ar9300_set_reset_reg. 692 * If not, the AR_WA register which was inited via EEPROM 693 * will get wiped out. 694 */ 695 ahp->ah_wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA)); 696 /* Set Bits 14 and 17 in the AR_WA register. */ 697 ahp->ah_wa_reg_val |= 698 AR_WA_D3_TO_L1_DISABLE | AR_WA_ASPM_TIMER_BASED_DISABLE; 699 700 if (!ar9300_set_reset_reg(ah, HAL_RESET_POWER_ON)) { /* reset chip */ 701 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't reset chip\n", __func__); 702 ecode = HAL_EIO; 703 goto bad; 704 } 705 706 if (AR_SREV_JUPITER(ah) 707 #if ATH_WOW_OFFLOAD 708 && !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14) 709 #endif 710 ) 711 { 712 /* Jupiter doesn't need bit 14 to be set. */ 713 ahp->ah_wa_reg_val &= ~AR_WA_D3_TO_L1_DISABLE; 714 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 715 } 716 717 #if ATH_SUPPORT_MCI 718 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 719 #if 0 720 ah->ah_bt_coex_set_weights = ar9300_mci_bt_coex_set_weights; 721 ah->ah_bt_coex_disable = ar9300_mci_bt_coex_disable; 722 ah->ah_bt_coex_enable = ar9300_mci_bt_coex_enable; 723 #endif 724 ahp->ah_mci_ready = AH_FALSE; 725 ahp->ah_mci_bt_state = MCI_BT_SLEEP; 726 ahp->ah_mci_coex_major_version_wlan = MCI_GPM_COEX_MAJOR_VERSION_WLAN; 727 ahp->ah_mci_coex_minor_version_wlan = MCI_GPM_COEX_MINOR_VERSION_WLAN; 728 ahp->ah_mci_coex_major_version_bt = MCI_GPM_COEX_MAJOR_VERSION_DEFAULT; 729 ahp->ah_mci_coex_minor_version_bt = MCI_GPM_COEX_MINOR_VERSION_DEFAULT; 730 ahp->ah_mci_coex_bt_version_known = AH_FALSE; 731 ahp->ah_mci_coex_2g5g_update = AH_TRUE; /* track if 2g5g status sent */ 732 /* will be updated before boot up sequence */ 733 ahp->ah_mci_coex_is_2g = AH_TRUE; 734 ahp->ah_mci_coex_wlan_channels_update = AH_FALSE; 735 ahp->ah_mci_coex_wlan_channels[0] = 0x00000000; 736 ahp->ah_mci_coex_wlan_channels[1] = 0xffffffff; 737 ahp->ah_mci_coex_wlan_channels[2] = 0xffffffff; 738 ahp->ah_mci_coex_wlan_channels[3] = 0x7fffffff; 739 ahp->ah_mci_query_bt = AH_TRUE; /* In case WLAN start after BT */ 740 ahp->ah_mci_unhalt_bt_gpm = AH_TRUE; /* Send UNHALT at beginning */ 741 ahp->ah_mci_halted_bt_gpm = AH_FALSE; /* Allow first HALT */ 742 ahp->ah_mci_need_flush_btinfo = AH_FALSE; 743 ahp->ah_mci_wlan_cal_seq = 0; 744 ahp->ah_mci_wlan_cal_done = 0; 745 } 746 #endif /* ATH_SUPPORT_MCI */ 747 748 #if ATH_WOW_OFFLOAD 749 ahp->ah_mcast_filter_l32_set = 0; 750 ahp->ah_mcast_filter_u32_set = 0; 751 #endif 752 753 if (AR_SREV_HORNET(ah)) { 754 #ifdef AH_SUPPORT_HORNET 755 if (!AR_SREV_HORNET_11(ah)) { 756 /* 757 * Do not check bootstrap register, which cannot be trusted 758 * due to s26 switch issue on CUS164/AP121. 759 */ 760 ahp->clk_25mhz = 1; 761 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 762 } else { 763 /* check bootstrap clock setting */ 764 #define AR_SOC_SEL_25M_40M 0xB80600AC 765 #define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); 766 #define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 767 if (REG_READ(AR_SOC_SEL_25M_40M) & 0x1) { 768 ahp->clk_25mhz = 0; 769 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 770 "Bootstrap clock 40MHz\n"); 771 } else { 772 ahp->clk_25mhz = 1; 773 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 774 "Bootstrap clock 25MHz\n"); 775 } 776 #undef REG_READ 777 #undef REG_WRITE 778 #undef AR_SOC_SEL_25M_40M 779 } 780 #endif /* AH_SUPPORT_HORNET */ 781 } 782 783 if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 784 /* check bootstrap clock setting */ 785 #define AR9340_SOC_SEL_25M_40M 0xB80600B0 786 #define AR9340_REF_CLK_40 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */ 787 #define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 788 if (REG_READ(AR9340_SOC_SEL_25M_40M) & AR9340_REF_CLK_40) { 789 ahp->clk_25mhz = 0; 790 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 40MHz\n"); 791 } else { 792 ahp->clk_25mhz = 1; 793 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 794 } 795 #undef REG_READ 796 #undef AR9340_SOC_SEL_25M_40M 797 #undef AR9340_REF_CLK_40 798 } 799 ar9300_init_pll(ah, AH_NULL); 800 801 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 802 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't wakeup chip\n", __func__); 803 ecode = HAL_EIO; 804 goto bad; 805 } 806 807 /* No serialization of Register Accesses needed. */ 808 ah->ah_config.ah_serialise_reg_war = SER_REG_MODE_OFF; 809 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: ah_serialise_reg_war is %d\n", 810 __func__, ah->ah_config.ah_serialise_reg_war); 811 812 /* 813 * Add mac revision check when needed. 814 * - Osprey 1.0 and 2.0 no longer supported. 815 */ 816 if (((ahpriv->ah_macVersion == AR_SREV_VERSION_OSPREY) && 817 (ahpriv->ah_macRev <= AR_SREV_REVISION_OSPREY_20)) || 818 (ahpriv->ah_macVersion != AR_SREV_VERSION_OSPREY && 819 ahpriv->ah_macVersion != AR_SREV_VERSION_WASP && 820 ahpriv->ah_macVersion != AR_SREV_VERSION_HORNET && 821 ahpriv->ah_macVersion != AR_SREV_VERSION_POSEIDON && 822 ahpriv->ah_macVersion != AR_SREV_VERSION_SCORPION && 823 ahpriv->ah_macVersion != AR_SREV_VERSION_JUPITER && 824 ahpriv->ah_macVersion != AR_SREV_VERSION_APHRODITE) ) { 825 HALDEBUG(ah, HAL_DEBUG_RESET, 826 "%s: Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 827 __func__, 828 ahpriv->ah_macVersion, 829 ahpriv->ah_macRev); 830 ecode = HAL_ENOTSUPP; 831 goto bad; 832 } 833 834 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 835 836 /* Setup supported calibrations */ 837 ahp->ah_iq_cal_data.cal_data = &iq_cal_single_sample; 838 ahp->ah_supp_cals = IQ_MISMATCH_CAL; 839 840 /* Enable ANI */ 841 ahp->ah_ani_function = HAL_ANI_ALL; 842 843 /* Enable RIFS */ 844 ahp->ah_rifs_enabled = AH_TRUE; 845 846 HALDEBUG(ah, HAL_DEBUG_RESET, 847 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, 848 ahpriv->ah_macVersion, 849 ahpriv->ah_macRev); 850 851 if (AR_SREV_HORNET_12(ah)) { 852 /* mac */ 853 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 854 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 855 ar9331_hornet1_2_mac_core, 856 ARRAY_LENGTH(ar9331_hornet1_2_mac_core), 2); 857 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 858 ar9331_hornet1_2_mac_postamble, 859 ARRAY_LENGTH(ar9331_hornet1_2_mac_postamble), 5); 860 861 /* bb */ 862 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 863 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 864 ar9331_hornet1_2_baseband_core, 865 ARRAY_LENGTH(ar9331_hornet1_2_baseband_core), 2); 866 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 867 ar9331_hornet1_2_baseband_postamble, 868 ARRAY_LENGTH(ar9331_hornet1_2_baseband_postamble), 5); 869 870 /* radio */ 871 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 872 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 873 ar9331_hornet1_2_radio_core, 874 ARRAY_LENGTH(ar9331_hornet1_2_radio_core), 2); 875 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 876 877 /* soc */ 878 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 879 ar9331_hornet1_2_soc_preamble, 880 ARRAY_LENGTH(ar9331_hornet1_2_soc_preamble), 2); 881 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 882 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 883 ar9331_hornet1_2_soc_postamble, 884 ARRAY_LENGTH(ar9331_hornet1_2_soc_postamble), 2); 885 886 /* rx/tx gain */ 887 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 888 ar9331_common_rx_gain_hornet1_2, 889 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 890 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 891 ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 892 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 893 894 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 895 896 /* Japan 2484Mhz CCK settings */ 897 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 898 ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484, 899 ARRAY_LENGTH( 900 ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484), 2); 901 902 #if 0 /* ATH_WOW */ 903 /* SerDes values during WOW sleep */ 904 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 905 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 906 #endif 907 908 /* additional clock settings */ 909 if (AH9300(ah)->clk_25mhz) { 910 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 911 ar9331_hornet1_2_xtal_25M, 912 ARRAY_LENGTH(ar9331_hornet1_2_xtal_25M), 2); 913 } else { 914 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 915 ar9331_hornet1_2_xtal_40M, 916 ARRAY_LENGTH(ar9331_hornet1_2_xtal_40M), 2); 917 } 918 919 } else if (AR_SREV_HORNET_11(ah)) { 920 /* mac */ 921 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 922 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 923 ar9331_hornet1_1_mac_core, 924 ARRAY_LENGTH(ar9331_hornet1_1_mac_core), 2); 925 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 926 ar9331_hornet1_1_mac_postamble, 927 ARRAY_LENGTH(ar9331_hornet1_1_mac_postamble), 5); 928 929 /* bb */ 930 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 931 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 932 ar9331_hornet1_1_baseband_core, 933 ARRAY_LENGTH(ar9331_hornet1_1_baseband_core), 2); 934 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 935 ar9331_hornet1_1_baseband_postamble, 936 ARRAY_LENGTH(ar9331_hornet1_1_baseband_postamble), 5); 937 938 /* radio */ 939 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 940 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 941 ar9331_hornet1_1_radio_core, 942 ARRAY_LENGTH(ar9331_hornet1_1_radio_core), 2); 943 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 944 945 /* soc */ 946 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 947 ar9331_hornet1_1_soc_preamble, 948 ARRAY_LENGTH(ar9331_hornet1_1_soc_preamble), 2); 949 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 950 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 951 ar9331_hornet1_1_soc_postamble, 952 ARRAY_LENGTH(ar9331_hornet1_1_soc_postamble), 2); 953 954 /* rx/tx gain */ 955 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 956 ar9331_common_rx_gain_hornet1_1, 957 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 958 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 959 ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 960 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 961 962 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 963 964 /* Japan 2484Mhz CCK settings */ 965 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 966 ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484, 967 ARRAY_LENGTH( 968 ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484), 2); 969 970 #if 0 /* ATH_WOW */ 971 /* SerDes values during WOW sleep */ 972 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 973 N(ar9300_pcie_phy_awow), 2); 974 #endif 975 976 /* additional clock settings */ 977 if (AH9300(ah)->clk_25mhz) { 978 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 979 ar9331_hornet1_1_xtal_25M, 980 ARRAY_LENGTH(ar9331_hornet1_1_xtal_25M), 2); 981 } else { 982 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 983 ar9331_hornet1_1_xtal_40M, 984 ARRAY_LENGTH(ar9331_hornet1_1_xtal_40M), 2); 985 } 986 987 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 988 /* mac */ 989 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 990 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 991 ar9485_poseidon1_1_mac_core, 992 ARRAY_LENGTH( ar9485_poseidon1_1_mac_core), 2); 993 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 994 ar9485_poseidon1_1_mac_postamble, 995 ARRAY_LENGTH(ar9485_poseidon1_1_mac_postamble), 5); 996 997 /* bb */ 998 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 999 ar9485_poseidon1_1, ARRAY_LENGTH(ar9485_poseidon1_1), 2); 1000 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1001 ar9485_poseidon1_1_baseband_core, 1002 ARRAY_LENGTH(ar9485_poseidon1_1_baseband_core), 2); 1003 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1004 ar9485_poseidon1_1_baseband_postamble, 1005 ARRAY_LENGTH(ar9485_poseidon1_1_baseband_postamble), 5); 1006 1007 /* radio */ 1008 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1009 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1010 ar9485_poseidon1_1_radio_core, 1011 ARRAY_LENGTH(ar9485_poseidon1_1_radio_core), 2); 1012 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1013 ar9485_poseidon1_1_radio_postamble, 1014 ARRAY_LENGTH(ar9485_poseidon1_1_radio_postamble), 2); 1015 1016 /* soc */ 1017 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1018 ar9485_poseidon1_1_soc_preamble, 1019 ARRAY_LENGTH(ar9485_poseidon1_1_soc_preamble), 2); 1020 1021 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1022 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1023 1024 /* rx/tx gain */ 1025 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1026 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 1027 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 1028 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1029 ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 1030 ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 1031 1032 /* Japan 2484Mhz CCK settings */ 1033 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1034 ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484, 1035 ARRAY_LENGTH( 1036 ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484), 2); 1037 1038 /* Load PCIE SERDES settings from INI */ 1039 if (ah->ah_config.ath_hal_pcie_clock_req) { 1040 /* Pci-e Clock Request = 1 */ 1041 if (ah->ah_config.ath_hal_pll_pwr_save 1042 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1043 { 1044 /* Sleep Setting */ 1045 if (ah->ah_config.ath_hal_pll_pwr_save & 1046 AR_PCIE_PLL_PWRSAVE_ON_D3) 1047 { 1048 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1049 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1050 ARRAY_LENGTH( 1051 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1052 2); 1053 } else { 1054 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1055 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1056 ARRAY_LENGTH( 1057 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1058 2); 1059 } 1060 /* Awake Setting */ 1061 if (ah->ah_config.ath_hal_pll_pwr_save & 1062 AR_PCIE_PLL_PWRSAVE_ON_D0) 1063 { 1064 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1065 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1066 ARRAY_LENGTH( 1067 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1068 2); 1069 } else { 1070 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1071 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1072 ARRAY_LENGTH( 1073 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1074 2); 1075 } 1076 1077 } else { 1078 /*Use driver default setting*/ 1079 /* Sleep Setting */ 1080 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1081 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1082 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1083 2); 1084 /* Awake Setting */ 1085 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1086 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1087 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1088 2); 1089 } 1090 } else { 1091 /* Pci-e Clock Request = 0 */ 1092 if (ah->ah_config.ath_hal_pll_pwr_save 1093 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1094 { 1095 /* Sleep Setting */ 1096 if (ah->ah_config.ath_hal_pll_pwr_save & 1097 AR_PCIE_PLL_PWRSAVE_ON_D3) 1098 { 1099 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1100 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1101 ARRAY_LENGTH( 1102 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1103 2); 1104 } else { 1105 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1106 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1107 ARRAY_LENGTH( 1108 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1109 2); 1110 } 1111 /* Awake Setting */ 1112 if (ah->ah_config.ath_hal_pll_pwr_save & 1113 AR_PCIE_PLL_PWRSAVE_ON_D0) 1114 { 1115 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1116 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1117 ARRAY_LENGTH( 1118 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1119 2); 1120 } else { 1121 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1122 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1123 ARRAY_LENGTH( 1124 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1125 2); 1126 } 1127 1128 } else { 1129 /*Use driver default setting*/ 1130 /* Sleep Setting */ 1131 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1132 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1133 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1134 2); 1135 /* Awake Setting */ 1136 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1137 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1138 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1139 2); 1140 } 1141 } 1142 /* pcie ps setting will honor registry setting, default is 0 */ 1143 //ah->ah_config.ath_hal_pciePowerSaveEnable = 0; 1144 } else if (AR_SREV_POSEIDON(ah)) { 1145 /* mac */ 1146 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1147 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1148 ar9485_poseidon1_0_mac_core, 1149 ARRAY_LENGTH(ar9485_poseidon1_0_mac_core), 2); 1150 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1151 ar9485_poseidon1_0_mac_postamble, 1152 ARRAY_LENGTH(ar9485_poseidon1_0_mac_postamble), 5); 1153 1154 /* bb */ 1155 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 1156 ar9485_poseidon1_0, 1157 ARRAY_LENGTH(ar9485_poseidon1_0), 2); 1158 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1159 ar9485_poseidon1_0_baseband_core, 1160 ARRAY_LENGTH(ar9485_poseidon1_0_baseband_core), 2); 1161 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1162 ar9485_poseidon1_0_baseband_postamble, 1163 ARRAY_LENGTH(ar9485_poseidon1_0_baseband_postamble), 5); 1164 1165 /* radio */ 1166 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1167 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1168 ar9485_poseidon1_0_radio_core, 1169 ARRAY_LENGTH(ar9485_poseidon1_0_radio_core), 2); 1170 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1171 ar9485_poseidon1_0_radio_postamble, 1172 ARRAY_LENGTH(ar9485_poseidon1_0_radio_postamble), 2); 1173 1174 /* soc */ 1175 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1176 ar9485_poseidon1_0_soc_preamble, 1177 ARRAY_LENGTH(ar9485_poseidon1_0_soc_preamble), 2); 1178 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1179 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1180 1181 /* rx/tx gain */ 1182 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1183 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 1184 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 1185 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1186 ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 1187 ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 1188 1189 /* Japan 2484Mhz CCK settings */ 1190 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1191 ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484, 1192 ARRAY_LENGTH( 1193 ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484), 2); 1194 1195 /* Load PCIE SERDES settings from INI */ 1196 if (ah->ah_config.ath_hal_pcie_clock_req) { 1197 /* Pci-e Clock Request = 1 */ 1198 if (ah->ah_config.ath_hal_pll_pwr_save 1199 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1200 { 1201 /* Sleep Setting */ 1202 if (ah->ah_config.ath_hal_pll_pwr_save & 1203 AR_PCIE_PLL_PWRSAVE_ON_D3) 1204 { 1205 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1206 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1207 ARRAY_LENGTH( 1208 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1209 2); 1210 } else { 1211 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1212 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1213 ARRAY_LENGTH( 1214 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1215 2); 1216 } 1217 /* Awake Setting */ 1218 if (ah->ah_config.ath_hal_pll_pwr_save & 1219 AR_PCIE_PLL_PWRSAVE_ON_D0) 1220 { 1221 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1222 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1223 ARRAY_LENGTH( 1224 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1225 2); 1226 } else { 1227 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1228 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1229 ARRAY_LENGTH( 1230 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1231 2); 1232 } 1233 1234 } else { 1235 /*Use driver default setting*/ 1236 /* Sleep Setting */ 1237 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1238 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1239 ARRAY_LENGTH( 1240 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1241 2); 1242 /* Awake Setting */ 1243 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1244 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1245 ARRAY_LENGTH( 1246 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1247 2); 1248 } 1249 } else { 1250 /* Pci-e Clock Request = 0 */ 1251 if (ah->ah_config.ath_hal_pll_pwr_save 1252 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1253 { 1254 /* Sleep Setting */ 1255 if (ah->ah_config.ath_hal_pll_pwr_save & 1256 AR_PCIE_PLL_PWRSAVE_ON_D3) 1257 { 1258 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1259 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1260 ARRAY_LENGTH( 1261 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1262 2); 1263 } else { 1264 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1265 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1266 ARRAY_LENGTH( 1267 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1268 2); 1269 } 1270 /* Awake Setting */ 1271 if (ah->ah_config.ath_hal_pll_pwr_save & 1272 AR_PCIE_PLL_PWRSAVE_ON_D0) 1273 { 1274 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1275 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1276 ARRAY_LENGTH( 1277 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1278 2); 1279 } else { 1280 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1281 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1282 ARRAY_LENGTH( 1283 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1284 2); 1285 } 1286 1287 } else { 1288 /*Use driver default setting*/ 1289 /* Sleep Setting */ 1290 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1291 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1292 ARRAY_LENGTH( 1293 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1294 2); 1295 /* Awake Setting */ 1296 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1297 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1298 ARRAY_LENGTH( 1299 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1300 2); 1301 } 1302 } 1303 /* pcie ps setting will honor registry setting, default is 0 */ 1304 /*ah->ah_config.ath_hal_pcie_power_save_enable = 0;*/ 1305 1306 #if 0 /* ATH_WOW */ 1307 /* SerDes values during WOW sleep */ 1308 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 1309 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 1310 #endif 1311 1312 } else if (AR_SREV_WASP(ah)) { 1313 /* mac */ 1314 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1315 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1316 ar9340_wasp_1p0_mac_core, 1317 ARRAY_LENGTH(ar9340_wasp_1p0_mac_core), 2); 1318 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1319 ar9340_wasp_1p0_mac_postamble, 1320 ARRAY_LENGTH(ar9340_wasp_1p0_mac_postamble), 5); 1321 1322 /* bb */ 1323 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1324 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1325 ar9340_wasp_1p0_baseband_core, 1326 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_core), 2); 1327 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1328 ar9340_wasp_1p0_baseband_postamble, 1329 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble), 5); 1330 1331 /* radio */ 1332 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1333 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1334 ar9340_wasp_1p0_radio_core, 1335 ARRAY_LENGTH(ar9340_wasp_1p0_radio_core), 2); 1336 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1337 ar9340_wasp_1p0_radio_postamble, 1338 ARRAY_LENGTH(ar9340_wasp_1p0_radio_postamble), 5); 1339 1340 /* soc */ 1341 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1342 ar9340_wasp_1p0_soc_preamble, 1343 ARRAY_LENGTH(ar9340_wasp_1p0_soc_preamble), 2); 1344 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1345 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1346 ar9340_wasp_1p0_soc_postamble, 1347 ARRAY_LENGTH(ar9340_wasp_1p0_soc_postamble), 5); 1348 1349 /* rx/tx gain */ 1350 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1351 ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 1352 ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 1353 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1354 ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 1355 ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 1356 1357 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1358 1359 /* Fast clock modal settings */ 1360 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1361 ar9340Modes_fast_clock_wasp_1p0, 1362 ARRAY_LENGTH(ar9340Modes_fast_clock_wasp_1p0), 3); 1363 1364 /* Additional setttings for 40Mhz */ 1365 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40mhz, 1366 ar9340_wasp_1p0_radio_core_40M, 1367 ARRAY_LENGTH(ar9340_wasp_1p0_radio_core_40M), 2); 1368 1369 /* DFS */ 1370 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1371 ar9340_wasp_1p0_baseband_postamble_dfs_channel, 1372 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble_dfs_channel), 3); 1373 } else if (AR_SREV_SCORPION(ah)) { 1374 /* mac */ 1375 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1376 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1377 ar955x_scorpion_1p0_mac_core, 1378 ARRAY_LENGTH(ar955x_scorpion_1p0_mac_core), 2); 1379 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1380 ar955x_scorpion_1p0_mac_postamble, 1381 ARRAY_LENGTH(ar955x_scorpion_1p0_mac_postamble), 5); 1382 1383 /* bb */ 1384 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1385 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1386 ar955x_scorpion_1p0_baseband_core, 1387 ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_core), 2); 1388 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1389 ar955x_scorpion_1p0_baseband_postamble, 1390 ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_postamble), 5); 1391 1392 /* radio */ 1393 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1394 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1395 ar955x_scorpion_1p0_radio_core, 1396 ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core), 2); 1397 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1398 ar955x_scorpion_1p0_radio_postamble, 1399 ARRAY_LENGTH(ar955x_scorpion_1p0_radio_postamble), 5); 1400 1401 /* soc */ 1402 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1403 ar955x_scorpion_1p0_soc_preamble, 1404 ARRAY_LENGTH(ar955x_scorpion_1p0_soc_preamble), 2); 1405 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1406 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1407 ar955x_scorpion_1p0_soc_postamble, 1408 ARRAY_LENGTH(ar955x_scorpion_1p0_soc_postamble), 5); 1409 1410 /* rx/tx gain */ 1411 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1412 ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 1413 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 1414 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 1415 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 1416 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 1417 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1418 ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 1419 ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 5); 1420 1421 /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */ 1422 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1423 1424 /* Fast clock modal settings */ 1425 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1426 ar955xModes_fast_clock_scorpion_1p0, 1427 ARRAY_LENGTH(ar955xModes_fast_clock_scorpion_1p0), 3); 1428 1429 /* Additional setttings for 40Mhz */ 1430 //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M, 1431 // ar955x_scorpion_1p0_radio_core_40M, 1432 // ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core_40M), 2); 1433 } else if (AR_SREV_JUPITER_10(ah)) { 1434 /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1435 1436 /* mac */ 1437 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1438 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1439 ar9300_jupiter_1p0_mac_core, 1440 ARRAY_LENGTH(ar9300_jupiter_1p0_mac_core), 2); 1441 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1442 ar9300_jupiter_1p0_mac_postamble, 1443 ARRAY_LENGTH(ar9300_jupiter_1p0_mac_postamble), 5); 1444 1445 /* bb */ 1446 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1447 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1448 ar9300_jupiter_1p0_baseband_core, 1449 ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_core), 2); 1450 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1451 ar9300_jupiter_1p0_baseband_postamble, 1452 ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_postamble), 5); 1453 1454 /* radio */ 1455 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1456 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1457 ar9300_jupiter_1p0_radio_core, 1458 ARRAY_LENGTH(ar9300_jupiter_1p0_radio_core), 2); 1459 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1460 ar9300_jupiter_1p0_radio_postamble, 1461 ARRAY_LENGTH(ar9300_jupiter_1p0_radio_postamble), 5); 1462 1463 /* soc */ 1464 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1465 ar9300_jupiter_1p0_soc_preamble, 1466 ARRAY_LENGTH(ar9300_jupiter_1p0_soc_preamble), 2); 1467 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1468 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1469 ar9300_jupiter_1p0_soc_postamble, 1470 ARRAY_LENGTH(ar9300_jupiter_1p0_soc_postamble), 5); 1471 1472 /* rx/tx gain */ 1473 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1474 ar9300_common_rx_gain_table_jupiter_1p0, 1475 ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 1476 1477 /* Load PCIE SERDES settings from INI */ 1478 if (ah->ah_config.ath_hal_pcie_clock_req) { 1479 /* Pci-e Clock Request = 1 */ 1480 /* 1481 * PLL ON + clkreq enable is not a valid combination, 1482 * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1483 */ 1484 { 1485 /*Use driver default setting*/ 1486 /* Awake -> Sleep Setting */ 1487 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1488 ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1489 ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1490 2); 1491 /* Sleep -> Awake Setting */ 1492 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1493 ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1494 ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1495 2); 1496 } 1497 } 1498 else { 1499 /* 1500 * Since Jupiter 1.0 and 2.0 share the same device id and will be 1501 * installed with same INF, but Jupiter 1.0 has issue with PLL OFF. 1502 * 1503 * Force Jupiter 1.0 to use ON/ON setting. 1504 */ 1505 ah->ah_config.ath_hal_pll_pwr_save = 0; 1506 /* Pci-e Clock Request = 0 */ 1507 if (ah->ah_config.ath_hal_pll_pwr_save & 1508 AR_PCIE_PLL_PWRSAVE_CONTROL) 1509 { 1510 /* Awake -> Sleep Setting */ 1511 if (ah->ah_config.ath_hal_pll_pwr_save & 1512 AR_PCIE_PLL_PWRSAVE_ON_D3) 1513 { 1514 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1515 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1516 ARRAY_LENGTH( 1517 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1518 2); 1519 } 1520 else { 1521 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1522 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1523 ARRAY_LENGTH( 1524 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1525 2); 1526 } 1527 /* Sleep -> Awake Setting */ 1528 if (ah->ah_config.ath_hal_pll_pwr_save & 1529 AR_PCIE_PLL_PWRSAVE_ON_D0) 1530 { 1531 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1532 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1533 ARRAY_LENGTH( 1534 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1535 2); 1536 } 1537 else { 1538 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1539 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1540 ARRAY_LENGTH( 1541 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1542 2); 1543 } 1544 1545 } 1546 else { 1547 /*Use driver default setting*/ 1548 /* Awake -> Sleep Setting */ 1549 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1550 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1551 ARRAY_LENGTH( 1552 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1553 2); 1554 /* Sleep -> Awake Setting */ 1555 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1556 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1557 ARRAY_LENGTH( 1558 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1559 2); 1560 } 1561 } 1562 /* 1563 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1564 * 0 for merlin 1565 */ 1566 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1567 1568 #if 0 // ATH_WOW 1569 /* SerDes values during WOW sleep */ 1570 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1571 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1572 #endif 1573 1574 /* Fast clock modal settings */ 1575 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1576 ar9300_modes_fast_clock_jupiter_1p0, 1577 ARRAY_LENGTH(ar9300_modes_fast_clock_jupiter_1p0), 3); 1578 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1579 ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484, 1580 ARRAY_LENGTH( 1581 ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484), 2); 1582 1583 } 1584 else if (AR_SREV_JUPITER_20(ah)) { 1585 /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1586 1587 /* mac */ 1588 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1589 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1590 ar9300_jupiter_2p0_mac_core, 1591 ARRAY_LENGTH(ar9300_jupiter_2p0_mac_core), 2); 1592 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1593 ar9300_jupiter_2p0_mac_postamble, 1594 ARRAY_LENGTH(ar9300_jupiter_2p0_mac_postamble), 5); 1595 1596 /* bb */ 1597 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1598 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1599 ar9300_jupiter_2p0_baseband_core, 1600 ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_core), 2); 1601 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1602 ar9300_jupiter_2p0_baseband_postamble, 1603 ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_postamble), 5); 1604 1605 /* radio */ 1606 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1607 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1608 ar9300_jupiter_2p0_radio_core, 1609 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_core), 2); 1610 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1611 ar9300_jupiter_2p0_radio_postamble, 1612 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble), 5); 1613 INIT_INI_ARRAY(&ahp->ah_ini_radio_post_sys2ant, 1614 ar9300_jupiter_2p0_radio_postamble_sys2ant, 1615 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble_sys2ant), 5); 1616 1617 /* soc */ 1618 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1619 ar9300_jupiter_2p0_soc_preamble, 1620 ARRAY_LENGTH(ar9300_jupiter_2p0_soc_preamble), 2); 1621 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1622 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1623 ar9300_jupiter_2p0_soc_postamble, 1624 ARRAY_LENGTH(ar9300_jupiter_2p0_soc_postamble), 5); 1625 1626 /* rx/tx gain */ 1627 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1628 ar9300Common_rx_gain_table_jupiter_2p0, 1629 ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 1630 1631 /* BTCOEX */ 1632 INIT_INI_ARRAY(&ahp->ah_ini_BTCOEX_MAX_TXPWR, 1633 ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table, 1634 ARRAY_LENGTH(ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table), 2); 1635 1636 /* Load PCIE SERDES settings from INI */ 1637 if (ah->ah_config.ath_hal_pcie_clock_req) { 1638 /* Pci-e Clock Request = 1 */ 1639 /* 1640 * PLL ON + clkreq enable is not a valid combination, 1641 * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1642 */ 1643 { 1644 /*Use driver default setting*/ 1645 /* Awake -> Sleep Setting */ 1646 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1647 ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1648 ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1649 2); 1650 /* Sleep -> Awake Setting */ 1651 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1652 ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1653 ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1654 2); 1655 } 1656 } 1657 else { 1658 /* Pci-e Clock Request = 0 */ 1659 if (ah->ah_config.ath_hal_pll_pwr_save & 1660 AR_PCIE_PLL_PWRSAVE_CONTROL) 1661 { 1662 /* Awake -> Sleep Setting */ 1663 if (ah->ah_config.ath_hal_pll_pwr_save & 1664 AR_PCIE_PLL_PWRSAVE_ON_D3) 1665 { 1666 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1667 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1668 ARRAY_LENGTH( 1669 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1670 2); 1671 } 1672 else { 1673 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1674 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1675 ARRAY_LENGTH( 1676 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1677 2); 1678 } 1679 /* Sleep -> Awake Setting */ 1680 if (ah->ah_config.ath_hal_pll_pwr_save & 1681 AR_PCIE_PLL_PWRSAVE_ON_D0) 1682 { 1683 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1684 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1685 ARRAY_LENGTH( 1686 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1687 2); 1688 } 1689 else { 1690 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1691 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1692 ARRAY_LENGTH( 1693 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1694 2); 1695 } 1696 1697 } 1698 else { 1699 /*Use driver default setting*/ 1700 /* Awake -> Sleep Setting */ 1701 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1702 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1703 ARRAY_LENGTH( 1704 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1705 2); 1706 /* Sleep -> Awake Setting */ 1707 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1708 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1709 ARRAY_LENGTH( 1710 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1711 2); 1712 } 1713 } 1714 1715 /* 1716 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1717 * 0 for merlin 1718 */ 1719 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1720 1721 #if 0 // ATH_WOW 1722 /* SerDes values during WOW sleep */ 1723 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1724 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1725 #endif 1726 1727 /* Fast clock modal settings */ 1728 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1729 ar9300Modes_fast_clock_jupiter_2p0, 1730 ARRAY_LENGTH(ar9300Modes_fast_clock_jupiter_2p0), 3); 1731 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1732 ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484, 1733 ARRAY_LENGTH( 1734 ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484), 2); 1735 1736 } else if (AR_SREV_APHRODITE(ah)) { 1737 /* Aphrodite: new INI format (pre, core, post arrays per subsystem) */ 1738 1739 /* mac */ 1740 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1741 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1742 ar956X_aphrodite_1p0_mac_core, 1743 ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_core), 2); 1744 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1745 ar956X_aphrodite_1p0_mac_postamble, 1746 ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_postamble), 5); 1747 1748 /* bb */ 1749 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1750 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1751 ar956X_aphrodite_1p0_baseband_core, 1752 ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_core), 2); 1753 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1754 ar956X_aphrodite_1p0_baseband_postamble, 1755 ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_postamble), 5); 1756 1757 //mark jupiter have but aphrodite don't have 1758 // /* radio */ 1759 // INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1760 // INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1761 // ar9300_aphrodite_1p0_radio_core, 1762 // ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_core), 2); 1763 // INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1764 // ar9300_aphrodite_1p0_radio_postamble, 1765 // ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_postamble), 5); 1766 1767 /* soc */ 1768 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1769 ar956X_aphrodite_1p0_soc_preamble, 1770 ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_preamble), 2); 1771 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1772 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1773 ar956X_aphrodite_1p0_soc_postamble, 1774 ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_postamble), 5); 1775 1776 /* rx/tx gain */ 1777 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1778 ar956XCommon_rx_gain_table_aphrodite_1p0, 1779 ARRAY_LENGTH(ar956XCommon_rx_gain_table_aphrodite_1p0), 2); 1780 //INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1781 // ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0, 1782 // ARRAY_LENGTH(ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0), 1783 // 5); 1784 1785 1786 /* 1787 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1788 * 0 for merlin 1789 */ 1790 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1791 1792 #if 0 // ATH_WOW 1793 /* SerDes values during WOW sleep */ 1794 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1795 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1796 #endif 1797 /* Fast clock modal settings */ 1798 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1799 ar956XModes_fast_clock_aphrodite_1p0, 1800 ARRAY_LENGTH(ar956XModes_fast_clock_aphrodite_1p0), 3); 1801 1802 } else if (AR_SREV_AR9580(ah)) { 1803 /* 1804 * AR9580/Peacock - 1805 * new INI format (pre, core, post arrays per subsystem) 1806 */ 1807 1808 /* mac */ 1809 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1810 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1811 ar9300_ar9580_1p0_mac_core, 1812 ARRAY_LENGTH(ar9300_ar9580_1p0_mac_core), 2); 1813 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1814 ar9300_ar9580_1p0_mac_postamble, 1815 ARRAY_LENGTH(ar9300_ar9580_1p0_mac_postamble), 5); 1816 1817 /* bb */ 1818 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1819 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1820 ar9300_ar9580_1p0_baseband_core, 1821 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_core), 2); 1822 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1823 ar9300_ar9580_1p0_baseband_postamble, 1824 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble), 5); 1825 1826 /* radio */ 1827 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1828 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1829 ar9300_ar9580_1p0_radio_core, 1830 ARRAY_LENGTH(ar9300_ar9580_1p0_radio_core), 2); 1831 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1832 ar9300_ar9580_1p0_radio_postamble, 1833 ARRAY_LENGTH(ar9300_ar9580_1p0_radio_postamble), 5); 1834 1835 /* soc */ 1836 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1837 ar9300_ar9580_1p0_soc_preamble, 1838 ARRAY_LENGTH(ar9300_ar9580_1p0_soc_preamble), 2); 1839 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1840 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1841 ar9300_ar9580_1p0_soc_postamble, 1842 ARRAY_LENGTH(ar9300_ar9580_1p0_soc_postamble), 5); 1843 1844 /* rx/tx gain */ 1845 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1846 ar9300_common_rx_gain_table_ar9580_1p0, 1847 ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 1848 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1849 ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 1850 ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 5); 1851 1852 /* DFS */ 1853 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1854 ar9300_ar9580_1p0_baseband_postamble_dfs_channel, 1855 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble_dfs_channel), 3); 1856 1857 1858 /* Load PCIE SERDES settings from INI */ 1859 1860 /*D3 Setting */ 1861 if (ah->ah_config.ath_hal_pcie_clock_req) { 1862 if (ah->ah_config.ath_hal_pll_pwr_save & 1863 AR_PCIE_PLL_PWRSAVE_CONTROL) 1864 { //registry control 1865 if (ah->ah_config.ath_hal_pll_pwr_save & 1866 AR_PCIE_PLL_PWRSAVE_ON_D3) 1867 { //bit1, in to D3 1868 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1869 ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 1870 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 1871 2); 1872 } else { 1873 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1874 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1875 ARRAY_LENGTH( 1876 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1877 2); 1878 } 1879 } else {//no registry control, default is pll on 1880 INIT_INI_ARRAY( 1881 &ahp->ah_ini_pcie_serdes, 1882 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1883 ARRAY_LENGTH( 1884 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1885 2); 1886 } 1887 } else { 1888 if (ah->ah_config.ath_hal_pll_pwr_save & 1889 AR_PCIE_PLL_PWRSAVE_CONTROL) 1890 { //registry control 1891 if (ah->ah_config.ath_hal_pll_pwr_save & 1892 AR_PCIE_PLL_PWRSAVE_ON_D3) 1893 { //bit1, in to D3 1894 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1895 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 1896 ARRAY_LENGTH( 1897 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 1898 2); 1899 } else { 1900 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1901 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1902 ARRAY_LENGTH( 1903 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1904 2); 1905 } 1906 } else {//no registry control, default is pll on 1907 INIT_INI_ARRAY( 1908 &ahp->ah_ini_pcie_serdes, 1909 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1910 ARRAY_LENGTH( 1911 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1912 2); 1913 } 1914 } 1915 1916 /*D0 Setting */ 1917 if (ah->ah_config.ath_hal_pcie_clock_req) { 1918 if (ah->ah_config.ath_hal_pll_pwr_save & 1919 AR_PCIE_PLL_PWRSAVE_CONTROL) 1920 { //registry control 1921 if (ah->ah_config.ath_hal_pll_pwr_save & 1922 AR_PCIE_PLL_PWRSAVE_ON_D0) 1923 { //bit2, out of D3 1924 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1925 ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 1926 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 1927 2); 1928 1929 } else { 1930 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1931 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1932 ARRAY_LENGTH( 1933 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1934 2); 1935 } 1936 } else { //no registry control, default is pll on 1937 INIT_INI_ARRAY( 1938 &ahp->ah_ini_pcie_serdes_low_power, 1939 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1940 ARRAY_LENGTH( 1941 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1942 2); 1943 } 1944 } else { 1945 if (ah->ah_config.ath_hal_pll_pwr_save & 1946 AR_PCIE_PLL_PWRSAVE_CONTROL) 1947 {//registry control 1948 if (ah->ah_config.ath_hal_pll_pwr_save & 1949 AR_PCIE_PLL_PWRSAVE_ON_D0) 1950 {//bit2, out of D3 1951 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1952 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 1953 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 1954 2); 1955 } else { 1956 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1957 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1958 ARRAY_LENGTH( 1959 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1960 2); 1961 } 1962 } else { //no registry control, default is pll on 1963 INIT_INI_ARRAY( 1964 &ahp->ah_ini_pcie_serdes_low_power, 1965 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1966 ARRAY_LENGTH( 1967 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1968 2); 1969 } 1970 } 1971 1972 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1973 1974 #if 0 /* ATH_WOW */ 1975 /* SerDes values during WOW sleep */ 1976 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 1977 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 1978 #endif 1979 1980 /* Fast clock modal settings */ 1981 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1982 ar9300Modes_fast_clock_ar9580_1p0, 1983 ARRAY_LENGTH(ar9300Modes_fast_clock_ar9580_1p0), 3); 1984 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1985 ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484, 1986 ARRAY_LENGTH( 1987 ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484), 2); 1988 1989 } else { 1990 /* 1991 * Osprey 2.2 - new INI format (pre, core, post arrays per subsystem) 1992 */ 1993 1994 /* mac */ 1995 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1996 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1997 ar9300_osprey_2p2_mac_core, 1998 ARRAY_LENGTH(ar9300_osprey_2p2_mac_core), 2); 1999 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 2000 ar9300_osprey_2p2_mac_postamble, 2001 ARRAY_LENGTH(ar9300_osprey_2p2_mac_postamble), 5); 2002 2003 /* bb */ 2004 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 2005 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 2006 ar9300_osprey_2p2_baseband_core, 2007 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_core), 2); 2008 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 2009 ar9300_osprey_2p2_baseband_postamble, 2010 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble), 5); 2011 2012 /* radio */ 2013 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 2014 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 2015 ar9300_osprey_2p2_radio_core, 2016 ARRAY_LENGTH(ar9300_osprey_2p2_radio_core), 2); 2017 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 2018 ar9300_osprey_2p2_radio_postamble, 2019 ARRAY_LENGTH(ar9300_osprey_2p2_radio_postamble), 5); 2020 2021 /* soc */ 2022 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 2023 ar9300_osprey_2p2_soc_preamble, 2024 ARRAY_LENGTH(ar9300_osprey_2p2_soc_preamble), 2); 2025 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 2026 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 2027 ar9300_osprey_2p2_soc_postamble, 2028 ARRAY_LENGTH(ar9300_osprey_2p2_soc_postamble), 5); 2029 2030 /* rx/tx gain */ 2031 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 2032 ar9300_common_rx_gain_table_osprey_2p2, 2033 ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 2034 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 2035 ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 2036 ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 5); 2037 2038 /* DFS */ 2039 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 2040 ar9300_osprey_2p2_baseband_postamble_dfs_channel, 2041 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble_dfs_channel), 3); 2042 2043 /* Load PCIE SERDES settings from INI */ 2044 2045 /*D3 Setting */ 2046 if (ah->ah_config.ath_hal_pcie_clock_req) { 2047 if (ah->ah_config.ath_hal_pll_pwr_save & 2048 AR_PCIE_PLL_PWRSAVE_CONTROL) 2049 { //registry control 2050 if (ah->ah_config.ath_hal_pll_pwr_save & 2051 AR_PCIE_PLL_PWRSAVE_ON_D3) 2052 { //bit1, in to D3 2053 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2054 ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2055 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2056 2); 2057 } else { 2058 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2059 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2060 ARRAY_LENGTH( 2061 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2062 2); 2063 } 2064 } else {//no registry control, default is pll on 2065 #ifndef ATH_BUS_PM 2066 INIT_INI_ARRAY( 2067 &ahp->ah_ini_pcie_serdes, 2068 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2069 ARRAY_LENGTH( 2070 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2071 2); 2072 #else 2073 //no registry control, default is pll off 2074 INIT_INI_ARRAY( 2075 &ahp->ah_ini_pcie_serdes, 2076 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2077 ARRAY_LENGTH( 2078 ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2079 2); 2080 #endif 2081 2082 } 2083 } else { 2084 if (ah->ah_config.ath_hal_pll_pwr_save & 2085 AR_PCIE_PLL_PWRSAVE_CONTROL) 2086 { //registry control 2087 if (ah->ah_config.ath_hal_pll_pwr_save & 2088 AR_PCIE_PLL_PWRSAVE_ON_D3) 2089 { //bit1, in to D3 2090 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2091 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2092 ARRAY_LENGTH( 2093 ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2094 2); 2095 } else { 2096 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2097 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2098 ARRAY_LENGTH( 2099 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2100 2); 2101 } 2102 } else { 2103 #ifndef ATH_BUS_PM 2104 //no registry control, default is pll on 2105 INIT_INI_ARRAY( 2106 &ahp->ah_ini_pcie_serdes, 2107 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2108 ARRAY_LENGTH( 2109 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2110 2); 2111 #else 2112 //no registry control, default is pll off 2113 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2114 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2); 2115 #endif 2116 } 2117 } 2118 2119 /*D0 Setting */ 2120 if (ah->ah_config.ath_hal_pcie_clock_req) { 2121 if (ah->ah_config.ath_hal_pll_pwr_save & 2122 AR_PCIE_PLL_PWRSAVE_CONTROL) 2123 { //registry control 2124 if (ah->ah_config.ath_hal_pll_pwr_save & 2125 AR_PCIE_PLL_PWRSAVE_ON_D0) 2126 { //bit2, out of D3 2127 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2128 ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2129 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2130 2); 2131 2132 } else { 2133 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2134 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2135 ARRAY_LENGTH( 2136 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2137 2); 2138 } 2139 } else { //no registry control, default is pll on 2140 INIT_INI_ARRAY( 2141 &ahp->ah_ini_pcie_serdes_low_power, 2142 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2143 ARRAY_LENGTH( 2144 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2145 2); 2146 } 2147 } else { 2148 if (ah->ah_config.ath_hal_pll_pwr_save & 2149 AR_PCIE_PLL_PWRSAVE_CONTROL) 2150 {//registry control 2151 if (ah->ah_config.ath_hal_pll_pwr_save & 2152 AR_PCIE_PLL_PWRSAVE_ON_D0) 2153 {//bit2, out of D3 2154 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2155 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2156 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2157 2); 2158 } else { 2159 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2160 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2161 ARRAY_LENGTH( 2162 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2163 2); 2164 } 2165 } else { //no registry control, default is pll on 2166 INIT_INI_ARRAY( 2167 &ahp->ah_ini_pcie_serdes_low_power, 2168 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2169 ARRAY_LENGTH( 2170 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2171 2); 2172 } 2173 } 2174 2175 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 2176 2177 #ifdef ATH_BUS_PM 2178 /*Use HAL to config PCI powersave by writing into the SerDes Registers */ 2179 ah->ah_config.ath_hal_pcie_ser_des_write = 1; 2180 #endif 2181 2182 #if 0 /* ATH_WOW */ 2183 /* SerDes values during WOW sleep */ 2184 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 2185 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 2186 #endif 2187 2188 /* Fast clock modal settings */ 2189 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 2190 ar9300Modes_fast_clock_osprey_2p2, 2191 ARRAY_LENGTH(ar9300Modes_fast_clock_osprey_2p2), 3); 2192 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 2193 ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484, 2194 ARRAY_LENGTH( 2195 ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484), 2); 2196 2197 } 2198 2199 if(AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) 2200 { 2201 #define AR_SOC_RST_OTP_INTF 0xB80600B4 2202 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2203 2204 ahp->ah_enterprise_mode = REG_READ(AR_SOC_RST_OTP_INTF); 2205 if (AR_SREV_SCORPION(ah)) { 2206 ahp->ah_enterprise_mode = ahp->ah_enterprise_mode << 12; 2207 } 2208 ath_hal_printf (ah, "Enterprise mode: 0x%08x\n", ahp->ah_enterprise_mode); 2209 #undef REG_READ 2210 #undef AR_SOC_RST_OTP_INTF 2211 } else { 2212 ahp->ah_enterprise_mode = OS_REG_READ(ah, AR_ENT_OTP); 2213 } 2214 2215 2216 if (ahpriv->ah_ispcie) { 2217 ar9300_config_pci_power_save(ah, 0, 0); 2218 } else { 2219 ar9300_disable_pcie_phy(ah); 2220 } 2221 ath_hal_printf(ah, "%s: calling ar9300_hw_attach\n", __func__); 2222 ecode = ar9300_hw_attach(ah); 2223 if (ecode != HAL_OK) { 2224 goto bad; 2225 } 2226 2227 /* set gain table pointers according to values read from the eeprom */ 2228 ar9300_tx_gain_table_apply(ah); 2229 ar9300_rx_gain_table_apply(ah); 2230 2231 /* 2232 ** 2233 ** Got everything we need now to setup the capabilities. 2234 */ 2235 2236 if (!ar9300_fill_capability_info(ah)) { 2237 HALDEBUG(ah, HAL_DEBUG_RESET, 2238 "%s:failed ar9300_fill_capability_info\n", __func__); 2239 ecode = HAL_EEREAD; 2240 goto bad; 2241 } 2242 ecode = ar9300_init_mac_addr(ah); 2243 if (ecode != HAL_OK) { 2244 HALDEBUG(ah, HAL_DEBUG_RESET, 2245 "%s: failed initializing mac address\n", __func__); 2246 goto bad; 2247 } 2248 2249 /* 2250 * Initialize receive buffer size to MAC default 2251 */ 2252 ahp->rx_buf_size = HAL_RXBUFSIZE_DEFAULT; 2253 2254 #if ATH_WOW 2255 #if 0 2256 /* 2257 * Needs to be removed once we stop using XB92 XXX 2258 * FIXME: Check with latest boards too - SriniK 2259 */ 2260 ar9300_wow_set_gpio_reset_low(ah); 2261 #endif 2262 2263 /* 2264 * Clear the Wow Status. 2265 */ 2266 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), 2267 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)) | 2268 AR_PMCTRL_WOW_PME_CLR); 2269 OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, 2270 AR_WOW_CLEAR_EVENTS(OS_REG_READ(ah, AR_WOW_PATTERN_REG))); 2271 #endif 2272 2273 /* 2274 * Set the cur_trig_level to a value that works all modes - 11a/b/g or 11n 2275 * with aggregation enabled or disabled. 2276 */ 2277 ahp->ah_tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 2278 2279 if (AR_SREV_HORNET(ah)) { 2280 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_HORNET_2GHZ; 2281 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2282 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2283 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2284 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2285 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2286 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2287 } else if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 2288 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ; 2289 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2290 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ; 2291 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ; 2292 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2293 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ; 2294 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2295 } else { 2296 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ; 2297 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2298 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2299 if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 2300 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ; 2301 } else { 2302 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2303 } 2304 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2305 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2306 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2307 } 2308 2309 2310 2311 2312 /* init BB Panic Watchdog timeout */ 2313 if (AR_SREV_HORNET(ah)) { 2314 ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO_HORNET; 2315 } else { 2316 ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO; 2317 } 2318 2319 2320 /* 2321 * Determine whether tx IQ calibration HW should be enabled, 2322 * and whether tx IQ calibration should be performed during 2323 * AGC calibration, or separately. 2324 */ 2325 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2326 /* 2327 * Register not initialized yet. This flag will be re-initialized 2328 * after INI loading following each reset. 2329 */ 2330 ahp->tx_iq_cal_enable = 1; 2331 /* if tx IQ cal is enabled, do it together with AGC cal */ 2332 ahp->tx_iq_cal_during_agc_cal = 1; 2333 } else if (AR_SREV_POSEIDON_OR_LATER(ah) && !AR_SREV_WASP(ah)) { 2334 ahp->tx_iq_cal_enable = 1; 2335 ahp->tx_iq_cal_during_agc_cal = 1; 2336 } else { 2337 /* osprey, hornet, wasp */ 2338 ahp->tx_iq_cal_enable = 1; 2339 ahp->tx_iq_cal_during_agc_cal = 0; 2340 } 2341 return ah; 2342 2343 bad: 2344 if (ahp) { 2345 ar9300_detach((struct ath_hal *) ahp); 2346 } 2347 if (status) { 2348 *status = ecode; 2349 } 2350 return AH_NULL; 2351 } 2352 2353 void 2354 ar9300_detach(struct ath_hal *ah) 2355 { 2356 HALASSERT(ah != AH_NULL); 2357 HALASSERT(ah->ah_magic == AR9300_MAGIC); 2358 2359 /* Make sure that chip is awake before writing to it */ 2360 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 2361 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 2362 "%s: failed to wake up chip\n", 2363 __func__); 2364 } 2365 2366 ar9300_hw_detach(ah); 2367 ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 2368 2369 // ath_hal_hdprintf_deregister(ah); 2370 2371 if (AH9300(ah)->ah_cal_mem) 2372 ath_hal_free(AH9300(ah)->ah_cal_mem); 2373 AH9300(ah)->ah_cal_mem = AH_NULL; 2374 2375 ath_hal_free(ah); 2376 } 2377 2378 struct ath_hal_9300 * 2379 ar9300_new_state(u_int16_t devid, HAL_SOFTC sc, 2380 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, 2381 uint16_t *eepromdata, HAL_STATUS *status) 2382 { 2383 static const u_int8_t defbssidmask[IEEE80211_ADDR_LEN] = 2384 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2385 struct ath_hal_9300 *ahp; 2386 struct ath_hal *ah; 2387 2388 /* NB: memory is returned zero'd */ 2389 ahp = ath_hal_malloc(sizeof(struct ath_hal_9300)); 2390 if (ahp == AH_NULL) { 2391 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2392 "%s: cannot allocate memory for state block\n", 2393 __func__); 2394 *status = HAL_ENOMEM; 2395 return AH_NULL; 2396 } 2397 2398 ah = &ahp->ah_priv.h; 2399 /* set initial values */ 2400 2401 /* stub everything first */ 2402 ar9300_set_stub_functions(ah); 2403 2404 /* setup the FreeBSD HAL methods */ 2405 ar9300_attach_freebsd_ops(ah); 2406 2407 /* These are private to this particular file, so .. */ 2408 ah->ah_disablePCIE = ar9300_disable_pcie_phy; 2409 AH_PRIVATE(ah)->ah_getNfAdjust = ar9300_get_nf_adjust; 2410 AH_PRIVATE(ah)->ah_getChipPowerLimits = ar9300_get_chip_power_limits; 2411 2412 #if 0 2413 /* Attach Osprey structure as default hal structure */ 2414 OS_MEMCPY(&ahp->ah_priv.priv, &ar9300hal, sizeof(ahp->ah_priv.priv)); 2415 #endif 2416 2417 #if 0 2418 AH_PRIVATE(ah)->amem_handle = amem_handle; 2419 AH_PRIVATE(ah)->ah_osdev = osdev; 2420 #endif 2421 ah->ah_sc = sc; 2422 ah->ah_st = st; 2423 ah->ah_sh = sh; 2424 ah->ah_magic = AR9300_MAGIC; 2425 AH_PRIVATE(ah)->ah_devid = devid; 2426 2427 AH_PRIVATE(ah)->ah_flags = 0; 2428 2429 /* 2430 ** Initialize factory defaults in the private space 2431 */ 2432 // ath_hal_factory_defaults(AH_PRIVATE(ah), hal_conf_parm); 2433 ar9300_config_defaults_freebsd(ah); 2434 2435 /* XXX FreeBSD: cal is always in EEPROM */ 2436 #if 0 2437 if (!hal_conf_parm->calInFlash) { 2438 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2439 } 2440 #endif 2441 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2442 2443 #if 0 2444 if (ar9300_eep_data_in_flash(ah)) { 2445 ahp->ah_priv.priv.ah_eeprom_read = ar9300_flash_read; 2446 ahp->ah_priv.priv.ah_eeprom_dump = AH_NULL; 2447 } else { 2448 ahp->ah_priv.priv.ah_eeprom_read = ar9300_eeprom_read_word; 2449 } 2450 #endif 2451 2452 /* XXX FreeBSD - for now, just supports EEPROM reading */ 2453 ahp->ah_priv.ah_eepromRead = ar9300_eeprom_read_word; 2454 2455 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 2456 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 2457 2458 ahp->ah_atim_window = 0; /* [0..1000] */ 2459 ahp->ah_diversity_control = 2460 ah->ah_config.ath_hal_diversity_control; 2461 ahp->ah_antenna_switch_swap = 2462 ah->ah_config.ath_hal_antenna_switch_swap; 2463 2464 /* 2465 * Enable MIC handling. 2466 */ 2467 ahp->ah_sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 2468 ahp->ah_enable32k_hz_clock = DONT_USE_32KHZ;/* XXX */ 2469 ahp->ah_slot_time = (u_int) -1; 2470 ahp->ah_ack_timeout = (u_int) -1; 2471 OS_MEMCPY(&ahp->ah_bssid_mask, defbssidmask, IEEE80211_ADDR_LEN); 2472 2473 /* 2474 * 11g-specific stuff 2475 */ 2476 ahp->ah_g_beacon_rate = 0; /* adhoc beacon fixed rate */ 2477 2478 /* SM power mode: Attach time, disable any setting */ 2479 ahp->ah_sm_power_mode = HAL_SMPS_DEFAULT; 2480 2481 return ahp; 2482 } 2483 2484 HAL_BOOL 2485 ar9300_chip_test(struct ath_hal *ah) 2486 { 2487 /*u_int32_t reg_addr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };*/ 2488 u_int32_t reg_addr[2] = { AR_STA_ID0 }; 2489 u_int32_t reg_hold[2]; 2490 u_int32_t pattern_data[4] = 2491 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 2492 int i, j; 2493 2494 /* Test PHY & MAC registers */ 2495 for (i = 0; i < 1; i++) { 2496 u_int32_t addr = reg_addr[i]; 2497 u_int32_t wr_data, rd_data; 2498 2499 reg_hold[i] = OS_REG_READ(ah, addr); 2500 for (j = 0; j < 0x100; j++) { 2501 wr_data = (j << 16) | j; 2502 OS_REG_WRITE(ah, addr, wr_data); 2503 rd_data = OS_REG_READ(ah, addr); 2504 if (rd_data != wr_data) { 2505 HALDEBUG(ah, HAL_DEBUG_REGIO, 2506 "%s: address test failed addr: " 2507 "0x%08x - wr:0x%08x != rd:0x%08x\n", 2508 __func__, addr, wr_data, rd_data); 2509 return AH_FALSE; 2510 } 2511 } 2512 for (j = 0; j < 4; j++) { 2513 wr_data = pattern_data[j]; 2514 OS_REG_WRITE(ah, addr, wr_data); 2515 rd_data = OS_REG_READ(ah, addr); 2516 if (wr_data != rd_data) { 2517 HALDEBUG(ah, HAL_DEBUG_REGIO, 2518 "%s: address test failed addr: " 2519 "0x%08x - wr:0x%08x != rd:0x%08x\n", 2520 __func__, addr, wr_data, rd_data); 2521 return AH_FALSE; 2522 } 2523 } 2524 OS_REG_WRITE(ah, reg_addr[i], reg_hold[i]); 2525 } 2526 OS_DELAY(100); 2527 return AH_TRUE; 2528 } 2529 2530 /* 2531 * Store the channel edges for the requested operational mode 2532 */ 2533 HAL_BOOL 2534 ar9300_get_channel_edges(struct ath_hal *ah, 2535 u_int16_t flags, u_int16_t *low, u_int16_t *high) 2536 { 2537 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2538 HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2539 2540 if (flags & IEEE80211_CHAN_5GHZ) { 2541 *low = p_cap->halLow5GhzChan; 2542 *high = p_cap->halHigh5GhzChan; 2543 return AH_TRUE; 2544 } 2545 if ((flags & IEEE80211_CHAN_2GHZ)) { 2546 *low = p_cap->halLow2GhzChan; 2547 *high = p_cap->halHigh2GhzChan; 2548 2549 return AH_TRUE; 2550 } 2551 return AH_FALSE; 2552 } 2553 2554 HAL_BOOL 2555 ar9300_regulatory_domain_override(struct ath_hal *ah, u_int16_t regdmn) 2556 { 2557 AH_PRIVATE(ah)->ah_currentRD = regdmn; 2558 return AH_TRUE; 2559 } 2560 2561 /* 2562 * Fill all software cached or static hardware state information. 2563 * Return failure if capabilities are to come from EEPROM and 2564 * cannot be read. 2565 */ 2566 HAL_BOOL 2567 ar9300_fill_capability_info(struct ath_hal *ah) 2568 { 2569 #define AR_KEYTABLE_SIZE 128 2570 struct ath_hal_9300 *ahp = AH9300(ah); 2571 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2572 HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2573 u_int16_t cap_field = 0, eeval; 2574 2575 ahpriv->ah_devType = (u_int16_t)ar9300_eeprom_get(ahp, EEP_DEV_TYPE); 2576 eeval = ar9300_eeprom_get(ahp, EEP_REG_0); 2577 2578 /* XXX record serial number */ 2579 AH_PRIVATE(ah)->ah_currentRD = eeval; 2580 2581 /* Always enable fast clock; leave it up to EEPROM and channel */ 2582 p_cap->halSupportsFastClock5GHz = AH_TRUE; 2583 2584 p_cap->halIntrMitigation = AH_TRUE; 2585 eeval = ar9300_eeprom_get(ahp, EEP_REG_1); 2586 AH_PRIVATE(ah)->ah_currentRDext = eeval | AR9300_RDEXT_DEFAULT; 2587 2588 /* Read the capability EEPROM location */ 2589 cap_field = ar9300_eeprom_get(ahp, EEP_OP_CAP); 2590 2591 /* Construct wireless mode from EEPROM */ 2592 p_cap->halWirelessModes = 0; 2593 eeval = ar9300_eeprom_get(ahp, EEP_OP_MODE); 2594 2595 /* 2596 * XXX FreeBSD specific: for now, set ath_hal_ht_enable to 1, 2597 * or we won't have 11n support. 2598 */ 2599 ah->ah_config.ath_hal_ht_enable = 1; 2600 2601 if (eeval & AR9300_OPFLAGS_11A) { 2602 p_cap->halWirelessModes |= HAL_MODE_11A | 2603 ((!ah->ah_config.ath_hal_ht_enable || 2604 (eeval & AR9300_OPFLAGS_N_5G_HT20)) ? 0 : 2605 (HAL_MODE_11NA_HT20 | ((eeval & AR9300_OPFLAGS_N_5G_HT40) ? 0 : 2606 (HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)))); 2607 } 2608 if (eeval & AR9300_OPFLAGS_11G) { 2609 p_cap->halWirelessModes |= HAL_MODE_11B | HAL_MODE_11G | 2610 ((!ah->ah_config.ath_hal_ht_enable || 2611 (eeval & AR9300_OPFLAGS_N_2G_HT20)) ? 0 : 2612 (HAL_MODE_11NG_HT20 | ((eeval & AR9300_OPFLAGS_N_2G_HT40) ? 0 : 2613 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS)))); 2614 } 2615 2616 /* Get chainamsks from eeprom */ 2617 p_cap->halTxChainMask = ar9300_eeprom_get(ahp, EEP_TX_MASK); 2618 p_cap->halRxChainMask = ar9300_eeprom_get(ahp, EEP_RX_MASK); 2619 2620 2621 2622 #define owl_get_ntxchains(_txchainmask) \ 2623 (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 2624 2625 /* FreeBSD: Update number of TX/RX streams */ 2626 p_cap->halTxStreams = owl_get_ntxchains(p_cap->halTxChainMask); 2627 p_cap->halRxStreams = owl_get_ntxchains(p_cap->halRxChainMask); 2628 2629 2630 /* 2631 * This being a newer chip supports TKIP non-splitmic mode. 2632 * 2633 */ 2634 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2635 p_cap->halTkipMicTxRxKeySupport = AH_TRUE; 2636 2637 p_cap->halLow2GhzChan = 2312; 2638 p_cap->halHigh2GhzChan = 2732; 2639 2640 p_cap->halLow5GhzChan = 4920; 2641 p_cap->halHigh5GhzChan = 6100; 2642 2643 p_cap->halCipherCkipSupport = AH_FALSE; 2644 p_cap->halCipherTkipSupport = AH_TRUE; 2645 p_cap->halCipherAesCcmSupport = AH_TRUE; 2646 2647 p_cap->halMicCkipSupport = AH_FALSE; 2648 p_cap->halMicTkipSupport = AH_TRUE; 2649 p_cap->halMicAesCcmSupport = AH_TRUE; 2650 2651 p_cap->halChanSpreadSupport = AH_TRUE; 2652 p_cap->halSleepAfterBeaconBroken = AH_TRUE; 2653 2654 p_cap->halBurstSupport = AH_TRUE; 2655 p_cap->halChapTuningSupport = AH_TRUE; 2656 p_cap->halTurboPrimeSupport = AH_TRUE; 2657 p_cap->halFastFramesSupport = AH_FALSE; 2658 2659 p_cap->halTurboGSupport = p_cap->halWirelessModes & HAL_MODE_108G; 2660 2661 // p_cap->hal_xr_support = AH_FALSE; 2662 2663 p_cap->halHTSupport = 2664 ah->ah_config.ath_hal_ht_enable ? AH_TRUE : AH_FALSE; 2665 2666 p_cap->halGTTSupport = AH_TRUE; 2667 p_cap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 2668 p_cap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 2669 p_cap->halHTSGI20Support = AH_TRUE; 2670 p_cap->halVEOLSupport = AH_TRUE; 2671 p_cap->halBssIdMaskSupport = AH_TRUE; 2672 /* Bug 26802, fixed in later revs? */ 2673 p_cap->halMcastKeySrchSupport = AH_TRUE; 2674 p_cap->halTsfAddSupport = AH_TRUE; 2675 2676 if (cap_field & AR_EEPROM_EEPCAP_MAXQCU) { 2677 p_cap->halTotalQueues = MS(cap_field, AR_EEPROM_EEPCAP_MAXQCU); 2678 } else { 2679 p_cap->halTotalQueues = HAL_NUM_TX_QUEUES; 2680 } 2681 2682 if (cap_field & AR_EEPROM_EEPCAP_KC_ENTRIES) { 2683 p_cap->halKeyCacheSize = 2684 1 << MS(cap_field, AR_EEPROM_EEPCAP_KC_ENTRIES); 2685 } else { 2686 p_cap->halKeyCacheSize = AR_KEYTABLE_SIZE; 2687 } 2688 p_cap->halFastCCSupport = AH_TRUE; 2689 // p_cap->hal_num_mr_retries = 4; 2690 // ahp->hal_tx_trig_level_max = MAX_TX_FIFO_THRESHOLD; 2691 2692 p_cap->halNumGpioPins = AR9382_MAX_GPIO_PIN_NUM; 2693 2694 #if 0 2695 /* XXX Verify support in Osprey */ 2696 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 2697 p_cap->halWowSupport = AH_TRUE; 2698 p_cap->hal_wow_match_pattern_exact = AH_TRUE; 2699 if (AR_SREV_MERLIN(ah)) { 2700 p_cap->hal_wow_pattern_match_dword = AH_TRUE; 2701 } 2702 } else { 2703 p_cap->halWowSupport = AH_FALSE; 2704 p_cap->hal_wow_match_pattern_exact = AH_FALSE; 2705 } 2706 #endif 2707 p_cap->halWowSupport = AH_TRUE; 2708 p_cap->halWowMatchPatternExact = AH_TRUE; 2709 if (AR_SREV_POSEIDON(ah)) { 2710 p_cap->halWowMatchPatternExact = AH_TRUE; 2711 } 2712 2713 p_cap->halCSTSupport = AH_TRUE; 2714 2715 p_cap->halRifsRxSupport = AH_TRUE; 2716 p_cap->halRifsTxSupport = AH_TRUE; 2717 2718 #define IEEE80211_AMPDU_LIMIT_MAX (65536) 2719 p_cap->halRtsAggrLimit = IEEE80211_AMPDU_LIMIT_MAX; 2720 #undef IEEE80211_AMPDU_LIMIT_MAX 2721 2722 p_cap->halMfpSupport = ah->ah_config.ath_hal_mfp_support; 2723 2724 p_cap->halForcePpmSupport = AH_TRUE; 2725 p_cap->halHwBeaconProcSupport = AH_TRUE; 2726 2727 /* ar9300 - has the HW UAPSD trigger support, 2728 * but it has the following limitations 2729 * The power state change from the following 2730 * frames are not put in High priority queue. 2731 * i) Mgmt frames 2732 * ii) NoN QoS frames 2733 * iii) QoS frames form the access categories for which 2734 * UAPSD is not enabled. 2735 * so we can not enable this feature currently. 2736 * could be enabled, if these limitations are fixed 2737 * in later versions of ar9300 chips 2738 */ 2739 p_cap->halHasUapsdSupport = AH_FALSE; 2740 2741 /* Number of buffers that can be help in a single TxD */ 2742 p_cap->halNumTxMaps = 4; 2743 2744 p_cap->halTxDescLen = sizeof(struct ar9300_txc); 2745 p_cap->halTxStatusLen = sizeof(struct ar9300_txs); 2746 p_cap->halRxStatusLen = sizeof(struct ar9300_rxs); 2747 2748 p_cap->halRxHpFifoDepth = HAL_HP_RXFIFO_DEPTH; 2749 p_cap->halRxLpFifoDepth = HAL_LP_RXFIFO_DEPTH; 2750 2751 /* Enable extension channel DFS support */ 2752 p_cap->halUseCombinedRadarRssi = AH_TRUE; 2753 p_cap->halExtChanDfsSupport = AH_TRUE; 2754 #if ATH_SUPPORT_SPECTRAL 2755 p_cap->halSpectralScanSupport = AH_TRUE; 2756 #endif 2757 2758 ahpriv->ah_rfsilent = ar9300_eeprom_get(ahp, EEP_RF_SILENT); 2759 if (ahpriv->ah_rfsilent & EEP_RFSILENT_ENABLED) { 2760 ahp->ah_gpio_select = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); 2761 ahp->ah_polarity = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_POLARITY); 2762 2763 ath_hal_enable_rfkill(ah, AH_TRUE); 2764 p_cap->halRfSilentSupport = AH_TRUE; 2765 } 2766 2767 /* XXX */ 2768 p_cap->halWpsPushButtonSupport = AH_FALSE; 2769 2770 #ifdef ATH_BT_COEX 2771 p_cap->halBtCoexSupport = AH_TRUE; 2772 p_cap->halBtCoexApsmWar = AH_FALSE; 2773 #endif 2774 2775 p_cap->halGenTimerSupport = AH_TRUE; 2776 ahp->ah_avail_gen_timers = ~((1 << AR_FIRST_NDP_TIMER) - 1); 2777 ahp->ah_avail_gen_timers &= (1 << AR_NUM_GEN_TIMERS) - 1; 2778 /* 2779 * According to Kyungwan, generic timer 0 and 8 are special 2780 * timers. Remove timer 8 from the available gen timer list. 2781 * Jupiter testing shows timer won't trigger with timer 8. 2782 */ 2783 ahp->ah_avail_gen_timers &= ~(1 << AR_GEN_TIMER_RESERVED); 2784 2785 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2786 #if ATH_SUPPORT_MCI 2787 if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_DISABLE_MCI) 2788 { 2789 p_cap->halMciSupport = AH_FALSE; 2790 } 2791 else 2792 #endif 2793 { 2794 p_cap->halMciSupport = (ahp->ah_enterprise_mode & 2795 AR_ENT_OTP_49GHZ_DISABLE) ? AH_FALSE: AH_TRUE; 2796 } 2797 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2798 "%s: (MCI) MCI support = %d\n", 2799 __func__, p_cap->halMciSupport); 2800 } 2801 else { 2802 p_cap->halMciSupport = AH_FALSE; 2803 } 2804 2805 if (AR_SREV_JUPITER_20(ah)) { 2806 p_cap->halRadioRetentionSupport = AH_TRUE; 2807 } else { 2808 p_cap->halRadioRetentionSupport = AH_FALSE; 2809 } 2810 2811 p_cap->halAutoSleepSupport = AH_TRUE; 2812 2813 p_cap->halMbssidAggrSupport = AH_TRUE; 2814 // p_cap->hal_proxy_sta_support = AH_TRUE; 2815 2816 /* XXX Mark it true after it is verfied as fixed */ 2817 p_cap->hal4kbSplitTransSupport = AH_FALSE; 2818 2819 /* Read regulatory domain flag */ 2820 if (AH_PRIVATE(ah)->ah_currentRDext & (1 << REG_EXT_JAPAN_MIDBAND)) { 2821 /* 2822 * If REG_EXT_JAPAN_MIDBAND is set, turn on U1 EVEN, U2, and MIDBAND. 2823 */ 2824 p_cap->halRegCap = 2825 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 2826 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 2827 AR_EEPROM_EEREGCAP_EN_KK_U2 | 2828 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 2829 } else { 2830 p_cap->halRegCap = 2831 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 2832 } 2833 2834 /* For AR9300 and above, midband channels are always supported */ 2835 p_cap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 2836 2837 p_cap->halNumAntCfg5GHz = 2838 ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ); 2839 p_cap->halNumAntCfg2GHz = 2840 ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ); 2841 2842 /* STBC supported */ 2843 p_cap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */ 2844 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 2845 p_cap->halTxStbcSupport = 0; 2846 } else { 2847 p_cap->halTxStbcSupport = 1; 2848 } 2849 2850 p_cap->halEnhancedDmaSupport = AH_TRUE; 2851 p_cap->halEnhancedDfsSupport = AH_TRUE; 2852 2853 /* 2854 * EV61133 (missing interrupts due to AR_ISR_RAC). 2855 * Fixed in Osprey 2.0. 2856 */ 2857 p_cap->halIsrRacSupport = AH_TRUE; 2858 2859 /* XXX FreeBSD won't support TKIP and WEP aggregation */ 2860 #if 0 2861 p_cap->hal_wep_tkip_aggr_support = AH_TRUE; 2862 p_cap->hal_wep_tkip_aggr_num_tx_delim = 10; /* TBD */ 2863 p_cap->hal_wep_tkip_aggr_num_rx_delim = 10; /* TBD */ 2864 p_cap->hal_wep_tkip_max_ht_rate = 15; /* TBD */ 2865 #endif 2866 2867 /* 2868 * XXX FreeBSD won't need these; but eventually add them 2869 * and add the WARs - AGGR extra delim WAR is useful to know 2870 * about. 2871 */ 2872 #if 0 2873 p_cap->hal_cfend_fix_support = AH_FALSE; 2874 p_cap->hal_aggr_extra_delim_war = AH_FALSE; 2875 #endif 2876 p_cap->halHasLongRxDescTsf = AH_TRUE; 2877 // p_cap->hal_rx_desc_timestamp_bits = 32; 2878 p_cap->halRxTxAbortSupport = AH_TRUE; 2879 p_cap->hal_ani_poll_interval = AR9300_ANI_POLLINTERVAL; 2880 p_cap->hal_channel_switch_time_usec = AR9300_CHANNEL_SWITCH_TIME_USEC; 2881 2882 /* Transmit Beamforming supported, fill capabilities */ 2883 p_cap->halPaprdEnabled = ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED); 2884 p_cap->halChanHalfRate = 2885 !(ahp->ah_enterprise_mode & AR_ENT_OTP_10MHZ_DISABLE); 2886 p_cap->halChanQuarterRate = 2887 !(ahp->ah_enterprise_mode & AR_ENT_OTP_5MHZ_DISABLE); 2888 2889 if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 2890 /* There is no AR_ENT_OTP_49GHZ_DISABLE feature in Jupiter, now the bit is used to disable BT. */ 2891 p_cap->hal49GhzSupport = 1; 2892 } else { 2893 p_cap->hal49GhzSupport = !(ahp->ah_enterprise_mode & AR_ENT_OTP_49GHZ_DISABLE); 2894 } 2895 2896 if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah) || AR_SREV_APHRODITE(ah)) { 2897 /* LDPC supported */ 2898 /* Poseidon doesn't support LDPC, or it will cause receiver CRC Error */ 2899 p_cap->halLDPCSupport = AH_FALSE; 2900 /* PCI_E LCR offset */ 2901 if (AR_SREV_POSEIDON(ah)) { 2902 p_cap->hal_pcie_lcr_offset = 0x80; /*for Poseidon*/ 2903 } 2904 /*WAR method for APSM L0s with Poseidon 1.0*/ 2905 if (AR_SREV_POSEIDON_10(ah)) { 2906 p_cap->hal_pcie_lcr_extsync_en = AH_TRUE; 2907 } 2908 } else { 2909 p_cap->halLDPCSupport = AH_TRUE; 2910 } 2911 2912 /* XXX is this a flag, or a chainmask number? */ 2913 p_cap->halApmEnable = !! ar9300_eeprom_get(ahp, EEP_CHAIN_MASK_REDUCE); 2914 #if ATH_ANT_DIV_COMB 2915 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { 2916 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) { 2917 u_int8_t ant_div_control1 = 2918 ar9300_eeprom_get(ahp, EEP_ANTDIV_control); 2919 /* if enable_lnadiv is 0x1 and enable_fast_div is 0x1, 2920 * we enable the diversity-combining algorithm. 2921 */ 2922 if ((ant_div_control1 >> 0x6) == 0x3) { 2923 p_cap->halAntDivCombSupport = AH_TRUE; 2924 } 2925 p_cap->halAntDivCombSupportOrg = p_cap->halAntDivCombSupport; 2926 } 2927 } 2928 #endif /* ATH_ANT_DIV_COMB */ 2929 2930 /* 2931 * FreeBSD: enable LNA mixing if the chip is Hornet or Poseidon. 2932 */ 2933 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { 2934 p_cap->halRxUsingLnaMixing = AH_TRUE; 2935 } 2936 2937 /* 2938 * AR5416 and later NICs support MYBEACON filtering. 2939 */ 2940 p_cap->halRxDoMyBeacon = AH_TRUE; 2941 2942 #if ATH_WOW_OFFLOAD 2943 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { 2944 p_cap->hal_wow_gtk_offload_support = AH_TRUE; 2945 p_cap->hal_wow_arp_offload_support = AH_TRUE; 2946 p_cap->hal_wow_ns_offload_support = AH_TRUE; 2947 p_cap->hal_wow_4way_hs_wakeup_support = AH_TRUE; 2948 p_cap->hal_wow_acer_magic_support = AH_TRUE; 2949 p_cap->hal_wow_acer_swka_support = AH_TRUE; 2950 } else { 2951 p_cap->hal_wow_gtk_offload_support = AH_FALSE; 2952 p_cap->hal_wow_arp_offload_support = AH_FALSE; 2953 p_cap->hal_wow_ns_offload_support = AH_FALSE; 2954 p_cap->hal_wow_4way_hs_wakeup_support = AH_FALSE; 2955 p_cap->hal_wow_acer_magic_support = AH_FALSE; 2956 p_cap->hal_wow_acer_swka_support = AH_FALSE; 2957 } 2958 #endif /* ATH_WOW_OFFLOAD */ 2959 2960 2961 return AH_TRUE; 2962 #undef AR_KEYTABLE_SIZE 2963 } 2964 2965 #if 0 2966 static HAL_BOOL 2967 ar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans, 2968 u_int32_t nchans) 2969 { 2970 struct ath_hal_9300 *ahp = AH9300(ah); 2971 2972 return ahp->ah_rf_hal.get_chip_power_lim(ah, chans, nchans); 2973 } 2974 #endif 2975 /* XXX FreeBSD */ 2976 2977 static HAL_BOOL 2978 ar9300_get_chip_power_limits(struct ath_hal *ah, 2979 struct ieee80211_channel *chan) 2980 { 2981 2982 chan->ic_maxpower = AR9300_MAX_RATE_POWER; 2983 chan->ic_minpower = 0; 2984 2985 return AH_TRUE; 2986 } 2987 2988 /* 2989 * Disable PLL when in L0s as well as receiver clock when in L1. 2990 * This power saving option must be enabled through the Serdes. 2991 * 2992 * Programming the Serdes must go through the same 288 bit serial shift 2993 * register as the other analog registers. Hence the 9 writes. 2994 * 2995 * XXX Clean up the magic numbers. 2996 */ 2997 void 2998 ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off) 2999 { 3000 struct ath_hal_9300 *ahp = AH9300(ah); 3001 int i; 3002 3003 if (AH_PRIVATE(ah)->ah_ispcie != AH_TRUE) { 3004 return; 3005 } 3006 3007 /* 3008 * Increase L1 Entry Latency. Some WB222 boards don't have 3009 * this change in eeprom/OTP. 3010 */ 3011 if (AR_SREV_JUPITER(ah)) { 3012 u_int32_t val = ah->ah_config.ath_hal_war70c; 3013 if ((val & 0xff000000) == 0x17000000) { 3014 val &= 0x00ffffff; 3015 val |= 0x27000000; 3016 OS_REG_WRITE(ah, 0x570c, val); 3017 } 3018 } 3019 3020 /* Do not touch SERDES registers */ 3021 if (ah->ah_config.ath_hal_pcie_power_save_enable == 2) { 3022 return; 3023 } 3024 3025 /* Nothing to do on restore for 11N */ 3026 if (!restore) { 3027 /* set bit 19 to allow forcing of pcie core into L1 state */ 3028 OS_REG_SET_BIT(ah, 3029 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), AR_PCIE_PM_CTRL_ENA); 3030 3031 /* 3032 * Set PCIE workaround config only if requested, else use the reset 3033 * value of this register. 3034 */ 3035 if (ah->ah_config.ath_hal_pcie_waen) { 3036 OS_REG_WRITE(ah, 3037 AR_HOSTIF_REG(ah, AR_WA), 3038 ah->ah_config.ath_hal_pcie_waen); 3039 } else { 3040 /* Set Bits 17 and 14 in the AR_WA register. */ 3041 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 3042 } 3043 } 3044 3045 /* Configure PCIE after Ini init. SERDES values now come from ini file */ 3046 if (ah->ah_config.ath_hal_pcie_ser_des_write) { 3047 if (power_off) { 3048 for (i = 0; i < ahp->ah_ini_pcie_serdes.ia_rows; i++) { 3049 OS_REG_WRITE(ah, 3050 INI_RA(&ahp->ah_ini_pcie_serdes, i, 0), 3051 INI_RA(&ahp->ah_ini_pcie_serdes, i, 1)); 3052 } 3053 } else { 3054 for (i = 0; i < ahp->ah_ini_pcie_serdes_low_power.ia_rows; i++) { 3055 OS_REG_WRITE(ah, 3056 INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 0), 3057 INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 1)); 3058 } 3059 } 3060 } 3061 3062 } 3063 3064 /* 3065 * Recipe from charles to turn off PCIe PHY in PCI mode for power savings 3066 */ 3067 void 3068 ar9300_disable_pcie_phy(struct ath_hal *ah) 3069 { 3070 /* Osprey does not support PCI mode */ 3071 } 3072 3073 static inline HAL_STATUS 3074 ar9300_init_mac_addr(struct ath_hal *ah) 3075 { 3076 u_int32_t sum; 3077 int i; 3078 u_int16_t eeval; 3079 struct ath_hal_9300 *ahp = AH9300(ah); 3080 u_int32_t EEP_MAC [] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 3081 3082 sum = 0; 3083 for (i = 0; i < 3; i++) { 3084 eeval = ar9300_eeprom_get(ahp, EEP_MAC[i]); 3085 sum += eeval; 3086 ahp->ah_macaddr[2*i] = eeval >> 8; 3087 ahp->ah_macaddr[2*i + 1] = eeval & 0xff; 3088 } 3089 if (sum == 0 || sum == 0xffff*3) { 3090 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: mac address read failed: %s\n", 3091 __func__, ath_hal_ether_sprintf(ahp->ah_macaddr)); 3092 return HAL_EEBADMAC; 3093 } 3094 3095 return HAL_OK; 3096 } 3097 3098 /* 3099 * Code for the "real" chip i.e. non-emulation. Review and revisit 3100 * when actual hardware is at hand. 3101 */ 3102 static inline HAL_STATUS 3103 ar9300_hw_attach(struct ath_hal *ah) 3104 { 3105 HAL_STATUS ecode; 3106 3107 if (!ar9300_chip_test(ah)) { 3108 HALDEBUG(ah, HAL_DEBUG_REGIO, 3109 "%s: hardware self-test failed\n", __func__); 3110 return HAL_ESELFTEST; 3111 } 3112 3113 ath_hal_printf(ah, "%s: calling ar9300_eeprom_attach\n", __func__); 3114 ecode = ar9300_eeprom_attach(ah); 3115 ath_hal_printf(ah, "%s: ar9300_eeprom_attach returned %d\n", __func__, ecode); 3116 if (ecode != HAL_OK) { 3117 return ecode; 3118 } 3119 if (!ar9300_rf_attach(ah, &ecode)) { 3120 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: RF setup failed, status %u\n", 3121 __func__, ecode); 3122 } 3123 3124 if (ecode != HAL_OK) { 3125 return ecode; 3126 } 3127 ar9300_ani_attach(ah); 3128 3129 return HAL_OK; 3130 } 3131 3132 static inline void 3133 ar9300_hw_detach(struct ath_hal *ah) 3134 { 3135 /* XXX EEPROM allocated state */ 3136 ar9300_ani_detach(ah); 3137 } 3138 3139 static int16_t 3140 ar9300_get_nf_adjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 3141 { 3142 return 0; 3143 } 3144 3145 void 3146 ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable) 3147 { 3148 struct ath_hal_9300 *ahp = AH9300(ah); 3149 u_int32_t m1_thresh_low = enable ? 127 : ahp->ah_immunity_vals[0], 3150 m2_thresh_low = enable ? 127 : ahp->ah_immunity_vals[1], 3151 m1_thresh = enable ? 127 : ahp->ah_immunity_vals[2], 3152 m2_thresh = enable ? 127 : ahp->ah_immunity_vals[3], 3153 m2_count_thr = enable ? 31 : ahp->ah_immunity_vals[4], 3154 m2_count_thr_low = enable ? 63 : ahp->ah_immunity_vals[5]; 3155 3156 if (ahp->ah_immunity_on == enable) { 3157 return; 3158 } 3159 3160 ahp->ah_immunity_on = enable; 3161 3162 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3163 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low); 3164 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3165 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low); 3166 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3167 AR_PHY_SFCORR_M1_THRESH, m1_thresh); 3168 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3169 AR_PHY_SFCORR_M2_THRESH, m2_thresh); 3170 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3171 AR_PHY_SFCORR_M2COUNT_THR, m2_count_thr); 3172 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3173 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low); 3174 3175 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3176 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low); 3177 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3178 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low); 3179 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3180 AR_PHY_SFCORR_EXT_M1_THRESH, m1_thresh); 3181 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3182 AR_PHY_SFCORR_EXT_M2_THRESH, m2_thresh); 3183 3184 if (!enable) { 3185 OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 3186 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3187 } else { 3188 OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 3189 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3190 } 3191 } 3192 3193 /* XXX FreeBSD: I'm not sure how to implement this.. */ 3194 #if 0 3195 int 3196 ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 3197 HAL_CAL_QUERY query) 3198 { 3199 #define AR9300_IS_CHAIN_RX_IQCAL_INVALID(_ah, _reg) \ 3200 ((OS_REG_READ((_ah), _reg) & 0x3fff) == 0) 3201 #define AR9300_IS_RX_IQCAL_DISABLED(_ah) \ 3202 (!(OS_REG_READ((_ah), AR_PHY_RX_IQCAL_CORR_B0) & \ 3203 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE)) 3204 /* Avoid comilation warnings. Variables are not used when EMULATION. */ 3205 struct ath_hal_9300 *ahp = AH9300(ah); 3206 u_int8_t rxchainmask = ahp->ah_rx_chainmask, i; 3207 int rx_iqcal_invalid = 0, num_chains = 0; 3208 static const u_int32_t offset_array[3] = { 3209 AR_PHY_RX_IQCAL_CORR_B0, 3210 AR_PHY_RX_IQCAL_CORR_B1, 3211 AR_PHY_RX_IQCAL_CORR_B2}; 3212 3213 *timerp = ar9300_cals; 3214 3215 switch (query) { 3216 case HAL_QUERY_CALS: 3217 return AR9300_NUM_CAL_TYPES; 3218 case HAL_QUERY_RERUN_CALS: 3219 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 3220 if (rxchainmask & (1 << i)) { 3221 num_chains++; 3222 } 3223 } 3224 for (i = 0; i < num_chains; i++) { 3225 if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 3226 HALASSERT(num_chains == 0x1); 3227 } 3228 if (AR9300_IS_CHAIN_RX_IQCAL_INVALID(ah, offset_array[i])) { 3229 rx_iqcal_invalid = 1; 3230 } 3231 } 3232 if (AR9300_IS_RX_IQCAL_DISABLED(ah)) { 3233 rx_iqcal_invalid = 1; 3234 } 3235 3236 return rx_iqcal_invalid; 3237 default: 3238 HALASSERT(0); 3239 } 3240 return 0; 3241 } 3242 #endif 3243 3244 #if ATH_TRAFFIC_FAST_RECOVER 3245 #define PLL3 0x16188 3246 #define PLL3_DO_MEAS_MASK 0x40000000 3247 #define PLL4 0x1618c 3248 #define PLL4_MEAS_DONE 0x8 3249 #define SQSUM_DVC_MASK 0x007ffff8 3250 unsigned long 3251 ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah) 3252 { 3253 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 3254 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK))); 3255 OS_DELAY(100); 3256 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK)); 3257 3258 while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 3259 OS_DELAY(100); 3260 } 3261 3262 return (( OS_REG_READ(ah, PLL3) & SQSUM_DVC_MASK ) >> 3); 3263 } else { 3264 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 3265 "%s: unable to get pll3_sqsum_dvc\n", 3266 __func__); 3267 return 0; 3268 } 3269 } 3270 #endif 3271 3272 3273 #define RX_GAIN_TABLE_LENGTH 128 3274 // this will be called if rfGainCAP is enabled and rfGainCAP setting is changed, 3275 // or rxGainTable setting is changed 3276 HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is_2GHz) 3277 { 3278 int i, done = 0, i_rx_gain = 32; 3279 u_int32_t rf_gain_cap; 3280 u_int32_t rx_gain_value, a_Byte, rx_gain_value_caped; 3281 static u_int32_t rx_gain_table[RX_GAIN_TABLE_LENGTH * 2][2]; 3282 ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; 3283 struct ath_hal_9300 *ahp = AH9300(ah); 3284 3285 if ( !((eep->base_eep_header.misc_configuration & 0x80) >> 7) ) 3286 return AH_FALSE; 3287 3288 if (is_2GHz) 3289 { 3290 rf_gain_cap = (u_int32_t) eep->modal_header_2g.rf_gain_cap; 3291 } 3292 else 3293 { 3294 rf_gain_cap = (u_int32_t) eep->modal_header_5g.rf_gain_cap; 3295 } 3296 3297 if (rf_gain_cap == 0) 3298 return AH_FALSE; 3299 3300 for (i = 0; i< RX_GAIN_TABLE_LENGTH * 2; i++) 3301 { 3302 if (AR_SREV_AR9580(ah)) 3303 { 3304 // BB_rx_ocgain2 3305 i_rx_gain = 128 + 32; 3306 switch (ar9300_rx_gain_index_get(ah)) 3307 { 3308 case 0: 3309 rx_gain_table[i][0] = 3310 ar9300_common_rx_gain_table_ar9580_1p0[i][0]; 3311 rx_gain_table[i][1] = 3312 ar9300_common_rx_gain_table_ar9580_1p0[i][1]; 3313 break; 3314 case 1: 3315 rx_gain_table[i][0] = 3316 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][0]; 3317 rx_gain_table[i][1] = 3318 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][1]; 3319 break; 3320 } 3321 } 3322 else if (AR_SREV_OSPREY_22(ah)) 3323 { 3324 i_rx_gain = 128 + 32; 3325 switch (ar9300_rx_gain_index_get(ah)) 3326 { 3327 case 0: 3328 rx_gain_table[i][0] = ar9300_common_rx_gain_table_osprey_2p2[i][0]; 3329 rx_gain_table[i][1] = ar9300_common_rx_gain_table_osprey_2p2[i][1]; 3330 break; 3331 case 1: 3332 rx_gain_table[i][0] = 3333 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][0]; 3334 rx_gain_table[i][1] = 3335 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][1]; 3336 break; 3337 } 3338 } 3339 else 3340 { 3341 return AH_FALSE; 3342 } 3343 } 3344 3345 while (1) 3346 { 3347 rx_gain_value = rx_gain_table[i_rx_gain][1]; 3348 rx_gain_value_caped = rx_gain_value; 3349 a_Byte = rx_gain_value & (0x000000FF); 3350 if (a_Byte>rf_gain_cap) 3351 { 3352 rx_gain_value_caped = (rx_gain_value_caped & 3353 (0xFFFFFF00)) + rf_gain_cap; 3354 } 3355 a_Byte = rx_gain_value & (0x0000FF00); 3356 if ( a_Byte > ( rf_gain_cap << 8 ) ) 3357 { 3358 rx_gain_value_caped = (rx_gain_value_caped & 3359 (0xFFFF00FF)) + (rf_gain_cap<<8); 3360 } 3361 a_Byte = rx_gain_value & (0x00FF0000); 3362 if ( a_Byte > ( rf_gain_cap << 16 ) ) 3363 { 3364 rx_gain_value_caped = (rx_gain_value_caped & 3365 (0xFF00FFFF)) + (rf_gain_cap<<16); 3366 } 3367 a_Byte = rx_gain_value & (0xFF000000); 3368 if ( a_Byte > ( rf_gain_cap << 24 ) ) 3369 { 3370 rx_gain_value_caped = (rx_gain_value_caped & 3371 (0x00FFFFFF)) + (rf_gain_cap<<24); 3372 } 3373 else 3374 { 3375 done = 1; 3376 } 3377 HALDEBUG(ah, HAL_DEBUG_RESET, 3378 "%s: rx_gain_address: %x, rx_gain_value: %x rx_gain_value_caped: %x\n", 3379 __func__, rx_gain_table[i_rx_gain][0], rx_gain_value, rx_gain_value_caped); 3380 if (rx_gain_value_caped != rx_gain_value) 3381 { 3382 rx_gain_table[i_rx_gain][1] = rx_gain_value_caped; 3383 } 3384 if (done == 1) 3385 break; 3386 i_rx_gain ++; 3387 } 3388 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, rx_gain_table, ARRAY_LENGTH(rx_gain_table), 2); 3389 return AH_TRUE; 3390 } 3391 3392 3393 void ar9300_rx_gain_table_apply(struct ath_hal *ah) 3394 { 3395 struct ath_hal_9300 *ahp = AH9300(ah); 3396 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 3397 u_int32_t xlan_gpio_cfg; 3398 u_int8_t i; 3399 3400 if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah)) 3401 { 3402 // this will be called if rxGainTable setting is changed 3403 if (ar9300_rf_gain_cap_apply(ah, 1)) 3404 return; 3405 } 3406 3407 switch (ar9300_rx_gain_index_get(ah)) 3408 { 3409 case 2: 3410 if (AR_SREV_JUPITER_10(ah)) { 3411 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3412 ar9300_common_mixed_rx_gain_table_jupiter_1p0, 3413 ARRAY_LENGTH(ar9300_common_mixed_rx_gain_table_jupiter_1p0), 2); 3414 break; 3415 } 3416 else if (AR_SREV_JUPITER_20(ah)) { 3417 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3418 ar9300Common_mixed_rx_gain_table_jupiter_2p0, 3419 ARRAY_LENGTH(ar9300Common_mixed_rx_gain_table_jupiter_2p0), 2); 3420 break; 3421 } 3422 case 0: 3423 default: 3424 if (AR_SREV_HORNET_12(ah)) { 3425 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3426 ar9331_common_rx_gain_hornet1_2, 3427 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 3428 } else if (AR_SREV_HORNET_11(ah)) { 3429 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3430 ar9331_common_rx_gain_hornet1_1, 3431 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 3432 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3433 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3434 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3435 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3436 /* XXX FreeBSD: this needs to be revisited!! */ 3437 xlan_gpio_cfg = ah->ah_config.ath_hal_ext_lna_ctl_gpio; 3438 if (xlan_gpio_cfg) { 3439 for (i = 0; i < 32; i++) { 3440 if (xlan_gpio_cfg & (1 << i)) { 3441 /* 3442 * XXX FreeBSD: definitely make sure this 3443 * results in the correct value being written 3444 * to the hardware, or weird crap is very likely 3445 * to occur! 3446 */ 3447 ath_hal_gpioCfgOutput(ah, i, 3448 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED); 3449 } 3450 } 3451 } 3452 3453 } else if (AR_SREV_POSEIDON(ah)) { 3454 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3455 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3456 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3457 } else if (AR_SREV_JUPITER_10(ah)) { 3458 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3459 ar9300_common_rx_gain_table_jupiter_1p0, 3460 ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 3461 } else if (AR_SREV_JUPITER_20(ah)) { 3462 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3463 ar9300Common_rx_gain_table_jupiter_2p0, 3464 ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 3465 } else if (AR_SREV_AR9580(ah)) { 3466 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3467 ar9300_common_rx_gain_table_ar9580_1p0, 3468 ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 3469 } else if (AR_SREV_WASP(ah)) { 3470 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3471 ar9340Common_rx_gain_table_wasp_1p0, 3472 ARRAY_LENGTH(ar9340Common_rx_gain_table_wasp_1p0), 2); 3473 } else if (AR_SREV_SCORPION(ah)) { 3474 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3475 ar955xCommon_rx_gain_table_scorpion_1p0, 3476 ARRAY_LENGTH(ar955xCommon_rx_gain_table_scorpion_1p0), 2); 3477 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3478 ar955xCommon_rx_gain_bounds_scorpion_1p0, 3479 ARRAY_LENGTH(ar955xCommon_rx_gain_bounds_scorpion_1p0), 5); 3480 } else { 3481 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3482 ar9300_common_rx_gain_table_osprey_2p2, 3483 ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 3484 } 3485 break; 3486 case 1: 3487 if (AR_SREV_HORNET_12(ah)) { 3488 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3489 ar9331_common_wo_xlna_rx_gain_hornet1_2, 3490 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_2), 2); 3491 } else if (AR_SREV_HORNET_11(ah)) { 3492 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3493 ar9331_common_wo_xlna_rx_gain_hornet1_1, 3494 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_1), 2); 3495 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3496 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3497 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3498 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3499 } else if (AR_SREV_POSEIDON(ah)) { 3500 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3501 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3502 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3503 } else if (AR_SREV_JUPITER_10(ah)) { 3504 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3505 ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0, 3506 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0), 3507 2); 3508 } else if (AR_SREV_JUPITER_20(ah)) { 3509 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3510 ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0, 3511 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0), 3512 2); 3513 } else if (AR_SREV_APHRODITE(ah)) { 3514 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3515 ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0, 3516 ARRAY_LENGTH(ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0), 3517 2); 3518 } else if (AR_SREV_AR9580(ah)) { 3519 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3520 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0, 3521 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0), 2); 3522 } else if (AR_SREV_WASP(ah)) { 3523 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3524 ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 3525 ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 3526 } else if (AR_SREV_SCORPION(ah)) { 3527 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3528 ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 3529 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 3530 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3531 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 3532 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 3533 } else { 3534 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3535 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2, 3536 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_osprey_2p2), 2); 3537 } 3538 break; 3539 } 3540 } 3541 3542 void ar9300_tx_gain_table_apply(struct ath_hal *ah) 3543 { 3544 struct ath_hal_9300 *ahp = AH9300(ah); 3545 3546 switch (ar9300_tx_gain_index_get(ah)) 3547 { 3548 case 0: 3549 default: 3550 if (AR_SREV_HORNET_12(ah)) { 3551 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3552 ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 3553 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 3554 } else if (AR_SREV_HORNET_11(ah)) { 3555 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3556 ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 3557 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 3558 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3559 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3560 ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 3561 ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 3562 } else if (AR_SREV_POSEIDON(ah)) { 3563 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3564 ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 3565 ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 3566 } else if (AR_SREV_AR9580(ah)) { 3567 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3568 ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 3569 ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 3570 5); 3571 } else if (AR_SREV_WASP(ah)) { 3572 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3573 ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0, 3574 ARRAY_LENGTH(ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0), 3575 5); 3576 } else if (AR_SREV_SCORPION(ah)) { 3577 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3578 ar955xModes_xpa_tx_gain_table_scorpion_1p0, 3579 ARRAY_LENGTH(ar955xModes_xpa_tx_gain_table_scorpion_1p0), 3580 9); 3581 } else if (AR_SREV_JUPITER_10(ah)) { 3582 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3583 ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0, 3584 ARRAY_LENGTH(ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0), 3585 5); 3586 } else if (AR_SREV_JUPITER_20(ah)) { 3587 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3588 ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0, 3589 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0), 3590 5); 3591 } else if (AR_SREV_APHRODITE(ah)) { 3592 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3593 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3594 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 3595 5); 3596 } else { 3597 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3598 ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 3599 ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 3600 5); 3601 } 3602 break; 3603 case 1: 3604 if (AR_SREV_HORNET_12(ah)) { 3605 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3606 ar9331_modes_high_ob_db_tx_gain_hornet1_2, 3607 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_2), 5); 3608 } else if (AR_SREV_HORNET_11(ah)) { 3609 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3610 ar9331_modes_high_ob_db_tx_gain_hornet1_1, 3611 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_1), 5); 3612 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3613 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3614 ar9485_modes_high_ob_db_tx_gain_poseidon1_1, 3615 ARRAY_LENGTH(ar9485_modes_high_ob_db_tx_gain_poseidon1_1), 5); 3616 } else if (AR_SREV_POSEIDON(ah)) { 3617 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3618 ar9485Modes_high_ob_db_tx_gain_poseidon1_0, 3619 ARRAY_LENGTH(ar9485Modes_high_ob_db_tx_gain_poseidon1_0), 5); 3620 } else if (AR_SREV_AR9580(ah)) { 3621 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3622 ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0, 3623 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0), 3624 5); 3625 } else if (AR_SREV_WASP(ah)) { 3626 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3627 ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 3628 ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 3629 } else if (AR_SREV_SCORPION(ah)) { 3630 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3631 ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 3632 ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 9); 3633 } else if (AR_SREV_JUPITER_10(ah)) { 3634 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3635 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0, 3636 ARRAY_LENGTH( 3637 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0), 5); 3638 } else if (AR_SREV_JUPITER_20(ah)) { 3639 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3640 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0, 3641 ARRAY_LENGTH( 3642 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0), 5); 3643 } else if (AR_SREV_APHRODITE(ah)) { 3644 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3645 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0, 3646 ARRAY_LENGTH( 3647 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0), 5); 3648 } else { 3649 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3650 ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2, 3651 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2), 3652 5); 3653 } 3654 break; 3655 case 2: 3656 if (AR_SREV_HORNET_12(ah)) { 3657 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3658 ar9331_modes_low_ob_db_tx_gain_hornet1_2, 3659 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_2), 5); 3660 } else if (AR_SREV_HORNET_11(ah)) { 3661 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3662 ar9331_modes_low_ob_db_tx_gain_hornet1_1, 3663 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_1), 5); 3664 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3665 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3666 ar9485_modes_low_ob_db_tx_gain_poseidon1_1, 3667 ARRAY_LENGTH(ar9485_modes_low_ob_db_tx_gain_poseidon1_1), 5); 3668 } else if (AR_SREV_POSEIDON(ah)) { 3669 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3670 ar9485Modes_low_ob_db_tx_gain_poseidon1_0, 3671 ARRAY_LENGTH(ar9485Modes_low_ob_db_tx_gain_poseidon1_0), 5); 3672 } else if (AR_SREV_AR9580(ah)) { 3673 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3674 ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0, 3675 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0), 3676 5); 3677 } else if (AR_SREV_WASP(ah)) { 3678 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3679 ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0, 3680 ARRAY_LENGTH(ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0), 5); 3681 } else if (AR_SREV_APHRODITE(ah)) { 3682 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3683 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3684 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 5); 3685 } else { 3686 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3687 ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2, 3688 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2), 3689 5); 3690 } 3691 break; 3692 case 3: 3693 if (AR_SREV_HORNET_12(ah)) { 3694 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3695 ar9331_modes_high_power_tx_gain_hornet1_2, 3696 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_2), 5); 3697 } else if (AR_SREV_HORNET_11(ah)) { 3698 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3699 ar9331_modes_high_power_tx_gain_hornet1_1, 3700 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_1), 5); 3701 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3702 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3703 ar9485_modes_high_power_tx_gain_poseidon1_1, 3704 ARRAY_LENGTH(ar9485_modes_high_power_tx_gain_poseidon1_1), 5); 3705 } else if (AR_SREV_POSEIDON(ah)) { 3706 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3707 ar9485Modes_high_power_tx_gain_poseidon1_0, 3708 ARRAY_LENGTH(ar9485Modes_high_power_tx_gain_poseidon1_0), 5); 3709 } else if (AR_SREV_AR9580(ah)) { 3710 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3711 ar9300Modes_high_power_tx_gain_table_ar9580_1p0, 3712 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_ar9580_1p0), 3713 5); 3714 } else if (AR_SREV_WASP(ah)) { 3715 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3716 ar9340Modes_high_power_tx_gain_table_wasp_1p0, 3717 ARRAY_LENGTH(ar9340Modes_high_power_tx_gain_table_wasp_1p0), 3718 5); 3719 } else if (AR_SREV_APHRODITE(ah)) { 3720 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3721 ar956XModes_high_power_tx_gain_table_aphrodite_1p0, 3722 ARRAY_LENGTH(ar956XModes_high_power_tx_gain_table_aphrodite_1p0), 5); 3723 } else { 3724 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3725 ar9300Modes_high_power_tx_gain_table_osprey_2p2, 3726 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_osprey_2p2), 3727 5); 3728 } 3729 break; 3730 case 4: 3731 if (AR_SREV_WASP(ah)) { 3732 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3733 ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0, 3734 ARRAY_LENGTH(ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0), 3735 5); 3736 } else if (AR_SREV_AR9580(ah)) { 3737 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3738 ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0, 3739 ARRAY_LENGTH(ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0), 3740 5); 3741 } else { 3742 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3743 ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2, 3744 ARRAY_LENGTH(ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2), 3745 5); 3746 } 3747 break; 3748 case 5: 3749 /* HW Green TX */ 3750 if (AR_SREV_POSEIDON(ah)) { 3751 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3752 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3753 ar9485_modes_green_ob_db_tx_gain_poseidon1_1, 3754 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1) / 3755 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1[0]), 5); 3756 } else { 3757 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3758 ar9485_modes_green_ob_db_tx_gain_poseidon1_0, 3759 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0) / 3760 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0[0]), 5); 3761 } 3762 ahp->ah_hw_green_tx_enable = 1; 3763 } 3764 else if (AR_SREV_WASP(ah)) { 3765 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3766 ar9340_modes_ub124_tx_gain_table_wasp_1p0, 3767 sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0) / 3768 sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0[0]), 5); 3769 } 3770 else if (AR_SREV_AR9580(ah)) { 3771 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3772 ar9300_modes_type5_tx_gain_table_ar9580_1p0, 3773 ARRAY_LENGTH( ar9300_modes_type5_tx_gain_table_ar9580_1p0), 3774 5); 3775 } 3776 else if (AR_SREV_OSPREY_22(ah)) { 3777 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3778 ar9300_modes_number_5_tx_gain_table_osprey_2p2, 3779 ARRAY_LENGTH( ar9300_modes_number_5_tx_gain_table_osprey_2p2), 3780 5); 3781 } 3782 break; 3783 case 6: 3784 if (AR_SREV_WASP(ah)) { 3785 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3786 ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0, 3787 sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0) / 3788 sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0[0]), 5); 3789 } 3790 /* HW Green TX */ 3791 else if (AR_SREV_POSEIDON(ah)) { 3792 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3793 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3794 ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1, 3795 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1) / 3796 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1[0]), 3797 5); 3798 } 3799 ahp->ah_hw_green_tx_enable = 1; 3800 } 3801 else if (AR_SREV_AR9580(ah)) { 3802 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3803 ar9300_modes_type6_tx_gain_table_ar9580_1p0, 3804 ARRAY_LENGTH( ar9300_modes_type6_tx_gain_table_ar9580_1p0), 3805 5); 3806 } 3807 break; 3808 case 7: 3809 if (AR_SREV_WASP(ah)) { 3810 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3811 ar9340Modes_cus227_tx_gain_table_wasp_1p0, 3812 sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0) / 3813 sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0[0]), 5); 3814 } 3815 break; 3816 } 3817 } 3818 3819 #if ATH_ANT_DIV_COMB 3820 void 3821 ar9300_ant_div_comb_get_config(struct ath_hal *ah, 3822 HAL_ANT_COMB_CONFIG *div_comb_conf) 3823 { 3824 u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3825 div_comb_conf->main_lna_conf = 3826 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(reg_val); 3827 div_comb_conf->alt_lna_conf = 3828 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(reg_val); 3829 div_comb_conf->fast_div_bias = 3830 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(reg_val); 3831 if (AR_SREV_HORNET_11(ah)) { 3832 div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_1; 3833 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3834 div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_2; 3835 } else { 3836 div_comb_conf->antdiv_configgroup = DEFAULT_ANTDIV_CONFIG_GROUP; 3837 } 3838 } 3839 3840 void 3841 ar9300_ant_div_comb_set_config(struct ath_hal *ah, 3842 HAL_ANT_COMB_CONFIG *div_comb_conf) 3843 { 3844 u_int32_t reg_val; 3845 struct ath_hal_9300 *ahp = AH9300(ah); 3846 3847 /* DO NOTHING when set to fixed antenna for manufacturing purpose */ 3848 if (AR_SREV_POSEIDON(ah) && ( ahp->ah_diversity_control == HAL_ANT_FIXED_A 3849 || ahp->ah_diversity_control == HAL_ANT_FIXED_B)) { 3850 return; 3851 } 3852 reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3853 reg_val &= ~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK | 3854 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK | 3855 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK | 3856 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK | 3857 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK ); 3858 reg_val |= 3859 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE( 3860 div_comb_conf->main_gaintb); 3861 reg_val |= 3862 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE( 3863 div_comb_conf->alt_gaintb); 3864 reg_val |= 3865 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE( 3866 div_comb_conf->main_lna_conf); 3867 reg_val |= 3868 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE( 3869 div_comb_conf->alt_lna_conf); 3870 reg_val |= 3871 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE( 3872 div_comb_conf->fast_div_bias); 3873 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); 3874 3875 } 3876 #endif /* ATH_ANT_DIV_COMB */ 3877 3878 static void 3879 ar9300_init_hostif_offsets(struct ath_hal *ah) 3880 { 3881 AR_HOSTIF_REG(ah, AR_RC) = 3882 AR9300_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 3883 AR_HOSTIF_REG(ah, AR_WA) = 3884 AR9300_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 3885 AR_HOSTIF_REG(ah, AR_PM_STATE) = 3886 AR9300_HOSTIF_OFFSET(HOST_INTF_PM_STATE); 3887 AR_HOSTIF_REG(ah, AR_H_INFOL) = 3888 AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOL); 3889 AR_HOSTIF_REG(ah, AR_H_INFOH) = 3890 AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOH); 3891 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 3892 AR9300_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 3893 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 3894 AR9300_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 3895 AR_HOSTIF_REG(ah, AR_EEPROM) = 3896 AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_CTRL); 3897 AR_HOSTIF_REG(ah, AR_SREV) = 3898 AR9300_HOSTIF_OFFSET(HOST_INTF_SREV); 3899 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 3900 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 3901 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 3902 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 3903 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 3904 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 3905 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 3906 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 3907 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 3908 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 3909 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 3910 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 3911 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 3912 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 3913 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 3914 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 3915 AR_HOSTIF_REG(ah, AR_PCIE_SERDES) = 3916 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_RW); 3917 AR_HOSTIF_REG(ah, AR_PCIE_SERDES2) = 3918 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LOAD); 3919 AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 3920 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 3921 AR_HOSTIF_REG(ah, AR_GPIO_IN) = 3922 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 3923 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 3924 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 3925 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 3926 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 3927 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 3928 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 3929 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 3930 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 3931 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 3932 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 3933 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 3934 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 3935 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 3936 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 3937 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 3938 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 3939 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 3940 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 3941 AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 3942 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 3943 AR_HOSTIF_REG(ah, AR_SPARE) = 3944 AR9300_HOSTIF_OFFSET(HOST_INTF_SPARE); 3945 AR_HOSTIF_REG(ah, AR_PCIE_CORE_RESET_EN) = 3946 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_CORE_RST_EN); 3947 AR_HOSTIF_REG(ah, AR_CLKRUN) = 3948 AR9300_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 3949 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 3950 AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 3951 AR_HOSTIF_REG(ah, AR_OBS) = 3952 AR9300_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 3953 AR_HOSTIF_REG(ah, AR_RFSILENT) = 3954 AR9300_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 3955 AR_HOSTIF_REG(ah, AR_GPIO_PDPU) = 3956 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_PDPU); 3957 AR_HOSTIF_REG(ah, AR_GPIO_DS) = 3958 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_DS); 3959 AR_HOSTIF_REG(ah, AR_MISC) = 3960 AR9300_HOSTIF_OFFSET(HOST_INTF_MISC); 3961 AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 3962 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 3963 #if 0 /* Offsets are not defined in reg_map structure */ 3964 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_ACTIVE) = 3965 AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_ACTIVE); 3966 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_PRIORITY) = 3967 AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_PRIORITY); 3968 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_CNTL) = 3969 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TSF_SNAPSHOT_BT_CNTL); 3970 #endif 3971 AR_HOSTIF_REG(ah, AR_PCIE_PHY_LATENCY_NFTS_ADJ) = 3972 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ); 3973 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 3974 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 3975 AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 3976 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 3977 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 3978 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 3979 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 3980 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 3981 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 3982 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 3983 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 3984 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 3985 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 3986 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 3987 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 3988 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 3989 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 3990 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 3991 } 3992 3993 static void 3994 ar9340_init_hostif_offsets(struct ath_hal *ah) 3995 { 3996 AR_HOSTIF_REG(ah, AR_RC) = 3997 AR9340_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 3998 AR_HOSTIF_REG(ah, AR_WA) = 3999 AR9340_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 4000 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 4001 AR9340_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 4002 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 4003 AR9340_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 4004 AR_HOSTIF_REG(ah, AR_SREV) = 4005 AR9340_HOSTIF_OFFSET(HOST_INTF_SREV); 4006 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 4007 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4008 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 4009 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4010 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 4011 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 4012 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 4013 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 4014 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 4015 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 4016 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 4017 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4018 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 4019 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4020 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 4021 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 4022 AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 4023 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 4024 AR_HOSTIF_REG(ah, AR_GPIO_IN) = 4025 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 4026 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 4027 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 4028 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 4029 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 4030 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 4031 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 4032 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 4033 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 4034 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 4035 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 4036 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 4037 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 4038 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 4039 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 4040 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 4041 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 4042 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 4043 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 4044 AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 4045 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 4046 AR_HOSTIF_REG(ah, AR_CLKRUN) = 4047 AR9340_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 4048 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 4049 AR9340_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 4050 AR_HOSTIF_REG(ah, AR_OBS) = 4051 AR9340_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 4052 AR_HOSTIF_REG(ah, AR_RFSILENT) = 4053 AR9340_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 4054 AR_HOSTIF_REG(ah, AR_MISC) = 4055 AR9340_HOSTIF_OFFSET(HOST_INTF_MISC); 4056 AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 4057 AR9340_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 4058 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 4059 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 4060 AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 4061 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 4062 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 4063 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 4064 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 4065 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 4066 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 4067 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 4068 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 4069 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 4070 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 4071 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 4072 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 4073 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 4074 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 4075 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 4076 } 4077 4078 /* 4079 * Host interface register offsets are different for Osprey and Wasp 4080 * and hence store the offsets in hal structure 4081 */ 4082 static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid) 4083 { 4084 if (devid == AR9300_DEVID_AR9340) { 4085 ar9340_init_hostif_offsets(ah); 4086 } else { 4087 ar9300_init_hostif_offsets(ah); 4088 } 4089 return 0; 4090 } 4091 4092 4093 static const char* 4094 ar9300_probe(uint16_t vendorid, uint16_t devid) 4095 { 4096 if (vendorid != ATHEROS_VENDOR_ID) 4097 return AH_NULL; 4098 4099 switch (devid) { 4100 case AR9300_DEVID_AR9380_PCIE: /* PCIE (Osprey) */ 4101 return "Atheros AR938x"; 4102 case AR9300_DEVID_AR9340: /* Wasp */ 4103 return "Atheros AR934x"; 4104 case AR9300_DEVID_AR9485_PCIE: /* Poseidon */ 4105 return "Atheros AR9485"; 4106 case AR9300_DEVID_AR9580_PCIE: /* Peacock */ 4107 return "Atheros AR9580"; 4108 case AR9300_DEVID_AR946X_PCIE: /* AR9462, AR9463, AR9482 */ 4109 return "Atheros AR946x/AR948x"; 4110 case AR9300_DEVID_AR9330: /* Hornet */ 4111 return "Atheros AR933x"; 4112 case AR9300_DEVID_QCA955X: /* Scorpion */ 4113 return "Qualcomm Atheros QCA955x"; 4114 case AR9300_DEVID_QCA9565: /* Aphrodite */ 4115 return "Qualcomm Atheros AR9565"; 4116 default: 4117 return AH_NULL; 4118 } 4119 4120 return AH_NULL; 4121 } 4122 4123 AH_CHIP(AR9300, ar9300_probe, ar9300_attach); 4124 4125