1 #ifndef __AR9300_FREEBSD_INC_H__ 2 #define __AR9300_FREEBSD_INC_H__ 3 4 /* 5 * Define some configuration entries for the AR9300 HAL, so #if entries 6 * don't have to be removed. 7 */ 8 #define ATH_DRIVER_SIM 0 /* SIM */ 9 #define ATH_WOW 0 /* Wake on Wireless */ 10 #define ATH_SUPPORT_MCI 1 /* MCI btcoex */ 11 #define ATH_SUPPORT_AIC 0 /* XXX to do with btcoex? */ 12 #define AH_NEED_TX_DATA_SWAP 0 /* TX descriptor swap? */ 13 #define AH_NEED_RX_DATA_SWAP 0 /* TX descriptor swap? */ 14 #define ATH_SUPPORT_WIRESHARK 0 /* Radiotap HAL code */ 15 #define AH_SUPPORT_WRITE_EEPROM 0 /* EEPROM write support */ 16 #define ATH_SUPPORT_WAPI 0 /* China WAPI support */ 17 #define ATH_ANT_DIV_COMB 1 /* Antenna combining */ 18 #define ATH_SUPPORT_RAW_ADC_CAPTURE 0 /* Raw ADC capture support */ 19 #define ATH_TRAFFIC_FAST_RECOVER 0 /* XXX not sure yet */ 20 #define ATH_SUPPORT_SPECTRAL 0 /* Spectral scan support */ 21 #define ATH_BT_COEX 1 /* Enable BT Coex code */ 22 #define ATH_PCIE_ERROR_MONITOR 0 /* ??? */ 23 #define ATH_SUPPORT_CRDC 0 /* ??? */ 24 #define ATH_LOW_POWER_ENABLE 0 /* ??? */ 25 #define ATH_SUPPORT_VOW_DCS 0 /* Video over wireless dynamic channel select */ 26 #define REMOVE_PKT_LOG 1 27 #define ATH_VC_MODE_PROXY_STA 0 /* Azimuth + proxysta? */ 28 #define ATH_GEN_RANDOMNESS 0 29 #define __PKT_SERIOUS_ERRORS__ 0 30 #define HAL_INTR_REFCOUNT_DISABLE 1 /* XXX wha? And atomics in the HAL!? */ 31 #define UMAC_SUPPORT_SMARTANTENNA 0 /* sigh.. */ 32 #define ATH_SMARTANTENNA_DISABLE_JTAG 0 33 #define ATH_SUPPORT_WIRESHARK 0 34 #define ATH_SUPPORT_WIFIPOS 0 35 #define ATH_SUPPORT_PAPRD 1 36 #define ATH_SUPPORT_TxBF 0 37 #define AH_PRIVATE_DIAG 1 38 39 /* XXX need to reverify these; they came in with qcamain */ 40 #define ATH_SUPPORT_FAST_CC 0 41 #define ATH_SUPPORT_RADIO_RETENTION 0 42 #define ATH_SUPPORT_CAL_REUSE 0 43 44 #define ATH_WOW_OFFLOAD 0 45 46 #define HAL_NO_INTERSPERSED_READS 47 48 /* Required or things will probe/attach, but not work right */ 49 #define AH_SUPPORT_OSPREY 1 50 #define AH_SUPPORT_POSEIDON 1 51 #define AH_SUPPORT_AR9300 1 52 53 /* These are the embedded boards; we don't currently support these */ 54 #ifdef AH_SUPPORT_AR9330 55 #define AH_SUPPORT_HORNET 1 56 #endif /* AH_SUPPORT_AR9330 */ 57 #ifdef AH_SUPPORT_AR9340 58 #define AH_SUPPORT_WASP 1 59 #endif /* AH_SUPPORT_AR9340 */ 60 #ifdef AH_SUPPORT_QCA9550 61 #define AH_SUPPORT_SCORPION 1 62 #endif /* AH_SUPPORT_QCA9550 */ 63 #define FIX_NOISE_FLOOR 1 64 65 /* XXX this needs to be removed! No atomics in the HAL! */ 66 typedef int os_atomic_t; /* XXX shouldn't do atomics here! */ 67 #define OS_ATOMIC_INC(a) (*a)++ 68 #define OS_ATOMIC_DEC(a) (*a)-- 69 70 /* 71 * HAL definitions which aren't necessarily for public consumption (yet). 72 */ 73 74 enum { 75 HAL_TRUE_CHIP = 1, 76 HAL_MAC_TO_MAC_EMU, 77 HAL_MAC_BB_EMU, 78 }; 79 80 /* HAL_KEY_TYPE */ 81 enum { 82 HAL_KEY_PROXY_STA_MASK = 0x10, 83 }; 84 85 typedef enum { 86 HAL_SMPS_DEFAULT = 0, 87 HAL_SMPS_SW_CTRL_LOW_PWR, /* Software control, low power setting */ 88 HAL_SMPS_SW_CTRL_HIGH_PWR, /* Software control, high power setting */ 89 HAL_SMPS_HW_CTRL /* Hardware Control */ 90 } HAL_SMPS_MODE; 91 92 /* 93 * Green Tx, Based on different RSSI of Received Beacon thresholds, 94 * using different tx power by modified register tx power related values. 95 * The thresholds are decided by system team. 96 */ 97 #define GreenTX_thres1 56 /* in dB */ 98 #define GreenTX_thres2 36 /* in dB */ 99 100 typedef enum { 101 HAL_RSSI_TX_POWER_NONE = 0, 102 HAL_RSSI_TX_POWER_SHORT = 1, /* short range, reduce OB/DB bias current and disable PAL */ 103 HAL_RSSI_TX_POWER_MIDDLE = 2, /* middle range, reduce OB/DB bias current and PAL is enabled */ 104 HAL_RSSI_TX_POWER_LONG = 3, /* long range, orig. OB/DB bias current and PAL is enabled */ 105 } HAL_RSSI_TX_POWER; 106 107 struct dfs_pulse { 108 u_int32_t rp_numpulses ; /* Num of pulses in radar burst */ 109 u_int32_t rp_pulsedur; /* Duration of each pulse in usecs */ 110 u_int32_t rp_pulsefreq; /* Frequency of pulses in burst */ 111 u_int32_t rp_max_pulsefreq; /* Frequency of pulses in burst */ 112 u_int32_t rp_patterntype; /* fixed or variable pattern type*/ 113 u_int32_t rp_pulsevar; /* Time variation of pulse duration for 114 matched filter (single-sided) in usecs */ 115 u_int32_t rp_threshold; /* Threshold for MF output to indicate 116 radar match */ 117 u_int32_t rp_mindur; /* Min pulse duration to be considered for 118 this pulse type */ 119 u_int32_t rp_maxdur; /* Max pusle duration to be considered for 120 this pulse type */ 121 u_int32_t rp_rssithresh; /* Minimum rssi to be considered a radar pulse */ 122 u_int32_t rp_meanoffset; /* Offset for timing adjustment */ 123 int32_t rp_rssimargin; /* rssi threshold margin. In Turbo Mode HW reports rssi 3dBm */ 124 /* lower than in non TURBO mode. 125 This will be used to offset that diff.*/ 126 u_int32_t rp_ignore_pri_window; 127 u_int32_t rp_pulseid; /* Unique ID for identifying filter */ 128 }; 129 130 struct dfs_staggered_pulse { 131 u_int32_t rp_numpulses; /* Num of pulses in radar burst */ 132 u_int32_t rp_pulsedur; /* Duration of each pulse in usecs */ 133 u_int32_t rp_min_pulsefreq; /* Frequency of pulses in burst */ 134 u_int32_t rp_max_pulsefreq; /* Frequency of pulses in burst */ 135 u_int32_t rp_patterntype; /* fixed or variable pattern type*/ 136 u_int32_t rp_pulsevar; /* Time variation of pulse duration for 137 matched filter (single-sided) in usecs */ 138 u_int32_t rp_threshold; /* Thershold for MF output to indicateC 139 radar match */ 140 u_int32_t rp_mindur; /* Min pulse duration to be considered for 141 this pulse type */ 142 u_int32_t rp_maxdur; /* Max pusle duration to be considered for 143 this pulse type */ 144 u_int32_t rp_rssithresh; /* Minimum rssi to be considered a radar pulse */ 145 u_int32_t rp_meanoffset; /* Offset for timing adjustment */ 146 int32_t rp_rssimargin; /* rssi threshold margin. In Turbo Mode HW reports rssi 3dBm */ 147 /* lower than in non TURBO mode. This will be used to offset that diff.*/ 148 u_int32_t rp_pulseid; /* Unique ID for identifying filter */ 149 }; 150 151 struct dfs_bin5pulse { 152 u_int32_t b5_threshold; /* Number of bin5 pulses to indicate detection */ 153 u_int32_t b5_mindur; /* Min duration for a bin5 pulse */ 154 u_int32_t b5_maxdur; /* Max duration for a bin5 pulse */ 155 u_int32_t b5_timewindow; /* Window over which to count bin5 pulses */ 156 u_int32_t b5_rssithresh; /* Min rssi to be considered a pulse */ 157 u_int32_t b5_rssimargin; /* rssi threshold margin. In Turbo Mode HW reports rssi 3dB */ 158 }; 159 160 #if 0 161 /* SPECTRAL SCAN defines begin */ 162 typedef struct { 163 u_int16_t ss_fft_period; /* Skip interval for FFT reports */ 164 u_int16_t ss_period; /* Spectral scan period */ 165 u_int16_t ss_count; /* # of reports to return from ss_active */ 166 u_int16_t ss_short_report;/* Set to report ony 1 set of FFT results */ 167 u_int8_t radar_bin_thresh_sel; 168 u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */ 169 int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */ 170 int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */ 171 int32_t ss_nf_temp_data; /* temperature data taken during nf scan */ 172 } HAL_SPECTRAL_PARAM; 173 #define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF 174 #define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 175 #endif 176 177 /* 178 * Noise power data definitions 179 * units are: 4 x dBm - NOISE_PWR_DATA_OFFSET (e.g. -25 = (-25/4 - 90) = -96.25 dBm) 180 * range (for 6 signed bits) is (-32 to 31) + offset => -122dBm to -59dBm 181 * resolution (2 bits) is 0.25dBm 182 */ 183 #define NOISE_PWR_DATA_OFFSET -90 /* dbm - all pwr report data is represented offset by this */ 184 #define INT_2_NOISE_PWR_DBM(_p) (((_p) - NOISE_PWR_DATA_OFFSET) << 2) 185 #define NOISE_PWR_DBM_2_INT(_p) ((((_p) + 3) >> 2) + NOISE_PWR_DATA_OFFSET) 186 #define NOISE_PWR_DBM_2_DEC(_p) (((-(_p)) & 3) * 25) 187 #define N2DBM(_x,_y) ((((_x) - NOISE_PWR_DATA_OFFSET) << 2) - (_y)/25) 188 /* SPECTRAL SCAN defines end */ 189 190 typedef struct halvowstats { 191 u_int32_t tx_frame_count; 192 u_int32_t rx_frame_count; 193 u_int32_t rx_clear_count; 194 u_int32_t cycle_count; 195 u_int32_t ext_cycle_count; 196 } HAL_VOWSTATS; 197 198 #define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 199 #define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 200 #define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 /* Check Rx Diversity is allowed */ 201 #define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 /* Check Diversity is on or off */ 202 #define HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR 0x00000010 203 #define HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX 0x00000020 204 205 /* 206 * Weight table configurations. 207 */ 208 #define AR9300_BT_WGHT 0xcccc4444 209 #define AR9300_STOMP_ALL_WLAN_WGHT0 0xfffffff0 210 #define AR9300_STOMP_ALL_WLAN_WGHT1 0xfffffff0 211 #define AR9300_STOMP_LOW_WLAN_WGHT0 0x88888880 212 #define AR9300_STOMP_LOW_WLAN_WGHT1 0x88888880 213 #define AR9300_STOMP_NONE_WLAN_WGHT0 0x00000000 214 #define AR9300_STOMP_NONE_WLAN_WGHT1 0x00000000 215 #define AR9300_STOMP_ALL_FORCE_WLAN_WGHT0 0xffffffff // Stomp BT even when WLAN is idle 216 #define AR9300_STOMP_ALL_FORCE_WLAN_WGHT1 0xffffffff 217 #define AR9300_STOMP_LOW_FORCE_WLAN_WGHT0 0x88888888 // Stomp BT even when WLAN is idle 218 #define AR9300_STOMP_LOW_FORCE_WLAN_WGHT1 0x88888888 219 220 #define JUPITER_STOMP_ALL_WLAN_WGHT0 0x01017d01 221 #define JUPITER_STOMP_ALL_WLAN_WGHT1 0x41414101 222 #define JUPITER_STOMP_ALL_WLAN_WGHT2 0x41414101 223 #define JUPITER_STOMP_ALL_WLAN_WGHT3 0x41414141 224 #define JUPITER_STOMP_LOW_WLAN_WGHT0 0x01017d01 225 #define JUPITER_STOMP_LOW_WLAN_WGHT1 0x3b3b3b01 226 #define JUPITER_STOMP_LOW_WLAN_WGHT2 0x3b3b3b01 227 #define JUPITER_STOMP_LOW_WLAN_WGHT3 0x3b3b3b3b 228 #define JUPITER_STOMP_LOW_FTP_WLAN_WGHT0 0x01017d01 229 #define JUPITER_STOMP_LOW_FTP_WLAN_WGHT1 0x013b0101 230 #define JUPITER_STOMP_LOW_FTP_WLAN_WGHT2 0x3b3b0101 231 #define JUPITER_STOMP_LOW_FTP_WLAN_WGHT3 0x3b3b013b 232 #define JUPITER_STOMP_NONE_WLAN_WGHT0 0x01017d01 233 #define JUPITER_STOMP_NONE_WLAN_WGHT1 0x01010101 234 #define JUPITER_STOMP_NONE_WLAN_WGHT2 0x01010101 235 #define JUPITER_STOMP_NONE_WLAN_WGHT3 0x01010101 236 #define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT0 0x01017d7d 237 #define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT1 0x7d7d7d01 238 #define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT2 0x7d7d7d7d 239 #define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT3 0x7d7d7d7d 240 #define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT0 0x01013b3b 241 #define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT1 0x3b3b3b01 242 #define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT2 0x3b3b3b3b 243 #define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT3 0x3b3b3b3b 244 245 #define MCI_CONCUR_TX_WLAN_WGHT1_MASK 0xff000000 246 #define MCI_CONCUR_TX_WLAN_WGHT1_MASK_S 24 247 #define MCI_CONCUR_TX_WLAN_WGHT2_MASK 0x00ff0000 248 #define MCI_CONCUR_TX_WLAN_WGHT2_MASK_S 16 249 #define MCI_CONCUR_TX_WLAN_WGHT3_MASK 0x000000ff 250 #define MCI_CONCUR_TX_WLAN_WGHT3_MASK_S 0 251 #define MCI_CONCUR_TX_WLAN_WGHT3_MASK2 0x00ff0000 252 #define MCI_CONCUR_TX_WLAN_WGHT3_MASK2_S 16 253 254 #define MCI_QUERY_BT_VERSION_VERBOSE 0 255 #define MCI_LINKID_INDEX_MGMT_PENDING 1 256 257 #define HAL_MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */ 258 259 typedef enum mci_message_header { 260 MCI_LNA_CTRL = 0x10, /* len = 0 */ 261 MCI_CONT_NACK = 0x20, /* len = 0 */ 262 MCI_CONT_INFO = 0x30, /* len = 4 */ 263 MCI_CONT_RST = 0x40, /* len = 0 */ 264 MCI_SCHD_INFO = 0x50, /* len = 16 */ 265 MCI_CPU_INT = 0x60, /* len = 4 */ 266 MCI_SYS_WAKING = 0x70, /* len = 0 */ 267 MCI_GPM = 0x80, /* len = 16 */ 268 MCI_LNA_INFO = 0x90, /* len = 1 */ 269 MCI_LNA_STATE = 0x94, 270 MCI_LNA_TAKE = 0x98, 271 MCI_LNA_TRANS = 0x9c, 272 MCI_SYS_SLEEPING = 0xa0, /* len = 0 */ 273 MCI_REQ_WAKE = 0xc0, /* len = 0 */ 274 MCI_DEBUG_16 = 0xfe, /* len = 2 */ 275 MCI_REMOTE_RESET = 0xff /* len = 16 */ 276 } MCI_MESSAGE_HEADER; 277 278 /* Default remote BT device MCI COEX version */ 279 #define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT 3 280 #define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0 281 /* Local WLAN MCI COEX version */ 282 #define MCI_GPM_COEX_MAJOR_VERSION_WLAN 3 283 #define MCI_GPM_COEX_MINOR_VERSION_WLAN 0 284 285 typedef enum mci_gpm_subtype { 286 MCI_GPM_BT_CAL_REQ = 0, 287 MCI_GPM_BT_CAL_GRANT = 1, 288 MCI_GPM_BT_CAL_DONE = 2, 289 MCI_GPM_WLAN_CAL_REQ = 3, 290 MCI_GPM_WLAN_CAL_GRANT = 4, 291 MCI_GPM_WLAN_CAL_DONE = 5, 292 MCI_GPM_COEX_AGENT = 0x0C, 293 MCI_GPM_RSVD_PATTERN = 0xFE, 294 MCI_GPM_RSVD_PATTERN32 = 0xFEFEFEFE, 295 MCI_GPM_BT_DEBUG = 0xFF 296 } MCI_GPM_SUBTYPE_T; 297 298 typedef enum mci_gpm_coex_opcode { 299 MCI_GPM_COEX_VERSION_QUERY = 0, 300 MCI_GPM_COEX_VERSION_RESPONSE = 1, 301 MCI_GPM_COEX_STATUS_QUERY = 2, 302 MCI_GPM_COEX_HALT_BT_GPM = 3, 303 MCI_GPM_COEX_WLAN_CHANNELS = 4, 304 MCI_GPM_COEX_BT_PROFILE_INFO = 5, 305 MCI_GPM_COEX_BT_STATUS_UPDATE = 6, 306 MCI_GPM_COEX_BT_UPDATE_FLAGS = 7 307 } MCI_GPM_COEX_OPCODE_T; 308 309 typedef enum mci_gpm_coex_query_type { 310 /* WLAN information */ 311 MCI_GPM_COEX_QUERY_WLAN_ALL_INFO = 0x01, 312 /* BT information */ 313 MCI_GPM_COEX_QUERY_BT_ALL_INFO = 0x01, 314 MCI_GPM_COEX_QUERY_BT_TOPOLOGY = 0x02, 315 MCI_GPM_COEX_QUERY_BT_DEBUG = 0x04 316 } MCI_GPM_COEX_QUERY_TYPE_T; 317 318 typedef enum mci_gpm_coex_halt_bt_gpm { 319 MCI_GPM_COEX_BT_GPM_UNHALT = 0, 320 MCI_GPM_COEX_BT_GPM_HALT = 1 321 } MCI_GPM_COEX_HALT_BT_GPM_T; 322 323 typedef enum mci_gpm_coex_profile_type { 324 MCI_GPM_COEX_PROFILE_UNKNOWN = 0, 325 MCI_GPM_COEX_PROFILE_RFCOMM = 1, 326 MCI_GPM_COEX_PROFILE_A2DP = 2, 327 MCI_GPM_COEX_PROFILE_HID = 3, 328 MCI_GPM_COEX_PROFILE_BNEP = 4, 329 MCI_GPM_COEX_PROFILE_VOICE = 5, 330 MCI_GPM_COEX_PROFILE_MAX 331 } MCI_GPM_COEX_PROFILE_TYPE_T; 332 333 typedef enum mci_gpm_coex_profile_state { 334 MCI_GPM_COEX_PROFILE_STATE_END = 0, 335 MCI_GPM_COEX_PROFILE_STATE_START = 1 336 } MCI_GPM_COEX_PROFILE_STATE_T; 337 338 typedef enum mci_gpm_coex_profile_role { 339 MCI_GPM_COEX_PROFILE_SLAVE = 0, 340 MCI_GPM_COEX_PROFILE_MASTER = 1 341 } MCI_GPM_COEX_PROFILE_ROLE_T; 342 343 typedef enum mci_gpm_coex_bt_status_type { 344 MCI_GPM_COEX_BT_NONLINK_STATUS = 0, 345 MCI_GPM_COEX_BT_LINK_STATUS = 1 346 } MCI_GPM_COEX_BT_STATUS_TYPE_T; 347 348 typedef enum mci_gpm_coex_bt_status_state { 349 MCI_GPM_COEX_BT_NORMAL_STATUS = 0, 350 MCI_GPM_COEX_BT_CRITICAL_STATUS = 1 351 } MCI_GPM_COEX_BT_STATUS_STATE_T; 352 353 #define MCI_GPM_INVALID_PROFILE_HANDLE 0xff 354 355 typedef enum mci_gpm_coex_bt_updata_flags_op { 356 MCI_GPM_COEX_BT_FLAGS_READ = 0x00, 357 MCI_GPM_COEX_BT_FLAGS_SET = 0x01, 358 MCI_GPM_COEX_BT_FLAGS_CLEAR = 0x02 359 } MCI_GPM_COEX_BT_FLAGS_OP_T; 360 361 /* MCI GPM/Coex opcode/type definitions */ 362 enum { 363 MCI_GPM_COEX_W_GPM_PAYLOAD = 1, 364 MCI_GPM_COEX_B_GPM_TYPE = 4, 365 MCI_GPM_COEX_B_GPM_OPCODE = 5, 366 /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */ 367 MCI_GPM_WLAN_CAL_W_SEQUENCE = 2, 368 /* MCI_GPM_COEX_VERSION_QUERY */ 369 /* MCI_GPM_COEX_VERSION_RESPONSE */ 370 MCI_GPM_COEX_B_MAJOR_VERSION = 6, 371 MCI_GPM_COEX_B_MINOR_VERSION = 7, 372 /* MCI_GPM_COEX_STATUS_QUERY */ 373 MCI_GPM_COEX_B_BT_BITMAP = 6, 374 MCI_GPM_COEX_B_WLAN_BITMAP = 7, 375 /* MCI_GPM_COEX_HALT_BT_GPM */ 376 MCI_GPM_COEX_B_HALT_STATE = 6, 377 /* MCI_GPM_COEX_WLAN_CHANNELS */ 378 MCI_GPM_COEX_B_CHANNEL_MAP = 6, 379 /* MCI_GPM_COEX_BT_PROFILE_INFO */ 380 MCI_GPM_COEX_B_PROFILE_TYPE = 6, 381 MCI_GPM_COEX_B_PROFILE_LINKID = 7, 382 MCI_GPM_COEX_B_PROFILE_STATE = 8, 383 MCI_GPM_COEX_B_PROFILE_ROLE = 9, 384 MCI_GPM_COEX_B_PROFILE_RATE = 10, 385 MCI_GPM_COEX_B_PROFILE_VOTYPE = 11, 386 MCI_GPM_COEX_H_PROFILE_T = 12, 387 MCI_GPM_COEX_B_PROFILE_W = 14, 388 MCI_GPM_COEX_B_PROFILE_A = 15, 389 /* MCI_GPM_COEX_BT_STATUS_UPDATE */ 390 MCI_GPM_COEX_B_STATUS_TYPE = 6, 391 MCI_GPM_COEX_B_STATUS_LINKID = 7, 392 MCI_GPM_COEX_B_STATUS_STATE = 8, 393 /* MCI_GPM_COEX_BT_UPDATE_FLAGS */ 394 MCI_GPM_COEX_B_BT_FLAGS_OP = 10, 395 MCI_GPM_COEX_W_BT_FLAGS = 6 396 }; 397 398 #define MCI_GPM_RECYCLE(_p_gpm) \ 399 { \ 400 *(((u_int32_t *)(_p_gpm)) + MCI_GPM_COEX_W_GPM_PAYLOAD) = MCI_GPM_RSVD_PATTERN32; \ 401 } 402 #define MCI_GPM_TYPE(_p_gpm) \ 403 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff) 404 #define MCI_GPM_OPCODE(_p_gpm) \ 405 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff) 406 407 #define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) \ 408 { \ 409 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff; \ 410 } 411 #define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) \ 412 { \ 413 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \ 414 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff; \ 415 } 416 #define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE) 417 418 #define MCI_NUM_BT_CHANNELS 79 419 420 #define MCI_GPM_SET_CHANNEL_BIT(_p_gpm, _bt_chan) \ 421 { \ 422 if (_bt_chan < MCI_NUM_BT_CHANNELS) { \ 423 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \ 424 (_bt_chan / 8)) |= 1 << (_bt_chan & 7); \ 425 } \ 426 } 427 428 #define MCI_GPM_CLR_CHANNEL_BIT(_p_gpm, _bt_chan) \ 429 { \ 430 if (_bt_chan < MCI_NUM_BT_CHANNELS) { \ 431 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \ 432 (_bt_chan / 8)) &= ~(1 << (_bt_chan & 7)); \ 433 } \ 434 } 435 436 #define HAL_MCI_INTERRUPT_SW_MSG_DONE 0x00000001 437 #define HAL_MCI_INTERRUPT_CPU_INT_MSG 0x00000002 438 #define HAL_MCI_INTERRUPT_RX_CHKSUM_FAIL 0x00000004 439 #define HAL_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008 440 #define HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010 441 #define HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020 442 #define HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080 443 #define HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100 444 #define HAL_MCI_INTERRUPT_RX_MSG 0x00000200 445 #define HAL_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400 446 #define HAL_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000 447 #define HAL_MCI_INTERRUPT_MSG_FAIL_MASK ( HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ 448 HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ 449 HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ 450 HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL ) 451 452 #define HAL_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 453 #define HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 454 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 455 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 456 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 457 #define HAL_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 458 #define HAL_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 459 #define HAL_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 460 #define HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 461 #define HAL_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 462 #define HAL_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 463 #define HAL_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 464 #define HAL_MCI_INTERRUPT_RX_MSG_MONITOR (HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ 465 HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ 466 HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ 467 HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ 468 HAL_MCI_INTERRUPT_RX_MSG_CONT_RST) 469 470 typedef enum mci_bt_state { 471 MCI_BT_SLEEP, 472 MCI_BT_AWAKE, 473 MCI_BT_CAL_START, 474 MCI_BT_CAL 475 } MCI_BT_STATE_T; 476 477 /* Type of state query */ 478 typedef enum mci_state_type { 479 HAL_MCI_STATE_ENABLE, 480 HAL_MCI_STATE_INIT_GPM_OFFSET, 481 HAL_MCI_STATE_NEXT_GPM_OFFSET, 482 HAL_MCI_STATE_LAST_GPM_OFFSET, 483 HAL_MCI_STATE_BT, 484 HAL_MCI_STATE_SET_BT_SLEEP, 485 HAL_MCI_STATE_SET_BT_AWAKE, 486 HAL_MCI_STATE_SET_BT_CAL_START, 487 HAL_MCI_STATE_SET_BT_CAL, 488 HAL_MCI_STATE_LAST_SCHD_MSG_OFFSET, 489 HAL_MCI_STATE_REMOTE_SLEEP, 490 HAL_MCI_STATE_CONT_RSSI_POWER, 491 HAL_MCI_STATE_CONT_PRIORITY, 492 HAL_MCI_STATE_CONT_TXRX, 493 HAL_MCI_STATE_RESET_REQ_WAKE, 494 HAL_MCI_STATE_SEND_WLAN_COEX_VERSION, 495 HAL_MCI_STATE_SET_BT_COEX_VERSION, 496 HAL_MCI_STATE_SEND_WLAN_CHANNELS, 497 HAL_MCI_STATE_SEND_VERSION_QUERY, 498 HAL_MCI_STATE_SEND_STATUS_QUERY, 499 HAL_MCI_STATE_NEED_FLUSH_BT_INFO, 500 HAL_MCI_STATE_SET_CONCUR_TX_PRI, 501 HAL_MCI_STATE_RECOVER_RX, 502 HAL_MCI_STATE_NEED_FTP_STOMP, 503 HAL_MCI_STATE_NEED_TUNING, 504 HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX, 505 HAL_MCI_STATE_DEBUG, 506 HAL_MCI_STATE_MAX 507 } HAL_MCI_STATE_TYPE; 508 509 #define HAL_MCI_STATE_DEBUG_REQ_BT_DEBUG 1 510 511 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002 512 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004 513 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008 514 #define HAL_MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010 515 #define HAL_MCI_BT_MCI_FLAGS_DEBUG 0x00000020 516 #define HAL_MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040 517 #define HAL_MCI_BT_MCI_FLAGS_CONT_MSG 0x00000080 518 #define HAL_MCI_BT_MCI_FLAGS_COEX_GPM 0x00000100 519 #define HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG 0x00000200 520 #define HAL_MCI_BT_MCI_FLAGS_MCI_MODE 0x00000400 521 #define HAL_MCI_BT_MCI_FLAGS_EGRET_MODE 0x00000800 522 #define HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE 0x00001000 523 #define HAL_MCI_BT_MCI_FLAGS_OTHER 0x00010000 524 525 #define HAL_MCI_DEFAULT_BT_MCI_FLAGS 0x00011dde 526 /* 527 HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR = 1 528 HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR = 1 529 HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD = 1 530 HAL_MCI_BT_MCI_FLAGS_LNA_CTRL = 1 531 HAL_MCI_BT_MCI_FLAGS_DEBUG = 0 532 HAL_MCI_BT_MCI_FLAGS_SCHED_MSG = 1 533 HAL_MCI_BT_MCI_FLAGS_CONT_MSG = 1 534 HAL_MCI_BT_MCI_FLAGS_COEX_GPM = 1 535 HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG = 0 536 HAL_MCI_BT_MCI_FLAGS_MCI_MODE = 1 537 HAL_MCI_BT_MCI_FLAGS_EGRET_MODE = 1 538 HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE = 1 539 HAL_MCI_BT_MCI_FLAGS_OTHER = 1 540 */ 541 542 #define HAL_MCI_TOGGLE_BT_MCI_FLAGS \ 543 ( HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR | \ 544 HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR | \ 545 HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD | \ 546 HAL_MCI_BT_MCI_FLAGS_MCI_MODE ) 547 548 #define HAL_MCI_2G_FLAGS_CLEAR_MASK 0x00000000 549 #define HAL_MCI_2G_FLAGS_SET_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS 550 #define HAL_MCI_2G_FLAGS HAL_MCI_DEFAULT_BT_MCI_FLAGS 551 552 #define HAL_MCI_5G_FLAGS_CLEAR_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS 553 #define HAL_MCI_5G_FLAGS_SET_MASK 0x00000000 554 #define HAL_MCI_5G_FLAGS (HAL_MCI_DEFAULT_BT_MCI_FLAGS & \ 555 ~HAL_MCI_TOGGLE_BT_MCI_FLAGS) 556 557 #define HAL_MCI_GPM_NOMORE 0 558 #define HAL_MCI_GPM_MORE 1 559 #define HAL_MCI_GPM_INVALID 0xffffffff 560 561 #define ATH_AIC_MAX_BT_CHANNEL 79 562 563 /* 564 * Default value for Jupiter is 0x00002201 565 * Default value for Aphrodite is 0x00002282 566 */ 567 #define ATH_MCI_CONFIG_CONCUR_TX 0x00000003 568 #define ATH_MCI_CONFIG_MCI_OBS_MCI 0x00000004 569 #define ATH_MCI_CONFIG_MCI_OBS_TXRX 0x00000008 570 #define ATH_MCI_CONFIG_MCI_OBS_BT 0x00000010 571 #define ATH_MCI_CONFIG_DISABLE_MCI_CAL 0x00000020 572 #define ATH_MCI_CONFIG_DISABLE_OSLA 0x00000040 573 #define ATH_MCI_CONFIG_DISABLE_FTP_STOMP 0x00000080 574 #define ATH_MCI_CONFIG_AGGR_THRESH 0x00000700 575 #define ATH_MCI_CONFIG_AGGR_THRESH_S 8 576 #define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH 0x00000800 577 #define ATH_MCI_CONFIG_CLK_DIV 0x00003000 578 #define ATH_MCI_CONFIG_CLK_DIV_S 12 579 #define ATH_MCI_CONFIG_DISABLE_TUNING 0x00004000 580 #define ATH_MCI_CONFIG_MCI_WEIGHT_DBG 0x40000000 581 #define ATH_MCI_CONFIG_DISABLE_MCI 0x80000000 582 583 #define ATH_MCI_CONFIG_MCI_OBS_MASK ( ATH_MCI_CONFIG_MCI_OBS_MCI | \ 584 ATH_MCI_CONFIG_MCI_OBS_TXRX | \ 585 ATH_MCI_CONFIG_MCI_OBS_BT ) 586 #define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F 587 588 #define ATH_MCI_CONCUR_TX_SHARED_CHN 0x01 589 #define ATH_MCI_CONCUR_TX_UNSHARED_CHN 0x02 590 #define ATH_MCI_CONCUR_TX_DEBUG 0x03 591 592 /* 593 * The values below come from the system team test result. 594 * For Jupiter, BT tx power level is from 0(-20dBm) to 6(4dBm). 595 * Lowest WLAN tx power would be in bit[23:16] of dword 1. 596 */ 597 static const u_int32_t mci_concur_tx_max_pwr[4][8] = 598 { /* No limit */ 599 {0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 600 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f}, 601 /* 11G */ 602 {0x16161616, 0x12121516, 0x12121212, 0x12121212, 603 0x12121212, 0x12121212, 0x12121212, 0x7f121212}, 604 /* HT20 */ 605 {0x15151515, 0x14141515, 0x14141414, 0x14141414, 606 0x14141414, 0x14141414, 0x14141414, 0x7f141414}, 607 /* HT40 */ 608 {0x10101010, 0x10101010, 0x10101010, 0x10101010, 609 0x10101010, 0x10101010, 0x10101010, 0x7f101010}}; 610 #define ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK 0x00ff0000 611 #define ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK_S 16 612 613 #endif /* __AR9300_FREEBSD_INC_H__ */ 614