1 #ifndef __AR9300_FREEBSD_INC_H__ 2 #define __AR9300_FREEBSD_INC_H__ 3 4 /* 5 * Define some configuration entries for the AR9300 HAL, so #if entries 6 * don't have to be removed. 7 */ 8 #define ATH_DRIVER_SIM 0 /* SIM */ 9 #define ATH_WOW 0 /* Wake on Wireless */ 10 #define ATH_SUPPORT_MCI 1 /* MCI btcoex */ 11 #define ATH_SUPPORT_AIC 0 /* XXX to do with btcoex? */ 12 #define AH_NEED_TX_DATA_SWAP 0 /* TX descriptor swap? */ 13 #define AH_NEED_RX_DATA_SWAP 0 /* TX descriptor swap? */ 14 #define ATH_SUPPORT_WIRESHARK 0 /* Radiotap HAL code */ 15 #define AH_SUPPORT_WRITE_EEPROM 0 /* EEPROM write support */ 16 #define ATH_SUPPORT_WAPI 0 /* China WAPI support */ 17 #define ATH_ANT_DIV_COMB 1 /* Antenna combining */ 18 #define ATH_SUPPORT_RAW_ADC_CAPTURE 0 /* Raw ADC capture support */ 19 #define ATH_TRAFFIC_FAST_RECOVER 0 /* XXX not sure yet */ 20 #define ATH_SUPPORT_SPECTRAL 1 /* Spectral scan support */ 21 #define ATH_BT_COEX 1 /* Enable BT Coex code */ 22 #define ATH_PCIE_ERROR_MONITOR 0 /* ??? */ 23 #define ATH_SUPPORT_CRDC 0 /* ??? */ 24 #define ATH_LOW_POWER_ENABLE 0 /* ??? */ 25 #define ATH_SUPPORT_VOW_DCS 0 /* Video over wireless dynamic channel select */ 26 #define REMOVE_PKT_LOG 1 27 #define ATH_VC_MODE_PROXY_STA 0 /* Azimuth + proxysta? */ 28 #define ATH_GEN_RANDOMNESS 0 29 #define __PKT_SERIOUS_ERRORS__ 0 30 #define HAL_INTR_REFCOUNT_DISABLE 1 /* XXX wha? And atomics in the HAL!? */ 31 #define UMAC_SUPPORT_SMARTANTENNA 0 /* sigh.. */ 32 #define ATH_SMARTANTENNA_DISABLE_JTAG 0 33 #define ATH_SUPPORT_WIRESHARK 0 34 #define ATH_SUPPORT_WIFIPOS 0 35 #define ATH_SUPPORT_PAPRD 1 36 #define ATH_SUPPORT_TxBF 0 37 #define AH_PRIVATE_DIAG 1 38 #define ATH_SUPPORT_KEYPLUMB_WAR 0 39 40 /* XXX need to reverify these; they came in with qcamain */ 41 #define ATH_SUPPORT_FAST_CC 0 42 #define ATH_SUPPORT_RADIO_RETENTION 0 43 #define ATH_SUPPORT_CAL_REUSE 0 44 45 #define ATH_WOW_OFFLOAD 0 46 47 #define HAL_NO_INTERSPERSED_READS 48 49 /* Required or things will probe/attach, but not work right */ 50 #define AH_SUPPORT_OSPREY 1 51 #define AH_SUPPORT_POSEIDON 1 52 #define AH_SUPPORT_AR9300 1 53 54 /* These are the embedded boards */ 55 #ifdef AH_SUPPORT_AR9330 56 #define AH_SUPPORT_HORNET 1 57 #endif /* AH_SUPPORT_AR9330 */ 58 #ifdef AH_SUPPORT_AR9340 59 #define AH_SUPPORT_WASP 1 60 #endif /* AH_SUPPORT_AR9340 */ 61 #ifdef AH_SUPPORT_QCA9550 62 #define AH_SUPPORT_SCORPION 1 63 #endif /* AH_SUPPORT_QCA9550 */ 64 #ifdef AH_SUPPORT_QCA9530 65 #define AH_SUPPORT_HONEYBEE 1 66 #endif /* AH_SUPPORT_QCA9530 */ 67 #define FIX_NOISE_FLOOR 1 68 69 /* XXX this needs to be removed! No atomics in the HAL! */ 70 typedef int os_atomic_t; /* XXX shouldn't do atomics here! */ 71 #define OS_ATOMIC_INC(a) (*a)++ 72 #define OS_ATOMIC_DEC(a) (*a)-- 73 74 /* 75 * HAL definitions which aren't necessarily for public consumption (yet). 76 */ 77 78 enum { 79 HAL_TRUE_CHIP = 1, 80 HAL_MAC_TO_MAC_EMU, 81 HAL_MAC_BB_EMU, 82 }; 83 84 /* HAL_KEY_TYPE */ 85 enum { 86 HAL_KEY_PROXY_STA_MASK = 0x10, 87 }; 88 89 typedef enum { 90 HAL_SMPS_DEFAULT = 0, 91 HAL_SMPS_SW_CTRL_LOW_PWR, /* Software control, low power setting */ 92 HAL_SMPS_SW_CTRL_HIGH_PWR, /* Software control, high power setting */ 93 HAL_SMPS_HW_CTRL /* Hardware Control */ 94 } HAL_SMPS_MODE; 95 96 /* 97 * Green Tx, Based on different RSSI of Received Beacon thresholds, 98 * using different tx power by modified register tx power related values. 99 * The thresholds are decided by system team. 100 */ 101 #define GreenTX_thres1 56 /* in dB */ 102 #define GreenTX_thres2 36 /* in dB */ 103 104 typedef enum { 105 HAL_RSSI_TX_POWER_NONE = 0, 106 HAL_RSSI_TX_POWER_SHORT = 1, /* short range, reduce OB/DB bias current and disable PAL */ 107 HAL_RSSI_TX_POWER_MIDDLE = 2, /* middle range, reduce OB/DB bias current and PAL is enabled */ 108 HAL_RSSI_TX_POWER_LONG = 3, /* long range, orig. OB/DB bias current and PAL is enabled */ 109 } HAL_RSSI_TX_POWER; 110 111 struct dfs_pulse { 112 u_int32_t rp_numpulses ; /* Num of pulses in radar burst */ 113 u_int32_t rp_pulsedur; /* Duration of each pulse in usecs */ 114 u_int32_t rp_pulsefreq; /* Frequency of pulses in burst */ 115 u_int32_t rp_max_pulsefreq; /* Frequency of pulses in burst */ 116 u_int32_t rp_patterntype; /* fixed or variable pattern type*/ 117 u_int32_t rp_pulsevar; /* Time variation of pulse duration for 118 matched filter (single-sided) in usecs */ 119 u_int32_t rp_threshold; /* Threshold for MF output to indicate 120 radar match */ 121 u_int32_t rp_mindur; /* Min pulse duration to be considered for 122 this pulse type */ 123 u_int32_t rp_maxdur; /* Max pusle duration to be considered for 124 this pulse type */ 125 u_int32_t rp_rssithresh; /* Minimum rssi to be considered a radar pulse */ 126 u_int32_t rp_meanoffset; /* Offset for timing adjustment */ 127 int32_t rp_rssimargin; /* rssi threshold margin. In Turbo Mode HW reports rssi 3dBm */ 128 /* lower than in non TURBO mode. 129 This will be used to offset that diff.*/ 130 u_int32_t rp_ignore_pri_window; 131 u_int32_t rp_pulseid; /* Unique ID for identifying filter */ 132 }; 133 134 struct dfs_staggered_pulse { 135 u_int32_t rp_numpulses; /* Num of pulses in radar burst */ 136 u_int32_t rp_pulsedur; /* Duration of each pulse in usecs */ 137 u_int32_t rp_min_pulsefreq; /* Frequency of pulses in burst */ 138 u_int32_t rp_max_pulsefreq; /* Frequency of pulses in burst */ 139 u_int32_t rp_patterntype; /* fixed or variable pattern type*/ 140 u_int32_t rp_pulsevar; /* Time variation of pulse duration for 141 matched filter (single-sided) in usecs */ 142 u_int32_t rp_threshold; /* Thershold for MF output to indicateC 143 radar match */ 144 u_int32_t rp_mindur; /* Min pulse duration to be considered for 145 this pulse type */ 146 u_int32_t rp_maxdur; /* Max pusle duration to be considered for 147 this pulse type */ 148 u_int32_t rp_rssithresh; /* Minimum rssi to be considered a radar pulse */ 149 u_int32_t rp_meanoffset; /* Offset for timing adjustment */ 150 int32_t rp_rssimargin; /* rssi threshold margin. In Turbo Mode HW reports rssi 3dBm */ 151 /* lower than in non TURBO mode. This will be used to offset that diff.*/ 152 u_int32_t rp_pulseid; /* Unique ID for identifying filter */ 153 }; 154 155 struct dfs_bin5pulse { 156 u_int32_t b5_threshold; /* Number of bin5 pulses to indicate detection */ 157 u_int32_t b5_mindur; /* Min duration for a bin5 pulse */ 158 u_int32_t b5_maxdur; /* Max duration for a bin5 pulse */ 159 u_int32_t b5_timewindow; /* Window over which to count bin5 pulses */ 160 u_int32_t b5_rssithresh; /* Min rssi to be considered a pulse */ 161 u_int32_t b5_rssimargin; /* rssi threshold margin. In Turbo Mode HW reports rssi 3dB */ 162 }; 163 164 #if 0 165 /* SPECTRAL SCAN defines begin */ 166 typedef struct { 167 u_int16_t ss_fft_period; /* Skip interval for FFT reports */ 168 u_int16_t ss_period; /* Spectral scan period */ 169 u_int16_t ss_count; /* # of reports to return from ss_active */ 170 u_int16_t ss_short_report;/* Set to report ony 1 set of FFT results */ 171 u_int8_t radar_bin_thresh_sel; 172 u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */ 173 int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */ 174 int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */ 175 int32_t ss_nf_temp_data; /* temperature data taken during nf scan */ 176 } HAL_SPECTRAL_PARAM; 177 #define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF 178 #define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 179 #endif 180 181 /* 182 * Noise power data definitions 183 * units are: 4 x dBm - NOISE_PWR_DATA_OFFSET (e.g. -25 = (-25/4 - 90) = -96.25 dBm) 184 * range (for 6 signed bits) is (-32 to 31) + offset => -122dBm to -59dBm 185 * resolution (2 bits) is 0.25dBm 186 */ 187 #define NOISE_PWR_DATA_OFFSET -90 /* dbm - all pwr report data is represented offset by this */ 188 #define INT_2_NOISE_PWR_DBM(_p) (((_p) - NOISE_PWR_DATA_OFFSET) << 2) 189 #define NOISE_PWR_DBM_2_INT(_p) ((((_p) + 3) >> 2) + NOISE_PWR_DATA_OFFSET) 190 #define NOISE_PWR_DBM_2_DEC(_p) (((-(_p)) & 3) * 25) 191 #define N2DBM(_x,_y) ((((_x) - NOISE_PWR_DATA_OFFSET) << 2) - (_y)/25) 192 /* SPECTRAL SCAN defines end */ 193 194 typedef struct halvowstats { 195 u_int32_t tx_frame_count; 196 u_int32_t rx_frame_count; 197 u_int32_t rx_clear_count; 198 u_int32_t cycle_count; 199 u_int32_t ext_cycle_count; 200 } HAL_VOWSTATS; 201 202 #define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 203 #define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 204 #define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 /* Check Rx Diversity is allowed */ 205 #define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 /* Check Diversity is on or off */ 206 #define HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR 0x00000010 207 #define HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX 0x00000020 208 209 /* 210 * Weight table configurations. 211 */ 212 #define AR9300_BT_WGHT 0xcccc4444 213 #define AR9300_STOMP_ALL_WLAN_WGHT0 0xfffffff0 214 #define AR9300_STOMP_ALL_WLAN_WGHT1 0xfffffff0 215 #define AR9300_STOMP_LOW_WLAN_WGHT0 0x88888880 216 #define AR9300_STOMP_LOW_WLAN_WGHT1 0x88888880 217 #define AR9300_STOMP_NONE_WLAN_WGHT0 0x00000000 218 #define AR9300_STOMP_NONE_WLAN_WGHT1 0x00000000 219 #define AR9300_STOMP_ALL_FORCE_WLAN_WGHT0 0xffffffff // Stomp BT even when WLAN is idle 220 #define AR9300_STOMP_ALL_FORCE_WLAN_WGHT1 0xffffffff 221 #define AR9300_STOMP_LOW_FORCE_WLAN_WGHT0 0x88888888 // Stomp BT even when WLAN is idle 222 #define AR9300_STOMP_LOW_FORCE_WLAN_WGHT1 0x88888888 223 224 #define JUPITER_STOMP_ALL_WLAN_WGHT0 0x01017d01 225 #define JUPITER_STOMP_ALL_WLAN_WGHT1 0x41414101 226 #define JUPITER_STOMP_ALL_WLAN_WGHT2 0x41414101 227 #define JUPITER_STOMP_ALL_WLAN_WGHT3 0x41414141 228 #define JUPITER_STOMP_LOW_WLAN_WGHT0 0x01017d01 229 #define JUPITER_STOMP_LOW_WLAN_WGHT1 0x3b3b3b01 230 #define JUPITER_STOMP_LOW_WLAN_WGHT2 0x3b3b3b01 231 #define JUPITER_STOMP_LOW_WLAN_WGHT3 0x3b3b3b3b 232 #define JUPITER_STOMP_LOW_FTP_WLAN_WGHT0 0x01017d01 233 #define JUPITER_STOMP_LOW_FTP_WLAN_WGHT1 0x013b0101 234 #define JUPITER_STOMP_LOW_FTP_WLAN_WGHT2 0x3b3b0101 235 #define JUPITER_STOMP_LOW_FTP_WLAN_WGHT3 0x3b3b013b 236 #define JUPITER_STOMP_NONE_WLAN_WGHT0 0x01017d01 237 #define JUPITER_STOMP_NONE_WLAN_WGHT1 0x01010101 238 #define JUPITER_STOMP_NONE_WLAN_WGHT2 0x01010101 239 #define JUPITER_STOMP_NONE_WLAN_WGHT3 0x01010101 240 #define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT0 0x01017d7d 241 #define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT1 0x7d7d7d01 242 #define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT2 0x7d7d7d7d 243 #define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT3 0x7d7d7d7d 244 #define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT0 0x01013b3b 245 #define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT1 0x3b3b3b01 246 #define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT2 0x3b3b3b3b 247 #define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT3 0x3b3b3b3b 248 249 #define MCI_CONCUR_TX_WLAN_WGHT1_MASK 0xff000000 250 #define MCI_CONCUR_TX_WLAN_WGHT1_MASK_S 24 251 #define MCI_CONCUR_TX_WLAN_WGHT2_MASK 0x00ff0000 252 #define MCI_CONCUR_TX_WLAN_WGHT2_MASK_S 16 253 #define MCI_CONCUR_TX_WLAN_WGHT3_MASK 0x000000ff 254 #define MCI_CONCUR_TX_WLAN_WGHT3_MASK_S 0 255 #define MCI_CONCUR_TX_WLAN_WGHT3_MASK2 0x00ff0000 256 #define MCI_CONCUR_TX_WLAN_WGHT3_MASK2_S 16 257 258 #define MCI_QUERY_BT_VERSION_VERBOSE 0 259 #define MCI_LINKID_INDEX_MGMT_PENDING 1 260 261 #define HAL_MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */ 262 263 typedef enum mci_message_header { 264 MCI_LNA_CTRL = 0x10, /* len = 0 */ 265 MCI_CONT_NACK = 0x20, /* len = 0 */ 266 MCI_CONT_INFO = 0x30, /* len = 4 */ 267 MCI_CONT_RST = 0x40, /* len = 0 */ 268 MCI_SCHD_INFO = 0x50, /* len = 16 */ 269 MCI_CPU_INT = 0x60, /* len = 4 */ 270 MCI_SYS_WAKING = 0x70, /* len = 0 */ 271 MCI_GPM = 0x80, /* len = 16 */ 272 MCI_LNA_INFO = 0x90, /* len = 1 */ 273 MCI_LNA_STATE = 0x94, 274 MCI_LNA_TAKE = 0x98, 275 MCI_LNA_TRANS = 0x9c, 276 MCI_SYS_SLEEPING = 0xa0, /* len = 0 */ 277 MCI_REQ_WAKE = 0xc0, /* len = 0 */ 278 MCI_DEBUG_16 = 0xfe, /* len = 2 */ 279 MCI_REMOTE_RESET = 0xff /* len = 16 */ 280 } MCI_MESSAGE_HEADER; 281 282 /* Default remote BT device MCI COEX version */ 283 #define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT 3 284 #define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0 285 /* Local WLAN MCI COEX version */ 286 #define MCI_GPM_COEX_MAJOR_VERSION_WLAN 3 287 #define MCI_GPM_COEX_MINOR_VERSION_WLAN 0 288 289 typedef enum mci_gpm_subtype { 290 MCI_GPM_BT_CAL_REQ = 0, 291 MCI_GPM_BT_CAL_GRANT = 1, 292 MCI_GPM_BT_CAL_DONE = 2, 293 MCI_GPM_WLAN_CAL_REQ = 3, 294 MCI_GPM_WLAN_CAL_GRANT = 4, 295 MCI_GPM_WLAN_CAL_DONE = 5, 296 MCI_GPM_COEX_AGENT = 0x0C, 297 MCI_GPM_RSVD_PATTERN = 0xFE, 298 MCI_GPM_RSVD_PATTERN32 = 0xFEFEFEFE, 299 MCI_GPM_BT_DEBUG = 0xFF 300 } MCI_GPM_SUBTYPE_T; 301 302 typedef enum mci_gpm_coex_opcode { 303 MCI_GPM_COEX_VERSION_QUERY = 0, 304 MCI_GPM_COEX_VERSION_RESPONSE = 1, 305 MCI_GPM_COEX_STATUS_QUERY = 2, 306 MCI_GPM_COEX_HALT_BT_GPM = 3, 307 MCI_GPM_COEX_WLAN_CHANNELS = 4, 308 MCI_GPM_COEX_BT_PROFILE_INFO = 5, 309 MCI_GPM_COEX_BT_STATUS_UPDATE = 6, 310 MCI_GPM_COEX_BT_UPDATE_FLAGS = 7 311 } MCI_GPM_COEX_OPCODE_T; 312 313 typedef enum mci_gpm_coex_query_type { 314 /* WLAN information */ 315 MCI_GPM_COEX_QUERY_WLAN_ALL_INFO = 0x01, 316 /* BT information */ 317 MCI_GPM_COEX_QUERY_BT_ALL_INFO = 0x01, 318 MCI_GPM_COEX_QUERY_BT_TOPOLOGY = 0x02, 319 MCI_GPM_COEX_QUERY_BT_DEBUG = 0x04 320 } MCI_GPM_COEX_QUERY_TYPE_T; 321 322 typedef enum mci_gpm_coex_halt_bt_gpm { 323 MCI_GPM_COEX_BT_GPM_UNHALT = 0, 324 MCI_GPM_COEX_BT_GPM_HALT = 1 325 } MCI_GPM_COEX_HALT_BT_GPM_T; 326 327 typedef enum mci_gpm_coex_profile_type { 328 MCI_GPM_COEX_PROFILE_UNKNOWN = 0, 329 MCI_GPM_COEX_PROFILE_RFCOMM = 1, 330 MCI_GPM_COEX_PROFILE_A2DP = 2, 331 MCI_GPM_COEX_PROFILE_HID = 3, 332 MCI_GPM_COEX_PROFILE_BNEP = 4, 333 MCI_GPM_COEX_PROFILE_VOICE = 5, 334 MCI_GPM_COEX_PROFILE_MAX 335 } MCI_GPM_COEX_PROFILE_TYPE_T; 336 337 typedef enum mci_gpm_coex_profile_state { 338 MCI_GPM_COEX_PROFILE_STATE_END = 0, 339 MCI_GPM_COEX_PROFILE_STATE_START = 1 340 } MCI_GPM_COEX_PROFILE_STATE_T; 341 342 typedef enum mci_gpm_coex_profile_role { 343 MCI_GPM_COEX_PROFILE_SLAVE = 0, 344 MCI_GPM_COEX_PROFILE_MASTER = 1 345 } MCI_GPM_COEX_PROFILE_ROLE_T; 346 347 typedef enum mci_gpm_coex_bt_status_type { 348 MCI_GPM_COEX_BT_NONLINK_STATUS = 0, 349 MCI_GPM_COEX_BT_LINK_STATUS = 1 350 } MCI_GPM_COEX_BT_STATUS_TYPE_T; 351 352 typedef enum mci_gpm_coex_bt_status_state { 353 MCI_GPM_COEX_BT_NORMAL_STATUS = 0, 354 MCI_GPM_COEX_BT_CRITICAL_STATUS = 1 355 } MCI_GPM_COEX_BT_STATUS_STATE_T; 356 357 #define MCI_GPM_INVALID_PROFILE_HANDLE 0xff 358 359 typedef enum mci_gpm_coex_bt_updata_flags_op { 360 MCI_GPM_COEX_BT_FLAGS_READ = 0x00, 361 MCI_GPM_COEX_BT_FLAGS_SET = 0x01, 362 MCI_GPM_COEX_BT_FLAGS_CLEAR = 0x02 363 } MCI_GPM_COEX_BT_FLAGS_OP_T; 364 365 /* MCI GPM/Coex opcode/type definitions */ 366 enum { 367 MCI_GPM_COEX_W_GPM_PAYLOAD = 1, 368 MCI_GPM_COEX_B_GPM_TYPE = 4, 369 MCI_GPM_COEX_B_GPM_OPCODE = 5, 370 /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */ 371 MCI_GPM_WLAN_CAL_W_SEQUENCE = 2, 372 /* MCI_GPM_COEX_VERSION_QUERY */ 373 /* MCI_GPM_COEX_VERSION_RESPONSE */ 374 MCI_GPM_COEX_B_MAJOR_VERSION = 6, 375 MCI_GPM_COEX_B_MINOR_VERSION = 7, 376 /* MCI_GPM_COEX_STATUS_QUERY */ 377 MCI_GPM_COEX_B_BT_BITMAP = 6, 378 MCI_GPM_COEX_B_WLAN_BITMAP = 7, 379 /* MCI_GPM_COEX_HALT_BT_GPM */ 380 MCI_GPM_COEX_B_HALT_STATE = 6, 381 /* MCI_GPM_COEX_WLAN_CHANNELS */ 382 MCI_GPM_COEX_B_CHANNEL_MAP = 6, 383 /* MCI_GPM_COEX_BT_PROFILE_INFO */ 384 MCI_GPM_COEX_B_PROFILE_TYPE = 6, 385 MCI_GPM_COEX_B_PROFILE_LINKID = 7, 386 MCI_GPM_COEX_B_PROFILE_STATE = 8, 387 MCI_GPM_COEX_B_PROFILE_ROLE = 9, 388 MCI_GPM_COEX_B_PROFILE_RATE = 10, 389 MCI_GPM_COEX_B_PROFILE_VOTYPE = 11, 390 MCI_GPM_COEX_H_PROFILE_T = 12, 391 MCI_GPM_COEX_B_PROFILE_W = 14, 392 MCI_GPM_COEX_B_PROFILE_A = 15, 393 /* MCI_GPM_COEX_BT_STATUS_UPDATE */ 394 MCI_GPM_COEX_B_STATUS_TYPE = 6, 395 MCI_GPM_COEX_B_STATUS_LINKID = 7, 396 MCI_GPM_COEX_B_STATUS_STATE = 8, 397 /* MCI_GPM_COEX_BT_UPDATE_FLAGS */ 398 MCI_GPM_COEX_B_BT_FLAGS_OP = 10, 399 MCI_GPM_COEX_W_BT_FLAGS = 6 400 }; 401 402 #define MCI_GPM_RECYCLE(_p_gpm) \ 403 { \ 404 *(((u_int32_t *)(_p_gpm)) + MCI_GPM_COEX_W_GPM_PAYLOAD) = MCI_GPM_RSVD_PATTERN32; \ 405 } 406 #define MCI_GPM_TYPE(_p_gpm) \ 407 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff) 408 #define MCI_GPM_OPCODE(_p_gpm) \ 409 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff) 410 411 #define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) \ 412 { \ 413 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff; \ 414 } 415 #define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) \ 416 { \ 417 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \ 418 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff; \ 419 } 420 #define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE) 421 422 #define MCI_NUM_BT_CHANNELS 79 423 424 #define MCI_GPM_SET_CHANNEL_BIT(_p_gpm, _bt_chan) \ 425 { \ 426 if (_bt_chan < MCI_NUM_BT_CHANNELS) { \ 427 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \ 428 (_bt_chan / 8)) |= 1 << (_bt_chan & 7); \ 429 } \ 430 } 431 432 #define MCI_GPM_CLR_CHANNEL_BIT(_p_gpm, _bt_chan) \ 433 { \ 434 if (_bt_chan < MCI_NUM_BT_CHANNELS) { \ 435 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \ 436 (_bt_chan / 8)) &= ~(1 << (_bt_chan & 7)); \ 437 } \ 438 } 439 440 #define HAL_MCI_INTERRUPT_SW_MSG_DONE 0x00000001 441 #define HAL_MCI_INTERRUPT_CPU_INT_MSG 0x00000002 442 #define HAL_MCI_INTERRUPT_RX_CHKSUM_FAIL 0x00000004 443 #define HAL_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008 444 #define HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010 445 #define HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020 446 #define HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080 447 #define HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100 448 #define HAL_MCI_INTERRUPT_RX_MSG 0x00000200 449 #define HAL_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400 450 #define HAL_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000 451 #define HAL_MCI_INTERRUPT_MSG_FAIL_MASK ( HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ 452 HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ 453 HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ 454 HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL ) 455 456 #define HAL_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 457 #define HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 458 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 459 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 460 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 461 #define HAL_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 462 #define HAL_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 463 #define HAL_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 464 #define HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 465 #define HAL_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 466 #define HAL_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 467 #define HAL_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 468 #define HAL_MCI_INTERRUPT_RX_MSG_MONITOR (HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ 469 HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ 470 HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ 471 HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ 472 HAL_MCI_INTERRUPT_RX_MSG_CONT_RST) 473 474 typedef enum mci_bt_state { 475 MCI_BT_SLEEP, 476 MCI_BT_AWAKE, 477 MCI_BT_CAL_START, 478 MCI_BT_CAL 479 } MCI_BT_STATE_T; 480 481 /* Type of state query */ 482 typedef enum mci_state_type { 483 HAL_MCI_STATE_ENABLE, 484 HAL_MCI_STATE_INIT_GPM_OFFSET, 485 HAL_MCI_STATE_NEXT_GPM_OFFSET, 486 HAL_MCI_STATE_LAST_GPM_OFFSET, 487 HAL_MCI_STATE_BT, 488 HAL_MCI_STATE_SET_BT_SLEEP, 489 HAL_MCI_STATE_SET_BT_AWAKE, 490 HAL_MCI_STATE_SET_BT_CAL_START, 491 HAL_MCI_STATE_SET_BT_CAL, 492 HAL_MCI_STATE_LAST_SCHD_MSG_OFFSET, 493 HAL_MCI_STATE_REMOTE_SLEEP, 494 HAL_MCI_STATE_CONT_RSSI_POWER, 495 HAL_MCI_STATE_CONT_PRIORITY, 496 HAL_MCI_STATE_CONT_TXRX, 497 HAL_MCI_STATE_RESET_REQ_WAKE, 498 HAL_MCI_STATE_SEND_WLAN_COEX_VERSION, 499 HAL_MCI_STATE_SET_BT_COEX_VERSION, 500 HAL_MCI_STATE_SEND_WLAN_CHANNELS, 501 HAL_MCI_STATE_SEND_VERSION_QUERY, 502 HAL_MCI_STATE_SEND_STATUS_QUERY, 503 HAL_MCI_STATE_NEED_FLUSH_BT_INFO, 504 HAL_MCI_STATE_SET_CONCUR_TX_PRI, 505 HAL_MCI_STATE_RECOVER_RX, 506 HAL_MCI_STATE_NEED_FTP_STOMP, 507 HAL_MCI_STATE_NEED_TUNING, 508 HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX, 509 HAL_MCI_STATE_DEBUG, 510 HAL_MCI_STATE_MAX 511 } HAL_MCI_STATE_TYPE; 512 513 #define HAL_MCI_STATE_DEBUG_REQ_BT_DEBUG 1 514 515 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002 516 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004 517 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008 518 #define HAL_MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010 519 #define HAL_MCI_BT_MCI_FLAGS_DEBUG 0x00000020 520 #define HAL_MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040 521 #define HAL_MCI_BT_MCI_FLAGS_CONT_MSG 0x00000080 522 #define HAL_MCI_BT_MCI_FLAGS_COEX_GPM 0x00000100 523 #define HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG 0x00000200 524 #define HAL_MCI_BT_MCI_FLAGS_MCI_MODE 0x00000400 525 #define HAL_MCI_BT_MCI_FLAGS_EGRET_MODE 0x00000800 526 #define HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE 0x00001000 527 #define HAL_MCI_BT_MCI_FLAGS_OTHER 0x00010000 528 529 #define HAL_MCI_DEFAULT_BT_MCI_FLAGS 0x00011dde 530 /* 531 HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR = 1 532 HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR = 1 533 HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD = 1 534 HAL_MCI_BT_MCI_FLAGS_LNA_CTRL = 1 535 HAL_MCI_BT_MCI_FLAGS_DEBUG = 0 536 HAL_MCI_BT_MCI_FLAGS_SCHED_MSG = 1 537 HAL_MCI_BT_MCI_FLAGS_CONT_MSG = 1 538 HAL_MCI_BT_MCI_FLAGS_COEX_GPM = 1 539 HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG = 0 540 HAL_MCI_BT_MCI_FLAGS_MCI_MODE = 1 541 HAL_MCI_BT_MCI_FLAGS_EGRET_MODE = 1 542 HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE = 1 543 HAL_MCI_BT_MCI_FLAGS_OTHER = 1 544 */ 545 546 #define HAL_MCI_TOGGLE_BT_MCI_FLAGS \ 547 ( HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR | \ 548 HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR | \ 549 HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD | \ 550 HAL_MCI_BT_MCI_FLAGS_MCI_MODE ) 551 552 #define HAL_MCI_2G_FLAGS_CLEAR_MASK 0x00000000 553 #define HAL_MCI_2G_FLAGS_SET_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS 554 #define HAL_MCI_2G_FLAGS HAL_MCI_DEFAULT_BT_MCI_FLAGS 555 556 #define HAL_MCI_5G_FLAGS_CLEAR_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS 557 #define HAL_MCI_5G_FLAGS_SET_MASK 0x00000000 558 #define HAL_MCI_5G_FLAGS (HAL_MCI_DEFAULT_BT_MCI_FLAGS & \ 559 ~HAL_MCI_TOGGLE_BT_MCI_FLAGS) 560 561 #define HAL_MCI_GPM_NOMORE 0 562 #define HAL_MCI_GPM_MORE 1 563 #define HAL_MCI_GPM_INVALID 0xffffffff 564 565 #define ATH_AIC_MAX_BT_CHANNEL 79 566 567 /* 568 * Default value for Jupiter is 0x00002201 569 * Default value for Aphrodite is 0x00002282 570 */ 571 #define ATH_MCI_CONFIG_CONCUR_TX 0x00000003 572 #define ATH_MCI_CONFIG_MCI_OBS_MCI 0x00000004 573 #define ATH_MCI_CONFIG_MCI_OBS_TXRX 0x00000008 574 #define ATH_MCI_CONFIG_MCI_OBS_BT 0x00000010 575 #define ATH_MCI_CONFIG_DISABLE_MCI_CAL 0x00000020 576 #define ATH_MCI_CONFIG_DISABLE_OSLA 0x00000040 577 #define ATH_MCI_CONFIG_DISABLE_FTP_STOMP 0x00000080 578 #define ATH_MCI_CONFIG_AGGR_THRESH 0x00000700 579 #define ATH_MCI_CONFIG_AGGR_THRESH_S 8 580 #define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH 0x00000800 581 #define ATH_MCI_CONFIG_CLK_DIV 0x00003000 582 #define ATH_MCI_CONFIG_CLK_DIV_S 12 583 #define ATH_MCI_CONFIG_DISABLE_TUNING 0x00004000 584 #define ATH_MCI_CONFIG_MCI_WEIGHT_DBG 0x40000000 585 #define ATH_MCI_CONFIG_DISABLE_MCI 0x80000000 586 587 #define ATH_MCI_CONFIG_MCI_OBS_MASK ( ATH_MCI_CONFIG_MCI_OBS_MCI | \ 588 ATH_MCI_CONFIG_MCI_OBS_TXRX | \ 589 ATH_MCI_CONFIG_MCI_OBS_BT ) 590 #define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F 591 592 #define ATH_MCI_CONCUR_TX_SHARED_CHN 0x01 593 #define ATH_MCI_CONCUR_TX_UNSHARED_CHN 0x02 594 #define ATH_MCI_CONCUR_TX_DEBUG 0x03 595 596 /* 597 * The values below come from the system team test result. 598 * For Jupiter, BT tx power level is from 0(-20dBm) to 6(4dBm). 599 * Lowest WLAN tx power would be in bit[23:16] of dword 1. 600 */ 601 static const u_int32_t mci_concur_tx_max_pwr[4][8] = 602 { /* No limit */ 603 {0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 604 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f}, 605 /* 11G */ 606 {0x16161616, 0x12121516, 0x12121212, 0x12121212, 607 0x12121212, 0x12121212, 0x12121212, 0x7f121212}, 608 /* HT20 */ 609 {0x15151515, 0x14141515, 0x14141414, 0x14141414, 610 0x14141414, 0x14141414, 0x14141414, 0x7f141414}, 611 /* HT40 */ 612 {0x10101010, 0x10101010, 0x10101010, 0x10101010, 613 0x10101010, 0x10101010, 0x10101010, 0x7f101010}}; 614 #define ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK 0x00ff0000 615 #define ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK_S 16 616 617 #endif /* __AR9300_FREEBSD_INC_H__ */ 618