1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "opt_ah.h" 18 19 #include "ah.h" 20 #include "ah_internal.h" 21 #include "ah_devid.h" 22 #ifdef AH_DEBUG 23 #include "ah_desc.h" /* NB: for HAL_PHYERR* */ 24 #endif 25 26 #include "ar9300/ar9300.h" 27 #include "ar9300/ar9300reg.h" 28 #include "ar9300/ar9300phy.h" 29 30 #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 31 32 /* 33 * Configure GPIO Output Mux control 34 */ 35 #if UMAC_SUPPORT_SMARTANTENNA 36 static void ar9340_soc_gpio_cfg_output_mux( 37 struct ath_hal *ah, 38 u_int32_t gpio, 39 u_int32_t ah_signal_type) 40 { 41 #define ADDR_READ(addr) (*((volatile u_int32_t *)(addr))) 42 #define ADDR_WRITE(addr, b) (void)((*(volatile u_int32_t *) (addr)) = (b)) 43 #define AR9340_SOC_GPIO_FUN0 0xB804002c 44 #define AR9340_SOC_GPIO_OE 0xB8040000 45 #if ATH_SMARTANTENNA_DISABLE_JTAG 46 #define AR9340_SOC_GPIO_FUNCTION (volatile u_int32_t*) 0xB804006c 47 #define WASP_DISABLE_JTAG 0x2 48 #define MAX_JTAG_GPIO_PIN 1 49 #endif 50 u_int8_t out_func, shift; 51 u_int32_t flags; 52 volatile u_int32_t* address; 53 54 if (!ah_signal_type){ 55 return; 56 } 57 #if ATH_SMARTANTENNA_DISABLE_JTAG 58 /* 59 * To use GPIO pins 0 and 1 for controling antennas, JTAG needs to disabled. 60 */ 61 if (gpio <= MAX_JTAG_GPIO_PIN) { 62 flags = ADDR_READ(AR9340_SOC_GPIO_FUNCTION); 63 flags |= WASP_DISABLE_JTAG; 64 ADDR_WRITE(AR9340_SOC_GPIO_FUNCTION, flags); 65 } 66 #endif 67 out_func = gpio / 4; 68 shift = (gpio % 4); 69 address = (volatile u_int32_t *)(AR9340_SOC_GPIO_FUN0 + (out_func*4)); 70 71 flags = ADDR_READ(address); 72 flags |= ah_signal_type << (8*shift); 73 ADDR_WRITE(address, flags); 74 flags = ADDR_READ(AR9340_SOC_GPIO_OE); 75 flags &= ~(1 << gpio); 76 ADDR_WRITE(AR9340_SOC_GPIO_OE, flags); 77 78 } 79 #endif 80 81 static void 82 ar9300_gpio_cfg_output_mux(struct ath_hal *ah, u_int32_t gpio, u_int32_t type) 83 { 84 int addr; 85 u_int32_t gpio_shift; 86 87 /* each MUX controls 6 GPIO pins */ 88 if (gpio > 11) { 89 addr = AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3); 90 } else if (gpio > 5) { 91 addr = AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2); 92 } else { 93 addr = AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1); 94 } 95 96 /* 97 * 5 bits per GPIO pin. 98 * Bits 0..4 for 1st pin in that mux, 99 * bits 5..9 for 2nd pin, etc. 100 */ 101 gpio_shift = (gpio % 6) * 5; 102 103 OS_REG_RMW(ah, addr, (type << gpio_shift), (0x1f << gpio_shift)); 104 } 105 106 /* 107 * Configure GPIO Output lines 108 */ 109 HAL_BOOL 110 ar9300_gpio_cfg_output( 111 struct ath_hal *ah, 112 u_int32_t gpio, 113 HAL_GPIO_MUX_TYPE hal_signal_type) 114 { 115 u_int32_t ah_signal_type; 116 u_int32_t gpio_shift; 117 u_int8_t smart_ant = 0; 118 static const u_int32_t mux_signal_conversion_table[] = { 119 /* HAL_GPIO_OUTPUT_MUX_AS_OUTPUT */ 120 AR_GPIO_OUTPUT_MUX_AS_OUTPUT, 121 /* HAL_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED */ 122 AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED, 123 /* HAL_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED */ 124 AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED, 125 /* HAL_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED */ 126 AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED, 127 /* HAL_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED */ 128 AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED, 129 /* HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE */ 130 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL, 131 /* HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME */ 132 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME, 133 /* HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA */ 134 AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA, 135 /* HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK */ 136 AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK, 137 /* HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA */ 138 AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA, 139 /* HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK */ 140 AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK, 141 /* HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX */ 142 AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX, 143 /* HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX */ 144 AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX, 145 /* HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX */ 146 AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX, 147 /* HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX */ 148 AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX, 149 /* HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE */ 150 AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE, 151 /* HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA */ 152 AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA, 153 /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0 */ 154 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0, 155 /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1 */ 156 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1, 157 /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2 */ 158 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2, 159 /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_SWCOM3 */ 160 AR_GPIO_OUTPUT_MUX_AS_SWCOM3, 161 }; 162 163 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); 164 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) || 165 (gpio == AR9382_GPIO_9_INPUT_ONLY)) 166 { 167 return AH_FALSE; 168 } 169 170 /* Convert HAL signal type definitions to hardware-specific values. */ 171 if ((int) hal_signal_type < ARRAY_LENGTH(mux_signal_conversion_table)) 172 { 173 ah_signal_type = mux_signal_conversion_table[hal_signal_type]; 174 } else { 175 return AH_FALSE; 176 } 177 178 if (gpio <= AR9382_MAX_JTAG_GPIO_PIN_NUM) { 179 OS_REG_SET_BIT(ah, 180 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), AR_GPIO_JTAG_DISABLE); 181 } 182 183 #if UMAC_SUPPORT_SMARTANTENNA 184 /* Get the pin and func values for smart antenna */ 185 switch (ah_signal_type) 186 { 187 case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0: 188 gpio = ATH_GPIOPIN_ANTCHAIN0; 189 ah_signal_type = ATH_GPIOFUNC_ANTCHAIN0; 190 smart_ant = 1; 191 break; 192 case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1: 193 gpio = ATH_GPIOPIN_ANTCHAIN1; 194 ah_signal_type = ATH_GPIOFUNC_ANTCHAIN1; 195 smart_ant = 1; 196 break; 197 case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2: 198 gpio = ATH_GPIOPIN_ANTCHAIN2; 199 ah_signal_type = ATH_GPIOFUNC_ANTCHAIN2; 200 smart_ant = 1; 201 break; 202 #if ATH_SMARTANTENNA_ROUTE_SWCOM_TO_GPIO 203 case AR_GPIO_OUTPUT_MUX_AS_SWCOM3: 204 gpio = ATH_GPIOPIN_ROUTE_SWCOM3; 205 ah_signal_type = ATH_GPIOFUNC_ROUTE_SWCOM3; 206 smart_ant = 1; 207 break; 208 #endif 209 default: 210 break; 211 } 212 #endif 213 214 if (smart_ant && (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah))) 215 { 216 #if UMAC_SUPPORT_SMARTANTENNA 217 ar9340_soc_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 218 #endif 219 return AH_TRUE; 220 } else 221 { 222 /* Configure the MUX */ 223 ar9300_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 224 } 225 226 /* 2 bits per output mode */ 227 gpio_shift = 2 * gpio; 228 229 OS_REG_RMW(ah, 230 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT), 231 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 232 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 233 return AH_TRUE; 234 } 235 236 /* 237 * Configure GPIO Output lines -LED off 238 */ 239 HAL_BOOL 240 ar9300_gpio_cfg_output_led_off( 241 struct ath_hal *ah, 242 u_int32_t gpio, 243 HAL_GPIO_MUX_TYPE halSignalType) 244 { 245 u_int32_t ah_signal_type; 246 u_int32_t gpio_shift; 247 u_int8_t smart_ant = 0; 248 249 static const u_int32_t mux_signal_conversion_table[] = { 250 /* HAL_GPIO_OUTPUT_MUX_AS_OUTPUT */ 251 AR_GPIO_OUTPUT_MUX_AS_OUTPUT, 252 /* HAL_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED */ 253 AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED, 254 /* HAL_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED */ 255 AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED, 256 /* HAL_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED */ 257 AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED, 258 /* HAL_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED */ 259 AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED, 260 /* HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE */ 261 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL, 262 /* HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME */ 263 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME, 264 /* HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA */ 265 AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA, 266 /* HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK */ 267 AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK, 268 /* HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA */ 269 AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA, 270 /* HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK */ 271 AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK, 272 /* HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX */ 273 AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX, 274 /* HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX */ 275 AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX, 276 /* HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX */ 277 AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX, 278 /* HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX */ 279 AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX, 280 AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE, 281 AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA, 282 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0, 283 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1, 284 AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2 285 }; 286 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); 287 288 /* Convert HAL signal type definitions to hardware-specific values. */ 289 if ((int) halSignalType < ARRAY_LENGTH(mux_signal_conversion_table)) 290 { 291 ah_signal_type = mux_signal_conversion_table[halSignalType]; 292 } else { 293 return AH_FALSE; 294 } 295 #if UMAC_SUPPORT_SMARTANTENNA 296 /* Get the pin and func values for smart antenna */ 297 switch (halSignalType) 298 { 299 case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0: 300 gpio = ATH_GPIOPIN_ANTCHAIN0; 301 ah_signal_type = ATH_GPIOFUNC_ANTCHAIN0; 302 smart_ant = 1; 303 break; 304 case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1: 305 gpio = ATH_GPIOPIN_ANTCHAIN1; 306 ah_signal_type = ATH_GPIOFUNC_ANTCHAIN1; 307 smart_ant = 1; 308 break; 309 case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2: 310 gpio = ATH_GPIOPIN_ANTCHAIN2; 311 ah_signal_type = ATH_GPIOFUNC_ANTCHAIN2; 312 smart_ant = 1; 313 break; 314 default: 315 break; 316 } 317 #endif 318 319 if (smart_ant && AR_SREV_WASP(ah)) 320 { 321 return AH_FALSE; 322 } 323 324 // Configure the MUX 325 ar9300_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 326 327 // 2 bits per output mode 328 gpio_shift = 2*gpio; 329 330 OS_REG_RMW(ah, 331 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT), 332 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 333 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 334 335 return AH_TRUE; 336 } 337 338 /* 339 * Configure GPIO Input lines 340 */ 341 HAL_BOOL 342 ar9300_gpio_cfg_input(struct ath_hal *ah, u_int32_t gpio) 343 { 344 u_int32_t gpio_shift; 345 346 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); 347 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) || 348 (gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM)) 349 { 350 return AH_FALSE; 351 } 352 353 if (gpio <= AR9382_MAX_JTAG_GPIO_PIN_NUM) { 354 OS_REG_SET_BIT(ah, 355 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), AR_GPIO_JTAG_DISABLE); 356 } 357 /* TODO: configure input mux for AR9300 */ 358 /* If configured as input, set output to tristate */ 359 gpio_shift = 2 * gpio; 360 361 OS_REG_RMW(ah, 362 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT), 363 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 364 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 365 return AH_TRUE; 366 } 367 368 /* 369 * Once configured for I/O - set output lines 370 * output the level of GPio PIN without care work mode 371 */ 372 HAL_BOOL 373 ar9300_gpio_set(struct ath_hal *ah, u_int32_t gpio, u_int32_t val) 374 { 375 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); 376 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) || 377 (gpio == AR9382_GPIO_9_INPUT_ONLY)) 378 { 379 return AH_FALSE; 380 } 381 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT), 382 ((val & 1) << gpio), AR_GPIO_BIT(gpio)); 383 384 return AH_TRUE; 385 } 386 387 /* 388 * Once configured for I/O - get input lines 389 */ 390 u_int32_t 391 ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio) 392 { 393 u_int32_t gpio_in; 394 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); 395 if (gpio == AR9382_GPIO_PIN_8_RESERVED) 396 { 397 return 0xffffffff; 398 } 399 400 gpio_in = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN)); 401 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN), 402 (1 << gpio), AR_GPIO_BIT(gpio)); 403 return (MS(gpio_in, AR_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0; 404 } 405 406 u_int32_t 407 ar9300_gpio_get_intr(struct ath_hal *ah) 408 { 409 unsigned int mask = 0; 410 struct ath_hal_9300 *ahp = AH9300(ah); 411 412 mask = ahp->ah_gpio_cause; 413 return mask; 414 } 415 416 /* 417 * Set the GPIO Interrupt 418 * Sync and Async interrupts are both set/cleared. 419 * Async GPIO interrupts may not be raised when the chip is put to sleep. 420 */ 421 void 422 ar9300_gpio_set_intr(struct ath_hal *ah, u_int gpio, u_int32_t ilevel) 423 { 424 425 426 int i, reg_bit; 427 u_int32_t reg_val; 428 u_int32_t regs[2], shifts[2]; 429 430 #ifdef AH_ASSERT 431 u_int32_t gpio_mask; 432 u_int32_t old_field_val = 0, field_val = 0; 433 #endif 434 435 #ifdef ATH_GPIO_USE_ASYNC_CAUSE 436 regs[0] = AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE); 437 regs[1] = AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK); 438 shifts[0] = AR_INTR_ASYNC_ENABLE_GPIO_S; 439 shifts[1] = AR_INTR_ASYNC_MASK_GPIO_S; 440 #else 441 regs[0] = AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE); 442 regs[1] = AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK); 443 shifts[0] = AR_INTR_SYNC_ENABLE_GPIO_S; 444 shifts[1] = AR_INTR_SYNC_MASK_GPIO_S; 445 #endif 446 447 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); 448 449 if ((gpio == AR9382_GPIO_PIN_8_RESERVED) || 450 (gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM)) 451 { 452 return; 453 } 454 455 #ifdef AH_ASSERT 456 gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.halNumGpioPins) - 1; 457 #endif 458 if (ilevel == HAL_GPIO_INTR_DISABLE) { 459 /* clear this GPIO's bit in the interrupt registers */ 460 for (i = 0; i < ARRAY_LENGTH(regs); i++) { 461 reg_val = OS_REG_READ(ah, regs[i]); 462 reg_bit = shifts[i] + gpio; 463 reg_val &= ~(1 << reg_bit); 464 OS_REG_WRITE(ah, regs[i], reg_val); 465 466 /* check that each register has same GPIOs enabled */ 467 #ifdef AH_ASSERT 468 field_val = (reg_val >> shifts[i]) & gpio_mask; 469 HALASSERT(i == 0 || old_field_val == field_val); 470 old_field_val = field_val; 471 #endif 472 } 473 474 } else { 475 reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL)); 476 reg_bit = gpio; 477 if (ilevel == HAL_GPIO_INTR_HIGH) { 478 /* 0 == interrupt on pin high */ 479 reg_val &= ~(1 << reg_bit); 480 } else if (ilevel == HAL_GPIO_INTR_LOW) { 481 /* 1 == interrupt on pin low */ 482 reg_val |= (1 << reg_bit); 483 } 484 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), reg_val); 485 486 /* set this GPIO's bit in the interrupt registers */ 487 for (i = 0; i < ARRAY_LENGTH(regs); i++) { 488 reg_val = OS_REG_READ(ah, regs[i]); 489 reg_bit = shifts[i] + gpio; 490 reg_val |= (1 << reg_bit); 491 OS_REG_WRITE(ah, regs[i], reg_val); 492 493 /* check that each register has same GPIOs enabled */ 494 #ifdef AH_ASSERT 495 field_val = (reg_val >> shifts[i]) & gpio_mask; 496 HALASSERT(i == 0 || old_field_val == field_val); 497 old_field_val = field_val; 498 #endif 499 } 500 } 501 } 502 503 u_int32_t 504 ar9300_gpio_get_polarity(struct ath_hal *ah) 505 { 506 return OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL)); 507 508 } 509 510 void 511 ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t pol_map, 512 u_int32_t changed_mask) 513 { 514 u_int32_t gpio_mask; 515 516 gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.halNumGpioPins) - 1; 517 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), gpio_mask & pol_map); 518 519 #ifndef ATH_GPIO_USE_ASYNC_CAUSE 520 /* 521 * For SYNC_CAUSE type interrupts, we need to clear the cause register 522 * explicitly. Otherwise an interrupt with the original polarity setting 523 * will come up immediately (if there is already an interrupt source), 524 * which is not what we want usually. 525 */ 526 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR), 527 changed_mask << AR_INTR_SYNC_ENABLE_GPIO_S); 528 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR)); 529 #endif 530 } 531 532 /* 533 * get the GPIO input pin mask 534 * gpio0 - gpio13 535 * gpio8, gpio11, regard as reserved by the chip ar9382 536 */ 537 538 u_int32_t 539 ar9300_gpio_get_mask(struct ath_hal *ah) 540 { 541 u_int32_t mask = (1 << (AR9382_MAX_GPIO_INPUT_PIN_NUM + 1) ) - 1; 542 543 if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9380_PCIE) { 544 mask = (1 << AR9382_MAX_GPIO_PIN_NUM) - 1; 545 mask &= ~(1 << AR9382_GPIO_PIN_8_RESERVED); 546 } 547 return mask; 548 } 549 550 int 551 ar9300_gpio_set_mask(struct ath_hal *ah, u_int32_t mask, u_int32_t pol_map) 552 { 553 u_int32_t invalid = ~((1 << (AR9382_MAX_GPIO_INPUT_PIN_NUM + 1)) - 1); 554 555 if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9380_PCIE) { 556 invalid = ~((1 << AR9382_MAX_GPIO_PIN_NUM) - 1); 557 invalid |= 1 << AR9382_GPIO_PIN_8_RESERVED; 558 } 559 if (mask & invalid) { 560 ath_hal_printf(ah, "%s: invalid GPIO mask 0x%x\n", __func__, mask); 561 return -1; 562 } 563 AH9300(ah)->ah_gpio_mask = mask; 564 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), mask & pol_map); 565 566 return 0; 567 } 568 569 #ifdef AH_DEBUG 570 void ar9300_gpio_show(struct ath_hal *ah); 571 void ar9300_gpio_show(struct ath_hal *ah) 572 { 573 ath_hal_printf(ah, "--- 9382 GPIOs ---(ah=%p)\n", ah ); 574 ath_hal_printf(ah, 575 "AH9300(_ah)->ah_hostifregs:%p\r\n", &(AH9300(ah)->ah_hostifregs)); 576 ath_hal_printf(ah, 577 "GPIO_OUT: 0x%08X\n", 578 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT))); 579 ath_hal_printf(ah, 580 "GPIO_IN: 0x%08X\n", 581 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN))); 582 ath_hal_printf(ah, 583 "GPIO_OE: 0x%08X\n", 584 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT))); 585 ath_hal_printf(ah, 586 "GPIO_OE1_OUT: 0x%08X\n", 587 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT))); 588 ath_hal_printf(ah, 589 "GPIO_INTR_POLAR: 0x%08X\n", 590 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL))); 591 ath_hal_printf(ah, 592 "GPIO_INPUT_VALUE: 0x%08X\n", 593 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL))); 594 ath_hal_printf(ah, 595 "GPIO_INPUT_MUX1: 0x%08X\n", 596 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1))); 597 ath_hal_printf(ah, 598 "GPIO_INPUT_MUX2: 0x%08X\n", 599 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2))); 600 ath_hal_printf(ah, 601 "GPIO_OUTPUT_MUX1: 0x%08X\n", 602 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1))); 603 ath_hal_printf(ah, 604 "GPIO_OUTPUT_MUX2: 0x%08X\n", 605 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2))); 606 ath_hal_printf(ah, 607 "GPIO_OUTPUT_MUX3: 0x%08X\n", 608 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3))); 609 ath_hal_printf(ah, 610 "GPIO_INPUT_STATE: 0x%08X\n", 611 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INPUT_STATE))); 612 ath_hal_printf(ah, 613 "GPIO_PDPU: 0x%08X\n", 614 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU))); 615 ath_hal_printf(ah, 616 "GPIO_DS: 0x%08X\n", 617 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_DS))); 618 ath_hal_printf(ah, 619 "AR_INTR_ASYNC_ENABLE: 0x%08X\n", 620 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE))); 621 ath_hal_printf(ah, 622 "AR_INTR_ASYNC_MASK: 0x%08X\n", 623 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK))); 624 ath_hal_printf(ah, 625 "AR_INTR_SYNC_ENABLE: 0x%08X\n", 626 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE))); 627 ath_hal_printf(ah, 628 "AR_INTR_SYNC_MASK: 0x%08X\n", 629 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK))); 630 ath_hal_printf(ah, 631 "AR_INTR_ASYNC_CAUSE: 0x%08X\n", 632 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE))); 633 ath_hal_printf(ah, 634 "AR_INTR_SYNC_CAUSE: 0x%08X\n", 635 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE))); 636 637 } 638 #endif /*AH_DEBUG*/ 639