1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "opt_ah.h" 18 19 #include "ah.h" 20 #include "ah_desc.h" 21 #include "ah_internal.h" 22 23 #include "ar9300/ar9300desc.h" 24 #include "ar9300/ar9300.h" 25 #include "ar9300/ar9300reg.h" 26 #include "ar9300/ar9300phy.h" 27 #include "ah_devid.h" 28 29 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 30 static void ar9300_swap_tx_desc(void *ds); 31 #endif 32 33 void 34 ar9300_tx_req_intr_desc(struct ath_hal *ah, void *ds) 35 { 36 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, 37 "%s:Desc Interrupt not supported\n", __func__); 38 } 39 40 static inline u_int16_t 41 ar9300_calc_ptr_chk_sum(struct ar9300_txc *ads) 42 { 43 u_int checksum; 44 u_int16_t ptrchecksum; 45 46 /* checksum = __bswap32(ads->ds_info) + ads->ds_link */ 47 checksum = ads->ds_info + ads->ds_link 48 + ads->ds_data0 + ads->ds_ctl3 49 + ads->ds_data1 + ads->ds_ctl5 50 + ads->ds_data2 + ads->ds_ctl7 51 + ads->ds_data3 + ads->ds_ctl9; 52 53 ptrchecksum = ((checksum & 0xffff) + (checksum >> 16)) & AR_tx_ptr_chk_sum; 54 return ptrchecksum; 55 } 56 57 HAL_BOOL 58 ar9300_fill_tx_desc( 59 struct ath_hal *ah, 60 void *ds, 61 HAL_DMA_ADDR *buf_addr, 62 u_int32_t *seg_len, 63 u_int desc_id, 64 u_int qcu, 65 HAL_KEY_TYPE key_type, 66 HAL_BOOL first_seg, 67 HAL_BOOL last_seg, 68 const void *ds0) 69 { 70 struct ar9300_txc *ads = AR9300TXC(ds); 71 short desclen; 72 73 /* Fill TXC info field */ 74 desclen = (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) ? 0x18 : 0x17; 75 ads->ds_info = TXC_INFO(qcu, desclen); 76 77 /* Set the buffer addresses */ 78 ads->ds_data0 = buf_addr[0]; 79 ads->ds_data1 = buf_addr[1]; 80 ads->ds_data2 = buf_addr[2]; 81 ads->ds_data3 = buf_addr[3]; 82 83 /* Set the buffer lengths */ 84 ads->ds_ctl3 = (seg_len[0] << AR_buf_len_S) & AR_buf_len; 85 ads->ds_ctl5 = (seg_len[1] << AR_buf_len_S) & AR_buf_len; 86 ads->ds_ctl7 = (seg_len[2] << AR_buf_len_S) & AR_buf_len; 87 ads->ds_ctl9 = (seg_len[3] << AR_buf_len_S) & AR_buf_len; 88 89 /* Fill in pointer checksum and descriptor id */ 90 ads->ds_ctl10 = (desc_id << AR_tx_desc_id_S) | ar9300_calc_ptr_chk_sum(ads); 91 92 if (first_seg) { 93 /* 94 * First descriptor, don't clobber xmit control data 95 * setup by ar9300_set_11n_tx_desc. 96 * 97 * Note: AR_encr_type is already setup in the first descriptor by 98 * set_11n_tx_desc(). 99 */ 100 ads->ds_ctl12 |= (last_seg ? 0 : AR_tx_more); 101 } else if (last_seg) { /* !first_seg && last_seg */ 102 /* 103 * Last descriptor in a multi-descriptor frame, 104 * copy the multi-rate transmit parameters from 105 * the first frame for processing on completion. 106 */ 107 ads->ds_ctl11 = 0; 108 ads->ds_ctl12 = 0; 109 #ifdef AH_NEED_DESC_SWAP 110 ads->ds_ctl13 = __bswap32(AR9300TXC_CONST(ds0)->ds_ctl13); 111 ads->ds_ctl14 = __bswap32(AR9300TXC_CONST(ds0)->ds_ctl14); 112 ads->ds_ctl17 = __bswap32(SM(key_type, AR_encr_type)); 113 #else 114 ads->ds_ctl13 = AR9300TXC_CONST(ds0)->ds_ctl13; 115 ads->ds_ctl14 = AR9300TXC_CONST(ds0)->ds_ctl14; 116 ads->ds_ctl17 = SM(key_type, AR_encr_type); 117 #endif 118 } else { /* !first_seg && !last_seg */ 119 /* 120 * XXX Intermediate descriptor in a multi-descriptor frame. 121 */ 122 ads->ds_ctl11 = 0; 123 ads->ds_ctl12 = AR_tx_more; 124 ads->ds_ctl13 = 0; 125 ads->ds_ctl14 = 0; 126 ads->ds_ctl17 = SM(key_type, AR_encr_type); 127 } 128 129 /* Only relevant for Jupiter/Aphrodite */ 130 ads->ds_ctl23 = 0; 131 132 return AH_TRUE; 133 } 134 135 void 136 ar9300_set_desc_link(struct ath_hal *ah, void *ds, u_int32_t link) 137 { 138 struct ar9300_txc *ads = AR9300TXC(ds); 139 140 ads->ds_link = link; 141 142 /* TODO - checksum is calculated twice for subframes 143 * Once in filldesc and again when linked. Need to fix. 144 */ 145 /* Fill in pointer checksum. Preserve descriptor id */ 146 ads->ds_ctl10 &= ~AR_tx_ptr_chk_sum; 147 ads->ds_ctl10 |= ar9300_calc_ptr_chk_sum(ads); 148 } 149 150 void 151 ar9300_get_desc_link_ptr(struct ath_hal *ah, void *ds, u_int32_t **link) 152 { 153 struct ar9300_txc *ads = AR9300TXC(ds); 154 155 *link = &ads->ds_link; 156 } 157 158 void 159 ar9300_clear_tx_desc_status(struct ath_hal *ah, void *ds) 160 { 161 struct ar9300_txs *ads = AR9300TXS(ds); 162 ads->status1 = ads->status2 = 0; 163 ads->status3 = ads->status4 = 0; 164 ads->status5 = ads->status6 = 0; 165 ads->status7 = ads->status8 = 0; 166 } 167 168 #ifdef ATH_SWRETRY 169 void 170 ar9300_clear_dest_mask(struct ath_hal *ah, void *ds) 171 { 172 struct ar9300_txc *ads = AR9300TXC(ds); 173 ads->ds_ctl11 |= AR_clr_dest_mask; 174 } 175 #endif 176 177 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 178 /* XXX what words need swapping */ 179 /* Swap transmit descriptor */ 180 static __inline void 181 ar9300_swap_tx_desc(void *dsp) 182 { 183 struct ar9300_txs *ds = (struct ar9300_txs *)dsp; 184 185 ds->ds_info = __bswap32(ds->ds_info); 186 ds->status1 = __bswap32(ds->status1); 187 ds->status2 = __bswap32(ds->status2); 188 ds->status3 = __bswap32(ds->status3); 189 ds->status4 = __bswap32(ds->status4); 190 ds->status5 = __bswap32(ds->status5); 191 ds->status6 = __bswap32(ds->status6); 192 ds->status7 = __bswap32(ds->status7); 193 ds->status8 = __bswap32(ds->status8); 194 } 195 #endif 196 197 198 /* 199 * Extract the transmit rate code. 200 */ 201 void 202 ar9300_get_tx_rate_code(struct ath_hal *ah, void *ds, struct ath_tx_status *ts) 203 { 204 struct ar9300_txc *ads = AR9300TXC(ds); 205 206 switch (ts->ts_finaltsi) { 207 case 0: 208 ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate0); 209 break; 210 case 1: 211 ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate1); 212 break; 213 case 2: 214 ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate2); 215 break; 216 case 3: 217 ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate3); 218 break; 219 } 220 221 ar9300_set_selfgenrate_limit(ah, ts->ts_rate); 222 } 223 224 /* 225 * Get TX Status descriptor contents. 226 */ 227 void 228 ar9300_get_raw_tx_desc(struct ath_hal *ah, u_int32_t *txstatus) 229 { 230 struct ath_hal_9300 *ahp = AH9300(ah); 231 struct ar9300_txs *ads; 232 233 ads = &ahp->ts_ring[ahp->ts_tail]; 234 235 OS_MEMCPY(txstatus, ads, sizeof(struct ar9300_txs)); 236 } 237 238 /* 239 * Processing of HW TX descriptor. 240 */ 241 HAL_STATUS 242 ar9300_proc_tx_desc(struct ath_hal *ah, void *txstatus) 243 { 244 struct ath_hal_9300 *ahp = AH9300(ah); 245 struct ar9300_txs *ads; 246 struct ath_tx_status *ts = (struct ath_tx_status *)txstatus; 247 u_int32_t dsinfo; 248 249 ads = &ahp->ts_ring[ahp->ts_tail]; 250 251 if ((ads->status8 & AR_tx_done) == 0) { 252 return HAL_EINPROGRESS; 253 } 254 255 /* 256 * Sanity check 257 */ 258 259 #if 0 260 ath_hal_printf(ah, 261 "CHH: tail=%d\n", ahp->ts_tail); 262 ath_hal_printf(ah, 263 "CHH: ds_info 0x%x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 264 ads->ds_info, 265 ads->status1, 266 ads->status2, 267 ads->status3, 268 ads->status4, 269 ads->status5, 270 ads->status6, 271 ads->status7, 272 ads->status8); 273 #endif 274 275 276 /* Increment the tail to point to the next status element. */ 277 ahp->ts_tail = (ahp->ts_tail + 1) & (ahp->ts_size-1); 278 279 /* 280 ** For big endian systems, ds_info is not swapped as the other 281 ** registers are. Ensure we use the bswap32 version (which is 282 ** defined to "nothing" in little endian systems 283 */ 284 285 dsinfo = ads->ds_info; 286 287 if ((MS(dsinfo, AR_desc_id) != ATHEROS_VENDOR_ID) || 288 (MS(dsinfo, AR_tx_rx_desc) != 1)) 289 { 290 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "%s: Tx Descriptor error %x\n", 291 __func__, dsinfo); 292 HALASSERT(0); 293 /* Zero out the status for reuse */ 294 OS_MEMZERO(ads, sizeof(struct ar9300_txs)); 295 return HAL_EIO; 296 } 297 298 /* Update software copies of the HW status */ 299 ts->ts_queue_id = MS(dsinfo, AR_tx_qcu_num); 300 ts->ts_desc_id = MS(ads->status1, AR_tx_desc_id); 301 ts->ts_seqnum = MS(ads->status8, AR_seq_num); 302 ts->ts_tstamp = ads->status4; 303 ts->ts_status = 0; 304 ts->ts_flags = 0; 305 306 if (ads->status3 & AR_excessive_retries) { 307 ts->ts_status |= HAL_TXERR_XRETRY; 308 } 309 if (ads->status3 & AR_filtered) { 310 ts->ts_status |= HAL_TXERR_FILT; 311 } 312 if (ads->status3 & AR_fifounderrun) { 313 ts->ts_status |= HAL_TXERR_FIFO; 314 ar9300_update_tx_trig_level(ah, AH_TRUE); 315 } 316 if (ads->status8 & AR_tx_op_exceeded) { 317 ts->ts_status |= HAL_TXERR_XTXOP; 318 } 319 if (ads->status3 & AR_tx_timer_expired) { 320 ts->ts_status |= HAL_TXERR_TIMER_EXPIRED; 321 } 322 if (ads->status3 & AR_desc_cfg_err) { 323 ts->ts_flags |= HAL_TX_DESC_CFG_ERR; 324 } 325 if (ads->status3 & AR_tx_data_underrun) { 326 ts->ts_flags |= HAL_TX_DATA_UNDERRUN; 327 ar9300_update_tx_trig_level(ah, AH_TRUE); 328 } 329 if (ads->status3 & AR_tx_delim_underrun) { 330 ts->ts_flags |= HAL_TX_DELIM_UNDERRUN; 331 ar9300_update_tx_trig_level(ah, AH_TRUE); 332 } 333 if (ads->status2 & AR_tx_ba_status) { 334 ts->ts_flags |= HAL_TX_BA; 335 ts->ts_ba_low = ads->status5; 336 ts->ts_ba_high = ads->status6; 337 } 338 339 /* 340 * Extract the transmit rate. 341 */ 342 ts->ts_finaltsi = MS(ads->status8, AR_final_tx_idx); 343 344 ts->ts_rssi = MS(ads->status7, AR_tx_rssi_combined); 345 ts->ts_rssi_ctl[0] = MS(ads->status2, AR_tx_rssi_ant00); 346 ts->ts_rssi_ctl[1] = MS(ads->status2, AR_tx_rssi_ant01); 347 ts->ts_rssi_ctl[2] = MS(ads->status2, AR_tx_rssi_ant02); 348 ts->ts_rssi_ext[0] = MS(ads->status7, AR_tx_rssi_ant10); 349 ts->ts_rssi_ext[1] = MS(ads->status7, AR_tx_rssi_ant11); 350 ts->ts_rssi_ext[2] = MS(ads->status7, AR_tx_rssi_ant12); 351 ts->ts_shortretry = MS(ads->status3, AR_rts_fail_cnt); 352 ts->ts_longretry = MS(ads->status3, AR_data_fail_cnt); 353 ts->ts_virtcol = MS(ads->status3, AR_virt_retry_cnt); 354 ts->ts_antenna = 0; 355 356 /* extract TID from block ack */ 357 ts->ts_tid = MS(ads->status8, AR_tx_tid); 358 359 /* Zero out the status for reuse */ 360 OS_MEMZERO(ads, sizeof(struct ar9300_txs)); 361 362 return HAL_OK; 363 } 364 365 /* 366 * Calculate air time of a transmit packet 367 * if comp_wastedt is 1, calculate air time only for failed subframes 368 * this is required for VOW_DCS ( dynamic channel selection ) 369 */ 370 u_int32_t 371 ar9300_calc_tx_airtime(struct ath_hal *ah, void *ds, struct ath_tx_status *ts, 372 HAL_BOOL comp_wastedt, u_int8_t nbad, u_int8_t nframes ) 373 { 374 struct ar9300_txc *ads = AR9300TXC(ds); 375 int finalindex_tries; 376 u_int32_t airtime, lastrate_dur; 377 378 379 /* 380 * Number of attempts made on the final index 381 * Note: If no BA was recv, then the data_fail_cnt is the number of tries 382 * made on the final index. If BA was recv, then add 1 to account for the 383 * successful attempt. 384 */ 385 if ( !comp_wastedt ){ 386 finalindex_tries = ts->ts_longretry + (ts->ts_flags & HAL_TX_BA)? 1 : 0; 387 } else { 388 finalindex_tries = ts->ts_longretry ; 389 } 390 391 /* 392 * Calculate time of transmit on air for packet including retries 393 * at different rates. 394 */ 395 switch (ts->ts_finaltsi) { 396 case 0: 397 lastrate_dur = MS(ads->ds_ctl15, AR_packet_dur0); 398 airtime = (lastrate_dur * finalindex_tries); 399 break; 400 case 1: 401 lastrate_dur = MS(ads->ds_ctl15, AR_packet_dur1); 402 airtime = (lastrate_dur * finalindex_tries) + 403 (MS(ads->ds_ctl13, AR_xmit_data_tries0) * 404 MS(ads->ds_ctl15, AR_packet_dur0)); 405 break; 406 case 2: 407 lastrate_dur = MS(ads->ds_ctl16, AR_packet_dur2); 408 airtime = (lastrate_dur * finalindex_tries) + 409 (MS(ads->ds_ctl13, AR_xmit_data_tries1) * 410 MS(ads->ds_ctl15, AR_packet_dur1)) + 411 (MS(ads->ds_ctl13, AR_xmit_data_tries0) * 412 MS(ads->ds_ctl15, AR_packet_dur0)); 413 break; 414 case 3: 415 lastrate_dur = MS(ads->ds_ctl16, AR_packet_dur3); 416 airtime = (lastrate_dur * finalindex_tries) + 417 (MS(ads->ds_ctl13, AR_xmit_data_tries2) * 418 MS(ads->ds_ctl16, AR_packet_dur2)) + 419 (MS(ads->ds_ctl13, AR_xmit_data_tries1) * 420 MS(ads->ds_ctl15, AR_packet_dur1)) + 421 (MS(ads->ds_ctl13, AR_xmit_data_tries0) * 422 MS(ads->ds_ctl15, AR_packet_dur0)); 423 break; 424 default: 425 HALASSERT(0); 426 return 0; 427 } 428 429 if ( comp_wastedt && (ts->ts_flags & HAL_TX_BA)){ 430 airtime += nbad?((lastrate_dur*nbad) / nframes):0; 431 } 432 return airtime; 433 434 } 435 436 #ifdef AH_PRIVATE_DIAG 437 void 438 ar9300__cont_tx_mode(struct ath_hal *ah, void *ds, int mode) 439 { 440 #if 0 441 static int qnum = 0; 442 int i; 443 unsigned int qbits, val, val1, val2; 444 int prefetch; 445 struct ar9300_txs *ads = AR9300TXS(ds); 446 447 if (mode == 10) { 448 return; 449 } 450 451 if (mode == 7) { /* print status from the cont tx desc */ 452 if (ads) { 453 val1 = ads->ds_txstatus1; 454 val2 = ads->ds_txstatus2; 455 HALDEBUG(ah, HAL_DEBUG_TXDESC, "s0(%x) s1(%x)\n", 456 (unsigned)val1, (unsigned)val2); 457 } 458 HALDEBUG(ah, HAL_DEBUG_TXDESC, "txe(%x) txd(%x)\n", 459 OS_REG_READ(ah, AR_Q_TXE), 460 OS_REG_READ(ah, AR_Q_TXD) 461 ); 462 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 463 val = OS_REG_READ(ah, AR_QTXDP(i)); 464 val2 = OS_REG_READ(ah, AR_QSTS(i)) & AR_Q_STS_PEND_FR_CNT; 465 HALDEBUG(ah, HAL_DEBUG_TXDESC, "[%d] %x %d\n", i, val, val2); 466 } 467 return; 468 } 469 if (mode == 8) { /* set TXE for qnum */ 470 OS_REG_WRITE(ah, AR_Q_TXE, 1 << qnum); 471 return; 472 } 473 if (mode == 9) { 474 prefetch = (int)ds; 475 return; 476 } 477 478 if (mode >= 1) { /* initiate cont tx operation */ 479 /* Disable AGC to A2 */ 480 qnum = (int) ds; 481 482 OS_REG_WRITE(ah, AR_PHY_TEST, 483 (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR) ); 484 485 OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000); 486 OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe); 487 OS_REG_WRITE(ah, AR_DIAG_SW, 488 (OS_REG_READ(ah, AR_DIAG_SW) | 489 (AR_DIAG_FORCE_RX_CLEAR + AR_DIAG_IGNORE_VIRT_CS)) ); 490 491 492 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ 493 494 if (mode == 3 || mode == 4) { 495 int txcfg; 496 497 if (mode == 3) { 498 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 499 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 500 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 100); 501 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 100); 502 OS_REG_WRITE(ah, AR_TIME_OUT, 2); 503 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, 100); 504 } 505 506 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 507 /* enable prefetch on qnum */ 508 OS_REG_WRITE(ah, AR_D_FPCTL, 0x10 | qnum); 509 txcfg = 5 | (6 << AR_FTRIG_S); 510 OS_REG_WRITE(ah, AR_TXCFG, txcfg); 511 512 OS_REG_WRITE(ah, AR_QMISC(qnum), /* set QCU modes */ 513 AR_Q_MISC_DCU_EARLY_TERM_REQ 514 + AR_Q_MISC_FSP_ASAP 515 + AR_Q_MISC_CBR_INCR_DIS1 516 + AR_Q_MISC_CBR_INCR_DIS0 517 ); 518 519 /* stop tx dma all all except qnum */ 520 qbits = 0x3ff; 521 qbits &= ~(1 << qnum); 522 for (i = 0; i < 10; i++) { 523 if (i == qnum) { 524 continue; 525 } 526 OS_REG_WRITE(ah, AR_Q_TXD, 1 << i); 527 } 528 529 OS_REG_WRITE(ah, AR_Q_TXD, qbits); 530 531 /* clear and freeze MIB counters */ 532 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); 533 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); 534 535 OS_REG_WRITE(ah, AR_DMISC(qnum), 536 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 537 AR_D_MISC_ARB_LOCKOUT_CNTRL_S) 538 + (AR_D_MISC_ARB_LOCKOUT_IGNORE) 539 + (AR_D_MISC_POST_FR_BKOFF_DIS) 540 + (AR_D_MISC_VIR_COL_HANDLING_IGNORE << 541 AR_D_MISC_VIR_COL_HANDLING_S)); 542 543 for (i = 0; i < HAL_NUM_TX_QUEUES + 2; i++) { /* disconnect QCUs */ 544 if (i == qnum) { 545 continue; 546 } 547 OS_REG_WRITE(ah, AR_DQCUMASK(i), 0); 548 } 549 } 550 } 551 if (mode == 0) { 552 OS_REG_WRITE(ah, AR_PHY_TEST, 553 (OS_REG_READ(ah, AR_PHY_TEST) & ~PHY_AGC_CLR)); 554 OS_REG_WRITE(ah, AR_DIAG_SW, 555 (OS_REG_READ(ah, AR_DIAG_SW) & 556 ~(AR_DIAG_FORCE_RX_CLEAR + AR_DIAG_IGNORE_VIRT_CS))); 557 } 558 #endif 559 } 560 #endif 561 562 void 563 ar9300_set_paprd_tx_desc(struct ath_hal *ah, void *ds, int chain_num) 564 { 565 struct ar9300_txc *ads = AR9300TXC(ds); 566 567 ads->ds_ctl12 |= SM((1 << chain_num), AR_paprd_chain_mask); 568 } 569 HAL_STATUS 570 ar9300_is_tx_done(struct ath_hal *ah) 571 { 572 struct ath_hal_9300 *ahp = AH9300(ah); 573 struct ar9300_txs *ads; 574 575 ads = &ahp->ts_ring[ahp->ts_tail]; 576 577 if (ads->status8 & AR_tx_done) { 578 return HAL_OK; 579 } 580 return HAL_EINPROGRESS; 581 } 582 583 void 584 ar9300_set_11n_tx_desc( 585 struct ath_hal *ah, 586 void *ds, 587 u_int pkt_len, 588 HAL_PKT_TYPE type, 589 u_int tx_power, 590 u_int key_ix, 591 HAL_KEY_TYPE key_type, 592 u_int flags) 593 { 594 struct ar9300_txc *ads = AR9300TXC(ds); 595 struct ath_hal_9300 *ahp = AH9300(ah); 596 597 HALASSERT(is_valid_pkt_type(type)); 598 HALASSERT(is_valid_key_type(key_type)); 599 600 tx_power += ahp->ah_tx_power_index_offset; 601 if (tx_power > 63) { 602 tx_power = 63; 603 } 604 ads->ds_ctl11 = 605 (pkt_len & AR_frame_len) 606 | (flags & HAL_TXDESC_VMF ? AR_virt_more_frag : 0) 607 | SM(tx_power, AR_xmit_power0) 608 | (flags & HAL_TXDESC_VEOL ? AR_veol : 0) 609 | (flags & HAL_TXDESC_CLRDMASK ? AR_clr_dest_mask : 0) 610 | (key_ix != HAL_TXKEYIX_INVALID ? AR_dest_idx_valid : 0) 611 | (flags & HAL_TXDESC_LOWRXCHAIN ? AR_low_rx_chain : 0); 612 613 ads->ds_ctl12 = 614 (key_ix != HAL_TXKEYIX_INVALID ? SM(key_ix, AR_dest_idx) : 0) 615 | SM(type, AR_frame_type) 616 | (flags & HAL_TXDESC_NOACK ? AR_no_ack : 0) 617 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ext_only : 0) 618 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ext_and_ctl : 0); 619 620 ads->ds_ctl17 = 621 SM(key_type, AR_encr_type) | (flags & HAL_TXDESC_LDPC ? AR_ldpc : 0); 622 623 ads->ds_ctl18 = 0; 624 ads->ds_ctl19 = AR_not_sounding; /* set not sounding for normal frame */ 625 626 627 /* 628 * Clear Ness1/2/3 (Number of Extension Spatial Streams) fields. 629 * Ness0 is cleared in ctl19. See EV66059 (BB panic). 630 */ 631 ads->ds_ctl20 = 0; 632 ads->ds_ctl21 = 0; 633 ads->ds_ctl22 = 0; 634 } 635 636 void ar9300_set_rx_chainmask(struct ath_hal *ah, int rxchainmask) 637 { 638 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rxchainmask); 639 } 640 641 void ar9300_update_loc_ctl_reg(struct ath_hal *ah, int pos_bit) 642 { 643 u_int32_t reg_val; 644 reg_val = OS_REG_READ(ah, AR_LOC_CTL_REG); 645 if (pos_bit) { 646 if (!(reg_val & AR_LOC_CTL_REG_FS)) { 647 /* set fast timestamp bit in the regiter */ 648 OS_REG_WRITE(ah, AR_LOC_CTL_REG, (reg_val | AR_LOC_CTL_REG_FS)); 649 OS_REG_WRITE(ah, AR_LOC_TIMER_REG, 0); 650 } 651 } 652 else { 653 OS_REG_WRITE(ah, AR_LOC_CTL_REG, (reg_val & ~AR_LOC_CTL_REG_FS)); 654 } 655 } 656 657 #if 0 658 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) 659 static const u_int8_t ba_duration_delta[] = { 660 24, /* 0: BPSK */ 661 12, /* 1: QPSK 1/2 */ 662 12, /* 2: QPSK 3/4 */ 663 4, /* 3: 16-QAM 1/2 */ 664 4, /* 4: 16-QAM 3/4 */ 665 4, /* 5: 64-QAM 2/3 */ 666 4, /* 6: 64-QAM 3/4 */ 667 4, /* 7: 64-QAM 5/6 */ 668 24, /* 8: BPSK */ 669 12, /* 9: QPSK 1/2 */ 670 12, /* 10: QPSK 3/4 */ 671 4, /* 11: 16-QAM 1/2 */ 672 4, /* 12: 16-QAM 3/4 */ 673 4, /* 13: 64-QAM 2/3 */ 674 4, /* 14: 64-QAM 3/4 */ 675 4, /* 15: 64-QAM 5/6 */ 676 }; 677 #endif 678 679 680 static u_int8_t 681 ar9300_get_tx_mode(u_int rate_flags) 682 { 683 684 /* Check whether STBC is enabled if TxBF is not enabled */ 685 if (rate_flags & HAL_RATESERIES_STBC){ 686 return AR9300_STBC_MODE; 687 } 688 return AR9300_DEF_MODE; 689 } 690 void 691 ar9300_set_11n_rate_scenario( 692 struct ath_hal *ah, 693 void *ds, 694 void *lastds, 695 u_int dur_update_en, 696 u_int rts_cts_rate, 697 u_int rts_cts_duration, 698 HAL_11N_RATE_SERIES series[], 699 u_int nseries, 700 u_int flags, 701 u_int32_t smart_antenna) 702 { 703 struct ath_hal_private *ap = AH_PRIVATE(ah); 704 struct ar9300_txc *ads = AR9300TXC(ds); 705 struct ar9300_txc *last_ads = AR9300TXC(lastds); 706 u_int32_t ds_ctl11; 707 u_int8_t ant, cal_pkt = 0; 708 u_int mode, tx_mode = AR9300_DEF_MODE; 709 710 HALASSERT(nseries == 4); 711 (void)nseries; 712 (void)rts_cts_duration; /* use H/W to calculate RTSCTSDuration */ 713 714 ds_ctl11 = ads->ds_ctl11; 715 /* 716 * Rate control settings override 717 */ 718 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { 719 if (flags & HAL_TXDESC_RTSENA) { 720 ds_ctl11 &= ~AR_cts_enable; 721 ds_ctl11 |= AR_rts_enable; 722 } else { 723 ds_ctl11 &= ~AR_rts_enable; 724 ds_ctl11 |= AR_cts_enable; 725 } 726 } else { 727 ds_ctl11 = (ds_ctl11 & ~(AR_rts_enable | AR_cts_enable)); 728 } 729 730 mode = ath_hal_get_curmode(ah, ap->ah_curchan); 731 cal_pkt = (ads->ds_ctl12 & AR_paprd_chain_mask)?1:0; 732 733 if (ah->ah_config.ath_hal_desc_tpc) { 734 int16_t txpower; 735 736 if (!cal_pkt) { 737 /* Series 0 TxPower */ 738 tx_mode = ar9300_get_tx_mode(series[0].RateFlags); 739 txpower = ar9300_get_rate_txpower(ah, mode, series[0].RateIndex, 740 series[0].ChSel, tx_mode); 741 } else { 742 txpower = AH9300(ah)->paprd_training_power; 743 } 744 ds_ctl11 &= ~AR_xmit_power0; 745 ds_ctl11 |= 746 set_11n_tx_power(0, AH_MIN(txpower, series[0].tx_power_cap)); 747 } 748 749 ads->ds_ctl11 = ds_ctl11; 750 751 752 ads->ds_ctl13 = set_11n_tries(series, 0) 753 | set_11n_tries(series, 1) 754 | set_11n_tries(series, 2) 755 | set_11n_tries(series, 3) 756 | (dur_update_en ? AR_dur_update_ena : 0) 757 | SM(0, AR_burst_dur); 758 759 ads->ds_ctl14 = set_11n_rate(series, 0) 760 | set_11n_rate(series, 1) 761 | set_11n_rate(series, 2) 762 | set_11n_rate(series, 3); 763 764 ads->ds_ctl15 = set_11n_pkt_dur_rts_cts(series, 0) 765 | set_11n_pkt_dur_rts_cts(series, 1); 766 767 ads->ds_ctl16 = set_11n_pkt_dur_rts_cts(series, 2) 768 | set_11n_pkt_dur_rts_cts(series, 3); 769 770 ads->ds_ctl18 = set_11n_rate_flags(series, 0) 771 | set_11n_rate_flags(series, 1) 772 | set_11n_rate_flags(series, 2) 773 | set_11n_rate_flags(series, 3) 774 | SM(rts_cts_rate, AR_rts_cts_rate); 775 /* set not sounding for normal frame */ 776 ads->ds_ctl19 = AR_not_sounding; 777 778 if (ah->ah_config.ath_hal_desc_tpc) { 779 int16_t txpower; 780 781 if (!cal_pkt) { 782 /* Series 1 TxPower */ 783 tx_mode = ar9300_get_tx_mode(series[1].RateFlags); 784 txpower = ar9300_get_rate_txpower( 785 ah, mode, series[1].RateIndex, series[1].ChSel, tx_mode); 786 } else { 787 txpower = AH9300(ah)->paprd_training_power; 788 } 789 ads->ds_ctl20 |= 790 set_11n_tx_power(1, AH_MIN(txpower, series[1].tx_power_cap)); 791 792 793 /* Series 2 TxPower */ 794 if (!cal_pkt) { 795 tx_mode = ar9300_get_tx_mode(series[2].RateFlags); 796 txpower = ar9300_get_rate_txpower( 797 ah, mode, series[2].RateIndex, series[2].ChSel, tx_mode); 798 } else { 799 txpower = AH9300(ah)->paprd_training_power; 800 } 801 ads->ds_ctl21 |= 802 set_11n_tx_power(2, AH_MIN(txpower, series[2].tx_power_cap)); 803 804 /* Series 3 TxPower */ 805 if (!cal_pkt) { 806 tx_mode = ar9300_get_tx_mode(series[3].RateFlags); 807 txpower = ar9300_get_rate_txpower( 808 ah, mode, series[3].RateIndex, series[3].ChSel, tx_mode); 809 } else { 810 txpower = AH9300(ah)->paprd_training_power; 811 } 812 ads->ds_ctl22 |= 813 set_11n_tx_power(3, AH_MIN(txpower, series[3].tx_power_cap)); 814 } 815 816 if (smart_antenna != 0xffffffff) 817 { 818 /* TX DESC dword 19 to 23 are used for smart antenna configuaration 819 * ctl19 for rate series 0 ... ctrl22 for series 3 820 * bits[2:0] used to configure smart anntenna 821 */ 822 ant = (smart_antenna&0x000000ff); 823 ads->ds_ctl19 |= ant; /* rateseries 0 */ 824 825 ant = (smart_antenna&0x0000ff00) >> 8; 826 ads->ds_ctl20 |= ant; /* rateseries 1 */ 827 828 ant = (smart_antenna&0x00ff0000) >> 16; 829 ads->ds_ctl21 |= ant; /* rateseries 2 */ 830 831 ant = (smart_antenna&0xff000000) >> 24; 832 ads->ds_ctl22 |= ant; /* rateseries 3 */ 833 } 834 835 #ifdef AH_NEED_DESC_SWAP 836 last_ads->ds_ctl13 = __bswap32(ads->ds_ctl13); 837 last_ads->ds_ctl14 = __bswap32(ads->ds_ctl14); 838 #else 839 last_ads->ds_ctl13 = ads->ds_ctl13; 840 last_ads->ds_ctl14 = ads->ds_ctl14; 841 #endif 842 } 843 844 void 845 ar9300_set_11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, 846 u_int aggr_len, u_int num_delims) 847 { 848 struct ar9300_txc *ads = AR9300TXC(ds); 849 850 ads->ds_ctl12 |= (AR_is_aggr | AR_more_aggr); 851 852 ads->ds_ctl17 &= ~AR_aggr_len; 853 ads->ds_ctl17 &= ~AR_pad_delim; 854 /* XXX should use a stack variable! */ 855 ads->ds_ctl17 |= SM(aggr_len, AR_aggr_len); 856 ads->ds_ctl17 |= SM(num_delims, AR_pad_delim); 857 } 858 859 void 860 ar9300_set_11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, 861 u_int num_delims) 862 { 863 struct ar9300_txc *ads = AR9300TXC(ds); 864 unsigned int ctl17; 865 866 ads->ds_ctl12 |= (AR_is_aggr | AR_more_aggr); 867 868 /* 869 * We use a stack variable to manipulate ctl6 to reduce uncached 870 * read modify, modfiy, write. 871 */ 872 ctl17 = ads->ds_ctl17; 873 ctl17 &= ~AR_pad_delim; 874 ctl17 |= SM(num_delims, AR_pad_delim); 875 ads->ds_ctl17 = ctl17; 876 } 877 878 void 879 ar9300_set_11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds) 880 { 881 struct ar9300_txc *ads = AR9300TXC(ds); 882 883 ads->ds_ctl12 |= AR_is_aggr; 884 ads->ds_ctl12 &= ~AR_more_aggr; 885 ads->ds_ctl17 &= ~AR_pad_delim; 886 } 887 888 void 889 ar9300_clr_11n_aggr(struct ath_hal *ah, struct ath_desc *ds) 890 { 891 struct ar9300_txc *ads = AR9300TXC(ds); 892 893 ads->ds_ctl12 &= (~AR_is_aggr & ~AR_more_aggr); 894 } 895 896 void 897 ar9300_set_11n_burst_duration(struct ath_hal *ah, struct ath_desc *ds, 898 u_int burst_duration) 899 { 900 struct ar9300_txc *ads = AR9300TXC(ds); 901 902 ads->ds_ctl13 &= ~AR_burst_dur; 903 ads->ds_ctl13 |= SM(burst_duration, AR_burst_dur); 904 } 905 906 void 907 ar9300_set_11n_rifs_burst_middle(struct ath_hal *ah, void *ds) 908 { 909 struct ar9300_txc *ads = AR9300TXC(ds); 910 911 ads->ds_ctl12 |= AR_more_rifs | AR_no_ack; 912 } 913 914 void 915 ar9300_set_11n_rifs_burst_last(struct ath_hal *ah, void *ds) 916 { 917 struct ar9300_txc *ads = AR9300TXC(ds); 918 919 ads->ds_ctl12 &= (~AR_more_aggr & ~AR_more_rifs); 920 } 921 922 void 923 ar9300_clr_11n_rifs_burst(struct ath_hal *ah, void *ds) 924 { 925 struct ar9300_txc *ads = AR9300TXC(ds); 926 927 ads->ds_ctl12 &= (~AR_more_rifs & ~AR_no_ack); 928 } 929 930 void 931 ar9300_set_11n_aggr_rifs_burst(struct ath_hal *ah, void *ds) 932 { 933 struct ar9300_txc *ads = AR9300TXC(ds); 934 935 ads->ds_ctl12 |= AR_no_ack; 936 ads->ds_ctl12 &= ~AR_more_rifs; 937 } 938 939 void 940 ar9300_set_11n_virtual_more_frag(struct ath_hal *ah, struct ath_desc *ds, 941 u_int vmf) 942 { 943 struct ar9300_txc *ads = AR9300TXC(ds); 944 945 if (vmf) { 946 ads->ds_ctl11 |= AR_virt_more_frag; 947 } else { 948 ads->ds_ctl11 &= ~AR_virt_more_frag; 949 } 950 } 951 952 void 953 ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info) 954 { 955 desc_info->txctl_numwords = TXCTL_NUMWORDS(ah); 956 desc_info->txctl_offset = TXCTL_OFFSET(ah); 957 desc_info->txstatus_numwords = TXSTATUS_NUMWORDS(ah); 958 desc_info->txstatus_offset = TXSTATUS_OFFSET(ah); 959 960 desc_info->rxctl_numwords = RXCTL_NUMWORDS(ah); 961 desc_info->rxctl_offset = RXCTL_OFFSET(ah); 962 desc_info->rxstatus_numwords = RXSTATUS_NUMWORDS(ah); 963 desc_info->rxstatus_offset = RXSTATUS_OFFSET(ah); 964 } 965