1b7d5e03cSMatthew Dillon /*
2b7d5e03cSMatthew Dillon * Copyright (c) 2013 Qualcomm Atheros, Inc.
3b7d5e03cSMatthew Dillon *
4b7d5e03cSMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
5b7d5e03cSMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
6b7d5e03cSMatthew Dillon * copyright notice and this permission notice appear in all copies.
7b7d5e03cSMatthew Dillon *
8b7d5e03cSMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9b7d5e03cSMatthew Dillon * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10b7d5e03cSMatthew Dillon * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11b7d5e03cSMatthew Dillon * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12b7d5e03cSMatthew Dillon * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13b7d5e03cSMatthew Dillon * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14b7d5e03cSMatthew Dillon * PERFORMANCE OF THIS SOFTWARE.
15b7d5e03cSMatthew Dillon */
16b7d5e03cSMatthew Dillon
17b7d5e03cSMatthew Dillon #ifndef _ATH_AR9300_EEP_H_
18b7d5e03cSMatthew Dillon #define _ATH_AR9300_EEP_H_
19b7d5e03cSMatthew Dillon
20b7d5e03cSMatthew Dillon #include "opt_ah.h"
21b7d5e03cSMatthew Dillon
22b7d5e03cSMatthew Dillon #include "ah.h"
23b7d5e03cSMatthew Dillon
24b7d5e03cSMatthew Dillon #if defined(WIN32) || defined(WIN64)
25b7d5e03cSMatthew Dillon #pragma pack (push, ar9300, 1)
26b7d5e03cSMatthew Dillon #endif
27b7d5e03cSMatthew Dillon
28b7d5e03cSMatthew Dillon /* FreeBSD extras - should be in ah_eeprom.h ? */
29b7d5e03cSMatthew Dillon #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
30b7d5e03cSMatthew Dillon #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
31b7d5e03cSMatthew Dillon #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
32b7d5e03cSMatthew Dillon #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
33b7d5e03cSMatthew Dillon #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
34b7d5e03cSMatthew Dillon #define AR_EEPROM_EEPCAP_MAXQCU_S 4
35b7d5e03cSMatthew Dillon #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
36b7d5e03cSMatthew Dillon #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
37b7d5e03cSMatthew Dillon #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
38b7d5e03cSMatthew Dillon
39b7d5e03cSMatthew Dillon
40b7d5e03cSMatthew Dillon #define MSTATE 100
41b7d5e03cSMatthew Dillon #define MOUTPUT 2048
42b7d5e03cSMatthew Dillon #define MDEFAULT 15
43b7d5e03cSMatthew Dillon #define MVALUE 100
44b7d5e03cSMatthew Dillon
45b7d5e03cSMatthew Dillon enum CompressAlgorithm
46b7d5e03cSMatthew Dillon {
47b7d5e03cSMatthew Dillon _compress_none = 0,
48b7d5e03cSMatthew Dillon _compress_lzma,
49b7d5e03cSMatthew Dillon _compress_pairs,
50b7d5e03cSMatthew Dillon _compress_block,
51b7d5e03cSMatthew Dillon _compress4,
52b7d5e03cSMatthew Dillon _compress5,
53b7d5e03cSMatthew Dillon _compress6,
54b7d5e03cSMatthew Dillon _compress7,
55b7d5e03cSMatthew Dillon };
56b7d5e03cSMatthew Dillon
57b7d5e03cSMatthew Dillon
58b7d5e03cSMatthew Dillon enum
59b7d5e03cSMatthew Dillon {
60b7d5e03cSMatthew Dillon calibration_data_none = 0,
61b7d5e03cSMatthew Dillon calibration_data_dram,
62b7d5e03cSMatthew Dillon calibration_data_flash,
63b7d5e03cSMatthew Dillon calibration_data_eeprom,
64b7d5e03cSMatthew Dillon calibration_data_otp,
65b7d5e03cSMatthew Dillon #ifdef ATH_CAL_NAND_FLASH
66b7d5e03cSMatthew Dillon calibration_data_nand,
67b7d5e03cSMatthew Dillon #endif
68b7d5e03cSMatthew Dillon CalibrationDataDontLoad,
69b7d5e03cSMatthew Dillon };
70b7d5e03cSMatthew Dillon #define HOST_CALDATA_SIZE (16*1024)
71b7d5e03cSMatthew Dillon
72b7d5e03cSMatthew Dillon //
73b7d5e03cSMatthew Dillon // DO NOT CHANGE THE DEFINTIONS OF THESE SYMBOLS.
74b7d5e03cSMatthew Dillon // Add additional definitions to the end.
75b7d5e03cSMatthew Dillon // Yes, the first one is 2. Do not use 0 or 1.
76b7d5e03cSMatthew Dillon //
77b7d5e03cSMatthew Dillon enum Ar9300EepromTemplate
78b7d5e03cSMatthew Dillon {
79b7d5e03cSMatthew Dillon ar9300_eeprom_template_generic = 2,
80b7d5e03cSMatthew Dillon ar9300_eeprom_template_hb112 = 3,
81b7d5e03cSMatthew Dillon ar9300_eeprom_template_hb116 = 4,
82b7d5e03cSMatthew Dillon ar9300_eeprom_template_xb112 = 5,
83b7d5e03cSMatthew Dillon ar9300_eeprom_template_xb113 = 6,
84b7d5e03cSMatthew Dillon ar9300_eeprom_template_xb114 = 7,
85b7d5e03cSMatthew Dillon ar9300_eeprom_template_tb417 = 8,
86b7d5e03cSMatthew Dillon ar9300_eeprom_template_ap111 = 9,
87b7d5e03cSMatthew Dillon ar9300_eeprom_template_ap121 = 10,
88b7d5e03cSMatthew Dillon ar9300_eeprom_template_hornet_generic = 11,
89b7d5e03cSMatthew Dillon ar9300_eeprom_template_wasp_2 = 12,
90b7d5e03cSMatthew Dillon ar9300_eeprom_template_wasp_k31 = 13,
91b7d5e03cSMatthew Dillon ar9300_eeprom_template_osprey_k31 = 14,
92b7d5e03cSMatthew Dillon ar9300_eeprom_template_aphrodite = 15
93b7d5e03cSMatthew Dillon };
94b7d5e03cSMatthew Dillon
95b7d5e03cSMatthew Dillon #define ar9300_eeprom_template_default ar9300_eeprom_template_generic
96b7d5e03cSMatthew Dillon #define Ar9300EepromFormatDefault 2
97b7d5e03cSMatthew Dillon
98b7d5e03cSMatthew Dillon #define reference_current 0
99b7d5e03cSMatthew Dillon #define compression_header_length 4
100b7d5e03cSMatthew Dillon #define compression_checksum_length 2
101b7d5e03cSMatthew Dillon
102b7d5e03cSMatthew Dillon #define OSPREY_EEP_VER 0xD000
103b7d5e03cSMatthew Dillon #define OSPREY_EEP_VER_MINOR_MASK 0xFFF
104b7d5e03cSMatthew Dillon #define OSPREY_EEP_MINOR_VER_1 0x1
105b7d5e03cSMatthew Dillon #define OSPREY_EEP_MINOR_VER OSPREY_EEP_MINOR_VER_1
106b7d5e03cSMatthew Dillon
107b7d5e03cSMatthew Dillon // 16-bit offset location start of calibration struct
108b7d5e03cSMatthew Dillon #define OSPREY_EEP_START_LOC 256
109b7d5e03cSMatthew Dillon #define OSPREY_NUM_5G_CAL_PIERS 8
110b7d5e03cSMatthew Dillon #define OSPREY_NUM_2G_CAL_PIERS 3
111b7d5e03cSMatthew Dillon #define OSPREY_NUM_5G_20_TARGET_POWERS 8
112b7d5e03cSMatthew Dillon #define OSPREY_NUM_5G_40_TARGET_POWERS 8
113b7d5e03cSMatthew Dillon #define OSPREY_NUM_2G_CCK_TARGET_POWERS 2
114b7d5e03cSMatthew Dillon #define OSPREY_NUM_2G_20_TARGET_POWERS 3
115b7d5e03cSMatthew Dillon #define OSPREY_NUM_2G_40_TARGET_POWERS 3
116b7d5e03cSMatthew Dillon //#define OSPREY_NUM_CTLS 21
117b7d5e03cSMatthew Dillon #define OSPREY_NUM_CTLS_5G 9
118b7d5e03cSMatthew Dillon #define OSPREY_NUM_CTLS_2G 12
119b7d5e03cSMatthew Dillon #define OSPREY_CTL_MODE_M 0xF
120b7d5e03cSMatthew Dillon #define OSPREY_NUM_BAND_EDGES_5G 8
121b7d5e03cSMatthew Dillon #define OSPREY_NUM_BAND_EDGES_2G 4
122b7d5e03cSMatthew Dillon #define OSPREY_NUM_PD_GAINS 4
123b7d5e03cSMatthew Dillon #define OSPREY_PD_GAINS_IN_MASK 4
124b7d5e03cSMatthew Dillon #define OSPREY_PD_GAIN_ICEPTS 5
125b7d5e03cSMatthew Dillon #define OSPREY_EEPROM_MODAL_SPURS 5
126b7d5e03cSMatthew Dillon #define OSPREY_MAX_RATE_POWER 63
127b7d5e03cSMatthew Dillon #define OSPREY_NUM_PDADC_VALUES 128
128b7d5e03cSMatthew Dillon #define OSPREY_NUM_RATES 16
129b7d5e03cSMatthew Dillon #define OSPREY_BCHAN_UNUSED 0xFF
130b7d5e03cSMatthew Dillon #define OSPREY_MAX_PWR_RANGE_IN_HALF_DB 64
131b7d5e03cSMatthew Dillon #define OSPREY_OPFLAGS_11A 0x01
132b7d5e03cSMatthew Dillon #define OSPREY_OPFLAGS_11G 0x02
133b7d5e03cSMatthew Dillon #define OSPREY_OPFLAGS_5G_HT40 0x04
134b7d5e03cSMatthew Dillon #define OSPREY_OPFLAGS_2G_HT40 0x08
135b7d5e03cSMatthew Dillon #define OSPREY_OPFLAGS_5G_HT20 0x10
136b7d5e03cSMatthew Dillon #define OSPREY_OPFLAGS_2G_HT20 0x20
137b7d5e03cSMatthew Dillon #define OSPREY_EEPMISC_BIG_ENDIAN 0x01
138b7d5e03cSMatthew Dillon #define OSPREY_EEPMISC_WOW 0x02
139b7d5e03cSMatthew Dillon #define OSPREY_CUSTOMER_DATA_SIZE 20
140b7d5e03cSMatthew Dillon
141b7d5e03cSMatthew Dillon #define FREQ2FBIN(x,y) \
142*0641bef7SMatthew Dillon (((int)(y) == (int)HAL_FREQ_BAND_2GHZ) ? ((x) - 2300) : (((x) - 4800) / 5))
143b7d5e03cSMatthew Dillon #define FBIN2FREQ(x,y) \
144*0641bef7SMatthew Dillon (((int)(y) == (int)HAL_FREQ_BAND_2GHZ) ? (2300 + x) : (4800 + 5 * x))
145b7d5e03cSMatthew Dillon #define OSPREY_MAX_CHAINS 3
146b7d5e03cSMatthew Dillon #define OSPREY_ANT_16S 25
147b7d5e03cSMatthew Dillon #define OSPREY_FUTURE_MODAL_SZ 6
148b7d5e03cSMatthew Dillon
149b7d5e03cSMatthew Dillon #define OSPREY_NUM_ANT_CHAIN_FIELDS 7
150b7d5e03cSMatthew Dillon #define OSPREY_NUM_ANT_COMMON_FIELDS 4
151b7d5e03cSMatthew Dillon #define OSPREY_SIZE_ANT_CHAIN_FIELD 3
152b7d5e03cSMatthew Dillon #define OSPREY_SIZE_ANT_COMMON_FIELD 4
153b7d5e03cSMatthew Dillon #define OSPREY_ANT_CHAIN_MASK 0x7
154b7d5e03cSMatthew Dillon #define OSPREY_ANT_COMMON_MASK 0xf
155b7d5e03cSMatthew Dillon #define OSPREY_CHAIN_0_IDX 0
156b7d5e03cSMatthew Dillon #define OSPREY_CHAIN_1_IDX 1
157b7d5e03cSMatthew Dillon #define OSPREY_CHAIN_2_IDX 2
158b7d5e03cSMatthew Dillon #define OSPREY_1_CHAINMASK 1
159b7d5e03cSMatthew Dillon #define OSPREY_2LOHI_CHAINMASK 5
160b7d5e03cSMatthew Dillon #define OSPREY_2LOMID_CHAINMASK 3
161b7d5e03cSMatthew Dillon #define OSPREY_3_CHAINMASK 7
162b7d5e03cSMatthew Dillon
163b7d5e03cSMatthew Dillon #define AR928X_NUM_ANT_CHAIN_FIELDS 6
164b7d5e03cSMatthew Dillon #define AR928X_SIZE_ANT_CHAIN_FIELD 2
165b7d5e03cSMatthew Dillon #define AR928X_ANT_CHAIN_MASK 0x3
166b7d5e03cSMatthew Dillon
167b7d5e03cSMatthew Dillon /* Delta from which to start power to pdadc table */
168b7d5e03cSMatthew Dillon /* This offset is used in both open loop and closed loop power control
169b7d5e03cSMatthew Dillon * schemes. In open loop power control, it is not really needed, but for
170b7d5e03cSMatthew Dillon * the "sake of consistency" it was kept.
171b7d5e03cSMatthew Dillon * For certain AP designs, this value is overwritten by the value in the flag
172b7d5e03cSMatthew Dillon * "pwrTableOffset" just before writing the pdadc vs pwr into the chip registers.
173b7d5e03cSMatthew Dillon */
174b7d5e03cSMatthew Dillon #define OSPREY_PWR_TABLE_OFFSET 0
175b7d5e03cSMatthew Dillon
176b7d5e03cSMatthew Dillon //enable flags for voltage and temp compensation
177b7d5e03cSMatthew Dillon #define ENABLE_TEMP_COMPENSATION 0x01
178b7d5e03cSMatthew Dillon #define ENABLE_VOLT_COMPENSATION 0x02
179b7d5e03cSMatthew Dillon
180b7d5e03cSMatthew Dillon #define FLASH_BASE_CALDATA_OFFSET 0x1000
181b7d5e03cSMatthew Dillon #define AR9300_EEPROM_SIZE 16*1024 // byte addressable
182b7d5e03cSMatthew Dillon #define FIXED_CCA_THRESHOLD 15
183b7d5e03cSMatthew Dillon
184b7d5e03cSMatthew Dillon typedef struct eepFlags {
185b7d5e03cSMatthew Dillon u_int8_t op_flags;
186b7d5e03cSMatthew Dillon u_int8_t eepMisc;
187b7d5e03cSMatthew Dillon } __packed EEP_FLAGS;
188b7d5e03cSMatthew Dillon
189b7d5e03cSMatthew Dillon typedef enum targetPowerHTRates {
190b7d5e03cSMatthew Dillon HT_TARGET_RATE_0_8_16,
191b7d5e03cSMatthew Dillon HT_TARGET_RATE_1_3_9_11_17_19,
192b7d5e03cSMatthew Dillon HT_TARGET_RATE_4,
193b7d5e03cSMatthew Dillon HT_TARGET_RATE_5,
194b7d5e03cSMatthew Dillon HT_TARGET_RATE_6,
195b7d5e03cSMatthew Dillon HT_TARGET_RATE_7,
196b7d5e03cSMatthew Dillon HT_TARGET_RATE_12,
197b7d5e03cSMatthew Dillon HT_TARGET_RATE_13,
198b7d5e03cSMatthew Dillon HT_TARGET_RATE_14,
199b7d5e03cSMatthew Dillon HT_TARGET_RATE_15,
200b7d5e03cSMatthew Dillon HT_TARGET_RATE_20,
201b7d5e03cSMatthew Dillon HT_TARGET_RATE_21,
202b7d5e03cSMatthew Dillon HT_TARGET_RATE_22,
203b7d5e03cSMatthew Dillon HT_TARGET_RATE_23
204b7d5e03cSMatthew Dillon }TARGET_POWER_HT_RATES;
205b7d5e03cSMatthew Dillon
206*0641bef7SMatthew Dillon static const int mapRate2Index[24]=
207b7d5e03cSMatthew Dillon {
208b7d5e03cSMatthew Dillon 0,1,1,1,2,
209b7d5e03cSMatthew Dillon 3,4,5,0,1,
210b7d5e03cSMatthew Dillon 1,1,6,7,8,
211b7d5e03cSMatthew Dillon 9,0,1,1,1,
212b7d5e03cSMatthew Dillon 10,11,12,13
213b7d5e03cSMatthew Dillon };
214b7d5e03cSMatthew Dillon
215b7d5e03cSMatthew Dillon typedef enum targetPowerLegacyRates {
216b7d5e03cSMatthew Dillon LEGACY_TARGET_RATE_6_24,
217b7d5e03cSMatthew Dillon LEGACY_TARGET_RATE_36,
218b7d5e03cSMatthew Dillon LEGACY_TARGET_RATE_48,
219b7d5e03cSMatthew Dillon LEGACY_TARGET_RATE_54
220b7d5e03cSMatthew Dillon }TARGET_POWER_LEGACY_RATES;
221b7d5e03cSMatthew Dillon
222b7d5e03cSMatthew Dillon typedef enum targetPowerCckRates {
223b7d5e03cSMatthew Dillon LEGACY_TARGET_RATE_1L_5L,
224b7d5e03cSMatthew Dillon LEGACY_TARGET_RATE_5S,
225b7d5e03cSMatthew Dillon LEGACY_TARGET_RATE_11L,
226b7d5e03cSMatthew Dillon LEGACY_TARGET_RATE_11S
227b7d5e03cSMatthew Dillon }TARGET_POWER_CCK_RATES;
228b7d5e03cSMatthew Dillon
229b7d5e03cSMatthew Dillon #define MAX_MODAL_RESERVED 11
230b7d5e03cSMatthew Dillon #define MAX_MODAL_FUTURE 5
231b7d5e03cSMatthew Dillon #define MAX_BASE_EXTENSION_FUTURE 2
232b7d5e03cSMatthew Dillon #define MAX_TEMP_SLOPE 8
233b7d5e03cSMatthew Dillon #define OSPREY_CHECKSUM_LOCATION (OSPREY_EEP_START_LOC + 1)
234b7d5e03cSMatthew Dillon
235b7d5e03cSMatthew Dillon typedef struct osprey_BaseEepHeader {
236b7d5e03cSMatthew Dillon u_int16_t reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration
237b7d5e03cSMatthew Dillon u_int8_t txrx_mask; //4 bits tx and 4 bits rx
238b7d5e03cSMatthew Dillon EEP_FLAGS op_cap_flags;
239b7d5e03cSMatthew Dillon u_int8_t rf_silent;
240b7d5e03cSMatthew Dillon u_int8_t blue_tooth_options;
241b7d5e03cSMatthew Dillon u_int8_t device_cap;
242b7d5e03cSMatthew Dillon u_int8_t device_type; // takes lower byte in eeprom location
243b7d5e03cSMatthew Dillon int8_t pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration
244b7d5e03cSMatthew Dillon u_int8_t params_for_tuning_caps[2]; //placeholder, get more details from Don
245b7d5e03cSMatthew Dillon u_int8_t feature_enable; //bit0 - enable tx temp comp
246b7d5e03cSMatthew Dillon //bit1 - enable tx volt comp
247b7d5e03cSMatthew Dillon //bit2 - enable fastClock - default to 1
248b7d5e03cSMatthew Dillon //bit3 - enable doubling - default to 1
249b7d5e03cSMatthew Dillon //bit4 - enable internal regulator - default to 1
250b7d5e03cSMatthew Dillon //bit5 - enable paprd - default to 0
251b7d5e03cSMatthew Dillon //bit6 - enable TuningCaps - default to 0
252b7d5e03cSMatthew Dillon //bit7 - enable tx_frame_to_xpa_on - default to 0
253b7d5e03cSMatthew Dillon u_int8_t misc_configuration; //misc flags: bit0 - turn down drivestrength
254b7d5e03cSMatthew Dillon // bit 1:2 - 0=don't force, 1=force to thermometer 0, 2=force to thermometer 1, 3=force to thermometer 2
255b7d5e03cSMatthew Dillon // bit 3 - reduce chain mask from 0x7 to 0x3 on 2 stream rates
256b7d5e03cSMatthew Dillon // bit 4 - enable quick drop
257b7d5e03cSMatthew Dillon // bit 5 - enable 8 temp slop
258b7d5e03cSMatthew Dillon // bit 6; enable xLNA_bias_strength
259b7d5e03cSMatthew Dillon // bit 7; enable rf_gain_cap
260b7d5e03cSMatthew Dillon u_int8_t eeprom_write_enable_gpio;
261b7d5e03cSMatthew Dillon u_int8_t wlan_disable_gpio;
262b7d5e03cSMatthew Dillon u_int8_t wlan_led_gpio;
263b7d5e03cSMatthew Dillon u_int8_t rx_band_select_gpio;
264b7d5e03cSMatthew Dillon u_int8_t txrxgain;
265b7d5e03cSMatthew Dillon u_int32_t swreg; // SW controlled internal regulator fields
266b7d5e03cSMatthew Dillon } __packed OSPREY_BASE_EEP_HEADER;
267b7d5e03cSMatthew Dillon
268b7d5e03cSMatthew Dillon typedef struct osprey_BaseExtension_1 {
269b7d5e03cSMatthew Dillon u_int8_t ant_div_control;
270b7d5e03cSMatthew Dillon u_int8_t future[MAX_BASE_EXTENSION_FUTURE];
271b7d5e03cSMatthew Dillon u_int8_t misc_enable;
272b7d5e03cSMatthew Dillon int8_t tempslopextension[MAX_TEMP_SLOPE];
273b7d5e03cSMatthew Dillon int8_t quick_drop_low;
274b7d5e03cSMatthew Dillon int8_t quick_drop_high;
275b7d5e03cSMatthew Dillon } __packed OSPREY_BASE_EXTENSION_1;
276b7d5e03cSMatthew Dillon
277b7d5e03cSMatthew Dillon typedef struct osprey_BaseExtension_2 {
278b7d5e03cSMatthew Dillon int8_t temp_slope_low;
279b7d5e03cSMatthew Dillon int8_t temp_slope_high;
280b7d5e03cSMatthew Dillon u_int8_t xatten1_db_low[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
281b7d5e03cSMatthew Dillon u_int8_t xatten1_margin_low[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
282b7d5e03cSMatthew Dillon u_int8_t xatten1_db_high[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
283b7d5e03cSMatthew Dillon u_int8_t xatten1_margin_high[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
284b7d5e03cSMatthew Dillon } __packed OSPREY_BASE_EXTENSION_2;
285b7d5e03cSMatthew Dillon
286b7d5e03cSMatthew Dillon typedef struct spurChanStruct {
287b7d5e03cSMatthew Dillon u_int16_t spur_chan;
288b7d5e03cSMatthew Dillon u_int8_t spurRangeLow;
289b7d5e03cSMatthew Dillon u_int8_t spurRangeHigh;
290b7d5e03cSMatthew Dillon } __packed SPUR_CHAN;
291b7d5e03cSMatthew Dillon
292b7d5e03cSMatthew Dillon //Note the order of the fields in this structure has been optimized to put all fields likely to change together
293b7d5e03cSMatthew Dillon typedef struct ospreyModalEepHeader {
294b7d5e03cSMatthew Dillon u_int32_t ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting)
295b7d5e03cSMatthew Dillon u_int32_t ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12
296b7d5e03cSMatthew Dillon u_int16_t ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each)
297b7d5e03cSMatthew Dillon u_int8_t xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
298b7d5e03cSMatthew Dillon u_int8_t xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
299b7d5e03cSMatthew Dillon int8_t temp_slope;
300b7d5e03cSMatthew Dillon int8_t voltSlope;
301b7d5e03cSMatthew Dillon u_int8_t spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format
302b7d5e03cSMatthew Dillon int8_t noise_floor_thresh_ch[OSPREY_MAX_CHAINS];// 3 //Check if the register is per chain
303b7d5e03cSMatthew Dillon u_int8_t reserved[MAX_MODAL_RESERVED];
304b7d5e03cSMatthew Dillon int8_t quick_drop;
305b7d5e03cSMatthew Dillon u_int8_t xpa_bias_lvl; // 1
306b7d5e03cSMatthew Dillon u_int8_t tx_frame_to_data_start; // 1
307b7d5e03cSMatthew Dillon u_int8_t tx_frame_to_pa_on; // 1
308b7d5e03cSMatthew Dillon u_int8_t txClip; // 4 bits tx_clip, 4 bits dac_scale_cck
309b7d5e03cSMatthew Dillon int8_t antenna_gain; // 1
310b7d5e03cSMatthew Dillon u_int8_t switchSettling; // 1
311b7d5e03cSMatthew Dillon int8_t adcDesiredSize; // 1
312b7d5e03cSMatthew Dillon u_int8_t tx_end_to_xpa_off; // 1
313b7d5e03cSMatthew Dillon u_int8_t txEndToRxOn; // 1
314b7d5e03cSMatthew Dillon u_int8_t tx_frame_to_xpa_on; // 1
315b7d5e03cSMatthew Dillon u_int8_t thresh62; // 1
316b7d5e03cSMatthew Dillon u_int32_t paprd_rate_mask_ht20;
317b7d5e03cSMatthew Dillon u_int32_t paprd_rate_mask_ht40;
318b7d5e03cSMatthew Dillon u_int16_t switchcomspdt;
319b7d5e03cSMatthew Dillon u_int8_t xLNA_bias_strength; // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2
320b7d5e03cSMatthew Dillon u_int8_t rf_gain_cap;
321b7d5e03cSMatthew Dillon u_int8_t tx_gain_cap; // bit0:4 txgain cap, txgain index for max_txgain + 20 (10dBm higher than max txgain)
322b7d5e03cSMatthew Dillon u_int8_t futureModal[MAX_MODAL_FUTURE];
323b7d5e03cSMatthew Dillon // last 12 bytes stolen and moved to newly created base extension structure
324b7d5e03cSMatthew Dillon } __packed OSPREY_MODAL_EEP_HEADER; // == 100 B
325b7d5e03cSMatthew Dillon
326b7d5e03cSMatthew Dillon typedef struct ospCalDataPerFreqOpLoop {
327b7d5e03cSMatthew Dillon int8_t ref_power; /* */
328b7d5e03cSMatthew Dillon u_int8_t volt_meas; /* pdadc voltage at power measurement */
329b7d5e03cSMatthew Dillon u_int8_t temp_meas; /* pcdac used for power measurement */
330b7d5e03cSMatthew Dillon int8_t rx_noisefloor_cal; /*range is -60 to -127 create a mapping equation 1db resolution */
331b7d5e03cSMatthew Dillon int8_t rx_noisefloor_power; /*range is same as noisefloor */
332b7d5e03cSMatthew Dillon u_int8_t rxTempMeas; /*temp measured when noisefloor cal was performed */
333b7d5e03cSMatthew Dillon } __packed OSP_CAL_DATA_PER_FREQ_OP_LOOP;
334b7d5e03cSMatthew Dillon
335b7d5e03cSMatthew Dillon typedef struct CalTargetPowerLegacy {
336b7d5e03cSMatthew Dillon u_int8_t t_pow2x[4];
337b7d5e03cSMatthew Dillon } __packed CAL_TARGET_POWER_LEG;
338b7d5e03cSMatthew Dillon
339b7d5e03cSMatthew Dillon typedef struct ospCalTargetPowerHt {
340b7d5e03cSMatthew Dillon u_int8_t t_pow2x[14];
341b7d5e03cSMatthew Dillon } __packed OSP_CAL_TARGET_POWER_HT;
342b7d5e03cSMatthew Dillon
343b7d5e03cSMatthew Dillon #if AH_BYTE_ORDER == AH_BIG_ENDIAN
344b7d5e03cSMatthew Dillon typedef struct CalCtlEdgePwr {
345b7d5e03cSMatthew Dillon u_int8_t flag :2,
346b7d5e03cSMatthew Dillon t_power :6;
347b7d5e03cSMatthew Dillon } __packed CAL_CTL_EDGE_PWR;
348b7d5e03cSMatthew Dillon #else
349b7d5e03cSMatthew Dillon typedef struct CalCtlEdgePwr {
350b7d5e03cSMatthew Dillon u_int8_t t_power :6,
351b7d5e03cSMatthew Dillon flag :2;
352b7d5e03cSMatthew Dillon } __packed CAL_CTL_EDGE_PWR;
353b7d5e03cSMatthew Dillon #endif
354b7d5e03cSMatthew Dillon
355b7d5e03cSMatthew Dillon typedef struct ospCalCtlData_5G {
356b7d5e03cSMatthew Dillon CAL_CTL_EDGE_PWR ctl_edges[OSPREY_NUM_BAND_EDGES_5G];
357b7d5e03cSMatthew Dillon } __packed OSP_CAL_CTL_DATA_5G;
358b7d5e03cSMatthew Dillon
359b7d5e03cSMatthew Dillon typedef struct ospCalCtlData_2G {
360b7d5e03cSMatthew Dillon CAL_CTL_EDGE_PWR ctl_edges[OSPREY_NUM_BAND_EDGES_2G];
361b7d5e03cSMatthew Dillon } __packed OSP_CAL_CTL_DATA_2G;
362b7d5e03cSMatthew Dillon
363b7d5e03cSMatthew Dillon typedef struct ospreyEeprom {
364b7d5e03cSMatthew Dillon u_int8_t eeprom_version;
365b7d5e03cSMatthew Dillon u_int8_t template_version;
366b7d5e03cSMatthew Dillon u_int8_t mac_addr[6];
367b7d5e03cSMatthew Dillon u_int8_t custData[OSPREY_CUSTOMER_DATA_SIZE];
368b7d5e03cSMatthew Dillon
369b7d5e03cSMatthew Dillon OSPREY_BASE_EEP_HEADER base_eep_header;
370b7d5e03cSMatthew Dillon
371b7d5e03cSMatthew Dillon OSPREY_MODAL_EEP_HEADER modal_header_2g;
372b7d5e03cSMatthew Dillon OSPREY_BASE_EXTENSION_1 base_ext1;
373b7d5e03cSMatthew Dillon u_int8_t cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS];
374b7d5e03cSMatthew Dillon OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS];
375b7d5e03cSMatthew Dillon u_int8_t cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS];
376b7d5e03cSMatthew Dillon u_int8_t cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS];
377b7d5e03cSMatthew Dillon u_int8_t cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS];
378b7d5e03cSMatthew Dillon u_int8_t cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS];
379b7d5e03cSMatthew Dillon CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS];
380b7d5e03cSMatthew Dillon CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS];
381b7d5e03cSMatthew Dillon OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS];
382b7d5e03cSMatthew Dillon OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS];
383b7d5e03cSMatthew Dillon u_int8_t ctl_index_2g[OSPREY_NUM_CTLS_2G];
384b7d5e03cSMatthew Dillon u_int8_t ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G];
385b7d5e03cSMatthew Dillon OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G];
386b7d5e03cSMatthew Dillon
387b7d5e03cSMatthew Dillon OSPREY_MODAL_EEP_HEADER modal_header_5g;
388b7d5e03cSMatthew Dillon OSPREY_BASE_EXTENSION_2 base_ext2;
389b7d5e03cSMatthew Dillon u_int8_t cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS];
390b7d5e03cSMatthew Dillon OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS];
391b7d5e03cSMatthew Dillon u_int8_t cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS];
392b7d5e03cSMatthew Dillon u_int8_t cal_target_freqbin_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS];
393b7d5e03cSMatthew Dillon u_int8_t cal_target_freqbin_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS];
394b7d5e03cSMatthew Dillon CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS];
395b7d5e03cSMatthew Dillon OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS];
396b7d5e03cSMatthew Dillon OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS];
397b7d5e03cSMatthew Dillon u_int8_t ctl_index_5g[OSPREY_NUM_CTLS_5G];
398b7d5e03cSMatthew Dillon u_int8_t ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G];
399b7d5e03cSMatthew Dillon OSP_CAL_CTL_DATA_5G ctl_power_data_5g[OSPREY_NUM_CTLS_5G];
400b7d5e03cSMatthew Dillon } __packed ar9300_eeprom_t;
401b7d5e03cSMatthew Dillon
402b7d5e03cSMatthew Dillon
403b7d5e03cSMatthew Dillon /*
404b7d5e03cSMatthew Dillon ** SWAP Functions
405b7d5e03cSMatthew Dillon ** used to read EEPROM data, which is apparently stored in little
406b7d5e03cSMatthew Dillon ** endian form. We have included both forms of the swap functions,
407b7d5e03cSMatthew Dillon ** one for big endian and one for little endian. The indices of the
408b7d5e03cSMatthew Dillon ** array elements are the differences
409b7d5e03cSMatthew Dillon */
410b7d5e03cSMatthew Dillon #if AH_BYTE_ORDER == AH_BIG_ENDIAN
411b7d5e03cSMatthew Dillon
412b7d5e03cSMatthew Dillon #define AR9300_EEPROM_MAGIC 0x5aa5
413b7d5e03cSMatthew Dillon #define SWAP16(_x) ( (u_int16_t)( (((const u_int8_t *)(&_x))[0] ) |\
414b7d5e03cSMatthew Dillon ( ( (const u_int8_t *)( &_x ) )[1]<< 8) ) )
415b7d5e03cSMatthew Dillon
416b7d5e03cSMatthew Dillon #define SWAP32(_x) ((u_int32_t)( \
417b7d5e03cSMatthew Dillon (((const u_int8_t *)(&_x))[0]) | \
418b7d5e03cSMatthew Dillon (((const u_int8_t *)(&_x))[1]<< 8) | \
419b7d5e03cSMatthew Dillon (((const u_int8_t *)(&_x))[2]<<16) | \
420b7d5e03cSMatthew Dillon (((const u_int8_t *)(&_x))[3]<<24)))
421b7d5e03cSMatthew Dillon
422b7d5e03cSMatthew Dillon #else // AH_BYTE_ORDER
423b7d5e03cSMatthew Dillon
424b7d5e03cSMatthew Dillon #define AR9300_EEPROM_MAGIC 0xa55a
425b7d5e03cSMatthew Dillon #define SWAP16(_x) ( (u_int16_t)( (((const u_int8_t *)(&_x))[1] ) |\
426b7d5e03cSMatthew Dillon ( ( (const u_int8_t *)( &_x ) )[0]<< 8) ) )
427b7d5e03cSMatthew Dillon
428b7d5e03cSMatthew Dillon #define SWAP32(_x) ((u_int32_t)( \
429b7d5e03cSMatthew Dillon (((const u_int8_t *)(&_x))[3]) | \
430b7d5e03cSMatthew Dillon (((const u_int8_t *)(&_x))[2]<< 8) | \
431b7d5e03cSMatthew Dillon (((const u_int8_t *)(&_x))[1]<<16) | \
432b7d5e03cSMatthew Dillon (((const u_int8_t *)(&_x))[0]<<24)))
433b7d5e03cSMatthew Dillon
434b7d5e03cSMatthew Dillon #endif // AH_BYTE_ORDER
435b7d5e03cSMatthew Dillon
436b7d5e03cSMatthew Dillon // OTP registers for OSPREY
437b7d5e03cSMatthew Dillon
438b7d5e03cSMatthew Dillon #define AR_GPIO_IN_OUT 0x4048 // GPIO input / output register
439b7d5e03cSMatthew Dillon #define OTP_MEM_START_ADDRESS 0x14000
440b7d5e03cSMatthew Dillon #define OTP_STATUS0_OTP_SM_BUSY 0x00015f18
441b7d5e03cSMatthew Dillon #define OTP_STATUS1_EFUSE_READ_DATA 0x00015f1c
442b7d5e03cSMatthew Dillon
443b7d5e03cSMatthew Dillon #define OTP_LDO_CONTROL_ENABLE 0x00015f24
444b7d5e03cSMatthew Dillon #define OTP_LDO_STATUS_POWER_ON 0x00015f2c
445b7d5e03cSMatthew Dillon #define OTP_INTF0_EFUSE_WR_ENABLE_REG_V 0x00015f00
446b7d5e03cSMatthew Dillon // OTP register for Jupiter
447b7d5e03cSMatthew Dillon #define GLB_OTP_LDO_CONTROL_ENABLE 0x00020020
448b7d5e03cSMatthew Dillon #define GLB_OTP_LDO_STATUS_POWER_ON 0x00020028
449b7d5e03cSMatthew Dillon #define OTP_PGENB_SETUP_HOLD_TIME_DELAY 0x15f34
450b7d5e03cSMatthew Dillon
451b7d5e03cSMatthew Dillon // OTP register for Jupiter BT
452b7d5e03cSMatthew Dillon #define BTOTP_MEM_START_ADDRESS 0x64000
453b7d5e03cSMatthew Dillon #define BTOTP_STATUS0_OTP_SM_BUSY 0x00065f18
454b7d5e03cSMatthew Dillon #define BTOTP_STATUS1_EFUSE_READ_DATA 0x00065f1c
455b7d5e03cSMatthew Dillon #define BTOTP_INTF0_EFUSE_WR_ENABLE_REG_V 0x00065f00
456b7d5e03cSMatthew Dillon #define BTOTP_INTF2 0x00065f08
457b7d5e03cSMatthew Dillon #define BTOTP_PGENB_SETUP_HOLD_TIME_DELAY 0x65f34
458b7d5e03cSMatthew Dillon #define BT_RESET_CTL 0x44000
459b7d5e03cSMatthew Dillon #define BT_CLOCK_CONTROL 0x44028
460b7d5e03cSMatthew Dillon
461b7d5e03cSMatthew Dillon
462b7d5e03cSMatthew Dillon // OTP register for WASP
463b7d5e03cSMatthew Dillon #define OTP_MEM_START_ADDRESS_WASP 0x00030000
464b7d5e03cSMatthew Dillon #define OTP_STATUS0_OTP_SM_BUSY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1018)
465b7d5e03cSMatthew Dillon #define OTP_STATUS1_EFUSE_READ_DATA_WASP (OTP_MEM_START_ADDRESS_WASP + 0x101C)
466b7d5e03cSMatthew Dillon #define OTP_LDO_CONTROL_ENABLE_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1024)
467b7d5e03cSMatthew Dillon #define OTP_LDO_STATUS_POWER_ON_WASP (OTP_MEM_START_ADDRESS_WASP + 0x102C)
468b7d5e03cSMatthew Dillon #define OTP_INTF0_EFUSE_WR_ENABLE_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1000)
469b7d5e03cSMatthew Dillon // Below control the access timing of OTP read/write
470b7d5e03cSMatthew Dillon #define OTP_PG_STROBE_PW_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1008)
471b7d5e03cSMatthew Dillon #define OTP_RD_STROBE_PW_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x100C)
472b7d5e03cSMatthew Dillon #define OTP_VDDQ_HOLD_TIME_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1030)
473b7d5e03cSMatthew Dillon #define OTP_PGENB_SETUP_HOLD_TIME_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1034)
474b7d5e03cSMatthew Dillon #define OTP_STROBE_PULSE_INTERVAL_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1038)
475b7d5e03cSMatthew Dillon #define OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x103C)
476b7d5e03cSMatthew Dillon
477b7d5e03cSMatthew Dillon #define AR9300_EEPROM_MAGIC_OFFSET 0x0
478b7d5e03cSMatthew Dillon /* reg_off = 4 * (eep_off) */
479b7d5e03cSMatthew Dillon #define AR9300_EEPROM_S 2
480b7d5e03cSMatthew Dillon #define AR9300_EEPROM_OFFSET 0x2000
481b7d5e03cSMatthew Dillon #ifdef AR9100
482b7d5e03cSMatthew Dillon #define AR9300_EEPROM_START_ADDR 0x1fff1000
483b7d5e03cSMatthew Dillon #else
484b7d5e03cSMatthew Dillon #define AR9300_EEPROM_START_ADDR 0x503f1200
485b7d5e03cSMatthew Dillon #endif
486b7d5e03cSMatthew Dillon #define AR9300_FLASH_CAL_START_OFFSET 0x1000
487b7d5e03cSMatthew Dillon #define AR9300_EEPROM_MAX 0xae0
488b7d5e03cSMatthew Dillon #define IS_EEP_MINOR_V3(_ahp) (ar9300_eeprom_get((_ahp), EEP_MINOR_REV) >= AR9300_EEP_MINOR_VER_3)
489b7d5e03cSMatthew Dillon
490b7d5e03cSMatthew Dillon #define ar9300_get_ntxchains(_txchainmask) \
491b7d5e03cSMatthew Dillon (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
492b7d5e03cSMatthew Dillon
493b7d5e03cSMatthew Dillon /* RF silent fields in \ */
494b7d5e03cSMatthew Dillon #define EEP_RFSILENT_ENABLED 0x0001 /* bit 0: enabled/disabled */
495b7d5e03cSMatthew Dillon #define EEP_RFSILENT_ENABLED_S 0 /* bit 0: enabled/disabled */
496b7d5e03cSMatthew Dillon #define EEP_RFSILENT_POLARITY 0x0002 /* bit 1: polarity */
497b7d5e03cSMatthew Dillon #define EEP_RFSILENT_POLARITY_S 1 /* bit 1: polarity */
498b7d5e03cSMatthew Dillon #define EEP_RFSILENT_GPIO_SEL 0x00fc /* bits 2..7: gpio PIN */
499b7d5e03cSMatthew Dillon #define EEP_RFSILENT_GPIO_SEL_S 2 /* bits 2..7: gpio PIN */
500b7d5e03cSMatthew Dillon #define AR9300_EEP_VER 0xE
501b7d5e03cSMatthew Dillon #define AR9300_BCHAN_UNUSED 0xFF
502b7d5e03cSMatthew Dillon #define AR9300_MAX_RATE_POWER 63
503b7d5e03cSMatthew Dillon
504b7d5e03cSMatthew Dillon typedef enum {
505b7d5e03cSMatthew Dillon CALDATA_AUTO=0,
506b7d5e03cSMatthew Dillon CALDATA_EEPROM,
507b7d5e03cSMatthew Dillon CALDATA_FLASH,
508b7d5e03cSMatthew Dillon CALDATA_OTP
509b7d5e03cSMatthew Dillon } CALDATA_TYPE;
510b7d5e03cSMatthew Dillon
511b7d5e03cSMatthew Dillon typedef enum {
512b7d5e03cSMatthew Dillon EEP_NFTHRESH_5,
513b7d5e03cSMatthew Dillon EEP_NFTHRESH_2,
514b7d5e03cSMatthew Dillon EEP_MAC_MSW,
515b7d5e03cSMatthew Dillon EEP_MAC_MID,
516b7d5e03cSMatthew Dillon EEP_MAC_LSW,
517b7d5e03cSMatthew Dillon EEP_REG_0,
518b7d5e03cSMatthew Dillon EEP_REG_1,
519b7d5e03cSMatthew Dillon EEP_OP_CAP,
520b7d5e03cSMatthew Dillon EEP_OP_MODE,
521b7d5e03cSMatthew Dillon EEP_RF_SILENT,
522b7d5e03cSMatthew Dillon EEP_OB_5,
523b7d5e03cSMatthew Dillon EEP_DB_5,
524b7d5e03cSMatthew Dillon EEP_OB_2,
525b7d5e03cSMatthew Dillon EEP_DB_2,
526b7d5e03cSMatthew Dillon EEP_MINOR_REV,
527b7d5e03cSMatthew Dillon EEP_TX_MASK,
528b7d5e03cSMatthew Dillon EEP_RX_MASK,
529b7d5e03cSMatthew Dillon EEP_FSTCLK_5G,
530b7d5e03cSMatthew Dillon EEP_RXGAIN_TYPE,
531b7d5e03cSMatthew Dillon EEP_OL_PWRCTRL,
532b7d5e03cSMatthew Dillon EEP_TXGAIN_TYPE,
533b7d5e03cSMatthew Dillon EEP_RC_CHAIN_MASK,
534b7d5e03cSMatthew Dillon EEP_DAC_HPWR_5G,
535b7d5e03cSMatthew Dillon EEP_FRAC_N_5G,
536b7d5e03cSMatthew Dillon EEP_DEV_TYPE,
537b7d5e03cSMatthew Dillon EEP_TEMPSENSE_SLOPE,
538b7d5e03cSMatthew Dillon EEP_TEMPSENSE_SLOPE_PAL_ON,
539b7d5e03cSMatthew Dillon EEP_PWR_TABLE_OFFSET,
540b7d5e03cSMatthew Dillon EEP_DRIVE_STRENGTH,
541b7d5e03cSMatthew Dillon EEP_INTERNAL_REGULATOR,
542b7d5e03cSMatthew Dillon EEP_SWREG,
543b7d5e03cSMatthew Dillon EEP_PAPRD_ENABLED,
544b7d5e03cSMatthew Dillon EEP_ANTDIV_control,
545b7d5e03cSMatthew Dillon EEP_CHAIN_MASK_REDUCE,
546b7d5e03cSMatthew Dillon } EEPROM_PARAM;
547b7d5e03cSMatthew Dillon
548b7d5e03cSMatthew Dillon #define AR9300_RATES_OFDM_OFFSET 0
549b7d5e03cSMatthew Dillon #define AR9300_RATES_CCK_OFFSET 4
550b7d5e03cSMatthew Dillon #define AR9300_RATES_HT20_OFFSET 8
551b7d5e03cSMatthew Dillon #define AR9300_RATES_HT40_OFFSET 22
552b7d5e03cSMatthew Dillon typedef enum ar9300_Rates {
553b7d5e03cSMatthew Dillon ALL_TARGET_LEGACY_6_24,
554b7d5e03cSMatthew Dillon ALL_TARGET_LEGACY_36,
555b7d5e03cSMatthew Dillon ALL_TARGET_LEGACY_48,
556b7d5e03cSMatthew Dillon ALL_TARGET_LEGACY_54,
557b7d5e03cSMatthew Dillon ALL_TARGET_LEGACY_1L_5L,
558b7d5e03cSMatthew Dillon ALL_TARGET_LEGACY_5S,
559b7d5e03cSMatthew Dillon ALL_TARGET_LEGACY_11L,
560b7d5e03cSMatthew Dillon ALL_TARGET_LEGACY_11S,
561b7d5e03cSMatthew Dillon ALL_TARGET_HT20_0_8_16,
562b7d5e03cSMatthew Dillon ALL_TARGET_HT20_1_3_9_11_17_19,
563b7d5e03cSMatthew Dillon ALL_TARGET_HT20_4,
564b7d5e03cSMatthew Dillon ALL_TARGET_HT20_5,
565b7d5e03cSMatthew Dillon ALL_TARGET_HT20_6,
566b7d5e03cSMatthew Dillon ALL_TARGET_HT20_7,
567b7d5e03cSMatthew Dillon ALL_TARGET_HT20_12,
568b7d5e03cSMatthew Dillon ALL_TARGET_HT20_13,
569b7d5e03cSMatthew Dillon ALL_TARGET_HT20_14,
570b7d5e03cSMatthew Dillon ALL_TARGET_HT20_15,
571b7d5e03cSMatthew Dillon ALL_TARGET_HT20_20,
572b7d5e03cSMatthew Dillon ALL_TARGET_HT20_21,
573b7d5e03cSMatthew Dillon ALL_TARGET_HT20_22,
574b7d5e03cSMatthew Dillon ALL_TARGET_HT20_23,
575b7d5e03cSMatthew Dillon ALL_TARGET_HT40_0_8_16,
576b7d5e03cSMatthew Dillon ALL_TARGET_HT40_1_3_9_11_17_19,
577b7d5e03cSMatthew Dillon ALL_TARGET_HT40_4,
578b7d5e03cSMatthew Dillon ALL_TARGET_HT40_5,
579b7d5e03cSMatthew Dillon ALL_TARGET_HT40_6,
580b7d5e03cSMatthew Dillon ALL_TARGET_HT40_7,
581b7d5e03cSMatthew Dillon ALL_TARGET_HT40_12,
582b7d5e03cSMatthew Dillon ALL_TARGET_HT40_13,
583b7d5e03cSMatthew Dillon ALL_TARGET_HT40_14,
584b7d5e03cSMatthew Dillon ALL_TARGET_HT40_15,
585b7d5e03cSMatthew Dillon ALL_TARGET_HT40_20,
586b7d5e03cSMatthew Dillon ALL_TARGET_HT40_21,
587b7d5e03cSMatthew Dillon ALL_TARGET_HT40_22,
588b7d5e03cSMatthew Dillon ALL_TARGET_HT40_23,
589b7d5e03cSMatthew Dillon ar9300_rate_size
590b7d5e03cSMatthew Dillon } AR9300_RATES;
591b7d5e03cSMatthew Dillon
592b7d5e03cSMatthew Dillon
593b7d5e03cSMatthew Dillon /**************************************************************************
594b7d5e03cSMatthew Dillon * fbin2freq
595b7d5e03cSMatthew Dillon *
596b7d5e03cSMatthew Dillon * Get channel value from binary representation held in eeprom
597b7d5e03cSMatthew Dillon * RETURNS: the frequency in MHz
598b7d5e03cSMatthew Dillon */
599b7d5e03cSMatthew Dillon static inline u_int16_t
fbin2freq(u_int8_t fbin,HAL_BOOL is_2ghz)600b7d5e03cSMatthew Dillon fbin2freq(u_int8_t fbin, HAL_BOOL is_2ghz)
601b7d5e03cSMatthew Dillon {
602b7d5e03cSMatthew Dillon /*
603b7d5e03cSMatthew Dillon * Reserved value 0xFF provides an empty definition both as
604b7d5e03cSMatthew Dillon * an fbin and as a frequency - do not convert
605b7d5e03cSMatthew Dillon */
606b7d5e03cSMatthew Dillon if (fbin == AR9300_BCHAN_UNUSED)
607b7d5e03cSMatthew Dillon {
608b7d5e03cSMatthew Dillon return fbin;
609b7d5e03cSMatthew Dillon }
610b7d5e03cSMatthew Dillon
611b7d5e03cSMatthew Dillon return (u_int16_t)((is_2ghz) ? (2300 + fbin) : (4800 + 5 * fbin));
612b7d5e03cSMatthew Dillon }
613b7d5e03cSMatthew Dillon
614b7d5e03cSMatthew Dillon extern int CompressionHeaderUnpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor);
615b7d5e03cSMatthew Dillon extern void Ar9300EepromFormatConvert(ar9300_eeprom_t *mptr);
616b7d5e03cSMatthew Dillon extern HAL_BOOL ar9300_eeprom_restore(struct ath_hal *ah);
617b7d5e03cSMatthew Dillon extern int ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr, int /*msize*/);
618b7d5e03cSMatthew Dillon extern int ar9300_eeprom_base_address(struct ath_hal *ah);
619b7d5e03cSMatthew Dillon extern int ar9300_eeprom_volatile(struct ath_hal *ah);
620b7d5e03cSMatthew Dillon extern int ar9300_eeprom_low_limit(struct ath_hal *ah);
621b7d5e03cSMatthew Dillon extern u_int16_t ar9300_compression_checksum(u_int8_t *data, int dsize);
622b7d5e03cSMatthew Dillon extern int ar9300_compression_header_unpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor);
623b7d5e03cSMatthew Dillon
624b7d5e03cSMatthew Dillon extern u_int16_t ar9300_eeprom_struct_size(void);
625b7d5e03cSMatthew Dillon extern ar9300_eeprom_t *ar9300EepromStructInit(int default_index);
626b7d5e03cSMatthew Dillon extern ar9300_eeprom_t *ar9300EepromStructGet(void);
627b7d5e03cSMatthew Dillon extern ar9300_eeprom_t *ar9300_eeprom_struct_default(int default_index);
628b7d5e03cSMatthew Dillon extern ar9300_eeprom_t *ar9300_eeprom_struct_default_find_by_id(int ver);
629b7d5e03cSMatthew Dillon extern int ar9300_eeprom_struct_default_many(void);
630b7d5e03cSMatthew Dillon extern int ar9300EepromUpdateCalPier(int pierIdx, int freq, int chain,
631b7d5e03cSMatthew Dillon int pwrCorrection, int volt_meas, int temp_meas);
632b7d5e03cSMatthew Dillon extern int ar9300_power_control_override(struct ath_hal *ah, int frequency, int *correction, int *voltage, int *temperature);
633b7d5e03cSMatthew Dillon
634b7d5e03cSMatthew Dillon extern void ar9300EepromDisplayCalData(int for2GHz);
635b7d5e03cSMatthew Dillon extern void ar9300EepromDisplayAll(void);
636b7d5e03cSMatthew Dillon extern void ar9300_set_target_power_from_eeprom(struct ath_hal *ah, u_int16_t freq,
637b7d5e03cSMatthew Dillon u_int8_t *target_power_val_t2);
638b7d5e03cSMatthew Dillon extern HAL_BOOL ar9300_eeprom_set_power_per_rate_table(struct ath_hal *ah,
639b7d5e03cSMatthew Dillon ar9300_eeprom_t *p_eep_data,
640b7d5e03cSMatthew Dillon const struct ieee80211_channel *chan,
641b7d5e03cSMatthew Dillon u_int8_t *p_pwr_array,
642b7d5e03cSMatthew Dillon u_int16_t cfg_ctl,
643b7d5e03cSMatthew Dillon u_int16_t antenna_reduction,
644b7d5e03cSMatthew Dillon u_int16_t twice_max_regulatory_power,
645b7d5e03cSMatthew Dillon u_int16_t power_limit,
646b7d5e03cSMatthew Dillon u_int8_t chainmask);
647b7d5e03cSMatthew Dillon extern int ar9300_transmit_power_reg_write(struct ath_hal *ah, u_int8_t *p_pwr_array);
648b7d5e03cSMatthew Dillon
649b7d5e03cSMatthew Dillon extern u_int8_t ar9300_eeprom_get_legacy_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz);
650b7d5e03cSMatthew Dillon extern u_int8_t ar9300_eeprom_get_ht20_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz);
651b7d5e03cSMatthew Dillon extern u_int8_t ar9300_eeprom_get_ht40_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz);
652b7d5e03cSMatthew Dillon extern u_int8_t ar9300_eeprom_get_cck_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq);
653b7d5e03cSMatthew Dillon extern HAL_BOOL ar9300_internal_regulator_apply(struct ath_hal *ah);
654b7d5e03cSMatthew Dillon extern HAL_BOOL ar9300_drive_strength_apply(struct ath_hal *ah);
655b7d5e03cSMatthew Dillon extern HAL_BOOL ar9300_attenuation_apply(struct ath_hal *ah, u_int16_t channel);
656b7d5e03cSMatthew Dillon extern int32_t ar9300_thermometer_get(struct ath_hal *ah);
657b7d5e03cSMatthew Dillon extern HAL_BOOL ar9300_thermometer_apply(struct ath_hal *ah);
658b7d5e03cSMatthew Dillon extern HAL_BOOL ar9300_xpa_timing_control_apply(struct ath_hal *ah, HAL_BOOL is_2ghz);
659b7d5e03cSMatthew Dillon extern HAL_BOOL ar9300_x_lNA_bias_strength_apply(struct ath_hal *ah, HAL_BOOL is_2ghz);
660b7d5e03cSMatthew Dillon
661b7d5e03cSMatthew Dillon extern int32_t ar9300MacAdressGet(u_int8_t *mac);
662b7d5e03cSMatthew Dillon extern int32_t ar9300CustomerDataGet(u_int8_t *data, int32_t len);
663b7d5e03cSMatthew Dillon extern int32_t ar9300ReconfigDriveStrengthGet(void);
664b7d5e03cSMatthew Dillon extern int32_t ar9300EnableTempCompensationGet(void);
665b7d5e03cSMatthew Dillon extern int32_t ar9300EnableVoltCompensationGet(void);
666b7d5e03cSMatthew Dillon extern int32_t ar9300FastClockEnableGet(void);
667b7d5e03cSMatthew Dillon extern int32_t ar9300EnableDoublingGet(void);
668b7d5e03cSMatthew Dillon
669b7d5e03cSMatthew Dillon extern u_int16_t *ar9300_regulatory_domain_get(struct ath_hal *ah);
670b7d5e03cSMatthew Dillon extern int32_t ar9300_eeprom_write_enable_gpio_get(struct ath_hal *ah);
671b7d5e03cSMatthew Dillon extern int32_t ar9300_wlan_led_gpio_get(struct ath_hal *ah);
672b7d5e03cSMatthew Dillon extern int32_t ar9300_wlan_disable_gpio_get(struct ath_hal *ah);
673b7d5e03cSMatthew Dillon extern int32_t ar9300_rx_band_select_gpio_get(struct ath_hal *ah);
674b7d5e03cSMatthew Dillon extern int32_t ar9300_rx_gain_index_get(struct ath_hal *ah);
675b7d5e03cSMatthew Dillon extern int32_t ar9300_tx_gain_index_get(struct ath_hal *ah);
676b7d5e03cSMatthew Dillon extern int32_t ar9300_xpa_bias_level_get(struct ath_hal *ah, HAL_BOOL is_2ghz);
677b7d5e03cSMatthew Dillon extern HAL_BOOL ar9300_xpa_bias_level_apply(struct ath_hal *ah, HAL_BOOL is_2ghz);
678b7d5e03cSMatthew Dillon extern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz);
679b7d5e03cSMatthew Dillon extern u_int32_t ar9300_ant_ctrl_common2_get(struct ath_hal *ah, HAL_BOOL is_2ghz);
680b7d5e03cSMatthew Dillon extern u_int16_t ar9300_ant_ctrl_chain_get(struct ath_hal *ah, int chain, HAL_BOOL is_2ghz);
681b7d5e03cSMatthew Dillon extern HAL_BOOL ar9300_ant_ctrl_apply(struct ath_hal *ah, HAL_BOOL is_2ghz);
682b7d5e03cSMatthew Dillon /* since valid noise floor values are negative, returns 1 on error */
683b7d5e03cSMatthew Dillon extern int32_t ar9300_noise_floor_cal_or_power_get(
684b7d5e03cSMatthew Dillon struct ath_hal *ah, int32_t frequency, int32_t ichain, HAL_BOOL use_cal);
685b7d5e03cSMatthew Dillon #define ar9300NoiseFloorGet(ah, frequency, ichain) \
686b7d5e03cSMatthew Dillon ar9300_noise_floor_cal_or_power_get(ah, frequency, ichain, 1/*use_cal*/)
687b7d5e03cSMatthew Dillon #define ar9300NoiseFloorPowerGet(ah, frequency, ichain) \
688b7d5e03cSMatthew Dillon ar9300_noise_floor_cal_or_power_get(ah, frequency, ichain, 0/*use_cal*/)
689b7d5e03cSMatthew Dillon extern void ar9300_eeprom_template_preference(int32_t value);
690b7d5e03cSMatthew Dillon extern int32_t ar9300_eeprom_template_install(struct ath_hal *ah, int32_t value);
691b7d5e03cSMatthew Dillon extern void ar9300_calibration_data_set(struct ath_hal *ah, int32_t source);
692b7d5e03cSMatthew Dillon extern int32_t ar9300_calibration_data_get(struct ath_hal *ah);
693b7d5e03cSMatthew Dillon extern int32_t ar9300_calibration_data_address_get(struct ath_hal *ah);
694b7d5e03cSMatthew Dillon extern void ar9300_calibration_data_address_set(struct ath_hal *ah, int32_t source);
695b7d5e03cSMatthew Dillon extern HAL_BOOL ar9300_calibration_data_read_flash(struct ath_hal *ah, long address, u_int8_t *buffer, int many);
696b7d5e03cSMatthew Dillon extern HAL_BOOL ar9300_calibration_data_read_eeprom(struct ath_hal *ah, long address, u_int8_t *buffer, int many);
697b7d5e03cSMatthew Dillon extern HAL_BOOL ar9300_calibration_data_read_otp(struct ath_hal *ah, long address, u_int8_t *buffer, int many, HAL_BOOL is_wifi);
698b7d5e03cSMatthew Dillon extern HAL_BOOL ar9300_calibration_data_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many);
699b7d5e03cSMatthew Dillon extern int32_t ar9300_eeprom_size(struct ath_hal *ah);
700b7d5e03cSMatthew Dillon extern int32_t ar9300_otp_size(struct ath_hal *ah);
701b7d5e03cSMatthew Dillon extern HAL_BOOL ar9300_calibration_data_read_array(struct ath_hal *ah, int address, u_int8_t *buffer, int many);
702b7d5e03cSMatthew Dillon
703b7d5e03cSMatthew Dillon
704b7d5e03cSMatthew Dillon
705b7d5e03cSMatthew Dillon #if defined(WIN32) || defined(WIN64)
706b7d5e03cSMatthew Dillon #pragma pack (pop, ar9300)
707b7d5e03cSMatthew Dillon #endif
708b7d5e03cSMatthew Dillon
709b7d5e03cSMatthew Dillon #endif /* _ATH_AR9300_EEP_H_ */
710