1b7d5e03cSMatthew Dillon /* 2b7d5e03cSMatthew Dillon * Copyright (c) 2013 Qualcomm Atheros, Inc. 3b7d5e03cSMatthew Dillon * 4b7d5e03cSMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any 5b7d5e03cSMatthew Dillon * purpose with or without fee is hereby granted, provided that the above 6b7d5e03cSMatthew Dillon * copyright notice and this permission notice appear in all copies. 7b7d5e03cSMatthew Dillon * 8b7d5e03cSMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9b7d5e03cSMatthew Dillon * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10b7d5e03cSMatthew Dillon * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11b7d5e03cSMatthew Dillon * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12b7d5e03cSMatthew Dillon * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13b7d5e03cSMatthew Dillon * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14b7d5e03cSMatthew Dillon * PERFORMANCE OF THIS SOFTWARE. 15b7d5e03cSMatthew Dillon */ 16b7d5e03cSMatthew Dillon 17b7d5e03cSMatthew Dillon #ifndef _DEV_ATH_AR9300REG_H 18b7d5e03cSMatthew Dillon #define _DEV_ATH_AR9300REG_H 19b7d5e03cSMatthew Dillon 20b7d5e03cSMatthew Dillon #include "osprey_reg_map.h" 21b7d5e03cSMatthew Dillon #include "wasp_reg_map.h" 22b7d5e03cSMatthew Dillon 23b7d5e03cSMatthew Dillon /****************************************************************************** 24b7d5e03cSMatthew Dillon * MAC Register Map 25b7d5e03cSMatthew Dillon ******************************************************************************/ 26b7d5e03cSMatthew Dillon #define AR_MAC_DMA_OFFSET(_x) offsetof(struct mac_dma_reg, _x) 27b7d5e03cSMatthew Dillon 28b7d5e03cSMatthew Dillon /* 29b7d5e03cSMatthew Dillon * MAC DMA Registers 30b7d5e03cSMatthew Dillon */ 31b7d5e03cSMatthew Dillon 32b7d5e03cSMatthew Dillon /* MAC Control Register - only write values of 1 have effect */ 33b7d5e03cSMatthew Dillon #define AR_CR AR_MAC_DMA_OFFSET(MAC_DMA_CR) 34b7d5e03cSMatthew Dillon #define AR_CR_LP_RXE 0x00000004 // Receive LPQ enable 35b7d5e03cSMatthew Dillon #define AR_CR_HP_RXE 0x00000008 // Receive HPQ enable 36b7d5e03cSMatthew Dillon #define AR_CR_RXD 0x00000020 // Receive disable 37b7d5e03cSMatthew Dillon #define AR_CR_SWI 0x00000040 // One-shot software interrupt 38b7d5e03cSMatthew Dillon #define AR_CR_RXE (AR_CR_LP_RXE|AR_CR_HP_RXE) 39b7d5e03cSMatthew Dillon 40b7d5e03cSMatthew Dillon /* MAC configuration and status register */ 41b7d5e03cSMatthew Dillon #define AR_CFG AR_MAC_DMA_OFFSET(MAC_DMA_CFG) 42b7d5e03cSMatthew Dillon #define AR_CFG_SWTD 0x00000001 // byteswap tx descriptor words 43b7d5e03cSMatthew Dillon #define AR_CFG_SWTB 0x00000002 // byteswap tx data buffer words 44b7d5e03cSMatthew Dillon #define AR_CFG_SWRD 0x00000004 // byteswap rx descriptor words 45b7d5e03cSMatthew Dillon #define AR_CFG_SWRB 0x00000008 // byteswap rx data buffer words 46b7d5e03cSMatthew Dillon #define AR_CFG_SWRG 0x00000010 // byteswap register access data words 47b7d5e03cSMatthew Dillon #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc) 48b7d5e03cSMatthew Dillon #define AR_CFG_PHOK 0x00000100 // PHY OK status 49b7d5e03cSMatthew Dillon #define AR_CFG_CLK_GATE_DIS 0x00000400 // Clock gating disable 50b7d5e03cSMatthew Dillon #define AR_CFG_EEBS 0x00000200 // EEPROM busy 51b7d5e03cSMatthew Dillon #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 // Mask of PCI core master request queue full threshold 52b7d5e03cSMatthew Dillon #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 // Shift for PCI core master request queue full threshold 53b7d5e03cSMatthew Dillon #define AR_CFG_MISSING_TX_INTR_FIX_ENABLE 0x00080000 // See EV 61133 for details. 54b7d5e03cSMatthew Dillon 55b7d5e03cSMatthew Dillon /* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */ 56b7d5e03cSMatthew Dillon #define AR_RXBP_THRESH AR_MAC_DMA_OFFSET(MAC_DMA_RXBUFPTR_THRESH) 57b7d5e03cSMatthew Dillon #define AR_RXBP_THRESH_HP 0x0000000f 58b7d5e03cSMatthew Dillon #define AR_RXBP_THRESH_HP_S 0 59b7d5e03cSMatthew Dillon #define AR_RXBP_THRESH_LP 0x00003f00 60b7d5e03cSMatthew Dillon #define AR_RXBP_THRESH_LP_S 8 61b7d5e03cSMatthew Dillon 62b7d5e03cSMatthew Dillon /* Tx DMA Descriptor Pointer Threshold register */ 63b7d5e03cSMatthew Dillon #define AR_TXDP_THRESH AR_MAC_DMA_OFFSET(MAC_DMA_TXDPPTR_THRESH) 64b7d5e03cSMatthew Dillon 65b7d5e03cSMatthew Dillon /* Mac Interrupt rate threshold register */ 66b7d5e03cSMatthew Dillon #define AR_MIRT AR_MAC_DMA_OFFSET(MAC_DMA_MIRT) 67b7d5e03cSMatthew Dillon #define AR_MIRT_VAL 0x0000ffff // in uS 68b7d5e03cSMatthew Dillon #define AR_MIRT_VAL_S 16 69b7d5e03cSMatthew Dillon 70b7d5e03cSMatthew Dillon /* MAC Global Interrupt enable register */ 71b7d5e03cSMatthew Dillon #define AR_IER AR_MAC_DMA_OFFSET(MAC_DMA_GLOBAL_IER) 72b7d5e03cSMatthew Dillon #define AR_IER_ENABLE 0x00000001 // Global interrupt enable 73b7d5e03cSMatthew Dillon #define AR_IER_DISABLE 0x00000000 // Global interrupt disable 74b7d5e03cSMatthew Dillon 75b7d5e03cSMatthew Dillon /* Mac Tx Interrupt mitigation threshold */ 76b7d5e03cSMatthew Dillon #define AR_TIMT AR_MAC_DMA_OFFSET(MAC_DMA_TIMT) 77b7d5e03cSMatthew Dillon #define AR_TIMT_LAST 0x0000ffff // Last packet threshold 78b7d5e03cSMatthew Dillon #define AR_TIMT_LAST_S 0 79b7d5e03cSMatthew Dillon #define AR_TIMT_FIRST 0xffff0000 // First packet threshold 80b7d5e03cSMatthew Dillon #define AR_TIMT_FIRST_S 16 81b7d5e03cSMatthew Dillon 82b7d5e03cSMatthew Dillon /* Mac Rx Interrupt mitigation threshold */ 83b7d5e03cSMatthew Dillon #define AR_RIMT AR_MAC_DMA_OFFSET(MAC_DMA_RIMT) 84b7d5e03cSMatthew Dillon #define AR_RIMT_LAST 0x0000ffff // Last packet threshold 85b7d5e03cSMatthew Dillon #define AR_RIMT_LAST_S 0 86b7d5e03cSMatthew Dillon #define AR_RIMT_FIRST 0xffff0000 // First packet threshold 87b7d5e03cSMatthew Dillon #define AR_RIMT_FIRST_S 16 88b7d5e03cSMatthew Dillon 89b7d5e03cSMatthew Dillon #define AR_DMASIZE_4B 0x00000000 // DMA size 4 bytes (TXCFG + RXCFG) 90b7d5e03cSMatthew Dillon #define AR_DMASIZE_8B 0x00000001 // DMA size 8 bytes 91b7d5e03cSMatthew Dillon #define AR_DMASIZE_16B 0x00000002 // DMA size 16 bytes 92b7d5e03cSMatthew Dillon #define AR_DMASIZE_32B 0x00000003 // DMA size 32 bytes 93b7d5e03cSMatthew Dillon #define AR_DMASIZE_64B 0x00000004 // DMA size 64 bytes 94b7d5e03cSMatthew Dillon #define AR_DMASIZE_128B 0x00000005 // DMA size 128 bytes 95b7d5e03cSMatthew Dillon #define AR_DMASIZE_256B 0x00000006 // DMA size 256 bytes 96b7d5e03cSMatthew Dillon #define AR_DMASIZE_512B 0x00000007 // DMA size 512 bytes 97b7d5e03cSMatthew Dillon 98b7d5e03cSMatthew Dillon /* MAC Tx DMA size config register */ 99b7d5e03cSMatthew Dillon #define AR_TXCFG AR_MAC_DMA_OFFSET(MAC_DMA_TXCFG) 100b7d5e03cSMatthew Dillon #define AR_TXCFG_DMASZ_MASK 0x00000007 101b7d5e03cSMatthew Dillon #define AR_TXCFG_DMASZ_4B 0 102b7d5e03cSMatthew Dillon #define AR_TXCFG_DMASZ_8B 1 103b7d5e03cSMatthew Dillon #define AR_TXCFG_DMASZ_16B 2 104b7d5e03cSMatthew Dillon #define AR_TXCFG_DMASZ_32B 3 105b7d5e03cSMatthew Dillon #define AR_TXCFG_DMASZ_64B 4 106b7d5e03cSMatthew Dillon #define AR_TXCFG_DMASZ_128B 5 107b7d5e03cSMatthew Dillon #define AR_TXCFG_DMASZ_256B 6 108b7d5e03cSMatthew Dillon #define AR_TXCFG_DMASZ_512B 7 109b7d5e03cSMatthew Dillon #define AR_FTRIG 0x000003F0 // Mask for Frame trigger level 110b7d5e03cSMatthew Dillon #define AR_FTRIG_S 4 // Shift for Frame trigger level 111b7d5e03cSMatthew Dillon #define AR_FTRIG_IMMED 0x00000000 // bytes in PCU TX FIFO before air 112b7d5e03cSMatthew Dillon #define AR_FTRIG_64B 0x00000010 // default 113b7d5e03cSMatthew Dillon #define AR_FTRIG_128B 0x00000020 114b7d5e03cSMatthew Dillon #define AR_FTRIG_192B 0x00000030 115b7d5e03cSMatthew Dillon #define AR_FTRIG_256B 0x00000040 // 5 bits total 116b7d5e03cSMatthew Dillon #define AR_FTRIG_512B 0x00000080 // 5 bits total 117b7d5e03cSMatthew Dillon #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 118b7d5e03cSMatthew Dillon #define AR_TXCFG_RTS_FAIL_EXCESSIVE_RETRIES 0x00080000 119b7d5e03cSMatthew Dillon #define AR_TXCFG_RTS_FAIL_EXCESSIVE_RETRIES_S 19 120b7d5e03cSMatthew Dillon 121b7d5e03cSMatthew Dillon /* MAC Rx DMA size config register */ 122b7d5e03cSMatthew Dillon #define AR_RXCFG AR_MAC_DMA_OFFSET(MAC_DMA_RXCFG) 123b7d5e03cSMatthew Dillon #define AR_RXCFG_CHIRP 0x00000008 // Only double chirps 124b7d5e03cSMatthew Dillon #define AR_RXCFG_ZLFDMA 0x00000010 // Enable DMA of zero-length frame 125b7d5e03cSMatthew Dillon #define AR_RXCFG_DMASZ_MASK 0x00000007 126b7d5e03cSMatthew Dillon #define AR_RXCFG_DMASZ_4B 0 127b7d5e03cSMatthew Dillon #define AR_RXCFG_DMASZ_8B 1 128b7d5e03cSMatthew Dillon #define AR_RXCFG_DMASZ_16B 2 129b7d5e03cSMatthew Dillon #define AR_RXCFG_DMASZ_32B 3 130b7d5e03cSMatthew Dillon #define AR_RXCFG_DMASZ_64B 4 131b7d5e03cSMatthew Dillon #define AR_RXCFG_DMASZ_128B 5 132b7d5e03cSMatthew Dillon #define AR_RXCFG_DMASZ_256B 6 133b7d5e03cSMatthew Dillon #define AR_RXCFG_DMASZ_512B 7 134b7d5e03cSMatthew Dillon 135b7d5e03cSMatthew Dillon /* MAC Rx jumbo descriptor last address register */ 136b7d5e03cSMatthew Dillon #define AR_RXJLA AR_MAC_DMA_OFFSET(MAC_DMA_RXJLA) 137b7d5e03cSMatthew Dillon 138b7d5e03cSMatthew Dillon 139b7d5e03cSMatthew Dillon /* MAC MIB control register */ 140b7d5e03cSMatthew Dillon #define AR_MIBC AR_MAC_DMA_OFFSET(MAC_DMA_MIBC) 141b7d5e03cSMatthew Dillon #define AR_MIBC_COW 0x00000001 // counter overflow warning 142b7d5e03cSMatthew Dillon #define AR_MIBC_FMC 0x00000002 // freeze MIB counters 143b7d5e03cSMatthew Dillon #define AR_MIBC_CMC 0x00000004 // clear MIB counters 144b7d5e03cSMatthew Dillon #define AR_MIBC_MCS 0x00000008 // MIB counter strobe increment all 145b7d5e03cSMatthew Dillon 146b7d5e03cSMatthew Dillon /* MAC timeout prescale count */ 147b7d5e03cSMatthew Dillon #define AR_TOPS AR_MAC_DMA_OFFSET(MAC_DMA_TOPS) 148b7d5e03cSMatthew Dillon #define AR_TOPS_MASK 0x0000FFFF // Mask for timeout prescale 149b7d5e03cSMatthew Dillon 150b7d5e03cSMatthew Dillon /* MAC no frame received timeout */ 151b7d5e03cSMatthew Dillon #define AR_RXNPTO AR_MAC_DMA_OFFSET(MAC_DMA_RXNPTO) 152b7d5e03cSMatthew Dillon #define AR_RXNPTO_MASK 0x000003FF // Mask for no frame received timeout 153b7d5e03cSMatthew Dillon 154b7d5e03cSMatthew Dillon /* MAC no frame trasmitted timeout */ 155b7d5e03cSMatthew Dillon #define AR_TXNPTO AR_MAC_DMA_OFFSET(MAC_DMA_TXNPTO) 156b7d5e03cSMatthew Dillon #define AR_TXNPTO_MASK 0x000003FF // Mask for no frame transmitted timeout 157b7d5e03cSMatthew Dillon #define AR_TXNPTO_QCU_MASK 0x000FFC00 // Mask indicating the set of QCUs 158b7d5e03cSMatthew Dillon // for which frame completions will cause 159b7d5e03cSMatthew Dillon // a reset of the no frame transmitted timeout 160b7d5e03cSMatthew Dillon 161b7d5e03cSMatthew Dillon /* MAC receive frame gap timeout */ 162b7d5e03cSMatthew Dillon #define AR_RPGTO AR_MAC_DMA_OFFSET(MAC_DMA_RPGTO) 163b7d5e03cSMatthew Dillon #define AR_RPGTO_MASK 0x000003FF // Mask for receive frame gap timeout 164b7d5e03cSMatthew Dillon 165b7d5e03cSMatthew Dillon /* MAC miscellaneous control/status register */ 166b7d5e03cSMatthew Dillon #define AR_MACMISC AR_MAC_DMA_OFFSET(MAC_DMA_MACMISC) 167b7d5e03cSMatthew Dillon #define AR_MACMISC_PCI_EXT_FORCE 0x00000010 //force msb to 10 to ahb 168b7d5e03cSMatthew Dillon #define AR_MACMISC_DMA_OBS 0x000001E0 // Mask for DMA observation bus mux select 169b7d5e03cSMatthew Dillon #define AR_MACMISC_DMA_OBS_S 5 // Shift for DMA observation bus mux select 170b7d5e03cSMatthew Dillon #define AR_MACMISC_DMA_OBS_LINE_0 0 // Observation DMA line 0 171b7d5e03cSMatthew Dillon #define AR_MACMISC_DMA_OBS_LINE_1 1 // Observation DMA line 1 172b7d5e03cSMatthew Dillon #define AR_MACMISC_DMA_OBS_LINE_2 2 // Observation DMA line 2 173b7d5e03cSMatthew Dillon #define AR_MACMISC_DMA_OBS_LINE_3 3 // Observation DMA line 3 174b7d5e03cSMatthew Dillon #define AR_MACMISC_DMA_OBS_LINE_4 4 // Observation DMA line 4 175b7d5e03cSMatthew Dillon #define AR_MACMISC_DMA_OBS_LINE_5 5 // Observation DMA line 5 176b7d5e03cSMatthew Dillon #define AR_MACMISC_DMA_OBS_LINE_6 6 // Observation DMA line 6 177b7d5e03cSMatthew Dillon #define AR_MACMISC_DMA_OBS_LINE_7 7 // Observation DMA line 7 178b7d5e03cSMatthew Dillon #define AR_MACMISC_DMA_OBS_LINE_8 8 // Observation DMA line 8 179b7d5e03cSMatthew Dillon #define AR_MACMISC_MISC_OBS 0x00000E00 // Mask for MISC observation bus mux select 180b7d5e03cSMatthew Dillon #define AR_MACMISC_MISC_OBS_S 9 // Shift for MISC observation bus mux select 181b7d5e03cSMatthew Dillon #define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000 // Mask for MAC observation bus mux select (lsb) 182b7d5e03cSMatthew Dillon #define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 // Shift for MAC observation bus mux select (lsb) 183b7d5e03cSMatthew Dillon #define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000 // Mask for MAC observation bus mux select (msb) 184b7d5e03cSMatthew Dillon #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 // Shift for MAC observation bus mux select (msb) 185b7d5e03cSMatthew Dillon #define AR_MACMISC_MISC_OBS_BUS_1 1 // MAC observation bus mux select 186b7d5e03cSMatthew Dillon 187b7d5e03cSMatthew Dillon /* MAC Interrupt Config register */ 188b7d5e03cSMatthew Dillon #define AR_INTCFG AR_MAC_DMA_OFFSET(MAC_DMA_INTER) 189b7d5e03cSMatthew Dillon #define AR_INTCFG_REQ 0x00000001 // Interrupt request flag 190b7d5e03cSMatthew Dillon // Indicates whether the DMA engine should generate 191b7d5e03cSMatthew Dillon // an interrupt upon completion of the frame 192b7d5e03cSMatthew Dillon #define AR_INTCFG_MSI_RXOK 0x00000000 // Rx interrupt for MSI logic is RXOK 193b7d5e03cSMatthew Dillon #define AR_INTCFG_MSI_RXINTM 0x00000004 // Rx interrupt for MSI logic is RXINTM 194b7d5e03cSMatthew Dillon #define AR_INTCFG_MSI_RXMINTR 0x00000006 // Rx interrupt for MSI logic is RXMINTR 195b7d5e03cSMatthew Dillon #define AR_INTCFG_MSI_TXOK 0x00000000 // Rx interrupt for MSI logic is TXOK 196b7d5e03cSMatthew Dillon #define AR_INTCFG_MSI_TXINTM 0x00000010 // Rx interrupt for MSI logic is TXINTM 197b7d5e03cSMatthew Dillon #define AR_INTCFG_MSI_TXMINTR 0x00000018 // Rx interrupt for MSI logic is TXMINTR 198b7d5e03cSMatthew Dillon 199b7d5e03cSMatthew Dillon /* MAC DMA Data Buffer length, in bytes */ 200b7d5e03cSMatthew Dillon #define AR_DATABUF AR_MAC_DMA_OFFSET(MAC_DMA_DATABUF) 201b7d5e03cSMatthew Dillon #define AR_DATABUF_MASK 0x00000FFF 202b7d5e03cSMatthew Dillon 203b7d5e03cSMatthew Dillon /* MAC global transmit timeout */ 204b7d5e03cSMatthew Dillon #define AR_GTXTO AR_MAC_DMA_OFFSET(MAC_DMA_GTT) 205b7d5e03cSMatthew Dillon #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 206b7d5e03cSMatthew Dillon #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 207b7d5e03cSMatthew Dillon #define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 208b7d5e03cSMatthew Dillon 209b7d5e03cSMatthew Dillon /* MAC global transmit timeout mode */ 210b7d5e03cSMatthew Dillon #define AR_GTTM AR_MAC_DMA_OFFSET(MAC_DMA_GTTM) 211b7d5e03cSMatthew Dillon #define AR_GTTM_USEC 0x00000001 // usec strobe 212b7d5e03cSMatthew Dillon #define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle 213b7d5e03cSMatthew Dillon #define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low 214b7d5e03cSMatthew Dillon #define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe 215b7d5e03cSMatthew Dillon 216b7d5e03cSMatthew Dillon /* MAC carrier sense timeout */ 217b7d5e03cSMatthew Dillon #define AR_CST AR_MAC_DMA_OFFSET(MAC_DMA_CST) 218b7d5e03cSMatthew Dillon #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 219b7d5e03cSMatthew Dillon #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 220b7d5e03cSMatthew Dillon #define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 221b7d5e03cSMatthew Dillon 222b7d5e03cSMatthew Dillon /* MAC Indicates the size of High and Low priority rx_dp FIFOs */ 223b7d5e03cSMatthew Dillon #define AR_RXDP_SIZE AR_MAC_DMA_OFFSET(MAC_DMA_RXDP_SIZE) 224b7d5e03cSMatthew Dillon #define AR_RXDP_LP_SZ_MASK 0x0000007f 225b7d5e03cSMatthew Dillon #define AR_RXDP_LP_SZ_S 0 226b7d5e03cSMatthew Dillon #define AR_RXDP_HP_SZ_MASK 0x00001f00 227b7d5e03cSMatthew Dillon #define AR_RXDP_HP_SZ_S 8 228b7d5e03cSMatthew Dillon 229b7d5e03cSMatthew Dillon /* MAC Rx High Priority Queue RXDP Pointer (lower 32 bits) */ 230b7d5e03cSMatthew Dillon #define AR_HP_RXDP AR_MAC_DMA_OFFSET(MAC_DMA_RX_QUEUE_HP_RXDP) 231b7d5e03cSMatthew Dillon 232b7d5e03cSMatthew Dillon /* MAC Rx Low Priority Queue RXDP Pointer (lower 32 bits) */ 233b7d5e03cSMatthew Dillon #define AR_LP_RXDP AR_MAC_DMA_OFFSET(MAC_DMA_RX_QUEUE_LP_RXDP) 234b7d5e03cSMatthew Dillon 235b7d5e03cSMatthew Dillon 236b7d5e03cSMatthew Dillon /* Primary Interrupt Status Register */ 237b7d5e03cSMatthew Dillon #define AR_ISR AR_MAC_DMA_OFFSET(MAC_DMA_ISR_P) 238b7d5e03cSMatthew Dillon #define AR_ISR_HP_RXOK 0x00000001 // At least one frame rx on high-priority queue sans errors 239b7d5e03cSMatthew Dillon #define AR_ISR_LP_RXOK 0x00000002 // At least one frame rx on low-priority queue sans errors 240b7d5e03cSMatthew Dillon #define AR_ISR_RXERR 0x00000004 // Receive error interrupt 241b7d5e03cSMatthew Dillon #define AR_ISR_RXNOPKT 0x00000008 // No frame received within timeout clock 242b7d5e03cSMatthew Dillon #define AR_ISR_RXEOL 0x00000010 // Received descriptor empty interrupt 243b7d5e03cSMatthew Dillon #define AR_ISR_RXORN 0x00000020 // Receive FIFO overrun interrupt 244b7d5e03cSMatthew Dillon #define AR_ISR_TXOK 0x00000040 // Transmit okay interrupt 245b7d5e03cSMatthew Dillon #define AR_ISR_TXERR 0x00000100 // Transmit error interrupt 246b7d5e03cSMatthew Dillon #define AR_ISR_TXNOPKT 0x00000200 // No frame transmitted interrupt 247b7d5e03cSMatthew Dillon #define AR_ISR_TXEOL 0x00000400 // Transmit descriptor empty interrupt 248b7d5e03cSMatthew Dillon #define AR_ISR_TXURN 0x00000800 // Transmit FIFO underrun interrupt 249b7d5e03cSMatthew Dillon #define AR_ISR_MIB 0x00001000 // MIB interrupt - see MIBC 250b7d5e03cSMatthew Dillon #define AR_ISR_SWI 0x00002000 // Software interrupt 251b7d5e03cSMatthew Dillon #define AR_ISR_RXPHY 0x00004000 // PHY receive error interrupt 252b7d5e03cSMatthew Dillon #define AR_ISR_RXKCM 0x00008000 // Key-cache miss interrupt 253b7d5e03cSMatthew Dillon #define AR_ISR_SWBA 0x00010000 // Software beacon alert interrupt 254b7d5e03cSMatthew Dillon #define AR_ISR_BRSSI 0x00020000 // Beacon threshold interrupt 255b7d5e03cSMatthew Dillon #define AR_ISR_BMISS 0x00040000 // Beacon missed interrupt 256b7d5e03cSMatthew Dillon #define AR_ISR_TXMINTR 0x00080000 // Maximum interrupt transmit rate 257b7d5e03cSMatthew Dillon #define AR_ISR_BNR 0x00100000 // Beacon not ready interrupt 258b7d5e03cSMatthew Dillon #define AR_ISR_RXCHIRP 0x00200000 // Phy received a 'chirp' 259b7d5e03cSMatthew Dillon #define AR_ISR_HCFPOLL 0x00400000 // Received directed HCF poll 260b7d5e03cSMatthew Dillon #define AR_ISR_BCNMISC 0x00800000 // CST, GTT, TIM, CABEND, DTIMSYNC, BCNTO, CABTO, 261b7d5e03cSMatthew Dillon // TSFOOR, DTIM, and TBTT_TIME bits bits from ISR_S2 262b7d5e03cSMatthew Dillon #define AR_ISR_TIM 0x00800000 // TIM interrupt 263b7d5e03cSMatthew Dillon #define AR_ISR_RXMINTR 0x01000000 // Maximum interrupt receive rate 264b7d5e03cSMatthew Dillon #define AR_ISR_QCBROVF 0x02000000 // QCU CBR overflow interrupt 265b7d5e03cSMatthew Dillon #define AR_ISR_QCBRURN 0x04000000 // QCU CBR underrun interrupt 266b7d5e03cSMatthew Dillon #define AR_ISR_QTRIG 0x08000000 // QCU scheduling trigger interrupt 267b7d5e03cSMatthew Dillon #define AR_ISR_GENTMR 0x10000000 // OR of generic timer bits in ISR 5 268b7d5e03cSMatthew Dillon #define AR_ISR_HCFTO 0x20000000 // HCF poll timeout 269b7d5e03cSMatthew Dillon #define AR_ISR_TXINTM 0x40000000 // Tx interrupt after mitigation 270b7d5e03cSMatthew Dillon #define AR_ISR_RXINTM 0x80000000 // Rx interrupt after mitigation 271b7d5e03cSMatthew Dillon 272b7d5e03cSMatthew Dillon /* MAC Secondary interrupt status register 0 */ 273b7d5e03cSMatthew Dillon #define AR_ISR_S0 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S0) 274b7d5e03cSMatthew Dillon #define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9) 275b7d5e03cSMatthew Dillon #define AR_ISR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9) 276b7d5e03cSMatthew Dillon 277b7d5e03cSMatthew Dillon /* MAC Secondary interrupt status register 1 */ 278b7d5e03cSMatthew Dillon #define AR_ISR_S1 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S1) 279b7d5e03cSMatthew Dillon #define AR_ISR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9) 280b7d5e03cSMatthew Dillon #define AR_ISR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9) 281b7d5e03cSMatthew Dillon #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9) 282b7d5e03cSMatthew Dillon #define AR_ISR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9) 283b7d5e03cSMatthew Dillon 284b7d5e03cSMatthew Dillon /* MAC Secondary interrupt status register 2 */ 285b7d5e03cSMatthew Dillon #define AR_ISR_S2 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S2) 286b7d5e03cSMatthew Dillon #define AR_ISR_S2_QCU_TXURN 0x000003FF // Mask for TXURN (QCU 0-9) 287b7d5e03cSMatthew Dillon #define AR_ISR_S2_BBPANIC 0x00010000 // Panic watchdog IRQ from BB 288b7d5e03cSMatthew Dillon #define AR_ISR_S2_CST 0x00400000 // Carrier sense timeout 289b7d5e03cSMatthew Dillon #define AR_ISR_S2_GTT 0x00800000 // Global transmit timeout 290b7d5e03cSMatthew Dillon #define AR_ISR_S2_TIM 0x01000000 // TIM 291b7d5e03cSMatthew Dillon #define AR_ISR_S2_CABEND 0x02000000 // CABEND 292b7d5e03cSMatthew Dillon #define AR_ISR_S2_DTIMSYNC 0x04000000 // DTIMSYNC 293b7d5e03cSMatthew Dillon #define AR_ISR_S2_BCNTO 0x08000000 // BCNTO 294b7d5e03cSMatthew Dillon #define AR_ISR_S2_CABTO 0x10000000 // CABTO 295b7d5e03cSMatthew Dillon #define AR_ISR_S2_DTIM 0x20000000 // DTIM 296b7d5e03cSMatthew Dillon #define AR_ISR_S2_TSFOOR 0x40000000 // Rx TSF out of range 297b7d5e03cSMatthew Dillon #define AR_ISR_S2_TBTT_TIME 0x80000000 // TBTT-referenced timer 298b7d5e03cSMatthew Dillon 299b7d5e03cSMatthew Dillon /* MAC Secondary interrupt status register 3 */ 300b7d5e03cSMatthew Dillon #define AR_ISR_S3 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S3) 301b7d5e03cSMatthew Dillon #define AR_ISR_S3_QCU_QCBROVF 0x000003FF // Mask for QCBROVF (QCU 0-9) 302b7d5e03cSMatthew Dillon #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 // Mask for QCBRURN (QCU 0-9) 303b7d5e03cSMatthew Dillon 304b7d5e03cSMatthew Dillon /* MAC Secondary interrupt status register 4 */ 305b7d5e03cSMatthew Dillon #define AR_ISR_S4 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S4) 306b7d5e03cSMatthew Dillon #define AR_ISR_S4_QCU_QTRIG 0x000003FF // Mask for QTRIG (QCU 0-9) 307b7d5e03cSMatthew Dillon #define AR_ISR_S4_RESV0 0xFFFFFC00 // Reserved 308b7d5e03cSMatthew Dillon 309b7d5e03cSMatthew Dillon /* MAC Secondary interrupt status register 5 */ 310b7d5e03cSMatthew Dillon #define AR_ISR_S5 AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S5) 311b7d5e03cSMatthew Dillon #define AR_ISR_S5_TIMER_TRIG 0x000000FF // Mask for timer trigger (0-7) 312b7d5e03cSMatthew Dillon #define AR_ISR_S5_TIMER_THRESH 0x0007FE00 // Mask for timer threshold(0-7) 313b7d5e03cSMatthew Dillon #define AR_ISR_S5_TIM_TIMER 0x00000010 // TIM Timer ISR 314b7d5e03cSMatthew Dillon #define AR_ISR_S5_DTIM_TIMER 0x00000020 // DTIM Timer ISR 315b7d5e03cSMatthew Dillon #define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80 // ISR for generic timer trigger 7 316b7d5e03cSMatthew Dillon #define AR_ISR_S5_GENTIMER_TRIG_S 0 317b7d5e03cSMatthew Dillon #define AR_ISR_S5_GENTIMER_THRESH 0xFF800000 // ISR for generic timer threshold 7 318b7d5e03cSMatthew Dillon #define AR_ISR_S5_GENTIMER_THRESH_S 16 319b7d5e03cSMatthew Dillon 320b7d5e03cSMatthew Dillon /* Primary Interrupt Mask Register */ 321b7d5e03cSMatthew Dillon #define AR_IMR AR_MAC_DMA_OFFSET(MAC_DMA_IMR_P) 322b7d5e03cSMatthew Dillon #define AR_IMR_RXOK_HP 0x00000001 // Receive high-priority interrupt enable mask 323b7d5e03cSMatthew Dillon #define AR_IMR_RXOK_LP 0x00000002 // Receive low-priority interrupt enable mask 324b7d5e03cSMatthew Dillon #define AR_IMR_RXERR 0x00000004 // Receive error interrupt 325b7d5e03cSMatthew Dillon #define AR_IMR_RXNOPKT 0x00000008 // No frame received within timeout clock 326b7d5e03cSMatthew Dillon #define AR_IMR_RXEOL 0x00000010 // Received descriptor empty interrupt 327b7d5e03cSMatthew Dillon #define AR_IMR_RXORN 0x00000020 // Receive FIFO overrun interrupt 328b7d5e03cSMatthew Dillon #define AR_IMR_TXOK 0x00000040 // Transmit okay interrupt 329b7d5e03cSMatthew Dillon #define AR_IMR_TXERR 0x00000100 // Transmit error interrupt 330b7d5e03cSMatthew Dillon #define AR_IMR_TXNOPKT 0x00000200 // No frame transmitted interrupt 331b7d5e03cSMatthew Dillon #define AR_IMR_TXEOL 0x00000400 // Transmit descriptor empty interrupt 332b7d5e03cSMatthew Dillon #define AR_IMR_TXURN 0x00000800 // Transmit FIFO underrun interrupt 333b7d5e03cSMatthew Dillon #define AR_IMR_MIB 0x00001000 // MIB interrupt - see MIBC 334b7d5e03cSMatthew Dillon #define AR_IMR_SWI 0x00002000 // Software interrupt 335b7d5e03cSMatthew Dillon #define AR_IMR_RXPHY 0x00004000 // PHY receive error interrupt 336b7d5e03cSMatthew Dillon #define AR_IMR_RXKCM 0x00008000 // Key-cache miss interrupt 337b7d5e03cSMatthew Dillon #define AR_IMR_SWBA 0x00010000 // Software beacon alert interrupt 338b7d5e03cSMatthew Dillon #define AR_IMR_BRSSI 0x00020000 // Beacon threshold interrupt 339b7d5e03cSMatthew Dillon #define AR_IMR_BMISS 0x00040000 // Beacon missed interrupt 340b7d5e03cSMatthew Dillon #define AR_IMR_TXMINTR 0x00080000 // Maximum interrupt transmit rate 341b7d5e03cSMatthew Dillon #define AR_IMR_BNR 0x00100000 // BNR interrupt 342b7d5e03cSMatthew Dillon #define AR_IMR_RXCHIRP 0x00200000 // RXCHIRP interrupt 343b7d5e03cSMatthew Dillon #define AR_IMR_BCNMISC 0x00800000 // Venice: BCNMISC 344b7d5e03cSMatthew Dillon #define AR_IMR_TIM 0x00800000 // TIM interrupt 345b7d5e03cSMatthew Dillon #define AR_IMR_RXMINTR 0x01000000 // Maximum interrupt receive rate 346b7d5e03cSMatthew Dillon #define AR_IMR_QCBROVF 0x02000000 // QCU CBR overflow interrupt 347b7d5e03cSMatthew Dillon #define AR_IMR_QCBRURN 0x04000000 // QCU CBR underrun interrupt 348b7d5e03cSMatthew Dillon #define AR_IMR_QTRIG 0x08000000 // QCU scheduling trigger interrupt 349b7d5e03cSMatthew Dillon #define AR_IMR_GENTMR 0x10000000 // Generic timer interrupt 350b7d5e03cSMatthew Dillon #define AR_IMR_TXINTM 0x40000000 // Tx interrupt after mitigation 351b7d5e03cSMatthew Dillon #define AR_IMR_RXINTM 0x80000000 // Rx interrupt after mitigation 352b7d5e03cSMatthew Dillon 353b7d5e03cSMatthew Dillon /* MAC Secondary interrupt mask register 0 */ 354b7d5e03cSMatthew Dillon #define AR_IMR_S0 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S0) 355b7d5e03cSMatthew Dillon #define AR_IMR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9) 356b7d5e03cSMatthew Dillon #define AR_IMR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9) 357b7d5e03cSMatthew Dillon 358b7d5e03cSMatthew Dillon /* MAC Secondary interrupt mask register 1 */ 359b7d5e03cSMatthew Dillon #define AR_IMR_S1 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S1) 360b7d5e03cSMatthew Dillon #define AR_IMR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9) 361b7d5e03cSMatthew Dillon #define AR_IMR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9) 362b7d5e03cSMatthew Dillon #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9) 363b7d5e03cSMatthew Dillon #define AR_IMR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9) 364b7d5e03cSMatthew Dillon 365b7d5e03cSMatthew Dillon /* MAC Secondary interrupt mask register 2 */ 366b7d5e03cSMatthew Dillon #define AR_IMR_S2 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S2) 367b7d5e03cSMatthew Dillon #define AR_IMR_S2_QCU_TXURN 0x000003FF // Mask for TXURN (QCU 0-9) 368b7d5e03cSMatthew Dillon #define AR_IMR_S2_QCU_TXURN_S 0 // Shift for TXURN (QCU 0-9) 369b7d5e03cSMatthew Dillon #define AR_IMR_S2_BBPANIC 0x00010000 // Panic watchdog IRQ from BB 370b7d5e03cSMatthew Dillon #define AR_IMR_S2_CST 0x00400000 // Carrier sense timeout 371b7d5e03cSMatthew Dillon #define AR_IMR_S2_GTT 0x00800000 // Global transmit timeout 372b7d5e03cSMatthew Dillon #define AR_IMR_S2_TIM 0x01000000 // TIM 373b7d5e03cSMatthew Dillon #define AR_IMR_S2_CABEND 0x02000000 // CABEND 374b7d5e03cSMatthew Dillon #define AR_IMR_S2_DTIMSYNC 0x04000000 // DTIMSYNC 375b7d5e03cSMatthew Dillon #define AR_IMR_S2_BCNTO 0x08000000 // BCNTO 376b7d5e03cSMatthew Dillon #define AR_IMR_S2_CABTO 0x10000000 // CABTO 377b7d5e03cSMatthew Dillon #define AR_IMR_S2_DTIM 0x20000000 // DTIM 378b7d5e03cSMatthew Dillon #define AR_IMR_S2_TSFOOR 0x40000000 // TSF out of range 379b7d5e03cSMatthew Dillon 380b7d5e03cSMatthew Dillon /* MAC Secondary interrupt mask register 3 */ 381b7d5e03cSMatthew Dillon #define AR_IMR_S3 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S3) 382b7d5e03cSMatthew Dillon #define AR_IMR_S3_QCU_QCBROVF 0x000003FF // Mask for QCBROVF (QCU 0-9) 383b7d5e03cSMatthew Dillon #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 // Mask for QCBRURN (QCU 0-9) 384b7d5e03cSMatthew Dillon #define AR_IMR_S3_QCU_QCBRURN_S 16 // Shift for QCBRURN (QCU 0-9) 385b7d5e03cSMatthew Dillon 386b7d5e03cSMatthew Dillon /* MAC Secondary interrupt mask register 4 */ 387b7d5e03cSMatthew Dillon #define AR_IMR_S4 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S4) 388b7d5e03cSMatthew Dillon #define AR_IMR_S4_QCU_QTRIG 0x000003FF // Mask for QTRIG (QCU 0-9) 389b7d5e03cSMatthew Dillon #define AR_IMR_S4_RESV0 0xFFFFFC00 // Reserved 390b7d5e03cSMatthew Dillon 391b7d5e03cSMatthew Dillon /* MAC Secondary interrupt mask register 5 */ 392b7d5e03cSMatthew Dillon #define AR_IMR_S5 AR_MAC_DMA_OFFSET(MAC_DMA_IMR_S5) 393b7d5e03cSMatthew Dillon #define AR_IMR_S5_TIMER_TRIG 0x000000FF // Mask for timer trigger (0-7) 394b7d5e03cSMatthew Dillon #define AR_IMR_S5_TIMER_THRESH 0x0000FF00 // Mask for timer threshold(0-7) 395b7d5e03cSMatthew Dillon #define AR_IMR_S5_TIM_TIMER 0x00000010 // TIM Timer Mask 396b7d5e03cSMatthew Dillon #define AR_IMR_S5_DTIM_TIMER 0x00000020 // DTIM Timer Mask 397b7d5e03cSMatthew Dillon #define AR_IMR_S5_GENTIMER7 0x00000080 // Mask for timer 7 trigger 398b7d5e03cSMatthew Dillon #define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80 // Mask for generic timer trigger 7-15 399b7d5e03cSMatthew Dillon #define AR_IMR_S5_GENTIMER_TRIG_S 0 400b7d5e03cSMatthew Dillon #define AR_IMR_S5_GENTIMER_THRESH 0xFF800000 // Mask for generic timer threshold 7-15 401b7d5e03cSMatthew Dillon #define AR_IMR_S5_GENTIMER_THRESH_S 16 402b7d5e03cSMatthew Dillon 403b7d5e03cSMatthew Dillon 404b7d5e03cSMatthew Dillon /* Interrupt status registers (read-and-clear access secondary shadow copies) */ 405b7d5e03cSMatthew Dillon 406b7d5e03cSMatthew Dillon /* MAC Primary interrupt status register read-and-clear access */ 407b7d5e03cSMatthew Dillon #define AR_ISR_RAC AR_MAC_DMA_OFFSET(MAC_DMA_ISR_P_RAC) 408b7d5e03cSMatthew Dillon /* MAC Secondary interrupt status register 0 - shadow copy */ 409b7d5e03cSMatthew Dillon #define AR_ISR_S0_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S0_S) 410b7d5e03cSMatthew Dillon #define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9) 411b7d5e03cSMatthew Dillon #define AR_ISR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9) 412b7d5e03cSMatthew Dillon 413b7d5e03cSMatthew Dillon /* MAC Secondary interrupt status register 1 - shadow copy */ 414b7d5e03cSMatthew Dillon #define AR_ISR_S1_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S1_S) 415b7d5e03cSMatthew Dillon #define AR_ISR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9) 416b7d5e03cSMatthew Dillon #define AR_ISR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9) 417b7d5e03cSMatthew Dillon #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9) 418b7d5e03cSMatthew Dillon #define AR_ISR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9) 419b7d5e03cSMatthew Dillon 420b7d5e03cSMatthew Dillon /* MAC Secondary interrupt status register 2 - shadow copy */ 421b7d5e03cSMatthew Dillon #define AR_ISR_S2_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S2_S) 422b7d5e03cSMatthew Dillon /* MAC Secondary interrupt status register 3 - shadow copy */ 423b7d5e03cSMatthew Dillon #define AR_ISR_S3_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S3_S) 424b7d5e03cSMatthew Dillon /* MAC Secondary interrupt status register 4 - shadow copy */ 425b7d5e03cSMatthew Dillon #define AR_ISR_S4_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S4_S) 426b7d5e03cSMatthew Dillon /* MAC Secondary interrupt status register 5 - shadow copy */ 427b7d5e03cSMatthew Dillon #define AR_ISR_S5_S AR_MAC_DMA_OFFSET(MAC_DMA_ISR_S5_S) 428b7d5e03cSMatthew Dillon 429b7d5e03cSMatthew Dillon /* MAC DMA Debug Registers */ 430b7d5e03cSMatthew Dillon #define AR_DMADBG_0 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_0) 431b7d5e03cSMatthew Dillon #define AR_DMADBG_1 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_1) 432b7d5e03cSMatthew Dillon #define AR_DMADBG_2 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_2) 433b7d5e03cSMatthew Dillon #define AR_DMADBG_3 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_3) 434b7d5e03cSMatthew Dillon #define AR_DMADBG_4 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_4) 435b7d5e03cSMatthew Dillon #define AR_DMADBG_5 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_5) 436b7d5e03cSMatthew Dillon #define AR_DMADBG_6 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_6) 437b7d5e03cSMatthew Dillon #define AR_DMADBG_7 AR_MAC_DMA_OFFSET(MAC_DMA_DMADBG_7) 438b7d5e03cSMatthew Dillon #define AR_DMATXDP_QCU_7_0 AR_MAC_DMA_OFFSET(MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0) 439b7d5e03cSMatthew Dillon #define AR_DMATXDP_QCU_9_8 AR_MAC_DMA_OFFSET(MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8) 440b7d5e03cSMatthew Dillon 441b7d5e03cSMatthew Dillon #define AR_DMADBG_RX_STATE 0x00000F00 // Mask for Rx DMA State machine 442b7d5e03cSMatthew Dillon 443b7d5e03cSMatthew Dillon 444b7d5e03cSMatthew Dillon /* 445b7d5e03cSMatthew Dillon * MAC QCU Registers 446b7d5e03cSMatthew Dillon */ 447b7d5e03cSMatthew Dillon #define AR_MAC_QCU_OFFSET(_x) offsetof(struct mac_qcu_reg, _x) 448b7d5e03cSMatthew Dillon 449b7d5e03cSMatthew Dillon #define AR_NUM_QCU 10 // Only use QCU 0-9 for forward QCU compatibility 450b7d5e03cSMatthew Dillon #define AR_QCU_0 0x0001 451b7d5e03cSMatthew Dillon #define AR_QCU_1 0x0002 452b7d5e03cSMatthew Dillon #define AR_QCU_2 0x0004 453b7d5e03cSMatthew Dillon #define AR_QCU_3 0x0008 454b7d5e03cSMatthew Dillon #define AR_QCU_4 0x0010 455b7d5e03cSMatthew Dillon #define AR_QCU_5 0x0020 456b7d5e03cSMatthew Dillon #define AR_QCU_6 0x0040 457b7d5e03cSMatthew Dillon #define AR_QCU_7 0x0080 458b7d5e03cSMatthew Dillon #define AR_QCU_8 0x0100 459b7d5e03cSMatthew Dillon #define AR_QCU_9 0x0200 460b7d5e03cSMatthew Dillon 461b7d5e03cSMatthew Dillon /* MAC Transmit Queue descriptor pointer */ 462b7d5e03cSMatthew Dillon #define AR_Q0_TXDP AR_MAC_QCU_OFFSET(MAC_QCU_TXDP) 463b7d5e03cSMatthew Dillon #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) 464b7d5e03cSMatthew Dillon 465b7d5e03cSMatthew Dillon /* MAC Transmit Status Ring Start Address */ 466b7d5e03cSMatthew Dillon #define AR_Q_STATUS_RING_START AR_MAC_QCU_OFFSET(MAC_QCU_STATUS_RING_START) 467b7d5e03cSMatthew Dillon /* MAC Transmit Status Ring End Address */ 468b7d5e03cSMatthew Dillon #define AR_Q_STATUS_RING_END AR_MAC_QCU_OFFSET(MAC_QCU_STATUS_RING_END) 469b7d5e03cSMatthew Dillon /* Current Address in the Transmit Status Ring pointed to by the MAC */ 470b7d5e03cSMatthew Dillon #define AR_Q_STATUS_RING_CURRENT AR_MAC_QCU_OFFSET(MAC_QCU_STATUS_RING_CURRENT) 471b7d5e03cSMatthew Dillon 472b7d5e03cSMatthew Dillon /* MAC Transmit Queue enable */ 473b7d5e03cSMatthew Dillon #define AR_Q_TXE AR_MAC_QCU_OFFSET(MAC_QCU_TXE) 474b7d5e03cSMatthew Dillon #define AR_Q_TXE_M 0x000003FF // Mask for TXE (QCU 0-9) 475b7d5e03cSMatthew Dillon 476b7d5e03cSMatthew Dillon /* MAC Transmit Queue disable */ 477b7d5e03cSMatthew Dillon #define AR_Q_TXD AR_MAC_QCU_OFFSET(MAC_QCU_TXD) 478b7d5e03cSMatthew Dillon #define AR_Q_TXD_M 0x000003FF // Mask for TXD (QCU 0-9) 479b7d5e03cSMatthew Dillon 480b7d5e03cSMatthew Dillon /* MAC CBR configuration */ 481b7d5e03cSMatthew Dillon #define AR_Q0_CBRCFG AR_MAC_QCU_OFFSET(MAC_QCU_CBR) 482b7d5e03cSMatthew Dillon #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) 483b7d5e03cSMatthew Dillon #define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF // Mask for CBR interval (us) 484b7d5e03cSMatthew Dillon #define AR_Q_CBRCFG_INTERVAL_S 0 // Shift for CBR interval (us) 485b7d5e03cSMatthew Dillon #define AR_Q_CBRCFG_OVF_THRESH 0xFF000000 // Mask for CBR overflow threshold 486b7d5e03cSMatthew Dillon #define AR_Q_CBRCFG_OVF_THRESH_S 24 // Shift for CBR overflow threshold 487b7d5e03cSMatthew Dillon 488b7d5e03cSMatthew Dillon /* MAC ready_time configuration */ 489b7d5e03cSMatthew Dillon #define AR_Q0_RDYTIMECFG AR_MAC_QCU_OFFSET(MAC_QCU_RDYTIME) 490b7d5e03cSMatthew Dillon #define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2)) 491b7d5e03cSMatthew Dillon #define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF // Mask for ready_time duration (us) 492b7d5e03cSMatthew Dillon #define AR_Q_RDYTIMECFG_DURATION_S 0 // Shift for ready_time duration (us) 493b7d5e03cSMatthew Dillon #define AR_Q_RDYTIMECFG_EN 0x01000000 // ready_time enable 494b7d5e03cSMatthew Dillon 495b7d5e03cSMatthew Dillon /* MAC OneShotArm set control */ 496b7d5e03cSMatthew Dillon #define AR_Q_ONESHOTARM_SC AR_MAC_QCU_OFFSET(MAC_QCU_ONESHOT_ARM_SC) 497b7d5e03cSMatthew Dillon #define AR_Q_ONESHOTARM_SC_M 0x000003FF // Mask for #define AR_Q_ONESHOTARM_SC (QCU 0-9) 498b7d5e03cSMatthew Dillon #define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00 // Reserved 499b7d5e03cSMatthew Dillon 500b7d5e03cSMatthew Dillon /* MAC OneShotArm clear control */ 501b7d5e03cSMatthew Dillon #define AR_Q_ONESHOTARM_CC AR_MAC_QCU_OFFSET(MAC_QCU_ONESHOT_ARM_CC) 502b7d5e03cSMatthew Dillon #define AR_Q_ONESHOTARM_CC_M 0x000003FF // Mask for #define AR_Q_ONESHOTARM_CC (QCU 0-9) 503b7d5e03cSMatthew Dillon #define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00 // Reserved 504b7d5e03cSMatthew Dillon 505b7d5e03cSMatthew Dillon /* MAC Miscellaneous QCU settings */ 506b7d5e03cSMatthew Dillon #define AR_Q0_MISC AR_MAC_QCU_OFFSET(MAC_QCU_MISC) 507b7d5e03cSMatthew Dillon #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) 508b7d5e03cSMatthew Dillon #define AR_Q_MISC_FSP 0x0000000F // Mask for Frame Scheduling Policy 509b7d5e03cSMatthew Dillon #define AR_Q_MISC_FSP_ASAP 0 // ASAP 510b7d5e03cSMatthew Dillon #define AR_Q_MISC_FSP_CBR 1 // CBR 511b7d5e03cSMatthew Dillon #define AR_Q_MISC_FSP_DBA_GATED 2 // DMA Beacon Alert gated 512b7d5e03cSMatthew Dillon #define AR_Q_MISC_FSP_TIM_GATED 3 // TIM gated 513b7d5e03cSMatthew Dillon #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 // Beacon-sent-gated 514b7d5e03cSMatthew Dillon #define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 // Beacon-received-gated 515b7d5e03cSMatthew Dillon #define AR_Q_MISC_ONE_SHOT_EN 0x00000010 // OneShot enable 516b7d5e03cSMatthew Dillon #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 // Disable CBR expired counter incr (empty q) 517b7d5e03cSMatthew Dillon #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 // Disable CBR expired counter incr (empty beacon q) 518b7d5e03cSMatthew Dillon #define AR_Q_MISC_BEACON_USE 0x00000080 // Beacon use indication 519b7d5e03cSMatthew Dillon #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 // CBR expired counter limit enable 520b7d5e03cSMatthew Dillon #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 // Enable TXE cleared on ready_time expired or VEOL 521b7d5e03cSMatthew Dillon #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 // Reset CBR expired counter 522b7d5e03cSMatthew Dillon #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 // DCU frame early termination request control 523b7d5e03cSMatthew Dillon #define AR_Q_MISC_RESV0 0xFFFFF000 // Reserved 524b7d5e03cSMatthew Dillon 525b7d5e03cSMatthew Dillon /* MAC Miscellaneous QCU status */ 526b7d5e03cSMatthew Dillon #define AR_Q0_STS AR_MAC_QCU_OFFSET(MAC_QCU_CNT) 527b7d5e03cSMatthew Dillon #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) 528b7d5e03cSMatthew Dillon #define AR_Q_STS_PEND_FR_CNT 0x00000003 // Mask for Pending Frame Count 529b7d5e03cSMatthew Dillon #define AR_Q_STS_RESV0 0x000000FC // Reserved 530b7d5e03cSMatthew Dillon #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 // Mask for CBR expired counter 531b7d5e03cSMatthew Dillon #define AR_Q_STS_RESV1 0xFFFF0000 // Reserved 532b7d5e03cSMatthew Dillon 533b7d5e03cSMatthew Dillon /* MAC ReadyTimeShutdown status */ 534b7d5e03cSMatthew Dillon #define AR_Q_RDYTIMESHDN AR_MAC_QCU_OFFSET(MAC_QCU_RDYTIME_SHDN) 535b7d5e03cSMatthew Dillon #define AR_Q_RDYTIMESHDN_M 0x000003FF // Mask for ReadyTimeShutdown status (QCU 0-9) 536b7d5e03cSMatthew Dillon 537b7d5e03cSMatthew Dillon /* MAC Descriptor CRC check */ 538b7d5e03cSMatthew Dillon #define AR_Q_DESC_CRCCHK AR_MAC_QCU_OFFSET(MAC_QCU_DESC_CRC_CHK) 539b7d5e03cSMatthew Dillon #define AR_Q_DESC_CRCCHK_EN 1 // Enable CRC check on the descriptor fetched from HOST 540b7d5e03cSMatthew Dillon 541b7d5e03cSMatthew Dillon #define AR_MAC_QCU_EOL AR_MAC_QCU_OFFSET(MAC_QCU_EOL) 542b7d5e03cSMatthew Dillon #define AR_MAC_QCU_EOL_DUR_CAL_EN 0x000003FF // Adjusts EOL for frame duration (QCU 0-9) 543b7d5e03cSMatthew Dillon #define AR_MAC_QCU_EOL_DUR_CAL_EN_S 0 544b7d5e03cSMatthew Dillon 545b7d5e03cSMatthew Dillon /* 546b7d5e03cSMatthew Dillon * MAC DCU Registers 547b7d5e03cSMatthew Dillon */ 548b7d5e03cSMatthew Dillon 549b7d5e03cSMatthew Dillon #define AR_MAC_DCU_OFFSET(_x) offsetof(struct mac_dcu_reg, _x) 550b7d5e03cSMatthew Dillon 551b7d5e03cSMatthew Dillon #define AR_NUM_DCU 10 // Only use 10 DCU's for forward QCU/DCU compatibility 552b7d5e03cSMatthew Dillon #define AR_DCU_0 0x0001 553b7d5e03cSMatthew Dillon #define AR_DCU_1 0x0002 554b7d5e03cSMatthew Dillon #define AR_DCU_2 0x0004 555b7d5e03cSMatthew Dillon #define AR_DCU_3 0x0008 556b7d5e03cSMatthew Dillon #define AR_DCU_4 0x0010 557b7d5e03cSMatthew Dillon #define AR_DCU_5 0x0020 558b7d5e03cSMatthew Dillon #define AR_DCU_6 0x0040 559b7d5e03cSMatthew Dillon #define AR_DCU_7 0x0080 560b7d5e03cSMatthew Dillon #define AR_DCU_8 0x0100 561b7d5e03cSMatthew Dillon #define AR_DCU_9 0x0200 562b7d5e03cSMatthew Dillon 563b7d5e03cSMatthew Dillon /* MAC QCU Mask */ 564b7d5e03cSMatthew Dillon #define AR_D0_QCUMASK AR_MAC_DCU_OFFSET(MAC_DCU_QCUMASK) 565b7d5e03cSMatthew Dillon #define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) 566b7d5e03cSMatthew Dillon #define AR_D_QCUMASK 0x000003FF // Mask for QCU Mask (QCU 0-9) 567b7d5e03cSMatthew Dillon #define AR_D_QCUMASK_RESV0 0xFFFFFC00 // Reserved 568b7d5e03cSMatthew Dillon 569b7d5e03cSMatthew Dillon /* DCU transmit filter cmd (w/only) */ 570b7d5e03cSMatthew Dillon #define AR_D_TXBLK_CMD AR_MAC_DCU_OFFSET(MAC_DCU_TXFILTER_DCU0_31_0) 571b7d5e03cSMatthew Dillon #define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) // DCU transmit filter data 572b7d5e03cSMatthew Dillon 573b7d5e03cSMatthew Dillon 574b7d5e03cSMatthew Dillon /* MAC DCU-global IFS settings: SIFS duration */ 575b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_SIFS AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_SIFS) 576b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_SIFS_M 0x0000FFFF // Mask for SIFS duration (core clocks) 577b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF // Reserved 578b7d5e03cSMatthew Dillon 579b7d5e03cSMatthew Dillon /* MAC DCU-global IFS settings: slot duration */ 580b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_SLOT AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_SLOT) 581b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_SLOT_M 0x0000FFFF // Mask for Slot duration (core clocks) 582b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 // Reserved 583b7d5e03cSMatthew Dillon 584b7d5e03cSMatthew Dillon /* MAC Retry limits */ 585b7d5e03cSMatthew Dillon #define AR_D0_RETRY_LIMIT AR_MAC_DCU_OFFSET(MAC_DCU_RETRY_LIMIT) 586b7d5e03cSMatthew Dillon #define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) 587b7d5e03cSMatthew Dillon #define AR_D_RETRY_LIMIT_FR_SH 0x0000000F // Mask for frame short retry limit 588b7d5e03cSMatthew Dillon #define AR_D_RETRY_LIMIT_FR_SH_S 0 // Shift for frame short retry limit 589b7d5e03cSMatthew Dillon #define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 // Mask for station short retry limit 590b7d5e03cSMatthew Dillon #define AR_D_RETRY_LIMIT_STA_SH_S 8 // Shift for station short retry limit 591b7d5e03cSMatthew Dillon #define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 // Mask for station short retry limit 592b7d5e03cSMatthew Dillon #define AR_D_RETRY_LIMIT_STA_LG_S 14 // Shift for station short retry limit 593b7d5e03cSMatthew Dillon #define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 // Reserved 594b7d5e03cSMatthew Dillon 595b7d5e03cSMatthew Dillon /* MAC DCU-global IFS settings: EIFS duration */ 596b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_EIFS AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_EIFS) 597b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_EIFS_M 0x0000FFFF // Mask for Slot duration (core clocks) 598b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 // Reserved 599b7d5e03cSMatthew Dillon 600b7d5e03cSMatthew Dillon /* MAC ChannelTime settings */ 601b7d5e03cSMatthew Dillon #define AR_D0_CHNTIME AR_MAC_DCU_OFFSET(MAC_DCU_CHANNEL_TIME) 602b7d5e03cSMatthew Dillon #define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) 603b7d5e03cSMatthew Dillon #define AR_D_CHNTIME_DUR 0x000FFFFF // Mask for ChannelTime duration (us) 604b7d5e03cSMatthew Dillon #define AR_D_CHNTIME_DUR_S 0 // Shift for ChannelTime duration (us) 605b7d5e03cSMatthew Dillon #define AR_D_CHNTIME_EN 0x00100000 // ChannelTime enable 606b7d5e03cSMatthew Dillon #define AR_D_CHNTIME_RESV0 0xFFE00000 // Reserved 607b7d5e03cSMatthew Dillon 608b7d5e03cSMatthew Dillon /* MAC DCU-global IFS settings: Miscellaneous */ 609b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_MISC AR_MAC_DCU_OFFSET(MAC_DCU_GBL_IFS_MISC) 610b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 // Mask forLFSR slice select 611b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 // Turbo mode indication 612b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 // Mask for DCU arbiter delay 613b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 // Random LSFR slice disable 614b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 // Slot transmission window length mask 615b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 // Force transmission on slot boundaries 616b7d5e03cSMatthew Dillon #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 // Ignore backoff 617b7d5e03cSMatthew Dillon 618b7d5e03cSMatthew Dillon /* MAC Miscellaneous DCU-specific settings */ 619b7d5e03cSMatthew Dillon #define AR_D0_MISC AR_MAC_DCU_OFFSET(MAC_DCU_MISC) 620b7d5e03cSMatthew Dillon #define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) 621b7d5e03cSMatthew Dillon #define AR_D_MISC_BKOFF_THRESH 0x0000003F // Mask for Backoff threshold setting 622b7d5e03cSMatthew Dillon #define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 // End of tx series station RTS/data failure count reset policy 623b7d5e03cSMatthew Dillon #define AR_D_MISC_CW_RESET_EN 0x00000080 // End of tx series CW reset enable 624b7d5e03cSMatthew Dillon #define AR_D_MISC_FRAG_WAIT_EN 0x00000100 // Fragment Starvation Policy 625b7d5e03cSMatthew Dillon #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 // Backoff during a frag burst 626b7d5e03cSMatthew Dillon #define AR_D_MISC_CW_BKOFF_EN 0x00001000 // Use binary exponential CW backoff 627b7d5e03cSMatthew Dillon #define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 // Mask for Virtual collision handling policy 628b7d5e03cSMatthew Dillon #define AR_D_MISC_VIR_COL_HANDLING_S 14 // Shift for Virtual collision handling policy 629b7d5e03cSMatthew Dillon #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 // Normal 630b7d5e03cSMatthew Dillon #define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 // Ignore 631b7d5e03cSMatthew Dillon #define AR_D_MISC_BEACON_USE 0x00010000 // Beacon use indication 632b7d5e03cSMatthew Dillon #define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 // Mask for DCU arbiter lockout control 633b7d5e03cSMatthew Dillon #define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 // Shift for DCU arbiter lockout control 634b7d5e03cSMatthew Dillon #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 // No lockout 635b7d5e03cSMatthew Dillon #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 // Intra-frame 636b7d5e03cSMatthew Dillon #define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 // Global 637b7d5e03cSMatthew Dillon #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 // DCU arbiter lockout ignore control 638b7d5e03cSMatthew Dillon #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 // Sequence number increment disable 639b7d5e03cSMatthew Dillon #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 // Post-frame backoff disable 640b7d5e03cSMatthew Dillon #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 // Virtual coll. handling policy 641b7d5e03cSMatthew Dillon #define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 // Initiate Retry procedure on Blown IFS 642b7d5e03cSMatthew Dillon #define AR_D_MISC_RESV0 0xFF000000 // Reserved 643b7d5e03cSMatthew Dillon 644b7d5e03cSMatthew Dillon /* MAC Frame sequence number control/status */ 645b7d5e03cSMatthew Dillon #define AR_D_SEQNUM AR_MAC_DCU_OFFSET(MAC_DCU_SEQ) 646b7d5e03cSMatthew Dillon 647b7d5e03cSMatthew Dillon /* MAC DCU transmit pause control/status */ 648b7d5e03cSMatthew Dillon #define AR_D_TXPSE AR_MAC_DCU_OFFSET(MAC_DCU_PAUSE) 649b7d5e03cSMatthew Dillon #define AR_D_TXPSE_CTRL 0x000003FF // Mask of DCUs to pause (DCUs 0-9) 650b7d5e03cSMatthew Dillon #define AR_D_TXPSE_RESV0 0x0000FC00 // Reserved 651b7d5e03cSMatthew Dillon #define AR_D_TXPSE_STATUS 0x00010000 // Transmit pause status 652b7d5e03cSMatthew Dillon #define AR_D_TXPSE_RESV1 0xFFFE0000 // Reserved 653b7d5e03cSMatthew Dillon 654b7d5e03cSMatthew Dillon /* MAC DCU WOW Keep-Alive Config register */ 655b7d5e03cSMatthew Dillon #define AR_D_WOW_KACFG AR_MAC_DCU_OFFSET(MAC_DCU_WOW_KACFG) 656b7d5e03cSMatthew Dillon 657b7d5e03cSMatthew Dillon /* MAC DCU transmission slot mask */ 658b7d5e03cSMatthew Dillon #define AR_D_TXSLOTMASK AR_MAC_DCU_OFFSET(MAC_DCU_TXSLOT) 659b7d5e03cSMatthew Dillon #define AR_D_TXSLOTMASK_NUM 0x0000000F // slot numbers 660b7d5e03cSMatthew Dillon 661b7d5e03cSMatthew Dillon /* MAC DCU-specific IFS settings */ 662b7d5e03cSMatthew Dillon #define AR_D0_LCL_IFS AR_MAC_DCU_OFFSET(MAC_DCU_LCL_IFS) 663b7d5e03cSMatthew Dillon #define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) 664b7d5e03cSMatthew Dillon #define AR_D9_LCL_IFS AR_DLCL_IFS(9) 665b7d5e03cSMatthew Dillon #define AR_D_LCL_IFS_CWMIN 0x000003FF // Mask for CW_MIN 666b7d5e03cSMatthew Dillon #define AR_D_LCL_IFS_CWMIN_S 0 // Shift for CW_MIN 667b7d5e03cSMatthew Dillon #define AR_D_LCL_IFS_CWMAX 0x000FFC00 // Mask for CW_MAX 668b7d5e03cSMatthew Dillon #define AR_D_LCL_IFS_CWMAX_S 10 // Shift for CW_MAX 669b7d5e03cSMatthew Dillon #define AR_D_LCL_IFS_AIFS 0x0FF00000 // Mask for AIFS 670b7d5e03cSMatthew Dillon #define AR_D_LCL_IFS_AIFS_S 20 // Shift for AIFS 671b7d5e03cSMatthew Dillon /* 672b7d5e03cSMatthew Dillon * Note: even though this field is 8 bits wide the 673b7d5e03cSMatthew Dillon * maximum supported AIFS value is 0xfc. Setting the AIFS value 674b7d5e03cSMatthew Dillon * to 0xfd 0xfe or 0xff will not work correctly and will cause 675b7d5e03cSMatthew Dillon * the DCU to hang. 676b7d5e03cSMatthew Dillon */ 677b7d5e03cSMatthew Dillon #define AR_D_LCL_IFS_RESV0 0xF0000000 // Reserved 678b7d5e03cSMatthew Dillon 679b7d5e03cSMatthew Dillon 680b7d5e03cSMatthew Dillon #define AR_CFG_LED 0x1f04 /* LED control */ 681b7d5e03cSMatthew Dillon #define AR_CFG_SCLK_RATE_IND 0x00000003 /* sleep clock indication */ 682b7d5e03cSMatthew Dillon #define AR_CFG_SCLK_RATE_IND_S 0 683b7d5e03cSMatthew Dillon #define AR_CFG_SCLK_32MHZ 0x00000000 /* Sleep clock rate */ 684b7d5e03cSMatthew Dillon #define AR_CFG_SCLK_4MHZ 0x00000001 /* Sleep clock rate */ 685b7d5e03cSMatthew Dillon #define AR_CFG_SCLK_1MHZ 0x00000002 /* Sleep clock rate */ 686b7d5e03cSMatthew Dillon #define AR_CFG_SCLK_32KHZ 0x00000003 /* Sleep clock rate */ 687b7d5e03cSMatthew Dillon #define AR_CFG_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ 688b7d5e03cSMatthew Dillon #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ 689b7d5e03cSMatthew Dillon #define AR_CFG_LED_MODE_SEL 0x00000380 /* LED mode: bits 7..9 */ 690b7d5e03cSMatthew Dillon #define AR_CFG_LED_MODE_SEL_S 7 /* LED mode: bits 7..9 */ 691b7d5e03cSMatthew Dillon #define AR_CFG_LED_POWER 0x00000280 /* Power LED: bit 9=1, bit 7=<LED State> */ 692b7d5e03cSMatthew Dillon #define AR_CFG_LED_POWER_S 7 /* LED mode: bits 7..9 */ 693b7d5e03cSMatthew Dillon #define AR_CFG_LED_NETWORK 0x00000300 /* Network LED: bit 9=1, bit 8=<LED State> */ 694b7d5e03cSMatthew Dillon #define AR_CFG_LED_NETWORK_S 7 /* LED mode: bits 7..9 */ 695b7d5e03cSMatthew Dillon #define AR_CFG_LED_MODE_PROP 0x0 /* Blink prop to filtered tx/rx */ 696b7d5e03cSMatthew Dillon #define AR_CFG_LED_MODE_RPROP 0x1 /* Blink prop to unfiltered tx/rx */ 697b7d5e03cSMatthew Dillon #define AR_CFG_LED_MODE_SPLIT 0x2 /* Blink power for tx/net for rx */ 698b7d5e03cSMatthew Dillon #define AR_CFG_LED_MODE_RAND 0x3 /* Blink randomly */ 699b7d5e03cSMatthew Dillon #define AR_CFG_LED_MODE_POWER_OFF 0x4 /* Power LED OFF */ 700b7d5e03cSMatthew Dillon #define AR_CFG_LED_MODE_POWER_ON 0x5 /* Power LED ON */ 701b7d5e03cSMatthew Dillon #define AR_CFG_LED_MODE_NETWORK_OFF 0x4 /* Network LED OFF */ 702b7d5e03cSMatthew Dillon #define AR_CFG_LED_MODE_NETWORK_ON 0x6 /* Network LED ON */ 703b7d5e03cSMatthew Dillon #define AR_CFG_LED_ASSOC_CTL 0x00000c00 /* LED control: bits 10..11 */ 704b7d5e03cSMatthew Dillon #define AR_CFG_LED_ASSOC_CTL_S 10 /* LED control: bits 10..11 */ 705b7d5e03cSMatthew Dillon #define AR_CFG_LED_ASSOC_NONE 0x0 /* 0x00000000: STA is not associated or trying */ 706b7d5e03cSMatthew Dillon #define AR_CFG_LED_ASSOC_ACTIVE 0x1 /* 0x00000400: STA is associated */ 707b7d5e03cSMatthew Dillon #define AR_CFG_LED_ASSOC_PENDING 0x2 /* 0x00000800: STA is trying to associate */ 708b7d5e03cSMatthew Dillon 709b7d5e03cSMatthew Dillon #define AR_CFG_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode: bit 3 */ 710b7d5e03cSMatthew Dillon #define AR_CFG_LED_BLINK_SLOW_S 3 /* LED slowest blink rate mode: bit 3 */ 711b7d5e03cSMatthew Dillon 712b7d5e03cSMatthew Dillon #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select: bits 4..6 */ 713b7d5e03cSMatthew Dillon #define AR_CFG_LED_BLINK_THRESH_SEL_S 4 /* LED blink threshold select: bits 4..6 */ 714b7d5e03cSMatthew Dillon 715b7d5e03cSMatthew Dillon #define AR_MAC_SLEEP 0x1f00 716b7d5e03cSMatthew Dillon #define AR_MAC_SLEEP_MAC_AWAKE 0x00000000 // mac is now awake 717b7d5e03cSMatthew Dillon #define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 // mac is now asleep 718b7d5e03cSMatthew Dillon 719b7d5e03cSMatthew Dillon 720b7d5e03cSMatthew Dillon 721b7d5e03cSMatthew Dillon /****************************************************************************** 722b7d5e03cSMatthew Dillon * Host Interface Register Map 723b7d5e03cSMatthew Dillon ******************************************************************************/ 724b7d5e03cSMatthew Dillon // DMA & PCI Registers in PCI space (usable during sleep) 725b7d5e03cSMatthew Dillon 726b7d5e03cSMatthew Dillon #define AR_HOSTIF_REG(_ah, _reg) (AH9300(_ah)->ah_hostifregs._reg) 727b7d5e03cSMatthew Dillon #define AR9300_HOSTIF_OFFSET(_x) offsetof(struct host_intf_reg, _x) 728b7d5e03cSMatthew Dillon #define AR9340_HOSTIF_OFFSET(_x) offsetof(struct host_intf_reg_ar9340, _x) 729b7d5e03cSMatthew Dillon 730b7d5e03cSMatthew Dillon /* Interface Reset Control Register */ 731b7d5e03cSMatthew Dillon #define AR_RC_AHB 0x00000001 // ahb reset 732b7d5e03cSMatthew Dillon #define AR_RC_APB 0x00000002 // apb reset 733b7d5e03cSMatthew Dillon #define AR_RC_HOSTIF 0x00000100 // host interface reset 734b7d5e03cSMatthew Dillon 735b7d5e03cSMatthew Dillon /* PCI express work-arounds */ 736b7d5e03cSMatthew Dillon #define AR_WA_D3_TO_L1_DISABLE (1 << 14) 737b7d5e03cSMatthew Dillon #define AR_WA_UNTIE_RESET_EN (1 << 15) /* Enable PCI Reset to POR (power-on-reset) */ 738b7d5e03cSMatthew Dillon #define AR_WA_D3_TO_L1_DISABLE_REAL (1 << 16) 739b7d5e03cSMatthew Dillon #define AR_WA_ASPM_TIMER_BASED_DISABLE (1 << 17) 740b7d5e03cSMatthew Dillon #define AR_WA_RESET_EN (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */ 741b7d5e03cSMatthew Dillon #define AR_WA_ANALOG_SHIFT (1 << 20) 742b7d5e03cSMatthew Dillon #define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */ 743b7d5e03cSMatthew Dillon #define AR_WA_COLD_RESET_OVERRIDE (1 << 13) /* PCI-E Cold reset override */ 744b7d5e03cSMatthew Dillon 745b7d5e03cSMatthew Dillon /* power management state */ 746b7d5e03cSMatthew Dillon #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 //for wow 747b7d5e03cSMatthew Dillon 748b7d5e03cSMatthew Dillon /* CXPL Debug signals which help debug Link Negotiation */ 749b7d5e03cSMatthew Dillon /* CXPL Debug signals which help debug Link Negotiation */ 750b7d5e03cSMatthew Dillon 751b7d5e03cSMatthew Dillon /* XXX check bit feilds */ 752b7d5e03cSMatthew Dillon /* Power Management Control Register */ 753b7d5e03cSMatthew Dillon #define AR_PCIE_PM_CTRL_ENA 0x00080000 754b7d5e03cSMatthew Dillon #define AR_PMCTRL_WOW_PME_CLR 0x00200000 /* Clear WoW event */ 755b7d5e03cSMatthew Dillon #define AR_PMCTRL_HOST_PME_EN 0x00400000 /* Send OOB WAKE_L on WoW event */ 756b7d5e03cSMatthew Dillon #define AR_PMCTRL_D3COLD_VAUX 0x00800000 757b7d5e03cSMatthew Dillon #define AR_PMCTRL_PWR_STATE_MASK 0x0F000000 /* Power State Mask */ 758b7d5e03cSMatthew Dillon #define AR_PMCTRL_PWR_STATE_D1D3 0x0F000000 /* Activate D1 and D3 */ 759b7d5e03cSMatthew Dillon #define AR_PMCTRL_PWR_STATE_D0 0x08000000 /* Activate D0 */ 760b7d5e03cSMatthew Dillon #define AR_PMCTRL_PWR_PM_CTRL_ENA 0x00008000 /* Enable power management */ 761b7d5e03cSMatthew Dillon #define AR_PMCTRL_AUX_PWR_DET 0x10000000 /* Puts Chip in L2 state */ 762b7d5e03cSMatthew Dillon 763b7d5e03cSMatthew Dillon 764b7d5e03cSMatthew Dillon 765b7d5e03cSMatthew Dillon /* APB and Local Bus Timeout Counters */ 766b7d5e03cSMatthew Dillon #define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF 767b7d5e03cSMatthew Dillon #define AR_HOST_TIMEOUT_APB_CNTR_S 0 768b7d5e03cSMatthew Dillon #define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000 769b7d5e03cSMatthew Dillon #define AR_HOST_TIMEOUT_LCL_CNTR_S 16 770b7d5e03cSMatthew Dillon 771b7d5e03cSMatthew Dillon /* EEPROM Control Register */ 772b7d5e03cSMatthew Dillon #define AR_EEPROM_ABSENT 0x00000100 773b7d5e03cSMatthew Dillon #define AR_EEPROM_CORRUPT 0x00000200 774b7d5e03cSMatthew Dillon #define AR_EEPROM_PROT_MASK 0x03FFFC00 775b7d5e03cSMatthew Dillon #define AR_EEPROM_PROT_MASK_S 10 776b7d5e03cSMatthew Dillon 777b7d5e03cSMatthew Dillon // Protect Bits RP is read protect WP is write protect 778b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_RP_0_31 0x0001 779b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_WP_0_31 0x0002 780b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_RP_32_63 0x0004 781b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_WP_32_63 0x0008 782b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_RP_64_127 0x0010 783b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_WP_64_127 0x0020 784b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_RP_128_191 0x0040 785b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_WP_128_191 0x0080 786b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_RP_192_255 0x0100 787b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_WP_192_255 0x0200 788b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_RP_256_511 0x0400 789b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_WP_256_511 0x0800 790b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_RP_512_1023 0x1000 791b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_WP_512_1023 0x2000 792b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_RP_1024_2047 0x4000 793b7d5e03cSMatthew Dillon #define EEPROM_PROTECT_WP_1024_2047 0x8000 794b7d5e03cSMatthew Dillon 795b7d5e03cSMatthew Dillon /* RF silent */ 796b7d5e03cSMatthew Dillon #define AR_RFSILENT_FORCE 0x01 797b7d5e03cSMatthew Dillon 798b7d5e03cSMatthew Dillon /* MAC silicon Rev ID */ 799b7d5e03cSMatthew Dillon #define AR_SREV_ID 0x000000FF /* Mask to read SREV info */ 800b7d5e03cSMatthew Dillon #define AR_SREV_VERSION 0x000000F0 /* Mask for Chip version */ 801b7d5e03cSMatthew Dillon #define AR_SREV_VERSION_S 4 /* Mask to shift Major Rev Info */ 802b7d5e03cSMatthew Dillon #define AR_SREV_REVISION 0x00000007 /* Mask for Chip revision level */ 803b7d5e03cSMatthew Dillon 804b7d5e03cSMatthew Dillon /* Sowl extension to SREV. AR_SREV_ID must be 0xFF */ 805b7d5e03cSMatthew Dillon #define AR_SREV_ID2 0xFFFFFFFF /* Mask to read SREV info */ 806b7d5e03cSMatthew Dillon #define AR_SREV_VERSION2 0xFFFC0000 /* Mask for Chip version */ 807b7d5e03cSMatthew Dillon #define AR_SREV_VERSION2_S 18 /* Mask to shift Major Rev Info */ 808b7d5e03cSMatthew Dillon #define AR_SREV_TYPE2 0x0003F000 /* Mask for Chip type */ 809b7d5e03cSMatthew Dillon #define AR_SREV_TYPE2_S 12 /* Mask to shift Major Rev Info */ 810b7d5e03cSMatthew Dillon #define AR_SREV_TYPE2_CHAIN 0x00001000 /* chain mode (1 = 3 chains, 0 = 2 chains) */ 811b7d5e03cSMatthew Dillon #define AR_SREV_TYPE2_HOST_MODE 0x00002000 /* host mode (1 = PCI, 0 = PCIe) */ 812b7d5e03cSMatthew Dillon /* Jupiter has a different TYPE2 definition. */ 813b7d5e03cSMatthew Dillon #define AR_SREV_TYPE2_JUPITER_CHAIN 0x00001000 /* chain (1 = 2 chains, 0 = 1 chain) */ 814b7d5e03cSMatthew Dillon #define AR_SREV_TYPE2_JUPITER_BAND 0x00002000 /* band (1 = dual band, 0 = single band) */ 815b7d5e03cSMatthew Dillon #define AR_SREV_TYPE2_JUPITER_BT 0x00004000 /* BT (1 = shared BT, 0 = no BT) */ 816b7d5e03cSMatthew Dillon #define AR_SREV_TYPE2_JUPITER_MODE 0x00008000 /* mode (1 = premium, 0 = standard) */ 817b7d5e03cSMatthew Dillon #define AR_SREV_REVISION2 0x00000F00 818b7d5e03cSMatthew Dillon #define AR_SREV_REVISION2_S 8 819b7d5e03cSMatthew Dillon 820b7d5e03cSMatthew Dillon #define AR_RADIO_SREV_MAJOR 0xf0 821b7d5e03cSMatthew Dillon #define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ 822b7d5e03cSMatthew Dillon #define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ 823b7d5e03cSMatthew Dillon #define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ 824b7d5e03cSMatthew Dillon #define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ 825b7d5e03cSMatthew Dillon 826b7d5e03cSMatthew Dillon #if 0 827b7d5e03cSMatthew Dillon #define AR_AHB_MODE 0x4024 // ahb mode for dma 828b7d5e03cSMatthew Dillon #define AR_AHB_EXACT_WR_EN 0x00000000 // write exact bytes 829b7d5e03cSMatthew Dillon #define AR_AHB_BUF_WR_EN 0x00000001 // buffer write upto cacheline 830b7d5e03cSMatthew Dillon #define AR_AHB_EXACT_RD_EN 0x00000000 // read exact bytes 831b7d5e03cSMatthew Dillon #define AR_AHB_CACHELINE_RD_EN 0x00000002 // read upto end of cacheline 832b7d5e03cSMatthew Dillon #define AR_AHB_PREFETCH_RD_EN 0x00000004 // prefetch upto page boundary 833b7d5e03cSMatthew Dillon #define AR_AHB_PAGE_SIZE_1K 0x00000000 // set page-size as 1k 834b7d5e03cSMatthew Dillon #define AR_AHB_PAGE_SIZE_2K 0x00000008 // set page-size as 2k 835b7d5e03cSMatthew Dillon #define AR_AHB_PAGE_SIZE_4K 0x00000010 // set page-size as 4k 836b7d5e03cSMatthew Dillon #endif 837b7d5e03cSMatthew Dillon 838b7d5e03cSMatthew Dillon #define AR_INTR_RTC_IRQ 0x00000001 // rtc in shutdown state 839b7d5e03cSMatthew Dillon #define AR_INTR_MAC_IRQ 0x00000002 // pending mac interrupt 840b7d5e03cSMatthew Dillon #if 0 841b7d5e03cSMatthew Dillon /* 842b7d5e03cSMatthew Dillon * the following definitions might be differents for WASP so 843b7d5e03cSMatthew Dillon * disable them to avoid improper use 844b7d5e03cSMatthew Dillon */ 845b7d5e03cSMatthew Dillon #define AR_INTR_EEP_PROT_ACCESS 0x00000004 // eeprom protected area access 846b7d5e03cSMatthew Dillon #define AR_INTR_MAC_AWAKE 0x00020000 // mac is awake 847b7d5e03cSMatthew Dillon #define AR_INTR_MAC_ASLEEP 0x00040000 // mac is asleep 848b7d5e03cSMatthew Dillon #endif 849b7d5e03cSMatthew Dillon #define AR_INTR_SPURIOUS 0xFFFFFFFF 850b7d5e03cSMatthew Dillon 851b7d5e03cSMatthew Dillon /* TODO: fill in other values */ 852b7d5e03cSMatthew Dillon 853b7d5e03cSMatthew Dillon /* Synchronous Interrupt Cause Register */ 854b7d5e03cSMatthew Dillon 855b7d5e03cSMatthew Dillon /* Synchronous Interrupt Enable Register */ 856b7d5e03cSMatthew Dillon #define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 // enable interrupts: bits 18..31 857b7d5e03cSMatthew Dillon #define AR_INTR_SYNC_ENABLE_GPIO_S 18 // enable interrupts: bits 18..31 858b7d5e03cSMatthew Dillon 859b7d5e03cSMatthew Dillon /* 860b7d5e03cSMatthew Dillon * synchronous interrupt signals 861b7d5e03cSMatthew Dillon */ 862b7d5e03cSMatthew Dillon enum { 863b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_RTC_IRQ = 0x00000001, 864b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_MAC_IRQ = 0x00000002, 865b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004, 866b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_APB_TIMEOUT = 0x00000008, 867b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010, 868b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_HOST1_FATAL = 0x00000020, 869b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_HOST1_PERR = 0x00000040, 870b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080, 871b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_RADM_CPL_EP = 0x00000100, 872b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200, 873b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400, 874b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800, 875b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000, 876b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000, 877b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_PM_ACCESS = 0x00004000, 878b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_MAC_AWAKE = 0x00008000, 879b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_MAC_ASLEEP = 0x00010000, 880b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000, 881b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_ALL = 0x0003FFFF, 882b7d5e03cSMatthew Dillon 883b7d5e03cSMatthew Dillon /* 884b7d5e03cSMatthew Dillon * Do not enable and turn on mask for both sync and async interrupt, since 885b7d5e03cSMatthew Dillon * chip can generate interrupt storm. 886b7d5e03cSMatthew Dillon */ 887b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_DEF_NO_HOST1_PERR = (AR9300_INTR_SYNC_HOST1_FATAL | 888b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_RADM_CPL_EP | 889b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_RADM_CPL_DLLP_ABORT | 890b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_RADM_CPL_TLP_ABORT | 891b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_RADM_CPL_ECRC_ERR | 892b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_RADM_CPL_TIMEOUT | 893b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_LOCAL_TIMEOUT | 894b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_MAC_SLEEP_ACCESS), 895b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_DEFAULT = (AR9300_INTR_SYNC_DEF_NO_HOST1_PERR | 896b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_HOST1_PERR), 897b7d5e03cSMatthew Dillon 898b7d5e03cSMatthew Dillon AR9300_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, 899b7d5e03cSMatthew Dillon 900b7d5e03cSMatthew Dillon /* WASP */ 901b7d5e03cSMatthew Dillon AR9340_INTR_SYNC_RTC_IRQ = 0x00000001, 902b7d5e03cSMatthew Dillon AR9340_INTR_SYNC_MAC_IRQ = 0x00000002, 903b7d5e03cSMatthew Dillon AR9340_INTR_SYNC_HOST1_FATAL = 0x00000004, 904b7d5e03cSMatthew Dillon AR9340_INTR_SYNC_HOST1_PERR = 0x00000008, 905b7d5e03cSMatthew Dillon AR9340_INTR_SYNC_LOCAL_TIMEOUT = 0x00000010, 906b7d5e03cSMatthew Dillon AR9340_INTR_SYNC_MAC_ASLEEP = 0x00000020, 907b7d5e03cSMatthew Dillon AR9340_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00000040, 908b7d5e03cSMatthew Dillon 909b7d5e03cSMatthew Dillon AR9340_INTR_SYNC_DEFAULT = (AR9340_INTR_SYNC_HOST1_FATAL | 910b7d5e03cSMatthew Dillon AR9340_INTR_SYNC_HOST1_PERR | 911b7d5e03cSMatthew Dillon AR9340_INTR_SYNC_LOCAL_TIMEOUT | 912b7d5e03cSMatthew Dillon AR9340_INTR_SYNC_MAC_SLEEP_ACCESS), 913b7d5e03cSMatthew Dillon 914b7d5e03cSMatthew Dillon AR9340_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, 915b7d5e03cSMatthew Dillon }; 916b7d5e03cSMatthew Dillon 917b7d5e03cSMatthew Dillon /* Asynchronous Interrupt Mask Register */ 918b7d5e03cSMatthew Dillon #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 // asynchronous interrupt mask: bits 18..31 919b7d5e03cSMatthew Dillon #define AR_INTR_ASYNC_MASK_GPIO_S 18 // asynchronous interrupt mask: bits 18..31 920b7d5e03cSMatthew Dillon #define AR_INTR_ASYNC_MASK_MCI 0x00000080 921b7d5e03cSMatthew Dillon #define AR_INTR_ASYNC_MASK_MCI_S 7 922b7d5e03cSMatthew Dillon 923b7d5e03cSMatthew Dillon /* Synchronous Interrupt Mask Register */ 924b7d5e03cSMatthew Dillon #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 // synchronous interrupt mask: bits 18..31 925b7d5e03cSMatthew Dillon #define AR_INTR_SYNC_MASK_GPIO_S 18 // synchronous interrupt mask: bits 18..31 926b7d5e03cSMatthew Dillon 927b7d5e03cSMatthew Dillon /* Asynchronous Interrupt Cause Register */ 928b7d5e03cSMatthew Dillon #define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 // GPIO interrupts: bits 18..31 929b7d5e03cSMatthew Dillon #define AR_INTR_ASYNC_CAUSE_MCI 0x00000080 930b7d5e03cSMatthew Dillon #define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO | AR_INTR_ASYNC_CAUSE_MCI) 931b7d5e03cSMatthew Dillon 932b7d5e03cSMatthew Dillon /* Asynchronous Interrupt Enable Register */ 933b7d5e03cSMatthew Dillon #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 // enable interrupts: bits 18..31 934b7d5e03cSMatthew Dillon #define AR_INTR_ASYNC_ENABLE_GPIO_S 18 // enable interrupts: bits 18..31 935b7d5e03cSMatthew Dillon #define AR_INTR_ASYNC_ENABLE_MCI 0x00000080 936b7d5e03cSMatthew Dillon #define AR_INTR_ASYNC_ENABLE_MCI_S 7 937b7d5e03cSMatthew Dillon 938b7d5e03cSMatthew Dillon /* PCIE PHY Data Register */ 939b7d5e03cSMatthew Dillon 940b7d5e03cSMatthew Dillon /* PCIE PHY Load Register */ 941b7d5e03cSMatthew Dillon #define AR_PCIE_PM_CTRL_ENA 0x00080000 942b7d5e03cSMatthew Dillon 943b7d5e03cSMatthew Dillon #define AR93XX_NUM_GPIO 16 // 0 to 15 944b7d5e03cSMatthew Dillon 945b7d5e03cSMatthew Dillon /* GPIO Output Register */ 946b7d5e03cSMatthew Dillon #define AR_GPIO_OUT_VAL 0x000FFFF 947b7d5e03cSMatthew Dillon #define AR_GPIO_OUT_VAL_S 0 948b7d5e03cSMatthew Dillon 949b7d5e03cSMatthew Dillon /* GPIO Input Register */ 950b7d5e03cSMatthew Dillon #define AR_GPIO_IN_VAL 0x000FFFF 951b7d5e03cSMatthew Dillon #define AR_GPIO_IN_VAL_S 0 952b7d5e03cSMatthew Dillon 953b7d5e03cSMatthew Dillon /* Host GPIO output enable bits */ 954b7d5e03cSMatthew Dillon #define AR_GPIO_OE_OUT_DRV 0x3 // 2 bit field mask, shifted by 2*bitpos 955b7d5e03cSMatthew Dillon #define AR_GPIO_OE_OUT_DRV_NO 0x0 // tristate 956b7d5e03cSMatthew Dillon #define AR_GPIO_OE_OUT_DRV_LOW 0x1 // drive if low 957b7d5e03cSMatthew Dillon #define AR_GPIO_OE_OUT_DRV_HI 0x2 // drive if high 958b7d5e03cSMatthew Dillon #define AR_GPIO_OE_OUT_DRV_ALL 0x3 // drive always 959b7d5e03cSMatthew Dillon 960b7d5e03cSMatthew Dillon /* Host GPIO output enable bits */ 961b7d5e03cSMatthew Dillon 962b7d5e03cSMatthew Dillon /* Host GPIO Interrupt Polarity */ 963b7d5e03cSMatthew Dillon #define AR_GPIO_INTR_POL_VAL 0x0001FFFF // bits 16:0 correspond to gpio 16:0 964b7d5e03cSMatthew Dillon #define AR_GPIO_INTR_POL_VAL_S 0 // bits 16:0 correspond to gpio 16:0 965b7d5e03cSMatthew Dillon 966b7d5e03cSMatthew Dillon /* Host GPIO Input Value */ 967b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 // default value for bt_priority_async 968b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 969b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 // default value for bt_frequency_async 970b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3 971b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 // default value for bt_active_async 972b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 973b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 // default value for rfsilent_bb_l 974b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 975b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 // 0 == set bt_priority_async to default, 1 == connect bt_prority_async to baseband 976b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10 977b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB 0x00000800 // 0 == set bt_frequency_async to default, 1 == connect bt_frequency_async to baseband 978b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB_S 11 979b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 // 0 == set bt_active_async to default, 1 == connect bt_active_async to baseband 980b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 981b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 // 0 == set rfsilent_bb_l to default, 1 == connect rfsilent_bb_l to baseband 982b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 983b7d5e03cSMatthew Dillon #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 984b7d5e03cSMatthew Dillon #define AR_GPIO_JTAG_DISABLE 0x00020000 // 1 == disable JTAG 985b7d5e03cSMatthew Dillon 986b7d5e03cSMatthew Dillon /* GPIO Input Mux1 */ 987b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 /* bits 8..11: input mux for BT priority input */ 988b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 /* bits 8..11: input mux for BT priority input */ 989b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_MUX1_BT_FREQUENCY 0x0000f000 /* bits 12..15: input mux for BT frequency input */ 990b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_MUX1_BT_FREQUENCY_S 12 /* bits 12..15: input mux for BT frequency input */ 991b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 /* bits 16..19: input mux for BT active input */ 992b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 /* bits 16..19: input mux for BT active input */ 993b7d5e03cSMatthew Dillon 994b7d5e03cSMatthew Dillon /* GPIO Input Mux2 */ 995b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f // bits 0..3: input mux for clk25 input 996b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_MUX2_CLK25_S 0 // bits 0..3: input mux for clk25 input 997b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 // bits 4..7: input mux for rfsilent_bb_l input 998b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 // bits 4..7: input mux for rfsilent_bb_l input 999b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 // bits 8..11: input mux for RTC Reset input 1000b7d5e03cSMatthew Dillon #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 // bits 8..11: input mux for RTC Reset input 1001b7d5e03cSMatthew Dillon 1002b7d5e03cSMatthew Dillon /* GPIO Output Mux1 */ 1003b7d5e03cSMatthew Dillon /* GPIO Output Mux2 */ 1004b7d5e03cSMatthew Dillon /* GPIO Output Mux3 */ 1005b7d5e03cSMatthew Dillon 1006b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 1007b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 1008b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 1009b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 1010b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 1011b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 1012b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 1013b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 1014b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 1015b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 1016b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 1017b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 1018b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 1019b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 1020b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 1021b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d 1022b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e 1023b7d5e03cSMatthew Dillon 1024b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0 0x1d 1025b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1 0x1e 1026b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2 0x1b 1027b7d5e03cSMatthew Dillon /* The above three seems to be functional values for peacock chip. For some 1028b7d5e03cSMatthew Dillon * reason these are continued for different boards as simple place holders. 1029b7d5e03cSMatthew Dillon * Now continuing to use these and adding the extra definitions for Scropion 1030b7d5e03cSMatthew Dillon */ 1031b7d5e03cSMatthew Dillon #define AR_GPIO_OUTPUT_MUX_AS_SWCOM3 0x26 1032b7d5e03cSMatthew Dillon 1033b7d5e03cSMatthew Dillon #define AR_ENABLE_SMARTANTENNA 0x00000001 1034b7d5e03cSMatthew Dillon 1035b7d5e03cSMatthew Dillon /* Host GPIO Input State */ 1036b7d5e03cSMatthew Dillon 1037b7d5e03cSMatthew Dillon /* Host Spare */ 1038b7d5e03cSMatthew Dillon 1039b7d5e03cSMatthew Dillon /* Host PCIE Core Reset Enable */ 1040b7d5e03cSMatthew Dillon 1041b7d5e03cSMatthew Dillon /* Host CLKRUN */ 1042b7d5e03cSMatthew Dillon 1043b7d5e03cSMatthew Dillon 1044b7d5e03cSMatthew Dillon /* Host EEPROM Status */ 1045b7d5e03cSMatthew Dillon #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 1046b7d5e03cSMatthew Dillon #define AR_EEPROM_STATUS_DATA_VAL_S 0 1047b7d5e03cSMatthew Dillon #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 1048b7d5e03cSMatthew Dillon #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 1049b7d5e03cSMatthew Dillon #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 1050b7d5e03cSMatthew Dillon #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 1051b7d5e03cSMatthew Dillon 1052b7d5e03cSMatthew Dillon /* Host Observation Control */ 1053b7d5e03cSMatthew Dillon 1054b7d5e03cSMatthew Dillon /* Host RF Silent */ 1055b7d5e03cSMatthew Dillon 1056b7d5e03cSMatthew Dillon /* Host GPIO PDPU */ 1057b7d5e03cSMatthew Dillon #define AR_GPIO_PDPU_OPTION 0x03 1058b7d5e03cSMatthew Dillon #define AR_GPIO_PULL_DOWN 0x02 1059b7d5e03cSMatthew Dillon 1060b7d5e03cSMatthew Dillon /* Host GPIO Drive Strength */ 1061b7d5e03cSMatthew Dillon 1062b7d5e03cSMatthew Dillon /* Host Miscellaneous */ 1063b7d5e03cSMatthew Dillon 1064b7d5e03cSMatthew Dillon /* Host PCIE MSI Control Register */ 1065b7d5e03cSMatthew Dillon #define AR_PCIE_MSI_ENABLE 0x00000001 1066b7d5e03cSMatthew Dillon #define AR_PCIE_MSI_HW_DBI_WR_EN 0x02000000 1067b7d5e03cSMatthew Dillon #define AR_PCIE_MSI_HW_INT_PENDING_ADDR 0xFFA0C1FF // bits 8..11: value must be 0x5060 1068b7d5e03cSMatthew Dillon #define AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64 0xFFA0C9FF // bits 8..11: value must be 0x5064 1069b7d5e03cSMatthew Dillon 1070b7d5e03cSMatthew Dillon 1071b7d5e03cSMatthew Dillon #define AR_INTR_PRIO_TX 0x00000001 1072b7d5e03cSMatthew Dillon #define AR_INTR_PRIO_RXLP 0x00000002 1073b7d5e03cSMatthew Dillon #define AR_INTR_PRIO_RXHP 0x00000004 1074b7d5e03cSMatthew Dillon 1075b7d5e03cSMatthew Dillon /* OTP Interface Register */ 1076b7d5e03cSMatthew Dillon #define AR_ENT_OTP AR9300_HOSTIF_OFFSET(HOST_INTF_OTP) 1077b7d5e03cSMatthew Dillon 1078b7d5e03cSMatthew Dillon #define AR_ENT_OTP_DUAL_BAND_DISABLE 0x00010000 1079b7d5e03cSMatthew Dillon #define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000 1080b7d5e03cSMatthew Dillon #define AR_ENT_OTP_5MHZ_DISABLE 0x00040000 1081b7d5e03cSMatthew Dillon #define AR_ENT_OTP_10MHZ_DISABLE 0x00080000 1082b7d5e03cSMatthew Dillon #define AR_ENT_OTP_49GHZ_DISABLE 0x00100000 1083b7d5e03cSMatthew Dillon #define AR_ENT_OTP_LOOPBACK_DISABLE 0x00200000 1084b7d5e03cSMatthew Dillon #define AR_ENT_OTP_TPC_PERF_DISABLE 0x00400000 1085b7d5e03cSMatthew Dillon #define AR_ENT_OTP_MIN_PKT_SIZE_DISABLE 0x00800000 1086b7d5e03cSMatthew Dillon #define AR_ENT_OTP_SPECTRAL_PRECISION 0x03000000 1087b7d5e03cSMatthew Dillon 1088b7d5e03cSMatthew Dillon /* OTP EFUSE registers */ 1089b7d5e03cSMatthew Dillon #define AR_OTP_EFUSE_OFFSET(_x) offsetof(struct efuse_reg_WLAN, _x) 1090b7d5e03cSMatthew Dillon #define AR_OTP_EFUSE_INTF0 AR_OTP_EFUSE_OFFSET(OTP_INTF0) 1091b7d5e03cSMatthew Dillon #define AR_OTP_EFUSE_INTF5 AR_OTP_EFUSE_OFFSET(OTP_INTF5) 1092b7d5e03cSMatthew Dillon #define AR_OTP_EFUSE_PGENB_SETUP_HOLD_TIME AR_OTP_EFUSE_OFFSET(OTP_PGENB_SETUP_HOLD_TIME) 1093b7d5e03cSMatthew Dillon #define AR_OTP_EFUSE_MEM AR_OTP_EFUSE_OFFSET(OTP_MEM) 1094b7d5e03cSMatthew Dillon 1095b7d5e03cSMatthew Dillon /****************************************************************************** 1096b7d5e03cSMatthew Dillon * RTC Register Map 1097b7d5e03cSMatthew Dillon ******************************************************************************/ 1098b7d5e03cSMatthew Dillon 1099b7d5e03cSMatthew Dillon #define AR_RTC_OFFSET(_x) offsetof(struct rtc_reg, _x) 1100b7d5e03cSMatthew Dillon 1101b7d5e03cSMatthew Dillon /* Reset Control */ 1102b7d5e03cSMatthew Dillon #define AR_RTC_RC AR_RTC_OFFSET(RESET_CONTROL) 1103b7d5e03cSMatthew Dillon #define AR_RTC_RC_M 0x00000003 1104b7d5e03cSMatthew Dillon #define AR_RTC_RC_MAC_WARM 0x00000001 1105b7d5e03cSMatthew Dillon #define AR_RTC_RC_MAC_COLD 0x00000002 1106b7d5e03cSMatthew Dillon 1107b7d5e03cSMatthew Dillon /* Crystal Control */ 1108b7d5e03cSMatthew Dillon #define AR_RTC_XTAL_CONTROL AR_RTC_OFFSET(XTAL_CONTROL) 1109b7d5e03cSMatthew Dillon 1110b7d5e03cSMatthew Dillon /* Reg Control 0 */ 1111b7d5e03cSMatthew Dillon #define AR_RTC_REG_CONTROL0 AR_RTC_OFFSET(REG_CONTROL0) 1112b7d5e03cSMatthew Dillon 1113b7d5e03cSMatthew Dillon /* Reg Control 1 */ 1114b7d5e03cSMatthew Dillon #define AR_RTC_REG_CONTROL1 AR_RTC_OFFSET(REG_CONTROL1) 1115b7d5e03cSMatthew Dillon #define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001 1116b7d5e03cSMatthew Dillon 1117b7d5e03cSMatthew Dillon /* TCXO Detect */ 1118b7d5e03cSMatthew Dillon #define AR_RTC_TCXO_DETECT AR_RTC_OFFSET(TCXO_DETECT) 1119b7d5e03cSMatthew Dillon 1120b7d5e03cSMatthew Dillon /* Crystal Test */ 1121b7d5e03cSMatthew Dillon #define AR_RTC_XTAL_TEST AR_RTC_OFFSET(XTAL_TEST) 1122b7d5e03cSMatthew Dillon 1123b7d5e03cSMatthew Dillon /* Sets the ADC/DAC clock quadrature */ 1124b7d5e03cSMatthew Dillon #define AR_RTC_QUADRATURE AR_RTC_OFFSET(QUADRATURE) 1125b7d5e03cSMatthew Dillon 1126b7d5e03cSMatthew Dillon /* PLL Control */ 1127b7d5e03cSMatthew Dillon #define AR_RTC_PLL_CONTROL AR_RTC_OFFSET(PLL_CONTROL) 1128b7d5e03cSMatthew Dillon #define AR_RTC_PLL_DIV 0x000003ff 1129b7d5e03cSMatthew Dillon #define AR_RTC_PLL_DIV_S 0 1130b7d5e03cSMatthew Dillon #define AR_RTC_PLL_REFDIV 0x00003C00 1131b7d5e03cSMatthew Dillon #define AR_RTC_PLL_REFDIV_S 10 1132b7d5e03cSMatthew Dillon #define AR_RTC_PLL_CLKSEL 0x0000C000 1133b7d5e03cSMatthew Dillon #define AR_RTC_PLL_CLKSEL_S 14 1134b7d5e03cSMatthew Dillon #define AR_RTC_PLL_BYPASS 0x00010000 1135b7d5e03cSMatthew Dillon #define AR_RTC_PLL_BYPASS_S 16 1136b7d5e03cSMatthew Dillon 1137b7d5e03cSMatthew Dillon 1138b7d5e03cSMatthew Dillon /* PLL Control 2: for Hornet */ 1139b7d5e03cSMatthew Dillon #define AR_RTC_PLL_CONTROL2 AR_RTC_OFFSET(PLL_CONTROL2) 1140b7d5e03cSMatthew Dillon 1141b7d5e03cSMatthew Dillon /* PLL Settle */ 1142b7d5e03cSMatthew Dillon #define AR_RTC_PLL_SETTLE AR_RTC_OFFSET(PLL_SETTLE) 1143b7d5e03cSMatthew Dillon 1144b7d5e03cSMatthew Dillon /* Crystal Settle */ 1145b7d5e03cSMatthew Dillon #define AR_RTC_XTAL_SETTLE AR_RTC_OFFSET(XTAL_SETTLE) 1146b7d5e03cSMatthew Dillon 1147b7d5e03cSMatthew Dillon /* Controls CLK_OUT pin clock speed */ 1148b7d5e03cSMatthew Dillon #define AR_RTC_CLOCK_OUT AR_RTC_OFFSET(CLOCK_OUT) 1149b7d5e03cSMatthew Dillon 1150b7d5e03cSMatthew Dillon /* Forces bias block on at all times */ 1151b7d5e03cSMatthew Dillon #define AR_RTC_BIAS_OVERRIDE AR_RTC_OFFSET(BIAS_OVERRIDE) 1152b7d5e03cSMatthew Dillon 1153b7d5e03cSMatthew Dillon /* System Sleep status bits */ 1154b7d5e03cSMatthew Dillon #define AR_RTC_SYSTEM_SLEEP AR_RTC_OFFSET(SYSTEM_SLEEP) 1155b7d5e03cSMatthew Dillon 1156b7d5e03cSMatthew Dillon /* Controls sleep options for MAC */ 1157b7d5e03cSMatthew Dillon #define AR_RTC_MAC_SLEEP_CONTROL AR_RTC_OFFSET(MAC_SLEEP_CONTROL) 1158b7d5e03cSMatthew Dillon 1159b7d5e03cSMatthew Dillon /* Keep Awake Timer */ 1160b7d5e03cSMatthew Dillon #define AR_RTC_KEEP_AWAKE AR_RTC_OFFSET(KEEP_AWAKE) 1161b7d5e03cSMatthew Dillon 1162b7d5e03cSMatthew Dillon /* Create a 32kHz clock derived from HF */ 1163b7d5e03cSMatthew Dillon #define AR_RTC_DERIVED_RTC_CLK AR_RTC_OFFSET(DERIVED_RTC_CLK) 1164b7d5e03cSMatthew Dillon 1165b7d5e03cSMatthew Dillon 1166b7d5e03cSMatthew Dillon /****************************************************************************** 1167b7d5e03cSMatthew Dillon * RTC SYNC Register Map 1168b7d5e03cSMatthew Dillon ******************************************************************************/ 1169b7d5e03cSMatthew Dillon 1170b7d5e03cSMatthew Dillon #define AR_RTC_SYNC_OFFSET(_x) offsetof(struct rtc_sync_reg, _x) 1171b7d5e03cSMatthew Dillon 1172b7d5e03cSMatthew Dillon /* reset RTC */ 1173b7d5e03cSMatthew Dillon #define AR_RTC_RESET AR_RTC_SYNC_OFFSET(RTC_SYNC_RESET) 1174b7d5e03cSMatthew Dillon #define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ 1175b7d5e03cSMatthew Dillon 1176b7d5e03cSMatthew Dillon /* system sleep status */ 1177b7d5e03cSMatthew Dillon #define AR_RTC_STATUS AR_RTC_SYNC_OFFSET(RTC_SYNC_STATUS) 1178b7d5e03cSMatthew Dillon #define AR_RTC_STATUS_M 0x0000003f 1179b7d5e03cSMatthew Dillon #define AR_RTC_STATUS_SHUTDOWN 0x00000001 1180b7d5e03cSMatthew Dillon #define AR_RTC_STATUS_ON 0x00000002 1181b7d5e03cSMatthew Dillon #define AR_RTC_STATUS_SLEEP 0x00000004 1182b7d5e03cSMatthew Dillon #define AR_RTC_STATUS_WAKEUP 0x00000008 1183b7d5e03cSMatthew Dillon #define AR_RTC_STATUS_SLEEP_ACCESS 0x00000010 1184b7d5e03cSMatthew Dillon #define AR_RTC_STATUS_PLL_CHANGING 0x00000020 1185b7d5e03cSMatthew Dillon 1186b7d5e03cSMatthew Dillon /* RTC Derived Register */ 1187b7d5e03cSMatthew Dillon #define AR_RTC_SLEEP_CLK AR_RTC_SYNC_OFFSET(RTC_SYNC_DERIVED) 1188b7d5e03cSMatthew Dillon #define AR_RTC_FORCE_DERIVED_CLK 0x00000002 1189b7d5e03cSMatthew Dillon #define AR_RTC_FORCE_SWREG_PRD 0x00000004 1190b7d5e03cSMatthew Dillon #define AR_RTC_PCIE_RST_PWDN_EN 0x00000008 1191b7d5e03cSMatthew Dillon 1192b7d5e03cSMatthew Dillon /* RTC Force Wake Register */ 1193b7d5e03cSMatthew Dillon #define AR_RTC_FORCE_WAKE AR_RTC_SYNC_OFFSET(RTC_SYNC_FORCE_WAKE) 1194b7d5e03cSMatthew Dillon #define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 1195b7d5e03cSMatthew Dillon #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 1196b7d5e03cSMatthew Dillon 1197b7d5e03cSMatthew Dillon /* RTC interrupt cause/clear */ 1198b7d5e03cSMatthew Dillon #define AR_RTC_INTR_CAUSE AR_RTC_SYNC_OFFSET(RTC_SYNC_INTR_CAUSE) 1199b7d5e03cSMatthew Dillon /* RTC interrupt enable */ 1200b7d5e03cSMatthew Dillon #define AR_RTC_INTR_ENABLE AR_RTC_SYNC_OFFSET(RTC_SYNC_INTR_ENABLE) 1201b7d5e03cSMatthew Dillon /* RTC interrupt mask */ 1202b7d5e03cSMatthew Dillon #define AR_RTC_INTR_MASK AR_RTC_SYNC_OFFSET(RTC_SYNC_INTR_MASK) 1203b7d5e03cSMatthew Dillon 1204b7d5e03cSMatthew Dillon 1205b7d5e03cSMatthew Dillon 1206b7d5e03cSMatthew Dillon /****************************************************************************** 1207b7d5e03cSMatthew Dillon * Analog Interface Register Map 1208b7d5e03cSMatthew Dillon ******************************************************************************/ 1209b7d5e03cSMatthew Dillon 1210b7d5e03cSMatthew Dillon #define AR_AN_OFFSET(_x) offsetof(struct analog_intf_reg_csr, _x) 1211b7d5e03cSMatthew Dillon 1212b7d5e03cSMatthew Dillon /* XXX */ 1213b7d5e03cSMatthew Dillon #if 1 1214b7d5e03cSMatthew Dillon // AR9280: rf long shift registers 1215b7d5e03cSMatthew Dillon #define AR_AN_RF2G1_CH0 0x7810 1216b7d5e03cSMatthew Dillon #define AR_AN_RF2G1_CH0_OB 0x03800000 1217b7d5e03cSMatthew Dillon #define AR_AN_RF2G1_CH0_OB_S 23 1218b7d5e03cSMatthew Dillon #define AR_AN_RF2G1_CH0_DB 0x1C000000 1219b7d5e03cSMatthew Dillon #define AR_AN_RF2G1_CH0_DB_S 26 1220b7d5e03cSMatthew Dillon 1221b7d5e03cSMatthew Dillon #define AR_AN_RF5G1_CH0 0x7818 1222b7d5e03cSMatthew Dillon #define AR_AN_RF5G1_CH0_OB5 0x00070000 1223b7d5e03cSMatthew Dillon #define AR_AN_RF5G1_CH0_OB5_S 16 1224b7d5e03cSMatthew Dillon #define AR_AN_RF5G1_CH0_DB5 0x00380000 1225b7d5e03cSMatthew Dillon #define AR_AN_RF5G1_CH0_DB5_S 19 1226b7d5e03cSMatthew Dillon 1227b7d5e03cSMatthew Dillon #define AR_AN_RF2G1_CH1 0x7834 1228b7d5e03cSMatthew Dillon #define AR_AN_RF2G1_CH1_OB 0x03800000 1229b7d5e03cSMatthew Dillon #define AR_AN_RF2G1_CH1_OB_S 23 1230b7d5e03cSMatthew Dillon #define AR_AN_RF2G1_CH1_DB 0x1C000000 1231b7d5e03cSMatthew Dillon #define AR_AN_RF2G1_CH1_DB_S 26 1232b7d5e03cSMatthew Dillon 1233b7d5e03cSMatthew Dillon #define AR_AN_RF5G1_CH1 0x783C 1234b7d5e03cSMatthew Dillon #define AR_AN_RF5G1_CH1_OB5 0x00070000 1235b7d5e03cSMatthew Dillon #define AR_AN_RF5G1_CH1_OB5_S 16 1236b7d5e03cSMatthew Dillon #define AR_AN_RF5G1_CH1_DB5 0x00380000 1237b7d5e03cSMatthew Dillon #define AR_AN_RF5G1_CH1_DB5_S 19 1238b7d5e03cSMatthew Dillon 1239b7d5e03cSMatthew Dillon #define AR_AN_TOP2 0x7894 1240b7d5e03cSMatthew Dillon #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 1241b7d5e03cSMatthew Dillon #define AR_AN_TOP2_XPABIAS_LVL_S 30 1242b7d5e03cSMatthew Dillon #define AR_AN_TOP2_LOCALBIAS 0x00200000 1243b7d5e03cSMatthew Dillon #define AR_AN_TOP2_LOCALBIAS_S 21 1244b7d5e03cSMatthew Dillon #define AR_AN_TOP2_PWDCLKIND 0x00400000 1245b7d5e03cSMatthew Dillon #define AR_AN_TOP2_PWDCLKIND_S 22 1246b7d5e03cSMatthew Dillon 1247b7d5e03cSMatthew Dillon #define AR_AN_SYNTH9 0x7868 1248b7d5e03cSMatthew Dillon #define AR_AN_SYNTH9_REFDIVA 0xf8000000 1249b7d5e03cSMatthew Dillon #define AR_AN_SYNTH9_REFDIVA_S 27 1250b7d5e03cSMatthew Dillon 1251b7d5e03cSMatthew Dillon // AR9285 Analog registers 1252b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G1 0x7820 1253b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G2 0x7824 1254b7d5e03cSMatthew Dillon 1255b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3 0x7828 1256b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_OB_0 0x00E00000 1257b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_OB_0_S 21 1258b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_OB_1 0x001C0000 1259b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_OB_1_S 18 1260b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_OB_2 0x00038000 1261b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_OB_2_S 15 1262b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_OB_3 0x00007000 1263b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_OB_3_S 12 1264b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_OB_4 0x00000E00 1265b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_OB_4_S 9 1266b7d5e03cSMatthew Dillon 1267b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_DB1_0 0x000001C0 1268b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_DB1_0_S 6 1269b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_DB1_1 0x00000038 1270b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_DB1_1_S 3 1271b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_DB1_2 0x00000007 1272b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G3_DB1_2_S 0 1273b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G4 0x782C 1274b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G4_DB1_3 0xE0000000 1275b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G4_DB1_3_S 29 1276b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G4_DB1_4 0x1C000000 1277b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G4_DB1_4_S 26 1278b7d5e03cSMatthew Dillon 1279b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G4_DB2_0 0x03800000 1280b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G4_DB2_0_S 23 1281b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G4_DB2_1 0x00700000 1282b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G4_DB2_1_S 20 1283b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G4_DB2_2 0x000E0000 1284b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G4_DB2_2_S 17 1285b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G4_DB2_3 0x0001C000 1286b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G4_DB2_3_S 14 1287b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G4_DB2_4 0x00003800 1288b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G4_DB2_4_S 11 1289b7d5e03cSMatthew Dillon 1290b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G6 0x7834 1291b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G7 0x7838 1292b7d5e03cSMatthew Dillon #define AR9285_AN_RF2G9 0x7840 1293b7d5e03cSMatthew Dillon #define AR9285_AN_RXTXBB1 0x7854 1294b7d5e03cSMatthew Dillon #define AR9285_AN_TOP2 0x7868 1295b7d5e03cSMatthew Dillon 1296b7d5e03cSMatthew Dillon #define AR9285_AN_TOP3 0x786c 1297b7d5e03cSMatthew Dillon #define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C 1298b7d5e03cSMatthew Dillon #define AR9285_AN_TOP3_XPABIAS_LVL_S 2 1299b7d5e03cSMatthew Dillon 1300b7d5e03cSMatthew Dillon #define AR9285_AN_TOP4 0x7870 1301b7d5e03cSMatthew Dillon #define AR9285_AN_TOP4_DEFAULT 0x10142c00 1302b7d5e03cSMatthew Dillon #endif 1303b7d5e03cSMatthew Dillon 1304b7d5e03cSMatthew Dillon 1305b7d5e03cSMatthew Dillon /****************************************************************************** 1306b7d5e03cSMatthew Dillon * MAC PCU Register Map 1307b7d5e03cSMatthew Dillon ******************************************************************************/ 1308b7d5e03cSMatthew Dillon 1309b7d5e03cSMatthew Dillon #define AR_MAC_PCU_OFFSET(_x) offsetof(struct mac_pcu_reg, _x) 1310b7d5e03cSMatthew Dillon 1311b7d5e03cSMatthew Dillon /* MAC station ID0 - low 32 bits */ 1312b7d5e03cSMatthew Dillon #define AR_STA_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_STA_ADDR_L32) 1313b7d5e03cSMatthew Dillon /* MAC station ID1 - upper 16 bits */ 1314b7d5e03cSMatthew Dillon #define AR_STA_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_STA_ADDR_U16) 1315b7d5e03cSMatthew Dillon #define AR_STA_ID1_SADH_MASK 0x0000FFFF // Mask for 16 msb of MAC addr 1316b7d5e03cSMatthew Dillon #define AR_STA_ID1_STA_AP 0x00010000 // Device is AP 1317b7d5e03cSMatthew Dillon #define AR_STA_ID1_ADHOC 0x00020000 // Device is ad-hoc 1318b7d5e03cSMatthew Dillon #define AR_STA_ID1_PWR_SAV 0x00040000 // Power save in generated frames 1319b7d5e03cSMatthew Dillon #define AR_STA_ID1_KSRCHDIS 0x00080000 // Key search disable 1320b7d5e03cSMatthew Dillon #define AR_STA_ID1_PCF 0x00100000 // Observe PCF 1321b7d5e03cSMatthew Dillon #define AR_STA_ID1_USE_DEFANT 0x00200000 // Use default antenna 1322b7d5e03cSMatthew Dillon #define AR_STA_ID1_DEFANT_UPDATE 0x00400000 // Update default ant w/TX antenna 1323b7d5e03cSMatthew Dillon #define AR_STA_ID1_RTS_USE_DEF 0x00800000 // Use default antenna to send RTS 1324b7d5e03cSMatthew Dillon #define AR_STA_ID1_ACKCTS_6MB 0x01000000 // Use 6Mb/s rate for ACK & CTS 1325b7d5e03cSMatthew Dillon #define AR_STA_ID1_BASE_RATE_11B 0x02000000 // Use 11b base rate for ACK & CTS 1326b7d5e03cSMatthew Dillon #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 // default ant for generated frames 1327b7d5e03cSMatthew Dillon #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 // Enable Michael 1328b7d5e03cSMatthew Dillon #define AR_STA_ID1_KSRCH_MODE 0x10000000 // Look-up unique key when !keyID 1329b7d5e03cSMatthew Dillon #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 // Don't replace seq num 1330b7d5e03cSMatthew Dillon #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 // IV endian-ness in CBC nonce 1331b7d5e03cSMatthew Dillon #define AR_STA_ID1_MCAST_KSRCH 0x80000000 // Adhoc key search enable 1332b7d5e03cSMatthew Dillon 1333b7d5e03cSMatthew Dillon /* MAC BSSID low 32 bits */ 1334b7d5e03cSMatthew Dillon #define AR_BSS_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID_L32) 1335b7d5e03cSMatthew Dillon /* MAC BSSID upper 16 bits / AID */ 1336b7d5e03cSMatthew Dillon #define AR_BSS_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID_U16) 1337b7d5e03cSMatthew Dillon #define AR_BSS_ID1_U16 0x0000FFFF // Mask for upper 16 bits of BSSID 1338b7d5e03cSMatthew Dillon #define AR_BSS_ID1_AID 0x07FF0000 // Mask for association ID 1339b7d5e03cSMatthew Dillon #define AR_BSS_ID1_AID_S 16 // Shift for association ID 1340b7d5e03cSMatthew Dillon 1341b7d5e03cSMatthew Dillon /* 1342b7d5e03cSMatthew Dillon * Added to support dual BSSID/TSF which are needed in the application 1343b7d5e03cSMatthew Dillon * of Mesh networking. See bug 35189. Note that the only function added 1344b7d5e03cSMatthew Dillon * with this BSSID2 is to receive multi/broadcast from BSSID2 as well 1345b7d5e03cSMatthew Dillon */ 1346b7d5e03cSMatthew Dillon /* MAC BSSID low 32 bits */ 1347b7d5e03cSMatthew Dillon #define AR_BSS2_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_L32) 1348b7d5e03cSMatthew Dillon /* MAC BSSID upper 16 bits / AID */ 1349b7d5e03cSMatthew Dillon #define AR_BSS2_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_U16) 1350b7d5e03cSMatthew Dillon 1351b7d5e03cSMatthew Dillon /* MAC Beacon average RSSI 1352b7d5e03cSMatthew Dillon * 1353b7d5e03cSMatthew Dillon * This register holds the average RSSI with 1/16 dB resolution. 1354b7d5e03cSMatthew Dillon * The RSSI is averaged over multiple beacons which matched our BSSID. 1355b7d5e03cSMatthew Dillon * Note that AVE_VALUE is 12 bits with 4 bits below the normal 8 bits. 1356b7d5e03cSMatthew Dillon * These lowest 4 bits provide for a resolution of 1/16 dB. 1357b7d5e03cSMatthew Dillon * 1358b7d5e03cSMatthew Dillon */ 1359b7d5e03cSMatthew Dillon #define AR_BCN_RSSI_AVE AR_MAC_PCU_OFFSET(MAC_PCU_BCN_RSSI_AVE) 1360b7d5e03cSMatthew Dillon #define AR_BCN_RSSI_AVE_VAL 0x00000FFF // Beacon RSSI value 1361b7d5e03cSMatthew Dillon #define AR_BCN_RSSI_AVE_VAL_S 0 1362b7d5e03cSMatthew Dillon 1363b7d5e03cSMatthew Dillon /* MAC ACK & CTS time-out */ 1364b7d5e03cSMatthew Dillon #define AR_TIME_OUT AR_MAC_PCU_OFFSET(MAC_PCU_ACK_CTS_TIMEOUT) 1365b7d5e03cSMatthew Dillon #define AR_TIME_OUT_ACK 0x00003FFF // Mask for ACK time-out 1366b7d5e03cSMatthew Dillon #define AR_TIME_OUT_ACK_S 0 1367b7d5e03cSMatthew Dillon #define AR_TIME_OUT_CTS 0x3FFF0000 // Mask for CTS time-out 1368b7d5e03cSMatthew Dillon #define AR_TIME_OUT_CTS_S 16 1369b7d5e03cSMatthew Dillon 1370b7d5e03cSMatthew Dillon /* beacon RSSI warning / bmiss threshold */ 1371b7d5e03cSMatthew Dillon #define AR_RSSI_THR AR_MAC_PCU_OFFSET(MAC_PCU_BCN_RSSI_CTL) 1372b7d5e03cSMatthew Dillon #define AR_RSSI_THR_VAL 0x000000FF // Beacon RSSI warning threshold 1373b7d5e03cSMatthew Dillon #define AR_RSSI_THR_VAL_S 0 1374b7d5e03cSMatthew Dillon #define AR_RSSI_THR_BM_THR 0x0000FF00 // Mask for Missed beacon threshold 1375b7d5e03cSMatthew Dillon #define AR_RSSI_THR_BM_THR_S 8 // Shift for Missed beacon threshold 1376b7d5e03cSMatthew Dillon #define AR_RSSI_BCN_WEIGHT 0x1F000000 // RSSI average weight 1377b7d5e03cSMatthew Dillon #define AR_RSSI_BCN_WEIGHT_S 24 1378b7d5e03cSMatthew Dillon #define AR_RSSI_BCN_RSSI_RST 0x20000000 // Reset RSSI value 1379b7d5e03cSMatthew Dillon 1380b7d5e03cSMatthew Dillon /* MAC transmit latency register */ 1381b7d5e03cSMatthew Dillon #define AR_USEC AR_MAC_PCU_OFFSET(MAC_PCU_USEC_LATENCY) 1382b7d5e03cSMatthew Dillon #define AR_USEC_USEC 0x000000FF // Mask for clock cycles in 1 usec 1383b7d5e03cSMatthew Dillon #define AR_USEC_USEC_S 0 // Shift for clock cycles in 1 usec 1384b7d5e03cSMatthew Dillon #define AR_USEC_TX_LAT 0x007FC000 // tx latency to start of SIGNAL (usec) 1385b7d5e03cSMatthew Dillon #define AR_USEC_TX_LAT_S 14 // tx latency to start of SIGNAL (usec) 1386b7d5e03cSMatthew Dillon #define AR_USEC_RX_LAT 0x1F800000 // rx latency to start of SIGNAL (usec) 1387b7d5e03cSMatthew Dillon #define AR_USEC_RX_LAT_S 23 // rx latency to start of SIGNAL (usec) 1388b7d5e03cSMatthew Dillon 1389b7d5e03cSMatthew Dillon #define AR_SLOT_HALF 13 1390b7d5e03cSMatthew Dillon #define AR_SLOT_QUARTER 21 1391b7d5e03cSMatthew Dillon 1392b7d5e03cSMatthew Dillon #define AR_USEC_RX_LATENCY 0x1f800000 1393b7d5e03cSMatthew Dillon #define AR_USEC_RX_LATENCY_S 23 1394b7d5e03cSMatthew Dillon #define AR_RX_LATENCY_FULL 37 1395b7d5e03cSMatthew Dillon #define AR_RX_LATENCY_HALF 74 1396b7d5e03cSMatthew Dillon #define AR_RX_LATENCY_QUARTER 148 1397b7d5e03cSMatthew Dillon #define AR_RX_LATENCY_FULL_FAST_CLOCK 41 1398b7d5e03cSMatthew Dillon #define AR_RX_LATENCY_HALF_FAST_CLOCK 82 1399b7d5e03cSMatthew Dillon #define AR_RX_LATENCY_QUARTER_FAST_CLOCK 163 1400b7d5e03cSMatthew Dillon 1401b7d5e03cSMatthew Dillon #define AR_USEC_TX_LATENCY 0x007fc000 1402b7d5e03cSMatthew Dillon #define AR_USEC_TX_LATENCY_S 14 1403b7d5e03cSMatthew Dillon #define AR_TX_LATENCY_FULL 54 1404b7d5e03cSMatthew Dillon #define AR_TX_LATENCY_HALF 108 1405b7d5e03cSMatthew Dillon #define AR_TX_LATENCY_QUARTER 216 1406b7d5e03cSMatthew Dillon #define AR_TX_LATENCY_FULL_FAST_CLOCK 54 1407b7d5e03cSMatthew Dillon #define AR_TX_LATENCY_HALF_FAST_CLOCK 119 1408b7d5e03cSMatthew Dillon #define AR_TX_LATENCY_QUARTER_FAST_CLOCK 238 1409b7d5e03cSMatthew Dillon 1410b7d5e03cSMatthew Dillon #define AR_USEC_HALF 19 1411b7d5e03cSMatthew Dillon #define AR_USEC_QUARTER 9 1412b7d5e03cSMatthew Dillon #define AR_USEC_HALF_FAST_CLOCK 21 1413b7d5e03cSMatthew Dillon #define AR_USEC_QUARTER_FAST_CLOCK 10 1414b7d5e03cSMatthew Dillon 1415b7d5e03cSMatthew Dillon #define AR_EIFS_HALF 175 1416b7d5e03cSMatthew Dillon #define AR_EIFS_QUARTER 340 1417b7d5e03cSMatthew Dillon 1418b7d5e03cSMatthew Dillon #define AR_RESET_TSF AR_MAC_PCU_OFFSET(MAC_PCU_RESET_TSF) 1419b7d5e03cSMatthew Dillon #define AR_RESET_TSF_ONCE 0x01000000 // reset tsf once ; self-clears bit 1420b7d5e03cSMatthew Dillon #define AR_RESET_TSF2_ONCE 0x02000000 // reset tsf2 once ; self-clears bit 1421b7d5e03cSMatthew Dillon 1422b7d5e03cSMatthew Dillon /* MAC CFP Interval (TU/msec) */ 1423b7d5e03cSMatthew Dillon #define AR_CFP_PERIOD 0x8024 /* MAC CFP Interval (TU/msec) */ 1424b7d5e03cSMatthew Dillon #define AR_TIMER0 0x8028 /* MAC Next beacon time (TU/msec) */ 1425b7d5e03cSMatthew Dillon #define AR_TIMER1 0x802c /* MAC DMA beacon alert time (1/8 TU) */ 1426b7d5e03cSMatthew Dillon #define AR_TIMER2 0x8030 /* MAC Software beacon alert (1/8 TU) */ 1427b7d5e03cSMatthew Dillon #define AR_TIMER3 0x8034 /* MAC ATIM window time */ 1428b7d5e03cSMatthew Dillon 1429b7d5e03cSMatthew Dillon /* MAC maximum CFP duration */ 1430b7d5e03cSMatthew Dillon #define AR_MAX_CFP_DUR AR_MAC_PCU_OFFSET(MAC_PCU_MAX_CFP_DUR) 1431b7d5e03cSMatthew Dillon #define AR_CFP_VAL 0x0000FFFF // CFP value in uS 1432b7d5e03cSMatthew Dillon 1433b7d5e03cSMatthew Dillon /* MAC receive filter register */ 1434b7d5e03cSMatthew Dillon #define AR_RX_FILTER AR_MAC_PCU_OFFSET(MAC_PCU_RX_FILTER) 1435b7d5e03cSMatthew Dillon #define AR_RX_FILTER_ALL 0x00000000 // Disallow all frames 1436b7d5e03cSMatthew Dillon #define AR_RX_UCAST 0x00000001 // Allow unicast frames 1437b7d5e03cSMatthew Dillon #define AR_RX_MCAST 0x00000002 // Allow multicast frames 1438b7d5e03cSMatthew Dillon #define AR_RX_BCAST 0x00000004 // Allow broadcast frames 1439b7d5e03cSMatthew Dillon #define AR_RX_CONTROL 0x00000008 // Allow control frames 1440b7d5e03cSMatthew Dillon #define AR_RX_BEACON 0x00000010 // Allow beacon frames 1441b7d5e03cSMatthew Dillon #define AR_RX_PROM 0x00000020 // Promiscuous mode all packets 1442b7d5e03cSMatthew Dillon #define AR_RX_PROBE_REQ 0x00000080 // Any probe request frameA 1443b7d5e03cSMatthew Dillon #define AR_RX_MY_BEACON 0x00000200 // Any beacon frame with matching BSSID 1444b7d5e03cSMatthew Dillon #define AR_RX_COMPR_BAR 0x00000400 // Compressed directed block ack request 1445b7d5e03cSMatthew Dillon #define AR_RX_COMPR_BA 0x00000800 // Compressed directed block ack 1446b7d5e03cSMatthew Dillon #define AR_RX_UNCOM_BA_BAR 0x00001000 // Uncompressed directed BA or BAR 1447b7d5e03cSMatthew Dillon #define AR_RX_HWBCNPROC_EN 0x00020000 // Enable hw beacon processing (see AR_HWBCNPROC1) 1448b7d5e03cSMatthew Dillon #define AR_RX_CONTROL_WRAPPER 0x00080000 // Control wrapper. Jupiter only. 1449b7d5e03cSMatthew Dillon #define AR_RX_4ADDRESS 0x00100000 // 4-Address frames 1450b7d5e03cSMatthew Dillon 1451b7d5e03cSMatthew Dillon #define AR_PHY_ERR_MASK_REG AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERROR_MASK_CONT) 1452b7d5e03cSMatthew Dillon 1453b7d5e03cSMatthew Dillon 1454b7d5e03cSMatthew Dillon /* MAC multicast filter lower 32 bits */ 1455b7d5e03cSMatthew Dillon #define AR_MCAST_FIL0 AR_MAC_PCU_OFFSET(MAC_PCU_MCAST_FILTER_L32) 1456b7d5e03cSMatthew Dillon /* MAC multicast filter upper 32 bits */ 1457b7d5e03cSMatthew Dillon #define AR_MCAST_FIL1 AR_MAC_PCU_OFFSET(MAC_PCU_MCAST_FILTER_U32) 1458b7d5e03cSMatthew Dillon 1459b7d5e03cSMatthew Dillon /* MAC PCU diagnostic switches */ 1460b7d5e03cSMatthew Dillon #define AR_DIAG_SW AR_MAC_PCU_OFFSET(MAC_PCU_DIAG_SW) 1461b7d5e03cSMatthew Dillon #define AR_DIAG_CACHE_ACK 0x00000001 // disable ACK when no valid key 1462b7d5e03cSMatthew Dillon #define AR_DIAG_ACK_DIS 0x00000002 // disable ACK generation 1463b7d5e03cSMatthew Dillon #define AR_DIAG_CTS_DIS 0x00000004 // disable CTS generation 1464b7d5e03cSMatthew Dillon #define AR_DIAG_ENCRYPT_DIS 0x00000008 // disable encryption 1465b7d5e03cSMatthew Dillon #define AR_DIAG_DECRYPT_DIS 0x00000010 // disable decryption 1466b7d5e03cSMatthew Dillon #define AR_DIAG_RX_DIS 0x00000020 // disable receive 1467b7d5e03cSMatthew Dillon #define AR_DIAG_LOOP_BACK 0x00000040 // enable loopback 1468b7d5e03cSMatthew Dillon #define AR_DIAG_CORR_FCS 0x00000080 // corrupt FCS 1469b7d5e03cSMatthew Dillon #define AR_DIAG_CHAN_INFO 0x00000100 // dump channel info 1470b7d5e03cSMatthew Dillon #define AR_DIAG_FRAME_NV0 0x00020000 // accept w/protocol version !0 1471b7d5e03cSMatthew Dillon #define AR_DIAG_OBS_PT_SEL1 0x000C0000 // observation point select 1472b7d5e03cSMatthew Dillon #define AR_DIAG_OBS_PT_SEL1_S 18 // Shift for observation point select 1473b7d5e03cSMatthew Dillon #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 // force rx_clear high 1474b7d5e03cSMatthew Dillon #define AR_DIAG_IGNORE_VIRT_CS 0x00200000 // ignore virtual carrier sense 1475b7d5e03cSMatthew Dillon #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 // force channel idle high 1476b7d5e03cSMatthew Dillon #define AR_DIAG_EIFS_CTRL_ENA 0x00800000 // use framed and ~wait_wep if 0 1477b7d5e03cSMatthew Dillon #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 // dual chain channel info 1478b7d5e03cSMatthew Dillon #define AR_DIAG_RX_ABORT 0x02000000 // abort rx 1479b7d5e03cSMatthew Dillon #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 // saturate cycle cnts (no shift) 1480b7d5e03cSMatthew Dillon #define AR_DIAG_OBS_PT_SEL2 0x08000000 // Mask for observation point sel 1481b7d5e03cSMatthew Dillon #define AR_DIAG_OBS_PT_SEL2_S 27 1482b7d5e03cSMatthew Dillon #define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 // force rx_clear (ctl) low (i.e. busy) 1483b7d5e03cSMatthew Dillon #define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 // force rx_clear (ext) low (i.e. busy) 1484b7d5e03cSMatthew Dillon 1485b7d5e03cSMatthew Dillon /* MAC local clock lower 32 bits */ 1486b7d5e03cSMatthew Dillon #define AR_TSF_L32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF_L32) 1487b7d5e03cSMatthew Dillon /* MAC local clock upper 32 bits */ 1488b7d5e03cSMatthew Dillon #define AR_TSF_U32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF_U32) 1489b7d5e03cSMatthew Dillon 1490b7d5e03cSMatthew Dillon /* 1491b7d5e03cSMatthew Dillon * Secondary TSF support added for dual BSSID/TSF 1492b7d5e03cSMatthew Dillon * which is needed in the application of DirectConnect or 1493b7d5e03cSMatthew Dillon * Mesh networking 1494b7d5e03cSMatthew Dillon */ 1495b7d5e03cSMatthew Dillon /* MAC local clock lower 32 bits */ 1496b7d5e03cSMatthew Dillon #define AR_TSF2_L32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_L32) 1497b7d5e03cSMatthew Dillon /* MAC local clock upper 32 bits */ 1498b7d5e03cSMatthew Dillon #define AR_TSF2_U32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_U32) 1499b7d5e03cSMatthew Dillon 1500b7d5e03cSMatthew Dillon /* ADDAC test register */ 1501b7d5e03cSMatthew Dillon #define AR_TST_ADDAC AR_MAC_PCU_OFFSET(MAC_PCU_TST_ADDAC) 1502b7d5e03cSMatthew Dillon 1503b7d5e03cSMatthew Dillon #define AR_TST_ADDAC_TST_MODE 0x1 1504b7d5e03cSMatthew Dillon #define AR_TST_ADDAC_TST_MODE_S 0 1505b7d5e03cSMatthew Dillon #define AR_TST_ADDAC_TST_LOOP_ENA 0x2 1506b7d5e03cSMatthew Dillon #define AR_TST_ADDAC_TST_LOOP_ENA_S 1 1507b7d5e03cSMatthew Dillon #define AR_TST_ADDAC_BEGIN_CAPTURE 0x80000 1508b7d5e03cSMatthew Dillon #define AR_TST_ADDAC_BEGIN_CAPTURE_S 19 1509b7d5e03cSMatthew Dillon 1510b7d5e03cSMatthew Dillon /* default antenna register */ 1511b7d5e03cSMatthew Dillon #define AR_DEF_ANTENNA AR_MAC_PCU_OFFSET(MAC_PCU_DEF_ANTENNA) 1512b7d5e03cSMatthew Dillon 1513b7d5e03cSMatthew Dillon /* MAC AES mute mask */ 1514b7d5e03cSMatthew Dillon #define AR_AES_MUTE_MASK0 AR_MAC_PCU_OFFSET(MAC_PCU_AES_MUTE_MASK_0) 1515b7d5e03cSMatthew Dillon #define AR_AES_MUTE_MASK0_FC 0x0000FFFF // frame ctrl mask bits 1516b7d5e03cSMatthew Dillon #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 // qos ctrl mask bits 1517b7d5e03cSMatthew Dillon #define AR_AES_MUTE_MASK0_QOS_S 16 1518b7d5e03cSMatthew Dillon 1519b7d5e03cSMatthew Dillon /* MAC AES mute mask 1 */ 1520b7d5e03cSMatthew Dillon #define AR_AES_MUTE_MASK1 AR_MAC_PCU_OFFSET(MAC_PCU_AES_MUTE_MASK_1) 1521b7d5e03cSMatthew Dillon #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF // seq + frag mask bits 1522b7d5e03cSMatthew Dillon #define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000 // frame ctrl mask for mgmt frames (Sowl) 1523b7d5e03cSMatthew Dillon #define AR_AES_MUTE_MASK1_FC_MGMT_S 16 1524b7d5e03cSMatthew Dillon 1525b7d5e03cSMatthew Dillon /* control clock domain */ 1526b7d5e03cSMatthew Dillon #define AR_GATED_CLKS AR_MAC_PCU_OFFSET(MAC_PCU_GATED_CLKS) 1527b7d5e03cSMatthew Dillon #define AR_GATED_CLKS_TX 0x00000002 1528b7d5e03cSMatthew Dillon #define AR_GATED_CLKS_RX 0x00000004 1529b7d5e03cSMatthew Dillon #define AR_GATED_CLKS_REG 0x00000008 1530b7d5e03cSMatthew Dillon 1531b7d5e03cSMatthew Dillon /* MAC PCU observation bus 2 */ 1532b7d5e03cSMatthew Dillon #define AR_OBS_BUS_CTRL AR_MAC_PCU_OFFSET(MAC_PCU_OBS_BUS_2) 1533b7d5e03cSMatthew Dillon #define AR_OBS_BUS_SEL_1 0x00040000 1534b7d5e03cSMatthew Dillon #define AR_OBS_BUS_SEL_2 0x00080000 1535b7d5e03cSMatthew Dillon #define AR_OBS_BUS_SEL_3 0x000C0000 1536b7d5e03cSMatthew Dillon #define AR_OBS_BUS_SEL_4 0x08040000 1537b7d5e03cSMatthew Dillon #define AR_OBS_BUS_SEL_5 0x08080000 1538b7d5e03cSMatthew Dillon 1539b7d5e03cSMatthew Dillon /* MAC PCU observation bus 1 */ 1540b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1 AR_MAC_PCU_OFFSET(MAC_PCU_OBS_BUS_1) 1541b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_PCU 0x00000001 1542b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_RX_END 0x00000002 1543b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_RX_WEP 0x00000004 1544b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_RX_BEACON 0x00000008 1545b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_RX_FILTER 0x00000010 1546b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_TX_HCF 0x00000020 1547b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_QUIET_TIME 0x00000040 1548b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 1549b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_TX_HOLD 0x00000100 1550b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_TX_FRAME 0x00000200 1551b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_RX_FRAME 0x00000400 1552b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_RX_CLEAR 0x00000800 1553b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_WEP_STATE 0x0003F000 1554b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_WEP_STATE_S 12 1555b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_RX_STATE 0x01F00000 1556b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_RX_STATE_S 20 1557b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_TX_STATE 0x7E000000 1558b7d5e03cSMatthew Dillon #define AR_OBS_BUS_1_TX_STATE_S 25 1559b7d5e03cSMatthew Dillon 1560b7d5e03cSMatthew Dillon /* MAC PCU dynamic MIMO power save */ 1561b7d5e03cSMatthew Dillon #define AR_PCU_SMPS AR_MAC_PCU_OFFSET(MAC_PCU_DYM_MIMO_PWR_SAVE) 1562b7d5e03cSMatthew Dillon #define AR_PCU_SMPS_MAC_CHAINMASK 0x00000001 // Use the Rx Chainmask of MAC's setting 1563b7d5e03cSMatthew Dillon #define AR_PCU_SMPS_HW_CTRL_EN 0x00000002 // Enable hardware control of dynamic MIMO PS 1564b7d5e03cSMatthew Dillon #define AR_PCU_SMPS_SW_CTRL_HPWR 0x00000004 // Software controlled High power chainmask setting 1565b7d5e03cSMatthew Dillon #define AR_PCU_SMPS_LPWR_CHNMSK 0x00000070 // Low power setting of Rx Chainmask 1566b7d5e03cSMatthew Dillon #define AR_PCU_SMPS_LPWR_CHNMSK_S 4 1567b7d5e03cSMatthew Dillon #define AR_PCU_SMPS_HPWR_CHNMSK 0x00000700 // High power setting of Rx Chainmask 1568b7d5e03cSMatthew Dillon #define AR_PCU_SMPS_HPWR_CHNMSK_S 8 1569b7d5e03cSMatthew Dillon #define AR_PCU_SMPS_LPWR_CHNMSK_VAL 0x1 1570b7d5e03cSMatthew Dillon 1571b7d5e03cSMatthew Dillon /* MAC PCU frame start time trigger for the AP's Downlink Traffic in TDMA mode */ 1572b7d5e03cSMatthew Dillon #define AR_TDMA_TXSTARTTRIG_LSB AR_MAC_PCU_OFFSET(MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB) 1573b7d5e03cSMatthew Dillon #define AR_TDMA_TXSTARTTRIG_MSB AR_MAC_PCU_OFFSET(MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB) 1574b7d5e03cSMatthew Dillon 1575b7d5e03cSMatthew Dillon /* MAC Time stamp of the last beacon received */ 1576b7d5e03cSMatthew Dillon #define AR_LAST_TSTP AR_MAC_PCU_OFFSET(MAC_PCU_LAST_BEACON_TSF) 1577b7d5e03cSMatthew Dillon /* MAC current NAV value */ 1578b7d5e03cSMatthew Dillon #define AR_NAV AR_MAC_PCU_OFFSET(MAC_PCU_NAV) 1579b7d5e03cSMatthew Dillon /* MAC RTS exchange success counter */ 1580b7d5e03cSMatthew Dillon #define AR_RTS_OK AR_MAC_PCU_OFFSET(MAC_PCU_RTS_SUCCESS_CNT) 1581b7d5e03cSMatthew Dillon /* MAC RTS exchange failure counter */ 1582b7d5e03cSMatthew Dillon #define AR_RTS_FAIL AR_MAC_PCU_OFFSET(MAC_PCU_RTS_FAIL_CNT) 1583b7d5e03cSMatthew Dillon /* MAC ACK failure counter */ 1584b7d5e03cSMatthew Dillon #define AR_ACK_FAIL AR_MAC_PCU_OFFSET(MAC_PCU_ACK_FAIL_CNT) 1585b7d5e03cSMatthew Dillon /* MAC FCS check failure counter */ 1586b7d5e03cSMatthew Dillon #define AR_FCS_FAIL AR_MAC_PCU_OFFSET(MAC_PCU_FCS_FAIL_CNT) 1587b7d5e03cSMatthew Dillon /* MAC Valid beacon value */ 1588b7d5e03cSMatthew Dillon #define AR_BEACON_CNT AR_MAC_PCU_OFFSET(MAC_PCU_BEACON_CNT) 1589b7d5e03cSMatthew Dillon 1590b7d5e03cSMatthew Dillon /* MAC PCU tdma slot alert control */ 1591b7d5e03cSMatthew Dillon #define AR_TDMA_SLOT_ALERT_CNTL AR_MAC_PCU_OFFSET(MAC_PCU_TDMA_SLOT_ALERT_CNTL) 1592b7d5e03cSMatthew Dillon 1593b7d5e03cSMatthew Dillon /* MAC PCU Basic MCS set for MCS 0 to 31 */ 1594b7d5e03cSMatthew Dillon #define AR_BASIC_SET AR_MAC_PCU_OFFSET(MAC_PCU_BASIC_SET) 1595b7d5e03cSMatthew Dillon #define ALL_RATE 0xff 1596b7d5e03cSMatthew Dillon 1597b7d5e03cSMatthew Dillon /* MAC_PCU_ _SEQ */ 1598b7d5e03cSMatthew Dillon #define AR_MGMT_SEQ AR_MAC_PCU_OFFSET(MAC_PCU_MGMT_SEQ) 1599b7d5e03cSMatthew Dillon #define AR_MGMT_SEQ_MIN 0xFFF /* sequence minimum value*/ 1600b7d5e03cSMatthew Dillon #define AR_MGMT_SEQ_MIN_S 0 1601b7d5e03cSMatthew Dillon #define AR_MIN_HW_SEQ 0 1602b7d5e03cSMatthew Dillon #define AR_MGMT_SEQ_MAX 0xFFF0000 /* sequence maximum value*/ 1603b7d5e03cSMatthew Dillon #define AR_MGMT_SEQ_MAX_S 16 1604b7d5e03cSMatthew Dillon #define AR_MAX_HW_SEQ 0xFF 1605b7d5e03cSMatthew Dillon /*MAC PCU Key Cache Antenna 1 */ 1606b7d5e03cSMatthew Dillon #define AR_TX_ANT_1 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_1) 1607b7d5e03cSMatthew Dillon /*MAC PCU Key Cache Antenna 2 */ 1608b7d5e03cSMatthew Dillon #define AR_TX_ANT_2 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_2) 1609b7d5e03cSMatthew Dillon /*MAC PCU Key Cache Antenna 3 */ 1610b7d5e03cSMatthew Dillon #define AR_TX_ANT_3 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_3) 1611b7d5e03cSMatthew Dillon /*MAC PCU Key Cache Antenna 4 */ 1612b7d5e03cSMatthew Dillon #define AR_TX_ANT_4 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_4) 1613b7d5e03cSMatthew Dillon 1614b7d5e03cSMatthew Dillon 1615b7d5e03cSMatthew Dillon /* Extended range mode */ 1616b7d5e03cSMatthew Dillon #define AR_XRMODE AR_MAC_PCU_OFFSET(MAC_PCU_XRMODE) 1617b7d5e03cSMatthew Dillon /* Extended range mode delay */ 1618b7d5e03cSMatthew Dillon #define AR_XRDEL AR_MAC_PCU_OFFSET(MAC_PCU_XRDEL) 1619b7d5e03cSMatthew Dillon /* Extended range mode timeout */ 1620b7d5e03cSMatthew Dillon #define AR_XRTO AR_MAC_PCU_OFFSET(MAC_PCU_XRTO) 1621b7d5e03cSMatthew Dillon /* Extended range mode chirp */ 1622b7d5e03cSMatthew Dillon #define AR_XRCRP AR_MAC_PCU_OFFSET(MAC_PCU_XRCRP) 1623b7d5e03cSMatthew Dillon /* Extended range stomp */ 1624b7d5e03cSMatthew Dillon #define AR_XRSTMP AR_MAC_PCU_OFFSET(MAC_PCU_XRSTMP) 1625b7d5e03cSMatthew Dillon 1626b7d5e03cSMatthew Dillon 1627b7d5e03cSMatthew Dillon /* Enhanced sleep control 1 */ 1628b7d5e03cSMatthew Dillon #define AR_SLEEP1 AR_MAC_PCU_OFFSET(MAC_PCU_SLP1) 1629b7d5e03cSMatthew Dillon #define AR_SLEEP1_ASSUME_DTIM 0x00080000 // Assume DTIM on missed beacon 1630b7d5e03cSMatthew Dillon #define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000 // Cab timeout(TU) mask 1631b7d5e03cSMatthew Dillon #define AR_SLEEP1_CAB_TIMEOUT_S 21 // Cab timeout(TU) shift 1632b7d5e03cSMatthew Dillon 1633b7d5e03cSMatthew Dillon /* Enhanced sleep control 2 */ 1634b7d5e03cSMatthew Dillon #define AR_SLEEP2 AR_MAC_PCU_OFFSET(MAC_PCU_SLP2) 1635b7d5e03cSMatthew Dillon #define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 // Beacon timeout(TU) mask 1636b7d5e03cSMatthew Dillon #define AR_SLEEP2_BEACON_TIMEOUT_S 21 // Beacon timeout(TU) shift 1637b7d5e03cSMatthew Dillon 1638b7d5e03cSMatthew Dillon /*MAC_PCU_SELF_GEN_DEFAULT*/ 1639b7d5e03cSMatthew Dillon #define AR_SELFGEN AR_MAC_PCU_OFFSET(MAC_PCU_SELF_GEN_DEFAULT) 1640b7d5e03cSMatthew Dillon #define AR_MMSS 0x00000007 1641b7d5e03cSMatthew Dillon #define AR_MMSS_S 0 1642b7d5e03cSMatthew Dillon #define AR_SELFGEN_MMSS_NO RESTRICTION 0 1643b7d5e03cSMatthew Dillon #define AR_SELFGEN_MMSS_ONEOVER4_us 1 1644b7d5e03cSMatthew Dillon #define AR_SELFGEN_MMSS_ONEOVER2_us 2 1645b7d5e03cSMatthew Dillon #define AR_SELFGEN_MMSS_ONE_us 3 1646b7d5e03cSMatthew Dillon #define AR_SELFGEN_MMSS_TWO_us 4 1647b7d5e03cSMatthew Dillon #define AR_SELFGEN_MMSS_FOUR_us 5 1648b7d5e03cSMatthew Dillon #define AR_SELFGEN_MMSS_EIGHT_us 6 1649b7d5e03cSMatthew Dillon #define AR_SELFGEN_MMSS_SIXTEEN_us 7 1650b7d5e03cSMatthew Dillon 1651b7d5e03cSMatthew Dillon #define AR_CEC 0x00000018 1652b7d5e03cSMatthew Dillon #define AR_CEC_S 3 1653b7d5e03cSMatthew Dillon /* Although in original standard 0 is for 1 stream and 1 is for 2 stream */ 1654b7d5e03cSMatthew Dillon /* due to H/W resaon, Here should set 1 for 1 stream and 2 for 2 stream */ 1655b7d5e03cSMatthew Dillon #define AR_SELFGEN_CEC_ONE_SPACETIMESTREAM 1 1656b7d5e03cSMatthew Dillon #define AR_SELFGEN_CEC_TWO_SPACETIMESTREAM 2 1657b7d5e03cSMatthew Dillon 1658b7d5e03cSMatthew Dillon /* BSSID mask lower 32 bits */ 1659b7d5e03cSMatthew Dillon #define AR_BSSMSKL AR_MAC_PCU_OFFSET(MAC_PCU_ADDR1_MASK_L32) 1660b7d5e03cSMatthew Dillon /* BSSID mask upper 16 bits */ 1661b7d5e03cSMatthew Dillon #define AR_BSSMSKU AR_MAC_PCU_OFFSET(MAC_PCU_ADDR1_MASK_U16) 1662b7d5e03cSMatthew Dillon 1663b7d5e03cSMatthew Dillon /* Transmit power control for gen frames */ 1664b7d5e03cSMatthew Dillon #define AR_TPC AR_MAC_PCU_OFFSET(MAC_PCU_TPC) 1665b7d5e03cSMatthew Dillon #define AR_TPC_ACK 0x0000003f // ack frames mask 1666b7d5e03cSMatthew Dillon #define AR_TPC_ACK_S 0x00 // ack frames shift 1667b7d5e03cSMatthew Dillon #define AR_TPC_CTS 0x00003f00 // cts frames mask 1668b7d5e03cSMatthew Dillon #define AR_TPC_CTS_S 0x08 // cts frames shift 1669b7d5e03cSMatthew Dillon #define AR_TPC_CHIRP 0x003f0000 // chirp frames mask 1670b7d5e03cSMatthew Dillon #define AR_TPC_CHIRP_S 16 // chirp frames shift 1671b7d5e03cSMatthew Dillon #define AR_TPC_RPT 0x3f000000 // rpt frames mask 1672b7d5e03cSMatthew Dillon #define AR_TPC_RPT_S 24 // rpt frames shift 1673b7d5e03cSMatthew Dillon 1674b7d5e03cSMatthew Dillon /* Profile count transmit frames */ 1675b7d5e03cSMatthew Dillon #define AR_TFCNT AR_MAC_PCU_OFFSET(MAC_PCU_TX_FRAME_CNT) 1676b7d5e03cSMatthew Dillon /* Profile count receive frames */ 1677b7d5e03cSMatthew Dillon #define AR_RFCNT AR_MAC_PCU_OFFSET(MAC_PCU_RX_FRAME_CNT) 1678b7d5e03cSMatthew Dillon /* Profile count receive clear */ 1679b7d5e03cSMatthew Dillon #define AR_RCCNT AR_MAC_PCU_OFFSET(MAC_PCU_RX_CLEAR_CNT) 1680b7d5e03cSMatthew Dillon /* Profile count cycle counter */ 1681b7d5e03cSMatthew Dillon #define AR_CCCNT AR_MAC_PCU_OFFSET(MAC_PCU_CYCLE_CNT) 1682b7d5e03cSMatthew Dillon 1683b7d5e03cSMatthew Dillon /* Quiet time programming for TGh */ 1684b7d5e03cSMatthew Dillon #define AR_QUIET1 AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1) 1685b7d5e03cSMatthew Dillon #define AR_QUIET1_NEXT_QUIET_S 0 // TSF of next quiet period (TU) 1686b7d5e03cSMatthew Dillon #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff 1687b7d5e03cSMatthew Dillon #define AR_QUIET1_QUIET_ENABLE 0x00010000 // Enable Quiet time operation 1688b7d5e03cSMatthew Dillon #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 // ack/cts in quiet period 1689b7d5e03cSMatthew Dillon #define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17 1690b7d5e03cSMatthew Dillon #define AR_QUIET2 AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_2) 1691b7d5e03cSMatthew Dillon #define AR_QUIET2_QUIET_PERIOD_S 0 // Periodicity of quiet period (TU) 1692b7d5e03cSMatthew Dillon #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff 1693b7d5e03cSMatthew Dillon #define AR_QUIET2_QUIET_DUR_S 16 // quiet period (TU) 1694b7d5e03cSMatthew Dillon #define AR_QUIET2_QUIET_DUR 0xffff0000 1695b7d5e03cSMatthew Dillon 1696b7d5e03cSMatthew Dillon /* locate no_ack in qos */ 1697b7d5e03cSMatthew Dillon #define AR_QOS_NO_ACK AR_MAC_PCU_OFFSET(MAC_PCU_QOS_NO_ACK) 1698b7d5e03cSMatthew Dillon #define AR_QOS_NO_ACK_TWO_BIT 0x0000000f // 2 bit sentinel for no-ack 1699b7d5e03cSMatthew Dillon #define AR_QOS_NO_ACK_TWO_BIT_S 0 1700b7d5e03cSMatthew Dillon #define AR_QOS_NO_ACK_BIT_OFF 0x00000070 // offset for no-ack 1701b7d5e03cSMatthew Dillon #define AR_QOS_NO_ACK_BIT_OFF_S 4 1702b7d5e03cSMatthew Dillon #define AR_QOS_NO_ACK_BYTE_OFF 0x00000180 // from end of header 1703b7d5e03cSMatthew Dillon #define AR_QOS_NO_ACK_BYTE_OFF_S 7 1704b7d5e03cSMatthew Dillon 1705b7d5e03cSMatthew Dillon /* Phy errors to be filtered */ 1706b7d5e03cSMatthew Dillon #define AR_PHY_ERR AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERROR_MASK) 1707b7d5e03cSMatthew Dillon /* XXX validate! XXX */ 1708b7d5e03cSMatthew Dillon #define AR_PHY_ERR_DCHIRP 0x00000008 // Bit 3 enables double chirp 1709b7d5e03cSMatthew Dillon #define AR_PHY_ERR_RADAR 0x00000020 // Bit 5 is Radar signal 1710b7d5e03cSMatthew Dillon #define AR_PHY_ERR_OFDM_TIMING 0x00020000 // Bit 17 is AH_FALSE detect for OFDM 1711b7d5e03cSMatthew Dillon #define AR_PHY_ERR_CCK_TIMING 0x02000000 // Bit 25 is AH_FALSE detect for CCK 1712b7d5e03cSMatthew Dillon 1713b7d5e03cSMatthew Dillon /* MAC PCU extended range latency */ 1714b7d5e03cSMatthew Dillon #define AR_XRLAT AR_MAC_PCU_OFFSET(MAC_PCU_XRLAT) 1715b7d5e03cSMatthew Dillon 1716b7d5e03cSMatthew Dillon /* MAC PCU Receive Buffer settings */ 1717b7d5e03cSMatthew Dillon #define AR_RXFIFO_CFG AR_MAC_PCU_OFFSET(MAC_PCU_RXBUF) 1718b7d5e03cSMatthew Dillon #define AR_RXFIFO_CFG_REG_RD_ENA_S 11 1719b7d5e03cSMatthew Dillon #define AR_RXFIFO_CFG_REG_RD_ENA (0x1 << AR_RXFIFO_CFG_REG_RD_ENA_S) 1720b7d5e03cSMatthew Dillon 1721b7d5e03cSMatthew Dillon /* MAC PCU QoS control */ 1722b7d5e03cSMatthew Dillon #define AR_MIC_QOS_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_MIC_QOS_CONTROL) 1723b7d5e03cSMatthew Dillon /* MAC PCU Michael QoS select */ 1724b7d5e03cSMatthew Dillon #define AR_MIC_QOS_SELECT AR_MAC_PCU_OFFSET(MAC_PCU_MIC_QOS_SELECT) 1725b7d5e03cSMatthew Dillon 1726b7d5e03cSMatthew Dillon /* PCU Miscellaneous Mode */ 1727b7d5e03cSMatthew Dillon #define AR_PCU_MISC AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE) 1728b7d5e03cSMatthew Dillon #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 // force bssid to match 1729b7d5e03cSMatthew Dillon #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 // tx/rx mic key are together 1730b7d5e03cSMatthew Dillon #define AR_PCU_TX_ADD_TSF 0x00000008 // add tx_tsf + int_tsf 1731b7d5e03cSMatthew Dillon #define AR_PCU_CCK_SIFS_MODE 0x00000010 // assume 11b sifs programmed 1732b7d5e03cSMatthew Dillon #define AR_PCU_RX_ANT_UPDT 0x00000800 // KC_RX_ANT_UPDATE 1733b7d5e03cSMatthew Dillon #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 // enforce txop / tbtt 1734b7d5e03cSMatthew Dillon #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 // count bmiss's when sleeping 1735b7d5e03cSMatthew Dillon #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 // use rx_clear to count sifs 1736b7d5e03cSMatthew Dillon #define AR_PCU_FORCE_QUIET_COLL 0x00040000 // kill xmit for channel change 1737b7d5e03cSMatthew Dillon #define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 1738b7d5e03cSMatthew Dillon #define AR_PCU_BT_ANT_PREVENT_RX_S 20 1739b7d5e03cSMatthew Dillon #define AR_PCU_TBTT_PROTECT 0x00200000 // no xmit upto tbtt + 20 uS 1740b7d5e03cSMatthew Dillon #define AR_PCU_CLEAR_VMF 0x01000000 // clear vmf mode (fast cc) 1741b7d5e03cSMatthew Dillon #define AR_PCU_CLEAR_BA_VALID 0x04000000 // clear ba state 1742b7d5e03cSMatthew Dillon #define AR_PCU_SEL_EVM 0x08000000 // select EVM data or PLCP header 1743b7d5e03cSMatthew Dillon #define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000 /* always perform key search */ 1744b7d5e03cSMatthew Dillon /* count of filtered ofdm */ 1745b7d5e03cSMatthew Dillon #define AR_FILT_OFDM AR_MAC_PCU_OFFSET(MAC_PCU_FILTER_OFDM_CNT) 1746b7d5e03cSMatthew Dillon #define AR_FILT_OFDM_COUNT 0x00FFFFFF // count of filtered ofdm 1747b7d5e03cSMatthew Dillon 1748b7d5e03cSMatthew Dillon /* count of filtered cck */ 1749b7d5e03cSMatthew Dillon #define AR_FILT_CCK AR_MAC_PCU_OFFSET(MAC_PCU_FILTER_CCK_CNT) 1750b7d5e03cSMatthew Dillon #define AR_FILT_CCK_COUNT 0x00FFFFFF // count of filtered cck 1751b7d5e03cSMatthew Dillon 1752b7d5e03cSMatthew Dillon /* MAC PCU PHY error counter 1 */ 1753b7d5e03cSMatthew Dillon #define AR_PHY_ERR_1 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_1) 1754b7d5e03cSMatthew Dillon #define AR_PHY_ERR_1_COUNT 0x00FFFFFF // phy errs that pass mask_1 1755b7d5e03cSMatthew Dillon /* MAC PCU PHY error mask 1 */ 1756b7d5e03cSMatthew Dillon #define AR_PHY_ERR_MASK_1 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_1_MASK) 1757b7d5e03cSMatthew Dillon 1758b7d5e03cSMatthew Dillon /* MAC PCU PHY error counter 2 */ 1759b7d5e03cSMatthew Dillon #define AR_PHY_ERR_2 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_2) 1760b7d5e03cSMatthew Dillon #define AR_PHY_ERR_2_COUNT 0x00FFFFFF // phy errs that pass mask_2 1761b7d5e03cSMatthew Dillon /* MAC PCU PHY error mask 2 */ 1762b7d5e03cSMatthew Dillon #define AR_PHY_ERR_MASK_2 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_2_MASK) 1763b7d5e03cSMatthew Dillon 1764b7d5e03cSMatthew Dillon #define AR_PHY_COUNTMAX (3 << 22) // Max counted before intr 1765b7d5e03cSMatthew Dillon #define AR_MIBCNT_INTRMASK (3 << 22) // Mask top 2 bits of counters 1766b7d5e03cSMatthew Dillon 1767b7d5e03cSMatthew Dillon /* interrupt if rx_tsf-int_tsf */ 1768b7d5e03cSMatthew Dillon #define AR_TSFOOR_THRESHOLD AR_MAC_PCU_OFFSET(MAC_PCU_TSF_THRESHOLD) 1769b7d5e03cSMatthew Dillon #define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF // field width 1770b7d5e03cSMatthew Dillon 1771b7d5e03cSMatthew Dillon /* MAC PCU PHY error counter 3 */ 1772b7d5e03cSMatthew Dillon #define AR_PHY_ERR_3 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_3) 1773b7d5e03cSMatthew Dillon #define AR_PHY_ERR_3_COUNT 0x00FFFFFF // phy errs that pass mask_3 1774b7d5e03cSMatthew Dillon /* MAC PCU PHY error mask 3 */ 1775b7d5e03cSMatthew Dillon #define AR_PHY_ERR_MASK_3 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_3_MASK) 1776b7d5e03cSMatthew Dillon 1777b7d5e03cSMatthew Dillon /* Bluetooth coexistance mode */ 1778b7d5e03cSMatthew Dillon #define AR_BT_COEX_MODE AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_MODE) 1779b7d5e03cSMatthew Dillon #define AR_BT_TIME_EXTEND 0x000000ff 1780b7d5e03cSMatthew Dillon #define AR_BT_TIME_EXTEND_S 0 1781b7d5e03cSMatthew Dillon #define AR_BT_TXSTATE_EXTEND 0x00000100 1782b7d5e03cSMatthew Dillon #define AR_BT_TXSTATE_EXTEND_S 8 1783b7d5e03cSMatthew Dillon #define AR_BT_TX_FRAME_EXTEND 0x00000200 1784b7d5e03cSMatthew Dillon #define AR_BT_TX_FRAME_EXTEND_S 9 1785b7d5e03cSMatthew Dillon #define AR_BT_MODE 0x00000c00 1786b7d5e03cSMatthew Dillon #define AR_BT_MODE_S 10 1787b7d5e03cSMatthew Dillon #define AR_BT_QUIET 0x00001000 1788b7d5e03cSMatthew Dillon #define AR_BT_QUIET_S 12 1789b7d5e03cSMatthew Dillon #define AR_BT_QCU_THRESH 0x0001e000 1790b7d5e03cSMatthew Dillon #define AR_BT_QCU_THRESH_S 13 1791b7d5e03cSMatthew Dillon #define AR_BT_RX_CLEAR_POLARITY 0x00020000 1792b7d5e03cSMatthew Dillon #define AR_BT_RX_CLEAR_POLARITY_S 17 1793b7d5e03cSMatthew Dillon #define AR_BT_PRIORITY_TIME 0x00fc0000 1794b7d5e03cSMatthew Dillon #define AR_BT_PRIORITY_TIME_S 18 1795b7d5e03cSMatthew Dillon #define AR_BT_FIRST_SLOT_TIME 0xff000000 1796b7d5e03cSMatthew Dillon #define AR_BT_FIRST_SLOT_TIME_S 24 1797b7d5e03cSMatthew Dillon 1798b7d5e03cSMatthew Dillon /* BlueTooth coexistance WLAN weights */ 1799b7d5e03cSMatthew Dillon #define AR_BT_COEX_WL_WEIGHTS0 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_WL_WEIGHTS0) 1800b7d5e03cSMatthew Dillon #define AR_BT_BT_WGHT 0x0000ffff 1801b7d5e03cSMatthew Dillon #define AR_BT_BT_WGHT_S 0 1802b7d5e03cSMatthew Dillon #define AR_BT_WL_WGHT 0xffff0000 1803b7d5e03cSMatthew Dillon #define AR_BT_WL_WGHT_S 16 1804b7d5e03cSMatthew Dillon 1805b7d5e03cSMatthew Dillon /* HCF timeout: Slotted behavior */ 1806b7d5e03cSMatthew Dillon #define AR_HCFTO AR_MAC_PCU_OFFSET(MAC_PCU_HCF_TIMEOUT) 1807b7d5e03cSMatthew Dillon 1808b7d5e03cSMatthew Dillon /* BlueTooth mode 2: Slotted behavior */ 1809b7d5e03cSMatthew Dillon #define AR_BT_COEX_MODE2 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_MODE2) 1810b7d5e03cSMatthew Dillon #define AR_BT_BCN_MISS_THRESH 0x000000ff 1811b7d5e03cSMatthew Dillon #define AR_BT_BCN_MISS_THRESH_S 0 1812b7d5e03cSMatthew Dillon #define AR_BT_BCN_MISS_CNT 0x0000ff00 1813b7d5e03cSMatthew Dillon #define AR_BT_BCN_MISS_CNT_S 8 1814b7d5e03cSMatthew Dillon #define AR_BT_HOLD_RX_CLEAR 0x00010000 1815b7d5e03cSMatthew Dillon #define AR_BT_HOLD_RX_CLEAR_S 16 1816b7d5e03cSMatthew Dillon #define AR_BT_SLEEP_ALLOW_BT 0x00020000 1817b7d5e03cSMatthew Dillon #define AR_BT_SLEEP_ALLOW_BT_S 17 1818b7d5e03cSMatthew Dillon #define AR_BT_PROTECT_AFTER_WAKE 0x00080000 1819b7d5e03cSMatthew Dillon #define AR_BT_PROTECT_AFTER_WAKE_S 19 1820b7d5e03cSMatthew Dillon #define AR_BT_DISABLE_BT_ANT 0x00100000 1821b7d5e03cSMatthew Dillon #define AR_BT_DISABLE_BT_ANT_S 20 1822b7d5e03cSMatthew Dillon #define AR_BT_QUIET_2_WIRE 0x00200000 1823b7d5e03cSMatthew Dillon #define AR_BT_QUIET_2_WIRE_S 21 1824b7d5e03cSMatthew Dillon #define AR_BT_WL_ACTIVE_MODE 0x00c00000 1825b7d5e03cSMatthew Dillon #define AR_BT_WL_ACTIVE_MODE_S 22 1826b7d5e03cSMatthew Dillon #define AR_BT_WL_TXRX_SEPARATE 0x01000000 1827b7d5e03cSMatthew Dillon #define AR_BT_WL_TXRX_SEPARATE_S 24 1828b7d5e03cSMatthew Dillon #define AR_BT_RS_DISCARD_EXTEND 0x02000000 1829b7d5e03cSMatthew Dillon #define AR_BT_RS_DISCARD_EXTEND_S 25 1830b7d5e03cSMatthew Dillon #define AR_BT_TSF_BT_ACTIVE_CTRL 0x0c000000 1831b7d5e03cSMatthew Dillon #define AR_BT_TSF_BT_ACTIVE_CTRL_S 26 1832b7d5e03cSMatthew Dillon #define AR_BT_TSF_BT_PRIORITY_CTRL 0x30000000 1833b7d5e03cSMatthew Dillon #define AR_BT_TSF_BT_PRIORITY_CTRL_S 28 1834b7d5e03cSMatthew Dillon #define AR_BT_INTERRUPT_ENABLE 0x40000000 1835b7d5e03cSMatthew Dillon #define AR_BT_INTERRUPT_ENABLE_S 30 1836b7d5e03cSMatthew Dillon #define AR_BT_PHY_ERR_BT_COLL_ENABLE 0x80000000 1837b7d5e03cSMatthew Dillon #define AR_BT_PHY_ERR_BT_COLL_ENABLE_S 31 1838b7d5e03cSMatthew Dillon 1839b7d5e03cSMatthew Dillon /* Generic Timers 2 */ 1840b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_0 AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS2) 1841b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_NEXT(_i) (AR_GEN_TIMERS2_0 + ((_i)<<2)) 1842b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_PERIOD(_i) (AR_GEN_TIMERS2_NEXT(8) + ((_i)<<2)) 1843b7d5e03cSMatthew Dillon 1844b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_0_NEXT AR_GEN_TIMERS2_NEXT(0) 1845b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_1_NEXT AR_GEN_TIMERS2_NEXT(1) 1846b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_2_NEXT AR_GEN_TIMERS2_NEXT(2) 1847b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_3_NEXT AR_GEN_TIMERS2_NEXT(3) 1848b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_4_NEXT AR_GEN_TIMERS2_NEXT(4) 1849b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_5_NEXT AR_GEN_TIMERS2_NEXT(5) 1850b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_6_NEXT AR_GEN_TIMERS2_NEXT(6) 1851b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_7_NEXT AR_GEN_TIMERS2_NEXT(7) 1852b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_0_PERIOD AR_GEN_TIMERS2_PERIOD(0) 1853b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_1_PERIOD AR_GEN_TIMERS2_PERIOD(1) 1854b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_2_PERIOD AR_GEN_TIMERS2_PERIOD(2) 1855b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_3_PERIOD AR_GEN_TIMERS2_PERIOD(3) 1856b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_4_PERIOD AR_GEN_TIMERS2_PERIOD(4) 1857b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_5_PERIOD AR_GEN_TIMERS2_PERIOD(5) 1858b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_6_PERIOD AR_GEN_TIMERS2_PERIOD(6) 1859b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_7_PERIOD AR_GEN_TIMERS2_PERIOD(7) 1860b7d5e03cSMatthew Dillon 1861b7d5e03cSMatthew Dillon #define AR_GEN_TIMER_BANK_1_LEN 8 1862b7d5e03cSMatthew Dillon #define AR_FIRST_NDP_TIMER 7 1863b7d5e03cSMatthew Dillon #define AR_NUM_GEN_TIMERS 16 1864b7d5e03cSMatthew Dillon #define AR_GEN_TIMER_RESERVED 8 1865b7d5e03cSMatthew Dillon 1866b7d5e03cSMatthew Dillon /* Generic Timers 2 Mode */ 1867b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS2_MODE AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS2_MODE) 1868b7d5e03cSMatthew Dillon 1869b7d5e03cSMatthew Dillon /* BlueTooth coexistance WLAN weights 1 */ 1870b7d5e03cSMatthew Dillon #define AR_BT_COEX_WL_WEIGHTS1 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_WL_WEIGHTS1) 1871b7d5e03cSMatthew Dillon 1872b7d5e03cSMatthew Dillon /* BlueTooth Coexistence TSF Snapshot for BT_ACTIVE */ 1873b7d5e03cSMatthew Dillon #define AR_BT_TSF_ACTIVE AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE) 1874b7d5e03cSMatthew Dillon 1875b7d5e03cSMatthew Dillon /* BlueTooth Coexistence TSF Snapshot for BT_PRIORITY */ 1876b7d5e03cSMatthew Dillon #define AR_BT_TSF_PRIORITY AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY) 1877b7d5e03cSMatthew Dillon 1878b7d5e03cSMatthew Dillon /* SIFS, TX latency and ACK shift */ 1879b7d5e03cSMatthew Dillon #define AR_TXSIFS AR_MAC_PCU_OFFSET(MAC_PCU_TXSIFS) 1880b7d5e03cSMatthew Dillon #define AR_TXSIFS_TIME 0x000000FF // uS in SIFS 1881b7d5e03cSMatthew Dillon #define AR_TXSIFS_TX_LATENCY 0x00000F00 // uS for transmission thru bb 1882b7d5e03cSMatthew Dillon #define AR_TXSIFS_TX_LATENCY_S 8 1883b7d5e03cSMatthew Dillon #define AR_TXSIFS_ACK_SHIFT 0x00007000 // chan width for ack 1884b7d5e03cSMatthew Dillon #define AR_TXSIFS_ACK_SHIFT_S 12 1885b7d5e03cSMatthew Dillon 1886b7d5e03cSMatthew Dillon /* BlueTooth mode 3 */ 1887b7d5e03cSMatthew Dillon #define AR_BT_COEX_MODE3 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_MODE3) 1888b7d5e03cSMatthew Dillon 1889b7d5e03cSMatthew Dillon 1890b7d5e03cSMatthew Dillon /* TXOP for legacy non-qos */ 1891b7d5e03cSMatthew Dillon #define AR_TXOP_X AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_X) 1892b7d5e03cSMatthew Dillon #define AR_TXOP_X_VAL 0x000000FF 1893b7d5e03cSMatthew Dillon 1894b7d5e03cSMatthew Dillon /* TXOP for TID 0 to 3 */ 1895b7d5e03cSMatthew Dillon #define AR_TXOP_0_3 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_0_3) 1896b7d5e03cSMatthew Dillon /* TXOP for TID 4 to 7 */ 1897b7d5e03cSMatthew Dillon #define AR_TXOP_4_7 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_4_7) 1898b7d5e03cSMatthew Dillon /* TXOP for TID 8 to 11 */ 1899b7d5e03cSMatthew Dillon #define AR_TXOP_8_11 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_8_11) 1900b7d5e03cSMatthew Dillon /* TXOP for TID 12 to 15 */ 1901b7d5e03cSMatthew Dillon #define AR_TXOP_12_15 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_12_15) 1902b7d5e03cSMatthew Dillon 1903b7d5e03cSMatthew Dillon /* Generic Timers */ 1904b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS_0 AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS) 1905b7d5e03cSMatthew Dillon #define AR_GEN_TIMERS(_i) (AR_GEN_TIMERS_0 + ((_i)<<2)) 1906b7d5e03cSMatthew Dillon 1907b7d5e03cSMatthew Dillon /* generic timers based on tsf - all uS */ 1908b7d5e03cSMatthew Dillon #define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0) 1909b7d5e03cSMatthew Dillon #define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMERS(1) 1910b7d5e03cSMatthew Dillon #define AR_NEXT_SWBA AR_GEN_TIMERS(2) 1911b7d5e03cSMatthew Dillon #define AR_NEXT_HCF AR_GEN_TIMERS(3) 1912b7d5e03cSMatthew Dillon #define AR_NEXT_TIM AR_GEN_TIMERS(4) 1913b7d5e03cSMatthew Dillon #define AR_NEXT_DTIM AR_GEN_TIMERS(5) 1914b7d5e03cSMatthew Dillon #define AR_NEXT_QUIET_TIMER AR_GEN_TIMERS(6) 1915b7d5e03cSMatthew Dillon #define AR_NEXT_NDP_TIMER AR_GEN_TIMERS(7) 1916b7d5e03cSMatthew Dillon #define AR_BEACON_PERIOD AR_GEN_TIMERS(8) 1917b7d5e03cSMatthew Dillon #define AR_DMA_BEACON_PERIOD AR_GEN_TIMERS(9) 1918b7d5e03cSMatthew Dillon #define AR_SWBA_PERIOD AR_GEN_TIMERS(10) 1919b7d5e03cSMatthew Dillon #define AR_HCF_PERIOD AR_GEN_TIMERS(11) 1920b7d5e03cSMatthew Dillon #define AR_TIM_PERIOD AR_GEN_TIMERS(12) 1921b7d5e03cSMatthew Dillon #define AR_DTIM_PERIOD AR_GEN_TIMERS(13) 1922b7d5e03cSMatthew Dillon #define AR_QUIET_PERIOD AR_GEN_TIMERS(14) 1923b7d5e03cSMatthew Dillon #define AR_NDP_PERIOD AR_GEN_TIMERS(15) 1924b7d5e03cSMatthew Dillon 1925b7d5e03cSMatthew Dillon /* Generic Timers Mode */ 1926b7d5e03cSMatthew Dillon #define AR_TIMER_MODE AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS_MODE) 1927b7d5e03cSMatthew Dillon #define AR_TBTT_TIMER_EN 0x00000001 1928b7d5e03cSMatthew Dillon #define AR_DBA_TIMER_EN 0x00000002 1929b7d5e03cSMatthew Dillon #define AR_SWBA_TIMER_EN 0x00000004 1930b7d5e03cSMatthew Dillon #define AR_HCF_TIMER_EN 0x00000008 1931b7d5e03cSMatthew Dillon #define AR_TIM_TIMER_EN 0x00000010 1932b7d5e03cSMatthew Dillon #define AR_DTIM_TIMER_EN 0x00000020 1933b7d5e03cSMatthew Dillon #define AR_QUIET_TIMER_EN 0x00000040 1934b7d5e03cSMatthew Dillon #define AR_NDP_TIMER_EN 0x00000080 1935b7d5e03cSMatthew Dillon #define AR_TIMER_OVERFLOW_INDEX 0x00000700 1936b7d5e03cSMatthew Dillon #define AR_TIMER_OVERFLOW_INDEX_S 8 1937b7d5e03cSMatthew Dillon #define AR_TIMER_THRESH 0xFFFFF000 1938b7d5e03cSMatthew Dillon #define AR_TIMER_THRESH_S 12 1939b7d5e03cSMatthew Dillon 1940b7d5e03cSMatthew Dillon #define AR_SLP32_MODE AR_MAC_PCU_OFFSET(MAC_PCU_SLP32_MODE) 1941b7d5e03cSMatthew Dillon #define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF // rising <-> falling edge 1942b7d5e03cSMatthew Dillon #define AR_SLP32_ENA 0x00100000 1943b7d5e03cSMatthew Dillon #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 // tsf update in progress 1944b7d5e03cSMatthew Dillon 1945b7d5e03cSMatthew Dillon #define AR_SLP32_WAKE AR_MAC_PCU_OFFSET(MAC_PCU_SLP32_WAKE) 1946b7d5e03cSMatthew Dillon #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF // time to wake crystal 1947b7d5e03cSMatthew Dillon 1948b7d5e03cSMatthew Dillon #define AR_SLP32_INC AR_MAC_PCU_OFFSET(MAC_PCU_SLP32_INC) 1949b7d5e03cSMatthew Dillon #define AR_SLP32_TST_INC 0x000FFFFF 1950b7d5e03cSMatthew Dillon 1951b7d5e03cSMatthew Dillon /* Sleep MIB cycle count 32kHz cycles for which mac is asleep */ 1952b7d5e03cSMatthew Dillon #define AR_SLP_CNT AR_MAC_PCU_OFFSET(MAC_PCU_SLP_MIB1) 1953b7d5e03cSMatthew Dillon #define AR_SLP_CYCLE_CNT 0x8254 // absolute number of 32kHz cycles 1954b7d5e03cSMatthew Dillon 1955b7d5e03cSMatthew Dillon /* Sleep MIB cycle count 2 */ 1956b7d5e03cSMatthew Dillon #define AR_SLP_MIB2 AR_MAC_PCU_OFFSET(MAC_PCU_SLP_MIB2) 1957b7d5e03cSMatthew Dillon 1958b7d5e03cSMatthew Dillon /* Sleep MIB control status */ 1959b7d5e03cSMatthew Dillon #define AR_SLP_MIB_CTRL AR_MAC_PCU_OFFSET(MAC_PCU_SLP_MIB3) 1960b7d5e03cSMatthew Dillon #define AR_SLP_MIB_CLEAR 0x00000001 // clear pending 1961b7d5e03cSMatthew Dillon #define AR_SLP_MIB_PENDING 0x00000002 // clear counters 1962b7d5e03cSMatthew Dillon 1963b7d5e03cSMatthew Dillon //#ifdef AR9300_EMULATION 1964b7d5e03cSMatthew Dillon // MAC trace buffer registers (emulation only) 1965b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER AR_MAC_PCU_OFFSET(MAC_PCU_LOGIC_ANALYZER) 1966b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_CTL 0x0000000F 1967b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_HOLD 0x00000001 1968b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_CLEAR 0x00000002 1969b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_STATE 0x00000004 1970b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_ENABLE 0x00000008 1971b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL 0x000000F0 1972b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL_S 4 1973b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR 0x0003FF00 1974b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR_S 8 1975b7d5e03cSMatthew Dillon 1976b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE 0xFFFC0000 1977b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_S 18 1978b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20614 0x00040000 1979b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 1980b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20803 0x40000000 1981b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996 0x9d500010 1982b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE 0x9d400010 1983b7d5e03cSMatthew Dillon 1984b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_32L AR_MAC_PCU_OFFSET(MAC_PCU_LOGIC_ANALYZER_32L) 1985b7d5e03cSMatthew Dillon #define AR_MAC_PCU_LOGIC_ANALYZER_16U AR_MAC_PCU_OFFSET(MAC_PCU_LOGIC_ANALYZER_16U) 1986b7d5e03cSMatthew Dillon 1987b7d5e03cSMatthew Dillon #define AR_MAC_PCU_TRACE_REG_START 0xE000 1988b7d5e03cSMatthew Dillon #define AR_MAC_PCU_TRACE_REG_END 0xFFFC 1989b7d5e03cSMatthew Dillon #define AR_MAC_PCU_TRACE_BUFFER_LENGTH (AR_MAC_PCU_TRACE_REG_END - AR_MAC_PCU_TRACE_REG_START + sizeof(uint32_t)) 1990b7d5e03cSMatthew Dillon //#endif // AR9300_EMULATION 1991b7d5e03cSMatthew Dillon 1992b7d5e03cSMatthew Dillon /* MAC PCU global mode register */ 1993b7d5e03cSMatthew Dillon #define AR_2040_MODE AR_MAC_PCU_OFFSET(MAC_PCU_20_40_MODE) 1994b7d5e03cSMatthew Dillon #define AR_2040_JOINED_RX_CLEAR 0x00000001 // use ctl + ext rx_clear for cca 1995b7d5e03cSMatthew Dillon 1996b7d5e03cSMatthew Dillon /* MAC PCU H transfer timeout register */ 1997b7d5e03cSMatthew Dillon #define AR_H_XFER_TIMEOUT AR_MAC_PCU_OFFSET(MAC_PCU_H_XFER_TIMEOUT) 1998b7d5e03cSMatthew Dillon #define AR_EXBF_IMMDIATE_RESP 0x00000040 1999b7d5e03cSMatthew Dillon #define AR_EXBF_NOACK_NO_RPT 0x00000100 2000b7d5e03cSMatthew Dillon #define AR_H_XFER_TIMEOUT_COUNT 0xf 2001b7d5e03cSMatthew Dillon #define AR_H_XFER_TIMEOUT_COUNT_S 0 2002b7d5e03cSMatthew Dillon 2003b7d5e03cSMatthew Dillon /* 2004b7d5e03cSMatthew Dillon * Additional cycle counter. See also AR_CCCNT 2005b7d5e03cSMatthew Dillon * extension channel rx clear count 2006b7d5e03cSMatthew Dillon * counts number of cycles rx_clear (ext) is low (i.e. busy) 2007b7d5e03cSMatthew Dillon * when the MAC is not actively transmitting/receiving 2008b7d5e03cSMatthew Dillon */ 2009b7d5e03cSMatthew Dillon #define AR_EXTRCCNT AR_MAC_PCU_OFFSET(MAC_PCU_RX_CLEAR_DIFF_CNT) 2010b7d5e03cSMatthew Dillon 2011b7d5e03cSMatthew Dillon /* antenna mask for self generated files */ 2012b7d5e03cSMatthew Dillon #define AR_SELFGEN_MASK AR_MAC_PCU_OFFSET(MAC_PCU_SELF_GEN_ANTENNA_MASK) 2013b7d5e03cSMatthew Dillon 2014b7d5e03cSMatthew Dillon /* control registers for block BA control fields */ 2015b7d5e03cSMatthew Dillon #define AR_BA_BAR_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_BA_BAR_CONTROL) 2016b7d5e03cSMatthew Dillon 2017b7d5e03cSMatthew Dillon /* legacy PLCP spoof */ 2018b7d5e03cSMatthew Dillon #define AR_LEG_PLCP_SPOOF AR_MAC_PCU_OFFSET(MAC_PCU_LEGACY_PLCP_SPOOF) 2019b7d5e03cSMatthew Dillon 2020b7d5e03cSMatthew Dillon /* PHY error mask and EIFS mask continued */ 2021b7d5e03cSMatthew Dillon #define AR_PHY_ERR_MASK_CONT AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERROR_MASK_CONT) 2022b7d5e03cSMatthew Dillon 2023b7d5e03cSMatthew Dillon /* MAC PCU transmit timer */ 2024b7d5e03cSMatthew Dillon #define AR_TX_TIMER AR_MAC_PCU_OFFSET(MAC_PCU_TX_TIMER) 2025b7d5e03cSMatthew Dillon 2026b7d5e03cSMatthew Dillon /* MAC PCU transmit buffer control */ 2027b7d5e03cSMatthew Dillon #define AR_PCU_TXBUF_CTRL AR_MAC_PCU_OFFSET(MAC_PCU_TXBUF_CTRL) 2028b7d5e03cSMatthew Dillon #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 2029b7d5e03cSMatthew Dillon #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 2030b7d5e03cSMatthew Dillon 2031b7d5e03cSMatthew Dillon /* 2032b7d5e03cSMatthew Dillon * MAC PCU miscellaneous mode 2 2033b7d5e03cSMatthew Dillon * WAR flags for various bugs, see mac_pcu_reg documentation. 2034b7d5e03cSMatthew Dillon */ 2035b7d5e03cSMatthew Dillon #define AR_PCU_MISC_MODE2 AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE2) 2036b7d5e03cSMatthew Dillon #define AR_PCU_MISC_MODE2_BUG_21532_ENABLE 0x00000001 2037b7d5e03cSMatthew Dillon #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 /* Decrypt MGT frames using MFP method */ 2038b7d5e03cSMatthew Dillon #define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 /* Don't decrypt MGT frames at all */ 2039b7d5e03cSMatthew Dillon 2040b7d5e03cSMatthew Dillon #define AR_BUG_58603_FIX_ENABLE 0x00000008 /* Enable fix for bug 58603. This allows 2041b7d5e03cSMatthew Dillon * the use of AR_AGG_WEP_ENABLE. 2042b7d5e03cSMatthew Dillon */ 2043b7d5e03cSMatthew Dillon 2044b7d5e03cSMatthew Dillon #define AR_PCU_MISC_MODE2_PROM_VC_MODE 0xa148103b /* Enable promiscous in azimuth mode */ 2045b7d5e03cSMatthew Dillon 2046b7d5e03cSMatthew Dillon #define AR_PCU_MISC_MODE2_RESERVED 0x00000038 2047b7d5e03cSMatthew Dillon 2048b7d5e03cSMatthew Dillon #define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search 2049b7d5e03cSMatthew Dillon * based on both MAC Address and Key ID. 2050b7d5e03cSMatthew Dillon * If bit is 0, then Multicast search is 2051b7d5e03cSMatthew Dillon * based on MAC address only. 2052b7d5e03cSMatthew Dillon * For Merlin and above only. 2053b7d5e03cSMatthew Dillon */ 2054b7d5e03cSMatthew Dillon 2055b7d5e03cSMatthew Dillon #define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080 2056b7d5e03cSMatthew Dillon #define AR_PCU_MISC_MODE2_MGMT_QOS 0x0000FF00 2057b7d5e03cSMatthew Dillon #define AR_PCU_MISC_MODE2_MGMT_QOS_S 8 2058b7d5e03cSMatthew Dillon #define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x00010000 2059b7d5e03cSMatthew Dillon #define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature, 2060b7d5e03cSMatthew Dillon * when it is enable, AGG_WEP would takes 2061b7d5e03cSMatthew Dillon * charge of the encryption interface of 2062b7d5e03cSMatthew Dillon * pcu_txsm. 2063b7d5e03cSMatthew Dillon */ 2064b7d5e03cSMatthew Dillon #define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 2065b7d5e03cSMatthew Dillon #define AR_PCU_MISC_MODE2_PROXY_STA 0x01000000 /* see EV 75996 */ 2066b7d5e03cSMatthew Dillon #define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 2067b7d5e03cSMatthew Dillon #define AR_DECOUPLE_DECRYPTION 0x08000000 2068b7d5e03cSMatthew Dillon 2069b7d5e03cSMatthew Dillon #define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000 2070b7d5e03cSMatthew Dillon 2071b7d5e03cSMatthew Dillon /* MAC PCU Alternate AES QoS mute mask */ 2072b7d5e03cSMatthew Dillon #define AR_ALT_AES_MUTE_MASK AR_MAC_PCU_OFFSET(MAC_PCU_ALT_AES_MUTE_MASK) 2073b7d5e03cSMatthew Dillon 2074b7d5e03cSMatthew Dillon /* Async Fifo registers - debug only */ 2075b7d5e03cSMatthew Dillon #define AR_ASYNC_FIFO_1 AR_MAC_PCU_OFFSET(ASYNC_FIFO_REG1) 2076b7d5e03cSMatthew Dillon #define AR_ASYNC_FIFO_2 AR_MAC_PCU_OFFSET(ASYNC_FIFO_REG2) 2077b7d5e03cSMatthew Dillon #define AR_ASYNC_FIFO_3 AR_MAC_PCU_OFFSET(ASYNC_FIFO_REG3) 2078b7d5e03cSMatthew Dillon 2079b7d5e03cSMatthew Dillon /* Maps the 16 user priority TID values to Access categories */ 2080b7d5e03cSMatthew Dillon #define AR_TID_TO_AC_MAP AR_MAC_PCU_OFFSET(MAC_PCU_TID_TO_AC) 2081b7d5e03cSMatthew Dillon 2082b7d5e03cSMatthew Dillon /* High Priority Queue Control */ 2083b7d5e03cSMatthew Dillon #define AR_HP_Q_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_HP_QUEUE) 2084b7d5e03cSMatthew Dillon 2085b7d5e03cSMatthew Dillon /* Rx High Priority Queue Control */ 2086b7d5e03cSMatthew Dillon #define AR_HPQ_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_HP_QUEUE) 2087b7d5e03cSMatthew Dillon #define AR_HPQ_ENABLE 0x00000001 2088b7d5e03cSMatthew Dillon #define AR_HPQ_MASK_BE 0x00000002 2089b7d5e03cSMatthew Dillon #define AR_HPQ_MASK_BK 0x00000004 2090b7d5e03cSMatthew Dillon #define AR_HPQ_MASK_VI 0x00000008 2091b7d5e03cSMatthew Dillon #define AR_HPQ_MASK_VO 0x00000010 2092b7d5e03cSMatthew Dillon #define AR_HPQ_UAPSD 0x00000020 2093b7d5e03cSMatthew Dillon #define AR_HPQ_FRAME_FILTER_0 0x00000040 2094b7d5e03cSMatthew Dillon #define AR_HPQ_FRAME_BSSID_MATCH_0 0x00000080 2095b7d5e03cSMatthew Dillon #define AR_HPQ_UAPSD_TRIGGER_EN 0x00100000 2096b7d5e03cSMatthew Dillon 2097b7d5e03cSMatthew Dillon #define AR_BT_COEX_BT_WEIGHTS0 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS0) 2098b7d5e03cSMatthew Dillon #define AR_BT_COEX_BT_WEIGHTS1 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS1) 2099b7d5e03cSMatthew Dillon #define AR_BT_COEX_BT_WEIGHTS2 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS2) 2100b7d5e03cSMatthew Dillon #define AR_BT_COEX_BT_WEIGHTS3 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS3) 2101b7d5e03cSMatthew Dillon 2102b7d5e03cSMatthew Dillon #define AR_AGC_SATURATION_CNT0 AR_MAC_PCU_OFFSET(MAC_PCU_AGC_SATURATION_CNT0) 2103b7d5e03cSMatthew Dillon #define AR_AGC_SATURATION_CNT1 AR_MAC_PCU_OFFSET(MAC_PCU_AGC_SATURATION_CNT1) 2104b7d5e03cSMatthew Dillon #define AR_AGC_SATURATION_CNT2 AR_MAC_PCU_OFFSET(MAC_PCU_AGC_SATURATION_CNT2) 2105b7d5e03cSMatthew Dillon 2106b7d5e03cSMatthew Dillon /* Hardware beacon processing */ 2107b7d5e03cSMatthew Dillon #define AR_HWBCNPROC1 AR_MAC_PCU_OFFSET(MAC_PCU_HW_BCN_PROC1) 2108b7d5e03cSMatthew Dillon #define AR_HWBCNPROC1_CRC_ENABLE 0x00000001 /* Enable hw beacon processing */ 2109b7d5e03cSMatthew Dillon #define AR_HWBCNPROC1_RESET_CRC 0x00000002 /* Reset the last beacon CRC calculated */ 2110b7d5e03cSMatthew Dillon #define AR_HWBCNPROC1_EXCLUDE_BCN_INTVL 0x00000004 /* Exclude Beacon interval in CRC calculation */ 2111b7d5e03cSMatthew Dillon #define AR_HWBCNPROC1_EXCLUDE_CAP_INFO 0x00000008 /* Exclude Beacon capability information in CRC calculation */ 2112b7d5e03cSMatthew Dillon #define AR_HWBCNPROC1_EXCLUDE_TIM_ELM 0x00000010 /* Exclude Beacon TIM element in CRC calculation */ 2113b7d5e03cSMatthew Dillon #define AR_HWBCNPROC1_EXCLUDE_ELM0 0x00000020 /* Exclude element ID ELM0 in CRC calculation */ 2114b7d5e03cSMatthew Dillon #define AR_HWBCNPROC1_EXCLUDE_ELM1 0x00000040 /* Exclude element ID ELM1 in CRC calculation */ 2115b7d5e03cSMatthew Dillon #define AR_HWBCNPROC1_EXCLUDE_ELM2 0x00000080 /* Exclude element ID ELM2 in CRC calculation */ 2116b7d5e03cSMatthew Dillon #define AR_HWBCNPROC1_ELM0_ID 0x0000FF00 /* Element ID 0 */ 2117b7d5e03cSMatthew Dillon #define AR_HWBCNPROC1_ELM0_ID_S 8 2118b7d5e03cSMatthew Dillon #define AR_HWBCNPROC1_ELM1_ID 0x00FF0000 /* Element ID 1 */ 2119b7d5e03cSMatthew Dillon #define AR_HWBCNPROC1_ELM1_ID_S 16 2120b7d5e03cSMatthew Dillon #define AR_HWBCNPROC1_ELM2_ID 0xFF000000 /* Element ID 2 */ 2121b7d5e03cSMatthew Dillon #define AR_HWBCNPROC1_ELM2_ID_S 24 2122b7d5e03cSMatthew Dillon 2123b7d5e03cSMatthew Dillon #define AR_HWBCNPROC2 AR_MAC_PCU_OFFSET(MAC_PCU_HW_BCN_PROC2) 2124b7d5e03cSMatthew Dillon #define AR_HWBCNPROC2_FILTER_INTERVAL_ENABLE 0x00000001 /* Enable filtering beacons based on filter interval */ 2125b7d5e03cSMatthew Dillon #define AR_HWBCNPROC2_RESET_INTERVAL 0x00000002 /* Reset internal interval counter interval */ 2126b7d5e03cSMatthew Dillon #define AR_HWBCNPROC2_EXCLUDE_ELM3 0x00000004 /* Exclude element ID ELM3 in CRC calculation */ 2127b7d5e03cSMatthew Dillon #define AR_HWBCNPROC2_RSVD 0x000000F8 /* reserved */ 2128b7d5e03cSMatthew Dillon #define AR_HWBCNPROC2_FILTER_INTERVAL 0x0000FF00 /* Filter interval for beacons */ 2129b7d5e03cSMatthew Dillon #define AR_HWBCNPROC2_FILTER_INTERVAL_S 8 2130b7d5e03cSMatthew Dillon #define AR_HWBCNPROC2_ELM3_ID 0x00FF0000 /* Element ID 3 */ 2131b7d5e03cSMatthew Dillon #define AR_HWBCNPROC2_ELM3_ID_S 16 2132b7d5e03cSMatthew Dillon #define AR_HWBCNPROC2_RSVD2 0xFF000000 /* reserved */ 2133b7d5e03cSMatthew Dillon 2134b7d5e03cSMatthew Dillon #define AR_MAC_PCU_MISC_MODE3 AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE3) 2135b7d5e03cSMatthew Dillon #define AR_BUG_61936_FIX_ENABLE 0x00000040 /* EV61936 - rx descriptor corruption */ 2136b7d5e03cSMatthew Dillon #define AR_TIME_BASED_DISCARD_EN 0x80000000 2137b7d5e03cSMatthew Dillon #define AR_TIME_BASED_DISCARD_EN_S 31 2138b7d5e03cSMatthew Dillon 2139b7d5e03cSMatthew Dillon #define AR_MAC_PCU_GEN_TIMER_TSF_SEL AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS_TSF_SEL) 2140b7d5e03cSMatthew Dillon 2141b7d5e03cSMatthew Dillon #define AR_MAC_PCU_TBD_FILTER AR_MAC_PCU_OFFSET(MAC_PCU_TBD_FILTER) 2142b7d5e03cSMatthew Dillon #define AR_MAC_PCU_USE_WBTIMER_TX_TS 0x00000001 2143b7d5e03cSMatthew Dillon #define AR_MAC_PCU_USE_WBTIMER_TX_TS_S 0 2144b7d5e03cSMatthew Dillon #define AR_MAC_PCU_USE_WBTIMER_RX_TS 0x00000002 2145b7d5e03cSMatthew Dillon #define AR_MAC_PCU_USE_WBTIMER_RX_TS_S 1 2146b7d5e03cSMatthew Dillon 2147b7d5e03cSMatthew Dillon #define AR_TXBUF_BA AR_MAC_PCU_OFFSET(MAC_PCU_TXBUF_BA) 2148b7d5e03cSMatthew Dillon 2149b7d5e03cSMatthew Dillon 2150b7d5e03cSMatthew Dillon /* MAC Key Cache */ 2151b7d5e03cSMatthew Dillon #define AR_KEYTABLE_0 AR_MAC_PCU_OFFSET(MAC_PCU_KEY_CACHE) 2152b7d5e03cSMatthew Dillon #define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32)) 2153b7d5e03cSMatthew Dillon #define AR_KEY_CACHE_SIZE 128 2154b7d5e03cSMatthew Dillon #define AR_RSVD_KEYTABLE_ENTRIES 4 2155b7d5e03cSMatthew Dillon #define AR_KEY_TYPE 0x00000007 // MAC Key Type Mask 2156b7d5e03cSMatthew Dillon #define AR_KEYTABLE_TYPE_40 0x00000000 /* WEP 40 bit key */ 2157b7d5e03cSMatthew Dillon #define AR_KEYTABLE_TYPE_104 0x00000001 /* WEP 104 bit key */ 2158b7d5e03cSMatthew Dillon #define AR_KEYTABLE_TYPE_128 0x00000003 /* WEP 128 bit key */ 2159b7d5e03cSMatthew Dillon #define AR_KEYTABLE_TYPE_TKIP 0x00000004 /* TKIP and Michael */ 2160b7d5e03cSMatthew Dillon #define AR_KEYTABLE_TYPE_AES 0x00000005 /* AES/OCB 128 bit key */ 2161b7d5e03cSMatthew Dillon #define AR_KEYTABLE_TYPE_CCM 0x00000006 /* AES/CCM 128 bit key */ 2162b7d5e03cSMatthew Dillon #define AR_KEYTABLE_TYPE_CLR 0x00000007 /* no encryption */ 2163b7d5e03cSMatthew Dillon #define AR_KEYTABLE_ANT 0x00000008 /* previous transmit antenna */ 2164b7d5e03cSMatthew Dillon #define AR_KEYTABLE_UAPSD 0x000001E0 /* UAPSD AC mask */ 2165b7d5e03cSMatthew Dillon #define AR_KEYTABLE_UAPSD_S 5 2166b7d5e03cSMatthew Dillon #define AR_KEYTABLE_PWRMGT 0x00000200 /* hw managed PowerMgt bit */ 2167b7d5e03cSMatthew Dillon 2168b7d5e03cSMatthew Dillon #define AR_KEYTABLE_MMSS 0x00001c00 /* remote's MMSS*/ 2169b7d5e03cSMatthew Dillon #define AR_KEYTABLE_MMSS_S 10 2170b7d5e03cSMatthew Dillon #define AR_KEYTABLE_CEC 0x00006000 /* remote's CEC*/ 2171b7d5e03cSMatthew Dillon #define AR_KEYTABLE_CEC_S 13 2172b7d5e03cSMatthew Dillon #define AR_KEYTABLE_STAGGED 0x00010000 /* remote's stagged sounding*/ 2173b7d5e03cSMatthew Dillon #define AR_KEYTABLE_STAGGED_S 16 2174b7d5e03cSMatthew Dillon 2175b7d5e03cSMatthew Dillon #define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */ 2176b7d5e03cSMatthew Dillon #define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) /* key bit 0-31 */ 2177b7d5e03cSMatthew Dillon #define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) /* key bit 32-47 */ 2178b7d5e03cSMatthew Dillon #define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) /* key bit 48-79 */ 2179b7d5e03cSMatthew Dillon #define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) /* key bit 80-95 */ 2180b7d5e03cSMatthew Dillon #define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) /* key bit 96-127 */ 2181b7d5e03cSMatthew Dillon #define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20) /* key type */ 2182b7d5e03cSMatthew Dillon #define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) /* MAC address 1-32 */ 2183b7d5e03cSMatthew Dillon #define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) /* MAC address 33-47 */ 2184b7d5e03cSMatthew Dillon #define AR_KEYTABLE_DIR_ACK_BIT 0x00000010 /* Directed ACK bit */ 2185b7d5e03cSMatthew Dillon 2186b7d5e03cSMatthew Dillon 2187b7d5e03cSMatthew Dillon 2188b7d5e03cSMatthew Dillon /* 2189b7d5e03cSMatthew Dillon * MAC WoW Registers. 2190b7d5e03cSMatthew Dillon */ 2191b7d5e03cSMatthew Dillon #define AR_WOW_PATTERN_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW1) 2192b7d5e03cSMatthew Dillon #define AR_WOW_PAT_BACKOFF 0x00000004 2193b7d5e03cSMatthew Dillon #define AR_WOW_BACK_OFF_SHIFT(x) ((x & 0xf) << 27) /* in usecs */ 2194b7d5e03cSMatthew Dillon #define AR_WOW_MAC_INTR_EN 0x00040000 2195b7d5e03cSMatthew Dillon #define AR_WOW_MAGIC_EN 0x00010000 2196b7d5e03cSMatthew Dillon #define AR_WOW_PATTERN_EN(x) ((x & 0xff) << 0) 2197b7d5e03cSMatthew Dillon #define AR_WOW_PATTERN_FOUND_SHIFT 8 2198b7d5e03cSMatthew Dillon #define AR_WOW_PATTERN_FOUND(x) (x & (0xff << AR_WOW_PATTERN_FOUND_SHIFT)) 2199b7d5e03cSMatthew Dillon #define AR_WOW_PATTERN_FOUND_MASK ((0xff) << AR_WOW_PATTERN_FOUND_SHIFT) 2200b7d5e03cSMatthew Dillon #define AR_WOW_MAGIC_PAT_FOUND 0x00020000 2201b7d5e03cSMatthew Dillon #define AR_WOW_MAC_INTR 0x00080000 2202b7d5e03cSMatthew Dillon #define AR_WOW_KEEP_ALIVE_FAIL 0x00100000 2203b7d5e03cSMatthew Dillon #define AR_WOW_BEACON_FAIL 0x00200000 2204b7d5e03cSMatthew Dillon 2205b7d5e03cSMatthew Dillon 2206b7d5e03cSMatthew Dillon #define AR_WOW_COUNT_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW2) 2207b7d5e03cSMatthew Dillon #define AR_WOW_AIFS_CNT(x) ((x & 0xff) << 0) 2208b7d5e03cSMatthew Dillon #define AR_WOW_SLOT_CNT(x) ((x & 0xff) << 8) 2209b7d5e03cSMatthew Dillon #define AR_WOW_KEEP_ALIVE_CNT(x) ((x & 0xff) << 16) 2210b7d5e03cSMatthew Dillon /* 2211b7d5e03cSMatthew Dillon * Default values for Wow Configuration for backoff, aifs, slot, keep-alive, etc. 2212b7d5e03cSMatthew Dillon * to be programmed into various registers. 2213b7d5e03cSMatthew Dillon */ 2214b7d5e03cSMatthew Dillon #define AR_WOW_CNT_AIFS_CNT 0x00000022 // AR_WOW_COUNT_REG 2215b7d5e03cSMatthew Dillon #define AR_WOW_CNT_SLOT_CNT 0x00000009 // AR_WOW_COUNT_REG 2216b7d5e03cSMatthew Dillon /* 2217b7d5e03cSMatthew Dillon * Keepalive count applicable for Merlin 2.0 and above. 2218b7d5e03cSMatthew Dillon */ 2219b7d5e03cSMatthew Dillon #define AR_WOW_CNT_KA_CNT 0x00000008 // AR_WOW_COUNT_REG 2220b7d5e03cSMatthew Dillon 2221b7d5e03cSMatthew Dillon 2222b7d5e03cSMatthew Dillon #define AR_WOW_BCN_EN_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW3_BEACON_FAIL) 2223b7d5e03cSMatthew Dillon #define AR_WOW_BEACON_FAIL_EN 0x00000001 2224b7d5e03cSMatthew Dillon 2225b7d5e03cSMatthew Dillon #define AR_WOW_BCN_TIMO_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW3_BEACON) 2226b7d5e03cSMatthew Dillon #define AR_WOW_BEACON_TIMO 0x40000000 /* Valid if BCN_EN is set */ 2227b7d5e03cSMatthew Dillon #define AR_WOW_BEACON_TIMO_MAX 0xFFFFFFFF /* Max. value for Beacon Timeout */ 2228b7d5e03cSMatthew Dillon 2229b7d5e03cSMatthew Dillon #define AR_WOW_KEEP_ALIVE_TIMO_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW3_KEEP_ALIVE) 2230b7d5e03cSMatthew Dillon #define AR_WOW_KEEP_ALIVE_TIMO 0x00007A12 2231b7d5e03cSMatthew Dillon #define AR_WOW_KEEP_ALIVE_NEVER 0xFFFFFFFF 2232b7d5e03cSMatthew Dillon 2233b7d5e03cSMatthew Dillon #define AR_WOW_KEEP_ALIVE_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_KA) 2234b7d5e03cSMatthew Dillon #define AR_WOW_KEEP_ALIVE_AUTO_DIS 0x00000001 2235b7d5e03cSMatthew Dillon #define AR_WOW_KEEP_ALIVE_FAIL_DIS 0x00000002 2236b7d5e03cSMatthew Dillon 2237b7d5e03cSMatthew Dillon #define AR_WOW_US_SCALAR_REG AR_MAC_PCU_OFFSET(PCU_1US) 2238b7d5e03cSMatthew Dillon 2239b7d5e03cSMatthew Dillon #define AR_WOW_KEEP_ALIVE_DELAY_REG AR_MAC_PCU_OFFSET(PCU_KA) 2240b7d5e03cSMatthew Dillon #define AR_WOW_KEEP_ALIVE_DELAY 0x000003E8 // 1 msec 2241b7d5e03cSMatthew Dillon 2242b7d5e03cSMatthew Dillon #define AR_WOW_PATTERN_MATCH_REG AR_MAC_PCU_OFFSET(WOW_EXACT) 2243b7d5e03cSMatthew Dillon #define AR_WOW_PAT_END_OF_PKT(x) ((x & 0xf) << 0) 2244b7d5e03cSMatthew Dillon #define AR_WOW_PAT_OFF_MATCH(x) ((x & 0xf) << 8) 2245b7d5e03cSMatthew Dillon 2246b7d5e03cSMatthew Dillon #define AR_WOW_PATTERN_MATCH_REG_2 AR_MAC_PCU_OFFSET(WOW2_EXACT) 2247b7d5e03cSMatthew Dillon #define AR_WOW_PATTERN_OFF1_REG AR_MAC_PCU_OFFSET(PCU_WOW4) /* Pattern bytes 0 -> 3 */ 2248b7d5e03cSMatthew Dillon #define AR_WOW_PATTERN_OFF2_REG AR_MAC_PCU_OFFSET(PCU_WOW5) /* Pattern bytes 4 -> 7 */ 2249b7d5e03cSMatthew Dillon #define AR_WOW_PATTERN_OFF3_REG AR_MAC_PCU_OFFSET(PCU_WOW6) /* Pattern bytes 8 -> 11 */ 2250b7d5e03cSMatthew Dillon #define AR_WOW_PATTERN_OFF4_REG AR_MAC_PCU_OFFSET(PCU_WOW7) /* Pattern bytes 12 -> 15 */ 2251b7d5e03cSMatthew Dillon 2252b7d5e03cSMatthew Dillon /* start address of the frame in RxBUF */ 2253b7d5e03cSMatthew Dillon #define AR_WOW_RXBUF_START_ADDR AR_MAC_PCU_OFFSET(MAC_PCU_WOW6) 2254b7d5e03cSMatthew Dillon 2255b7d5e03cSMatthew Dillon /* Pattern detect and enable bits */ 2256b7d5e03cSMatthew Dillon #define AR_WOW_PATTERN_DETECT_ENABLE AR_MAC_PCU_OFFSET(MAC_PCU_WOW4) 2257b7d5e03cSMatthew Dillon 2258b7d5e03cSMatthew Dillon /* Rx Abort Enable */ 2259b7d5e03cSMatthew Dillon #define AR_WOW_RX_ABORT_ENABLE AR_MAC_PCU_OFFSET(MAC_PCU_WOW5) 2260b7d5e03cSMatthew Dillon 2261b7d5e03cSMatthew Dillon /* PHY error counter 1, 2, and 3 mask continued */ 2262b7d5e03cSMatthew Dillon #define AR_PHY_ERR_CNT_MASK_CONT AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_MASK_CONT) 2263b7d5e03cSMatthew Dillon 2264b7d5e03cSMatthew Dillon /* AZIMUTH mode reg can be used for proxySTA */ 2265b7d5e03cSMatthew Dillon #define AR_AZIMUTH_MODE AR_MAC_PCU_OFFSET(MAC_PCU_AZIMUTH_MODE) 2266b7d5e03cSMatthew Dillon #define AR_AZIMUTH_KEY_SEARCH_AD1 0x00000002 2267b7d5e03cSMatthew Dillon #define AR_AZIMUTH_CTS_MATCH_TX_AD2 0x00000040 2268b7d5e03cSMatthew Dillon #define AR_AZIMUTH_BA_USES_AD1 0x00000080 2269b7d5e03cSMatthew Dillon #define AR_AZIMUTH_FILTER_PASS_HOLD 0x00000200 2270b7d5e03cSMatthew Dillon 2271b7d5e03cSMatthew Dillon /* Length of Pattern Match for Pattern */ 2272b7d5e03cSMatthew Dillon #define AR_WOW_LENGTH1_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH1) 2273b7d5e03cSMatthew Dillon #define AR_WOW_LENGTH2_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH2) 2274b7d5e03cSMatthew Dillon #define AR_WOW_LENGTH3_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH3) 2275b7d5e03cSMatthew Dillon #define AR_WOW_LENGTH4_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH4) 2276b7d5e03cSMatthew Dillon 2277b7d5e03cSMatthew Dillon #define AR_LOC_CTL_REG AR_MAC_PCU_OFFSET(MAC_PCU_LOCATION_MODE_CONTROL) 2278b7d5e03cSMatthew Dillon #define AR_LOC_TIMER_REG AR_MAC_PCU_OFFSET(MAC_PCU_LOCATION_MODE_TIMER) 2279b7d5e03cSMatthew Dillon #define AR_LOC_CTL_REG_FS 0x1 2280b7d5e03cSMatthew Dillon 2281b7d5e03cSMatthew Dillon /* Register to enable pattern match for less than 256 bytes packets */ 2282b7d5e03cSMatthew Dillon #define AR_WOW_PATTERN_MATCH_LT_256B_REG AR_MAC_PCU_OFFSET(WOW_PATTERN_MATCH_LESS_THAN_256_BYTES) 2283b7d5e03cSMatthew Dillon 2284b7d5e03cSMatthew Dillon 2285b7d5e03cSMatthew Dillon #define AR_WOW_STATUS(x) (x & (AR_WOW_PATTERN_FOUND_MASK | AR_WOW_MAGIC_PAT_FOUND | \ 2286b7d5e03cSMatthew Dillon AR_WOW_KEEP_ALIVE_FAIL | AR_WOW_BEACON_FAIL)) 2287b7d5e03cSMatthew Dillon #define AR_WOW_CLEAR_EVENTS(x) (x & ~(AR_WOW_PATTERN_EN(0xff) | \ 2288b7d5e03cSMatthew Dillon AR_WOW_MAGIC_EN | AR_WOW_MAC_INTR_EN | AR_WOW_BEACON_FAIL | \ 2289b7d5e03cSMatthew Dillon AR_WOW_KEEP_ALIVE_FAIL)) 2290b7d5e03cSMatthew Dillon 2291b7d5e03cSMatthew Dillon 2292b7d5e03cSMatthew Dillon /* 2293b7d5e03cSMatthew Dillon * Keep it long for Beacon workaround - ensures no AH_FALSE alarm 2294b7d5e03cSMatthew Dillon */ 2295b7d5e03cSMatthew Dillon #define AR_WOW_BMISSTHRESHOLD 0x20 2296b7d5e03cSMatthew Dillon 2297b7d5e03cSMatthew Dillon 2298b7d5e03cSMatthew Dillon /* WoW - Transmit buffer for keep alive frames */ 2299b7d5e03cSMatthew Dillon #define AR_WOW_TRANSMIT_BUFFER AR_MAC_PCU_OFFSET(MAC_PCU_BUF) 2300b7d5e03cSMatthew Dillon #define AR_WOW_TXBUF(_i) (AR_WOW_TRANSMIT_BUFFER + ((_i)<<2)) 2301b7d5e03cSMatthew Dillon 2302b7d5e03cSMatthew Dillon #define AR_WOW_KA_DESC_WORD2 AR_WOW_TXBUF(0) 2303b7d5e03cSMatthew Dillon #define AR_WOW_KA_DESC_WORD3 AR_WOW_TXBUF(1) 2304b7d5e03cSMatthew Dillon #define AR_WOW_KA_DESC_WORD4 AR_WOW_TXBUF(2) 2305b7d5e03cSMatthew Dillon #define AR_WOW_KA_DESC_WORD5 AR_WOW_TXBUF(3) 2306b7d5e03cSMatthew Dillon #define AR_WOW_KA_DESC_WORD6 AR_WOW_TXBUF(4) 2307b7d5e03cSMatthew Dillon #define AR_WOW_KA_DESC_WORD7 AR_WOW_TXBUF(5) 2308b7d5e03cSMatthew Dillon #define AR_WOW_KA_DESC_WORD8 AR_WOW_TXBUF(6) 2309b7d5e03cSMatthew Dillon #define AR_WOW_KA_DESC_WORD9 AR_WOW_TXBUF(7) 2310b7d5e03cSMatthew Dillon #define AR_WOW_KA_DESC_WORD10 AR_WOW_TXBUF(8) 2311b7d5e03cSMatthew Dillon #define AR_WOW_KA_DESC_WORD11 AR_WOW_TXBUF(9) 2312b7d5e03cSMatthew Dillon #define AR_WOW_KA_DESC_WORD12 AR_WOW_TXBUF(10) 2313b7d5e03cSMatthew Dillon #define AR_WOW_KA_DESC_WORD13 AR_WOW_TXBUF(11) 2314b7d5e03cSMatthew Dillon 2315b7d5e03cSMatthew Dillon /* KA_DATA_WORD = 6 words. Depending on the number of 2316b7d5e03cSMatthew Dillon * descriptor words, it can start at AR_WOW_TXBUF(12) 2317b7d5e03cSMatthew Dillon * or AR_WOW_TXBUF(13) */ 2318b7d5e03cSMatthew Dillon 2319b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_GTK_DATA_START AR_WOW_TXBUF(19) 2320b7d5e03cSMatthew Dillon 2321b7d5e03cSMatthew Dillon #define AR_WOW_KA_DATA_WORD_END_JUPITER AR_WOW_TXBUF(60) 2322b7d5e03cSMatthew Dillon 2323b7d5e03cSMatthew Dillon #define AR_WOW_SW_NULL_PARAMETER AR_WOW_TXBUF(61) 2324b7d5e03cSMatthew Dillon #define AR_WOW_SW_NULL_LONG_PERIOD_MASK 0x0000FFFF 2325b7d5e03cSMatthew Dillon #define AR_WOW_SW_NULL_LONG_PERIOD_MASK_S 0 2326b7d5e03cSMatthew Dillon #define AR_WOW_SW_NULL_SHORT_PERIOD_MASK 0xFFFF0000 2327b7d5e03cSMatthew Dillon #define AR_WOW_SW_NULL_SHORT_PERIOD_MASK_S 16 2328b7d5e03cSMatthew Dillon 2329b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_COMMAND_JUPITER AR_WOW_TXBUF(62) 2330b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ENA_GTK 0x80000000 2331b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ENA_ACER_MAGIC 0x40000000 2332b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ENA_STD_MAGIC 0x20000000 2333b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ENA_SWKA 0x10000000 2334b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ENA_ARP_OFFLOAD 0x08000000 2335b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ENA_NS_OFFLOAD 0x04000000 2336b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ENA_4WAY_WAKE 0x02000000 2337b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ENA_GTK_ERROR_WAKE 0x01000000 2338b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ENA_AP_LOSS_WAKE 0x00800000 2339b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ENA_BT_SLEEP 0x00080000 2340b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ENA_SW_NULL 0x00040000 2341b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ENA_HWKA_FAIL 0x00020000 2342b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ENA_DEVID_SWAR 0x00010000 2343b7d5e03cSMatthew Dillon 2344b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_STATUS_JUPITER AR_WOW_TXBUF(63) 2345b7d5e03cSMatthew Dillon 2346b7d5e03cSMatthew Dillon /* WoW Transmit Buffer for patterns */ 2347b7d5e03cSMatthew Dillon #define AR_WOW_TB_PATTERN0 AR_WOW_TXBUF(64) 2348b7d5e03cSMatthew Dillon #define AR_WOW_TB_PATTERN1 AR_WOW_TXBUF(128) 2349b7d5e03cSMatthew Dillon #define AR_WOW_TB_PATTERN2 AR_WOW_TXBUF(192) 2350b7d5e03cSMatthew Dillon #define AR_WOW_TB_PATTERN3 AR_WOW_TXBUF(256) 2351b7d5e03cSMatthew Dillon #define AR_WOW_TB_PATTERN4 AR_WOW_TXBUF(320) 2352b7d5e03cSMatthew Dillon #define AR_WOW_TB_PATTERN5 AR_WOW_TXBUF(384) 2353b7d5e03cSMatthew Dillon #define AR_WOW_TB_PATTERN6 AR_WOW_TXBUF(448) 2354b7d5e03cSMatthew Dillon #define AR_WOW_TB_PATTERN7 AR_WOW_TXBUF(512) 2355b7d5e03cSMatthew Dillon #define AR_WOW_TB_MASK0 AR_WOW_TXBUF(768) 2356b7d5e03cSMatthew Dillon #define AR_WOW_TB_MASK1 AR_WOW_TXBUF(776) 2357b7d5e03cSMatthew Dillon #define AR_WOW_TB_MASK2 AR_WOW_TXBUF(784) 2358b7d5e03cSMatthew Dillon #define AR_WOW_TB_MASK3 AR_WOW_TXBUF(792) 2359b7d5e03cSMatthew Dillon #define AR_WOW_TB_MASK4 AR_WOW_TXBUF(800) 2360b7d5e03cSMatthew Dillon #define AR_WOW_TB_MASK5 AR_WOW_TXBUF(808) 2361b7d5e03cSMatthew Dillon #define AR_WOW_TB_MASK6 AR_WOW_TXBUF(816) 2362b7d5e03cSMatthew Dillon #define AR_WOW_TB_MASK7 AR_WOW_TXBUF(824) 2363b7d5e03cSMatthew Dillon 2364b7d5e03cSMatthew Dillon 2365b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_START AR_WOW_TXBUF(825) 2366b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_START_JUPITER AR_WOW_TXBUF(832) 2367b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_WORDS 4 2368b7d5e03cSMatthew Dillon 2369b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_GTK_DATA_START_JUPITER AR_WOW_TXBUF(836) 2370b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_GTK_DATA_WORDS_JUPITER 20 2371b7d5e03cSMatthew Dillon 2372b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ACER_MAGIC_START AR_WOW_TXBUF(856) 2373b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ACER_MAGIC_WORDS 2 2374b7d5e03cSMatthew Dillon 2375b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ACER_KA0_START AR_WOW_TXBUF(858) 2376b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ACER_KA0_PERIOD_MS AR_WOW_TXBUF(858) 2377b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ACER_KA0_SIZE AR_WOW_TXBUF(859) 2378b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ACER_KA0_DATA AR_WOW_TXBUF(860) 2379b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ACER_KA0_DATA_WORDS 20 2380b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ACER_KA0_WORDS 22 2381b7d5e03cSMatthew Dillon 2382b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ACER_KA1_START AR_WOW_TXBUF(880) 2383b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ACER_KA1_PERIOD_MS AR_WOW_TXBUF(880) 2384b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ACER_KA1_SIZE AR_WOW_TXBUF(881) 2385b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ACER_KA1_DATA AR_WOW_TXBUF(882) 2386b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ACER_KA1_DATA_WORDS 20 2387b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ACER_KA1_WORDS 22 2388b7d5e03cSMatthew Dillon 2389b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ARP0_START AR_WOW_TXBUF(902) 2390b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ARP0_VALID AR_WOW_TXBUF(902) 2391b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ARP0_RMT_IP AR_WOW_TXBUF(903) 2392b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ARP0_HOST_IP AR_WOW_TXBUF(904) 2393b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ARP0_MAC_L AR_WOW_TXBUF(905) 2394b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ARP0_MAC_H AR_WOW_TXBUF(906) 2395b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ARP0_WORDS 5 2396b7d5e03cSMatthew Dillon 2397b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ARP1_START AR_WOW_TXBUF(907) 2398b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ARP1_VALID AR_WOW_TXBUF(907) 2399b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ARP1_RMT_IP AR_WOW_TXBUF(908) 2400b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ARP1_HOST_IP AR_WOW_TXBUF(909) 2401b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ARP1_MAC_L AR_WOW_TXBUF(910) 2402b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ARP1_MAC_H AR_WOW_TXBUF(911) 2403b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_ARP1_WORDS 5 2404b7d5e03cSMatthew Dillon 2405b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS0_START AR_WOW_TXBUF(912) 2406b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS0_VALID AR_WOW_TXBUF(912) 2407b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS0_RMT_IPV6 AR_WOW_TXBUF(913) 2408b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS0_SOLICIT_IPV6 AR_WOW_TXBUF(917) 2409b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS0_MAC_L AR_WOW_TXBUF(921) 2410b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS0_MAC_H AR_WOW_TXBUF(922) 2411b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS0_TGT0_IPV6 AR_WOW_TXBUF(923) 2412b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS0_TGT1_IPV6 AR_WOW_TXBUF(927) 2413b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS0_WORDS 19 2414b7d5e03cSMatthew Dillon 2415b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS1_START AR_WOW_TXBUF(931) 2416b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS1_VALID AR_WOW_TXBUF(931) 2417b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS1_RMT_IPV6 AR_WOW_TXBUF(932) 2418b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS1_SOLICIT_IPV6 AR_WOW_TXBUF(936) 2419b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS1_MAC_L AR_WOW_TXBUF(940) 2420b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS1_MAC_H AR_WOW_TXBUF(941) 2421b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS1_TGT0_IPV6 AR_WOW_TXBUF(942) 2422b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS1_TGT1_IPV6 AR_WOW_TXBUF(946) 2423b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_NS1_WORDS 19 2424b7d5e03cSMatthew Dillon 2425b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_WLAN_REGSET_START AR_WOW_TXBUF(950) 2426b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_WLAN_REGSET_NUM AR_WOW_TXBUF(950) 2427b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_WLAN_REGSET_REGVAL AR_WOW_TXBUF(951) 2428b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_WLAN_REGSET_MAX_PAIR 32 2429b7d5e03cSMatthew Dillon #define AR_WOW_OFFLOAD_WLAN_REGSET_WORDS 65 //(1 + AR_WOW_OFFLOAD_WLAN_REGSET_MAX_PAIR * 2) 2430b7d5e03cSMatthew Dillon 2431b7d5e03cSMatthew Dillon /* Currently Pattern 0-7 are supported - so bit 0-7 are set */ 2432b7d5e03cSMatthew Dillon #define AR_WOW_PATTERN_SUPPORTED 0xFF 2433b7d5e03cSMatthew Dillon #define AR_WOW_LENGTH_MAX 0xFF 2434b7d5e03cSMatthew Dillon #define AR_WOW_LENGTH1_SHIFT(_i) ((0x3 - ((_i) & 0x3)) << 0x3) 2435b7d5e03cSMatthew Dillon #define AR_WOW_LENGTH1_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LENGTH1_SHIFT(_i)) 2436b7d5e03cSMatthew Dillon #define AR_WOW_LENGTH2_SHIFT(_i) ((0x7 - ((_i) & 0x7)) << 0x3) 2437b7d5e03cSMatthew Dillon #define AR_WOW_LENGTH2_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LENGTH2_SHIFT(_i)) 2438b7d5e03cSMatthew Dillon 2439b7d5e03cSMatthew Dillon /* 2440b7d5e03cSMatthew Dillon * MAC Direct Connect registers 2441b7d5e03cSMatthew Dillon * 2442b7d5e03cSMatthew Dillon * Added to support dual BSSID/TSF which are needed in the application 2443b7d5e03cSMatthew Dillon * of Mesh networking or Direct Connect. 2444b7d5e03cSMatthew Dillon */ 2445b7d5e03cSMatthew Dillon 2446b7d5e03cSMatthew Dillon /* 2447b7d5e03cSMatthew Dillon * Note that the only function added with this BSSID2 is to receive 2448b7d5e03cSMatthew Dillon * multi/broadcast from BSSID2 as well 2449b7d5e03cSMatthew Dillon */ 2450b7d5e03cSMatthew Dillon /* MAC BSSID low 32 bits */ 2451b7d5e03cSMatthew Dillon #define AR_BSS2_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_L32) 2452b7d5e03cSMatthew Dillon /* MAC BSSID upper 16 bits / AID */ 2453b7d5e03cSMatthew Dillon #define AR_BSS2_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_U16) 2454b7d5e03cSMatthew Dillon 2455b7d5e03cSMatthew Dillon /* 2456b7d5e03cSMatthew Dillon * Secondary TSF support added for dual BSSID/TSF 2457b7d5e03cSMatthew Dillon */ 2458b7d5e03cSMatthew Dillon /* MAC local clock lower 32 bits */ 2459b7d5e03cSMatthew Dillon #define AR_TSF2_L32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_L32) 2460b7d5e03cSMatthew Dillon /* MAC local clock upper 32 bits */ 2461b7d5e03cSMatthew Dillon #define AR_TSF2_U32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_U32) 2462b7d5e03cSMatthew Dillon 2463b7d5e03cSMatthew Dillon /* MAC Direct Connect Control */ 2464b7d5e03cSMatthew Dillon #define AR_DIRECT_CONNECT AR_MAC_PCU_OFFSET(MAC_PCU_DIRECT_CONNECT) 2465b7d5e03cSMatthew Dillon #define AR_DC_AP_STA_EN 0x00000001 2466b7d5e03cSMatthew Dillon #define AR_DC_AP_STA_EN_S 0 2467b7d5e03cSMatthew Dillon 2468b7d5e03cSMatthew Dillon /* 2469b7d5e03cSMatthew Dillon * tx_bf Register 2470b7d5e03cSMatthew Dillon */ 2471b7d5e03cSMatthew Dillon #define AR_SVD_OFFSET(_x) offsetof(struct svd_reg, _x) 2472b7d5e03cSMatthew Dillon 2473b7d5e03cSMatthew Dillon #define AR_TXBF_DBG AR_SVD_OFFSET(TXBF_DBG) 2474b7d5e03cSMatthew Dillon 2475b7d5e03cSMatthew Dillon #define AR_TXBF AR_SVD_OFFSET(TXBF) 2476b7d5e03cSMatthew Dillon #define AR_TXBF_CB_TX 0x00000003 2477b7d5e03cSMatthew Dillon #define AR_TXBF_CB_TX_S 0 2478b7d5e03cSMatthew Dillon #define AR_TXBF_PSI_1_PHI_3 0 2479b7d5e03cSMatthew Dillon #define AR_TXBF_PSI_2_PHI_4 1 2480b7d5e03cSMatthew Dillon #define AR_TXBF_PSI_3_PHI_5 2 2481b7d5e03cSMatthew Dillon #define AR_TXBF_PSI_4_PHI_6 3 2482b7d5e03cSMatthew Dillon 2483b7d5e03cSMatthew Dillon #define AR_TXBF_NB_TX 0x0000000C 2484b7d5e03cSMatthew Dillon #define AR_TXBF_NB_TX_S 2 2485b7d5e03cSMatthew Dillon #define AR_TXBF_NUMBEROFBIT_4 0 2486b7d5e03cSMatthew Dillon #define AR_TXBF_NUMBEROFBIT_2 1 2487b7d5e03cSMatthew Dillon #define AR_TXBF_NUMBEROFBIT_6 2 2488b7d5e03cSMatthew Dillon #define AR_TXBF_NUMBEROFBIT_8 3 2489b7d5e03cSMatthew Dillon 2490b7d5e03cSMatthew Dillon #define AR_TXBF_NG_RPT_TX 0x00000030 2491b7d5e03cSMatthew Dillon #define AR_TXBF_NG_RPT_TX_S 4 2492b7d5e03cSMatthew Dillon #define AR_TXBF_No_GROUP 0 2493b7d5e03cSMatthew Dillon #define AR_TXBF_TWO_GROUP 1 2494b7d5e03cSMatthew Dillon #define AR_TXBF_FOUR_GROUP 2 2495b7d5e03cSMatthew Dillon 2496b7d5e03cSMatthew Dillon #define AR_TXBF_NG_CVCACHE 0x000000C0 2497b7d5e03cSMatthew Dillon #define AR_TXBF_NG_CVCACHE_S 6 2498b7d5e03cSMatthew Dillon #define AR_TXBF_FOUR_CLIENTS 0 2499b7d5e03cSMatthew Dillon #define AR_TXBF_EIGHT_CLIENTS 1 2500b7d5e03cSMatthew Dillon #define AR_TXBF_SIXTEEN_CLIENTS 2 2501b7d5e03cSMatthew Dillon 2502b7d5e03cSMatthew Dillon #define AR_TXBF_TXCV_BFWEIGHT_METHOD 0x00000600 2503b7d5e03cSMatthew Dillon #define AR_TXBF_TXCV_BFWEIGHT_METHOD_S 9 2504b7d5e03cSMatthew Dillon #define AR_TXBF_NO_WEIGHTING 0 2505b7d5e03cSMatthew Dillon #define AR_TXBF_MAX_POWER 1 2506b7d5e03cSMatthew Dillon #define AR_TXBF_KEEP_RATIO 2 2507b7d5e03cSMatthew Dillon 2508b7d5e03cSMatthew Dillon #define AR_TXBF_RLR_EN 0x00000800 2509b7d5e03cSMatthew Dillon #define AR_TXBF_RC_20_U_DONE 0x00001000 2510b7d5e03cSMatthew Dillon #define AR_TXBF_RC_20_L_DONE 0x00002000 2511b7d5e03cSMatthew Dillon #define AR_TXBF_RC_40_DONE 0x00004000 2512b7d5e03cSMatthew Dillon #define AR_TXBF_FORCE_UPDATE_V2BB 0x00008000 2513b7d5e03cSMatthew Dillon 2514b7d5e03cSMatthew Dillon #define AR_TXBF_TIMER AR_SVD_OFFSET(TXBF_TIMER) 2515b7d5e03cSMatthew Dillon #define AR_TXBF_TIMER_TIMEOUT 0x000000FF 2516b7d5e03cSMatthew Dillon #define AR_TXBF_TIMER_TIMEOUT_S 0 2517b7d5e03cSMatthew Dillon #define AR_TXBF_TIMER_ATIMEOU 0x0000FF00 2518b7d5e03cSMatthew Dillon #define AR_TXBF_TIMER_ATIMEOUT_S 8 2519b7d5e03cSMatthew Dillon 2520b7d5e03cSMatthew Dillon /* for SVD cache update */ 2521b7d5e03cSMatthew Dillon #define AR_TXBF_SW AR_SVD_OFFSET(TXBF_SW) 2522b7d5e03cSMatthew Dillon #define AR_LRU_ACK 0x00000001 2523b7d5e03cSMatthew Dillon #define AR_LRU_ADDR 0x000003FE 2524b7d5e03cSMatthew Dillon #define AR_LRU_ADDR_S 1 2525b7d5e03cSMatthew Dillon #define AR_LRU_EN 0x00000800 2526b7d5e03cSMatthew Dillon #define AR_LRU_EN_S 11 2527b7d5e03cSMatthew Dillon #define AR_DEST_IDX 0x0007f000 2528b7d5e03cSMatthew Dillon #define AR_DEST_IDX_S 12 2529b7d5e03cSMatthew Dillon #define AR_LRU_WR_ACK 0x00080000 2530b7d5e03cSMatthew Dillon #define AR_LRU_WR_ACK_S 19 2531b7d5e03cSMatthew Dillon #define AR_LRU_RD_ACK 0x00100000 2532b7d5e03cSMatthew Dillon #define AR_LRU_RD_ACK_S 20 2533b7d5e03cSMatthew Dillon 2534b7d5e03cSMatthew Dillon #define AR_RC0_0 AR_SVD_OFFSET(RC0) 2535b7d5e03cSMatthew Dillon #define AR_RC0(_idx) (AR_RC0_0+(_idx)) 2536b7d5e03cSMatthew Dillon #define AR_RC1_0 AR_SVD_OFFSET(RC1) 2537b7d5e03cSMatthew Dillon #define AR_RC1(_idx) (AR_RC1_0+(_idx)) 2538b7d5e03cSMatthew Dillon 2539b7d5e03cSMatthew Dillon #define AR_CVCACHE_0 AR_SVD_OFFSET(CVCACHE) 2540b7d5e03cSMatthew Dillon #define AR_CVCACHE(_idx) (AR_CVCACHE_0+(_idx)) 2541b7d5e03cSMatthew Dillon /* for CV CACHE Header */ 2542b7d5e03cSMatthew Dillon #define AR_CVCACHE_Ng_IDX 0x0000C000 2543b7d5e03cSMatthew Dillon #define AR_CVCACHE_Ng_IDX_S 14 2544b7d5e03cSMatthew Dillon #define AR_CVCACHE_BW40 0x00010000 2545b7d5e03cSMatthew Dillon #define AR_CVCACHE_BW40_S 16 2546b7d5e03cSMatthew Dillon #define AR_CVCACHE_IMPLICIT 0x00020000 2547b7d5e03cSMatthew Dillon #define AR_CVCACHE_IMPLICIT_S 17 2548b7d5e03cSMatthew Dillon #define AR_CVCACHE_DEST_IDX 0x01FC0000 2549b7d5e03cSMatthew Dillon #define AR_CVCACHE_DEST_IDX_S 18 2550b7d5e03cSMatthew Dillon #define AR_CVCACHE_Nc_IDX 0x06000000 2551b7d5e03cSMatthew Dillon #define AR_CVCACHE_Nc_IDX_S 25 2552b7d5e03cSMatthew Dillon #define AR_CVCACHE_Nr_IDX 0x18000000 2553b7d5e03cSMatthew Dillon #define AR_CVCACHE_Nr_IDX_S 27 2554b7d5e03cSMatthew Dillon #define AR_CVCACHE_EXPIRED 0x20000000 2555b7d5e03cSMatthew Dillon #define AR_CVCACHE_EXPIRED_S 29 2556b7d5e03cSMatthew Dillon #define AR_CVCACHE_WRITE 0x80000000 2557b7d5e03cSMatthew Dillon /* for CV cache data*/ 2558b7d5e03cSMatthew Dillon #define AR_CVCACHE_RD_EN 0x40000000 2559b7d5e03cSMatthew Dillon #define AR_CVCACHE_DATA 0x3fffffff 2560b7d5e03cSMatthew Dillon /* 2561b7d5e03cSMatthew Dillon * ANT DIV setting 2562b7d5e03cSMatthew Dillon */ 2563b7d5e03cSMatthew Dillon #define ANT_DIV_CONTROL_ALL (0x7e000000) 2564b7d5e03cSMatthew Dillon #define ANT_DIV_CONTROL_ALL_S (25) 2565b7d5e03cSMatthew Dillon #define ANT_DIV_ENABLE (0x1000000) 2566b7d5e03cSMatthew Dillon #define ANT_DIV_ENABLE_S (24) 2567b7d5e03cSMatthew Dillon #define FAST_DIV_ENABLE (0x2000) 2568b7d5e03cSMatthew Dillon #define FAST_DIV_ENABLE_S (13) 2569b7d5e03cSMatthew Dillon 2570b7d5e03cSMatthew Dillon /* Global register */ 2571b7d5e03cSMatthew Dillon #define AR_GLB_REG_OFFSET(_x) offsetof(struct wlan_bt_glb_reg_pcie, _x) 2572b7d5e03cSMatthew Dillon 2573b7d5e03cSMatthew Dillon #define AR_MBOX_CTRL_STATUS AR_GLB_REG_OFFSET(GLB_MBOX_CONTROL_STATUS) 2574b7d5e03cSMatthew Dillon #define AR_MBOX_INT_EMB_CPU 0x0001 2575b7d5e03cSMatthew Dillon #define AR_MBOX_INT_WLAN 0x0002 2576b7d5e03cSMatthew Dillon #define AR_MBOX_RESET 0x0004 2577b7d5e03cSMatthew Dillon #define AR_MBOX_RAM_REQ_MASK 0x0018 2578b7d5e03cSMatthew Dillon #define AR_MBOX_RAM_REQ_NO_RAM 0x0000 2579b7d5e03cSMatthew Dillon #define AR_MBOX_RAM_REQ_USB 0x0008 2580b7d5e03cSMatthew Dillon #define AR_MBOX_RAM_REQ_WLAN_BUF 0x0010 2581b7d5e03cSMatthew Dillon #define AR_MBOX_RAM_REQ_PATCH_REAPPY 0x0018 2582b7d5e03cSMatthew Dillon #define AR_MBOX_RAM_CONF 0x0020 2583b7d5e03cSMatthew Dillon #define AR_MBOX_WLAN_BUF 0x0040 2584b7d5e03cSMatthew Dillon #define AR_MBOX_WOW_REQ 0x0080 2585b7d5e03cSMatthew Dillon #define AR_MBOX_WOW_CONF 0x0100 2586b7d5e03cSMatthew Dillon #define AR_MBOX_WOW_ERROR_MASK 0x1e00 2587b7d5e03cSMatthew Dillon #define AR_MBOX_WOW_ERROR_NONE 0x0000 2588b7d5e03cSMatthew Dillon #define AR_MBOX_WOW_ERROR_INVALID_MSG 0x0200 2589b7d5e03cSMatthew Dillon #define AR_MBOX_WOW_ERROR_MALFORMED_MSG 0x0400 2590b7d5e03cSMatthew Dillon #define AR_MBOX_WOW_ERROR_INVALID_RAM_IMAGE 0x0600 2591b7d5e03cSMatthew Dillon 2592b7d5e03cSMatthew Dillon #define AR_WLAN_WOW_STATUS AR_GLB_REG_OFFSET(GLB_WLAN_WOW_STATUS) 2593b7d5e03cSMatthew Dillon 2594b7d5e03cSMatthew Dillon #define AR_WLAN_WOW_ENABLE AR_GLB_REG_OFFSET(GLB_WLAN_WOW_ENABLE) 2595b7d5e03cSMatthew Dillon 2596b7d5e03cSMatthew Dillon #define AR_EMB_CPU_WOW_STATUS AR_GLB_REG_OFFSET(GLB_EMB_CPU_WOW_STATUS) 2597b7d5e03cSMatthew Dillon #define AR_EMB_CPU_WOW_STATUS_KEEP_ALIVE_FAIL 0x1 2598b7d5e03cSMatthew Dillon #define AR_EMB_CPU_WOW_STATUS_BEACON_MISS 0x2 2599b7d5e03cSMatthew Dillon #define AR_EMB_CPU_WOW_STATUS_PATTERN_MATCH 0x4 2600b7d5e03cSMatthew Dillon #define AR_EMB_CPU_WOW_STATUS_MAGIC_PATTERN 0x8 2601b7d5e03cSMatthew Dillon 2602b7d5e03cSMatthew Dillon #define AR_EMB_CPU_WOW_ENABLE AR_GLB_REG_OFFSET(GLB_EMB_CPU_WOW_ENABLE) 2603b7d5e03cSMatthew Dillon #define AR_EMB_CPU_WOW_ENABLE_KEEP_ALIVE_FAIL 0x1 2604b7d5e03cSMatthew Dillon #define AR_EMB_CPU_WOW_ENABLE_BEACON_MISS 0x2 2605b7d5e03cSMatthew Dillon #define AR_EMB_CPU_WOW_ENABLE_PATTERN_MATCH 0x4 2606b7d5e03cSMatthew Dillon #define AR_EMB_CPU_WOW_ENABLE_MAGIC_PATTERN 0x8 2607b7d5e03cSMatthew Dillon 2608b7d5e03cSMatthew Dillon #define AR_SW_WOW_CONTROL AR_GLB_REG_OFFSET(GLB_SW_WOW_CONTROL) 2609b7d5e03cSMatthew Dillon #define AR_SW_WOW_ENABLE 0x1 2610b7d5e03cSMatthew Dillon #define AR_SWITCH_TO_REFCLK 0x2 2611b7d5e03cSMatthew Dillon #define AR_RESET_CONTROL 0x4 2612b7d5e03cSMatthew Dillon #define AR_RESET_VALUE_MASK 0x8 2613b7d5e03cSMatthew Dillon #define AR_HW_WOW_DISABLE 0x10 2614b7d5e03cSMatthew Dillon #define AR_CLR_MAC_INTERRUPT 0x20 2615b7d5e03cSMatthew Dillon #define AR_CLR_KA_INTERRUPT 0x40 2616b7d5e03cSMatthew Dillon 2617b7d5e03cSMatthew Dillon /* 2618b7d5e03cSMatthew Dillon * WLAN coex registers 2619b7d5e03cSMatthew Dillon */ 2620b7d5e03cSMatthew Dillon #define AR_WLAN_COEX_OFFSET(_x) offsetof(struct wlan_coex_reg, _x) 2621b7d5e03cSMatthew Dillon 2622b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND0 AR_WLAN_COEX_OFFSET(MCI_COMMAND0) 2623b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND0_HEADER 0xFF 2624b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND0_HEADER_S 0 2625b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND0_LEN 0x1f00 2626b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND0_LEN_S 8 2627b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000 2628b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S 13 2629b7d5e03cSMatthew Dillon 2630b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND1 AR_WLAN_COEX_OFFSET(MCI_COMMAND1) 2631b7d5e03cSMatthew Dillon 2632b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND2 AR_WLAN_COEX_OFFSET(MCI_COMMAND2) 2633b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND2_RESET_TX 0x01 2634b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND2_RESET_TX_S 0 2635b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND2_RESET_RX 0x02 2636b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND2_RESET_RX_S 1 2637b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES 0x3FC 2638b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S 2 2639b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP 0x400 2640b7d5e03cSMatthew Dillon #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S 10 2641b7d5e03cSMatthew Dillon 2642b7d5e03cSMatthew Dillon #define AR_MCI_RX_CTRL AR_WLAN_COEX_OFFSET(MCI_RX_CTRL) 2643b7d5e03cSMatthew Dillon 2644b7d5e03cSMatthew Dillon #define AR_MCI_TX_CTRL AR_WLAN_COEX_OFFSET(MCI_TX_CTRL) 2645b7d5e03cSMatthew Dillon /* 0 = no division, 1 = divide by 2, 2 = divide by 4, 3 = divide by 8 */ 2646b7d5e03cSMatthew Dillon #define AR_MCI_TX_CTRL_CLK_DIV 0x03 2647b7d5e03cSMatthew Dillon #define AR_MCI_TX_CTRL_CLK_DIV_S 0 2648b7d5e03cSMatthew Dillon #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE 0x04 2649b7d5e03cSMatthew Dillon #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S 2 2650b7d5e03cSMatthew Dillon #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ 0xFFFFF8 2651b7d5e03cSMatthew Dillon #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S 3 2652b7d5e03cSMatthew Dillon #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM 0xF000000 2653b7d5e03cSMatthew Dillon #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S 24 2654b7d5e03cSMatthew Dillon 2655b7d5e03cSMatthew Dillon #define AR_MCI_MSG_ATTRIBUTES_TABLE AR_WLAN_COEX_OFFSET(MCI_MSG_ATTRIBUTES_TABLE) 2656b7d5e03cSMatthew Dillon #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM 0xFFFF 2657b7d5e03cSMatthew Dillon #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S 0 2658b7d5e03cSMatthew Dillon #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR 0xFFFF0000 2659b7d5e03cSMatthew Dillon #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S 16 2660b7d5e03cSMatthew Dillon 2661b7d5e03cSMatthew Dillon #define AR_MCI_SCHD_TABLE_0 AR_WLAN_COEX_OFFSET(MCI_SCHD_TABLE_0) 2662b7d5e03cSMatthew Dillon #define AR_MCI_SCHD_TABLE_1 AR_WLAN_COEX_OFFSET(MCI_SCHD_TABLE_1) 2663b7d5e03cSMatthew Dillon #define AR_MCI_GPM_0 AR_WLAN_COEX_OFFSET(MCI_GPM_0) 2664b7d5e03cSMatthew Dillon #define AR_MCI_GPM_1 AR_WLAN_COEX_OFFSET(MCI_GPM_1) 2665b7d5e03cSMatthew Dillon #define AR_MCI_GPM_WRITE_PTR 0xFFFF0000 2666b7d5e03cSMatthew Dillon #define AR_MCI_GPM_WRITE_PTR_S 16 2667b7d5e03cSMatthew Dillon #define AR_MCI_GPM_BUF_LEN 0x0000FFFF 2668b7d5e03cSMatthew Dillon #define AR_MCI_GPM_BUF_LEN_S 0 2669b7d5e03cSMatthew Dillon 2670b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RAW AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_RAW) 2671b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_EN AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_EN) 2672b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_SW_MSG_DONE 0x00000001 2673b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_SW_MSG_DONE_S 0 2674b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_CPU_INT_MSG 0x00000002 2675b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_CPU_INT_MSG_S 1 2676b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL 0x00000004 2677b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S 2 2678b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008 2679b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_INVALID_HDR_S 3 2680b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010 2681b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S 4 2682b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020 2683b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S 5 2684b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080 2685b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S 7 2686b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100 2687b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S 8 2688b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG 0x00000200 2689b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_S 9 2690b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400 2691b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S 10 2692b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_BT_PRI 0x07fff800 2693b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_BT_PRI_S 11 2694b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_BT_PRI_THRESH 0x08000000 2695b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_BT_PRI_THRESH_S 27 2696b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_BT_FREQ 0x10000000 2697b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_BT_FREQ_S 28 2698b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_BT_STOMP 0x20000000 2699b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_BT_STOMP_S 29 2700b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_BB_AIC_IRQ 0x40000000 2701b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_BB_AIC_IRQ_S 30 2702b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000 2703b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S 31 2704b7d5e03cSMatthew Dillon 2705b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_MSG_FAIL_MASK ( AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ 2706b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ 2707b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ 2708b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_TX_SW_MSG_FAIL ) 2709b7d5e03cSMatthew Dillon 2710b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_DEFAULT ( AR_MCI_INTERRUPT_SW_MSG_DONE | \ 2711b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_INVALID_HDR | \ 2712b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ 2713b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ 2714b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ 2715b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_TX_SW_MSG_FAIL | \ 2716b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG | \ 2717b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE | \ 2718b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT ) 2719b7d5e03cSMatthew Dillon 2720b7d5e03cSMatthew Dillon #define AR_MCI_REMOTE_CPU_INT AR_WLAN_COEX_OFFSET(MCI_REMOTE_CPU_INT) 2721b7d5e03cSMatthew Dillon #define AR_MCI_REMOTE_CPU_INT_EN AR_WLAN_COEX_OFFSET(MCI_REMOTE_CPU_INT_EN) 2722b7d5e03cSMatthew Dillon 2723b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_RAW AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_RX_MSG_RAW) 2724b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_EN AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_RX_MSG_EN) 2725b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 2726b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0 2727b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 2728b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1 2729b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 2730b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2 2731b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 2732b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3 2733b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 2734b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4 2735b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 2736b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5 2737b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 2738b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6 2739b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 2740b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8 2741b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 2742b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9 2743b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 2744b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10 2745b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 2746b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11 2747b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 2748b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12 2749b7d5e03cSMatthew Dillon #ifdef AH_DEBUG 2750b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_DEFAULT ( AR_MCI_INTERRUPT_RX_MSG_GPM | \ 2751b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | \ 2752b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \ 2753b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING | \ 2754b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ 2755b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ 2756b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ 2757b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ 2758b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ 2759b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_CONT_RST | \ 2760b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE ) 2761b7d5e03cSMatthew Dillon #else 2762b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_MSG_DEFAULT ( AR_MCI_INTERRUPT_RX_MSG_GPM | \ 2763b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | \ 2764b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \ 2765b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING | \ 2766b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE ) 2767b7d5e03cSMatthew Dillon #endif 2768b7d5e03cSMatthew Dillon #define AR_MCI_INTERRUPT_RX_HW_MSG_MASK ( AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ 2769b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ 2770b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ 2771b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ 2772b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ 2773b7d5e03cSMatthew Dillon AR_MCI_INTERRUPT_RX_MSG_CONT_RST ) 2774b7d5e03cSMatthew Dillon 2775b7d5e03cSMatthew Dillon #define AR_MCI_CPU_INT AR_WLAN_COEX_OFFSET(MCI_CPU_INT) 2776b7d5e03cSMatthew Dillon 2777b7d5e03cSMatthew Dillon #define AR_MCI_RX_STATUS AR_WLAN_COEX_OFFSET(MCI_RX_STATUS) 2778b7d5e03cSMatthew Dillon #define AR_MCI_RX_LAST_SCHD_MSG_INDEX 0x00000F00 2779b7d5e03cSMatthew Dillon #define AR_MCI_RX_LAST_SCHD_MSG_INDEX_S 8 2780b7d5e03cSMatthew Dillon #define AR_MCI_RX_REMOTE_SLEEP 0x00001000 2781b7d5e03cSMatthew Dillon #define AR_MCI_RX_REMOTE_SLEEP_S 12 2782b7d5e03cSMatthew Dillon #define AR_MCI_RX_MCI_CLK_REQ 0x00002000 2783b7d5e03cSMatthew Dillon #define AR_MCI_RX_MCI_CLK_REQ_S 13 2784b7d5e03cSMatthew Dillon 2785b7d5e03cSMatthew Dillon #define AR_MCI_CONT_STATUS AR_WLAN_COEX_OFFSET(MCI_CONT_STATUS) 2786b7d5e03cSMatthew Dillon #define AR_MCI_CONT_RSSI_POWER 0x000000FF 2787b7d5e03cSMatthew Dillon #define AR_MCI_CONT_RSSI_POWER_S 0 2788b7d5e03cSMatthew Dillon #define AR_MCI_CONT_RRIORITY 0x0000FF00 2789b7d5e03cSMatthew Dillon #define AR_MCI_CONT_RRIORITY_S 8 2790b7d5e03cSMatthew Dillon #define AR_MCI_CONT_TXRX 0x00010000 2791b7d5e03cSMatthew Dillon #define AR_MCI_CONT_TXRX_S 16 2792b7d5e03cSMatthew Dillon 2793b7d5e03cSMatthew Dillon #define AR_MCI_BT_PRI0 AR_WLAN_COEX_OFFSET(MCI_BT_PRI0) 2794b7d5e03cSMatthew Dillon #define AR_MCI_BT_PRI1 AR_WLAN_COEX_OFFSET(MCI_BT_PRI1) 2795b7d5e03cSMatthew Dillon #define AR_MCI_BT_PRI2 AR_WLAN_COEX_OFFSET(MCI_BT_PRI2) 2796b7d5e03cSMatthew Dillon #define AR_MCI_BT_PRI3 AR_WLAN_COEX_OFFSET(MCI_BT_PRI3) 2797b7d5e03cSMatthew Dillon #define AR_MCI_BT_PRI AR_WLAN_COEX_OFFSET(MCI_BT_PRI) 2798b7d5e03cSMatthew Dillon #define AR_MCI_WL_FREQ0 AR_WLAN_COEX_OFFSET(MCI_WL_FREQ0) 2799b7d5e03cSMatthew Dillon #define AR_MCI_WL_FREQ1 AR_WLAN_COEX_OFFSET(MCI_WL_FREQ1) 2800b7d5e03cSMatthew Dillon #define AR_MCI_WL_FREQ2 AR_WLAN_COEX_OFFSET(MCI_WL_FREQ2) 2801b7d5e03cSMatthew Dillon #define AR_MCI_GAIN AR_WLAN_COEX_OFFSET(MCI_GAIN) 2802b7d5e03cSMatthew Dillon #define AR_MCI_WBTIMER1 AR_WLAN_COEX_OFFSET(MCI_WBTIMER1) 2803b7d5e03cSMatthew Dillon #define AR_MCI_WBTIMER2 AR_WLAN_COEX_OFFSET(MCI_WBTIMER2) 2804b7d5e03cSMatthew Dillon #define AR_MCI_WBTIMER3 AR_WLAN_COEX_OFFSET(MCI_WBTIMER3) 2805b7d5e03cSMatthew Dillon #define AR_MCI_WBTIMER4 AR_WLAN_COEX_OFFSET(MCI_WBTIMER4) 2806b7d5e03cSMatthew Dillon #define AR_MCI_MAXGAIN AR_WLAN_COEX_OFFSET(MCI_MAXGAIN) 2807b7d5e03cSMatthew Dillon #define AR_MCI_HW_SCHD_TBL_CTL AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_CTL) 2808b7d5e03cSMatthew Dillon #define AR_MCI_HW_SCHD_TBL_D0 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D0) 2809b7d5e03cSMatthew Dillon #define AR_MCI_HW_SCHD_TBL_D1 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D1) 2810b7d5e03cSMatthew Dillon #define AR_MCI_HW_SCHD_TBL_D2 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D2) 2811b7d5e03cSMatthew Dillon #define AR_MCI_HW_SCHD_TBL_D3 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D3) 2812b7d5e03cSMatthew Dillon #define AR_MCI_TX_PAYLOAD0 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD0) 2813b7d5e03cSMatthew Dillon #define AR_MCI_TX_PAYLOAD1 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD1) 2814b7d5e03cSMatthew Dillon #define AR_MCI_TX_PAYLOAD2 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD2) 2815b7d5e03cSMatthew Dillon #define AR_MCI_TX_PAYLOAD3 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD3) 2816b7d5e03cSMatthew Dillon #define AR_BTCOEX_WBTIMER AR_WLAN_COEX_OFFSET(BTCOEX_WBTIMER) 2817b7d5e03cSMatthew Dillon 2818b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL AR_WLAN_COEX_OFFSET(BTCOEX_CTRL) 2819b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_JUPITER_MODE 0x00000001 2820b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_JUPITER_MODE_S 0 2821b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_WBTIMER_EN 0x00000002 2822b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_WBTIMER_EN_S 1 2823b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_MCI_MODE_EN 0x00000004 2824b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_MCI_MODE_EN_S 2 2825b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_LNA_SHARED 0x00000008 2826b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_LNA_SHARED_S 3 2827b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_PA_SHARED 0x00000010 2828b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_PA_SHARED_S 4 2829b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN 0x00000020 2830b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S 5 2831b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN 0x00000040 2832b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S 6 2833b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_NUM_ANTENNAS 0x00000180 2834b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_NUM_ANTENNAS_S 7 2835b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_RX_CHAIN_MASK 0x00000E00 2836b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_RX_CHAIN_MASK_S 9 2837b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_AGGR_THRESH 0x00007000 2838b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_AGGR_THRESH_S 12 2839b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_1_CHAIN_BCN 0x00080000 2840b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_1_CHAIN_BCN_S 19 2841b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_1_CHAIN_ACK 0x00100000 2842b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_1_CHAIN_ACK_S 20 2843b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN 0x1FE00000 2844b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S 28 2845b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_REDUCE_TXPWR 0x20000000 2846b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_REDUCE_TXPWR_S 29 2847b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_SPDT_ENABLE_10 0x40000000 2848b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_SPDT_ENABLE_10_S 30 2849b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000 2850b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31 2851b7d5e03cSMatthew Dillon 2852b7d5e03cSMatthew Dillon #define AR_BTCOEX_WL_WEIGHTS0 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS0) 2853b7d5e03cSMatthew Dillon #define AR_BTCOEX_WL_WEIGHTS1 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS1) 2854b7d5e03cSMatthew Dillon #define AR_BTCOEX_WL_WEIGHTS2 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS2) 2855b7d5e03cSMatthew Dillon #define AR_BTCOEX_WL_WEIGHTS3 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS3) 2856b7d5e03cSMatthew Dillon #define AR_BTCOEX_MAX_TXPWR(_x) (AR_WLAN_COEX_OFFSET(BTCOEX_MAX_TXPWR) + ((_x) << 2)) 2857b7d5e03cSMatthew Dillon #define AR_BTCOEX_WL_LNA AR_WLAN_COEX_OFFSET(BTCOEX_WL_LNA) 2858b7d5e03cSMatthew Dillon #define AR_BTCOEX_RFGAIN_CTRL AR_WLAN_COEX_OFFSET(BTCOEX_RFGAIN_CTRL) 2859b7d5e03cSMatthew Dillon 2860b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL2 AR_WLAN_COEX_OFFSET(BTCOEX_CTRL2) 2861b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL2_TXPWR_THRESH 0x0007F800 2862b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL2_TXPWR_THRESH_S 11 2863b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK 0x00380000 2864b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S 19 2865b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL2_RX_DEWEIGHT 0x00400000 2866b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL2_RX_DEWEIGHT_S 22 2867b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL 0x00800000 2868b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S 23 2869b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL 0x01000000 2870b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S 24 2871b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE 0x02000000 2872b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S 25 2873b7d5e03cSMatthew Dillon 2874b7d5e03cSMatthew Dillon #define AR_BTCOEX_RC AR_WLAN_COEX_OFFSET(BTCOEX_RC) 2875b7d5e03cSMatthew Dillon #define AR_BTCOEX_MAX_RFGAIN(_x) AR_WLAN_COEX_OFFSET(BTCOEX_MAX_RFGAIN[_x]) 2876b7d5e03cSMatthew Dillon #define AR_BTCOEX_DBG AR_WLAN_COEX_OFFSET(BTCOEX_DBG) 2877b7d5e03cSMatthew Dillon #define AR_MCI_LAST_HW_MSG_HDR AR_WLAN_COEX_OFFSET(MCI_LAST_HW_MSG_HDR) 2878b7d5e03cSMatthew Dillon #define AR_MCI_LAST_HW_MSG_BDY AR_WLAN_COEX_OFFSET(MCI_LAST_HW_MSG_BDY) 2879b7d5e03cSMatthew Dillon 2880b7d5e03cSMatthew Dillon #define AR_MCI_SCHD_TABLE_2 AR_WLAN_COEX_OFFSET(MCI_SCHD_TABLE_2) 2881b7d5e03cSMatthew Dillon #define AR_MCI_SCHD_TABLE_2_MEM_BASED 0x00000001 2882b7d5e03cSMatthew Dillon #define AR_MCI_SCHD_TABLE_2_MEM_BASED_S 0 2883b7d5e03cSMatthew Dillon #define AR_MCI_SCHD_TABLE_2_HW_BASED 0x00000002 2884b7d5e03cSMatthew Dillon #define AR_MCI_SCHD_TABLE_2_HW_BASED_S 1 2885b7d5e03cSMatthew Dillon 2886b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL3 AR_WLAN_COEX_OFFSET(BTCOEX_CTRL3) 2887b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT 0x00000FFF 2888b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0 2889b7d5e03cSMatthew Dillon 2890b7d5e03cSMatthew Dillon /****************************************************************************** 2891b7d5e03cSMatthew Dillon * WLAN BT Global Register Map 2892b7d5e03cSMatthew Dillon ******************************************************************************/ 2893b7d5e03cSMatthew Dillon #define AR_WLAN_BT_GLB_OFFSET(_x) offsetof(struct wlan_bt_glb_reg_pcie, _x) 2894b7d5e03cSMatthew Dillon 2895b7d5e03cSMatthew Dillon /* 2896b7d5e03cSMatthew Dillon * WLAN BT Global Registers 2897b7d5e03cSMatthew Dillon */ 2898b7d5e03cSMatthew Dillon 2899b7d5e03cSMatthew Dillon #define AR_GLB_GPIO_CONTROL AR_WLAN_BT_GLB_OFFSET(GLB_GPIO_CONTROL) 2900b7d5e03cSMatthew Dillon #define AR_GLB_WLAN_WOW_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_WLAN_WOW_STATUS) 2901b7d5e03cSMatthew Dillon #define AR_GLB_WLAN_WOW_ENABLE AR_WLAN_BT_GLB_OFFSET(GLB_WLAN_WOW_ENABLE) 2902b7d5e03cSMatthew Dillon #define AR_GLB_EMB_CPU_WOW_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_EMB_CPU_WOW_STATUS) 2903b7d5e03cSMatthew Dillon #define AR_GLB_EMB_CPU_WOW_ENABLE AR_WLAN_BT_GLB_OFFSET(GLB_EMB_CPU_WOW_ENABLE) 2904b7d5e03cSMatthew Dillon #define AR_GLB_MBOX_CONTROL_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_MBOX_CONTROL_STATUS) 2905b7d5e03cSMatthew Dillon #define AR_GLB_SW_WOW_CLK_CONTROL AR_WLAN_BT_GLB_OFFSET(GLB_SW_WOW_CLK_CONTROL) 2906b7d5e03cSMatthew Dillon #define AR_GLB_APB_TIMEOUT AR_WLAN_BT_GLB_OFFSET(GLB_APB_TIMEOUT) 2907b7d5e03cSMatthew Dillon #define AR_GLB_OTP_LDO_CONTROL AR_WLAN_BT_GLB_OFFSET(GLB_OTP_LDO_CONTROL) 2908b7d5e03cSMatthew Dillon #define AR_GLB_OTP_LDO_POWER_GOOD AR_WLAN_BT_GLB_OFFSET(GLB_OTP_LDO_POWER_GOOD) 2909b7d5e03cSMatthew Dillon #define AR_GLB_OTP_LDO_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_OTP_LDO_STATUS) 2910b7d5e03cSMatthew Dillon #define AR_GLB_SWREG_DISCONT_MODE AR_WLAN_BT_GLB_OFFSET(GLB_SWREG_DISCONT_MODE) 2911b7d5e03cSMatthew Dillon #define AR_GLB_BT_GPIO_REMAP_OUT_CONTROL0 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_OUT_CONTROL0) 2912b7d5e03cSMatthew Dillon #define AR_GLB_BT_GPIO_REMAP_OUT_CONTROL1 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_OUT_CONTROL1) 2913b7d5e03cSMatthew Dillon #define AR_GLB_BT_GPIO_REMAP_IN_CONTROL0 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_IN_CONTROL0) 2914b7d5e03cSMatthew Dillon #define AR_GLB_BT_GPIO_REMAP_IN_CONTROL1 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_IN_CONTROL1) 2915b7d5e03cSMatthew Dillon #define AR_GLB_BT_GPIO_REMAP_IN_CONTROL2 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_IN_CONTROL2) 2916b7d5e03cSMatthew Dillon #define AR_GLB_SCRATCH(_ah) \ 2917b7d5e03cSMatthew Dillon (AR_SREV_APHRODITE(_ah)? \ 2918b7d5e03cSMatthew Dillon AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Aphrodite_10.GLB_SCRATCH) : \ 2919b7d5e03cSMatthew Dillon (AR_SREV_JUPITER_20(_ah) ? \ 2920b7d5e03cSMatthew Dillon AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_20.GLB_SCRATCH) : \ 2921b7d5e03cSMatthew Dillon AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_10.GLB_SCRATCH))) 2922b7d5e03cSMatthew Dillon 2923b7d5e03cSMatthew Dillon #define AR_GLB_CONTROL AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_20.GLB_CONTROL) 2924b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_SPDT_ENABLE 0x00000001 2925b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_SPDT_ENABLE_S 0 2926b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL 0x00000002 2927b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S 1 2928b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT 0x00000004 2929b7d5e03cSMatthew Dillon #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S 2 2930b7d5e03cSMatthew Dillon #define AR_GLB_WLAN_UART_INTF_EN 0x00020000 2931b7d5e03cSMatthew Dillon #define AR_GLB_WLAN_UART_INTF_EN_S 17 2932b7d5e03cSMatthew Dillon #define AR_GLB_DS_JTAG_DISABLE 0x00040000 2933b7d5e03cSMatthew Dillon #define AR_GLB_DS_JTAG_DISABLE_S 18 2934b7d5e03cSMatthew Dillon 2935b7d5e03cSMatthew Dillon #define AR_GLB_STATUS AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_20.GLB_STATUS) 2936b7d5e03cSMatthew Dillon 2937b7d5e03cSMatthew Dillon /* 2938b7d5e03cSMatthew Dillon * MAC Version and Revision 2939b7d5e03cSMatthew Dillon */ 2940b7d5e03cSMatthew Dillon 2941b7d5e03cSMatthew Dillon #define AR_SREV_VERSION_OSPREY 0x1C0 2942b7d5e03cSMatthew Dillon #define AR_SREV_VERSION_AR9580 0x1C0 2943b7d5e03cSMatthew Dillon #define AR_SREV_VERSION_JUPITER 0x280 2944b7d5e03cSMatthew Dillon #define AR_SREV_VERSION_HORNET 0x200 2945b7d5e03cSMatthew Dillon #define AR_SREV_VERSION_WASP 0x300 /* XXX: Check Wasp version number */ 2946b7d5e03cSMatthew Dillon #define AR_SREV_VERSION_SCORPION 0x400 2947b7d5e03cSMatthew Dillon #define AR_SREV_VERSION_POSEIDON 0x240 2948*a20e5e51SMatthew Dillon #define AR_SREV_VERSION_HONEYBEE 0x500 2949b7d5e03cSMatthew Dillon #define AR_SREV_VERSION_APHRODITE 0x2C0 2950b7d5e03cSMatthew Dillon 2951b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_OSPREY_10 0 /* Osprey 1.0 */ 2952b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_OSPREY_20 2 /* Osprey 2.0/2.1 */ 2953b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_OSPREY_22 3 /* Osprey 2.2 */ 2954b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_AR9580_10 4 /* AR9580/Peacock 1.0 */ 2955b7d5e03cSMatthew Dillon 2956b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_HORNET_10 0 /* Hornet 1.0 */ 2957b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_HORNET_11 1 /* Hornet 1.1 */ 2958b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_HORNET_12 2 /* Hornet 1.2 */ 2959b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_HORNET_11_MASK 0xf /* Hornet 1.1 revision mask */ 2960b7d5e03cSMatthew Dillon 2961b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_POSEIDON_10 0 /* Poseidon 1.0 */ 2962b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_POSEIDON_11 1 /* Poseidon 1.1 */ 2963b7d5e03cSMatthew Dillon 2964b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_WASP_10 0 /* Wasp 1.0 */ 2965b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_WASP_11 1 /* Wasp 1.1 */ 2966b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_WASP_12 2 /* Wasp 1.2 */ 2967b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_WASP_13 3 /* Wasp 1.3 */ 2968b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_WASP_MASK 0xf /* Wasp revision mask */ 2969b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_WASP_MINOR_MINOR_MASK 0x10000 /* Wasp minor minor revision mask */ 2970b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT 16 /* Wasp minor minor revision shift */ 2971b7d5e03cSMatthew Dillon 2972b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_JUPITER_10 0 /* Jupiter 1.0 */ 2973b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_JUPITER_20 2 /* Jupiter 2.0 */ 2974*a20e5e51SMatthew Dillon #define AR_SREV_REVISION_JUPITER_21 3 /* Jupiter 2.1 */ 2975*a20e5e51SMatthew Dillon 2976*a20e5e51SMatthew Dillon #define AR_SREV_REVISION_HONEYBEE_10 0 /* Honeybee 1.0 */ 2977*a20e5e51SMatthew Dillon #define AR_SREV_REVISION_HONEYBEE_11 1 /* Honeybee 1.1 */ 2978*a20e5e51SMatthew Dillon #define AR_SREV_REVISION_HONEYBEE_MASK 0xf /* Honeybee revision mask */ 2979b7d5e03cSMatthew Dillon 2980b7d5e03cSMatthew Dillon #define AR_SREV_REVISION_APHRODITE_10 0 /* Aphrodite 1.0 */ 2981b7d5e03cSMatthew Dillon 2982b7d5e03cSMatthew Dillon #if defined(AH_SUPPORT_OSPREY) 2983b7d5e03cSMatthew Dillon #define AR_SREV_OSPREY(_ah) \ 2984b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_OSPREY)) 2985b7d5e03cSMatthew Dillon 2986b7d5e03cSMatthew Dillon #define AR_SREV_OSPREY_22(_ah) \ 2987b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) && \ 2988b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OSPREY_22)) 2989b7d5e03cSMatthew Dillon #else 2990b7d5e03cSMatthew Dillon #define AR_SREV_OSPREY(_ah) 0 2991b7d5e03cSMatthew Dillon #define AR_SREV_OSPREY_10(_ah) 0 2992b7d5e03cSMatthew Dillon #define AR_SREV_OSPREY_20(_ah) 0 2993b7d5e03cSMatthew Dillon #define AR_SREV_OSPREY_22(_ah) 0 2994b7d5e03cSMatthew Dillon #define AR_SREV_OSPREY_20_OR_LATER(_ah) 0 2995b7d5e03cSMatthew Dillon #define AR_SREV_OSPREY_22_OR_LATER(_ah) 0 2996b7d5e03cSMatthew Dillon #endif /* #if defined(AH_SUPPORT_OSPREY) */ 2997b7d5e03cSMatthew Dillon 2998b7d5e03cSMatthew Dillon #define AR_SREV_AR9580(_ah) \ 2999b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && \ 3000b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_AR9580_10)) 3001b7d5e03cSMatthew Dillon 3002b7d5e03cSMatthew Dillon #define AR_SREV_AR9580_10(_ah) \ 3003b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && \ 3004b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_AR9580_10)) 3005b7d5e03cSMatthew Dillon 3006b7d5e03cSMatthew Dillon /* NOTE: When adding chips newer than Peacock, add chip check here. */ 3007b7d5e03cSMatthew Dillon #define AR_SREV_AR9580_10_OR_LATER(_ah) \ 3008*a20e5e51SMatthew Dillon (AR_SREV_AR9580(_ah) || AR_SREV_SCORPION(_ah) || AR_SREV_HONEYBEE(_ah)) 3009b7d5e03cSMatthew Dillon 3010b7d5e03cSMatthew Dillon #define AR_SREV_JUPITER(_ah) \ 3011b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER)) 3012b7d5e03cSMatthew Dillon 3013b7d5e03cSMatthew Dillon #define AR_SREV_JUPITER_10(_ah) \ 3014b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ 3015b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_JUPITER_10)) 3016b7d5e03cSMatthew Dillon 3017b7d5e03cSMatthew Dillon #define AR_SREV_JUPITER_20(_ah) \ 3018b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ 3019b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_JUPITER_20)) 3020b7d5e03cSMatthew Dillon 3021*a20e5e51SMatthew Dillon #define AR_SREV_JUPITER_21(_ah) \ 3022*a20e5e51SMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ 3023*a20e5e51SMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_JUPITER_21)) 3024*a20e5e51SMatthew Dillon 3025b7d5e03cSMatthew Dillon #define AR_SREV_JUPITER_20_OR_LATER(_ah) \ 3026b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ 3027b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_JUPITER_20)) 3028b7d5e03cSMatthew Dillon 3029*a20e5e51SMatthew Dillon #define AR_SREV_JUPITER_21_OR_LATER(_ah) \ 3030*a20e5e51SMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ 3031*a20e5e51SMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_JUPITER_21)) 3032*a20e5e51SMatthew Dillon 3033b7d5e03cSMatthew Dillon #define AR_SREV_APHRODITE(_ah) \ 3034b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_APHRODITE)) 3035b7d5e03cSMatthew Dillon 3036b7d5e03cSMatthew Dillon #define AR_SREV_APHRODITE_10(_ah) \ 3037b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_APHRODITE) && \ 3038b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_APHRODITE_10)) 3039b7d5e03cSMatthew Dillon 3040b7d5e03cSMatthew Dillon #if defined(AH_SUPPORT_HORNET) 3041b7d5e03cSMatthew Dillon #define AR_SREV_HORNET_10(_ah) \ 3042b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HORNET) && \ 3043b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HORNET_10)) 3044b7d5e03cSMatthew Dillon 3045b7d5e03cSMatthew Dillon #define AR_SREV_HORNET_11(_ah) \ 3046b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HORNET) && \ 3047b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HORNET_11)) 3048b7d5e03cSMatthew Dillon 3049b7d5e03cSMatthew Dillon #define AR_SREV_HORNET_12(_ah) \ 3050b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HORNET) && \ 3051b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HORNET_12)) 3052b7d5e03cSMatthew Dillon 3053b7d5e03cSMatthew Dillon #define AR_SREV_HORNET(_ah) \ 3054b7d5e03cSMatthew Dillon ( AR_SREV_HORNET_10(_ah) || AR_SREV_HORNET_11(_ah) || AR_SREV_HORNET_12(_ah) ) 3055b7d5e03cSMatthew Dillon #else 3056b7d5e03cSMatthew Dillon #define AR_SREV_HORNET_10(_ah) 0 3057b7d5e03cSMatthew Dillon #define AR_SREV_HORNET_11(_ah) 0 3058b7d5e03cSMatthew Dillon #define AR_SREV_HORNET_12(_ah) 0 3059b7d5e03cSMatthew Dillon #define AR_SREV_HORNET(_ah) 0 3060b7d5e03cSMatthew Dillon #endif /* #if defined(AH_SUPPORT_HORNET) */ 3061b7d5e03cSMatthew Dillon 3062b7d5e03cSMatthew Dillon #if defined(AH_SUPPORT_WASP) 3063b7d5e03cSMatthew Dillon #define AR_SREV_WASP(_ah) \ 3064b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP)) 3065b7d5e03cSMatthew Dillon #else 3066b7d5e03cSMatthew Dillon #define AR_SREV_WASP(_ah) 0 3067b7d5e03cSMatthew Dillon #endif /* #if defined(AH_SUPPORT_WASP) */ 3068b7d5e03cSMatthew Dillon 3069*a20e5e51SMatthew Dillon #if defined(AH_SUPPORT_HONEYBEE) 3070*a20e5e51SMatthew Dillon #define AR_SREV_HONEYBEE(_ah) \ 3071*a20e5e51SMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HONEYBEE)) 3072*a20e5e51SMatthew Dillon #define AR_SREV_HONEYBEE_10(_ah) \ 3073*a20e5e51SMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HONEYBEE) && \ 3074*a20e5e51SMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HONEYBEE_10)) 3075*a20e5e51SMatthew Dillon #define AR_SREV_HONEYBEE_11(_ah) \ 3076*a20e5e51SMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HONEYBEE) && \ 3077*a20e5e51SMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HONEYBEE_11)) 3078*a20e5e51SMatthew Dillon #else 3079*a20e5e51SMatthew Dillon #define AR_SREV_HONEYBEE(_ah) 0 3080*a20e5e51SMatthew Dillon #define AR_SREV_HONEYBEE_10(_ah) 0 3081*a20e5e51SMatthew Dillon #define AR_SREV_HONEYBEE_11(_ah) 0 3082*a20e5e51SMatthew Dillon #endif /* #if defined(AH_SUPPORT_HONEYBEE) */ 3083*a20e5e51SMatthew Dillon 3084b7d5e03cSMatthew Dillon #define AR_SREV_WASP_10(_ah) \ 3085b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \ 3086b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_10)) 3087b7d5e03cSMatthew Dillon 3088b7d5e03cSMatthew Dillon #define AR_SREV_WASP_11(_ah) \ 3089b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \ 3090b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_11)) 3091b7d5e03cSMatthew Dillon 3092b7d5e03cSMatthew Dillon #define AR_SREV_WASP_12(_ah) \ 3093b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \ 3094b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_12)) 3095b7d5e03cSMatthew Dillon 3096b7d5e03cSMatthew Dillon #if defined(AH_SUPPORT_SCORPION) 3097b7d5e03cSMatthew Dillon #define AR_SREV_SCORPION(_ah) \ 3098b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_SCORPION)) 3099b7d5e03cSMatthew Dillon #else 3100b7d5e03cSMatthew Dillon #define AR_SREV_SCORPION(_ah) 0 3101b7d5e03cSMatthew Dillon #endif /* #if defined(AH_SUPPORT_SCORPION) */ 3102b7d5e03cSMatthew Dillon 3103b7d5e03cSMatthew Dillon #if defined(AH_SUPPORT_POSEIDON) 3104b7d5e03cSMatthew Dillon #define AR_SREV_POSEIDON(_ah) \ 3105b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON)) 3106b7d5e03cSMatthew Dillon 3107b7d5e03cSMatthew Dillon #define AR_SREV_POSEIDON_10(_ah) \ 3108b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON) && \ 3109b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_POSEIDON_10)) 3110b7d5e03cSMatthew Dillon 3111b7d5e03cSMatthew Dillon #define AR_SREV_POSEIDON_11(_ah) \ 3112b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON) && \ 3113b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_POSEIDON_11)) 3114b7d5e03cSMatthew Dillon #else 3115b7d5e03cSMatthew Dillon #define AR_SREV_POSEIDON(_ah) 0 3116b7d5e03cSMatthew Dillon #define AR_SREV_POSEIDON_10(_ah) 0 3117b7d5e03cSMatthew Dillon #define AR_SREV_POSEIDON_11(_ah) 0 3118b7d5e03cSMatthew Dillon #endif /* #if defined(AH_SUPPORT_POSEIDON) */ 3119b7d5e03cSMatthew Dillon 3120b7d5e03cSMatthew Dillon #define AR_SREV_POSEIDON_11_OR_LATER(_ah) \ 3121b7d5e03cSMatthew Dillon ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON) && \ 3122b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_POSEIDON_11)) 3123b7d5e03cSMatthew Dillon 3124b7d5e03cSMatthew Dillon #define AR_SREV_POSEIDON_OR_LATER(_ah) \ 3125b7d5e03cSMatthew Dillon (AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_POSEIDON) 3126*a20e5e51SMatthew Dillon #define AR_SREV_SOC(_ah) (AR_SREV_HORNET(_ah) || AR_SREV_POSEIDON(_ah) || AR_SREV_WASP(_ah) || AR_SREV_HONEYBEE(_ah)) 3127b7d5e03cSMatthew Dillon /* 3128b7d5e03cSMatthew Dillon * Mask used to construct AAD for CCMP-AES 3129b7d5e03cSMatthew Dillon * Cisco spec defined bits 0-3 as mask 3130b7d5e03cSMatthew Dillon * IEEE802.11w defined as bit 4. 3131b7d5e03cSMatthew Dillon */ 3132b7d5e03cSMatthew Dillon #define AR_MFP_QOS_MASK_IEEE 0x10 3133b7d5e03cSMatthew Dillon #define AR_MFP_QOS_MASK_CISCO 0xf 3134b7d5e03cSMatthew Dillon 3135b7d5e03cSMatthew Dillon /* 3136b7d5e03cSMatthew Dillon * frame control field mask: 3137b7d5e03cSMatthew Dillon * 0 0 0 0 0 0 0 0 3138b7d5e03cSMatthew Dillon * | | | | | | | | _ Order bit 3139b7d5e03cSMatthew Dillon * | | | | | | | _ _ Protected Frame bit 3140b7d5e03cSMatthew Dillon * | | | | | | _ _ _ More data bit 3141b7d5e03cSMatthew Dillon * | | | | | _ _ _ _ Power management bit 3142b7d5e03cSMatthew Dillon * | | | | _ _ _ _ _ Retry bit 3143b7d5e03cSMatthew Dillon * | | | _ _ _ _ _ _ More fragments bit 3144b7d5e03cSMatthew Dillon * | | _ _ _ _ _ _ _ FromDS bit 3145b7d5e03cSMatthew Dillon * | _ _ _ _ _ _ _ _ ToDS bit 3146b7d5e03cSMatthew Dillon */ 3147b7d5e03cSMatthew Dillon #define AR_AES_MUTE_MASK1_FC_MGMT_MFP 0xC7FF 3148b7d5e03cSMatthew Dillon #endif 3149