1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 /* 18 * READ THIS NOTICE! 19 * 20 * Values defined in this file may only be changed under exceptional circumstances. 21 * 22 * Please ask Fiona Cain before making any changes. 23 */ 24 25 #ifndef __ar9300template_cus157_h__ 26 #define __ar9300template_cus157_h__ 27 28 static ar9300_eeprom_t Ar9300Template_cus157= 29 { 30 31 2, // eepromVersion; 32 33 ar9300_eeprom_template_cus157, // templateVersion; 34 35 {0x00,0x03,0x7f,0x0,0x0,0x0}, //macAddr[6]; 36 37 //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= 38 39 {"cus157-030-f0000"}, 40 // {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 41 42 //static OSPREY_BASE_EEP_HEADER baseEepHeader= 43 44 { 45 {0,0x1f}, // regDmn[2]; //Does this need to be outside of this structure, if it gets written after calibration 46 0x77, // txrxMask; //4 bits tx and 4 bits rx 47 {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // opCapFlags; 48 0, // rfSilent; 49 0, // blueToothOptions; 50 0, // deviceCap; 51 5, // deviceType; // takes lower byte in eeprom location 52 OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration 53 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don 54 0x0d, //featureEnable; //bit0 - enable tx temp comp 55 //bit1 - enable tx volt comp 56 //bit2 - enable fastClock - default to 1 57 //bit3 - enable doubling - default to 1 58 //bit4 - enable internal regulator - default to 0 59 //bit5 - enable paprd -- default to 0 60 0, //miscConfiguration: bit0 - turn down drivestrength 61 6, // eepromWriteEnableGpio 62 0, // wlanDisableGpio 63 8, // wlanLedGpio 64 0xff, // rxBandSelectGpio 65 0x10, // txrxgain 66 0, // swreg 67 }, 68 69 70 //static OSPREY_MODAL_EEP_HEADER modalHeader2G= 71 { 72 73 0x110, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting) 74 0x44444, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 75 {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 76 {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 77 {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 78 25, // tempSlope; 79 0, // voltSlope; 80 {FREQ2FBIN(2464, 1),0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 81 {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 82 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 83 0, // quick drop 84 0, // xpaBiasLvl; // 1 85 0x0e, // txFrameToDataStart; // 1 86 0x0e, // txFrameToPaOn; // 1 87 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 88 0, // antennaGain; // 1 89 0x2c, // switchSettling; // 1 90 -30, // adcDesiredSize; // 1 91 0, // txEndToXpaOff; // 1 92 0x2, // txEndToRxOn; // 1 93 0xe, // txFrameToXpaOn; // 1 94 28, // thresh62; // 1 95 0x80C080, // paprdRateMaskHt20 // 4 96 0x80C080, // paprdRateMaskHt40 97 0, // ant_div_control 98 {0,0,0,0,0,0,0,0,0} //futureModal[9]; 99 }, 100 101 {{0,0,0,0,0,0,0,0,0,0,0,0,0,0}}, // base_ext1 102 103 //static A_UINT8 calFreqPier2G[OSPREY_NUM_2G_CAL_PIERS]= 104 { 105 FREQ2FBIN(2412, 1), 106 FREQ2FBIN(2437, 1), 107 FREQ2FBIN(2462, 1) 108 }, 109 110 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData2G[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= 111 112 { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 113 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 114 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 115 }, 116 117 //A_UINT8 calTarget_freqbin_Cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 118 119 { 120 FREQ2FBIN(2412, 1), 121 FREQ2FBIN(2472, 1) 122 }, 123 124 //static CAL_TARGET_POWER_LEG calTarget_freqbin_2G[OSPREY_NUM_2G_20_TARGET_POWERS] 125 { 126 FREQ2FBIN(2412, 1), 127 FREQ2FBIN(2437, 1), 128 FREQ2FBIN(2472, 1) 129 }, 130 131 //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS] 132 { 133 FREQ2FBIN(2412, 1), 134 FREQ2FBIN(2437, 1), 135 FREQ2FBIN(2472, 1) 136 }, 137 138 //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS] 139 { 140 FREQ2FBIN(2412, 1), 141 FREQ2FBIN(2437, 1), 142 FREQ2FBIN(2472, 1) 143 }, 144 145 //static CAL_TARGET_POWER_LEG calTargetPowerCck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= 146 { 147 //1L-5L,5S,11L,11S 148 {{34,34,34,34}}, 149 {{34,34,34,34}} 150 }, 151 152 //static CAL_TARGET_POWER_LEG calTargetPower2G[OSPREY_NUM_2G_20_TARGET_POWERS]= 153 { 154 //6-24,36,48,54 155 {{34,34,34,30}}, 156 {{34,34,34,30}}, 157 {{34,34,34,30}}, 158 }, 159 160 //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS]= 161 { 162 //0_8_16,1-3_9-11_17-19, 163 // 4,5,6,7,12,13,14,15,20,21,22,23 164 {{32,32,32,32,30,30,32,32,30,30,32,32,30,30}}, 165 {{32,32,32,32,30,30,32,32,30,30,32,32,30,30}}, 166 {{32,32,32,32,30,30,32,32,30,30,32,32,30,30}}, 167 }, 168 169 //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS]= 170 { 171 //0_8_16,1-3_9-11_17-19, 172 // 4,5,6,7,12,13,14,15,20,21,22,23 173 {{30,30,30,30,30,28,30,30,28,28,30,30,28,26}}, 174 {{30,30,30,30,30,28,30,30,28,28,30,30,28,26}}, 175 {{30,30,30,30,30,28,30,30,28,28,30,30,28,26}}, 176 }, 177 178 //static A_UINT8 ctlIndex_2G[OSPREY_NUM_CTLS_2G]= 179 180 { 181 182 0x11, 183 0x12, 184 0x15, 185 0x17, 186 0x41, 187 0x42, 188 0x45, 189 0x47, 190 0x31, 191 0x32, 192 0x35, 193 0x37 194 195 }, 196 197 //A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; 198 199 { 200 {FREQ2FBIN(2412, 1), 201 FREQ2FBIN(2417, 1), 202 FREQ2FBIN(2457, 1), 203 FREQ2FBIN(2462, 1)}, 204 205 {FREQ2FBIN(2412, 1), 206 FREQ2FBIN(2417, 1), 207 FREQ2FBIN(2462, 1), 208 0xFF}, 209 210 {FREQ2FBIN(2412, 1), 211 FREQ2FBIN(2417, 1), 212 FREQ2FBIN(2462, 1), 213 0xFF}, 214 215 {FREQ2FBIN(2422, 1), 216 FREQ2FBIN(2427, 1), 217 FREQ2FBIN(2447, 1), 218 FREQ2FBIN(2452, 1)}, 219 220 {/*Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 221 /*Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 222 /*Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), 223 /*Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(2484, 1)}, 224 225 {/*Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 226 /*Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 227 /*Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), 228 0}, 229 230 {/*Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 231 /*Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 232 FREQ2FBIN(2472, 1), 233 0}, 234 235 {/*Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1), 236 /*Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1), 237 /*Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1), 238 /*Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)}, 239 240 {/*Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 241 /*Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 242 /*Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), 243 0}, 244 245 {/*Data[9].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 246 /*Data[9].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 247 /*Data[9].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), 248 0}, 249 250 {/*Data[10].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 251 /*Data[10].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 252 /*Data[10].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), 253 0}, 254 255 {/*Data[11].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1), 256 /*Data[11].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1), 257 /*Data[11].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1), 258 /*Data[11].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)} 259 }, 260 261 262 //OSP_CAL_CTL_DATA_2G ctlPowerData_2G[OSPREY_NUM_CTLS_2G]; 263 264 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 265 { 266 267 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 268 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 269 {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, 270 271 {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, 272 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 273 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 274 275 {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, 276 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 277 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 278 279 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 280 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 281 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 282 283 }, 284 #else 285 { 286 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 287 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 288 {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, 289 290 {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, 291 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 292 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 293 294 {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, 295 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 296 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 297 298 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 299 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 300 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 301 }, 302 #endif 303 304 //static OSPREY_MODAL_EEP_HEADER modalHeader5G= 305 306 { 307 308 0x220, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting) 309 0x44444, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 310 {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 311 {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 312 {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 313 45, // tempSlope; 314 0, // voltSlope; 315 {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 316 {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 317 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 318 0, // quick drop 319 0, // xpaBiasLvl; // 1 320 0x0e, // txFrameToDataStart; // 1 321 0x0e, // txFrameToPaOn; // 1 322 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 323 0, // antennaGain; // 1 324 0x2d, // switchSettling; // 1 325 -30, // adcDesiredSize; // 1 326 0, // txEndToXpaOff; // 1 327 0x2, // txEndToRxOn; // 1 328 0xe, // txFrameToXpaOn; // 1 329 28, // thresh62; // 1 330 0xf0e0e0, // paprdRateMaskHt20 // 4 331 0xf0e0e0, // paprdRateMaskHt40 // 4 332 {0,0,0,0,0,0,0,0,0,0} //futureModal[10]; 333 }, 334 335 { // base_ext2 336 40, // tempSlopeLow 337 50, // tempSlopeHigh 338 {0,0,0}, 339 {0,0,0}, 340 {0,0,0}, 341 {0,0,0} 342 }, 343 344 //static A_UINT8 calFreqPier5G[OSPREY_NUM_5G_CAL_PIERS]= 345 { 346 //pPiers[0] = 347 FREQ2FBIN(5180, 0), 348 //pPiers[1] = 349 FREQ2FBIN(5220, 0), 350 //pPiers[2] = 351 FREQ2FBIN(5320, 0), 352 //pPiers[3] = 353 FREQ2FBIN(5400, 0), 354 //pPiers[4] = 355 FREQ2FBIN(5500, 0), 356 //pPiers[5] = 357 FREQ2FBIN(5600, 0), 358 //pPiers[6] = 359 FREQ2FBIN(5700, 0), 360 //pPiers[7] = 361 FREQ2FBIN(5785, 0), 362 }, 363 364 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData5G[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= 365 366 { 367 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 368 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 369 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 370 371 }, 372 373 //static CAL_TARGET_POWER_LEG calTarget_freqbin_5G[OSPREY_NUM_5G_20_TARGET_POWERS]= 374 375 { 376 FREQ2FBIN(5180, 0), 377 FREQ2FBIN(5240, 0), 378 FREQ2FBIN(5320, 0), 379 FREQ2FBIN(5400, 0), 380 FREQ2FBIN(5500, 0), 381 FREQ2FBIN(5600, 0), 382 FREQ2FBIN(5700, 0), 383 FREQ2FBIN(5825, 0) 384 }, 385 386 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]= 387 388 { 389 FREQ2FBIN(5180, 0), 390 FREQ2FBIN(5240, 0), 391 FREQ2FBIN(5320, 0), 392 FREQ2FBIN(5400, 0), 393 FREQ2FBIN(5500, 0), 394 FREQ2FBIN(5700, 0), 395 FREQ2FBIN(5745, 0), 396 FREQ2FBIN(5825, 0) 397 }, 398 399 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]= 400 401 { 402 FREQ2FBIN(5180, 0), 403 FREQ2FBIN(5240, 0), 404 FREQ2FBIN(5320, 0), 405 FREQ2FBIN(5400, 0), 406 FREQ2FBIN(5500, 0), 407 FREQ2FBIN(5700, 0), 408 FREQ2FBIN(5745, 0), 409 FREQ2FBIN(5825, 0) 410 }, 411 412 413 //static CAL_TARGET_POWER_LEG calTargetPower5G[OSPREY_NUM_5G_20_TARGET_POWERS]= 414 415 416 { 417 //6-24,36,48,54 418 {{30,30,26,22}}, 419 {{30,30,26,22}}, 420 {{30,30,30,24}}, 421 {{30,30,30,24}}, 422 {{30,30,26,22}}, 423 {{30,24,20,18}}, 424 {{30,24,20,18}}, 425 {{30,24,20,18}}, 426 }, 427 428 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]= 429 430 { 431 //0_8_16,1-3_9-11_17-19, 432 // 4,5,6,7,12,13,14,15,20,21,22,23 433 {{30,30,30,28,24,20,30,28,24,18,30,26,22,16}}, 434 {{30,30,30,28,24,20,30,28,24,18,30,26,22,16}}, 435 {{30,30,30,26,22,18,30,26,22,16,30,24,20,14}}, 436 {{30,30,30,26,22,18,30,26,22,16,30,24,20,14}}, 437 {{30,30,30,24,20,16,30,24,20,14,30,22,18,12}}, 438 {{30,30,30,24,20,16,30,24,20,14,30,22,18,12}}, 439 {{28,28,28,22,18,14,28,22,18,12,28,20,16,10}}, 440 {{28,28,28,22,18,14,28,22,18,12,28,20,16,10}}, 441 }, 442 443 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]= 444 { 445 //0_8_16,1-3_9-11_17-19, 446 // 4,5,6,7,12,13,14,15,20,21,22,23 447 {{28,28,28,26,22,18,28,24,20,16,20,16,16,16}}, 448 {{28,28,28,26,22,18,28,24,20,16,20,16,16,16}}, 449 {{28,28,28,28,24,20,28,28,24,20,22,20,20,20}}, 450 {{28,28,28,28,24,20,28,28,24,20,22,20,20,20}}, 451 {{28,28,28,24,20,16,28,24,20,16,18,16,16,16}}, 452 {{28,28,28,22,18,14,22,20,16,12,14,12,12,10}}, 453 {{28,28,28,22,18,14,22,20,16,12,14,12,12,10}}, 454 {{28,28,28,22,18,14,22,20,16,12,14,12,12,10}}, 455 }, 456 457 //static A_UINT8 ctlIndex_5G[OSPREY_NUM_CTLS_5G]= 458 459 { 460 //pCtlIndex[0] = 461 0x10, 462 //pCtlIndex[1] = 463 0x16, 464 //pCtlIndex[2] = 465 0x18, 466 //pCtlIndex[3] = 467 0x40, 468 //pCtlIndex[4] = 469 0x46, 470 //pCtlIndex[5] = 471 0x48, 472 //pCtlIndex[6] = 473 0x30, 474 //pCtlIndex[7] = 475 0x36, 476 //pCtlIndex[8] = 477 0x38 478 }, 479 480 // A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; 481 482 { 483 {/* Data[0].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 484 /* Data[0].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), 485 /* Data[0].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0), 486 /* Data[0].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), 487 /* Data[0].ctlEdges[4].bChannel*/FREQ2FBIN(5600, 0), 488 /* Data[0].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), 489 /* Data[0].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), 490 /* Data[0].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, 491 492 {/* Data[1].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 493 /* Data[1].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), 494 /* Data[1].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0), 495 /* Data[1].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), 496 /* Data[1].ctlEdges[4].bChannel*/FREQ2FBIN(5520, 0), 497 /* Data[1].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), 498 /* Data[1].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), 499 /* Data[1].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, 500 501 {/* Data[2].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), 502 /* Data[2].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0), 503 /* Data[2].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0), 504 /* Data[2].ctlEdges[3].bChannel*/FREQ2FBIN(5310, 0), 505 /* Data[2].ctlEdges[4].bChannel*/FREQ2FBIN(5510, 0), 506 /* Data[2].ctlEdges[5].bChannel*/FREQ2FBIN(5550, 0), 507 /* Data[2].ctlEdges[6].bChannel*/FREQ2FBIN(5670, 0), 508 /* Data[2].ctlEdges[7].bChannel*/FREQ2FBIN(5755, 0)}, 509 510 {/* Data[3].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 511 /* Data[3].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0), 512 /* Data[3].ctlEdges[2].bChannel*/FREQ2FBIN(5260, 0), 513 /* Data[3].ctlEdges[3].bChannel*/FREQ2FBIN(5320, 0), 514 /* Data[3].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0), 515 /* Data[3].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), 516 /* Data[3].ctlEdges[6].bChannel*/0xFF, 517 /* Data[3].ctlEdges[7].bChannel*/0xFF}, 518 519 {/* Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 520 /* Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), 521 /* Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(5500, 0), 522 /* Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(5700, 0), 523 /* Data[4].ctlEdges[4].bChannel*/0xFF, 524 /* Data[4].ctlEdges[5].bChannel*/0xFF, 525 /* Data[4].ctlEdges[6].bChannel*/0xFF, 526 /* Data[4].ctlEdges[7].bChannel*/0xFF}, 527 528 {/* Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), 529 /* Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(5270, 0), 530 /* Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(5310, 0), 531 /* Data[5].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0), 532 /* Data[5].ctlEdges[4].bChannel*/FREQ2FBIN(5590, 0), 533 /* Data[5].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0), 534 /* Data[5].ctlEdges[6].bChannel*/0xFF, 535 /* Data[5].ctlEdges[7].bChannel*/0xFF}, 536 537 {/* Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 538 /* Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0), 539 /* Data[6].ctlEdges[2].bChannel*/FREQ2FBIN(5220, 0), 540 /* Data[6].ctlEdges[3].bChannel*/FREQ2FBIN(5260, 0), 541 /* Data[6].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0), 542 /* Data[6].ctlEdges[5].bChannel*/FREQ2FBIN(5600, 0), 543 /* Data[6].ctlEdges[6].bChannel*/FREQ2FBIN(5700, 0), 544 /* Data[6].ctlEdges[7].bChannel*/FREQ2FBIN(5745, 0)}, 545 546 {/* Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 547 /* Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), 548 /* Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(5320, 0), 549 /* Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), 550 /* Data[7].ctlEdges[4].bChannel*/FREQ2FBIN(5560, 0), 551 /* Data[7].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), 552 /* Data[7].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), 553 /* Data[7].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, 554 555 {/* Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), 556 /* Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0), 557 /* Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0), 558 /* Data[8].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0), 559 /* Data[8].ctlEdges[4].bChannel*/FREQ2FBIN(5550, 0), 560 /* Data[8].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0), 561 /* Data[8].ctlEdges[6].bChannel*/FREQ2FBIN(5755, 0), 562 /* Data[8].ctlEdges[7].bChannel*/FREQ2FBIN(5795, 0)} 563 }, 564 565 //static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= 566 567 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 568 { 569 {{{1, 60}, 570 {1, 60}, 571 {1, 60}, 572 {1, 60}, 573 {1, 60}, 574 {1, 60}, 575 {1, 60}, 576 {0, 60}}}, 577 578 {{{1, 60}, 579 {1, 60}, 580 {1, 60}, 581 {1, 60}, 582 {1, 60}, 583 {1, 60}, 584 {1, 60}, 585 {0, 60}}}, 586 587 {{{0, 60}, 588 {1, 60}, 589 {0, 60}, 590 {1, 60}, 591 {1, 60}, 592 {1, 60}, 593 {1, 60}, 594 {1, 60}}}, 595 596 {{{0, 60}, 597 {1, 60}, 598 {1, 60}, 599 {0, 60}, 600 {1, 60}, 601 {0, 60}, 602 {0, 60}, 603 {0, 60}}}, 604 605 {{{1, 60}, 606 {1, 60}, 607 {1, 60}, 608 {0, 60}, 609 {0, 60}, 610 {0, 60}, 611 {0, 60}, 612 {0, 60}}}, 613 614 {{{1, 60}, 615 {1, 60}, 616 {1, 60}, 617 {1, 60}, 618 {1, 60}, 619 {0, 60}, 620 {0, 60}, 621 {0, 60}}}, 622 623 {{{1, 60}, 624 {1, 60}, 625 {1, 60}, 626 {1, 60}, 627 {1, 60}, 628 {1, 60}, 629 {1, 60}, 630 {1, 60}}}, 631 632 {{{1, 60}, 633 {1, 60}, 634 {0, 60}, 635 {1, 60}, 636 {1, 60}, 637 {1, 60}, 638 {1, 60}, 639 {0, 60}}}, 640 641 {{{1, 60}, 642 {0, 60}, 643 {1, 60}, 644 {1, 60}, 645 {1, 60}, 646 {1, 60}, 647 {0, 60}, 648 {1, 60}}}, 649 } 650 #else 651 { 652 {{{60, 1}, 653 {60, 1}, 654 {60, 1}, 655 {60, 1}, 656 {60, 1}, 657 {60, 1}, 658 {60, 1}, 659 {60, 0}}}, 660 661 {{{60, 1}, 662 {60, 1}, 663 {60, 1}, 664 {60, 1}, 665 {60, 1}, 666 {60, 1}, 667 {60, 1}, 668 {60, 0}}}, 669 670 {{{60, 0}, 671 {60, 1}, 672 {60, 0}, 673 {60, 1}, 674 {60, 1}, 675 {60, 1}, 676 {60, 1}, 677 {60, 1}}}, 678 679 {{{60, 0}, 680 {60, 1}, 681 {60, 1}, 682 {60, 0}, 683 {60, 1}, 684 {60, 0}, 685 {60, 0}, 686 {60, 0}}}, 687 688 {{{60, 1}, 689 {60, 1}, 690 {60, 1}, 691 {60, 0}, 692 {60, 0}, 693 {60, 0}, 694 {60, 0}, 695 {60, 0}}}, 696 697 {{{60, 1}, 698 {60, 1}, 699 {60, 1}, 700 {60, 1}, 701 {60, 1}, 702 {60, 0}, 703 {60, 0}, 704 {60, 0}}}, 705 706 {{{60, 1}, 707 {60, 1}, 708 {60, 1}, 709 {60, 1}, 710 {60, 1}, 711 {60, 1}, 712 {60, 1}, 713 {60, 1}}}, 714 715 {{{60, 1}, 716 {60, 1}, 717 {60, 0}, 718 {60, 1}, 719 {60, 1}, 720 {60, 1}, 721 {60, 1}, 722 {60, 0}}}, 723 724 {{{60, 1}, 725 {60, 0}, 726 {60, 1}, 727 {60, 1}, 728 {60, 1}, 729 {60, 1}, 730 {60, 0}, 731 {60, 1}}}, 732 } 733 #endif 734 }; 735 736 #endif 737 738