1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 31 * $FreeBSD: src/sys/amd64/include/specialreg.h,v 1.39 2007/05/31 11:26:44 des Exp $ 32 */ 33 34 #ifndef _CPU_SPECIALREG_H_ 35 #define _CPU_SPECIALREG_H_ 36 37 /* 38 * Bits in 386 special registers: 39 */ 40 #define CR0_PE 0x00000001 /* Protected mode Enable */ 41 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 42 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 43 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 44 #define CR0_PG 0x80000000 /* Paging enable */ 45 46 /* 47 * Bits in 486 special registers: 48 */ 49 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 50 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in all modes) */ 51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52 #define CR0_NW 0x20000000 /* Not Write-through */ 53 #define CR0_CD 0x40000000 /* Cache Disable */ 54 55 /* 56 * Bits in CR4 special register 57 */ 58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60 #define CR4_TSD 0x00000004 /* Time stamp disable */ 61 #define CR4_DE 0x00000008 /* Debugging extensions */ 62 #define CR4_PSE 0x00000010 /* Page size extensions */ 63 #define CR4_PAE 0x00000020 /* Physical address extension */ 64 #define CR4_MCE 0x00000040 /* Machine check enable */ 65 #define CR4_PGE 0x00000080 /* Page global enable */ 66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68 #define CR4_XMM 0x00000400 /* Enable SIMD/MMX2 to use except 16 */ 69 #define CR4_VMXE 0x00002000 /* Enables VMX - Intel specific */ 70 #define CR4_XSAVE 0x00040000 /* Enable XSave (for AVX Instructions)*/ 71 72 /* 73 * Bits in x86_64 special registers. EFER is 64 bits wide. 74 */ 75 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 76 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 77 #define EFER_LMA 0x000000400 /* Long mode active (R) */ 78 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 79 #define EFER_SVME 0x000001000 /* SVM Enable (R/W) */ 80 81 /* 82 * CPUID instruction features register 83 */ 84 #define CPUID_FPU 0x00000001 85 #define CPUID_VME 0x00000002 86 #define CPUID_DE 0x00000004 87 #define CPUID_PSE 0x00000008 88 #define CPUID_TSC 0x00000010 89 #define CPUID_MSR 0x00000020 90 #define CPUID_PAE 0x00000040 91 #define CPUID_MCE 0x00000080 92 #define CPUID_CX8 0x00000100 93 #define CPUID_APIC 0x00000200 94 #define CPUID_B10 0x00000400 95 #define CPUID_SEP 0x00000800 96 #define CPUID_MTRR 0x00001000 97 #define CPUID_PGE 0x00002000 98 #define CPUID_MCA 0x00004000 99 #define CPUID_CMOV 0x00008000 100 #define CPUID_PAT 0x00010000 101 #define CPUID_PSE36 0x00020000 102 #define CPUID_PSN 0x00040000 103 #define CPUID_CLFSH 0x00080000 104 #define CPUID_B20 0x00100000 105 #define CPUID_DS 0x00200000 106 #define CPUID_ACPI 0x00400000 107 #define CPUID_MMX 0x00800000 108 #define CPUID_FXSR 0x01000000 109 #define CPUID_SSE 0x02000000 110 #define CPUID_XMM 0x02000000 111 #define CPUID_SSE2 0x04000000 112 #define CPUID_SS 0x08000000 113 #define CPUID_HTT 0x10000000 114 #define CPUID_TM 0x20000000 115 #define CPUID_IA64 0x40000000 116 #define CPUID_PBE 0x80000000 117 118 #define CPUID2_SSE3 0x00000001 119 #define CPUID2_PCLMULQDQ 0x00000002 120 #define CPUID2_DTES64 0x00000004 121 #define CPUID2_MON 0x00000008 122 #define CPUID2_DS_CPL 0x00000010 123 #define CPUID2_VMX 0x00000020 124 #define CPUID2_SMX 0x00000040 125 #define CPUID2_EST 0x00000080 126 #define CPUID2_TM2 0x00000100 127 #define CPUID2_SSSE3 0x00000200 128 #define CPUID2_CNXTID 0x00000400 129 #define CPUID2_CX16 0x00002000 130 #define CPUID2_XTPR 0x00004000 131 #define CPUID2_PDCM 0x00008000 132 #define CPUID2_DCA 0x00040000 133 #define CPUID2_SSE41 0x00080000 134 #define CPUID2_SSE42 0x00100000 135 #define CPUID2_X2APIC 0x00200000 136 #define CPUID2_POPCNT 0x00800000 137 #define CPUID2_AESNI 0x02000000 /* AES Instruction Set */ 138 #define CPUID2_XSAVE 0x04000000 /* XSave supported by CPU */ 139 #define CPUID2_OSXSAVE 0x08000000 /* XSave and AVX supported by OS */ 140 #define CPUID2_AVX 0x10000000 /* AVX instruction set support */ 141 #define CPUID2_F16C 0x20000000 /* CVT16 instruction set support */ 142 #define CPUID2_RDRAND 0x40000000 /* RdRand. On chip random numbers */ 143 #define CPUID2_VMM 0x80000000 /* AMD 25481 2.34 page 11 */ 144 145 /*Bits related to the XFEATURE_ENABLED_MASK control register*/ 146 #define CPU_XFEATURE_X87 0x00000001 147 #define CPU_XFEATURE_SSE 0x00000002 148 #define CPU_XFEATURE_YMM 0x00000004 149 150 /* 151 * Important bits in the AMD extended cpuid flags 152 */ 153 #define AMDID_SYSCALL 0x00000800 154 #define AMDID_MP 0x00080000 155 #define AMDID_NX 0x00100000 156 #define AMDID_EXT_MMX 0x00400000 157 #define AMDID_FFXSR 0x01000000 158 #define AMDID_PAGE1GB 0x04000000 159 #define AMDID_RDTSCP 0x08000000 160 #define AMDID_LM 0x20000000 161 #define AMDID_EXT_3DNOW 0x40000000 162 #define AMDID_3DNOW 0x80000000 163 164 #define AMDID2_LAHF 0x00000001 165 #define AMDID2_CMP 0x00000002 166 #define AMDID2_SVM 0x00000004 167 #define AMDID2_EXT_APIC 0x00000008 168 #define AMDID2_CR8 0x00000010 169 #define AMDID2_ABM 0x00000020 170 #define AMDID2_SSE4A 0x00000040 171 #define AMDID2_MAS 0x00000080 172 #define AMDID2_PREFETCH 0x00000100 173 #define AMDID2_OSVW 0x00000200 174 #define AMDID2_IBS 0x00000400 175 #define AMDID2_SSE5 0x00000800 176 #define AMDID2_SKINIT 0x00001000 177 #define AMDID2_WDT 0x00002000 178 179 /* 180 * CPUID instruction 1 eax info 181 */ 182 #define CPUID_STEPPING 0x0000000f 183 #define CPUID_MODEL 0x000000f0 184 #define CPUID_FAMILY 0x00000f00 185 #define CPUID_EXT_MODEL 0x000f0000 186 #define CPUID_EXT_FAMILY 0x0ff00000 187 #define CPUID_TO_MODEL(id) \ 188 ((((id) & CPUID_MODEL) >> 4) | \ 189 (((id) & CPUID_EXT_MODEL) >> 12)) 190 #define CPUID_TO_FAMILY(id) \ 191 ((((id) & CPUID_FAMILY) >> 8) + \ 192 (((id) & CPUID_EXT_FAMILY) >> 20)) 193 194 /* 195 * CPUID instruction 1 ebx info 196 */ 197 #define CPUID_BRAND_INDEX 0x000000ff 198 #define CPUID_CLFUSH_SIZE 0x0000ff00 199 #define CPUID_HTT_CORES 0x00ff0000 200 #define CPUID_HTT_CORE_SHIFT 16 201 #define CPUID_LOCAL_APIC_ID 0xff000000 202 203 /* 204 * AMD extended function 8000_0008h ecx info 205 */ 206 #define AMDID_CMP_CORES 0x000000ff 207 #define AMDID_COREID_SIZE 0x0000f000 208 #define AMDID_COREID_SIZE_SHIFT 12 209 210 /* 211 * INTEL Deterministic Cache Parameters 212 * (Function 04h) 213 */ 214 #define FUNC_4_MAX_CORE_NO(eax) ((((eax) >> 26) & 0x3f)) 215 216 /* 217 * INTEL x2APIC Features / Processor topology 218 * (Function 0Bh) 219 */ 220 #define FUNC_B_THREAD_LEVEL 0 221 222 #define FUNC_B_INVALID_TYPE 0 223 #define FUNC_B_THREAD_TYPE 1 224 #define FUNC_B_CORE_TYPE 2 225 226 #define FUNC_B_TYPE(ecx) (((ecx) >> 8) & 0xff) 227 #define FUNC_B_BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) 228 #define FUNC_B_LEVEL_MAX_SIBLINGS(ebx) ((ebx) & 0xffff) 229 230 /* 231 * Structured Extended Features 232 */ 233 #define CPUID_STDEXT_FSGSBASE 0x00000001 234 #define CPUID_STDEXT_TSC_ADJUST 0x00000002 235 #define CPUID_STDEXT_BMI1 0x00000008 236 #define CPUID_STDEXT_HLE 0x00000010 237 #define CPUID_STDEXT_AVX2 0x00000020 238 #define CPUID_STDEXT_SMEP 0x00000080 239 #define CPUID_STDEXT_BMI2 0x00000100 240 #define CPUID_STDEXT_ENH_MOVSB 0x00000200 241 #define CPUID_STDEXT_RTM 0x00000800 242 #define CPUID_STDEXT_INVPCID 0x00000400 243 #define CPUID_STDEXT_RDSEED 0x00040000 244 #define CPUID_STDEXT_ADX 0x00080000 245 #define CPUID_STDEXT_SMAP 0x00100000 246 247 /* 248 * CPUID manufacturers identifiers 249 */ 250 #define AMD_VENDOR_ID "AuthenticAMD" 251 #define CENTAUR_VENDOR_ID "CentaurHauls" 252 #define INTEL_VENDOR_ID "GenuineIntel" 253 254 /* 255 * Model-specific registers for the i386 family 256 */ 257 #define MSR_P5_MC_ADDR 0x000 258 #define MSR_P5_MC_TYPE 0x001 259 #define MSR_TSC 0x010 260 #define MSR_P5_CESR 0x011 261 #define MSR_P5_CTR0 0x012 262 #define MSR_P5_CTR1 0x013 263 #define MSR_IA32_PLATFORM_ID 0x017 264 #define MSR_APICBASE 0x01b 265 #define MSR_EBL_CR_POWERON 0x02a 266 #define MSR_TEST_CTL 0x033 267 #define MSR_BIOS_UPDT_TRIG 0x079 268 #define MSR_BBL_CR_D0 0x088 269 #define MSR_BBL_CR_D1 0x089 270 #define MSR_BBL_CR_D2 0x08a 271 #define MSR_BIOS_SIGN 0x08b 272 #define MSR_PERFCTR0 0x0c1 273 #define MSR_PERFCTR1 0x0c2 274 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 275 #define MSR_MTRRcap 0x0fe 276 #define MSR_BBL_CR_ADDR 0x116 277 #define MSR_BBL_CR_DECC 0x118 278 #define MSR_BBL_CR_CTL 0x119 279 #define MSR_BBL_CR_TRIG 0x11a 280 #define MSR_BBL_CR_BUSY 0x11b 281 #define MSR_BBL_CR_CTL3 0x11e 282 #define MSR_SYSENTER_CS_MSR 0x174 283 #define MSR_SYSENTER_ESP_MSR 0x175 284 #define MSR_SYSENTER_EIP_MSR 0x176 285 #define MSR_MCG_CAP 0x179 286 #define MSR_MCG_STATUS 0x17a 287 #define MSR_MCG_CTL 0x17b 288 #define MSR_EVNTSEL0 0x186 289 #define MSR_EVNTSEL1 0x187 290 #define MSR_THERM_CONTROL 0x19a 291 #define MSR_THERM_INTERRUPT 0x19b 292 #define MSR_THERM_STATUS 0x19c 293 #define MSR_IA32_MISC_ENABLE 0x1a0 294 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 295 #define MSR_DEBUGCTLMSR 0x1d9 296 #define MSR_LASTBRANCHFROMIP 0x1db 297 #define MSR_LASTBRANCHTOIP 0x1dc 298 #define MSR_LASTINTFROMIP 0x1dd 299 #define MSR_LASTINTTOIP 0x1de 300 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 301 #define MSR_MTRRVarBase 0x200 302 #define MSR_MTRR64kBase 0x250 303 #define MSR_MTRR16kBase 0x258 304 #define MSR_MTRR4kBase 0x268 305 #define MSR_PAT 0x277 306 #define MSR_MTRRdefType 0x2ff 307 #define MSR_MC0_CTL 0x400 308 #define MSR_MC0_STATUS 0x401 309 #define MSR_MC0_ADDR 0x402 310 #define MSR_MC0_MISC 0x403 311 #define MSR_MC1_CTL 0x404 312 #define MSR_MC1_STATUS 0x405 313 #define MSR_MC1_ADDR 0x406 314 #define MSR_MC1_MISC 0x407 315 #define MSR_MC2_CTL 0x408 316 #define MSR_MC2_STATUS 0x409 317 #define MSR_MC2_ADDR 0x40a 318 #define MSR_MC2_MISC 0x40b 319 #define MSR_MC3_CTL 0x40c 320 #define MSR_MC3_STATUS 0x40d 321 #define MSR_MC3_ADDR 0x40e 322 #define MSR_MC3_MISC 0x40f 323 #define MSR_MC4_CTL 0x410 324 #define MSR_MC4_STATUS 0x411 325 #define MSR_MC4_ADDR 0x412 326 #define MSR_MC4_MISC 0x413 327 328 /* 329 * Constants related to MSR's. 330 */ 331 #define APICBASE_RESERVED 0x000006ff 332 #define APICBASE_BSP 0x00000100 333 #define APICBASE_ENABLED 0x00000800 334 #define APICBASE_ADDRESS 0xfffff000 335 336 /* 337 * PAT modes. 338 */ 339 #define PAT_UNCACHEABLE 0x00 340 #define PAT_WRITE_COMBINING 0x01 341 #define PAT_WRITE_THROUGH 0x04 342 #define PAT_WRITE_PROTECTED 0x05 343 #define PAT_WRITE_BACK 0x06 344 #define PAT_UNCACHED 0x07 345 #define PAT_VALUE(i, m) ((long)(m) << (8 * (i))) 346 #define PAT_MASK(i) PAT_VALUE(i, 0xff) 347 348 /* 349 * Constants related to MTRRs 350 */ 351 #define MTRR_UNCACHEABLE 0x00 352 #define MTRR_WRITE_COMBINING 0x01 353 #define MTRR_WRITE_THROUGH 0x04 354 #define MTRR_WRITE_PROTECTED 0x05 355 #define MTRR_WRITE_BACK 0x06 356 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 357 #define MTRR_N16K 16 358 #define MTRR_N4K 64 359 #define MTRR_CAP_WC 0x0000000000000400UL 360 #define MTRR_CAP_FIXED 0x0000000000000100UL 361 #define MTRR_CAP_VCNT 0x00000000000000ffUL 362 #define MTRR_DEF_ENABLE 0x0000000000000800UL 363 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400UL 364 #define MTRR_DEF_TYPE 0x00000000000000ffUL 365 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000UL 366 #define MTRR_PHYSBASE_TYPE 0x00000000000000ffUL 367 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000UL 368 #define MTRR_PHYSMASK_VALID 0x0000000000000800UL 369 370 /* Performance Control Register (5x86 only). */ 371 #define PCR0 0x20 372 #define PCR0_RSTK 0x01 /* Enables return stack */ 373 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 374 #define PCR0_LOOP 0x04 /* Enables loop */ 375 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 376 serialize pipe. */ 377 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 378 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 379 #define PCR0_LSSER 0x80 /* Disable reorder */ 380 381 /* Device Identification Registers */ 382 #define DIR0 0xfe 383 #define DIR1 0xff 384 385 /* 386 * Machine Check register constants. 387 */ 388 #define MCG_CAP_COUNT 0x000000ff 389 #define MCG_CAP_CTL_P 0x00000100 390 #define MCG_CAP_EXT_P 0x00000200 391 #define MCG_CAP_TES_P 0x00000800 392 #define MCG_CAP_EXT_CNT 0x00ff0000 393 #define MCG_STATUS_RIPV 0x00000001 394 #define MCG_STATUS_EIPV 0x00000002 395 #define MCG_STATUS_MCIP 0x00000004 396 #define MCG_CTL_ENABLE 0xffffffffffffffffUL 397 #define MCG_CTL_DISABLE 0x0000000000000000UL 398 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 399 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 400 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 401 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 402 #define MC_STATUS_MCA_ERROR 0x000000000000ffffUL 403 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000UL 404 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000UL 405 #define MC_STATUS_PCC 0x0200000000000000UL 406 #define MC_STATUS_ADDRV 0x0400000000000000UL 407 #define MC_STATUS_MISCV 0x0800000000000000UL 408 #define MC_STATUS_EN 0x1000000000000000UL 409 #define MC_STATUS_UC 0x2000000000000000UL 410 #define MC_STATUS_OVER 0x4000000000000000UL 411 #define MC_STATUS_VAL 0x8000000000000000UL 412 413 /* 414 * The following four 3-byte registers control the non-cacheable regions. 415 * These registers must be written as three separate bytes. 416 * 417 * NCRx+0: A31-A24 of starting address 418 * NCRx+1: A23-A16 of starting address 419 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 420 * 421 * The non-cacheable region's starting address must be aligned to the 422 * size indicated by the NCR_SIZE_xx field. 423 */ 424 #define NCR1 0xc4 425 #define NCR2 0xc7 426 #define NCR3 0xca 427 #define NCR4 0xcd 428 429 #define NCR_SIZE_0K 0 430 #define NCR_SIZE_4K 1 431 #define NCR_SIZE_8K 2 432 #define NCR_SIZE_16K 3 433 #define NCR_SIZE_32K 4 434 #define NCR_SIZE_64K 5 435 #define NCR_SIZE_128K 6 436 #define NCR_SIZE_256K 7 437 #define NCR_SIZE_512K 8 438 #define NCR_SIZE_1M 9 439 #define NCR_SIZE_2M 10 440 #define NCR_SIZE_4M 11 441 #define NCR_SIZE_8M 12 442 #define NCR_SIZE_16M 13 443 #define NCR_SIZE_32M 14 444 #define NCR_SIZE_4G 15 445 446 /* 447 * The address region registers are used to specify the location and 448 * size for the eight address regions. 449 * 450 * ARRx + 0: A31-A24 of start address 451 * ARRx + 1: A23-A16 of start address 452 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 453 */ 454 #define ARR0 0xc4 455 #define ARR1 0xc7 456 #define ARR2 0xca 457 #define ARR3 0xcd 458 #define ARR4 0xd0 459 #define ARR5 0xd3 460 #define ARR6 0xd6 461 #define ARR7 0xd9 462 463 #define ARR_SIZE_0K 0 464 #define ARR_SIZE_4K 1 465 #define ARR_SIZE_8K 2 466 #define ARR_SIZE_16K 3 467 #define ARR_SIZE_32K 4 468 #define ARR_SIZE_64K 5 469 #define ARR_SIZE_128K 6 470 #define ARR_SIZE_256K 7 471 #define ARR_SIZE_512K 8 472 #define ARR_SIZE_1M 9 473 #define ARR_SIZE_2M 10 474 #define ARR_SIZE_4M 11 475 #define ARR_SIZE_8M 12 476 #define ARR_SIZE_16M 13 477 #define ARR_SIZE_32M 14 478 #define ARR_SIZE_4G 15 479 480 /* 481 * The region control registers specify the attributes associated with 482 * the ARRx addres regions. 483 */ 484 #define RCR0 0xdc 485 #define RCR1 0xdd 486 #define RCR2 0xde 487 #define RCR3 0xdf 488 #define RCR4 0xe0 489 #define RCR5 0xe1 490 #define RCR6 0xe2 491 #define RCR7 0xe3 492 493 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 494 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 495 #define RCR_WWO 0x02 /* Weak write ordering. */ 496 #define RCR_WL 0x04 /* Weak locking. */ 497 #define RCR_WG 0x08 /* Write gathering. */ 498 #define RCR_WT 0x10 /* Write-through. */ 499 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 500 501 /* AMD Write Allocate Top-Of-Memory and Control Register */ 502 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 503 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 504 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 505 506 /* x86_64 MSR's */ 507 #define MSR_EFER 0xc0000080 /* extended features */ 508 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 509 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 510 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 511 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 512 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 513 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 514 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 515 #define MSR_PERFEVSEL0 0xc0010000 516 #define MSR_PERFEVSEL1 0xc0010001 517 #define MSR_PERFEVSEL2 0xc0010002 518 #define MSR_PERFEVSEL3 0xc0010003 519 #undef MSR_PERFCTR0 520 #undef MSR_PERFCTR1 521 #define MSR_PERFCTR0 0xc0010004 522 #define MSR_PERFCTR1 0xc0010005 523 #define MSR_PERFCTR2 0xc0010006 524 #define MSR_PERFCTR3 0xc0010007 525 #define MSR_SYSCFG 0xc0010010 526 #define MSR_IORRBASE0 0xc0010016 527 #define MSR_IORRMASK0 0xc0010017 528 #define MSR_IORRBASE1 0xc0010018 529 #define MSR_IORRMASK1 0xc0010019 530 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 531 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 532 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 533 534 /* AMD MSRs */ 535 #define MSR_AMD_DE_CFG 0xc0011029 536 537 /* AMD SVM MSRs */ 538 #define MSR_AMD_VM_CR 0xc0010114 539 #define MSR_AMD_VM_HSAVE_PA 0xc0010117 540 541 /* AMD MSR_AMD_VM_CR fields */ 542 #define MSR_AMD_VM_CR_SVMDIS 0x00000010 /* SVM Disabled */ 543 544 /* VIA ACE crypto featureset: for via_feature_rng */ 545 #define VIA_HAS_RNG 1 /* cpu has RNG */ 546 547 /* VIA ACE crypto featureset: for via_feature_xcrypt */ 548 #define VIA_HAS_AES 1 /* cpu has AES */ 549 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 550 #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 551 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 552 553 /* Centaur Extended Feature flags */ 554 #define VIA_CPUID_HAS_RNG 0x000004 555 #define VIA_CPUID_DO_RNG 0x000008 556 #define VIA_CPUID_HAS_ACE 0x000040 557 #define VIA_CPUID_DO_ACE 0x000080 558 #define VIA_CPUID_HAS_ACE2 0x000100 559 #define VIA_CPUID_DO_ACE2 0x000200 560 #define VIA_CPUID_HAS_PHE 0x000400 561 #define VIA_CPUID_DO_PHE 0x000800 562 #define VIA_CPUID_HAS_PMM 0x001000 563 #define VIA_CPUID_DO_PMM 0x002000 564 565 #endif /* !_CPU_SPECIALREG_H_ */ 566