1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 31 * $FreeBSD: src/sys/amd64/include/specialreg.h,v 1.39 2007/05/31 11:26:44 des Exp $ 32 */ 33 34 #ifndef _CPU_SPECIALREG_H_ 35 #define _CPU_SPECIALREG_H_ 36 37 /* 38 * Bits in 386 special registers: 39 */ 40 #define CR0_PE 0x00000001 /* Protected mode Enable */ 41 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 42 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 43 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 44 #define CR0_PG 0x80000000 /* Paging enable */ 45 46 /* 47 * Bits in 486 special registers: 48 */ 49 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 50 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in all modes) */ 51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52 #define CR0_NW 0x20000000 /* Not Write-through */ 53 #define CR0_CD 0x40000000 /* Cache Disable */ 54 55 /* 56 * Bits in CR4 special register 57 */ 58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60 #define CR4_TSD 0x00000004 /* Time stamp disable */ 61 #define CR4_DE 0x00000008 /* Debugging extensions */ 62 #define CR4_PSE 0x00000010 /* Page size extensions */ 63 #define CR4_PAE 0x00000020 /* Physical address extension */ 64 #define CR4_MCE 0x00000040 /* Machine check enable */ 65 #define CR4_PGE 0x00000080 /* Page global enable */ 66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68 #define CR4_XMM 0x00000400 /* Enable SIMD/MMX2 to use except 16 */ 69 #define CR4_VMXE 0x00002000 /* Enables VMX - Intel specific */ 70 #define CR4_XSAVE 0x00040000 /* Enable XSave (for AVX Instructions)*/ 71 72 /* 73 * Bits in x86_64 special registers. EFER is 64 bits wide. 74 */ 75 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 76 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 77 #define EFER_LMA 0x000000400 /* Long mode active (R) */ 78 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 79 #define EFER_SVME 0x000001000 /* SVM Enable (R/W) */ 80 81 /* 82 * CPUID instruction features register 83 */ 84 #define CPUID_FPU 0x00000001 85 #define CPUID_VME 0x00000002 86 #define CPUID_DE 0x00000004 87 #define CPUID_PSE 0x00000008 88 #define CPUID_TSC 0x00000010 89 #define CPUID_MSR 0x00000020 90 #define CPUID_PAE 0x00000040 91 #define CPUID_MCE 0x00000080 92 #define CPUID_CX8 0x00000100 93 #define CPUID_APIC 0x00000200 94 #define CPUID_B10 0x00000400 95 #define CPUID_SEP 0x00000800 96 #define CPUID_MTRR 0x00001000 97 #define CPUID_PGE 0x00002000 98 #define CPUID_MCA 0x00004000 99 #define CPUID_CMOV 0x00008000 100 #define CPUID_PAT 0x00010000 101 #define CPUID_PSE36 0x00020000 102 #define CPUID_PSN 0x00040000 103 #define CPUID_CLFSH 0x00080000 104 #define CPUID_B20 0x00100000 105 #define CPUID_DS 0x00200000 106 #define CPUID_ACPI 0x00400000 107 #define CPUID_MMX 0x00800000 108 #define CPUID_FXSR 0x01000000 109 #define CPUID_SSE 0x02000000 110 #define CPUID_XMM 0x02000000 111 #define CPUID_SSE2 0x04000000 112 #define CPUID_SS 0x08000000 113 #define CPUID_HTT 0x10000000 114 #define CPUID_TM 0x20000000 115 #define CPUID_IA64 0x40000000 116 #define CPUID_PBE 0x80000000 117 118 #define CPUID2_SSE3 0x00000001 119 #define CPUID2_PCLMULQDQ 0x00000002 120 #define CPUID2_DTES64 0x00000004 121 #define CPUID2_MON 0x00000008 122 #define CPUID2_DS_CPL 0x00000010 123 #define CPUID2_VMX 0x00000020 124 #define CPUID2_SMX 0x00000040 125 #define CPUID2_EST 0x00000080 126 #define CPUID2_TM2 0x00000100 127 #define CPUID2_SSSE3 0x00000200 128 #define CPUID2_CNXTID 0x00000400 129 #define CPUID2_CX16 0x00002000 130 #define CPUID2_XTPR 0x00004000 131 #define CPUID2_PDCM 0x00008000 132 #define CPUID2_DCA 0x00040000 133 #define CPUID2_SSE41 0x00080000 134 #define CPUID2_SSE42 0x00100000 135 #define CPUID2_X2APIC 0x00200000 136 #define CPUID2_POPCNT 0x00800000 137 #define CPUID2_TSCDLT 0x01000000 /* LAPIC TSC-Deadline Mode support */ 138 #define CPUID2_AESNI 0x02000000 /* AES Instruction Set */ 139 #define CPUID2_XSAVE 0x04000000 /* XSave supported by CPU */ 140 #define CPUID2_OSXSAVE 0x08000000 /* XSave and AVX supported by OS */ 141 #define CPUID2_AVX 0x10000000 /* AVX instruction set support */ 142 #define CPUID2_F16C 0x20000000 /* CVT16 instruction set support */ 143 #define CPUID2_RDRAND 0x40000000 /* RdRand. On chip random numbers */ 144 #define CPUID2_VMM 0x80000000 /* AMD 25481 2.34 page 11 */ 145 146 /*Bits related to the XFEATURE_ENABLED_MASK control register*/ 147 #define CPU_XFEATURE_X87 0x00000001 148 #define CPU_XFEATURE_SSE 0x00000002 149 #define CPU_XFEATURE_YMM 0x00000004 150 151 /* 152 * Important bits in the AMD extended cpuid flags 153 */ 154 #define AMDID_SYSCALL 0x00000800 155 #define AMDID_MP 0x00080000 156 #define AMDID_NX 0x00100000 157 #define AMDID_EXT_MMX 0x00400000 158 #define AMDID_FFXSR 0x01000000 159 #define AMDID_PAGE1GB 0x04000000 160 #define AMDID_RDTSCP 0x08000000 161 #define AMDID_LM 0x20000000 162 #define AMDID_EXT_3DNOW 0x40000000 163 #define AMDID_3DNOW 0x80000000 164 165 #define AMDID2_LAHF 0x00000001 166 #define AMDID2_CMP 0x00000002 167 #define AMDID2_SVM 0x00000004 168 #define AMDID2_EXT_APIC 0x00000008 169 #define AMDID2_CR8 0x00000010 170 #define AMDID2_ABM 0x00000020 171 #define AMDID2_SSE4A 0x00000040 172 #define AMDID2_MAS 0x00000080 173 #define AMDID2_PREFETCH 0x00000100 174 #define AMDID2_OSVW 0x00000200 175 #define AMDID2_IBS 0x00000400 176 #define AMDID2_SSE5 0x00000800 177 #define AMDID2_SKINIT 0x00001000 178 #define AMDID2_WDT 0x00002000 179 #define AMDID2_TOPOEXT 0x00400000 180 181 /* 182 * CPUID instruction 1 eax info 183 */ 184 #define CPUID_STEPPING 0x0000000f 185 #define CPUID_MODEL 0x000000f0 186 #define CPUID_FAMILY 0x00000f00 187 #define CPUID_EXT_MODEL 0x000f0000 188 #define CPUID_EXT_FAMILY 0x0ff00000 189 #define CPUID_TO_MODEL(id) \ 190 ((((id) & CPUID_MODEL) >> 4) | \ 191 (((id) & CPUID_EXT_MODEL) >> 12)) 192 #define CPUID_TO_FAMILY(id) \ 193 ((((id) & CPUID_FAMILY) >> 8) + \ 194 (((id) & CPUID_EXT_FAMILY) >> 20)) 195 196 /* 197 * CPUID instruction 1 ebx info 198 */ 199 #define CPUID_BRAND_INDEX 0x000000ff 200 #define CPUID_CLFUSH_SIZE 0x0000ff00 201 #define CPUID_HTT_CORES 0x00ff0000 202 #define CPUID_HTT_CORE_SHIFT 16 203 #define CPUID_LOCAL_APIC_ID 0xff000000 204 205 /* 206 * AMD extended function 8000_0007h edx info 207 */ 208 #define AMDPM_TS 0x00000001 209 #define AMDPM_FID 0x00000002 210 #define AMDPM_VID 0x00000004 211 #define AMDPM_TTP 0x00000008 212 #define AMDPM_TM 0x00000010 213 #define AMDPM_STC 0x00000020 214 #define AMDPM_100MHZ_STEPS 0x00000040 215 #define AMDPM_HW_PSTATE 0x00000080 216 #define AMDPM_TSC_INVARIANT 0x00000100 217 #define AMDPM_CPB 0x00000200 218 219 /* 220 * AMD extended function 8000_0008h ecx info 221 */ 222 #define AMDID_CMP_CORES 0x000000ff 223 #define AMDID_COREID_SIZE 0x0000f000 224 #define AMDID_COREID_SIZE_SHIFT 12 225 226 /* 227 * INTEL Deterministic Cache Parameters 228 * (Function 04h) 229 */ 230 #define FUNC_4_MAX_CORE_NO(eax) ((((eax) >> 26) & 0x3f)) 231 232 /* 233 * INTEL x2APIC Features / Processor topology 234 * (Function 0Bh) 235 */ 236 #define FUNC_B_THREAD_LEVEL 0 237 238 #define FUNC_B_INVALID_TYPE 0 239 #define FUNC_B_THREAD_TYPE 1 240 #define FUNC_B_CORE_TYPE 2 241 242 #define FUNC_B_TYPE(ecx) (((ecx) >> 8) & 0xff) 243 #define FUNC_B_BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) 244 #define FUNC_B_LEVEL_MAX_SIBLINGS(ebx) ((ebx) & 0xffff) 245 246 /* 247 * Structured Extended Features 248 */ 249 /* EBX */ 250 #define CPUID_STDEXT_FSGSBASE 0x00000001 251 #define CPUID_STDEXT_TSC_ADJUST 0x00000002 252 #define CPUID_STDEXT_BMI1 0x00000008 253 #define CPUID_STDEXT_HLE 0x00000010 254 #define CPUID_STDEXT_AVX2 0x00000020 255 #define CPUID_STDEXT_SMEP 0x00000080 256 #define CPUID_STDEXT_BMI2 0x00000100 257 #define CPUID_STDEXT_ENH_MOVSB 0x00000200 258 #define CPUID_STDEXT_RTM 0x00000800 259 #define CPUID_STDEXT_INVPCID 0x00000400 260 #define CPUID_STDEXT_RDSEED 0x00040000 261 #define CPUID_STDEXT_ADX 0x00080000 262 #define CPUID_STDEXT_SMAP 0x00100000 263 264 /* ECX */ 265 #define CPUID_STDEXT2_RDPID 0x00400000 266 267 /* 268 * Thermal and PM Features 269 */ 270 #define CPUID_THERMAL_SENSOR 0x00000001 271 #define CPUID_THERMAL_TURBO 0x00000002 272 #define CPUID_THERMAL_ARAT 0x00000004 273 #define CPUID_THERMAL_PLN 0x00000010 274 #define CPUID_THERMAL_ECMD 0x00000020 275 #define CPUID_THERMAL_PTM 0x00000040 276 #define CPUID_THERMAL_HWP 0x00000080 /* Hardware P-states */ 277 278 #define CPUID_THERMAL2_SETBH 0x00000008 279 280 /* 281 * MONITOR/MWAIT 282 */ 283 #define CPUID_MWAIT_EXT 0x00000001 284 #define CPUID_MWAIT_INTBRK 0x00000002 285 #define CPUID_MWAIT_CX_SUBCNT(emu, i) (((emu) >> ((i) * 4)) & 0xf) 286 287 /* MWAIT EAX to Cx and its sub state */ 288 #define MWAIT_EAX_TO_CX(x) ((((x) >> 4) + 1) & 0xf) 289 #define MWAIT_EAX_TO_CX_SUB(x) ((x) & 0xf) 290 291 /* MWAIT EAX hint and ECX extension */ 292 #define MWAIT_EAX_HINT(cx, sub) \ 293 (((((uint32_t)(cx) - 1) & 0xf) << 4) | ((sub) & 0xf)) 294 #define MWAIT_ECX_INTBRK 0x1 295 296 /* 297 * CPUID manufacturers identifiers 298 */ 299 #define AMD_VENDOR_ID "AuthenticAMD" 300 #define CENTAUR_VENDOR_ID "CentaurHauls" 301 #define INTEL_VENDOR_ID "GenuineIntel" 302 303 /* 304 * Model-specific registers for the i386 family 305 */ 306 #define MSR_P5_MC_ADDR 0x000 307 #define MSR_P5_MC_TYPE 0x001 308 #define MSR_TSC 0x010 309 #define MSR_P5_CESR 0x011 310 #define MSR_P5_CTR0 0x012 311 #define MSR_P5_CTR1 0x013 312 #define MSR_IA32_PLATFORM_ID 0x017 313 #define MSR_APICBASE 0x01b 314 #define MSR_EBL_CR_POWERON 0x02a 315 #define MSR_TEST_CTL 0x033 316 #define MSR_SPEC_CTRL 0x048 /* IBRS Spectre mitigation */ 317 #define MSR_PRED_CMD 0x049 /* IBPB Spectre mitigation */ 318 #define MSR_BIOS_UPDT_TRIG 0x079 319 #define MSR_BBL_CR_D0 0x088 320 #define MSR_BBL_CR_D1 0x089 321 #define MSR_BBL_CR_D2 0x08a 322 #define MSR_BIOS_SIGN 0x08b 323 #define MSR_PERFCTR0 0x0c1 324 #define MSR_PERFCTR1 0x0c2 325 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 326 #define MSR_MTRRcap 0x0fe 327 #define MSR_BBL_CR_ADDR 0x116 328 #define MSR_BBL_CR_DECC 0x118 329 #define MSR_BBL_CR_CTL 0x119 330 #define MSR_BBL_CR_TRIG 0x11a 331 #define MSR_BBL_CR_BUSY 0x11b 332 #define MSR_BBL_CR_CTL3 0x11e 333 #define MSR_SYSENTER_CS_MSR 0x174 334 #define MSR_SYSENTER_ESP_MSR 0x175 335 #define MSR_SYSENTER_EIP_MSR 0x176 336 #define MSR_MCG_CAP 0x179 337 #define MSR_MCG_STATUS 0x17a 338 #define MSR_MCG_CTL 0x17b 339 #define MSR_EVNTSEL0 0x186 340 #define MSR_EVNTSEL1 0x187 341 #define MSR_THERM_CONTROL 0x19a 342 #define MSR_THERM_INTERRUPT 0x19b 343 #define MSR_THERM_STATUS 0x19c 344 #define MSR_IA32_MISC_ENABLE 0x1a0 345 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 346 #define MSR_PKG_THERM_STATUS 0x1b1 347 #define MSR_PKG_THERM_INTR 0x1b2 348 #define MSR_DEBUGCTLMSR 0x1d9 349 #define MSR_LASTBRANCHFROMIP 0x1db 350 #define MSR_LASTBRANCHTOIP 0x1dc 351 #define MSR_LASTINTFROMIP 0x1dd 352 #define MSR_LASTINTTOIP 0x1de 353 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 354 #define MSR_MTRRVarBase 0x200 355 #define MSR_MTRR64kBase 0x250 356 #define MSR_MTRR16kBase 0x258 357 #define MSR_MTRR4kBase 0x268 358 #define MSR_PAT 0x277 359 #define MSR_MTRRdefType 0x2ff 360 #define MSR_MC0_CTL 0x400 361 #define MSR_MC0_STATUS 0x401 362 #define MSR_MC0_ADDR 0x402 363 #define MSR_MC0_MISC 0x403 364 #define MSR_MC1_CTL 0x404 365 #define MSR_MC1_STATUS 0x405 366 #define MSR_MC1_ADDR 0x406 367 #define MSR_MC1_MISC 0x407 368 #define MSR_MC2_CTL 0x408 369 #define MSR_MC2_STATUS 0x409 370 #define MSR_MC2_ADDR 0x40a 371 #define MSR_MC2_MISC 0x40b 372 #define MSR_MC3_CTL 0x40c 373 #define MSR_MC3_STATUS 0x40d 374 #define MSR_MC3_ADDR 0x40e 375 #define MSR_MC3_MISC 0x40f 376 #define MSR_MC4_CTL 0x410 377 #define MSR_MC4_STATUS 0x411 378 #define MSR_MC4_ADDR 0x412 379 #define MSR_MC4_MISC 0x413 380 #define MSR_RAPL_POWER_UNIT 0x606 381 #define MSR_PKG_ENERGY_STATUS 0x611 382 #define MSR_DRAM_ENERGY_STATUS 0x619 383 #define MSR_PP0_ENERGY_STATUS 0x639 384 #define MSR_PP1_ENERGY_STATUS 0x641 385 #define MSR_PLATFORM_ENERGY_COUNTER 0x64d /* Skylake and later */ 386 387 /* 388 * Constants related to MSR's. 389 */ 390 #define APICBASE_RESERVED 0x000006ff 391 #define APICBASE_BSP 0x00000100 392 #define APICBASE_X2APIC 0x00000400 393 #define APICBASE_ENABLED 0x00000800 394 #define APICBASE_ADDRESS 0xfffff000 395 396 /* 397 * IBRS and IBPB Spectre mitigation 398 * 399 * Intel: Either CPUID_80000008_I1_IBPB_SUPPORT or CPUID_7_0_I3_SPEC_CTRL 400 * indicates IBPB support. However, note that MSR_PRED_CMD is 401 * a command register that may only be written, not read. 402 * 403 * IBPB: (barrier) 404 * $1 is written to MSR_PRED_CMD unconditionally, writing 0 405 * has no effect. 406 * 407 * IBRS and STIBP 408 * Serves as barrier and mode, set on entry to kernel and clear 409 * on exit. Be sure to clear before going idle (else hyperthread 410 * performance will drop). 411 */ 412 413 #define CPUID_7_0_I3_SPEC_CTRL 0x04000000 /* in EDX (index 3) */ 414 #define CPUID_7_0_I3_STIBP 0x08000000 /* in EDX (index 3) */ 415 416 #define SPEC_CTRL_IBRS 0x00000001 417 #define SPEC_CTRL_STIBP 0x00000002 418 #define SPEC_CTRL_DUMMY1 0x00010000 /* ficticious */ 419 #define SPEC_CTRL_DUMMY2 0x00020000 /* ficticious */ 420 #define SPEC_CTRL_DUMMY3 0x00040000 /* ficticious */ 421 #define SPEC_CTRL_DUMMY4 0x00080000 /* ficticious */ 422 #define SPEC_CTRL_DUMMY5 0x00100000 /* ficticious */ 423 #define SPEC_CTRL_DUMMY6 0x00200000 /* ficticious */ 424 425 /* 426 * In EBX (index 1) 427 */ 428 #define CPUID_INTEL_80000008_I1_IBPB_SUPPORT 0x00001000 429 430 #define CPUID_AMD_80000008_I1_IBPB_SUPPORT 0x00001000 431 #define CPUID_AMD_80000008_I1_IBRS_SUPPORT 0x00004000 432 #define CPUID_AMD_80000008_I1_STIBP_SUPPORT 0x00008000 433 434 #define CPUID_AMD_80000008_I1_IBRS_AUTO 0x00010000 435 #define CPUID_AMD_80000008_I1_STIBP_AUTO 0x00020000 436 #define CPUID_AMD_80000008_I1_IBRS_REQUESTED 0x00040000 437 438 /* 439 * PAT modes. 440 */ 441 #define PAT_UNCACHEABLE 0x00 442 #define PAT_WRITE_COMBINING 0x01 443 #define PAT_WRITE_THROUGH 0x04 444 #define PAT_WRITE_PROTECTED 0x05 445 #define PAT_WRITE_BACK 0x06 446 #define PAT_UNCACHED 0x07 447 #define PAT_VALUE(i, m) ((long)(m) << (8 * (i))) 448 #define PAT_MASK(i) PAT_VALUE(i, 0xff) 449 450 /* 451 * Constants related to MTRRs 452 */ 453 #define MTRR_UNCACHEABLE 0x00 454 #define MTRR_WRITE_COMBINING 0x01 455 #define MTRR_WRITE_THROUGH 0x04 456 #define MTRR_WRITE_PROTECTED 0x05 457 #define MTRR_WRITE_BACK 0x06 458 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 459 #define MTRR_N16K 16 460 #define MTRR_N4K 64 461 #define MTRR_CAP_WC 0x0000000000000400UL 462 #define MTRR_CAP_FIXED 0x0000000000000100UL 463 #define MTRR_CAP_VCNT 0x00000000000000ffUL 464 #define MTRR_DEF_ENABLE 0x0000000000000800UL 465 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400UL 466 #define MTRR_DEF_TYPE 0x00000000000000ffUL 467 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000UL 468 #define MTRR_PHYSBASE_TYPE 0x00000000000000ffUL 469 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000UL 470 #define MTRR_PHYSMASK_VALID 0x0000000000000800UL 471 472 /* Performance Control Register (5x86 only). */ 473 #define PCR0 0x20 474 #define PCR0_RSTK 0x01 /* Enables return stack */ 475 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 476 #define PCR0_LOOP 0x04 /* Enables loop */ 477 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 478 serialize pipe. */ 479 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 480 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 481 #define PCR0_LSSER 0x80 /* Disable reorder */ 482 483 /* Device Identification Registers */ 484 #define DIR0 0xfe 485 #define DIR1 0xff 486 487 /* 488 * Machine Check register constants. 489 */ 490 #define MCG_CAP_COUNT 0x000000ff 491 #define MCG_CAP_CTL_P 0x00000100 492 #define MCG_CAP_EXT_P 0x00000200 493 #define MCG_CAP_TES_P 0x00000800 494 #define MCG_CAP_EXT_CNT 0x00ff0000 495 #define MCG_STATUS_RIPV 0x00000001 496 #define MCG_STATUS_EIPV 0x00000002 497 #define MCG_STATUS_MCIP 0x00000004 498 #define MCG_CTL_ENABLE 0xffffffffffffffffUL 499 #define MCG_CTL_DISABLE 0x0000000000000000UL 500 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 501 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 502 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 503 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 504 #define MC_STATUS_MCA_ERROR 0x000000000000ffffUL 505 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000UL 506 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000UL 507 #define MC_STATUS_PCC 0x0200000000000000UL 508 #define MC_STATUS_ADDRV 0x0400000000000000UL 509 #define MC_STATUS_MISCV 0x0800000000000000UL 510 #define MC_STATUS_EN 0x1000000000000000UL 511 #define MC_STATUS_UC 0x2000000000000000UL 512 #define MC_STATUS_OVER 0x4000000000000000UL 513 #define MC_STATUS_VAL 0x8000000000000000UL 514 515 /* 516 * The following four 3-byte registers control the non-cacheable regions. 517 * These registers must be written as three separate bytes. 518 * 519 * NCRx+0: A31-A24 of starting address 520 * NCRx+1: A23-A16 of starting address 521 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 522 * 523 * The non-cacheable region's starting address must be aligned to the 524 * size indicated by the NCR_SIZE_xx field. 525 */ 526 #define NCR1 0xc4 527 #define NCR2 0xc7 528 #define NCR3 0xca 529 #define NCR4 0xcd 530 531 #define NCR_SIZE_0K 0 532 #define NCR_SIZE_4K 1 533 #define NCR_SIZE_8K 2 534 #define NCR_SIZE_16K 3 535 #define NCR_SIZE_32K 4 536 #define NCR_SIZE_64K 5 537 #define NCR_SIZE_128K 6 538 #define NCR_SIZE_256K 7 539 #define NCR_SIZE_512K 8 540 #define NCR_SIZE_1M 9 541 #define NCR_SIZE_2M 10 542 #define NCR_SIZE_4M 11 543 #define NCR_SIZE_8M 12 544 #define NCR_SIZE_16M 13 545 #define NCR_SIZE_32M 14 546 #define NCR_SIZE_4G 15 547 548 /* 549 * The address region registers are used to specify the location and 550 * size for the eight address regions. 551 * 552 * ARRx + 0: A31-A24 of start address 553 * ARRx + 1: A23-A16 of start address 554 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 555 */ 556 #define ARR0 0xc4 557 #define ARR1 0xc7 558 #define ARR2 0xca 559 #define ARR3 0xcd 560 #define ARR4 0xd0 561 #define ARR5 0xd3 562 #define ARR6 0xd6 563 #define ARR7 0xd9 564 565 #define ARR_SIZE_0K 0 566 #define ARR_SIZE_4K 1 567 #define ARR_SIZE_8K 2 568 #define ARR_SIZE_16K 3 569 #define ARR_SIZE_32K 4 570 #define ARR_SIZE_64K 5 571 #define ARR_SIZE_128K 6 572 #define ARR_SIZE_256K 7 573 #define ARR_SIZE_512K 8 574 #define ARR_SIZE_1M 9 575 #define ARR_SIZE_2M 10 576 #define ARR_SIZE_4M 11 577 #define ARR_SIZE_8M 12 578 #define ARR_SIZE_16M 13 579 #define ARR_SIZE_32M 14 580 #define ARR_SIZE_4G 15 581 582 /* 583 * The region control registers specify the attributes associated with 584 * the ARRx addres regions. 585 */ 586 #define RCR0 0xdc 587 #define RCR1 0xdd 588 #define RCR2 0xde 589 #define RCR3 0xdf 590 #define RCR4 0xe0 591 #define RCR5 0xe1 592 #define RCR6 0xe2 593 #define RCR7 0xe3 594 595 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 596 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 597 #define RCR_WWO 0x02 /* Weak write ordering. */ 598 #define RCR_WL 0x04 /* Weak locking. */ 599 #define RCR_WG 0x08 /* Write gathering. */ 600 #define RCR_WT 0x10 /* Write-through. */ 601 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 602 603 /* AMD Write Allocate Top-Of-Memory and Control Register */ 604 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 605 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 606 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 607 608 /* x86_64 MSR's */ 609 #define MSR_EFER 0xc0000080 /* extended features */ 610 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 611 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 612 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 613 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 614 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 615 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 616 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 617 #define MSR_TSCAUX 0xc0000103 /* TSC_AUX register (for rdtscp) */ 618 #define MSR_PERFEVSEL0 0xc0010000 619 #define MSR_PERFEVSEL1 0xc0010001 620 #define MSR_PERFEVSEL2 0xc0010002 621 #define MSR_PERFEVSEL3 0xc0010003 622 #undef MSR_PERFCTR0 623 #undef MSR_PERFCTR1 624 #define MSR_PERFCTR0 0xc0010004 625 #define MSR_PERFCTR1 0xc0010005 626 #define MSR_PERFCTR2 0xc0010006 627 #define MSR_PERFCTR3 0xc0010007 628 #define MSR_SYSCFG 0xc0010010 629 #define MSR_IORRBASE0 0xc0010016 630 #define MSR_IORRMASK0 0xc0010017 631 #define MSR_IORRBASE1 0xc0010018 632 #define MSR_IORRMASK1 0xc0010019 633 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 634 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 635 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 636 637 /* AMD MSRs */ 638 #define MSR_AMD_DE_CFG 0xc0011029 639 640 /* AMD SVM MSRs */ 641 #define MSR_AMD_VM_CR 0xc0010114 642 #define MSR_AMD_VM_HSAVE_PA 0xc0010117 643 644 /* AMD MSR_AMD_VM_CR fields */ 645 #define MSR_AMD_VM_CR_SVMDIS 0x00000010 /* SVM Disabled */ 646 647 /* VIA ACE crypto featureset: for via_feature_rng */ 648 #define VIA_HAS_RNG 1 /* cpu has RNG */ 649 650 /* VIA ACE crypto featureset: for via_feature_xcrypt */ 651 #define VIA_HAS_AES 1 /* cpu has AES */ 652 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 653 #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 654 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 655 656 /* Centaur Extended Feature flags */ 657 #define VIA_CPUID_HAS_RNG 0x000004 658 #define VIA_CPUID_DO_RNG 0x000008 659 #define VIA_CPUID_HAS_ACE 0x000040 660 #define VIA_CPUID_DO_ACE 0x000080 661 #define VIA_CPUID_HAS_ACE2 0x000100 662 #define VIA_CPUID_DO_ACE2 0x000200 663 #define VIA_CPUID_HAS_PHE 0x000400 664 #define VIA_CPUID_DO_PHE 0x000800 665 #define VIA_CPUID_HAS_PMM 0x001000 666 #define VIA_CPUID_DO_PMM 0x002000 667 668 /* Hardware P-states interface */ 669 #define MSR_PPERF 0x0000064e 670 #define MSR_PERF_LIMIT_REASONS 0x0000064f 671 #define MSR_PM_ENABLE 0x00000770 672 #define MSR_HWP_CAPABILITIES 0x00000771 673 #define MSR_HWP_REQUEST_PKG 0x00000772 674 #define MSR_HWP_INTERRUPT 0x00000773 675 #define MSR_HWP_REQUEST 0x00000774 676 #define MSR_HWP_STATUS 0x00000777 677 678 /* Local APIC TSC Deadline Mode Target count */ 679 #define MSR_TSC_DEADLINE 0x000006e0 680 681 #endif /* !_CPU_SPECIALREG_H_ */ 682