1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 31 * $FreeBSD: src/sys/amd64/include/specialreg.h,v 1.39 2007/05/31 11:26:44 des Exp $ 32 */ 33 34 #ifndef _CPU_SPECIALREG_H_ 35 #define _CPU_SPECIALREG_H_ 36 37 /* 38 * Bits in CR0 special register 39 */ 40 #define CR0_PE 0x00000001 /* Protected mode Enable */ 41 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 42 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 43 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 44 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 45 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 46 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in all modes) */ 47 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 48 #define CR0_NW 0x20000000 /* Not Write-through */ 49 #define CR0_CD 0x40000000 /* Cache Disable */ 50 #define CR0_PG 0x80000000 /* PaGing enable */ 51 52 /* 53 * Bits in CR4 special register 54 */ 55 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 56 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 57 #define CR4_TSD 0x00000004 /* Time stamp disable */ 58 #define CR4_DE 0x00000008 /* Debugging extensions */ 59 #define CR4_PSE 0x00000010 /* Page size extensions */ 60 #define CR4_PAE 0x00000020 /* Physical address extension */ 61 #define CR4_MCE 0x00000040 /* Machine check enable */ 62 #define CR4_PGE 0x00000080 /* Page global enable */ 63 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 64 #define CR4_OSFXSR 0x00000200 /* Fast FPU save/restore used by OS */ 65 #define CR4_OSXMMEXCPT 0x00000400 /* Enable SIMD/MMX2 to use except 16 */ 66 #define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */ 67 #define CR4_LA57 0x00001000 /* Enable 57-bit linear address */ 68 #define CR4_VMXE 0x00002000 /* Enable VMX - Intel specific */ 69 #define CR4_SMXE 0x00004000 /* Enable SMX - Intel specific */ 70 #define CR4_FSGSBASE 0x00010000 /* Enable *FSBASE and *GSBASE instructions */ 71 #define CR4_PCIDE 0x00020000 /* Enable Process Context IDentifiers */ 72 #define CR4_OSXSAVE 0x00040000 /* Enable XSave (for AVX Instructions) */ 73 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevent */ 74 #define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Prevent */ 75 #define CR4_PKE 0x00400000 /* Protection Keys Enable for user pages */ 76 #define CR4_CET 0x00800000 /* Enable CET */ 77 #define CR4_PKS 0x01000000 /* Protection Keys Enable for kern pages */ 78 79 /* 80 * Extended Control Register XCR0 81 */ 82 #define CPU_XFEATURE_X87 0x00000001 /* x87 FPU/MMX state */ 83 #define CPU_XFEATURE_SSE 0x00000002 /* SSE state */ 84 #define CPU_XFEATURE_YMM 0x00000004 /* AVX-256 (YMMn registers) */ 85 #define CPU_XFEATURE_AVX CPU_XFEATURE_YMM 86 87 /* 88 * CPUID "features" bits 89 */ 90 91 /* CPUID Fn0000_0001 %edx features */ 92 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 93 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 94 #define CPUID_DE 0x00000004 /* has debugging extension */ 95 #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ 96 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 97 #define CPUID_MSR 0x00000020 /* has model specific registers */ 98 #define CPUID_PAE 0x00000040 /* has physical address extension */ 99 #define CPUID_MCE 0x00000080 /* has machine check exception */ 100 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 101 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 102 /* Bit 10 reserved 0x00000400 */ 103 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 104 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 105 #define CPUID_PGE 0x00002000 /* has page global extension */ 106 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 107 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 108 #define CPUID_PAT 0x00010000 /* Page Attribute Table */ 109 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 110 #define CPUID_PSN 0x00040000 /* Processor Serial Number */ 111 #define CPUID_CLFSH 0x00080000 /* CLFLUSH instruction supported */ 112 /* Bit 20 reserved 0x00100000 */ 113 #define CPUID_DS 0x00200000 /* Debug Store */ 114 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 115 #define CPUID_MMX 0x00800000 /* MMX supported */ 116 #define CPUID_FXSR 0x01000000 /* Fast FP/MMX Save/Restore */ 117 #define CPUID_SSE 0x02000000 /* Streaming SIMD Extensions */ 118 #define CPUID_SSE2 0x04000000 /* Streaming SIMD Extensions 2 */ 119 #define CPUID_SS 0x08000000 /* Self-Snoop */ 120 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 121 #define CPUID_TM 0x20000000 /* Thermal Monitor (TCC) */ 122 #define CPUID_IA64 0x40000000 /* IA64 processor emulating x86 */ 123 #define CPUID_PBE 0x80000000 /* Pending Break Enable */ 124 125 /* CPUID Fn0000_0001 %ecx features */ 126 #define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */ 127 #define CPUID2_PCLMULQDQ 0x00000002 /* PCLMULQDQ instructions */ 128 #define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */ 129 #define CPUID2_MON 0x00000008 /* MONITOR/MWAIT instructions */ 130 #define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */ 131 #define CPUID2_VMX 0x00000020 /* Virtual Machine eXtensions */ 132 #define CPUID2_SMX 0x00000040 /* Safer Mode eXtensions */ 133 #define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */ 134 #define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */ 135 #define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */ 136 #define CPUID2_CNXTID 0x00000400 /* Context ID */ 137 #define CPUID2_SDBG 0x00000800 /* Silicon Debug */ 138 #define CPUID2_FMA 0x00001000 /* Fused Multiply Add */ 139 #define CPUID2_CX16 0x00002000 /* CMPXCHG16B instruction */ 140 #define CPUID2_XTPR 0x00004000 /* Task Priority Messages disabled? */ 141 #define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 142 /* Bit 16 reserved 0x00010000 */ 143 #define CPUID2_PCID 0x00020000 /* Process Context ID */ 144 #define CPUID2_DCA 0x00040000 /* Direct Cache Access */ 145 #define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ 146 #define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ 147 #define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */ 148 #define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */ 149 #define CPUID2_POPCNT 0x00800000 /* POPCOUNT instruction available */ 150 #define CPUID2_TSCDLT 0x01000000 /* LAPIC TSC-Deadline Mode support */ 151 #define CPUID2_AESNI 0x02000000 /* AES Instruction Set */ 152 #define CPUID2_XSAVE 0x04000000 /* XSave supported by CPU */ 153 #define CPUID2_OSXSAVE 0x08000000 /* XSave and AVX supported by OS */ 154 #define CPUID2_AVX 0x10000000 /* AVX instruction set support */ 155 #define CPUID2_F16C 0x20000000 /* F16C (half-precision) FP support */ 156 #define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */ 157 #define CPUID2_VMM 0x80000000 /* Hypervisor present */ 158 159 /* CPUID Fn0000_0001 %eax info */ 160 #define CPUID_STEPPING 0x0000000f 161 #define CPUID_MODEL 0x000000f0 162 #define CPUID_FAMILY 0x00000f00 163 #define CPUID_EXT_MODEL 0x000f0000 164 #define CPUID_EXT_FAMILY 0x0ff00000 165 166 #define CPUID_TO_MODEL(id) \ 167 ((((id) & CPUID_MODEL) >> 4) | (((id) & CPUID_EXT_MODEL) >> 12)) 168 #define CPUID_TO_FAMILY(id) \ 169 ((((id) & CPUID_FAMILY) >> 8) + (((id) & CPUID_EXT_FAMILY) >> 20)) 170 171 /* CPUID Fn0000_0001 %ebx info */ 172 #define CPUID_BRAND_INDEX 0x000000ff 173 #define CPUID_CLFUSH_SIZE 0x0000ff00 174 #define CPUID_HTT_CORES 0x00ff0000 175 #define CPUID_HTT_CORE_SHIFT 16 176 #define CPUID_LOCAL_APIC_ID 0xff000000 177 178 /* 179 * Intel Deterministic Cache Parameters 180 * CPUID Fn0000_0004 181 */ 182 #define FUNC_4_MAX_CORE_NO(eax) ((((eax) >> 26) & 0x3f)) 183 184 /* 185 * Intel/AMD MONITOR/MWAIT 186 * CPUID Fn0000_0005 187 */ 188 /* %ecx */ 189 #define CPUID_MWAIT_EXT 0x00000001 /* MONITOR/MWAIT Extensions */ 190 #define CPUID_MWAIT_INTBRK 0x00000002 /* Interrupt as Break Event */ 191 /* %edx: number of substates for specific C-state */ 192 #define CPUID_MWAIT_CX_SUBCNT(edx, cstate) \ 193 (((edx) >> ((cstate) * 4)) & 0xf) 194 195 /* MWAIT EAX to Cx and its substate */ 196 #define MWAIT_EAX_TO_CX(x) ((((x) >> 4) + 1) & 0xf) 197 #define MWAIT_EAX_TO_CX_SUB(x) ((x) & 0xf) 198 199 /* MWAIT EAX hint and ECX extension */ 200 #define MWAIT_EAX_HINT(cx, sub) \ 201 (((((uint32_t)(cx) - 1) & 0xf) << 4) | ((sub) & 0xf)) 202 #define MWAIT_ECX_INTBRK 0x1 203 204 /* 205 * Intel/AMD Digital Thermal Sensor and Power Management 206 * CPUID Fn0000_0006 207 */ 208 /* %eax */ 209 #define CPUID_THERMAL_SENSOR 0x00000001 /* Digital thermal sensor */ 210 #define CPUID_THERMAL_TURBO 0x00000002 /* Intel Turbo boost */ 211 #define CPUID_THERMAL_ARAT 0x00000004 /* Always running APIC timer */ 212 #define CPUID_THERMAL_PLN 0x00000010 /* Power limit notification */ 213 #define CPUID_THERMAL_ECMD 0x00000020 /* Clock modulation extension */ 214 #define CPUID_THERMAL_PTM 0x00000040 /* Package thermal management */ 215 #define CPUID_THERMAL_HWP 0x00000080 /* Hardware P-states */ 216 /* %ecx */ 217 #define CPUID_THERMAL2_SETBH 0x00000008 /* Energy performance bias */ 218 219 /* 220 * Intel/AMD Structured Extended Feature 221 * CPUID Fn0000_0007 222 * %ecx == 0: Subleaf 0 223 * %eax: The Maximum input value for supported subleaf. 224 * %ebx: Feature bits. 225 * %ecx: Feature bits. 226 * %edx: Feature bits. 227 * %ecx == 1: Structure Extendede Feature Enumeration Sub-leaf 228 * %eax: See below. 229 */ 230 /* %ecx = 0, %ebx */ 231 #define CPUID_STDEXT_FSGSBASE 0x00000001 /* {RD,WR}{FS,GS}BASE */ 232 #define CPUID_STDEXT_TSC_ADJUST 0x00000002 /* IA32_TSC_ADJUST MSR support */ 233 #define CPUID_STDEXT_SGX 0x00000004 /* Software Guard Extensions */ 234 #define CPUID_STDEXT_BMI1 0x00000008 /* Advanced bit manipulation ext. 1st grp */ 235 #define CPUID_STDEXT_HLE 0x00000010 /* Hardware Lock Elision */ 236 #define CPUID_STDEXT_AVX2 0x00000020 /* Advanced Vector Extensions 2 */ 237 #define CPUID_STDEXT_FDP_EXC 0x00000040 /* x87FPU Data ptr updated only on x87exp */ 238 #define CPUID_STDEXT_SMEP 0x00000080 /* Supervisor-Mode Execution Prevention */ 239 #define CPUID_STDEXT_BMI2 0x00000100 /* Advanced bit manipulation ext. 2nd grp */ 240 #define CPUID_STDEXT_ERMS 0x00000200 /* Enhanced REP MOVSB/STOSB */ 241 #define CPUID_STDEXT_INVPCID 0x00000400 /* INVPCID instruction */ 242 #define CPUID_STDEXT_RTM 0x00000800 /* Restricted Transactional Memory */ 243 #define CPUID_STDEXT_PQM 0x00001000 /* Platform Quality of Service Monitoring */ 244 #define CPUID_STDEXT_NFPUSG 0x00002000 /* Deprecate FPU CS and FPU DS values */ 245 #define CPUID_STDEXT_MPX 0x00004000 /* Memory Protection Extensions */ 246 #define CPUID_STDEXT_PQE 0x00008000 /* Platform Quality of Service Enforcement */ 247 #define CPUID_STDEXT_AVX512F 0x00010000 /* AVX-512 Foundation */ 248 #define CPUID_STDEXT_AVX512DQ 0x00020000 /* AVX-512 Double/Quadword */ 249 #define CPUID_STDEXT_RDSEED 0x00040000 /* RDSEED instruction */ 250 #define CPUID_STDEXT_ADX 0x00080000 /* ADCX/ADOX instructions */ 251 #define CPUID_STDEXT_SMAP 0x00100000 /* Supervisor-Mode Access Prevention */ 252 #define CPUID_STDEXT_AVX512IFMA 0x00200000 /* AVX-512 Integer Fused Multiply Add */ 253 /* Bit 22: reserved; was PCOMMIT */ 254 #define CPUID_STDEXT_CLFLUSHOPT 0x00800000 /* Cache Line FLUSH OPTimized */ 255 #define CPUID_STDEXT_CLWB 0x01000000 /* Cache Line Write Back */ 256 #define CPUID_STDEXT_PROCTRACE 0x02000000 /* Processor Trace */ 257 #define CPUID_STDEXT_AVX512PF 0x04000000 /* AVX-512 PreFetch */ 258 #define CPUID_STDEXT_AVX512ER 0x08000000 /* AVX-512 Exponential and Reciprocal */ 259 #define CPUID_STDEXT_AVX512CD 0x10000000 /* AVX-512 Conflict Detection */ 260 #define CPUID_STDEXT_SHA 0x20000000 /* SHA Extensions */ 261 #define CPUID_STDEXT_AVX512BW 0x40000000 /* AVX-512 Byte and Word */ 262 #define CPUID_STDEXT_AVX512VL 0x80000000 /* AVX-512 Vector Length */ 263 264 /* %ecx = 0, %ecx */ 265 #define CPUID_STDEXT2_PREFETCHWT1 0x00000001 /* PREFETCHWT1 instruction */ 266 #define CPUID_STDEXT2_AVX512VBMI 0x00000002 /* AVX-512 Vector Byte Manipulation */ 267 #define CPUID_STDEXT2_UMIP 0x00000004 /* User-Mode Instruction prevention */ 268 #define CPUID_STDEXT2_PKU 0x00000008 /* Protection Keys for User-mode pages */ 269 #define CPUID_STDEXT2_OSPKE 0x00000010 /* PKU enabled by OS */ 270 #define CPUID_STDEXT2_WAITPKG 0x00000020 /* Timed pause and user-level monitor/wait */ 271 #define CPUID_STDEXT2_AVX512VBMI2 0x00000040 /* AVX-512 Vector Byte Manipulation 2 */ 272 #define CPUID_STDEXT2_CET_SS 0x00000080 /* CET Shadow Stack */ 273 #define CPUID_STDEXT2_GFNI 0x00000100 /* Galois Field instructions */ 274 #define CPUID_STDEXT2_VAES 0x00000200 /* Vector AES instruction set */ 275 #define CPUID_STDEXT2_VPCLMULQDQ 0x00000400 /* CLMUL instruction set */ 276 #define CPUID_STDEXT2_AVX512VNNI 0x00000800 /* Vector Neural Network instructions */ 277 #define CPUID_STDEXT2_AVX512BITALG 0x00001000 /* BITALG instructions */ 278 /* Bit 13: reserved */ 279 #define CPUID_STDEXT2_AVX512VPOPCNTDQ 0x00004000 /* Vector Population Count Double/Quadword */ 280 /* Bit 15: reserved */ 281 #define CPUID_STDEXT2_LA57 0x00010000 /* 57-bit linear addr & 5-level paging */ 282 /* Bits 21-17: MAWAU value for BNDLDX/BNDSTX */ 283 #define CPUID_STDEXT2_RDPID 0x00400000 /* RDPID and IA32_TSC_AUX */ 284 #define CPUID_STDEXT2_KL 0x00800000 /* Key Locker */ 285 /* Bit 24: reserved */ 286 #define CPUID_STDEXT2_CLDEMOTE 0x02000000 /* Cache line demote */ 287 /* Bit 26: reserved */ 288 #define CPUID_STDEXT2_MOVDIRI 0x08000000 /* MOVDIRI instruction */ 289 #define CPUID_STDEXT2_MOVDIR64B 0x10000000 /* MOVDIR64B instruction */ 290 #define CPUID_STDEXT2_ENQCMD 0x20000000 /* Enqueue Stores */ 291 #define CPUID_STDEXT2_SGXLC 0x40000000 /* SGX Launch Configuration */ 292 #define CPUID_STDEXT2_PKS 0x80000000 /* Protection Keys for kern-mode pages */ 293 294 /* %ecx = 0, %edx */ 295 #define CPUID_STDEXT3_AVX5124VNNIW 0x00000004 /* AVX512 4-reg Neural Network instructions */ 296 #define CPUID_STDEXT3_AVX5124FMAPS 0x00000008 /* AVX512 4-reg Multiply Accumulation Single precision */ 297 #define CPUID_STDEXT3_FSRM 0x00000010 /* Fast Short REP MOVE */ 298 #define CPUID_STDEXT3_AVX512VP2INTERSECT 0x00000100 /* AVX512 VP2INTERSECT */ 299 #define CPUID_STDEXT3_MCUOPT 0x00000200 /* IA32_MCU_OPT_CTRL */ 300 #define CPUID_STDEXT3_MD_CLEAR 0x00000400 /* VERW clears CPU buffers */ 301 #define CPUID_STDEXT3_TSXFA 0x00002000 /* MSR_TSX_FORCE_ABORT bit 0 */ 302 #define CPUID_STDEXT3_SERIALIZE 0x00004000 /* SERIALIZE instruction */ 303 #define CPUID_STDEXT3_HYBRID 0x00008000 /* Hybrid part */ 304 #define CPUID_STDEXT3_TSXLDTRK 0x00010000 /* TSX suspend load addr tracking */ 305 #define CPUID_STDEXT3_PCONFIG 0x00040000 /* Platform configuration */ 306 #define CPUID_STDEXT3_CET_IBT 0x00100000 /* CET Indirect Branch Tracking */ 307 #define CPUID_STDEXT3_IBPB 0x04000000 /* IBRS / IBPB Speculation Control */ 308 #define CPUID_STDEXT3_STIBP 0x08000000 /* STIBP Speculation Control */ 309 #define CPUID_STDEXT3_L1D_FLUSH 0x10000000 /* IA32_FLUSH_CMD MSR */ 310 #define CPUID_STDEXT3_ARCH_CAP 0x20000000 /* IA32_ARCH_CAPABILITIES */ 311 #define CPUID_STDEXT3_CORE_CAP 0x40000000 /* IA32_CORE_CAPABILITIES */ 312 #define CPUID_STDEXT3_SSBD 0x80000000 /* Speculative Store Bypass Disable */ 313 314 /* 315 * Intel x2APIC Features / Processor topology 316 * CPUID Fn0000_000B 317 */ 318 #define FUNC_B_THREAD_LEVEL 0 319 320 #define FUNC_B_INVALID_TYPE 0 321 #define FUNC_B_THREAD_TYPE 1 322 #define FUNC_B_CORE_TYPE 2 323 324 #define FUNC_B_TYPE(ecx) (((ecx) >> 8) & 0xff) 325 #define FUNC_B_BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) 326 #define FUNC_B_LEVEL_MAX_SIBLINGS(ebx) ((ebx) & 0xffff) 327 328 /* 329 * Intel/AMD CPUID Processor Extended State Enumeration 330 * CPUID Fn0000_000D 331 * %ecx == 0: supported features info: 332 * %eax: Valid bits of lower 32bits of XCR0 333 * %ebx: Maximum save area size for features enabled in XCR0 334 * %ecx: Maximum save area size for all cpu features 335 * %edx: Valid bits of upper 32bits of XCR0 336 * %ecx == 1: 337 * %eax: Bit 0 => xsaveopt instruction available (sandy bridge onwards) 338 * %ebx: Save area size for features enabled by XCR0 | IA32_XSS 339 * %ecx: Valid bits of lower 32bits of IA32_XSS 340 * %edx: Valid bits of upper 32bits of IA32_XSS 341 * %ecx >= 2: Save area details for XCR0 bit n 342 * %eax: size of save area for this feature 343 * %ebx: offset of save area for this feature 344 * %ecx, %edx: reserved 345 * All of %eax, %ebx, %ecx and %edx are zero for unsupported features. 346 */ 347 /* %ecx = 1, %eax */ 348 #define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */ 349 #define CPUID_PES1_XSAVEC 0x00000002 /* xsavec & compacted XRSTOR */ 350 #define CPUID_PES1_XGETBV 0x00000004 /* xgetbv with ECX = 1 */ 351 #define CPUID_PES1_XSAVES 0x00000008 /* xsaves/xrstors, IA32_XSS */ 352 353 /* 354 * Extended Features 355 * CPUID Fn8000_0001 356 */ 357 /* %edx */ 358 #define CPUID_SYSCALL 0x00000800 /* (Intel/AMD) SYSCALL/SYSRET */ 359 #define CPUID_MPC 0x00080000 /* (AMD) Multiprocessing Capable */ 360 #define CPUID_XD 0x00100000 /* (Intel) Execute Disable */ 361 #define CPUID_NOX CPUID_XD /* (AMD) No Execute Page Protection */ 362 #define CPUID_MMXX 0x00400000 /* (AMD) MMX Extensions */ 363 #define CPUID_FFXSR 0x02000000 /* (AMD) FXSAVE/FXSTOR Extensions */ 364 #define CPUID_PAGE1GB 0x04000000 /* (Intel) 1GB Large Page Support */ 365 #define CPUID_RDTSCP 0x08000000 /* (Intel) Read TSC Pair Instruction */ 366 #define CPUID_EM64T 0x20000000 /* (Intel) EM64T long mode */ 367 #define CPUID_3DNOW2 0x40000000 /* (AMD) 3DNow! Instruction Extension */ 368 #define CPUID_3DNOW 0x80000000 /* (AMD) 3DNow! Instructions */ 369 /* compatibility defines */ 370 #define AMDID_SYSCALL CPUID_SYSCALL 371 #define AMDID_MP CPUID_MPC 372 #define AMDID_NX CPUID_NOX 373 #define AMDID_EXT_MMX CPUID_MMXX 374 #define AMDID_FFXSR CPUID_FFXSR 375 #define AMDID_PAGE1GB CPUID_PAGE1GB 376 #define AMDID_RDTSCP CPUID_RDTSCP 377 #define AMDID_LM CPUID_EM64T 378 #define AMDID_EXT_3DNOW CPUID_3DNOW2 379 #define AMDID_3DNOW CPUID_3DNOW 380 /* %ecx */ 381 #define CPUID_LAHF 0x00000001 /* (Intel/AMD) LAHF/SAHF in 64-bit mode */ 382 #define CPUID_CMPLEGACY 0x00000002 /* (AMD) Core multi-processing legacy mode */ 383 #define CPUID_SVM 0x00000004 /* (AMD) Secure Virtual Machine */ 384 #define CPUID_EAPIC 0x00000008 /* (AMD) Extended APIC space */ 385 #define CPUID_ALTMOVCR0 0x00000010 /* (AMD) LOCK MOV CR0 means MOV CR8 */ 386 #define CPUID_ABM 0x00000020 /* (AMD) LZCNT instruction */ 387 #define CPUID_SSE4A 0x00000040 /* (AMD) SSE4A instruction set */ 388 #define CPUID_MISALIGNSSE 0x00000080 /* (AMD) Misaligned SSE mode */ 389 #define CPUID_PREFETCHW 0x00000100 /* (Intel/AMD) PREFETCHW */ 390 #define CPUID_3DNOWPF CPUID_PREFETCHW /* 3DNow Prefetch */ 391 #define CPUID_OSVW 0x00000200 /* (AMD) OS visible workaround */ 392 #define CPUID_IBS 0x00000400 /* (AMD) Instruction Based Sampling */ 393 #define CPUID_XOP 0x00000800 /* (AMD) XOP instruction set */ 394 #define CPUID_SKINIT 0x00001000 /* (AMD) SKINIT and STGI */ 395 #define CPUID_WDT 0x00002000 /* (AMD) Watchdog timer support */ 396 #define CPUID_LWP 0x00008000 /* (AMD) Light Weight Profiling */ 397 #define CPUID_FMA4 0x00010000 /* (AMD) FMA4 instructions */ 398 #define CPUID_TCE 0x00020000 /* (AMD) Translation cache Extension */ 399 #define CPUID_NODEID 0x00080000 /* (AMD) NodeID MSR available*/ 400 #define CPUID_TBM 0x00200000 /* (AMD) TBM instructions */ 401 #define CPUID_TOPOEXT 0x00400000 /* (AMD) CPUID Topology Extension */ 402 #define CPUID_PCEC 0x00800000 /* (AMD) Processor Perf Counter Extension */ 403 #define CPUID_PCENB 0x01000000 /* (AMD) NB Perf Counter Extension */ 404 #define CPUID_SPM 0x02000000 /* (AMD) Stream Perf Mon */ 405 #define CPUID_DBE 0x04000000 /* (AMD) Data access breakpoint extension */ 406 #define CPUID_PTSC 0x08000000 /* (AMD) Performance time-stamp counter */ 407 #define CPUID_L2IPERFC 0x10000000 /* (AMD) L2I performance counter extension */ 408 #define CPUID_MWAITX 0x20000000 /* (AMD) MWAITX/MONITORX support */ 409 /* compatibility defines */ 410 #define AMDID2_LAHF CPUID_LAHF 411 #define AMDID2_CMP CPUID_CMPLEGACY 412 #define AMDID2_SVM CPUID_SVM 413 #define AMDID2_EXT_APIC CPUID_EAPIC 414 #define AMDID2_CR8 CPUID_ALTMOVCR0 415 #define AMDID2_ABM CPUID_ABM 416 #define AMDID2_SSE4A CPUID_SSE4A 417 #define AMDID2_MAS CPUID_MISALIGNSSE 418 #define AMDID2_PREFETCH CPUID_PREFETCHW 419 #define AMDID2_OSVW CPUID_OSVW 420 #define AMDID2_IBS CPUID_IBS 421 #define AMDID2_SSE5 CPUID_XOP 422 #define AMDID2_SKINIT CPUID_SKINIT 423 #define AMDID2_WDT CPUID_WDT 424 #define AMDID2_TOPOEXT CPUID_TOPOEXT 425 426 /* 427 * Advanced Power Management 428 * CPUID Fn8000_0007 %edx 429 * Only ITSC is for both Intel and AMD; others are for AMD only. 430 */ 431 #define CPUID_APM_TS 0x00000001 /* Temperature Sensor */ 432 #define CPUID_APM_FID 0x00000002 /* Frequency ID control */ 433 #define CPUID_APM_VID 0x00000004 /* Voltage ID control */ 434 #define CPUID_APM_TTP 0x00000008 /* THERMTRIP (PCI F3xE4 register) */ 435 #define CPUID_APM_HTC 0x00000010 /* Hardware Thermal Control (TM) */ 436 #define CPUID_APM_STC 0x00000020 /* Software Thermal Control */ 437 #define CPUID_APM_100 0x00000040 /* 100MHz multiplier control */ 438 #define CPUID_APM_HWP 0x00000080 /* Hardware P-State control */ 439 #define CPUID_APM_ITSC 0x00000100 /* (Intel/AMD) Invariant TSC */ 440 #define CPUID_APM_CPB 0x00000200 /* Core Performance Boost */ 441 #define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */ 442 #define CPUID_APM_PROCFI 0x00000800 /* Processor Feedback */ 443 #define CPUID_APM_PROCPR 0x00001000 /* Processor Power Reporting */ 444 #define CPUID_APM_CONNSTBY 0x00002000 /* Connected Standby */ 445 #define CPUID_APM_RAPL 0x00004000 /* Running Average Power Limit */ 446 /* compatibility defines */ 447 #define AMDPM_TS CPUID_APM_TS 448 #define AMDPM_FID CPUID_APM_FID 449 #define AMDPM_VID CPUID_APM_VID 450 #define AMDPM_TTP CPUID_APM_TTP 451 #define AMDPM_TM CPUID_APM_HTC 452 #define AMDPM_STC CPUID_APM_STC 453 #define AMDPM_100MHZ_STEPS CPUID_APM_100 454 #define AMDPM_HW_PSTATE CPUID_APM_HWP 455 #define AMDPM_TSC_INVARIANT CPUID_APM_ITSC 456 #define AMDPM_CPB CPUID_APM_CPB 457 458 /* 459 * AMD Processor Capacity Parameters and Extended Features 460 * CPUID Fn8000_0008 461 * %eax: Long Mode Size Identifiers 462 * %ebx: Extended Feature Identifiers 463 * %ecx: Size Identifiers 464 * %edx: RDPRU Register Identifier Range 465 */ 466 /* %ebx */ 467 #define CPUID_CAPEX_CLZERO 0x00000001 /* CLZERO instruction */ 468 #define CPUID_CAPEX_IRPERF 0x00000002 /* InstRetCntMsr */ 469 #define CPUID_CAPEX_XSAVEERPTR 0x00000004 /* RstrFpErrPtrs by XRSTOR */ 470 #define CPUID_CAPEX_RDPRU 0x00000010 /* RDPRU instruction */ 471 #define CPUID_CAPEX_MCOMMIT 0x00000100 /* MCOMMIT instruction */ 472 #define CPUID_CAPEX_WBNOINVD 0x00000200 /* WBNOINVD instruction */ 473 #define CPUID_CAPEX_IBPB 0x00001000 /* Speculation Control IBPB */ 474 #define CPUID_CAPEX_IBRS 0x00004000 /* Speculation Control IBRS */ 475 #define CPUID_CAPEX_STIBP 0x00008000 /* Speculation Control STIBP */ 476 #define CPUID_CAPEX_IBRS_ALWAYSON 0x00010000 /* IBRS always on mode */ 477 #define CPUID_CAPEX_STIBP_ALWAYSON 0x00020000 /* STIBP always on mode */ 478 #define CPUID_CAPEX_PREFER_IBRS 0x00040000 /* IBRS preferred */ 479 #define CPUID_CAPEX_SSBD 0x01000000 /* Speculation Control SSBD */ 480 #define CPUID_CAPEX_VIRT_SSBD 0x02000000 /* Virt Spec Control SSBD */ 481 #define CPUID_CAPEX_SSB_NO 0x04000000 /* SSBD not required */ 482 /* %ecx info */ 483 #define AMDID_CMP_CORES 0x000000ff 484 #define AMDID_COREID_SIZE 0x0000f000 485 #define AMDID_COREID_SIZE_SHIFT 12 486 487 /* 488 * AMD SVM Revision and Feature Identification 489 * CPUID Fn8000_000A 490 */ 491 /* %eax - SVM revision */ 492 #define CPUID_AMD_SVM_REV 0x000000ff /* (bits 7-0) SVM revision number */ 493 /* %edx - SVM features */ 494 #define CPUID_AMD_SVM_NP 0x00000001 /* Nested Paging */ 495 #define CPUID_AMD_SVM_LbrVirt 0x00000002 /* LBR virtualization */ 496 #define CPUID_AMD_SVM_SVML 0x00000004 /* SVM Lock */ 497 #define CPUID_AMD_SVM_NRIPS 0x00000008 /* NRIP Save on #VMEXIT */ 498 #define CPUID_AMD_SVM_TSCRateCtrl 0x00000010 /* MSR-based TSC rate control */ 499 #define CPUID_AMD_SVM_VMCBCleanBits 0x00000020 /* VMCB Clean Bits support */ 500 #define CPUID_AMD_SVM_FlushByASID 0x00000040 /* Flush by ASID */ 501 #define CPUID_AMD_SVM_DecodeAssist 0x00000080 /* Decode Assists support */ 502 #define CPUID_AMD_SVM_PauseFilter 0x00000400 /* PAUSE intercept filter */ 503 #define CPUID_AMD_SVM_PFThreshold 0x00001000 /* PAUSE filter threshold */ 504 #define CPUID_AMD_SVM_AVIC 0x00002000 /* Advanced Virtual Interrupt Controller */ 505 #define CPUID_AMD_SVM_V_VMSAVE_VMLOAD 0x00008000 /* VMSAVE/VMLOAD virtualization */ 506 #define CPUID_AMD_SVM_vGIF 0x00010000 /* Global Interrupt Flag virtualization */ 507 #define CPUID_AMD_SVM_GMET 0x00020000 /* Guest Mode Execution Trap */ 508 #define CPUID_AMD_SVM_SPEC_CTRL 0x00100000 /* SPEC_CTRL virtualization */ 509 #define CPUID_AMD_SVM_TLBICTL 0x01000000 /* TLB Intercept Control */ 510 511 /* 512 * CPUID manufacturers identifiers 513 */ 514 #define AMD_VENDOR_ID "AuthenticAMD" 515 #define CENTAUR_VENDOR_ID "CentaurHauls" 516 #define INTEL_VENDOR_ID "GenuineIntel" 517 518 /* 519 * Model-Specific Registers 520 */ 521 #define MSR_P5_MC_ADDR 0x000 522 #define MSR_P5_MC_TYPE 0x001 523 #define MSR_TSC 0x010 524 #define MSR_P5_CESR 0x011 525 #define MSR_P5_CTR0 0x012 526 #define MSR_P5_CTR1 0x013 527 #define MSR_IA32_PLATFORM_ID 0x017 528 529 #define MSR_APICBASE 0x01b 530 #define APICBASE_RESERVED 0x000006ff 531 #define APICBASE_BSP 0x00000100 /* bootstrap processor */ 532 #define APICBASE_X2APIC 0x00000400 /* x2APIC mode */ 533 #define APICBASE_ENABLED 0x00000800 /* software enable */ 534 #define APICBASE_ADDRESS 0xfffff000 /* physical address */ 535 536 #define MSR_EBL_CR_POWERON 0x02a 537 #define MSR_TEST_CTL 0x033 538 539 #define MSR_SPEC_CTRL 0x048 /* IBRS Spectre mitigation */ 540 #define SPEC_CTRL_IBRS 0x00000001 541 #define SPEC_CTRL_STIBP 0x00000002 542 #define SPEC_CTRL_SSBD 0x00000004 543 #define SPEC_CTRL_DUMMY1 0x00010000 /* ficticious */ 544 #define SPEC_CTRL_DUMMY2 0x00020000 /* ficticious */ 545 #define SPEC_CTRL_DUMMY3 0x00040000 /* ficticious */ 546 #define SPEC_CTRL_DUMMY4 0x00080000 /* ficticious */ 547 #define SPEC_CTRL_DUMMY5 0x00100000 /* ficticious */ 548 #define SPEC_CTRL_DUMMY6 0x00200000 /* ficticious */ 549 550 #define MSR_PRED_CMD 0x049 /* IBPB Spectre mitigation */ 551 552 #define MSR_BIOS_UPDT_TRIG 0x079 553 #define MSR_BBL_CR_D0 0x088 554 #define MSR_BBL_CR_D1 0x089 555 #define MSR_BBL_CR_D2 0x08a 556 #define MSR_BIOS_SIGN 0x08b 557 #define MSR_PERFCTR0 0x0c1 558 #define MSR_PERFCTR1 0x0c2 559 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 560 #define MSR_MTRRcap 0x0fe 561 562 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 563 #define IA32_ARCH_CAP_RDCL_NO 0x00000001 564 #define IA32_ARCH_CAP_IBRS_ALL 0x00000002 565 #define IA32_ARCH_CAP_RSBA 0x00000004 566 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008 567 #define IA32_ARCH_CAP_SSB_NO 0x00000010 568 #define IA32_ARCH_CAP_MDS_NO 0x00000020 569 #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x00000040 570 #define IA32_ARCH_CAP_TSX_CTRL 0x00000080 571 #define IA32_ARCH_CAP_TAA_NO 0x00000100 572 573 #define MSR_IA32_FLUSH_CMD 0x10b 574 #define IA32_FLUSH_CMD_L1D 0x01 575 576 #define MSR_BBL_CR_ADDR 0x116 577 #define MSR_BBL_CR_DECC 0x118 578 #define MSR_BBL_CR_CTL 0x119 579 #define MSR_BBL_CR_TRIG 0x11a 580 #define MSR_BBL_CR_BUSY 0x11b 581 #define MSR_BBL_CR_CTL3 0x11e 582 #define MSR_SYSENTER_CS 0x174 583 #define MSR_SYSENTER_ESP 0x175 584 #define MSR_SYSENTER_EIP 0x176 585 #define MSR_MCG_CAP 0x179 586 #define MSR_MCG_STATUS 0x17a 587 #define MSR_MCG_CTL 0x17b 588 #define MSR_EVNTSEL0 0x186 589 #define MSR_EVNTSEL1 0x187 590 #define MSR_THERM_CONTROL 0x19a 591 #define MSR_THERM_INTERRUPT 0x19b 592 #define MSR_THERM_STATUS 0x19c 593 594 #define MSR_IA32_MISC_ENABLE 0x1a0 /* Enable Misc. Processor Features */ 595 #define IA32_MISC_FAST_STR_EN (1ULL << 0) 596 #define IA32_MISC_ATCC_EN (1ULL << 3) 597 #define IA32_MISC_PERFMON_EN (1ULL << 7) 598 #define IA32_MISC_BTS_UNAVAIL (1ULL << 11) 599 #define IA32_MISC_PEBS_UNAVAIL (1ULL << 12) 600 #define IA32_MISC_EISST_EN (1ULL << 16) 601 #define IA32_MISC_MWAIT_EN (1ULL << 18) 602 #define IA32_MISC_LIMIT_CPUID (1ULL << 22) 603 #define IA32_MISC_XTPR_DIS (1ULL << 23) 604 #define IA32_MISC_XD_DIS (1ULL << 34) 605 606 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 607 #define MSR_PKG_THERM_STATUS 0x1b1 608 #define MSR_PKG_THERM_INTR 0x1b2 609 #define MSR_DEBUGCTLMSR 0x1d9 610 #define MSR_LASTBRANCHFROMIP 0x1db 611 #define MSR_LASTBRANCHTOIP 0x1dc 612 #define MSR_LASTINTFROMIP 0x1dd 613 #define MSR_LASTINTTOIP 0x1de 614 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 615 #define MSR_MTRRVarBase 0x200 616 #define MSR_MTRR64kBase 0x250 617 #define MSR_MTRR16kBase 0x258 618 #define MSR_MTRR4kBase 0x268 619 #define MSR_PAT 0x277 620 #define MSR_MTRRdefType 0x2ff 621 #define MSR_MC0_CTL 0x400 622 #define MSR_MC0_STATUS 0x401 623 #define MSR_MC0_ADDR 0x402 624 #define MSR_MC0_MISC 0x403 625 #define MSR_MC1_CTL 0x404 626 #define MSR_MC1_STATUS 0x405 627 #define MSR_MC1_ADDR 0x406 628 #define MSR_MC1_MISC 0x407 629 #define MSR_MC2_CTL 0x408 630 #define MSR_MC2_STATUS 0x409 631 #define MSR_MC2_ADDR 0x40a 632 #define MSR_MC2_MISC 0x40b 633 #define MSR_MC3_CTL 0x40c 634 #define MSR_MC3_STATUS 0x40d 635 #define MSR_MC3_ADDR 0x40e 636 #define MSR_MC3_MISC 0x40f 637 #define MSR_MC4_CTL 0x410 638 #define MSR_MC4_STATUS 0x411 639 #define MSR_MC4_ADDR 0x412 640 #define MSR_MC4_MISC 0x413 641 #define MSR_RAPL_POWER_UNIT 0x606 642 #define MSR_PKG_ENERGY_STATUS 0x611 643 #define MSR_DRAM_ENERGY_STATUS 0x619 644 #define MSR_PP0_ENERGY_STATUS 0x639 645 #define MSR_PP1_ENERGY_STATUS 0x641 646 #define MSR_PLATFORM_ENERGY_COUNTER 0x64d /* Skylake and later */ 647 #define MSR_PPERF 0x64e /* Productive Performance Count */ 648 #define MSR_PERF_LIMIT_REASONS 0x64f /* Indicator of Frequency Clipping */ 649 #define MSR_TSC_DEADLINE 0x6e0 /* LAPIC TSC Deadline Mode Target count */ 650 651 /* Hardware P-states interface */ 652 #define MSR_PM_ENABLE 0x770 /* Enable/disable HWP */ 653 #define MSR_HWP_CAPABILITIES 0x771 /* HWP Performance Range Enumeration */ 654 #define MSR_HWP_REQUEST_PKG 0x772 /* Control hints to all logical proc */ 655 #define MSR_HWP_INTERRUPT 0x773 /* Control HWP Native Interrupts */ 656 #define MSR_HWP_REQUEST 0x774 /* Control hints to a logical proc */ 657 #define MSR_HWP_STATUS 0x777 658 659 /* 660 * PAT modes. 661 */ 662 #define PAT_UNCACHEABLE 0x00 663 #define PAT_WRITE_COMBINING 0x01 664 #define PAT_WRITE_THROUGH 0x04 665 #define PAT_WRITE_PROTECTED 0x05 666 #define PAT_WRITE_BACK 0x06 667 #define PAT_UNCACHED 0x07 668 #define PAT_VALUE(i, m) ((long)(m) << (8 * (i))) 669 #define PAT_MASK(i) PAT_VALUE(i, 0xff) 670 671 /* 672 * Constants related to MTRRs 673 */ 674 #define MTRR_UNCACHEABLE 0x00 675 #define MTRR_WRITE_COMBINING 0x01 676 #define MTRR_WRITE_THROUGH 0x04 677 #define MTRR_WRITE_PROTECTED 0x05 678 #define MTRR_WRITE_BACK 0x06 679 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 680 #define MTRR_N16K 16 681 #define MTRR_N4K 64 682 #define MTRR_CAP_WC 0x0000000000000400UL 683 #define MTRR_CAP_FIXED 0x0000000000000100UL 684 #define MTRR_CAP_VCNT 0x00000000000000ffUL 685 #define MTRR_DEF_ENABLE 0x0000000000000800UL 686 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400UL 687 #define MTRR_DEF_TYPE 0x00000000000000ffUL 688 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000UL 689 #define MTRR_PHYSBASE_TYPE 0x00000000000000ffUL 690 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000UL 691 #define MTRR_PHYSMASK_VALID 0x0000000000000800UL 692 693 /* Performance Control Register (5x86 only). */ 694 #define PCR0 0x20 695 #define PCR0_RSTK 0x01 /* Enables return stack */ 696 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 697 #define PCR0_LOOP 0x04 /* Enables loop */ 698 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to serialize pipe. */ 699 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 700 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 701 #define PCR0_LSSER 0x80 /* Disable reorder */ 702 703 /* Device Identification Registers */ 704 #define DIR0 0xfe 705 #define DIR1 0xff 706 707 /* 708 * Machine Check register constants. 709 */ 710 #define MCG_CAP_COUNT 0x000000ff 711 #define MCG_CAP_CTL_P 0x00000100 712 #define MCG_CAP_EXT_P 0x00000200 713 #define MCG_CAP_TES_P 0x00000800 714 #define MCG_CAP_EXT_CNT 0x00ff0000 715 #define MCG_STATUS_RIPV 0x00000001 716 #define MCG_STATUS_EIPV 0x00000002 717 #define MCG_STATUS_MCIP 0x00000004 718 #define MCG_CTL_ENABLE 0xffffffffffffffffUL 719 #define MCG_CTL_DISABLE 0x0000000000000000UL 720 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 721 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 722 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 723 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 724 #define MC_STATUS_MCA_ERROR 0x000000000000ffffUL 725 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000UL 726 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000UL 727 #define MC_STATUS_PCC 0x0200000000000000UL 728 #define MC_STATUS_ADDRV 0x0400000000000000UL 729 #define MC_STATUS_MISCV 0x0800000000000000UL 730 #define MC_STATUS_EN 0x1000000000000000UL 731 #define MC_STATUS_UC 0x2000000000000000UL 732 #define MC_STATUS_OVER 0x4000000000000000UL 733 #define MC_STATUS_VAL 0x8000000000000000UL 734 735 /* 736 * The following four 3-byte registers control the non-cacheable regions. 737 * These registers must be written as three separate bytes. 738 * 739 * NCRx+0: A31-A24 of starting address 740 * NCRx+1: A23-A16 of starting address 741 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 742 * 743 * The non-cacheable region's starting address must be aligned to the 744 * size indicated by the NCR_SIZE_xx field. 745 */ 746 #define NCR1 0xc4 747 #define NCR2 0xc7 748 #define NCR3 0xca 749 #define NCR4 0xcd 750 751 #define NCR_SIZE_0K 0 752 #define NCR_SIZE_4K 1 753 #define NCR_SIZE_8K 2 754 #define NCR_SIZE_16K 3 755 #define NCR_SIZE_32K 4 756 #define NCR_SIZE_64K 5 757 #define NCR_SIZE_128K 6 758 #define NCR_SIZE_256K 7 759 #define NCR_SIZE_512K 8 760 #define NCR_SIZE_1M 9 761 #define NCR_SIZE_2M 10 762 #define NCR_SIZE_4M 11 763 #define NCR_SIZE_8M 12 764 #define NCR_SIZE_16M 13 765 #define NCR_SIZE_32M 14 766 #define NCR_SIZE_4G 15 767 768 /* 769 * The address region registers are used to specify the location and 770 * size for the eight address regions. 771 * 772 * ARRx + 0: A31-A24 of start address 773 * ARRx + 1: A23-A16 of start address 774 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 775 */ 776 #define ARR0 0xc4 777 #define ARR1 0xc7 778 #define ARR2 0xca 779 #define ARR3 0xcd 780 #define ARR4 0xd0 781 #define ARR5 0xd3 782 #define ARR6 0xd6 783 #define ARR7 0xd9 784 785 #define ARR_SIZE_0K 0 786 #define ARR_SIZE_4K 1 787 #define ARR_SIZE_8K 2 788 #define ARR_SIZE_16K 3 789 #define ARR_SIZE_32K 4 790 #define ARR_SIZE_64K 5 791 #define ARR_SIZE_128K 6 792 #define ARR_SIZE_256K 7 793 #define ARR_SIZE_512K 8 794 #define ARR_SIZE_1M 9 795 #define ARR_SIZE_2M 10 796 #define ARR_SIZE_4M 11 797 #define ARR_SIZE_8M 12 798 #define ARR_SIZE_16M 13 799 #define ARR_SIZE_32M 14 800 #define ARR_SIZE_4G 15 801 802 /* 803 * The region control registers specify the attributes associated with 804 * the ARRx addres regions. 805 */ 806 #define RCR0 0xdc 807 #define RCR1 0xdd 808 #define RCR2 0xde 809 #define RCR3 0xdf 810 #define RCR4 0xe0 811 #define RCR5 0xe1 812 #define RCR6 0xe2 813 #define RCR7 0xe3 814 815 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 816 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 817 #define RCR_WWO 0x02 /* Weak write ordering. */ 818 #define RCR_WL 0x04 /* Weak locking. */ 819 #define RCR_WG 0x08 /* Write gathering. */ 820 #define RCR_WT 0x10 /* Write-through. */ 821 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 822 823 /* AMD Write Allocate Top-Of-Memory and Control Register */ 824 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 825 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 826 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 827 828 /* 829 * x86_64 MSR's 830 */ 831 #define MSR_EFER 0xc0000080 /* Extended Feature Enable Register */ 832 #define EFER_SCE 0x00000001 /* System Call Extensions (R/W) */ 833 #define EFER_LME 0x00000100 /* Long Mode Enable (R/W) */ 834 #define EFER_LMA 0x00000400 /* Long Mode Active (R) */ 835 #define EFER_NXE 0x00000800 /* PTE No-Execute Enable (R/W) */ 836 #define EFER_SVME 0x00001000 /* SVM Enable (R/W) */ 837 #define EFER_LMSLE 0x00002000 /* Long Mode Segment Limit Enable */ 838 #define EFER_FFXSR 0x00004000 /* Fast FXSAVE/FXRSTOR Enable */ 839 #define EFER_TCE 0x00008000 /* Translation Cache Extension */ 840 #define EFER_MCOMMIT 0x00020000 /* MCOMMIT Enable */ 841 #define EFER_INTWB 0x00040000 /* Intr WBINVD/WBNOINVD Enable */ 842 843 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 844 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 845 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 846 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 847 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 848 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 849 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 850 #define MSR_TSC_AUX 0xc0000103 /* TSC_AUX register (for rdtscp) */ 851 #define MSR_PERFEVSEL0 0xc0010000 852 #define MSR_PERFEVSEL1 0xc0010001 853 #define MSR_PERFEVSEL2 0xc0010002 854 #define MSR_PERFEVSEL3 0xc0010003 855 #define MSR_K7_PERFCTR0 0xc0010004 856 #define MSR_K7_PERFCTR1 0xc0010005 857 #define MSR_K7_PERFCTR2 0xc0010006 858 #define MSR_K7_PERFCTR3 0xc0010007 859 #define MSR_SYSCFG 0xc0010010 860 #define MSR_IORRBASE0 0xc0010016 861 #define MSR_IORRMASK0 0xc0010017 862 #define MSR_IORRBASE1 0xc0010018 863 #define MSR_IORRMASK1 0xc0010019 864 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 865 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 866 867 #define MSR_AMD_NB_CFG 0xc001001f /* Northbridge Configuration */ 868 #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) 869 870 #define MSR_AMD_PATCH_LEVEL 0x0000008b 871 #define MSR_AMD_PATCH_LOADER 0xc0010020 /* update microcode */ 872 873 #define MSR_AMD_VM_CR 0xc0010114 /* SVM: feature control */ 874 #define VM_CR_DPD 0x00000001 /* Debug Port Disable */ 875 #define VM_CR_R_INIT 0x00000002 /* Intercept INIT signals */ 876 #define VM_CR_DIS_A20M 0x00000004 /* Disable A20 masking */ 877 #define VM_CR_LOCK 0x00000008 /* SVM Lock */ 878 #define VM_CR_SVMDIS 0x00000010 /* SVM Disable */ 879 880 #define MSR_AMD_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */ 881 #define MSR_AMD_LS_CFG 0xc0011020 /* Load-Store Configuration */ 882 #define MSR_AMD_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ 883 #define MSR_AMD_DE_CFG 0xc0011029 /* Decode Configuration */ 884 885 /* VIA ACE crypto featureset: for via_feature_rng */ 886 #define VIA_HAS_RNG 1 /* cpu has RNG */ 887 888 /* VIA ACE crypto featureset: for via_feature_xcrypt */ 889 #define VIA_HAS_AES 1 /* cpu has AES */ 890 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 891 #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 892 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 893 894 /* Centaur Extended Feature flags */ 895 #define VIA_CPUID_HAS_RNG 0x000004 896 #define VIA_CPUID_DO_RNG 0x000008 897 #define VIA_CPUID_HAS_ACE 0x000040 898 #define VIA_CPUID_DO_ACE 0x000080 899 #define VIA_CPUID_HAS_ACE2 0x000100 900 #define VIA_CPUID_DO_ACE2 0x000200 901 #define VIA_CPUID_HAS_PHE 0x000400 902 #define VIA_CPUID_DO_PHE 0x000800 903 #define VIA_CPUID_HAS_PMM 0x001000 904 #define VIA_CPUID_DO_PMM 0x002000 905 906 #endif /* !_CPU_SPECIALREG_H_ */ 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