1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 31 * $FreeBSD: src/sys/amd64/include/specialreg.h,v 1.39 2007/05/31 11:26:44 des Exp $ 32 */ 33 34 #ifndef _CPU_SPECIALREG_H_ 35 #define _CPU_SPECIALREG_H_ 36 37 /* 38 * Bits in 386 special registers: 39 */ 40 #define CR0_PE 0x00000001 /* Protected mode Enable */ 41 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 42 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 43 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 44 #define CR0_PG 0x80000000 /* Paging enable */ 45 46 /* 47 * Bits in 486 special registers: 48 */ 49 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 50 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in all modes) */ 51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52 #define CR0_NW 0x20000000 /* Not Write-through */ 53 #define CR0_CD 0x40000000 /* Cache Disable */ 54 55 /* 56 * Bits in CR4 special register 57 */ 58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60 #define CR4_TSD 0x00000004 /* Time stamp disable */ 61 #define CR4_DE 0x00000008 /* Debugging extensions */ 62 #define CR4_PSE 0x00000010 /* Page size extensions */ 63 #define CR4_PAE 0x00000020 /* Physical address extension */ 64 #define CR4_MCE 0x00000040 /* Machine check enable */ 65 #define CR4_PGE 0x00000080 /* Page global enable */ 66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68 #define CR4_XMM 0x00000400 /* Enable SIMD/MMX2 to use except 16 */ 69 #define CR4_VMXE 0x00002000 /* Enables VMX - Intel specific */ 70 #define CR4_XSAVE 0x00040000 /* Enable XSave (for AVX Instructions)*/ 71 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevent */ 72 #define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Prevent */ 73 #define CR4_PKE 0x00400000 /* Protection Keys Enable */ 74 75 76 /* 77 * Bits in x86_64 special registers. EFER is 64 bits wide. 78 */ 79 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 80 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 81 #define EFER_LMA 0x000000400 /* Long mode active (R) */ 82 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 83 #define EFER_SVME 0x000001000 /* SVM Enable (R/W) */ 84 85 /* 86 * CPUID instruction features register 87 */ 88 #define CPUID_FPU 0x00000001 89 #define CPUID_VME 0x00000002 90 #define CPUID_DE 0x00000004 91 #define CPUID_PSE 0x00000008 92 #define CPUID_TSC 0x00000010 93 #define CPUID_MSR 0x00000020 94 #define CPUID_PAE 0x00000040 95 #define CPUID_MCE 0x00000080 96 #define CPUID_CX8 0x00000100 97 #define CPUID_APIC 0x00000200 98 #define CPUID_B10 0x00000400 99 #define CPUID_SEP 0x00000800 100 #define CPUID_MTRR 0x00001000 101 #define CPUID_PGE 0x00002000 102 #define CPUID_MCA 0x00004000 103 #define CPUID_CMOV 0x00008000 104 #define CPUID_PAT 0x00010000 105 #define CPUID_PSE36 0x00020000 106 #define CPUID_PSN 0x00040000 107 #define CPUID_CLFSH 0x00080000 108 #define CPUID_B20 0x00100000 109 #define CPUID_DS 0x00200000 110 #define CPUID_ACPI 0x00400000 111 #define CPUID_MMX 0x00800000 112 #define CPUID_FXSR 0x01000000 113 #define CPUID_SSE 0x02000000 114 #define CPUID_XMM 0x02000000 115 #define CPUID_SSE2 0x04000000 116 #define CPUID_SS 0x08000000 117 #define CPUID_HTT 0x10000000 118 #define CPUID_TM 0x20000000 119 #define CPUID_IA64 0x40000000 120 #define CPUID_PBE 0x80000000 121 122 #define CPUID2_SSE3 0x00000001 123 #define CPUID2_PCLMULQDQ 0x00000002 124 #define CPUID2_DTES64 0x00000004 125 #define CPUID2_MON 0x00000008 126 #define CPUID2_DS_CPL 0x00000010 127 #define CPUID2_VMX 0x00000020 128 #define CPUID2_SMX 0x00000040 129 #define CPUID2_EST 0x00000080 130 #define CPUID2_TM2 0x00000100 131 #define CPUID2_SSSE3 0x00000200 132 #define CPUID2_CNXTID 0x00000400 133 #define CPUID2_CX16 0x00002000 134 #define CPUID2_XTPR 0x00004000 135 #define CPUID2_PDCM 0x00008000 136 #define CPUID2_DCA 0x00040000 137 #define CPUID2_SSE41 0x00080000 138 #define CPUID2_SSE42 0x00100000 139 #define CPUID2_X2APIC 0x00200000 140 #define CPUID2_POPCNT 0x00800000 141 #define CPUID2_TSCDLT 0x01000000 /* LAPIC TSC-Deadline Mode support */ 142 #define CPUID2_AESNI 0x02000000 /* AES Instruction Set */ 143 #define CPUID2_XSAVE 0x04000000 /* XSave supported by CPU */ 144 #define CPUID2_OSXSAVE 0x08000000 /* XSave and AVX supported by OS */ 145 #define CPUID2_AVX 0x10000000 /* AVX instruction set support */ 146 #define CPUID2_F16C 0x20000000 /* CVT16 instruction set support */ 147 #define CPUID2_RDRAND 0x40000000 /* RdRand. On chip random numbers */ 148 #define CPUID2_VMM 0x80000000 /* AMD 25481 2.34 page 11 */ 149 150 /*Bits related to the XFEATURE_ENABLED_MASK control register*/ 151 #define CPU_XFEATURE_X87 0x00000001 152 #define CPU_XFEATURE_SSE 0x00000002 153 #define CPU_XFEATURE_YMM 0x00000004 154 155 /* 156 * Important bits in the AMD extended cpuid flags 157 */ 158 #define AMDID_SYSCALL 0x00000800 159 #define AMDID_MP 0x00080000 160 #define AMDID_NX 0x00100000 161 #define AMDID_EXT_MMX 0x00400000 162 #define AMDID_FFXSR 0x01000000 163 #define AMDID_PAGE1GB 0x04000000 164 #define AMDID_RDTSCP 0x08000000 165 #define AMDID_LM 0x20000000 166 #define AMDID_EXT_3DNOW 0x40000000 167 #define AMDID_3DNOW 0x80000000 168 169 #define AMDID2_LAHF 0x00000001 170 #define AMDID2_CMP 0x00000002 171 #define AMDID2_SVM 0x00000004 172 #define AMDID2_EXT_APIC 0x00000008 173 #define AMDID2_CR8 0x00000010 174 #define AMDID2_ABM 0x00000020 175 #define AMDID2_SSE4A 0x00000040 176 #define AMDID2_MAS 0x00000080 177 #define AMDID2_PREFETCH 0x00000100 178 #define AMDID2_OSVW 0x00000200 179 #define AMDID2_IBS 0x00000400 180 #define AMDID2_SSE5 0x00000800 181 #define AMDID2_SKINIT 0x00001000 182 #define AMDID2_WDT 0x00002000 183 #define AMDID2_TOPOEXT 0x00400000 184 185 /* 186 * CPUID instruction 1 eax info 187 */ 188 #define CPUID_STEPPING 0x0000000f 189 #define CPUID_MODEL 0x000000f0 190 #define CPUID_FAMILY 0x00000f00 191 #define CPUID_EXT_MODEL 0x000f0000 192 #define CPUID_EXT_FAMILY 0x0ff00000 193 #define CPUID_TO_MODEL(id) \ 194 ((((id) & CPUID_MODEL) >> 4) | \ 195 (((id) & CPUID_EXT_MODEL) >> 12)) 196 #define CPUID_TO_FAMILY(id) \ 197 ((((id) & CPUID_FAMILY) >> 8) + \ 198 (((id) & CPUID_EXT_FAMILY) >> 20)) 199 200 /* 201 * CPUID instruction 1 ebx info 202 */ 203 #define CPUID_BRAND_INDEX 0x000000ff 204 #define CPUID_CLFUSH_SIZE 0x0000ff00 205 #define CPUID_HTT_CORES 0x00ff0000 206 #define CPUID_HTT_CORE_SHIFT 16 207 #define CPUID_LOCAL_APIC_ID 0xff000000 208 209 /* 210 * AMD extended function 8000_0007h edx info 211 */ 212 #define AMDPM_TS 0x00000001 213 #define AMDPM_FID 0x00000002 214 #define AMDPM_VID 0x00000004 215 #define AMDPM_TTP 0x00000008 216 #define AMDPM_TM 0x00000010 217 #define AMDPM_STC 0x00000020 218 #define AMDPM_100MHZ_STEPS 0x00000040 219 #define AMDPM_HW_PSTATE 0x00000080 220 #define AMDPM_TSC_INVARIANT 0x00000100 221 #define AMDPM_CPB 0x00000200 222 223 /* 224 * AMD extended function 8000_0008h ecx info 225 */ 226 #define AMDID_CMP_CORES 0x000000ff 227 #define AMDID_COREID_SIZE 0x0000f000 228 #define AMDID_COREID_SIZE_SHIFT 12 229 230 /* 231 * INTEL Deterministic Cache Parameters 232 * (Function 04h) 233 */ 234 #define FUNC_4_MAX_CORE_NO(eax) ((((eax) >> 26) & 0x3f)) 235 236 /* 237 * INTEL x2APIC Features / Processor topology 238 * (Function 0Bh) 239 */ 240 #define FUNC_B_THREAD_LEVEL 0 241 242 #define FUNC_B_INVALID_TYPE 0 243 #define FUNC_B_THREAD_TYPE 1 244 #define FUNC_B_CORE_TYPE 2 245 246 #define FUNC_B_TYPE(ecx) (((ecx) >> 8) & 0xff) 247 #define FUNC_B_BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) 248 #define FUNC_B_LEVEL_MAX_SIBLINGS(ebx) ((ebx) & 0xffff) 249 250 /* 251 * Structured Extended Features 252 */ 253 /* EBX */ 254 #define CPUID_STDEXT_FSGSBASE 0x00000001 255 #define CPUID_STDEXT_TSC_ADJUST 0x00000002 256 #define CPUID_STDEXT_BMI1 0x00000008 257 #define CPUID_STDEXT_HLE 0x00000010 258 #define CPUID_STDEXT_AVX2 0x00000020 259 #define CPUID_STDEXT_SMEP 0x00000080 260 #define CPUID_STDEXT_BMI2 0x00000100 261 #define CPUID_STDEXT_ENH_MOVSB 0x00000200 262 #define CPUID_STDEXT_RTM 0x00000800 263 #define CPUID_STDEXT_INVPCID 0x00000400 264 #define CPUID_STDEXT_RDSEED 0x00040000 265 #define CPUID_STDEXT_ADX 0x00080000 266 #define CPUID_STDEXT_SMAP 0x00100000 267 268 /* ECX */ 269 #define CPUID_STDEXT2_RDPID 0x00400000 270 271 /* 272 * Thermal and PM Features 273 */ 274 #define CPUID_THERMAL_SENSOR 0x00000001 275 #define CPUID_THERMAL_TURBO 0x00000002 276 #define CPUID_THERMAL_ARAT 0x00000004 277 #define CPUID_THERMAL_PLN 0x00000010 278 #define CPUID_THERMAL_ECMD 0x00000020 279 #define CPUID_THERMAL_PTM 0x00000040 280 #define CPUID_THERMAL_HWP 0x00000080 /* Hardware P-states */ 281 282 #define CPUID_THERMAL2_SETBH 0x00000008 283 284 /* 285 * MONITOR/MWAIT 286 */ 287 #define CPUID_MWAIT_EXT 0x00000001 288 #define CPUID_MWAIT_INTBRK 0x00000002 289 #define CPUID_MWAIT_CX_SUBCNT(emu, i) (((emu) >> ((i) * 4)) & 0xf) 290 291 /* MWAIT EAX to Cx and its sub state */ 292 #define MWAIT_EAX_TO_CX(x) ((((x) >> 4) + 1) & 0xf) 293 #define MWAIT_EAX_TO_CX_SUB(x) ((x) & 0xf) 294 295 /* MWAIT EAX hint and ECX extension */ 296 #define MWAIT_EAX_HINT(cx, sub) \ 297 (((((uint32_t)(cx) - 1) & 0xf) << 4) | ((sub) & 0xf)) 298 #define MWAIT_ECX_INTBRK 0x1 299 300 /* 301 * CPUID manufacturers identifiers 302 */ 303 #define AMD_VENDOR_ID "AuthenticAMD" 304 #define CENTAUR_VENDOR_ID "CentaurHauls" 305 #define INTEL_VENDOR_ID "GenuineIntel" 306 307 /* 308 * Model-specific registers for the i386 family 309 */ 310 #define MSR_P5_MC_ADDR 0x000 311 #define MSR_P5_MC_TYPE 0x001 312 #define MSR_TSC 0x010 313 #define MSR_P5_CESR 0x011 314 #define MSR_P5_CTR0 0x012 315 #define MSR_P5_CTR1 0x013 316 #define MSR_IA32_PLATFORM_ID 0x017 317 #define MSR_APICBASE 0x01b 318 #define MSR_EBL_CR_POWERON 0x02a 319 #define MSR_TEST_CTL 0x033 320 #define MSR_SPEC_CTRL 0x048 /* IBRS Spectre mitigation */ 321 #define MSR_PRED_CMD 0x049 /* IBPB Spectre mitigation */ 322 #define MSR_BIOS_UPDT_TRIG 0x079 323 #define MSR_BBL_CR_D0 0x088 324 #define MSR_BBL_CR_D1 0x089 325 #define MSR_BBL_CR_D2 0x08a 326 #define MSR_BIOS_SIGN 0x08b 327 #define MSR_PERFCTR0 0x0c1 328 #define MSR_PERFCTR1 0x0c2 329 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 330 #define MSR_MTRRcap 0x0fe 331 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 332 #define MSR_BBL_CR_ADDR 0x116 333 #define MSR_BBL_CR_DECC 0x118 334 #define MSR_BBL_CR_CTL 0x119 335 #define MSR_BBL_CR_TRIG 0x11a 336 #define MSR_BBL_CR_BUSY 0x11b 337 #define MSR_BBL_CR_CTL3 0x11e 338 #define MSR_SYSENTER_CS_MSR 0x174 339 #define MSR_SYSENTER_ESP_MSR 0x175 340 #define MSR_SYSENTER_EIP_MSR 0x176 341 #define MSR_MCG_CAP 0x179 342 #define MSR_MCG_STATUS 0x17a 343 #define MSR_MCG_CTL 0x17b 344 #define MSR_EVNTSEL0 0x186 345 #define MSR_EVNTSEL1 0x187 346 #define MSR_THERM_CONTROL 0x19a 347 #define MSR_THERM_INTERRUPT 0x19b 348 #define MSR_THERM_STATUS 0x19c 349 #define MSR_IA32_MISC_ENABLE 0x1a0 350 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 351 #define MSR_PKG_THERM_STATUS 0x1b1 352 #define MSR_PKG_THERM_INTR 0x1b2 353 #define MSR_DEBUGCTLMSR 0x1d9 354 #define MSR_LASTBRANCHFROMIP 0x1db 355 #define MSR_LASTBRANCHTOIP 0x1dc 356 #define MSR_LASTINTFROMIP 0x1dd 357 #define MSR_LASTINTTOIP 0x1de 358 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 359 #define MSR_MTRRVarBase 0x200 360 #define MSR_MTRR64kBase 0x250 361 #define MSR_MTRR16kBase 0x258 362 #define MSR_MTRR4kBase 0x268 363 #define MSR_PAT 0x277 364 #define MSR_MTRRdefType 0x2ff 365 #define MSR_MC0_CTL 0x400 366 #define MSR_MC0_STATUS 0x401 367 #define MSR_MC0_ADDR 0x402 368 #define MSR_MC0_MISC 0x403 369 #define MSR_MC1_CTL 0x404 370 #define MSR_MC1_STATUS 0x405 371 #define MSR_MC1_ADDR 0x406 372 #define MSR_MC1_MISC 0x407 373 #define MSR_MC2_CTL 0x408 374 #define MSR_MC2_STATUS 0x409 375 #define MSR_MC2_ADDR 0x40a 376 #define MSR_MC2_MISC 0x40b 377 #define MSR_MC3_CTL 0x40c 378 #define MSR_MC3_STATUS 0x40d 379 #define MSR_MC3_ADDR 0x40e 380 #define MSR_MC3_MISC 0x40f 381 #define MSR_MC4_CTL 0x410 382 #define MSR_MC4_STATUS 0x411 383 #define MSR_MC4_ADDR 0x412 384 #define MSR_MC4_MISC 0x413 385 #define MSR_RAPL_POWER_UNIT 0x606 386 #define MSR_PKG_ENERGY_STATUS 0x611 387 #define MSR_DRAM_ENERGY_STATUS 0x619 388 #define MSR_PP0_ENERGY_STATUS 0x639 389 #define MSR_PP1_ENERGY_STATUS 0x641 390 #define MSR_PLATFORM_ENERGY_COUNTER 0x64d /* Skylake and later */ 391 392 /* 393 * Constants related to MSR's. 394 */ 395 #define APICBASE_RESERVED 0x000006ff 396 #define APICBASE_BSP 0x00000100 397 #define APICBASE_X2APIC 0x00000400 398 #define APICBASE_ENABLED 0x00000800 399 #define APICBASE_ADDRESS 0xfffff000 400 401 /* 402 * IBRS and IBPB Spectre mitigation 403 * 404 * Intel: Either CPUID_80000008_I1_IBPB_SUPPORT or CPUID_7_0_I3_SPEC_CTRL 405 * indicates IBPB support. However, note that MSR_PRED_CMD is 406 * a command register that may only be written, not read. 407 * 408 * IBPB: (barrier) 409 * $1 is written to MSR_PRED_CMD unconditionally, writing 0 410 * has no effect. 411 * 412 * IBRS and STIBP 413 * Serves as barrier and mode, set on entry to kernel and clear 414 * on exit. Be sure to clear before going idle (else hyperthread 415 * performance will drop). 416 */ 417 418 #define CPUID_7_0_I3_SPEC_CTRL 0x04000000 /* in EDX (index 3) */ 419 #define CPUID_7_0_I3_STIBP 0x08000000 /* in EDX (index 3) */ 420 421 #define SPEC_CTRL_IBRS 0x00000001 422 #define SPEC_CTRL_STIBP 0x00000002 423 #define SPEC_CTRL_DUMMY1 0x00010000 /* ficticious */ 424 #define SPEC_CTRL_DUMMY2 0x00020000 /* ficticious */ 425 #define SPEC_CTRL_DUMMY3 0x00040000 /* ficticious */ 426 #define SPEC_CTRL_DUMMY4 0x00080000 /* ficticious */ 427 #define SPEC_CTRL_DUMMY5 0x00100000 /* ficticious */ 428 #define SPEC_CTRL_DUMMY6 0x00200000 /* ficticious */ 429 430 /* 431 * In EBX (index 1) 432 */ 433 #define CPUID_INTEL_80000008_I1_IBPB_SUPPORT 0x00001000 434 435 #define CPUID_AMD_80000008_I1_IBPB_SUPPORT 0x00001000 436 #define CPUID_AMD_80000008_I1_IBRS_SUPPORT 0x00004000 437 #define CPUID_AMD_80000008_I1_STIBP_SUPPORT 0x00008000 438 439 #define CPUID_AMD_80000008_I1_IBRS_AUTO 0x00010000 440 #define CPUID_AMD_80000008_I1_STIBP_AUTO 0x00020000 441 #define CPUID_AMD_80000008_I1_IBRS_REQUESTED 0x00040000 442 443 /* 444 * MDS mitigation in microcode (Intel only) in EDX (index 3) 445 */ 446 #define CPUID_SEF_AVX512_4VNNIW 0x00000004 447 #define CPUID_SEF_AVX512_4FMAPS 0x00000008 448 #define CPUID_SEF_MD_CLEAR 0x00000400 449 #define CPUID_SEF_TSX_FORCE_ABORT 0x00002000 450 451 #define CPUID_SEF_ARCH_CAP 0x20000000 452 453 /* 454 * MSR_IA32_ARCH_CAPABILITIES 455 */ 456 #define IA32_ARCH_CAP_RDCL_NO 0x00000001 457 #define IA32_ARCH_CAP_IBRS_ALL 0x00000002 458 #define IA32_ARCH_CAP_RSBA 0x00000004 459 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008 460 #define IA32_ARCH_SSB_NO 0x00000010 461 #define IA32_ARCH_MDS_NO 0x00000020 462 #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x00000040 463 #define IA32_ARCH_CAP_TSX_CTRL 0x00000080 464 #define IA32_ARCH_CAP_TAA_NO 0x00000100 465 466 /* 467 * PAT modes. 468 */ 469 #define PAT_UNCACHEABLE 0x00 470 #define PAT_WRITE_COMBINING 0x01 471 #define PAT_WRITE_THROUGH 0x04 472 #define PAT_WRITE_PROTECTED 0x05 473 #define PAT_WRITE_BACK 0x06 474 #define PAT_UNCACHED 0x07 475 #define PAT_VALUE(i, m) ((long)(m) << (8 * (i))) 476 #define PAT_MASK(i) PAT_VALUE(i, 0xff) 477 478 /* 479 * Constants related to MTRRs 480 */ 481 #define MTRR_UNCACHEABLE 0x00 482 #define MTRR_WRITE_COMBINING 0x01 483 #define MTRR_WRITE_THROUGH 0x04 484 #define MTRR_WRITE_PROTECTED 0x05 485 #define MTRR_WRITE_BACK 0x06 486 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 487 #define MTRR_N16K 16 488 #define MTRR_N4K 64 489 #define MTRR_CAP_WC 0x0000000000000400UL 490 #define MTRR_CAP_FIXED 0x0000000000000100UL 491 #define MTRR_CAP_VCNT 0x00000000000000ffUL 492 #define MTRR_DEF_ENABLE 0x0000000000000800UL 493 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400UL 494 #define MTRR_DEF_TYPE 0x00000000000000ffUL 495 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000UL 496 #define MTRR_PHYSBASE_TYPE 0x00000000000000ffUL 497 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000UL 498 #define MTRR_PHYSMASK_VALID 0x0000000000000800UL 499 500 /* Performance Control Register (5x86 only). */ 501 #define PCR0 0x20 502 #define PCR0_RSTK 0x01 /* Enables return stack */ 503 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 504 #define PCR0_LOOP 0x04 /* Enables loop */ 505 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 506 serialize pipe. */ 507 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 508 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 509 #define PCR0_LSSER 0x80 /* Disable reorder */ 510 511 /* Device Identification Registers */ 512 #define DIR0 0xfe 513 #define DIR1 0xff 514 515 /* 516 * Machine Check register constants. 517 */ 518 #define MCG_CAP_COUNT 0x000000ff 519 #define MCG_CAP_CTL_P 0x00000100 520 #define MCG_CAP_EXT_P 0x00000200 521 #define MCG_CAP_TES_P 0x00000800 522 #define MCG_CAP_EXT_CNT 0x00ff0000 523 #define MCG_STATUS_RIPV 0x00000001 524 #define MCG_STATUS_EIPV 0x00000002 525 #define MCG_STATUS_MCIP 0x00000004 526 #define MCG_CTL_ENABLE 0xffffffffffffffffUL 527 #define MCG_CTL_DISABLE 0x0000000000000000UL 528 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 529 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 530 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 531 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 532 #define MC_STATUS_MCA_ERROR 0x000000000000ffffUL 533 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000UL 534 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000UL 535 #define MC_STATUS_PCC 0x0200000000000000UL 536 #define MC_STATUS_ADDRV 0x0400000000000000UL 537 #define MC_STATUS_MISCV 0x0800000000000000UL 538 #define MC_STATUS_EN 0x1000000000000000UL 539 #define MC_STATUS_UC 0x2000000000000000UL 540 #define MC_STATUS_OVER 0x4000000000000000UL 541 #define MC_STATUS_VAL 0x8000000000000000UL 542 543 /* 544 * The following four 3-byte registers control the non-cacheable regions. 545 * These registers must be written as three separate bytes. 546 * 547 * NCRx+0: A31-A24 of starting address 548 * NCRx+1: A23-A16 of starting address 549 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 550 * 551 * The non-cacheable region's starting address must be aligned to the 552 * size indicated by the NCR_SIZE_xx field. 553 */ 554 #define NCR1 0xc4 555 #define NCR2 0xc7 556 #define NCR3 0xca 557 #define NCR4 0xcd 558 559 #define NCR_SIZE_0K 0 560 #define NCR_SIZE_4K 1 561 #define NCR_SIZE_8K 2 562 #define NCR_SIZE_16K 3 563 #define NCR_SIZE_32K 4 564 #define NCR_SIZE_64K 5 565 #define NCR_SIZE_128K 6 566 #define NCR_SIZE_256K 7 567 #define NCR_SIZE_512K 8 568 #define NCR_SIZE_1M 9 569 #define NCR_SIZE_2M 10 570 #define NCR_SIZE_4M 11 571 #define NCR_SIZE_8M 12 572 #define NCR_SIZE_16M 13 573 #define NCR_SIZE_32M 14 574 #define NCR_SIZE_4G 15 575 576 /* 577 * The address region registers are used to specify the location and 578 * size for the eight address regions. 579 * 580 * ARRx + 0: A31-A24 of start address 581 * ARRx + 1: A23-A16 of start address 582 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 583 */ 584 #define ARR0 0xc4 585 #define ARR1 0xc7 586 #define ARR2 0xca 587 #define ARR3 0xcd 588 #define ARR4 0xd0 589 #define ARR5 0xd3 590 #define ARR6 0xd6 591 #define ARR7 0xd9 592 593 #define ARR_SIZE_0K 0 594 #define ARR_SIZE_4K 1 595 #define ARR_SIZE_8K 2 596 #define ARR_SIZE_16K 3 597 #define ARR_SIZE_32K 4 598 #define ARR_SIZE_64K 5 599 #define ARR_SIZE_128K 6 600 #define ARR_SIZE_256K 7 601 #define ARR_SIZE_512K 8 602 #define ARR_SIZE_1M 9 603 #define ARR_SIZE_2M 10 604 #define ARR_SIZE_4M 11 605 #define ARR_SIZE_8M 12 606 #define ARR_SIZE_16M 13 607 #define ARR_SIZE_32M 14 608 #define ARR_SIZE_4G 15 609 610 /* 611 * The region control registers specify the attributes associated with 612 * the ARRx addres regions. 613 */ 614 #define RCR0 0xdc 615 #define RCR1 0xdd 616 #define RCR2 0xde 617 #define RCR3 0xdf 618 #define RCR4 0xe0 619 #define RCR5 0xe1 620 #define RCR6 0xe2 621 #define RCR7 0xe3 622 623 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 624 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 625 #define RCR_WWO 0x02 /* Weak write ordering. */ 626 #define RCR_WL 0x04 /* Weak locking. */ 627 #define RCR_WG 0x08 /* Write gathering. */ 628 #define RCR_WT 0x10 /* Write-through. */ 629 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 630 631 /* AMD Write Allocate Top-Of-Memory and Control Register */ 632 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 633 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 634 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 635 636 /* x86_64 MSR's */ 637 #define MSR_EFER 0xc0000080 /* extended features */ 638 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 639 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 640 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 641 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 642 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 643 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 644 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 645 #define MSR_TSCAUX 0xc0000103 /* TSC_AUX register (for rdtscp) */ 646 #define MSR_PERFEVSEL0 0xc0010000 647 #define MSR_PERFEVSEL1 0xc0010001 648 #define MSR_PERFEVSEL2 0xc0010002 649 #define MSR_PERFEVSEL3 0xc0010003 650 #undef MSR_PERFCTR0 651 #undef MSR_PERFCTR1 652 #define MSR_PERFCTR0 0xc0010004 653 #define MSR_PERFCTR1 0xc0010005 654 #define MSR_PERFCTR2 0xc0010006 655 #define MSR_PERFCTR3 0xc0010007 656 #define MSR_SYSCFG 0xc0010010 657 #define MSR_IORRBASE0 0xc0010016 658 #define MSR_IORRMASK0 0xc0010017 659 #define MSR_IORRBASE1 0xc0010018 660 #define MSR_IORRMASK1 0xc0010019 661 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 662 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 663 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 664 665 /* AMD MSRs */ 666 #define MSR_AMD_DE_CFG 0xc0011029 667 668 /* AMD SVM MSRs */ 669 #define MSR_AMD_VM_CR 0xc0010114 670 #define MSR_AMD_VM_HSAVE_PA 0xc0010117 671 672 /* AMD MSR_AMD_VM_CR fields */ 673 #define MSR_AMD_VM_CR_SVMDIS 0x00000010 /* SVM Disabled */ 674 675 /* VIA ACE crypto featureset: for via_feature_rng */ 676 #define VIA_HAS_RNG 1 /* cpu has RNG */ 677 678 /* VIA ACE crypto featureset: for via_feature_xcrypt */ 679 #define VIA_HAS_AES 1 /* cpu has AES */ 680 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 681 #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 682 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 683 684 /* Centaur Extended Feature flags */ 685 #define VIA_CPUID_HAS_RNG 0x000004 686 #define VIA_CPUID_DO_RNG 0x000008 687 #define VIA_CPUID_HAS_ACE 0x000040 688 #define VIA_CPUID_DO_ACE 0x000080 689 #define VIA_CPUID_HAS_ACE2 0x000100 690 #define VIA_CPUID_DO_ACE2 0x000200 691 #define VIA_CPUID_HAS_PHE 0x000400 692 #define VIA_CPUID_DO_PHE 0x000800 693 #define VIA_CPUID_HAS_PMM 0x001000 694 #define VIA_CPUID_DO_PMM 0x002000 695 696 /* Hardware P-states interface */ 697 #define MSR_PPERF 0x0000064e 698 #define MSR_PERF_LIMIT_REASONS 0x0000064f 699 #define MSR_PM_ENABLE 0x00000770 700 #define MSR_HWP_CAPABILITIES 0x00000771 701 #define MSR_HWP_REQUEST_PKG 0x00000772 702 #define MSR_HWP_INTERRUPT 0x00000773 703 #define MSR_HWP_REQUEST 0x00000774 704 #define MSR_HWP_STATUS 0x00000777 705 706 /* Local APIC TSC Deadline Mode Target count */ 707 #define MSR_TSC_DEADLINE 0x000006e0 708 709 #endif /* !_CPU_SPECIALREG_H_ */ 710