1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/acpica/acpi_cpu.c,v 1.72 2008/04/12 12:06:00 rpaulo Exp $ 28 */ 29 30 #include "opt_acpi.h" 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/malloc.h> 35 #include <sys/globaldata.h> 36 #include <sys/power.h> 37 #include <sys/proc.h> 38 #include <sys/sbuf.h> 39 #include <sys/thread2.h> 40 #include <sys/serialize.h> 41 #include <sys/msgport2.h> 42 43 #include <bus/pci/pcivar.h> 44 #include <machine/atomic.h> 45 #include <machine/globaldata.h> 46 #include <machine/md_var.h> 47 #include <machine/smp.h> 48 #include <sys/rman.h> 49 50 #include <net/netisr2.h> 51 #include <net/netmsg2.h> 52 #include <net/if_var.h> 53 54 #include "acpi.h" 55 #include "acpivar.h" 56 #include "acpi_cpu.h" 57 58 /* 59 * Support for ACPI Processor devices, including C[1-3] sleep states. 60 */ 61 62 /* Hooks for the ACPI CA debugging infrastructure */ 63 #define _COMPONENT ACPI_PROCESSOR 64 ACPI_MODULE_NAME("PROCESSOR") 65 66 struct netmsg_acpi_cst { 67 struct netmsg_base base; 68 struct acpi_cst_softc *sc; 69 int val; 70 }; 71 72 struct acpi_cx { 73 struct resource *p_lvlx; /* Register to read to enter state. */ 74 int rid; /* rid of p_lvlx */ 75 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 76 uint32_t trans_lat; /* Transition latency (usec). */ 77 uint32_t power; /* Power consumed (mW). */ 78 int res_type; /* Resource type for p_lvlx. */ 79 }; 80 #define MAX_CX_STATES 8 81 82 struct acpi_cst_softc { 83 device_t cst_dev; 84 struct acpi_cpux_softc *cst_parent; 85 ACPI_HANDLE cst_handle; 86 int cst_cpuid; 87 uint32_t cst_flags; /* ACPI_CST_FLAG_ */ 88 uint32_t cst_p_blk; /* ACPI P_BLK location */ 89 uint32_t cst_p_blk_len; /* P_BLK length (must be 6). */ 90 struct acpi_cx cst_cx_states[MAX_CX_STATES]; 91 int cst_cx_count; /* Number of valid Cx states. */ 92 int cst_prev_sleep;/* Last idle sleep duration. */ 93 /* Runtime state. */ 94 int cst_non_c3; /* Index of lowest non-C3 state. */ 95 u_long cst_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 96 /* Values for sysctl. */ 97 int cst_cx_lowest; /* Current Cx lowest */ 98 int cst_cx_lowest_req; /* Requested Cx lowest */ 99 char cst_cx_supported[64]; 100 }; 101 102 #define ACPI_CST_FLAG_PROBING 0x1 103 104 #define CPU_GET_REG(reg, width) \ 105 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 106 rman_get_bushandle((reg)), 0)) 107 108 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */ 109 110 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 111 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 112 113 #define PCI_VENDOR_INTEL 0x8086 114 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 115 #define PCI_REVISION_A_STEP 0 116 #define PCI_REVISION_B_STEP 1 117 #define PCI_REVISION_4E 2 118 #define PCI_REVISION_4M 3 119 #define PIIX4_DEVACTB_REG 0x58 120 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 121 #define PIIX4_BRLD_EN_IRQ (1<<1) 122 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 123 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 124 #define PIIX4_PCNTRL_BST_EN (1<<10) 125 126 /* Platform hardware resource information. */ 127 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 128 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 129 static int cpu_quirks; /* Indicate any hardware bugs. */ 130 131 /* Runtime state. */ 132 static int cpu_disable_idle; /* Disable entry to idle function */ 133 static int cpu_cx_count; /* Number of valid Cx states */ 134 135 /* Values for sysctl. */ 136 static int cpu_cx_generic; 137 static int cpu_cx_lowest; /* Current Cx lowest */ 138 static int cpu_cx_lowest_req; /* Requested Cx lowest */ 139 static struct lwkt_serialize cpu_cx_slize = LWKT_SERIALIZE_INITIALIZER; 140 141 /* C3 state transition */ 142 static int cpu_c3_ncpus; 143 144 static device_t *cpu_devices; 145 static int cpu_ndevices; 146 static struct acpi_cst_softc **cpu_softc; 147 148 static int acpi_cst_probe(device_t dev); 149 static int acpi_cst_attach(device_t dev); 150 static int acpi_cst_suspend(device_t dev); 151 static int acpi_cst_resume(device_t dev); 152 static int acpi_cst_shutdown(device_t dev); 153 154 static void acpi_cpu_cx_probe(struct acpi_cst_softc *sc); 155 static void acpi_cpu_generic_cx_probe(struct acpi_cst_softc *sc); 156 static int acpi_cpu_cx_cst(struct acpi_cst_softc *sc); 157 static int acpi_cpu_cx_cst_dispatch(struct acpi_cst_softc *sc); 158 static void acpi_cpu_startup(void *arg); 159 static void acpi_cpu_startup_cx(struct acpi_cst_softc *sc); 160 static void acpi_cpu_cx_list(struct acpi_cst_softc *sc); 161 static void acpi_cpu_idle(void); 162 static void acpi_cpu_cst_notify(device_t); 163 static int acpi_cpu_quirks(void); 164 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 165 static int acpi_cpu_set_cx_lowest(struct acpi_cst_softc *, int); 166 static int acpi_cpu_set_cx_lowest_oncpu(struct acpi_cst_softc *, int); 167 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 168 static int acpi_cpu_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS); 169 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 170 static int acpi_cpu_global_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS); 171 static void acpi_cpu_cx_non_c3(struct acpi_cst_softc *sc); 172 static void acpi_cpu_global_cx_count(void); 173 174 static void acpi_cpu_c1(void); /* XXX */ 175 176 static device_method_t acpi_cst_methods[] = { 177 /* Device interface */ 178 DEVMETHOD(device_probe, acpi_cst_probe), 179 DEVMETHOD(device_attach, acpi_cst_attach), 180 DEVMETHOD(device_detach, bus_generic_detach), 181 DEVMETHOD(device_shutdown, acpi_cst_shutdown), 182 DEVMETHOD(device_suspend, acpi_cst_suspend), 183 DEVMETHOD(device_resume, acpi_cst_resume), 184 185 /* Bus interface */ 186 DEVMETHOD(bus_add_child, bus_generic_add_child), 187 DEVMETHOD(bus_read_ivar, bus_generic_read_ivar), 188 DEVMETHOD(bus_get_resource_list, bus_generic_get_resource_list), 189 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 190 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 191 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 192 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 193 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 194 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 195 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 196 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 197 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 198 DEVMETHOD_END 199 }; 200 201 static driver_t acpi_cst_driver = { 202 "cpu_cst", 203 acpi_cst_methods, 204 sizeof(struct acpi_cst_softc), 205 }; 206 207 static devclass_t acpi_cst_devclass; 208 DRIVER_MODULE(cpu_cst, cpu, acpi_cst_driver, acpi_cst_devclass, NULL, NULL); 209 MODULE_DEPEND(cpu_cst, acpi, 1, 1, 1); 210 211 static int 212 acpi_cst_probe(device_t dev) 213 { 214 int cpu_id; 215 216 if (acpi_disabled("cpu_cst") || acpi_get_type(dev) != ACPI_TYPE_PROCESSOR) 217 return (ENXIO); 218 219 cpu_id = acpi_get_magic(dev); 220 221 if (cpu_softc == NULL) 222 cpu_softc = kmalloc(sizeof(struct acpi_cst_softc *) * 223 SMP_MAXCPU, M_TEMP /* XXX */, M_INTWAIT | M_ZERO); 224 225 /* 226 * Check if we already probed this processor. We scan the bus twice 227 * so it's possible we've already seen this one. 228 */ 229 if (cpu_softc[cpu_id] != NULL) { 230 device_printf(dev, "CPU%d cstate already exist\n", cpu_id); 231 return (ENXIO); 232 } 233 234 /* Mark this processor as in-use and save our derived id for attach. */ 235 cpu_softc[cpu_id] = (void *)1; 236 device_set_desc(dev, "ACPI CPU C-State"); 237 238 return (0); 239 } 240 241 static int 242 acpi_cst_attach(device_t dev) 243 { 244 ACPI_BUFFER buf; 245 ACPI_OBJECT *obj; 246 struct acpi_cst_softc *sc; 247 ACPI_STATUS status; 248 249 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 250 251 sc = device_get_softc(dev); 252 sc->cst_dev = dev; 253 sc->cst_parent = device_get_softc(device_get_parent(dev)); 254 sc->cst_handle = acpi_get_handle(dev); 255 sc->cst_cpuid = acpi_get_magic(dev); 256 cpu_softc[sc->cst_cpuid] = sc; 257 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 258 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 259 260 buf.Pointer = NULL; 261 buf.Length = ACPI_ALLOCATE_BUFFER; 262 status = AcpiEvaluateObject(sc->cst_handle, NULL, NULL, &buf); 263 if (ACPI_FAILURE(status)) { 264 device_printf(dev, "attach failed to get Processor obj - %s\n", 265 AcpiFormatException(status)); 266 return (ENXIO); 267 } 268 obj = (ACPI_OBJECT *)buf.Pointer; 269 sc->cst_p_blk = obj->Processor.PblkAddress; 270 sc->cst_p_blk_len = obj->Processor.PblkLength; 271 AcpiOsFree(obj); 272 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 273 device_get_unit(dev), sc->cst_p_blk, sc->cst_p_blk_len)); 274 275 /* 276 * If this is the first cpu we attach, create and initialize the generic 277 * resources that will be used by all acpi cpu devices. 278 */ 279 if (device_get_unit(dev) == 0) { 280 /* Assume we won't be using generic Cx mode by default */ 281 cpu_cx_generic = FALSE; 282 283 /* Queue post cpu-probing task handler */ 284 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 285 } 286 287 /* Probe for Cx state support. */ 288 acpi_cpu_cx_probe(sc); 289 290 /* Finally, call identify and probe/attach for child devices. */ 291 bus_generic_probe(dev); 292 bus_generic_attach(dev); 293 294 return (0); 295 } 296 297 /* 298 * Disable any entry to the idle function during suspend and re-enable it 299 * during resume. 300 */ 301 static int 302 acpi_cst_suspend(device_t dev) 303 { 304 int error; 305 306 error = bus_generic_suspend(dev); 307 if (error) 308 return (error); 309 cpu_disable_idle = TRUE; 310 return (0); 311 } 312 313 static int 314 acpi_cst_resume(device_t dev) 315 { 316 317 cpu_disable_idle = FALSE; 318 return (bus_generic_resume(dev)); 319 } 320 321 static int 322 acpi_cst_shutdown(device_t dev) 323 { 324 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 325 326 /* Allow children to shutdown first. */ 327 bus_generic_shutdown(dev); 328 329 /* 330 * Disable any entry to the idle function. There is a small race where 331 * an idle thread have passed this check but not gone to sleep. This 332 * is ok since device_shutdown() does not free the softc, otherwise 333 * we'd have to be sure all threads were evicted before returning. 334 */ 335 cpu_disable_idle = TRUE; 336 337 return_VALUE (0); 338 } 339 340 static void 341 acpi_cpu_cx_probe(struct acpi_cst_softc *sc) 342 { 343 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 344 345 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 346 sc->cst_prev_sleep = 1000000; 347 sc->cst_cx_lowest = 0; 348 sc->cst_cx_lowest_req = 0; 349 350 /* 351 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 352 * any, we'll revert to generic FADT/P_BLK Cx control method which will 353 * be handled by acpi_cpu_startup. We need to defer to after having 354 * probed all the cpus in the system before probing for generic Cx 355 * states as we may already have found cpus with valid _CST packages 356 */ 357 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 358 /* 359 * We were unable to find a _CST package for this cpu or there 360 * was an error parsing it. Switch back to generic mode. 361 */ 362 cpu_cx_generic = TRUE; 363 if (bootverbose) 364 device_printf(sc->cst_dev, "switching to generic Cx mode\n"); 365 } 366 367 /* 368 * TODO: _CSD Package should be checked here. 369 */ 370 } 371 372 static void 373 acpi_cpu_generic_cx_probe(struct acpi_cst_softc *sc) 374 { 375 ACPI_GENERIC_ADDRESS gas; 376 struct acpi_cx *cx_ptr; 377 378 sc->cst_cx_count = 0; 379 cx_ptr = sc->cst_cx_states; 380 381 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 382 sc->cst_prev_sleep = 1000000; 383 384 /* C1 has been required since just after ACPI 1.0 */ 385 cx_ptr->type = ACPI_STATE_C1; 386 cx_ptr->trans_lat = 0; 387 cx_ptr++; 388 sc->cst_cx_count++; 389 390 /* 391 * The spec says P_BLK must be 6 bytes long. However, some systems 392 * use it to indicate a fractional set of features present so we 393 * take 5 as C2. Some may also have a value of 7 to indicate 394 * another C3 but most use _CST for this (as required) and having 395 * "only" C1-C3 is not a hardship. 396 */ 397 if (sc->cst_p_blk_len < 5) 398 return; 399 400 /* Validate and allocate resources for C2 (P_LVL2). */ 401 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 402 gas.BitWidth = 8; 403 if (AcpiGbl_FADT.C2Latency <= 100) { 404 gas.Address = sc->cst_p_blk + 4; 405 406 cx_ptr->rid = sc->cst_parent->cpux_next_rid; 407 acpi_bus_alloc_gas(sc->cst_dev, &cx_ptr->type, &cx_ptr->rid, &gas, 408 &cx_ptr->p_lvlx, RF_SHAREABLE); 409 if (cx_ptr->p_lvlx != NULL) { 410 sc->cst_parent->cpux_next_rid++; 411 cx_ptr->type = ACPI_STATE_C2; 412 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 413 cx_ptr++; 414 sc->cst_cx_count++; 415 sc->cst_non_c3 = 1; 416 } 417 } 418 if (sc->cst_p_blk_len < 6) 419 return; 420 421 /* Validate and allocate resources for C3 (P_LVL3). */ 422 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 423 gas.Address = sc->cst_p_blk + 5; 424 425 cx_ptr->rid = sc->cst_parent->cpux_next_rid; 426 acpi_bus_alloc_gas(sc->cst_dev, &cx_ptr->type, &cx_ptr->rid, &gas, 427 &cx_ptr->p_lvlx, RF_SHAREABLE); 428 if (cx_ptr->p_lvlx != NULL) { 429 sc->cst_parent->cpux_next_rid++; 430 cx_ptr->type = ACPI_STATE_C3; 431 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 432 cx_ptr++; 433 sc->cst_cx_count++; 434 } 435 } 436 } 437 438 /* 439 * Parse a _CST package and set up its Cx states. Since the _CST object 440 * can change dynamically, our notify handler may call this function 441 * to clean up and probe the new _CST package. 442 */ 443 static int 444 acpi_cpu_cx_cst(struct acpi_cst_softc *sc) 445 { 446 struct acpi_cx *cx_ptr; 447 ACPI_STATUS status; 448 ACPI_BUFFER buf; 449 ACPI_OBJECT *top; 450 ACPI_OBJECT *pkg; 451 uint32_t count; 452 int i; 453 454 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 455 456 buf.Pointer = NULL; 457 buf.Length = ACPI_ALLOCATE_BUFFER; 458 status = AcpiEvaluateObject(sc->cst_handle, "_CST", NULL, &buf); 459 if (ACPI_FAILURE(status)) 460 return (ENXIO); 461 462 /* _CST is a package with a count and at least one Cx package. */ 463 top = (ACPI_OBJECT *)buf.Pointer; 464 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 465 device_printf(sc->cst_dev, "invalid _CST package\n"); 466 AcpiOsFree(buf.Pointer); 467 return (ENXIO); 468 } 469 if (count != top->Package.Count - 1) { 470 device_printf(sc->cst_dev, "invalid _CST state count (%d != %d)\n", 471 count, top->Package.Count - 1); 472 count = top->Package.Count - 1; 473 } 474 if (count > MAX_CX_STATES) { 475 device_printf(sc->cst_dev, "_CST has too many states (%d)\n", count); 476 count = MAX_CX_STATES; 477 } 478 479 sc->cst_flags |= ACPI_CST_FLAG_PROBING; 480 cpu_sfence(); 481 482 /* Set up all valid states. */ 483 sc->cst_cx_count = 0; 484 cx_ptr = sc->cst_cx_states; 485 for (i = 0; i < count; i++) { 486 pkg = &top->Package.Elements[i + 1]; 487 if (!ACPI_PKG_VALID(pkg, 4) || 488 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 489 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 490 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 491 492 device_printf(sc->cst_dev, "skipping invalid Cx state package\n"); 493 continue; 494 } 495 496 /* Validate the state to see if we should use it. */ 497 switch (cx_ptr->type) { 498 case ACPI_STATE_C1: 499 sc->cst_non_c3 = i; 500 cx_ptr++; 501 sc->cst_cx_count++; 502 continue; 503 case ACPI_STATE_C2: 504 sc->cst_non_c3 = i; 505 break; 506 case ACPI_STATE_C3: 507 default: 508 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 509 510 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 511 "acpi_cpu%d: C3[%d] not available.\n", 512 device_get_unit(sc->cst_dev), i)); 513 continue; 514 } 515 break; 516 } 517 518 #ifdef notyet 519 /* Free up any previous register. */ 520 if (cx_ptr->p_lvlx != NULL) { 521 bus_release_resource(sc->cst_dev, 0, 0, cx_ptr->p_lvlx); 522 cx_ptr->p_lvlx = NULL; 523 } 524 #endif 525 526 /* Allocate the control register for C2 or C3. */ 527 cx_ptr->rid = sc->cst_parent->cpux_next_rid; 528 acpi_PkgGas(sc->cst_dev, pkg, 0, &cx_ptr->res_type, &cx_ptr->rid, 529 &cx_ptr->p_lvlx, RF_SHAREABLE); 530 if (cx_ptr->p_lvlx) { 531 sc->cst_parent->cpux_next_rid++; 532 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 533 "acpi_cpu%d: Got C%d - %d latency\n", 534 device_get_unit(sc->cst_dev), cx_ptr->type, 535 cx_ptr->trans_lat)); 536 cx_ptr++; 537 sc->cst_cx_count++; 538 } 539 } 540 AcpiOsFree(buf.Pointer); 541 542 /* 543 * Fix up the lowest Cx being used 544 */ 545 if (sc->cst_cx_lowest_req < sc->cst_cx_count) 546 sc->cst_cx_lowest = sc->cst_cx_lowest_req; 547 if (sc->cst_cx_lowest > sc->cst_cx_count - 1) 548 sc->cst_cx_lowest = sc->cst_cx_count - 1; 549 550 /* 551 * Cache the lowest non-C3 state. 552 * NOTE: must after cst_cx_lowest is set. 553 */ 554 acpi_cpu_cx_non_c3(sc); 555 556 cpu_sfence(); 557 sc->cst_flags &= ~ACPI_CST_FLAG_PROBING; 558 559 return (0); 560 } 561 562 static void 563 acpi_cst_probe_handler(netmsg_t msg) 564 { 565 struct netmsg_acpi_cst *rmsg = (struct netmsg_acpi_cst *)msg; 566 int error; 567 568 error = acpi_cpu_cx_cst(rmsg->sc); 569 lwkt_replymsg(&rmsg->base.lmsg, error); 570 } 571 572 static int 573 acpi_cpu_cx_cst_dispatch(struct acpi_cst_softc *sc) 574 { 575 struct netmsg_acpi_cst msg; 576 577 netmsg_init(&msg.base, NULL, &curthread->td_msgport, MSGF_PRIORITY, 578 acpi_cst_probe_handler); 579 msg.sc = sc; 580 581 return lwkt_domsg(netisr_cpuport(sc->cst_cpuid), &msg.base.lmsg, 0); 582 } 583 584 /* 585 * Call this *after* all CPUs have been attached. 586 */ 587 static void 588 acpi_cpu_startup(void *arg) 589 { 590 struct acpi_cst_softc *sc; 591 int i; 592 593 /* Get set of CPU devices */ 594 devclass_get_devices(acpi_cst_devclass, &cpu_devices, &cpu_ndevices); 595 596 /* 597 * Setup any quirks that might necessary now that we have probed 598 * all the CPUs 599 */ 600 acpi_cpu_quirks(); 601 602 if (cpu_cx_generic) { 603 /* 604 * We are using generic Cx mode, probe for available Cx states 605 * for all processors. 606 */ 607 for (i = 0; i < cpu_ndevices; i++) { 608 sc = device_get_softc(cpu_devices[i]); 609 acpi_cpu_generic_cx_probe(sc); 610 } 611 } else { 612 /* 613 * We are using _CST mode, remove C3 state if necessary. 614 * 615 * As we now know for sure that we will be using _CST mode 616 * install our notify handler. 617 */ 618 for (i = 0; i < cpu_ndevices; i++) { 619 sc = device_get_softc(cpu_devices[i]); 620 if (cpu_quirks & CPU_QUIRK_NO_C3) 621 sc->cst_cx_count = sc->cst_non_c3 + 1; 622 sc->cst_parent->cpux_cst_notify = acpi_cpu_cst_notify; 623 } 624 } 625 acpi_cpu_global_cx_count(); 626 627 /* Perform Cx final initialization. */ 628 for (i = 0; i < cpu_ndevices; i++) { 629 sc = device_get_softc(cpu_devices[i]); 630 acpi_cpu_startup_cx(sc); 631 632 if (sc->cst_parent->glob_sysctl_tree != NULL) { 633 struct acpi_cpux_softc *cpux = sc->cst_parent; 634 635 /* Add a sysctl handler to handle global Cx lowest setting */ 636 SYSCTL_ADD_PROC(&cpux->glob_sysctl_ctx, 637 SYSCTL_CHILDREN(cpux->glob_sysctl_tree), 638 OID_AUTO, "cx_lowest", 639 CTLTYPE_STRING | CTLFLAG_RW, NULL, 0, 640 acpi_cpu_global_cx_lowest_sysctl, "A", 641 "Requested global lowest Cx sleep state"); 642 SYSCTL_ADD_PROC(&cpux->glob_sysctl_ctx, 643 SYSCTL_CHILDREN(cpux->glob_sysctl_tree), 644 OID_AUTO, "cx_lowest_use", 645 CTLTYPE_STRING | CTLFLAG_RD, NULL, 0, 646 acpi_cpu_global_cx_lowest_use_sysctl, "A", 647 "Global lowest Cx sleep state to use"); 648 } 649 } 650 651 /* Take over idling from cpu_idle_default(). */ 652 cpu_cx_lowest = 0; 653 cpu_cx_lowest_req = 0; 654 cpu_disable_idle = FALSE; 655 cpu_idle_hook = acpi_cpu_idle; 656 } 657 658 static void 659 acpi_cpu_cx_list(struct acpi_cst_softc *sc) 660 { 661 struct sbuf sb; 662 int i; 663 664 /* 665 * Set up the list of Cx states 666 */ 667 sbuf_new(&sb, sc->cst_cx_supported, sizeof(sc->cst_cx_supported), 668 SBUF_FIXEDLEN); 669 for (i = 0; i < sc->cst_cx_count; i++) 670 sbuf_printf(&sb, "C%d/%d ", i + 1, sc->cst_cx_states[i].trans_lat); 671 sbuf_trim(&sb); 672 sbuf_finish(&sb); 673 } 674 675 static void 676 acpi_cpu_startup_cx(struct acpi_cst_softc *sc) 677 { 678 struct acpi_cpux_softc *cpux = sc->cst_parent; 679 680 acpi_cpu_cx_list(sc); 681 682 SYSCTL_ADD_STRING(&cpux->pcpu_sysctl_ctx, 683 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 684 OID_AUTO, "cx_supported", CTLFLAG_RD, 685 sc->cst_cx_supported, 0, 686 "Cx/microsecond values for supported Cx states"); 687 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 688 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 689 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 690 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 691 "requested lowest Cx sleep state"); 692 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 693 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 694 OID_AUTO, "cx_lowest_use", CTLTYPE_STRING | CTLFLAG_RD, 695 (void *)sc, 0, acpi_cpu_cx_lowest_use_sysctl, "A", 696 "lowest Cx sleep state to use"); 697 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 698 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 699 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD, 700 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 701 "percent usage for each Cx state"); 702 703 #ifdef notyet 704 /* Signal platform that we can handle _CST notification. */ 705 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 706 ACPI_LOCK(acpi); 707 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 708 ACPI_UNLOCK(acpi); 709 } 710 #endif 711 } 712 713 /* 714 * Idle the CPU in the lowest state possible. This function is called with 715 * interrupts disabled. Note that once it re-enables interrupts, a task 716 * switch can occur so do not access shared data (i.e. the softc) after 717 * interrupts are re-enabled. 718 */ 719 static void 720 acpi_cpu_idle(void) 721 { 722 struct acpi_cst_softc *sc; 723 struct acpi_cx *cx_next; 724 uint64_t start_time, end_time; 725 int bm_active, cx_next_idx, i; 726 727 /* If disabled, return immediately. */ 728 if (cpu_disable_idle) { 729 ACPI_ENABLE_IRQS(); 730 return; 731 } 732 733 /* 734 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 735 * since there is no ACPI processor object for this CPU. This occurs 736 * for logical CPUs in the HTT case. 737 */ 738 sc = cpu_softc[mdcpu->mi.gd_cpuid]; 739 if (sc == NULL) { 740 acpi_cpu_c1(); 741 return; 742 } 743 744 /* Still probing; use C1 */ 745 if (sc->cst_flags & ACPI_CST_FLAG_PROBING) { 746 acpi_cpu_c1(); 747 return; 748 } 749 750 /* Find the lowest state that has small enough latency. */ 751 cx_next_idx = 0; 752 for (i = sc->cst_cx_lowest; i >= 0; i--) { 753 if (sc->cst_cx_states[i].trans_lat * 3 <= sc->cst_prev_sleep) { 754 cx_next_idx = i; 755 break; 756 } 757 } 758 759 /* 760 * Check for bus master activity. If there was activity, clear 761 * the bit and use the lowest non-C3 state. Note that the USB 762 * driver polling for new devices keeps this bit set all the 763 * time if USB is loaded. 764 */ 765 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 766 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 767 if (bm_active != 0) { 768 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 769 cx_next_idx = min(cx_next_idx, sc->cst_non_c3); 770 } 771 } 772 773 /* Select the next state and update statistics. */ 774 cx_next = &sc->cst_cx_states[cx_next_idx]; 775 sc->cst_cx_stats[cx_next_idx]++; 776 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 777 778 /* 779 * Execute HLT (or equivalent) and wait for an interrupt. We can't 780 * calculate the time spent in C1 since the place we wake up is an 781 * ISR. Assume we slept half of quantum and return. 782 */ 783 if (cx_next->type == ACPI_STATE_C1) { 784 sc->cst_prev_sleep = (sc->cst_prev_sleep * 3 + 500000 / hz) / 4; 785 acpi_cpu_c1(); 786 return; 787 } 788 789 /* 790 * For C3(+), disable bus master arbitration and enable bus master wake 791 * if BM control is available, otherwise flush the CPU cache. 792 */ 793 if (cx_next->type >= ACPI_STATE_C3) { 794 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 795 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 796 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 797 } else 798 ACPI_FLUSH_CPU_CACHE(); 799 } 800 801 /* 802 * Read from P_LVLx to enter C2(+), checking time spent asleep. 803 * Use the ACPI timer for measuring sleep time. Since we need to 804 * get the time very close to the CPU start/stop clock logic, this 805 * is the only reliable time source. 806 */ 807 AcpiRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock); 808 CPU_GET_REG(cx_next->p_lvlx, 1); 809 810 /* 811 * Read the end time twice. Since it may take an arbitrary time 812 * to enter the idle state, the first read may be executed before 813 * the processor has stopped. Doing it again provides enough 814 * margin that we are certain to have a correct value. 815 */ 816 AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 817 AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 818 819 /* Enable bus master arbitration and disable bus master wakeup. */ 820 if (cx_next->type >= ACPI_STATE_C3) { 821 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 822 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 823 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 824 } 825 } 826 ACPI_ENABLE_IRQS(); 827 828 /* Find the actual time asleep in microseconds. */ 829 end_time = acpi_TimerDelta(end_time, start_time); 830 sc->cst_prev_sleep = (sc->cst_prev_sleep * 3 + PM_USEC(end_time)) / 4; 831 } 832 833 /* 834 * Re-evaluate the _CST object when we are notified that it changed. 835 */ 836 static void 837 acpi_cpu_cst_notify(device_t dev) 838 { 839 struct acpi_cst_softc *sc = device_get_softc(dev); 840 841 KASSERT(curthread->td_type != TD_TYPE_NETISR, 842 ("notify in netisr%d", mycpuid)); 843 844 lwkt_serialize_enter(&cpu_cx_slize); 845 846 /* Update the list of Cx states. */ 847 acpi_cpu_cx_cst_dispatch(sc); 848 acpi_cpu_cx_list(sc); 849 850 /* Update the new lowest useable Cx state for all CPUs. */ 851 acpi_cpu_global_cx_count(); 852 853 /* 854 * Fix up the lowest Cx being used 855 */ 856 if (cpu_cx_lowest_req < cpu_cx_count) 857 cpu_cx_lowest = cpu_cx_lowest_req; 858 if (cpu_cx_lowest > cpu_cx_count - 1) 859 cpu_cx_lowest = cpu_cx_count - 1; 860 861 lwkt_serialize_exit(&cpu_cx_slize); 862 } 863 864 static int 865 acpi_cpu_quirks(void) 866 { 867 device_t acpi_dev; 868 uint32_t val; 869 870 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 871 872 /* 873 * Bus mastering arbitration control is needed to keep caches coherent 874 * while sleeping in C3. If it's not present but a working flush cache 875 * instruction is present, flush the caches before entering C3 instead. 876 * Otherwise, just disable C3 completely. 877 */ 878 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 879 AcpiGbl_FADT.Pm2ControlLength == 0) { 880 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 881 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 882 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 883 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 884 "acpi_cpu: no BM control, using flush cache method\n")); 885 } else { 886 cpu_quirks |= CPU_QUIRK_NO_C3; 887 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 888 "acpi_cpu: no BM control, C3 not available\n")); 889 } 890 } 891 892 /* 893 * If we are using generic Cx mode, C3 on multiple CPUs requires using 894 * the expensive flush cache instruction. 895 */ 896 if (cpu_cx_generic && ncpus > 1) { 897 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 898 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 899 "acpi_cpu: SMP, using flush cache mode for C3\n")); 900 } 901 902 /* Look for various quirks of the PIIX4 part. */ 903 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 904 if (acpi_dev != NULL) { 905 switch (pci_get_revid(acpi_dev)) { 906 /* 907 * Disable C3 support for all PIIX4 chipsets. Some of these parts 908 * do not report the BMIDE status to the BM status register and 909 * others have a livelock bug if Type-F DMA is enabled. Linux 910 * works around the BMIDE bug by reading the BM status directly 911 * but we take the simpler approach of disabling C3 for these 912 * parts. 913 * 914 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 915 * Livelock") from the January 2002 PIIX4 specification update. 916 * Applies to all PIIX4 models. 917 * 918 * Also, make sure that all interrupts cause a "Stop Break" 919 * event to exit from C2 state. 920 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 921 * should be set to zero, otherwise it causes C2 to short-sleep. 922 * PIIX4 doesn't properly support C3 and bus master activity 923 * need not break out of C2. 924 */ 925 case PCI_REVISION_A_STEP: 926 case PCI_REVISION_B_STEP: 927 case PCI_REVISION_4E: 928 case PCI_REVISION_4M: 929 cpu_quirks |= CPU_QUIRK_NO_C3; 930 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 931 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 932 933 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 934 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 935 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 936 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 937 val |= PIIX4_STOP_BREAK_MASK; 938 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 939 } 940 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 941 if (val) { 942 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 943 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 944 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 945 } 946 break; 947 default: 948 break; 949 } 950 } 951 952 return (0); 953 } 954 955 static int 956 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 957 { 958 struct acpi_cst_softc *sc; 959 struct sbuf sb; 960 char buf[128]; 961 int i; 962 uintmax_t fract, sum, whole; 963 964 sc = (struct acpi_cst_softc *) arg1; 965 sum = 0; 966 for (i = 0; i < sc->cst_cx_count; i++) 967 sum += sc->cst_cx_stats[i]; 968 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 969 for (i = 0; i < sc->cst_cx_count; i++) { 970 if (sum > 0) { 971 whole = (uintmax_t)sc->cst_cx_stats[i] * 100; 972 fract = (whole % sum) * 100; 973 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 974 (u_int)(fract / sum)); 975 } else 976 sbuf_printf(&sb, "0.00%% "); 977 } 978 sbuf_printf(&sb, "last %dus", sc->cst_prev_sleep); 979 sbuf_trim(&sb); 980 sbuf_finish(&sb); 981 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 982 sbuf_delete(&sb); 983 984 return (0); 985 } 986 987 static int 988 acpi_cpu_set_cx_lowest_oncpu(struct acpi_cst_softc *sc, int val) 989 { 990 int old_lowest, error = 0, old_lowest_req; 991 uint32_t old_type, type; 992 993 KKASSERT(mycpuid == sc->cst_cpuid); 994 995 old_lowest_req = sc->cst_cx_lowest_req; 996 sc->cst_cx_lowest_req = val; 997 998 if (val > sc->cst_cx_count - 1) 999 val = sc->cst_cx_count - 1; 1000 old_lowest = atomic_swap_int(&sc->cst_cx_lowest, val); 1001 1002 old_type = sc->cst_cx_states[old_lowest].type; 1003 type = sc->cst_cx_states[val].type; 1004 if (old_type >= ACPI_STATE_C3 && type < ACPI_STATE_C3) { 1005 KKASSERT(cpu_c3_ncpus > 0); 1006 if (atomic_fetchadd_int(&cpu_c3_ncpus, -1) == 1) { 1007 /* 1008 * All of the CPUs exit C3 state, use a better 1009 * one shot timer. 1010 */ 1011 error = cputimer_intr_select_caps(CPUTIMER_INTR_CAP_NONE); 1012 KKASSERT(!error || error == ERESTART); 1013 if (error == ERESTART) { 1014 if (bootverbose) 1015 kprintf("exit C3, restart intr cputimer\n"); 1016 cputimer_intr_restart(); 1017 } 1018 } 1019 } else if (type >= ACPI_STATE_C3 && old_type < ACPI_STATE_C3) { 1020 if (atomic_fetchadd_int(&cpu_c3_ncpus, 1) == 0) { 1021 /* 1022 * When the first CPU enters C3(+) state, switch 1023 * to an one shot timer, which could handle 1024 * C3(+) state, i.e. the timer will not hang. 1025 */ 1026 error = cputimer_intr_select_caps(CPUTIMER_INTR_CAP_PS); 1027 if (error == ERESTART) { 1028 if (bootverbose) 1029 kprintf("enter C3, restart intr cputimer\n"); 1030 cputimer_intr_restart(); 1031 } else if (error) { 1032 kprintf("no suitable intr cputimer found\n"); 1033 1034 /* Restore */ 1035 sc->cst_cx_lowest_req = old_lowest_req; 1036 sc->cst_cx_lowest = old_lowest; 1037 atomic_fetchadd_int(&cpu_c3_ncpus, -1); 1038 } 1039 } 1040 } 1041 1042 if (error) 1043 return error; 1044 1045 /* Cache the new lowest non-C3 state. */ 1046 acpi_cpu_cx_non_c3(sc); 1047 1048 /* Reset the statistics counters. */ 1049 bzero(sc->cst_cx_stats, sizeof(sc->cst_cx_stats)); 1050 return (0); 1051 } 1052 1053 static void 1054 acpi_cst_set_lowest_handler(netmsg_t msg) 1055 { 1056 struct netmsg_acpi_cst *rmsg = (struct netmsg_acpi_cst *)msg; 1057 int error; 1058 1059 error = acpi_cpu_set_cx_lowest_oncpu(rmsg->sc, rmsg->val); 1060 lwkt_replymsg(&rmsg->base.lmsg, error); 1061 } 1062 1063 static int 1064 acpi_cpu_set_cx_lowest(struct acpi_cst_softc *sc, int val) 1065 { 1066 struct netmsg_acpi_cst msg; 1067 1068 netmsg_init(&msg.base, NULL, &curthread->td_msgport, MSGF_PRIORITY, 1069 acpi_cst_set_lowest_handler); 1070 msg.sc = sc; 1071 msg.val = val; 1072 1073 return lwkt_domsg(netisr_cpuport(sc->cst_cpuid), &msg.base.lmsg, 0); 1074 } 1075 1076 static int 1077 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1078 { 1079 struct acpi_cst_softc *sc; 1080 char state[8]; 1081 int val, error; 1082 1083 sc = (struct acpi_cst_softc *)arg1; 1084 ksnprintf(state, sizeof(state), "C%d", sc->cst_cx_lowest_req + 1); 1085 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1086 if (error != 0 || req->newptr == NULL) 1087 return (error); 1088 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1089 return (EINVAL); 1090 val = (int) strtol(state + 1, NULL, 10) - 1; 1091 if (val < 0) 1092 return (EINVAL); 1093 1094 lwkt_serialize_enter(&cpu_cx_slize); 1095 error = acpi_cpu_set_cx_lowest(sc, val); 1096 lwkt_serialize_exit(&cpu_cx_slize); 1097 1098 return error; 1099 } 1100 1101 static int 1102 acpi_cpu_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS) 1103 { 1104 struct acpi_cst_softc *sc; 1105 char state[8]; 1106 1107 sc = (struct acpi_cst_softc *)arg1; 1108 ksnprintf(state, sizeof(state), "C%d", sc->cst_cx_lowest + 1); 1109 return sysctl_handle_string(oidp, state, sizeof(state), req); 1110 } 1111 1112 static int 1113 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1114 { 1115 struct acpi_cst_softc *sc; 1116 char state[8]; 1117 int val, error, i; 1118 1119 ksnprintf(state, sizeof(state), "C%d", cpu_cx_lowest_req + 1); 1120 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1121 if (error != 0 || req->newptr == NULL) 1122 return (error); 1123 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1124 return (EINVAL); 1125 val = (int) strtol(state + 1, NULL, 10) - 1; 1126 if (val < 0) 1127 return (EINVAL); 1128 1129 lwkt_serialize_enter(&cpu_cx_slize); 1130 1131 cpu_cx_lowest_req = val; 1132 cpu_cx_lowest = val; 1133 if (cpu_cx_lowest > cpu_cx_count - 1) 1134 cpu_cx_lowest = cpu_cx_count - 1; 1135 1136 /* Update the new lowest useable Cx state for all CPUs. */ 1137 for (i = 0; i < cpu_ndevices; i++) { 1138 sc = device_get_softc(cpu_devices[i]); 1139 error = acpi_cpu_set_cx_lowest(sc, val); 1140 if (error) { 1141 KKASSERT(i == 0); 1142 break; 1143 } 1144 } 1145 1146 lwkt_serialize_exit(&cpu_cx_slize); 1147 1148 return error; 1149 } 1150 1151 static int 1152 acpi_cpu_global_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS) 1153 { 1154 char state[8]; 1155 1156 ksnprintf(state, sizeof(state), "C%d", cpu_cx_lowest + 1); 1157 return sysctl_handle_string(oidp, state, sizeof(state), req); 1158 } 1159 1160 /* 1161 * Put the CPU in C1 in a machine-dependant way. 1162 * XXX: shouldn't be here! 1163 */ 1164 static void 1165 acpi_cpu_c1(void) 1166 { 1167 #ifdef __ia64__ 1168 ia64_call_pal_static(PAL_HALT_LIGHT, 0, 0, 0); 1169 #else 1170 splz(); 1171 if ((mycpu->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) 1172 __asm __volatile("sti; hlt"); 1173 else 1174 __asm __volatile("sti; pause"); 1175 #endif /* !__ia64__ */ 1176 } 1177 1178 static void 1179 acpi_cpu_cx_non_c3(struct acpi_cst_softc *sc) 1180 { 1181 int i; 1182 1183 sc->cst_non_c3 = 0; 1184 for (i = sc->cst_cx_lowest; i >= 0; i--) { 1185 if (sc->cst_cx_states[i].type < ACPI_STATE_C3) { 1186 sc->cst_non_c3 = i; 1187 break; 1188 } 1189 } 1190 if (bootverbose) 1191 device_printf(sc->cst_dev, "non-C3 %d\n", sc->cst_non_c3); 1192 } 1193 1194 /* 1195 * Update the largest Cx state supported in the global cpu_cx_count. 1196 * It will be used in the global Cx sysctl handler. 1197 */ 1198 static void 1199 acpi_cpu_global_cx_count(void) 1200 { 1201 struct acpi_cst_softc *sc; 1202 int i; 1203 1204 if (cpu_ndevices == 0) { 1205 cpu_cx_count = 0; 1206 return; 1207 } 1208 1209 sc = device_get_softc(cpu_devices[0]); 1210 cpu_cx_count = sc->cst_cx_count; 1211 1212 for (i = 1; i < cpu_ndevices; i++) { 1213 struct acpi_cst_softc *sc = device_get_softc(cpu_devices[i]); 1214 1215 if (sc->cst_cx_count < cpu_cx_count) 1216 cpu_cx_count = sc->cst_cx_count; 1217 } 1218 if (bootverbose) 1219 kprintf("cpu_cst: global Cx count %d\n", cpu_cx_count); 1220 } 1221