1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/agpreg.h,v 1.3.2.5 2003/06/02 17:38:19 jhb Exp $ 27 * $DragonFly: src/sys/dev/agp/agpreg.h,v 1.5 2004/07/04 00:24:52 dillon Exp $ 28 */ 29 30 #ifndef _PCI_AGPREG_H_ 31 #define _PCI_AGPREG_H_ 32 33 /* 34 * Offsets for various AGP configuration registers. 35 */ 36 #define AGP_APBASE 0x10 37 #define AGP_CAPPTR 0x34 38 39 /* 40 * Offsets from the AGP Capability pointer. 41 */ 42 #define AGP_CAPID 0x0 43 #define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20) 44 #define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16) 45 #define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8) 46 #define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0) 47 48 #define AGP_STATUS 0x4 49 #define AGP_COMMAND 0x8 50 #define AGP_STATUS_AGP3 0x0008 51 #define AGP_STATUS_RQ_MASK 0xff000000 52 #define AGP_COMMAND_RQ_MASK 0xff000000 53 #define AGP_STATUS_ARQSZ_MASK 0xe000 54 #define AGP_COMMAND_ARQSZ_MASK 0xe000 55 #define AGP_STATUS_CAL_MASK 0x1c00 56 #define AGP_COMMAND_CAL_MASK 0x1c00 57 #define AGP_STATUS_ISOCH 0x10000 58 #define AGP_STATUS_SBA 0x0200 59 #define AGP_STATUS_ITA_COH 0x0100 60 #define AGP_STATUS_GART64 0x0080 61 #define AGP_STATUS_HTRANS 0x0040 62 #define AGP_STATUS_64BIT 0x0020 63 #define AGP_STATUS_FW 0x0010 64 #define AGP_COMMAND_RQ_MASK 0xff000000 65 #define AGP_COMMAND_ARQSZ_MASK 0xe000 66 #define AGP_COMMAND_CAL_MASK 0x1c00 67 #define AGP_COMMAND_SBA 0x0200 68 #define AGP_COMMAND_AGP 0x0100 69 #define AGP_COMMAND_GART64 0x0080 70 #define AGP_COMMAND_64BIT 0x0020 71 #define AGP_COMMAND_FW 0x0010 72 73 74 /* 75 * Config offsets for Intel AGP chipsets. 76 */ 77 #define AGP_INTEL_NBXCFG 0x50 78 #define AGP_INTEL_ERRSTS 0x91 79 #define AGP_INTEL_AGPCTRL 0xb0 80 #define AGP_INTEL_APSIZE 0xb4 81 #define AGP_INTEL_ATTBASE 0xb8 82 83 /* 84 * Config offsets for Intel i820/i840/i845/i850/i860/i865 AGP chipsets. 85 */ 86 #define AGP_INTEL_MCHCFG 0x50 87 #define AGP_INTEL_I820_RDCR 0x51 88 #define AGP_INTEL_I845_MCHCFG 0x51 89 #define AGP_INTEL_I8XX_ERRSTS 0xc8 90 91 /* 92 * Config offsets for VIA AGP chipsets. 93 */ 94 #define AGP_VIA_GARTCTRL 0x80 95 #define AGP_VIA_APSIZE 0x84 96 #define AGP_VIA_ATTBASE 0x88 97 98 /* 99 * Config offsets for VIA AGP 3.0 chipsets. 100 */ 101 #define AGP3_VIA_GARTCTRL 0x90 102 #define AGP3_VIA_APSIZE 0x94 103 #define AGP3_VIA_ATTBASE 0x98 104 105 /* 106 * Config offsets for SiS AGP chipsets. 107 */ 108 #define AGP_SIS_ATTBASE 0x90 109 #define AGP_SIS_WINCTRL 0x94 110 #define AGP_SIS_TLBCTRL 0x97 111 #define AGP_SIS_TLBFLUSH 0x98 112 113 /* 114 * Config offsets for Ali AGP chipsets. 115 */ 116 #define AGP_ALI_AGPCTRL 0xb8 117 #define AGP_ALI_ATTBASE 0xbc 118 #define AGP_ALI_TLBCTRL 0xc0 119 120 /* 121 * Config offsets for the AMD 751 chipset. 122 */ 123 #define AGP_AMD751_APBASE 0x10 124 #define AGP_AMD751_REGISTERS 0x14 125 #define AGP_AMD751_APCTRL 0xac 126 #define AGP_AMD751_MODECTRL 0xb0 127 #define AGP_AMD751_MODECTRL_SYNEN 0x80 128 #define AGP_AMD751_MODECTRL2 0xb2 129 #define AGP_AMD751_MODECTRL2_G1LM 0x01 130 #define AGP_AMD751_MODECTRL2_GPDCE 0x02 131 #define AGP_AMD751_MODECTRL2_NGSE 0x08 132 133 /* 134 * Memory mapped register offsets for AMD 751 chipset. 135 */ 136 #define AGP_AMD751_CAPS 0x00 137 #define AGP_AMD751_CAPS_EHI 0x0800 138 #define AGP_AMD751_CAPS_P2P 0x0400 139 #define AGP_AMD751_CAPS_MPC 0x0200 140 #define AGP_AMD751_CAPS_VBE 0x0100 141 #define AGP_AMD751_CAPS_REV 0x00ff 142 #define AGP_AMD751_STATUS 0x02 143 #define AGP_AMD751_STATUS_P2PS 0x0800 144 #define AGP_AMD751_STATUS_GCS 0x0400 145 #define AGP_AMD751_STATUS_MPS 0x0200 146 #define AGP_AMD751_STATUS_VBES 0x0100 147 #define AGP_AMD751_STATUS_P2PE 0x0008 148 #define AGP_AMD751_STATUS_GCE 0x0004 149 #define AGP_AMD751_STATUS_VBEE 0x0001 150 #define AGP_AMD751_ATTBASE 0x04 151 #define AGP_AMD751_TLBCTRL 0x0c 152 153 /* 154 * Config registers for i810 device 0 155 */ 156 #define AGP_I810_SMRAM 0x70 157 #define AGP_I810_SMRAM_GMS 0xc0 158 #define AGP_I810_SMRAM_GMS_DISABLED 0x00 159 #define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 160 #define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 161 #define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 162 #define AGP_I810_MISCC 0x72 163 #define AGP_I810_MISCC_WINSIZE 0x0001 164 #define AGP_I810_MISCC_WINSIZE_64 0x0000 165 #define AGP_I810_MISCC_WINSIZE_32 0x0001 166 #define AGP_I810_MISCC_PLCK 0x0008 167 #define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 168 #define AGP_I810_MISCC_PLCK_LOCKED 0x0008 169 #define AGP_I810_MISCC_WPTC 0x0030 170 #define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 171 #define AGP_I810_MISCC_WPTC_62 0x0010 172 #define AGP_I810_MISCC_WPTC_50 0x0020 173 #define AGP_I810_MISCC_WPTC_37 0x0030 174 #define AGP_I810_MISCC_RPTC 0x00c0 175 #define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 176 #define AGP_I810_MISCC_RPTC_62 0x0040 177 #define AGP_I810_MISCC_RPTC_50 0x0080 178 #define AGP_I810_MISCC_RPTC_37 0x00c0 179 180 /* 181 * Config registers for i810 device 1 182 */ 183 #define AGP_I810_GMADR 0x10 184 #define AGP_I810_MMADR 0x14 185 186 /* 187 * Memory mapped register offsets for i810 chipset. 188 */ 189 #define AGP_I810_PGTBL_CTL 0x2020 190 #define AGP_I810_DRT 0x3000 191 #define AGP_I810_DRT_UNPOPULATED 0x00 192 #define AGP_I810_DRT_POPULATED 0x01 193 #define AGP_I810_GTT 0x10000 194 195 /* 196 * Config registers for i830MG device 0 197 */ 198 #define AGP_I830_GCC1 0x52 199 #define AGP_I830_GCC1_DEV2 0x08 200 #define AGP_I830_GCC1_DEV2_ENABLED 0x00 201 #define AGP_I830_GCC1_DEV2_DISABLED 0x08 202 #define AGP_I830_GCC1_GMS 0x70 203 #define AGP_I830_GCC1_GMS_STOLEN_512 0x20 204 #define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 205 #define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 206 #define AGP_I830_GCC1_GMASIZE 0x01 207 #define AGP_I830_GCC1_GMASIZE_64 0x01 208 #define AGP_I830_GCC1_GMASIZE_128 0x00 209 210 /* 211 * Config registers for 852GM/855GM/865G device 0 212 */ 213 #define AGP_I855_GCC1 0x52 214 #define AGP_I855_GCC1_DEV2 0x08 215 #define AGP_I855_GCC1_DEV2_ENABLED 0x00 216 #define AGP_I855_GCC1_DEV2_DISABLED 0x08 217 #define AGP_I855_GCC1_GMS 0x70 218 #define AGP_I855_GCC1_GMS_STOLEN_0M 0x00 219 #define AGP_I855_GCC1_GMS_STOLEN_1M 0x10 220 #define AGP_I855_GCC1_GMS_STOLEN_4M 0x20 221 #define AGP_I855_GCC1_GMS_STOLEN_8M 0x30 222 #define AGP_I855_GCC1_GMS_STOLEN_16M 0x40 223 #define AGP_I855_GCC1_GMS_STOLEN_32M 0x50 224 225 /* 226 * 852GM/855GM variant identification 227 */ 228 #define AGP_I85X_CAPID 0x44 229 #define AGP_I85X_VARIANT_MASK 0x7 230 #define AGP_I85X_VARIANT_SHIFT 5 231 #define AGP_I855_GME 0x0 232 #define AGP_I855_GM 0x4 233 #define AGP_I852_GME 0x2 234 #define AGP_I852_GM 0x5 235 236 /* 237 * NVIDIA nForce/nForce2 registers 238 */ 239 #define AGP_NVIDIA_0_APBASE 0x10 240 #define AGP_NVIDIA_0_APSIZE 0x80 241 #define AGP_NVIDIA_1_WBC 0xf0 242 #define AGP_NVIDIA_2_GARTCTRL 0xd0 243 #define AGP_NVIDIA_2_APBASE 0xd8 244 #define AGP_NVIDIA_2_APLIMIT 0xdc 245 #define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4) 246 #define AGP_NVIDIA_3_APBASE 0x50 247 #define AGP_NVIDIA_3_APLIMIT 0x54 248 249 #endif /* !_PCI_AGPREG_H_ */ 250