1 /* $FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.5.2.5 2003/06/04 17:56:59 sam Exp $ */ 2 /* $DragonFly: src/sys/dev/crypto/hifn/hifn7751.c,v 1.7 2004/06/02 14:42:48 eirikn Exp $ */ 3 /* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ 4 5 /* 6 * Invertex AEON / Hifn 7751 driver 7 * Copyright (c) 1999 Invertex Inc. All rights reserved. 8 * Copyright (c) 1999 Theo de Raadt 9 * Copyright (c) 2000-2001 Network Security Technologies, Inc. 10 * http://www.netsec.net 11 * 12 * This driver is based on a previous driver by Invertex, for which they 13 * requested: Please send any comments, feedback, bug-fixes, or feature 14 * requests to software@invertex.com. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. The name of the author may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 30 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 31 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 37 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 * 39 * Effort sponsored in part by the Defense Advanced Research Projects 40 * Agency (DARPA) and Air Force Research Laboratory, Air Force 41 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 42 * 43 */ 44 45 /* 46 * Driver for the Hifn 7751 encryption processor. 47 */ 48 #include "opt_hifn.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/proc.h> 53 #include <sys/errno.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/mbuf.h> 57 #include <sys/sysctl.h> 58 59 #include <vm/vm.h> 60 #include <vm/pmap.h> 61 62 #include <machine/clock.h> 63 #include <machine/bus.h> 64 #include <machine/resource.h> 65 #include <sys/bus.h> 66 #include <sys/rman.h> 67 68 #include <opencrypto/cryptodev.h> 69 #include <sys/random.h> 70 71 #include <bus/pci/pcivar.h> 72 #include <bus/pci/pcireg.h> 73 74 #ifdef HIFN_RNDTEST 75 #include "../rndtest/rndtest.h" 76 #endif 77 #include "hifn7751reg.h" 78 #include "hifn7751var.h" 79 80 /* 81 * Prototypes and count for the pci_device structure 82 */ 83 static int hifn_probe(device_t); 84 static int hifn_attach(device_t); 85 static int hifn_detach(device_t); 86 static int hifn_suspend(device_t); 87 static int hifn_resume(device_t); 88 static void hifn_shutdown(device_t); 89 90 static device_method_t hifn_methods[] = { 91 /* Device interface */ 92 DEVMETHOD(device_probe, hifn_probe), 93 DEVMETHOD(device_attach, hifn_attach), 94 DEVMETHOD(device_detach, hifn_detach), 95 DEVMETHOD(device_suspend, hifn_suspend), 96 DEVMETHOD(device_resume, hifn_resume), 97 DEVMETHOD(device_shutdown, hifn_shutdown), 98 99 /* bus interface */ 100 DEVMETHOD(bus_print_child, bus_generic_print_child), 101 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 102 103 { 0, 0 } 104 }; 105 static driver_t hifn_driver = { 106 "hifn", 107 hifn_methods, 108 sizeof (struct hifn_softc) 109 }; 110 static devclass_t hifn_devclass; 111 112 DECLARE_DUMMY_MODULE(hifn); 113 DRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0); 114 MODULE_DEPEND(hifn, crypto, 1, 1, 1); 115 #ifdef HIFN_RNDTEST 116 MODULE_DEPEND(hifn, rndtest, 1, 1, 1); 117 #endif 118 119 static void hifn_reset_board(struct hifn_softc *, int); 120 static void hifn_reset_puc(struct hifn_softc *); 121 static void hifn_puc_wait(struct hifn_softc *); 122 static int hifn_enable_crypto(struct hifn_softc *); 123 static void hifn_set_retry(struct hifn_softc *sc); 124 static void hifn_init_dma(struct hifn_softc *); 125 static void hifn_init_pci_registers(struct hifn_softc *); 126 static int hifn_sramsize(struct hifn_softc *); 127 static int hifn_dramsize(struct hifn_softc *); 128 static int hifn_ramtype(struct hifn_softc *); 129 static void hifn_sessions(struct hifn_softc *); 130 static void hifn_intr(void *); 131 static u_int hifn_write_command(struct hifn_command *, u_int8_t *); 132 static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); 133 static int hifn_newsession(void *, u_int32_t *, struct cryptoini *); 134 static int hifn_freesession(void *, u_int64_t); 135 static int hifn_process(void *, struct cryptop *, int); 136 static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); 137 static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); 138 static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); 139 static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); 140 static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); 141 static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); 142 static int hifn_init_pubrng(struct hifn_softc *); 143 #ifndef HIFN_NO_RNG 144 static void hifn_rng(void *); 145 #endif 146 static void hifn_tick(void *); 147 static void hifn_abort(struct hifn_softc *); 148 static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); 149 150 static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); 151 static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); 152 153 static __inline__ u_int32_t 154 READ_REG_0(struct hifn_softc *sc, bus_size_t reg) 155 { 156 u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg); 157 sc->sc_bar0_lastreg = (bus_size_t) -1; 158 return (v); 159 } 160 #define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) 161 162 static __inline__ u_int32_t 163 READ_REG_1(struct hifn_softc *sc, bus_size_t reg) 164 { 165 u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg); 166 sc->sc_bar1_lastreg = (bus_size_t) -1; 167 return (v); 168 } 169 #define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) 170 171 SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters"); 172 173 #ifdef HIFN_DEBUG 174 static int hifn_debug = 0; 175 SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug, 176 0, "control debugging msgs"); 177 #endif 178 179 static struct hifn_stats hifnstats; 180 SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats, 181 hifn_stats, "driver statistics"); 182 static int hifn_maxbatch = 1; 183 SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch, 184 0, "max ops to batch w/o interrupt"); 185 186 /* 187 * Probe for a supported device. The PCI vendor and device 188 * IDs are used to detect devices we know how to handle. 189 */ 190 static int 191 hifn_probe(device_t dev) 192 { 193 if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX && 194 pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON) 195 return (0); 196 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 197 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 || 198 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 199 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)) 200 return (0); 201 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 202 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751) 203 return (0); 204 return (ENXIO); 205 } 206 207 static void 208 hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 209 { 210 bus_addr_t *paddr = (bus_addr_t*) arg; 211 *paddr = segs->ds_addr; 212 } 213 214 static const char* 215 hifn_partname(struct hifn_softc *sc) 216 { 217 /* XXX sprintf numbers when not decoded */ 218 switch (pci_get_vendor(sc->sc_dev)) { 219 case PCI_VENDOR_HIFN: 220 switch (pci_get_device(sc->sc_dev)) { 221 case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; 222 case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; 223 case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; 224 case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; 225 } 226 return "Hifn unknown-part"; 227 case PCI_VENDOR_INVERTEX: 228 switch (pci_get_device(sc->sc_dev)) { 229 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; 230 } 231 return "Invertex unknown-part"; 232 case PCI_VENDOR_NETSEC: 233 switch (pci_get_device(sc->sc_dev)) { 234 case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; 235 } 236 return "NetSec unknown-part"; 237 } 238 return "Unknown-vendor unknown-part"; 239 } 240 241 static void 242 default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 243 { 244 u_int32_t *p = (u_int32_t *)buf; 245 for (count /= sizeof (u_int32_t); count; count--) 246 add_true_randomness(*p++); 247 } 248 249 /* 250 * Attach an interface that successfully probed. 251 */ 252 static int 253 hifn_attach(device_t dev) 254 { 255 struct hifn_softc *sc = device_get_softc(dev); 256 u_int32_t cmd; 257 caddr_t kva; 258 int rseg, rid; 259 char rbase; 260 u_int16_t ena, rev; 261 262 KASSERT(sc != NULL, ("hifn_attach: null software carrier!")); 263 bzero(sc, sizeof (*sc)); 264 sc->sc_dev = dev; 265 266 /* XXX handle power management */ 267 268 /* 269 * The 7951 has a random number generator and 270 * public key support; note this. 271 */ 272 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 273 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951) 274 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; 275 /* 276 * The 7811 has a random number generator and 277 * we also note it's identity 'cuz of some quirks. 278 */ 279 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 280 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) 281 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; 282 283 /* 284 * Configure support for memory-mapped access to 285 * registers and for DMA operations. 286 */ 287 #define PCIM_ENA (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN) 288 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 289 cmd |= PCIM_ENA; 290 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 291 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 292 if ((cmd & PCIM_ENA) != PCIM_ENA) { 293 device_printf(dev, "failed to enable %s\n", 294 (cmd & PCIM_ENA) == 0 ? 295 "memory mapping & bus mastering" : 296 (cmd & PCIM_CMD_MEMEN) == 0 ? 297 "memory mapping" : "bus mastering"); 298 goto fail_pci; 299 } 300 #undef PCIM_ENA 301 302 /* 303 * Setup PCI resources. Note that we record the bus 304 * tag and handle for each register mapping, this is 305 * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, 306 * and WRITE_REG_1 macros throughout the driver. 307 */ 308 rid = HIFN_BAR0; 309 sc->sc_bar0res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 310 0, ~0, 1, RF_ACTIVE); 311 if (sc->sc_bar0res == NULL) { 312 device_printf(dev, "cannot map bar%d register space\n", 0); 313 goto fail_pci; 314 } 315 sc->sc_st0 = rman_get_bustag(sc->sc_bar0res); 316 sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res); 317 sc->sc_bar0_lastreg = (bus_size_t) -1; 318 319 rid = HIFN_BAR1; 320 sc->sc_bar1res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 321 0, ~0, 1, RF_ACTIVE); 322 if (sc->sc_bar1res == NULL) { 323 device_printf(dev, "cannot map bar%d register space\n", 1); 324 goto fail_io0; 325 } 326 sc->sc_st1 = rman_get_bustag(sc->sc_bar1res); 327 sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res); 328 sc->sc_bar1_lastreg = (bus_size_t) -1; 329 330 hifn_set_retry(sc); 331 332 /* 333 * Setup the area where the Hifn DMA's descriptors 334 * and associated data structures. 335 */ 336 if (bus_dma_tag_create(NULL, /* parent */ 337 1, 0, /* alignment,boundary */ 338 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 339 BUS_SPACE_MAXADDR, /* highaddr */ 340 NULL, NULL, /* filter, filterarg */ 341 HIFN_MAX_DMALEN, /* maxsize */ 342 MAX_SCATTER, /* nsegments */ 343 HIFN_MAX_SEGLEN, /* maxsegsize */ 344 BUS_DMA_ALLOCNOW, /* flags */ 345 &sc->sc_dmat)) { 346 device_printf(dev, "cannot allocate DMA tag\n"); 347 goto fail_io1; 348 } 349 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 350 device_printf(dev, "cannot create dma map\n"); 351 bus_dma_tag_destroy(sc->sc_dmat); 352 goto fail_io1; 353 } 354 if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 355 device_printf(dev, "cannot alloc dma buffer\n"); 356 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 357 bus_dma_tag_destroy(sc->sc_dmat); 358 goto fail_io1; 359 } 360 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva, 361 sizeof (*sc->sc_dma), 362 hifn_dmamap_cb, &sc->sc_dma_physaddr, 363 BUS_DMA_NOWAIT)) { 364 device_printf(dev, "cannot load dma map\n"); 365 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap); 366 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 367 bus_dma_tag_destroy(sc->sc_dmat); 368 goto fail_io1; 369 } 370 sc->sc_dma = (struct hifn_dma *)kva; 371 bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 372 373 KASSERT(sc->sc_st0 != NULL, ("hifn_attach: null bar0 tag!")); 374 KASSERT(sc->sc_sh0 != NULL, ("hifn_attach: null bar0 handle!")); 375 KASSERT(sc->sc_st1 != NULL, ("hifn_attach: null bar1 tag!")); 376 KASSERT(sc->sc_sh1 != NULL, ("hifn_attach: null bar1 handle!")); 377 378 /* 379 * Reset the board and do the ``secret handshake'' 380 * to enable the crypto support. Then complete the 381 * initialization procedure by setting up the interrupt 382 * and hooking in to the system crypto support so we'll 383 * get used for system services like the crypto device, 384 * IPsec, RNG device, etc. 385 */ 386 hifn_reset_board(sc, 0); 387 388 if (hifn_enable_crypto(sc) != 0) { 389 device_printf(dev, "crypto enabling failed\n"); 390 goto fail_mem; 391 } 392 hifn_reset_puc(sc); 393 394 hifn_init_dma(sc); 395 hifn_init_pci_registers(sc); 396 397 if (hifn_ramtype(sc)) 398 goto fail_mem; 399 400 if (sc->sc_drammodel == 0) 401 hifn_sramsize(sc); 402 else 403 hifn_dramsize(sc); 404 405 /* 406 * Workaround for NetSec 7751 rev A: half ram size because two 407 * of the address lines were left floating 408 */ 409 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 410 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && 411 pci_get_revid(dev) == 0x61) /*XXX???*/ 412 sc->sc_ramsize >>= 1; 413 414 /* 415 * Arrange the interrupt line. 416 */ 417 rid = 0; 418 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 419 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 420 if (sc->sc_irq == NULL) { 421 device_printf(dev, "could not map interrupt\n"); 422 goto fail_mem; 423 } 424 /* 425 * NB: Network code assumes we are blocked with splimp() 426 * so make sure the IRQ is marked appropriately. 427 */ 428 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 429 hifn_intr, sc, &sc->sc_intrhand)) { 430 device_printf(dev, "could not setup interrupt\n"); 431 goto fail_intr2; 432 } 433 434 hifn_sessions(sc); 435 436 /* 437 * NB: Keep only the low 16 bits; this masks the chip id 438 * from the 7951. 439 */ 440 rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; 441 442 rseg = sc->sc_ramsize / 1024; 443 rbase = 'K'; 444 if (sc->sc_ramsize >= (1024 * 1024)) { 445 rbase = 'M'; 446 rseg /= 1024; 447 } 448 device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram, %u sessions\n", 449 hifn_partname(sc), rev, 450 rseg, rbase, sc->sc_drammodel ? 'd' : 's', 451 sc->sc_maxses); 452 453 sc->sc_cid = crypto_get_driverid(0); 454 if (sc->sc_cid < 0) { 455 device_printf(dev, "could not get crypto driver id\n"); 456 goto fail_intr; 457 } 458 459 WRITE_REG_0(sc, HIFN_0_PUCNFG, 460 READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); 461 ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 462 463 switch (ena) { 464 case HIFN_PUSTAT_ENA_2: 465 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 466 hifn_newsession, hifn_freesession, hifn_process, sc); 467 crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0, 468 hifn_newsession, hifn_freesession, hifn_process, sc); 469 /*FALLTHROUGH*/ 470 case HIFN_PUSTAT_ENA_1: 471 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0, 472 hifn_newsession, hifn_freesession, hifn_process, sc); 473 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0, 474 hifn_newsession, hifn_freesession, hifn_process, sc); 475 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 476 hifn_newsession, hifn_freesession, hifn_process, sc); 477 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 478 hifn_newsession, hifn_freesession, hifn_process, sc); 479 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 480 hifn_newsession, hifn_freesession, hifn_process, sc); 481 break; 482 } 483 484 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 485 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 486 487 if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) 488 hifn_init_pubrng(sc); 489 490 /* NB: 1 means the callout runs w/o Giant locked */ 491 callout_init(&sc->sc_tickto); 492 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 493 494 return (0); 495 496 fail_intr: 497 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 498 fail_intr2: 499 /* XXX don't store rid */ 500 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 501 fail_mem: 502 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 503 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 504 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 505 bus_dma_tag_destroy(sc->sc_dmat); 506 507 /* Turn off DMA polling */ 508 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 509 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 510 fail_io1: 511 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 512 fail_io0: 513 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 514 fail_pci: 515 return (ENXIO); 516 } 517 518 /* 519 * Detach an interface that successfully probed. 520 */ 521 static int 522 hifn_detach(device_t dev) 523 { 524 struct hifn_softc *sc = device_get_softc(dev); 525 int s; 526 527 KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); 528 529 s = splimp(); 530 531 /*XXX other resources */ 532 callout_stop(&sc->sc_tickto); 533 callout_stop(&sc->sc_rngto); 534 #ifdef HIFN_RNDTEST 535 if (sc->sc_rndtest) 536 rndtest_detach(sc->sc_rndtest); 537 #endif 538 539 /* Turn off DMA polling */ 540 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 541 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 542 543 crypto_unregister_all(sc->sc_cid); 544 545 bus_generic_detach(dev); /*XXX should be no children, right? */ 546 547 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 548 /* XXX don't store rid */ 549 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 550 551 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 552 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 553 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 554 bus_dma_tag_destroy(sc->sc_dmat); 555 556 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 557 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 558 559 splx(s); 560 561 return (0); 562 } 563 564 /* 565 * Stop all chip I/O so that the kernel's probe routines don't 566 * get confused by errant DMAs when rebooting. 567 */ 568 static void 569 hifn_shutdown(device_t dev) 570 { 571 #ifdef notyet 572 hifn_stop(device_get_softc(dev)); 573 #endif 574 } 575 576 /* 577 * Device suspend routine. Stop the interface and save some PCI 578 * settings in case the BIOS doesn't restore them properly on 579 * resume. 580 */ 581 static int 582 hifn_suspend(device_t dev) 583 { 584 struct hifn_softc *sc = device_get_softc(dev); 585 #ifdef notyet 586 int i; 587 588 hifn_stop(sc); 589 for (i = 0; i < 5; i++) 590 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 591 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 592 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 593 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 594 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 595 #endif 596 sc->sc_suspended = 1; 597 598 return (0); 599 } 600 601 /* 602 * Device resume routine. Restore some PCI settings in case the BIOS 603 * doesn't, re-enable busmastering, and restart the interface if 604 * appropriate. 605 */ 606 static int 607 hifn_resume(device_t dev) 608 { 609 struct hifn_softc *sc = device_get_softc(dev); 610 #ifdef notyet 611 int i; 612 613 /* better way to do this? */ 614 for (i = 0; i < 5; i++) 615 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 616 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 617 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 618 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 619 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 620 621 /* reenable busmastering */ 622 pci_enable_busmaster(dev); 623 pci_enable_io(dev, HIFN_RES); 624 625 /* reinitialize interface if necessary */ 626 if (ifp->if_flags & IFF_UP) 627 rl_init(sc); 628 #endif 629 sc->sc_suspended = 0; 630 631 return (0); 632 } 633 634 static int 635 hifn_init_pubrng(struct hifn_softc *sc) 636 { 637 u_int32_t r; 638 int i; 639 640 #ifdef HIFN_RNDTEST 641 sc->sc_rndtest = rndtest_attach(sc->sc_dev); 642 if (sc->sc_rndtest) 643 sc->sc_harvest = rndtest_harvest; 644 else 645 sc->sc_harvest = default_harvest; 646 #else 647 sc->sc_harvest = default_harvest; 648 #endif 649 if ((sc->sc_flags & HIFN_IS_7811) == 0) { 650 /* Reset 7951 public key/rng engine */ 651 WRITE_REG_1(sc, HIFN_1_PUB_RESET, 652 READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); 653 654 for (i = 0; i < 100; i++) { 655 DELAY(1000); 656 if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & 657 HIFN_PUBRST_RESET) == 0) 658 break; 659 } 660 661 if (i == 100) { 662 device_printf(sc->sc_dev, "public key init failed\n"); 663 return (1); 664 } 665 } 666 667 #ifndef HIFN_NO_RNG 668 /* Enable the rng, if available */ 669 if (sc->sc_flags & HIFN_HAS_RNG) { 670 if (sc->sc_flags & HIFN_IS_7811) { 671 r = READ_REG_1(sc, HIFN_1_7811_RNGENA); 672 if (r & HIFN_7811_RNGENA_ENA) { 673 r &= ~HIFN_7811_RNGENA_ENA; 674 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 675 } 676 WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, 677 HIFN_7811_RNGCFG_DEFL); 678 r |= HIFN_7811_RNGENA_ENA; 679 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 680 } else 681 WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, 682 READ_REG_1(sc, HIFN_1_RNG_CONFIG) | 683 HIFN_RNGCFG_ENA); 684 685 sc->sc_rngfirst = 1; 686 if (hz >= 100) 687 sc->sc_rnghz = hz / 100; 688 else 689 sc->sc_rnghz = 1; 690 /* NB: 1 means the callout runs w/o Giant locked */ 691 callout_init(&sc->sc_rngto); 692 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 693 } 694 #endif 695 696 /* Enable public key engine, if available */ 697 if (sc->sc_flags & HIFN_HAS_PUBLIC) { 698 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 699 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; 700 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 701 } 702 703 return (0); 704 } 705 706 #ifndef HIFN_NO_RNG 707 static void 708 hifn_rng(void *vsc) 709 { 710 #define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0 711 struct hifn_softc *sc = vsc; 712 u_int32_t sts, num[2]; 713 int i; 714 715 if (sc->sc_flags & HIFN_IS_7811) { 716 for (i = 0; i < 5; i++) { 717 sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); 718 if (sts & HIFN_7811_RNGSTS_UFL) { 719 device_printf(sc->sc_dev, 720 "RNG underflow: disabling\n"); 721 return; 722 } 723 if ((sts & HIFN_7811_RNGSTS_RDY) == 0) 724 break; 725 726 /* 727 * There are at least two words in the RNG FIFO 728 * at this point. 729 */ 730 num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 731 num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 732 /* NB: discard first data read */ 733 if (sc->sc_rngfirst) 734 sc->sc_rngfirst = 0; 735 else 736 (*sc->sc_harvest)(sc->sc_rndtest, 737 num, sizeof (num)); 738 } 739 } else { 740 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA); 741 742 /* NB: discard first data read */ 743 if (sc->sc_rngfirst) 744 sc->sc_rngfirst = 0; 745 else 746 (*sc->sc_harvest)(sc->sc_rndtest, 747 num, sizeof (num[0])); 748 } 749 750 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 751 #undef RANDOM_BITS 752 } 753 #endif 754 755 static void 756 hifn_puc_wait(struct hifn_softc *sc) 757 { 758 int i; 759 760 for (i = 5000; i > 0; i--) { 761 DELAY(1); 762 if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET)) 763 break; 764 } 765 if (!i) 766 device_printf(sc->sc_dev, "proc unit did not reset\n"); 767 } 768 769 /* 770 * Reset the processing unit. 771 */ 772 static void 773 hifn_reset_puc(struct hifn_softc *sc) 774 { 775 /* Reset processing unit */ 776 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 777 hifn_puc_wait(sc); 778 } 779 780 /* 781 * Set the Retry and TRDY registers; note that we set them to 782 * zero because the 7811 locks up when forced to retry (section 783 * 3.6 of "Specification Update SU-0014-04". Not clear if we 784 * should do this for all Hifn parts, but it doesn't seem to hurt. 785 */ 786 static void 787 hifn_set_retry(struct hifn_softc *sc) 788 { 789 /* NB: RETRY only responds to 8-bit reads/writes */ 790 pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); 791 pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4); 792 } 793 794 /* 795 * Resets the board. Values in the regesters are left as is 796 * from the reset (i.e. initial values are assigned elsewhere). 797 */ 798 static void 799 hifn_reset_board(struct hifn_softc *sc, int full) 800 { 801 u_int32_t reg; 802 803 /* 804 * Set polling in the DMA configuration register to zero. 0x7 avoids 805 * resetting the board and zeros out the other fields. 806 */ 807 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 808 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 809 810 /* 811 * Now that polling has been disabled, we have to wait 1 ms 812 * before resetting the board. 813 */ 814 DELAY(1000); 815 816 /* Reset the DMA unit */ 817 if (full) { 818 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 819 DELAY(1000); 820 } else { 821 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, 822 HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); 823 hifn_reset_puc(sc); 824 } 825 826 KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); 827 bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 828 829 /* Bring dma unit out of reset */ 830 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 831 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 832 833 hifn_puc_wait(sc); 834 hifn_set_retry(sc); 835 836 if (sc->sc_flags & HIFN_IS_7811) { 837 for (reg = 0; reg < 1000; reg++) { 838 if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & 839 HIFN_MIPSRST_CRAMINIT) 840 break; 841 DELAY(1000); 842 } 843 if (reg == 1000) 844 printf(": cram init timeout\n"); 845 } 846 } 847 848 static u_int32_t 849 hifn_next_signature(u_int32_t a, u_int cnt) 850 { 851 int i; 852 u_int32_t v; 853 854 for (i = 0; i < cnt; i++) { 855 856 /* get the parity */ 857 v = a & 0x80080125; 858 v ^= v >> 16; 859 v ^= v >> 8; 860 v ^= v >> 4; 861 v ^= v >> 2; 862 v ^= v >> 1; 863 864 a = (v & 1) ^ (a << 1); 865 } 866 867 return a; 868 } 869 870 struct pci2id { 871 u_short pci_vendor; 872 u_short pci_prod; 873 char card_id[13]; 874 }; 875 static struct pci2id pci2id[] = { 876 { 877 PCI_VENDOR_HIFN, 878 PCI_PRODUCT_HIFN_7951, 879 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 880 0x00, 0x00, 0x00, 0x00, 0x00 } 881 }, { 882 PCI_VENDOR_NETSEC, 883 PCI_PRODUCT_NETSEC_7751, 884 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 885 0x00, 0x00, 0x00, 0x00, 0x00 } 886 }, { 887 PCI_VENDOR_INVERTEX, 888 PCI_PRODUCT_INVERTEX_AEON, 889 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 890 0x00, 0x00, 0x00, 0x00, 0x00 } 891 }, { 892 PCI_VENDOR_HIFN, 893 PCI_PRODUCT_HIFN_7811, 894 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 895 0x00, 0x00, 0x00, 0x00, 0x00 } 896 }, { 897 /* 898 * Other vendors share this PCI ID as well, such as 899 * http://www.powercrypt.com, and obviously they also 900 * use the same key. 901 */ 902 PCI_VENDOR_HIFN, 903 PCI_PRODUCT_HIFN_7751, 904 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 905 0x00, 0x00, 0x00, 0x00, 0x00 } 906 }, 907 }; 908 909 /* 910 * Checks to see if crypto is already enabled. If crypto isn't enable, 911 * "hifn_enable_crypto" is called to enable it. The check is important, 912 * as enabling crypto twice will lock the board. 913 */ 914 static int 915 hifn_enable_crypto(struct hifn_softc *sc) 916 { 917 u_int32_t dmacfg, ramcfg, encl, addr, i; 918 char *offtbl = NULL; 919 920 for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) { 921 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) && 922 pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) { 923 offtbl = pci2id[i].card_id; 924 break; 925 } 926 } 927 if (offtbl == NULL) { 928 device_printf(sc->sc_dev, "Unknown card!\n"); 929 return (1); 930 } 931 932 ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); 933 dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); 934 935 /* 936 * The RAM config register's encrypt level bit needs to be set before 937 * every read performed on the encryption level register. 938 */ 939 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 940 941 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 942 943 /* 944 * Make sure we don't re-unlock. Two unlocks kills chip until the 945 * next reboot. 946 */ 947 if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { 948 #ifdef HIFN_DEBUG 949 if (hifn_debug) 950 device_printf(sc->sc_dev, 951 "Strong crypto already enabled!\n"); 952 #endif 953 goto report; 954 } 955 956 if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { 957 #ifdef HIFN_DEBUG 958 if (hifn_debug) 959 device_printf(sc->sc_dev, 960 "Unknown encryption level 0x%x\n", encl); 961 #endif 962 return 1; 963 } 964 965 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | 966 HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 967 DELAY(1000); 968 addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); 969 DELAY(1000); 970 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); 971 DELAY(1000); 972 973 for (i = 0; i <= 12; i++) { 974 addr = hifn_next_signature(addr, offtbl[i] + 0x101); 975 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); 976 977 DELAY(1000); 978 } 979 980 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 981 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 982 983 #ifdef HIFN_DEBUG 984 if (hifn_debug) { 985 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) 986 device_printf(sc->sc_dev, "Engine is permanently " 987 "locked until next system reset!\n"); 988 else 989 device_printf(sc->sc_dev, "Engine enabled " 990 "successfully!\n"); 991 } 992 #endif 993 994 report: 995 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); 996 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); 997 998 switch (encl) { 999 case HIFN_PUSTAT_ENA_1: 1000 case HIFN_PUSTAT_ENA_2: 1001 break; 1002 case HIFN_PUSTAT_ENA_0: 1003 default: 1004 device_printf(sc->sc_dev, "disabled"); 1005 break; 1006 } 1007 1008 return 0; 1009 } 1010 1011 /* 1012 * Give initial values to the registers listed in the "Register Space" 1013 * section of the HIFN Software Development reference manual. 1014 */ 1015 static void 1016 hifn_init_pci_registers(struct hifn_softc *sc) 1017 { 1018 /* write fixed values needed by the Initialization registers */ 1019 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 1020 WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 1021 WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 1022 1023 /* write all 4 ring address registers */ 1024 WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + 1025 offsetof(struct hifn_dma, cmdr[0])); 1026 WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + 1027 offsetof(struct hifn_dma, srcr[0])); 1028 WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + 1029 offsetof(struct hifn_dma, dstr[0])); 1030 WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + 1031 offsetof(struct hifn_dma, resr[0])); 1032 1033 DELAY(2000); 1034 1035 /* write status register */ 1036 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1037 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 1038 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | 1039 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 1040 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 1041 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 1042 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 1043 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 1044 HIFN_DMACSR_S_WAIT | 1045 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 1046 HIFN_DMACSR_C_WAIT | 1047 HIFN_DMACSR_ENGINE | 1048 ((sc->sc_flags & HIFN_HAS_PUBLIC) ? 1049 HIFN_DMACSR_PUBDONE : 0) | 1050 ((sc->sc_flags & HIFN_IS_7811) ? 1051 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); 1052 1053 sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; 1054 sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 1055 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 1056 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 1057 ((sc->sc_flags & HIFN_IS_7811) ? 1058 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); 1059 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 1060 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1061 1062 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1063 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | 1064 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | 1065 (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); 1066 1067 WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1068 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 1069 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 1070 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 1071 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 1072 } 1073 1074 /* 1075 * The maximum number of sessions supported by the card 1076 * is dependent on the amount of context ram, which 1077 * encryption algorithms are enabled, and how compression 1078 * is configured. This should be configured before this 1079 * routine is called. 1080 */ 1081 static void 1082 hifn_sessions(struct hifn_softc *sc) 1083 { 1084 u_int32_t pucnfg; 1085 int ctxsize; 1086 1087 pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1088 1089 if (pucnfg & HIFN_PUCNFG_COMPSING) { 1090 if (pucnfg & HIFN_PUCNFG_ENCCNFG) 1091 ctxsize = 128; 1092 else 1093 ctxsize = 512; 1094 sc->sc_maxses = 1 + 1095 ((sc->sc_ramsize - 32768) / ctxsize); 1096 } else 1097 sc->sc_maxses = sc->sc_ramsize / 16384; 1098 1099 if (sc->sc_maxses > 2048) 1100 sc->sc_maxses = 2048; 1101 } 1102 1103 /* 1104 * Determine ram type (sram or dram). Board should be just out of a reset 1105 * state when this is called. 1106 */ 1107 static int 1108 hifn_ramtype(struct hifn_softc *sc) 1109 { 1110 u_int8_t data[8], dataexpect[8]; 1111 int i; 1112 1113 for (i = 0; i < sizeof(data); i++) 1114 data[i] = dataexpect[i] = 0x55; 1115 if (hifn_writeramaddr(sc, 0, data)) 1116 return (-1); 1117 if (hifn_readramaddr(sc, 0, data)) 1118 return (-1); 1119 if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1120 sc->sc_drammodel = 1; 1121 return (0); 1122 } 1123 1124 for (i = 0; i < sizeof(data); i++) 1125 data[i] = dataexpect[i] = 0xaa; 1126 if (hifn_writeramaddr(sc, 0, data)) 1127 return (-1); 1128 if (hifn_readramaddr(sc, 0, data)) 1129 return (-1); 1130 if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1131 sc->sc_drammodel = 1; 1132 return (0); 1133 } 1134 1135 return (0); 1136 } 1137 1138 #define HIFN_SRAM_MAX (32 << 20) 1139 #define HIFN_SRAM_STEP_SIZE 16384 1140 #define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) 1141 1142 static int 1143 hifn_sramsize(struct hifn_softc *sc) 1144 { 1145 u_int32_t a; 1146 u_int8_t data[8]; 1147 u_int8_t dataexpect[sizeof(data)]; 1148 int32_t i; 1149 1150 for (i = 0; i < sizeof(data); i++) 1151 data[i] = dataexpect[i] = i ^ 0x5a; 1152 1153 for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { 1154 a = i * HIFN_SRAM_STEP_SIZE; 1155 bcopy(&i, data, sizeof(i)); 1156 hifn_writeramaddr(sc, a, data); 1157 } 1158 1159 for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { 1160 a = i * HIFN_SRAM_STEP_SIZE; 1161 bcopy(&i, dataexpect, sizeof(i)); 1162 if (hifn_readramaddr(sc, a, data) < 0) 1163 return (0); 1164 if (bcmp(data, dataexpect, sizeof(data)) != 0) 1165 return (0); 1166 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; 1167 } 1168 1169 return (0); 1170 } 1171 1172 /* 1173 * XXX For dram boards, one should really try all of the 1174 * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG 1175 * is already set up correctly. 1176 */ 1177 static int 1178 hifn_dramsize(struct hifn_softc *sc) 1179 { 1180 u_int32_t cnfg; 1181 1182 cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & 1183 HIFN_PUCNFG_DRAMMASK; 1184 sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); 1185 return (0); 1186 } 1187 1188 static void 1189 hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) 1190 { 1191 struct hifn_dma *dma = sc->sc_dma; 1192 1193 if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1194 dma->cmdi = 0; 1195 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1196 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1197 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1198 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1199 } 1200 *cmdp = dma->cmdi++; 1201 dma->cmdk = dma->cmdi; 1202 1203 if (dma->srci == HIFN_D_SRC_RSIZE) { 1204 dma->srci = 0; 1205 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID | 1206 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1207 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1208 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1209 } 1210 *srcp = dma->srci++; 1211 dma->srck = dma->srci; 1212 1213 if (dma->dsti == HIFN_D_DST_RSIZE) { 1214 dma->dsti = 0; 1215 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID | 1216 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1217 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, 1218 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1219 } 1220 *dstp = dma->dsti++; 1221 dma->dstk = dma->dsti; 1222 1223 if (dma->resi == HIFN_D_RES_RSIZE) { 1224 dma->resi = 0; 1225 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1226 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1227 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1228 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1229 } 1230 *resp = dma->resi++; 1231 dma->resk = dma->resi; 1232 } 1233 1234 static int 1235 hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1236 { 1237 struct hifn_dma *dma = sc->sc_dma; 1238 hifn_base_command_t wc; 1239 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1240 int r, cmdi, resi, srci, dsti; 1241 1242 wc.masks = htole16(3 << 13); 1243 wc.session_num = htole16(addr >> 14); 1244 wc.total_source_count = htole16(8); 1245 wc.total_dest_count = htole16(addr & 0x3fff); 1246 1247 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1248 1249 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1250 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1251 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1252 1253 /* build write command */ 1254 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1255 *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; 1256 bcopy(data, &dma->test_src, sizeof(dma->test_src)); 1257 1258 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr 1259 + offsetof(struct hifn_dma, test_src)); 1260 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr 1261 + offsetof(struct hifn_dma, test_dst)); 1262 1263 dma->cmdr[cmdi].l = htole32(16 | masks); 1264 dma->srcr[srci].l = htole32(8 | masks); 1265 dma->dstr[dsti].l = htole32(4 | masks); 1266 dma->resr[resi].l = htole32(4 | masks); 1267 1268 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1269 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1270 1271 for (r = 10000; r >= 0; r--) { 1272 DELAY(10); 1273 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1274 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1275 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1276 break; 1277 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1278 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1279 } 1280 if (r == 0) { 1281 device_printf(sc->sc_dev, "writeramaddr -- " 1282 "result[%d](addr %d) still valid\n", resi, addr); 1283 r = -1; 1284 return (-1); 1285 } else 1286 r = 0; 1287 1288 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1289 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1290 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1291 1292 return (r); 1293 } 1294 1295 static int 1296 hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1297 { 1298 struct hifn_dma *dma = sc->sc_dma; 1299 hifn_base_command_t rc; 1300 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1301 int r, cmdi, srci, dsti, resi; 1302 1303 rc.masks = htole16(2 << 13); 1304 rc.session_num = htole16(addr >> 14); 1305 rc.total_source_count = htole16(addr & 0x3fff); 1306 rc.total_dest_count = htole16(8); 1307 1308 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1309 1310 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1311 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1312 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1313 1314 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1315 *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; 1316 1317 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + 1318 offsetof(struct hifn_dma, test_src)); 1319 dma->test_src = 0; 1320 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + 1321 offsetof(struct hifn_dma, test_dst)); 1322 dma->test_dst = 0; 1323 dma->cmdr[cmdi].l = htole32(8 | masks); 1324 dma->srcr[srci].l = htole32(8 | masks); 1325 dma->dstr[dsti].l = htole32(8 | masks); 1326 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); 1327 1328 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1329 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1330 1331 for (r = 10000; r >= 0; r--) { 1332 DELAY(10); 1333 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1334 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1335 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1336 break; 1337 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1338 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1339 } 1340 if (r == 0) { 1341 device_printf(sc->sc_dev, "readramaddr -- " 1342 "result[%d](addr %d) still valid\n", resi, addr); 1343 r = -1; 1344 } else { 1345 r = 0; 1346 bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); 1347 } 1348 1349 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1350 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1351 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1352 1353 return (r); 1354 } 1355 1356 /* 1357 * Initialize the descriptor rings. 1358 */ 1359 static void 1360 hifn_init_dma(struct hifn_softc *sc) 1361 { 1362 struct hifn_dma *dma = sc->sc_dma; 1363 int i; 1364 1365 hifn_set_retry(sc); 1366 1367 /* initialize static pointer values */ 1368 for (i = 0; i < HIFN_D_CMD_RSIZE; i++) 1369 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + 1370 offsetof(struct hifn_dma, command_bufs[i][0])); 1371 for (i = 0; i < HIFN_D_RES_RSIZE; i++) 1372 dma->resr[i].p = htole32(sc->sc_dma_physaddr + 1373 offsetof(struct hifn_dma, result_bufs[i][0])); 1374 1375 dma->cmdr[HIFN_D_CMD_RSIZE].p = 1376 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); 1377 dma->srcr[HIFN_D_SRC_RSIZE].p = 1378 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); 1379 dma->dstr[HIFN_D_DST_RSIZE].p = 1380 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); 1381 dma->resr[HIFN_D_RES_RSIZE].p = 1382 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); 1383 1384 dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; 1385 dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; 1386 dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; 1387 } 1388 1389 /* 1390 * Writes out the raw command buffer space. Returns the 1391 * command buffer size. 1392 */ 1393 static u_int 1394 hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) 1395 { 1396 u_int8_t *buf_pos; 1397 hifn_base_command_t *base_cmd; 1398 hifn_mac_command_t *mac_cmd; 1399 hifn_crypt_command_t *cry_cmd; 1400 int using_mac, using_crypt, len; 1401 u_int32_t dlen, slen; 1402 1403 buf_pos = buf; 1404 using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; 1405 using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; 1406 1407 base_cmd = (hifn_base_command_t *)buf_pos; 1408 base_cmd->masks = htole16(cmd->base_masks); 1409 slen = cmd->src_mapsize; 1410 if (cmd->sloplen) 1411 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); 1412 else 1413 dlen = cmd->dst_mapsize; 1414 base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); 1415 base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); 1416 dlen >>= 16; 1417 slen >>= 16; 1418 base_cmd->session_num = htole16(cmd->session_num | 1419 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 1420 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 1421 buf_pos += sizeof(hifn_base_command_t); 1422 1423 if (using_mac) { 1424 mac_cmd = (hifn_mac_command_t *)buf_pos; 1425 dlen = cmd->maccrd->crd_len; 1426 mac_cmd->source_count = htole16(dlen & 0xffff); 1427 dlen >>= 16; 1428 mac_cmd->masks = htole16(cmd->mac_masks | 1429 ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); 1430 mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); 1431 mac_cmd->reserved = 0; 1432 buf_pos += sizeof(hifn_mac_command_t); 1433 } 1434 1435 if (using_crypt) { 1436 cry_cmd = (hifn_crypt_command_t *)buf_pos; 1437 dlen = cmd->enccrd->crd_len; 1438 cry_cmd->source_count = htole16(dlen & 0xffff); 1439 dlen >>= 16; 1440 cry_cmd->masks = htole16(cmd->cry_masks | 1441 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); 1442 cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); 1443 cry_cmd->reserved = 0; 1444 buf_pos += sizeof(hifn_crypt_command_t); 1445 } 1446 1447 if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { 1448 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); 1449 buf_pos += HIFN_MAC_KEY_LENGTH; 1450 } 1451 1452 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { 1453 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1454 case HIFN_CRYPT_CMD_ALG_3DES: 1455 bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); 1456 buf_pos += HIFN_3DES_KEY_LENGTH; 1457 break; 1458 case HIFN_CRYPT_CMD_ALG_DES: 1459 bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); 1460 buf_pos += cmd->cklen; 1461 break; 1462 case HIFN_CRYPT_CMD_ALG_RC4: 1463 len = 256; 1464 do { 1465 int clen; 1466 1467 clen = MIN(cmd->cklen, len); 1468 bcopy(cmd->ck, buf_pos, clen); 1469 len -= clen; 1470 buf_pos += clen; 1471 } while (len > 0); 1472 bzero(buf_pos, 4); 1473 buf_pos += 4; 1474 break; 1475 } 1476 } 1477 1478 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { 1479 bcopy(cmd->iv, buf_pos, HIFN_IV_LENGTH); 1480 buf_pos += HIFN_IV_LENGTH; 1481 } 1482 1483 if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { 1484 bzero(buf_pos, 8); 1485 buf_pos += 8; 1486 } 1487 1488 return (buf_pos - buf); 1489 #undef MIN 1490 } 1491 1492 static int 1493 hifn_dmamap_aligned(struct hifn_operand *op) 1494 { 1495 int i; 1496 1497 for (i = 0; i < op->nsegs; i++) { 1498 if (op->segs[i].ds_addr & 3) 1499 return (0); 1500 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) 1501 return (0); 1502 } 1503 return (1); 1504 } 1505 1506 static int 1507 hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) 1508 { 1509 struct hifn_dma *dma = sc->sc_dma; 1510 struct hifn_operand *dst = &cmd->dst; 1511 u_int32_t p, l; 1512 int idx, used = 0, i; 1513 1514 idx = dma->dsti; 1515 for (i = 0; i < dst->nsegs - 1; i++) { 1516 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1517 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1518 HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); 1519 HIFN_DSTR_SYNC(sc, idx, 1520 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1521 used++; 1522 1523 if (++idx == HIFN_D_DST_RSIZE) { 1524 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1525 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1526 HIFN_DSTR_SYNC(sc, idx, 1527 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1528 idx = 0; 1529 } 1530 } 1531 1532 if (cmd->sloplen == 0) { 1533 p = dst->segs[i].ds_addr; 1534 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1535 dst->segs[i].ds_len; 1536 } else { 1537 p = sc->sc_dma_physaddr + 1538 offsetof(struct hifn_dma, slop[cmd->slopidx]); 1539 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1540 sizeof(u_int32_t); 1541 1542 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { 1543 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1544 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1545 HIFN_D_MASKDONEIRQ | 1546 (dst->segs[i].ds_len - cmd->sloplen)); 1547 HIFN_DSTR_SYNC(sc, idx, 1548 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1549 used++; 1550 1551 if (++idx == HIFN_D_DST_RSIZE) { 1552 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1553 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1554 HIFN_DSTR_SYNC(sc, idx, 1555 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1556 idx = 0; 1557 } 1558 } 1559 } 1560 dma->dstr[idx].p = htole32(p); 1561 dma->dstr[idx].l = htole32(l); 1562 HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1563 used++; 1564 1565 if (++idx == HIFN_D_DST_RSIZE) { 1566 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | 1567 HIFN_D_MASKDONEIRQ); 1568 HIFN_DSTR_SYNC(sc, idx, 1569 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1570 idx = 0; 1571 } 1572 1573 dma->dsti = idx; 1574 dma->dstu += used; 1575 return (idx); 1576 } 1577 1578 static int 1579 hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) 1580 { 1581 struct hifn_dma *dma = sc->sc_dma; 1582 struct hifn_operand *src = &cmd->src; 1583 int idx, i; 1584 u_int32_t last = 0; 1585 1586 idx = dma->srci; 1587 for (i = 0; i < src->nsegs; i++) { 1588 if (i == src->nsegs - 1) 1589 last = HIFN_D_LAST; 1590 1591 dma->srcr[idx].p = htole32(src->segs[i].ds_addr); 1592 dma->srcr[idx].l = htole32(src->segs[i].ds_len | 1593 HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last); 1594 HIFN_SRCR_SYNC(sc, idx, 1595 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1596 1597 if (++idx == HIFN_D_SRC_RSIZE) { 1598 dma->srcr[idx].l = htole32(HIFN_D_VALID | 1599 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1600 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1601 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1602 idx = 0; 1603 } 1604 } 1605 dma->srci = idx; 1606 dma->srcu += src->nsegs; 1607 return (idx); 1608 } 1609 1610 static void 1611 hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1612 { 1613 struct hifn_operand *op = arg; 1614 1615 KASSERT(nsegs <= MAX_SCATTER, 1616 ("hifn_op_cb: too many DMA segments (%u > %u) " 1617 "returned when mapping operand", nsegs, MAX_SCATTER)); 1618 op->mapsize = mapsize; 1619 op->nsegs = nsegs; 1620 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1621 } 1622 1623 static int 1624 hifn_crypto( 1625 struct hifn_softc *sc, 1626 struct hifn_command *cmd, 1627 struct cryptop *crp, 1628 int hint) 1629 { 1630 struct hifn_dma *dma = sc->sc_dma; 1631 u_int32_t cmdlen; 1632 int cmdi, resi, err = 0; 1633 1634 /* 1635 * need 1 cmd, and 1 res 1636 * 1637 * NB: check this first since it's easy. 1638 */ 1639 if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || 1640 (dma->resu + 1) > HIFN_D_RES_RSIZE) { 1641 #ifdef HIFN_DEBUG 1642 if (hifn_debug) { 1643 device_printf(sc->sc_dev, 1644 "cmd/result exhaustion, cmdu %u resu %u\n", 1645 dma->cmdu, dma->resu); 1646 } 1647 #endif 1648 hifnstats.hst_nomem_cr++; 1649 return (ERESTART); 1650 } 1651 1652 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) { 1653 hifnstats.hst_nomem_map++; 1654 return (ENOMEM); 1655 } 1656 1657 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1658 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map, 1659 cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1660 hifnstats.hst_nomem_load++; 1661 err = ENOMEM; 1662 goto err_srcmap1; 1663 } 1664 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1665 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map, 1666 cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1667 hifnstats.hst_nomem_load++; 1668 err = ENOMEM; 1669 goto err_srcmap1; 1670 } 1671 } else { 1672 err = EINVAL; 1673 goto err_srcmap1; 1674 } 1675 1676 if (hifn_dmamap_aligned(&cmd->src)) { 1677 cmd->sloplen = cmd->src_mapsize & 3; 1678 cmd->dst = cmd->src; 1679 } else { 1680 if (crp->crp_flags & CRYPTO_F_IOV) { 1681 err = EINVAL; 1682 goto err_srcmap; 1683 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1684 int totlen, len; 1685 struct mbuf *m, *m0, *mlast; 1686 1687 KASSERT(cmd->dst_m == cmd->src_m, 1688 ("hifn_crypto: dst_m initialized improperly")); 1689 hifnstats.hst_unaligned++; 1690 /* 1691 * Source is not aligned on a longword boundary. 1692 * Copy the data to insure alignment. If we fail 1693 * to allocate mbufs or clusters while doing this 1694 * we return ERESTART so the operation is requeued 1695 * at the crypto later, but only if there are 1696 * ops already posted to the hardware; otherwise we 1697 * have no guarantee that we'll be re-entered. 1698 */ 1699 totlen = cmd->src_mapsize; 1700 if (cmd->src_m->m_flags & M_PKTHDR) { 1701 len = MHLEN; 1702 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 1703 if (m0 && !m_dup_pkthdr(m0, cmd->src_m, MB_DONTWAIT)) { 1704 m_free(m0); 1705 m0 = NULL; 1706 } 1707 } else { 1708 len = MLEN; 1709 MGET(m0, MB_DONTWAIT, MT_DATA); 1710 } 1711 if (m0 == NULL) { 1712 hifnstats.hst_nomem_mbuf++; 1713 err = dma->cmdu ? ERESTART : ENOMEM; 1714 goto err_srcmap; 1715 } 1716 if (totlen >= MINCLSIZE) { 1717 MCLGET(m0, MB_DONTWAIT); 1718 if ((m0->m_flags & M_EXT) == 0) { 1719 hifnstats.hst_nomem_mcl++; 1720 err = dma->cmdu ? ERESTART : ENOMEM; 1721 m_freem(m0); 1722 goto err_srcmap; 1723 } 1724 len = MCLBYTES; 1725 } 1726 totlen -= len; 1727 m0->m_pkthdr.len = m0->m_len = len; 1728 mlast = m0; 1729 1730 while (totlen > 0) { 1731 MGET(m, MB_DONTWAIT, MT_DATA); 1732 if (m == NULL) { 1733 hifnstats.hst_nomem_mbuf++; 1734 err = dma->cmdu ? ERESTART : ENOMEM; 1735 m_freem(m0); 1736 goto err_srcmap; 1737 } 1738 len = MLEN; 1739 if (totlen >= MINCLSIZE) { 1740 MCLGET(m, MB_DONTWAIT); 1741 if ((m->m_flags & M_EXT) == 0) { 1742 hifnstats.hst_nomem_mcl++; 1743 err = dma->cmdu ? ERESTART : ENOMEM; 1744 mlast->m_next = m; 1745 m_freem(m0); 1746 goto err_srcmap; 1747 } 1748 len = MCLBYTES; 1749 } 1750 1751 m->m_len = len; 1752 m0->m_pkthdr.len += len; 1753 totlen -= len; 1754 1755 mlast->m_next = m; 1756 mlast = m; 1757 } 1758 cmd->dst_m = m0; 1759 } 1760 } 1761 1762 if (cmd->dst_map == NULL) { 1763 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) { 1764 hifnstats.hst_nomem_map++; 1765 err = ENOMEM; 1766 goto err_srcmap; 1767 } 1768 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1769 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map, 1770 cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1771 hifnstats.hst_nomem_map++; 1772 err = ENOMEM; 1773 goto err_dstmap1; 1774 } 1775 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1776 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map, 1777 cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1778 hifnstats.hst_nomem_load++; 1779 err = ENOMEM; 1780 goto err_dstmap1; 1781 } 1782 } 1783 } 1784 1785 #ifdef HIFN_DEBUG 1786 if (hifn_debug) { 1787 device_printf(sc->sc_dev, 1788 "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", 1789 READ_REG_1(sc, HIFN_1_DMA_CSR), 1790 READ_REG_1(sc, HIFN_1_DMA_IER), 1791 dma->cmdu, dma->srcu, dma->dstu, dma->resu, 1792 cmd->src_nsegs, cmd->dst_nsegs); 1793 } 1794 #endif 1795 1796 if (cmd->src_map == cmd->dst_map) { 1797 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1798 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1799 } else { 1800 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1801 BUS_DMASYNC_PREWRITE); 1802 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 1803 BUS_DMASYNC_PREREAD); 1804 } 1805 1806 /* 1807 * need N src, and N dst 1808 */ 1809 if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || 1810 (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { 1811 #ifdef HIFN_DEBUG 1812 if (hifn_debug) { 1813 device_printf(sc->sc_dev, 1814 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", 1815 dma->srcu, cmd->src_nsegs, 1816 dma->dstu, cmd->dst_nsegs); 1817 } 1818 #endif 1819 hifnstats.hst_nomem_sd++; 1820 err = ERESTART; 1821 goto err_dstmap; 1822 } 1823 1824 if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1825 dma->cmdi = 0; 1826 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1827 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1828 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1829 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1830 } 1831 cmdi = dma->cmdi++; 1832 cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); 1833 HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); 1834 1835 /* .p for command/result already set */ 1836 dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST | 1837 HIFN_D_MASKDONEIRQ); 1838 HIFN_CMDR_SYNC(sc, cmdi, 1839 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1840 dma->cmdu++; 1841 if (sc->sc_c_busy == 0) { 1842 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); 1843 sc->sc_c_busy = 1; 1844 } 1845 1846 /* 1847 * We don't worry about missing an interrupt (which a "command wait" 1848 * interrupt salvages us from), unless there is more than one command 1849 * in the queue. 1850 */ 1851 if (dma->cmdu > 1) { 1852 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; 1853 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1854 } 1855 1856 hifnstats.hst_ipackets++; 1857 hifnstats.hst_ibytes += cmd->src_mapsize; 1858 1859 hifn_dmamap_load_src(sc, cmd); 1860 if (sc->sc_s_busy == 0) { 1861 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); 1862 sc->sc_s_busy = 1; 1863 } 1864 1865 /* 1866 * Unlike other descriptors, we don't mask done interrupt from 1867 * result descriptor. 1868 */ 1869 #ifdef HIFN_DEBUG 1870 if (hifn_debug) 1871 printf("load res\n"); 1872 #endif 1873 if (dma->resi == HIFN_D_RES_RSIZE) { 1874 dma->resi = 0; 1875 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1876 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1877 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1879 } 1880 resi = dma->resi++; 1881 KASSERT(dma->hifn_commands[resi] == NULL, 1882 ("hifn_crypto: command slot %u busy", resi)); 1883 dma->hifn_commands[resi] = cmd; 1884 HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); 1885 if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { 1886 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1887 HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 1888 sc->sc_curbatch++; 1889 if (sc->sc_curbatch > hifnstats.hst_maxbatch) 1890 hifnstats.hst_maxbatch = sc->sc_curbatch; 1891 hifnstats.hst_totbatch++; 1892 } else { 1893 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 1894 HIFN_D_VALID | HIFN_D_LAST); 1895 sc->sc_curbatch = 0; 1896 } 1897 HIFN_RESR_SYNC(sc, resi, 1898 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1899 dma->resu++; 1900 if (sc->sc_r_busy == 0) { 1901 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); 1902 sc->sc_r_busy = 1; 1903 } 1904 1905 if (cmd->sloplen) 1906 cmd->slopidx = resi; 1907 1908 hifn_dmamap_load_dst(sc, cmd); 1909 1910 if (sc->sc_d_busy == 0) { 1911 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); 1912 sc->sc_d_busy = 1; 1913 } 1914 1915 #ifdef HIFN_DEBUG 1916 if (hifn_debug) { 1917 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", 1918 READ_REG_1(sc, HIFN_1_DMA_CSR), 1919 READ_REG_1(sc, HIFN_1_DMA_IER)); 1920 } 1921 #endif 1922 1923 sc->sc_active = 5; 1924 KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); 1925 return (err); /* success */ 1926 1927 err_dstmap: 1928 if (cmd->src_map != cmd->dst_map) 1929 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 1930 err_dstmap1: 1931 if (cmd->src_map != cmd->dst_map) 1932 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 1933 err_srcmap: 1934 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1935 if (cmd->src_m != cmd->dst_m) 1936 m_freem(cmd->dst_m); 1937 } 1938 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 1939 err_srcmap1: 1940 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 1941 return (err); 1942 } 1943 1944 static void 1945 hifn_tick(void* vsc) 1946 { 1947 struct hifn_softc *sc = vsc; 1948 int s; 1949 1950 s = splimp(); 1951 if (sc->sc_active == 0) { 1952 struct hifn_dma *dma = sc->sc_dma; 1953 u_int32_t r = 0; 1954 1955 if (dma->cmdu == 0 && sc->sc_c_busy) { 1956 sc->sc_c_busy = 0; 1957 r |= HIFN_DMACSR_C_CTRL_DIS; 1958 } 1959 if (dma->srcu == 0 && sc->sc_s_busy) { 1960 sc->sc_s_busy = 0; 1961 r |= HIFN_DMACSR_S_CTRL_DIS; 1962 } 1963 if (dma->dstu == 0 && sc->sc_d_busy) { 1964 sc->sc_d_busy = 0; 1965 r |= HIFN_DMACSR_D_CTRL_DIS; 1966 } 1967 if (dma->resu == 0 && sc->sc_r_busy) { 1968 sc->sc_r_busy = 0; 1969 r |= HIFN_DMACSR_R_CTRL_DIS; 1970 } 1971 if (r) 1972 WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); 1973 } else 1974 sc->sc_active--; 1975 splx(s); 1976 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 1977 } 1978 1979 static void 1980 hifn_intr(void *arg) 1981 { 1982 struct hifn_softc *sc = arg; 1983 struct hifn_dma *dma; 1984 u_int32_t dmacsr, restart; 1985 int i, u; 1986 1987 dma = sc->sc_dma; 1988 1989 dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); 1990 1991 #ifdef HIFN_DEBUG 1992 if (hifn_debug) { 1993 device_printf(sc->sc_dev, 1994 "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", 1995 dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, 1996 dma->cmdi, dma->srci, dma->dsti, dma->resi, 1997 dma->cmdk, dma->srck, dma->dstk, dma->resk, 1998 dma->cmdu, dma->srcu, dma->dstu, dma->resu); 1999 } 2000 #endif 2001 2002 /* Nothing in the DMA unit interrupted */ 2003 if ((dmacsr & sc->sc_dmaier) == 0) { 2004 hifnstats.hst_noirq++; 2005 return; 2006 } 2007 2008 WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); 2009 2010 if ((sc->sc_flags & HIFN_HAS_PUBLIC) && 2011 (dmacsr & HIFN_DMACSR_PUBDONE)) 2012 WRITE_REG_1(sc, HIFN_1_PUB_STATUS, 2013 READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 2014 2015 restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); 2016 if (restart) 2017 device_printf(sc->sc_dev, "overrun %x\n", dmacsr); 2018 2019 if (sc->sc_flags & HIFN_IS_7811) { 2020 if (dmacsr & HIFN_DMACSR_ILLR) 2021 device_printf(sc->sc_dev, "illegal read\n"); 2022 if (dmacsr & HIFN_DMACSR_ILLW) 2023 device_printf(sc->sc_dev, "illegal write\n"); 2024 } 2025 2026 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 2027 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 2028 if (restart) { 2029 device_printf(sc->sc_dev, "abort, resetting.\n"); 2030 hifnstats.hst_abort++; 2031 hifn_abort(sc); 2032 return; 2033 } 2034 2035 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { 2036 /* 2037 * If no slots to process and we receive a "waiting on 2038 * command" interrupt, we disable the "waiting on command" 2039 * (by clearing it). 2040 */ 2041 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 2042 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2043 } 2044 2045 /* clear the rings */ 2046 i = dma->resk; u = dma->resu; 2047 while (u != 0) { 2048 HIFN_RESR_SYNC(sc, i, 2049 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2050 if (dma->resr[i].l & htole32(HIFN_D_VALID)) { 2051 HIFN_RESR_SYNC(sc, i, 2052 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2053 break; 2054 } 2055 2056 if (i != HIFN_D_RES_RSIZE) { 2057 struct hifn_command *cmd; 2058 u_int8_t *macbuf = NULL; 2059 2060 HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); 2061 cmd = dma->hifn_commands[i]; 2062 KASSERT(cmd != NULL, 2063 ("hifn_intr: null command slot %u", i)); 2064 dma->hifn_commands[i] = NULL; 2065 2066 if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2067 macbuf = dma->result_bufs[i]; 2068 macbuf += 12; 2069 } 2070 2071 hifn_callback(sc, cmd, macbuf); 2072 hifnstats.hst_opackets++; 2073 u--; 2074 } 2075 2076 if (++i == (HIFN_D_RES_RSIZE + 1)) 2077 i = 0; 2078 } 2079 dma->resk = i; dma->resu = u; 2080 2081 i = dma->srck; u = dma->srcu; 2082 while (u != 0) { 2083 if (i == HIFN_D_SRC_RSIZE) 2084 i = 0; 2085 HIFN_SRCR_SYNC(sc, i, 2086 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2087 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { 2088 HIFN_SRCR_SYNC(sc, i, 2089 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2090 break; 2091 } 2092 i++, u--; 2093 } 2094 dma->srck = i; dma->srcu = u; 2095 2096 i = dma->cmdk; u = dma->cmdu; 2097 while (u != 0) { 2098 HIFN_CMDR_SYNC(sc, i, 2099 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2100 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { 2101 HIFN_CMDR_SYNC(sc, i, 2102 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2103 break; 2104 } 2105 if (i != HIFN_D_CMD_RSIZE) { 2106 u--; 2107 HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); 2108 } 2109 if (++i == (HIFN_D_CMD_RSIZE + 1)) 2110 i = 0; 2111 } 2112 dma->cmdk = i; dma->cmdu = u; 2113 2114 if (sc->sc_needwakeup) { /* XXX check high watermark */ 2115 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 2116 #ifdef HIFN_DEBUG 2117 if (hifn_debug) 2118 device_printf(sc->sc_dev, 2119 "wakeup crypto (%x) u %d/%d/%d/%d\n", 2120 sc->sc_needwakeup, 2121 dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2122 #endif 2123 sc->sc_needwakeup &= ~wakeup; 2124 crypto_unblock(sc->sc_cid, wakeup); 2125 } 2126 } 2127 2128 /* 2129 * Allocate a new 'session' and return an encoded session id. 'sidp' 2130 * contains our registration id, and should contain an encoded session 2131 * id on successful allocation. 2132 */ 2133 static int 2134 hifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 2135 { 2136 struct cryptoini *c; 2137 struct hifn_softc *sc = arg; 2138 int i, mac = 0, cry = 0; 2139 2140 KASSERT(sc != NULL, ("hifn_newsession: null softc")); 2141 if (sidp == NULL || cri == NULL || sc == NULL) 2142 return (EINVAL); 2143 2144 for (i = 0; i < sc->sc_maxses; i++) 2145 if (sc->sc_sessions[i].hs_state == HS_STATE_FREE) 2146 break; 2147 if (i == sc->sc_maxses) 2148 return (ENOMEM); 2149 2150 for (c = cri; c != NULL; c = c->cri_next) { 2151 switch (c->cri_alg) { 2152 case CRYPTO_MD5: 2153 case CRYPTO_SHA1: 2154 case CRYPTO_MD5_HMAC: 2155 case CRYPTO_SHA1_HMAC: 2156 if (mac) 2157 return (EINVAL); 2158 mac = 1; 2159 break; 2160 case CRYPTO_DES_CBC: 2161 case CRYPTO_3DES_CBC: 2162 /* XXX this may read fewer, does it matter? */ 2163 read_random(sc->sc_sessions[i].hs_iv, HIFN_IV_LENGTH); 2164 /*FALLTHROUGH*/ 2165 case CRYPTO_ARC4: 2166 if (cry) 2167 return (EINVAL); 2168 cry = 1; 2169 break; 2170 default: 2171 return (EINVAL); 2172 } 2173 } 2174 if (mac == 0 && cry == 0) 2175 return (EINVAL); 2176 2177 *sidp = HIFN_SID(device_get_unit(sc->sc_dev), i); 2178 sc->sc_sessions[i].hs_state = HS_STATE_USED; 2179 2180 return (0); 2181 } 2182 2183 /* 2184 * Deallocate a session. 2185 * XXX this routine should run a zero'd mac/encrypt key into context ram. 2186 * XXX to blow away any keys already stored there. 2187 */ 2188 static int 2189 hifn_freesession(void *arg, u_int64_t tid) 2190 { 2191 struct hifn_softc *sc = arg; 2192 int session; 2193 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 2194 2195 KASSERT(sc != NULL, ("hifn_freesession: null softc")); 2196 if (sc == NULL) 2197 return (EINVAL); 2198 2199 session = HIFN_SESSION(sid); 2200 if (session >= sc->sc_maxses) 2201 return (EINVAL); 2202 2203 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 2204 return (0); 2205 } 2206 2207 static int 2208 hifn_process(void *arg, struct cryptop *crp, int hint) 2209 { 2210 struct hifn_softc *sc = arg; 2211 struct hifn_command *cmd = NULL; 2212 int session, err; 2213 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 2214 2215 if (crp == NULL || crp->crp_callback == NULL) { 2216 hifnstats.hst_invalid++; 2217 return (EINVAL); 2218 } 2219 session = HIFN_SESSION(crp->crp_sid); 2220 2221 if (sc == NULL || session >= sc->sc_maxses) { 2222 err = EINVAL; 2223 goto errout; 2224 } 2225 2226 cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_INTWAIT | M_ZERO); 2227 2228 if (crp->crp_flags & CRYPTO_F_IMBUF) { 2229 cmd->src_m = (struct mbuf *)crp->crp_buf; 2230 cmd->dst_m = (struct mbuf *)crp->crp_buf; 2231 } else if (crp->crp_flags & CRYPTO_F_IOV) { 2232 cmd->src_io = (struct uio *)crp->crp_buf; 2233 cmd->dst_io = (struct uio *)crp->crp_buf; 2234 } else { 2235 err = EINVAL; 2236 goto errout; /* XXX we don't handle contiguous buffers! */ 2237 } 2238 2239 crd1 = crp->crp_desc; 2240 if (crd1 == NULL) { 2241 err = EINVAL; 2242 goto errout; 2243 } 2244 crd2 = crd1->crd_next; 2245 2246 if (crd2 == NULL) { 2247 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 2248 crd1->crd_alg == CRYPTO_SHA1_HMAC || 2249 crd1->crd_alg == CRYPTO_SHA1 || 2250 crd1->crd_alg == CRYPTO_MD5) { 2251 maccrd = crd1; 2252 enccrd = NULL; 2253 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 2254 crd1->crd_alg == CRYPTO_3DES_CBC || 2255 crd1->crd_alg == CRYPTO_ARC4) { 2256 if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) 2257 cmd->base_masks |= HIFN_BASE_CMD_DECODE; 2258 maccrd = NULL; 2259 enccrd = crd1; 2260 } else { 2261 err = EINVAL; 2262 goto errout; 2263 } 2264 } else { 2265 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 2266 crd1->crd_alg == CRYPTO_SHA1_HMAC || 2267 crd1->crd_alg == CRYPTO_MD5 || 2268 crd1->crd_alg == CRYPTO_SHA1) && 2269 (crd2->crd_alg == CRYPTO_DES_CBC || 2270 crd2->crd_alg == CRYPTO_3DES_CBC || 2271 crd2->crd_alg == CRYPTO_ARC4) && 2272 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 2273 cmd->base_masks = HIFN_BASE_CMD_DECODE; 2274 maccrd = crd1; 2275 enccrd = crd2; 2276 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 2277 crd1->crd_alg == CRYPTO_ARC4 || 2278 crd1->crd_alg == CRYPTO_3DES_CBC) && 2279 (crd2->crd_alg == CRYPTO_MD5_HMAC || 2280 crd2->crd_alg == CRYPTO_SHA1_HMAC || 2281 crd2->crd_alg == CRYPTO_MD5 || 2282 crd2->crd_alg == CRYPTO_SHA1) && 2283 (crd1->crd_flags & CRD_F_ENCRYPT)) { 2284 enccrd = crd1; 2285 maccrd = crd2; 2286 } else { 2287 /* 2288 * We cannot order the 7751 as requested 2289 */ 2290 err = EINVAL; 2291 goto errout; 2292 } 2293 } 2294 2295 if (enccrd) { 2296 cmd->enccrd = enccrd; 2297 cmd->base_masks |= HIFN_BASE_CMD_CRYPT; 2298 switch (enccrd->crd_alg) { 2299 case CRYPTO_ARC4: 2300 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; 2301 if ((enccrd->crd_flags & CRD_F_ENCRYPT) 2302 != sc->sc_sessions[session].hs_prev_op) 2303 sc->sc_sessions[session].hs_state = 2304 HS_STATE_USED; 2305 break; 2306 case CRYPTO_DES_CBC: 2307 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | 2308 HIFN_CRYPT_CMD_MODE_CBC | 2309 HIFN_CRYPT_CMD_NEW_IV; 2310 break; 2311 case CRYPTO_3DES_CBC: 2312 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | 2313 HIFN_CRYPT_CMD_MODE_CBC | 2314 HIFN_CRYPT_CMD_NEW_IV; 2315 break; 2316 default: 2317 err = EINVAL; 2318 goto errout; 2319 } 2320 if (enccrd->crd_alg != CRYPTO_ARC4) { 2321 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 2322 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2323 bcopy(enccrd->crd_iv, cmd->iv, 2324 HIFN_IV_LENGTH); 2325 else 2326 bcopy(sc->sc_sessions[session].hs_iv, 2327 cmd->iv, HIFN_IV_LENGTH); 2328 2329 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) 2330 == 0) { 2331 if (crp->crp_flags & CRYPTO_F_IMBUF) 2332 m_copyback(cmd->src_m, 2333 enccrd->crd_inject, 2334 HIFN_IV_LENGTH, cmd->iv); 2335 else if (crp->crp_flags & CRYPTO_F_IOV) 2336 cuio_copyback(cmd->src_io, 2337 enccrd->crd_inject, 2338 HIFN_IV_LENGTH, cmd->iv); 2339 } 2340 } else { 2341 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2342 bcopy(enccrd->crd_iv, cmd->iv, 2343 HIFN_IV_LENGTH); 2344 else if (crp->crp_flags & CRYPTO_F_IMBUF) 2345 m_copydata(cmd->src_m, 2346 enccrd->crd_inject, 2347 HIFN_IV_LENGTH, cmd->iv); 2348 else if (crp->crp_flags & CRYPTO_F_IOV) 2349 cuio_copydata(cmd->src_io, 2350 enccrd->crd_inject, 2351 HIFN_IV_LENGTH, cmd->iv); 2352 } 2353 } 2354 2355 cmd->ck = enccrd->crd_key; 2356 cmd->cklen = enccrd->crd_klen >> 3; 2357 2358 if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2359 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2360 } 2361 2362 if (maccrd) { 2363 cmd->maccrd = maccrd; 2364 cmd->base_masks |= HIFN_BASE_CMD_MAC; 2365 2366 switch (maccrd->crd_alg) { 2367 case CRYPTO_MD5: 2368 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2369 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2370 HIFN_MAC_CMD_POS_IPSEC; 2371 break; 2372 case CRYPTO_MD5_HMAC: 2373 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2374 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2375 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2376 break; 2377 case CRYPTO_SHA1: 2378 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2379 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2380 HIFN_MAC_CMD_POS_IPSEC; 2381 break; 2382 case CRYPTO_SHA1_HMAC: 2383 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2384 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2385 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2386 break; 2387 } 2388 2389 if ((maccrd->crd_alg == CRYPTO_SHA1_HMAC || 2390 maccrd->crd_alg == CRYPTO_MD5_HMAC) && 2391 sc->sc_sessions[session].hs_state == HS_STATE_USED) { 2392 cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; 2393 bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); 2394 bzero(cmd->mac + (maccrd->crd_klen >> 3), 2395 HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); 2396 } 2397 } 2398 2399 cmd->crp = crp; 2400 cmd->session_num = session; 2401 cmd->softc = sc; 2402 2403 err = hifn_crypto(sc, cmd, crp, hint); 2404 if (!err) { 2405 if (enccrd) 2406 sc->sc_sessions[session].hs_prev_op = 2407 enccrd->crd_flags & CRD_F_ENCRYPT; 2408 if (sc->sc_sessions[session].hs_state == HS_STATE_USED) 2409 sc->sc_sessions[session].hs_state = HS_STATE_KEY; 2410 return 0; 2411 } else if (err == ERESTART) { 2412 /* 2413 * There weren't enough resources to dispatch the request 2414 * to the part. Notify the caller so they'll requeue this 2415 * request and resubmit it again soon. 2416 */ 2417 #ifdef HIFN_DEBUG 2418 if (hifn_debug) 2419 device_printf(sc->sc_dev, "requeue request\n"); 2420 #endif 2421 free(cmd, M_DEVBUF); 2422 sc->sc_needwakeup |= CRYPTO_SYMQ; 2423 return (err); 2424 } 2425 2426 errout: 2427 if (cmd != NULL) 2428 free(cmd, M_DEVBUF); 2429 if (err == EINVAL) 2430 hifnstats.hst_invalid++; 2431 else 2432 hifnstats.hst_nomem++; 2433 crp->crp_etype = err; 2434 crypto_done(crp); 2435 return (err); 2436 } 2437 2438 static void 2439 hifn_abort(struct hifn_softc *sc) 2440 { 2441 struct hifn_dma *dma = sc->sc_dma; 2442 struct hifn_command *cmd; 2443 struct cryptop *crp; 2444 int i, u; 2445 2446 i = dma->resk; u = dma->resu; 2447 while (u != 0) { 2448 cmd = dma->hifn_commands[i]; 2449 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); 2450 dma->hifn_commands[i] = NULL; 2451 crp = cmd->crp; 2452 2453 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { 2454 /* Salvage what we can. */ 2455 u_int8_t *macbuf; 2456 2457 if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2458 macbuf = dma->result_bufs[i]; 2459 macbuf += 12; 2460 } else 2461 macbuf = NULL; 2462 hifnstats.hst_opackets++; 2463 hifn_callback(sc, cmd, macbuf); 2464 } else { 2465 if (cmd->src_map == cmd->dst_map) { 2466 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2467 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2468 } else { 2469 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2470 BUS_DMASYNC_POSTWRITE); 2471 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2472 BUS_DMASYNC_POSTREAD); 2473 } 2474 2475 if (cmd->src_m != cmd->dst_m) { 2476 m_freem(cmd->src_m); 2477 crp->crp_buf = (caddr_t)cmd->dst_m; 2478 } 2479 2480 /* non-shared buffers cannot be restarted */ 2481 if (cmd->src_map != cmd->dst_map) { 2482 /* 2483 * XXX should be EAGAIN, delayed until 2484 * after the reset. 2485 */ 2486 crp->crp_etype = ENOMEM; 2487 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2488 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2489 } else 2490 crp->crp_etype = ENOMEM; 2491 2492 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2493 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2494 2495 free(cmd, M_DEVBUF); 2496 if (crp->crp_etype != EAGAIN) 2497 crypto_done(crp); 2498 } 2499 2500 if (++i == HIFN_D_RES_RSIZE) 2501 i = 0; 2502 u--; 2503 } 2504 dma->resk = i; dma->resu = u; 2505 2506 /* Force upload of key next time */ 2507 for (i = 0; i < sc->sc_maxses; i++) 2508 if (sc->sc_sessions[i].hs_state == HS_STATE_KEY) 2509 sc->sc_sessions[i].hs_state = HS_STATE_USED; 2510 2511 hifn_reset_board(sc, 1); 2512 hifn_init_dma(sc); 2513 hifn_init_pci_registers(sc); 2514 } 2515 2516 static void 2517 hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) 2518 { 2519 struct hifn_dma *dma = sc->sc_dma; 2520 struct cryptop *crp = cmd->crp; 2521 struct cryptodesc *crd; 2522 struct mbuf *m; 2523 int totlen, i, u; 2524 2525 if (cmd->src_map == cmd->dst_map) { 2526 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2527 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2528 } else { 2529 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2530 BUS_DMASYNC_POSTWRITE); 2531 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2532 BUS_DMASYNC_POSTREAD); 2533 } 2534 2535 if (crp->crp_flags & CRYPTO_F_IMBUF) { 2536 if (cmd->src_m != cmd->dst_m) { 2537 crp->crp_buf = (caddr_t)cmd->dst_m; 2538 totlen = cmd->src_mapsize; 2539 for (m = cmd->dst_m; m != NULL; m = m->m_next) { 2540 if (totlen < m->m_len) { 2541 m->m_len = totlen; 2542 totlen = 0; 2543 } else 2544 totlen -= m->m_len; 2545 } 2546 cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; 2547 m_freem(cmd->src_m); 2548 } 2549 } 2550 2551 if (cmd->sloplen != 0) { 2552 if (crp->crp_flags & CRYPTO_F_IMBUF) 2553 m_copyback((struct mbuf *)crp->crp_buf, 2554 cmd->src_mapsize - cmd->sloplen, 2555 cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2556 else if (crp->crp_flags & CRYPTO_F_IOV) 2557 cuio_copyback((struct uio *)crp->crp_buf, 2558 cmd->src_mapsize - cmd->sloplen, 2559 cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]); 2560 } 2561 2562 i = dma->dstk; u = dma->dstu; 2563 while (u != 0) { 2564 if (i == HIFN_D_DST_RSIZE) 2565 i = 0; 2566 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2567 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2568 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { 2569 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2570 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2571 break; 2572 } 2573 i++, u--; 2574 } 2575 dma->dstk = i; dma->dstu = u; 2576 2577 hifnstats.hst_obytes += cmd->dst_mapsize; 2578 2579 if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == 2580 HIFN_BASE_CMD_CRYPT) { 2581 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2582 if (crd->crd_alg != CRYPTO_DES_CBC && 2583 crd->crd_alg != CRYPTO_3DES_CBC) 2584 continue; 2585 if (crp->crp_flags & CRYPTO_F_IMBUF) 2586 m_copydata((struct mbuf *)crp->crp_buf, 2587 crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH, 2588 HIFN_IV_LENGTH, 2589 cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2590 else if (crp->crp_flags & CRYPTO_F_IOV) { 2591 cuio_copydata((struct uio *)crp->crp_buf, 2592 crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH, 2593 HIFN_IV_LENGTH, 2594 cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2595 } 2596 break; 2597 } 2598 } 2599 2600 if (macbuf != NULL) { 2601 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2602 int len; 2603 2604 if (crd->crd_alg == CRYPTO_MD5) 2605 len = 16; 2606 else if (crd->crd_alg == CRYPTO_SHA1) 2607 len = 20; 2608 else if (crd->crd_alg == CRYPTO_MD5_HMAC || 2609 crd->crd_alg == CRYPTO_SHA1_HMAC) 2610 len = 12; 2611 else 2612 continue; 2613 2614 if (crp->crp_flags & CRYPTO_F_IMBUF) 2615 m_copyback((struct mbuf *)crp->crp_buf, 2616 crd->crd_inject, len, macbuf); 2617 else if ((crp->crp_flags & CRYPTO_F_IOV) && crp->crp_mac) 2618 bcopy((caddr_t)macbuf, crp->crp_mac, len); 2619 break; 2620 } 2621 } 2622 2623 if (cmd->src_map != cmd->dst_map) { 2624 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2625 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2626 } 2627 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2628 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2629 free(cmd, M_DEVBUF); 2630 crypto_done(crp); 2631 } 2632 2633 /* 2634 * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 2635 * and Group 1 registers; avoid conditions that could create 2636 * burst writes by doing a read in between the writes. 2637 * 2638 * NB: The read we interpose is always to the same register; 2639 * we do this because reading from an arbitrary (e.g. last) 2640 * register may not always work. 2641 */ 2642 static void 2643 hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2644 { 2645 if (sc->sc_flags & HIFN_IS_7811) { 2646 if (sc->sc_bar0_lastreg == reg - 4) 2647 bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG); 2648 sc->sc_bar0_lastreg = reg; 2649 } 2650 bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val); 2651 } 2652 2653 static void 2654 hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2655 { 2656 if (sc->sc_flags & HIFN_IS_7811) { 2657 if (sc->sc_bar1_lastreg == reg - 4) 2658 bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID); 2659 sc->sc_bar1_lastreg = reg; 2660 } 2661 bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val); 2662 } 2663