1 /* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.1.2.1 2002/11/21 23:37:11 sam Exp $ */ 2 /* $DragonFly: src/sys/dev/crypto/hifn/hifn7751reg.h,v 1.3 2007/12/04 09:11:12 hasso Exp $ */ 3 /* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */ 4 5 /*- 6 * Invertex AEON / Hifn 7751 driver 7 * Copyright (c) 1999 Invertex Inc. All rights reserved. 8 * Copyright (c) 1999 Theo de Raadt 9 * Copyright (c) 2000-2001 Network Security Technologies, Inc. 10 * http://www.netsec.net 11 * 12 * Please send any comments, feedback, bug-fixes, or feature requests to 13 * software@invertex.com. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. The name of the author may not be used to endorse or promote products 25 * derived from this software without specific prior written permission. 26 * 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 30 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 31 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 37 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 * 39 * Effort sponsored in part by the Defense Advanced Research Projects 40 * Agency (DARPA) and Air Force Research Laboratory, Air Force 41 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 42 * 43 */ 44 #ifndef __HIFN_H__ 45 #define __HIFN_H__ 46 47 #include <sys/endian.h> 48 49 /* 50 * Some PCI configuration space offset defines. The names were made 51 * identical to the names used by the Linux kernel. 52 */ 53 #ifdef notyet 54 #define HIFN_BAR0 (PCIR_MAPS+0x0) /* PUC register map */ 55 #define HIFN_BAR1 (PCIR_MAPS+0x4) /* DMA register map */ 56 #else 57 #define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */ 58 #define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */ 59 #endif 60 #define HIFN_TRDY_TIMEOUT 0x40 61 #define HIFN_RETRY_TIMEOUT 0x41 62 63 /* 64 * PCI vendor and device identifiers 65 * (the names are preserved from their OpenBSD source). 66 */ 67 #define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ 68 #define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */ 69 #define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ 70 #define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */ 71 #define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */ 72 #define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */ 73 #define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */ 74 75 #define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */ 76 #define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */ 77 78 #define PCI_VENDOR_NETSEC 0x1660 /* NetSec */ 79 #define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */ 80 81 /* 82 * The values below should multiple of 4 -- and be large enough to handle 83 * any command the driver implements. 84 * 85 * MAX_COMMAND = base command + mac command + encrypt command + 86 * mac-key + rc4-key 87 * MAX_RESULT = base result + mac result + mac + encrypt result 88 * 89 * 90 */ 91 #define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) 92 #define HIFN_MAX_RESULT (8 + 4 + 20 + 4) 93 94 /* 95 * hifn_desc_t 96 * 97 * Holds an individual descriptor for any of the rings. 98 */ 99 typedef struct hifn_desc { 100 volatile u_int32_t l; /* length and status bits */ 101 volatile u_int32_t p; 102 } hifn_desc_t; 103 104 /* 105 * Masks for the "length" field of struct hifn_desc. 106 */ 107 #define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ 108 #define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ 109 #define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ 110 #define HIFN_D_OVER 0x08000000 /* overflow */ 111 #define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ 112 #define HIFN_D_JUMP 0x40000000 /* jump descriptor */ 113 #define HIFN_D_VALID 0x80000000 /* valid bit */ 114 115 116 /* 117 * Processing Unit Registers (offset from BASEREG0) 118 */ 119 #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ 120 #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ 121 #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ 122 #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ 123 #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ 124 #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ 125 #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ 126 #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ 127 #define HIFN_0_SPACESIZE 0x20 /* Register space size */ 128 129 /* Processing Unit Control Register (HIFN_0_PUCTRL) */ 130 #define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ 131 #define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ 132 #define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ 133 #define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ 134 #define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ 135 136 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ 137 #define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ 138 #define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ 139 #define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 140 #define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 141 #define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ 142 #define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ 143 #define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ 144 #define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ 145 #define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ 146 #define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ 147 148 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ 149 #define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ 150 #define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ 151 #define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ 152 #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ 153 #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ 154 #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ 155 #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ 156 #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ 157 #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ 158 #define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ 159 #define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ 160 #define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ 161 #define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ 162 #define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ 163 #define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ 164 #define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ 165 #define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ 166 #define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ 167 #define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ 168 #define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ 169 #define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ 170 #define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ 171 #define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ 172 173 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ 174 #define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ 175 #define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ 176 #define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 177 #define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 178 #define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ 179 #define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ 180 #define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ 181 #define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ 182 #define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ 183 #define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ 184 185 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ 186 #define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ 187 #define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ 188 #define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 189 #define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 190 #define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ 191 #define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ 192 #define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ 193 #define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ 194 #define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ 195 #define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ 196 #define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ 197 #define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ 198 #define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ 199 #define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ 200 #define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ 201 #define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ 202 #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ 203 204 /* FIFO Status Register (HIFN_0_FIFOSTAT) */ 205 #define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ 206 #define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ 207 208 /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ 209 #define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */ 210 211 /* 212 * DMA Interface Registers (offset from BASEREG1) 213 */ 214 #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ 215 #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ 216 #define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ 217 #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ 218 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ 219 #define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ 220 #define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ 221 #define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */ 222 #define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ 223 #define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ 224 #define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ 225 #define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ 226 #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ 227 #define HIFN_1_REVID 0x98 /* Revision ID */ 228 229 #define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ 230 #define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ 231 #define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */ 232 #define HIFN_1_PUB_OP 0x308 /* Public Operand */ 233 #define HIFN_1_PUB_STATUS 0x30c /* Public Status */ 234 #define HIFN_1_PUB_IEN 0x310 /* Public Interrupt nable */ 235 #define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ 236 #define HIFN_1_RNG_DATA 0x318 /* RNG data */ 237 #define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ 238 #define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ 239 240 /* DMA Status and Control Register (HIFN_1_DMA_CSR) */ 241 #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ 242 #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ 243 #define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ 244 #define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ 245 #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ 246 #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ 247 #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ 248 #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ 249 #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ 250 #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ 251 #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ 252 #define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ 253 #define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ 254 #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ 255 #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ 256 #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ 257 #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ 258 #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ 259 #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ 260 #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ 261 #define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ 262 #define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ 263 #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ 264 #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ 265 #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ 266 #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ 267 #define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ 268 #define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ 269 #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ 270 #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ 271 #define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ 272 #define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ 273 #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ 274 #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ 275 #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ 276 #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ 277 #define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ 278 #define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ 279 280 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ 281 #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ 282 #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ 283 #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ 284 #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ 285 #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ 286 #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ 287 #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ 288 #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ 289 #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ 290 #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ 291 #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ 292 #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ 293 #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ 294 #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ 295 #define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ 296 #define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ 297 #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ 298 #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ 299 #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ 300 #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ 301 #define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ 302 #define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ 303 304 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */ 305 #define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ 306 #define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ 307 #define HIFN_DMACNFG_UNLOCK 0x00000800 308 #define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ 309 #define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ 310 #define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ 311 #define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ 312 #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ 313 314 /* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ 315 #define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ 316 317 /* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */ 318 #define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */ 319 #define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */ 320 #define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */ 321 322 /* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */ 323 #define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */ 324 #define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */ 325 326 /* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */ 327 #define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */ 328 #define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */ 329 #define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */ 330 #define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */ 331 #define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */ 332 #define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */ 333 #define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */ 334 #define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */ 335 #define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */ 336 337 /* Public key reset register (HIFN_1_PUB_RESET) */ 338 #define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ 339 340 /* Public operation register (HIFN_1_PUB_OP) */ 341 #define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */ 342 #define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */ 343 #define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */ 344 #define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ 345 #define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ 346 #define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ 347 #define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ 348 #define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ 349 #define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ 350 #define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ 351 #define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ 352 #define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ 353 #define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ 354 #define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ 355 #define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ 356 #define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */ 357 #define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */ 358 359 /* Public operand length register (HIFN_1_PUB_OPLEN) */ 360 #define HIFN_PUBOPLEN_MODLEN 0x0000007f 361 #define HIFN_PUBOPLEN_EXPLEN 0x0003ff80 362 #define HIFN_PUBOPLEN_REDLEN 0x003c0000 363 364 /* Public status register (HIFN_1_PUB_STATUS) */ 365 #define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ 366 #define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ 367 368 /* Public interrupt enable register (HIFN_1_PUB_IEN) */ 369 #define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ 370 371 /* Random number generator config register (HIFN_1_RNG_CONFIG) */ 372 #define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ 373 374 /* 375 * Register offsets in register set 1 376 */ 377 378 #define HIFN_UNLOCK_SECRET1 0xf4 379 #define HIFN_UNLOCK_SECRET2 0xfc 380 381 /* 382 * PLL config register 383 * 384 * This register is present only on 7954/7955/7956 parts. It must be 385 * programmed according to the bus interface method used by the h/w. 386 * Note that the parts require a stable clock. Since the PCI clock 387 * may vary the reference clock must usually be used. To avoid 388 * overclocking the core logic, setup must be done carefully, refer 389 * to the driver for details. The exact multiplier required varies 390 * by part and system configuration; refer to the Hifn documentation. 391 */ 392 #define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */ 393 #define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */ 394 /* bit 2 reserved */ 395 #define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */ 396 #define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */ 397 /* bits 5-9 reserved */ 398 #define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */ 399 #define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */ 400 #define HIFN_PLL_ND_SHIFT 11 401 #define HIFN_PLL_ND_2 0x00000000 /* 2x */ 402 #define HIFN_PLL_ND_4 0x00000800 /* 4x */ 403 #define HIFN_PLL_ND_6 0x00001000 /* 6x */ 404 #define HIFN_PLL_ND_8 0x00001800 /* 8x */ 405 #define HIFN_PLL_ND_10 0x00002000 /* 10x */ 406 #define HIFN_PLL_ND_12 0x00002800 /* 12x */ 407 /* bits 14-15 reserved */ 408 #define HIFN_PLL_IS 0x00010000 /* charge pump current select */ 409 /* bits 17-31 reserved */ 410 411 /* 412 * Board configuration specifies only these bits. 413 */ 414 #define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL) 415 416 /********************************************************************* 417 * Structs for board commands 418 * 419 *********************************************************************/ 420 421 /* 422 * Structure to help build up the command data structure. 423 */ 424 typedef struct hifn_base_command { 425 volatile u_int16_t masks; 426 volatile u_int16_t session_num; 427 volatile u_int16_t total_source_count; 428 volatile u_int16_t total_dest_count; 429 } hifn_base_command_t; 430 431 #define HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */ 432 #define HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */ 433 #define HIFN_BASE_CMD_MAC 0x0400 434 #define HIFN_BASE_CMD_CRYPT 0x0800 435 #define HIFN_BASE_CMD_DECODE 0x2000 436 #define HIFN_BASE_CMD_SRCLEN_M 0xc000 437 #define HIFN_BASE_CMD_SRCLEN_S 14 438 #define HIFN_BASE_CMD_DSTLEN_M 0x3000 439 #define HIFN_BASE_CMD_DSTLEN_S 12 440 #define HIFN_BASE_CMD_LENMASK_HI 0x30000 441 #define HIFN_BASE_CMD_LENMASK_LO 0x0ffff 442 443 /* 444 * Structure to help build up the command data structure. 445 */ 446 typedef struct hifn_crypt_command { 447 volatile u_int16_t masks; 448 volatile u_int16_t header_skip; 449 volatile u_int16_t source_count; 450 volatile u_int16_t reserved; 451 } hifn_crypt_command_t; 452 453 #define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ 454 #define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ 455 #define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ 456 #define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ 457 #define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ 458 #define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt/DES mode: */ 459 #define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ 460 #define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ 461 #define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ 462 #define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ 463 #define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ 464 #define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ 465 #define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ 466 467 #define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 468 #define HIFN_CRYPT_CMD_SRCLEN_S 14 469 470 #define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ 471 #define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ 472 #define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ 473 #define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ 474 475 /* 476 * Structure to help build up the command data structure. 477 */ 478 typedef struct hifn_mac_command { 479 volatile u_int16_t masks; 480 volatile u_int16_t header_skip; 481 volatile u_int16_t source_count; 482 volatile u_int16_t reserved; 483 } hifn_mac_command_t; 484 485 #define HIFN_MAC_CMD_ALG_MASK 0x0001 486 #define HIFN_MAC_CMD_ALG_SHA1 0x0000 487 #define HIFN_MAC_CMD_ALG_MD5 0x0001 488 #define HIFN_MAC_CMD_MODE_MASK 0x000c 489 #define HIFN_MAC_CMD_MODE_HMAC 0x0000 490 #define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 491 #define HIFN_MAC_CMD_MODE_HASH 0x0008 492 #define HIFN_MAC_CMD_MODE_FULL 0x0004 493 #define HIFN_MAC_CMD_TRUNC 0x0010 494 #define HIFN_MAC_CMD_RESULT 0x0020 495 #define HIFN_MAC_CMD_APPEND 0x0040 496 #define HIFN_MAC_CMD_SRCLEN_M 0xc000 497 #define HIFN_MAC_CMD_SRCLEN_S 14 498 499 /* 500 * MAC POS IPsec initiates authentication after encryption on encodes 501 * and before decryption on decodes. 502 */ 503 #define HIFN_MAC_CMD_POS_IPSEC 0x0200 504 #define HIFN_MAC_CMD_NEW_KEY 0x0800 505 506 struct hifn_comp_command { 507 volatile u_int16_t masks; 508 volatile u_int16_t header_skip; 509 volatile u_int16_t source_count; 510 volatile u_int16_t reserved; 511 }; 512 513 #define HIFN_COMP_CMD_SRCLEN_M 0xc000 514 #define HIFN_COMP_CMD_SRCLEN_S 14 515 #define HIFN_COMP_CMD_ONE 0x0100 /* must be one */ 516 #define HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */ 517 #define HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */ 518 #define HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */ 519 #define HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */ 520 #define HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */ 521 #define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */ 522 #define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */ 523 524 struct hifn_base_result { 525 volatile u_int16_t flags; 526 volatile u_int16_t session; 527 volatile u_int16_t src_cnt; /* 15:0 of source count */ 528 volatile u_int16_t dst_cnt; /* 15:0 of dest count */ 529 }; 530 531 #define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */ 532 #define HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */ 533 #define HIFN_BASE_RES_SRCLEN_S 14 534 #define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */ 535 #define HIFN_BASE_RES_DSTLEN_S 12 536 537 struct hifn_comp_result { 538 volatile u_int16_t flags; 539 volatile u_int16_t crc; 540 }; 541 542 #define HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */ 543 #define HIFN_COMP_RES_LCB_S 8 544 #define HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */ 545 #define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */ 546 #define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */ 547 548 struct hifn_mac_result { 549 volatile u_int16_t flags; 550 volatile u_int16_t reserved; 551 /* followed by 0, 6, 8, or 10 u_int16_t's of the MAC, then crypt */ 552 }; 553 554 #define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */ 555 #define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */ 556 557 struct hifn_crypt_result { 558 volatile u_int16_t flags; 559 volatile u_int16_t reserved; 560 }; 561 562 #define HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */ 563 564 /* 565 * The poll frequency and poll scalar defines are unshifted values used 566 * to set fields in the DMA Configuration Register. 567 */ 568 #ifndef HIFN_POLL_FREQUENCY 569 #define HIFN_POLL_FREQUENCY 0x1 570 #endif 571 572 #ifndef HIFN_POLL_SCALAR 573 #define HIFN_POLL_SCALAR 0x0 574 #endif 575 576 #define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ 577 #define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ 578 #endif /* __HIFN_H__ */ 579