1 /*- 2 * Copyright (c) 2003 Sam Leffler, Errno Consulting 3 * Copyright (c) 2003 Global Technology Associates, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/safe/safe.c,v 1.22 2011/06/12 23:33:08 delphij Exp $ 28 */ 29 30 /* 31 * SafeNet SafeXcel-1141 hardware crypto accelerator 32 */ 33 #include "opt_safe.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/proc.h> 38 #include <sys/errno.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/mbuf.h> 42 #include <sys/module.h> 43 #include <sys/lock.h> 44 #include <sys/sysctl.h> 45 #include <sys/endian.h> 46 47 #include <vm/vm.h> 48 #include <vm/pmap.h> 49 50 #include <sys/bus.h> 51 #include <sys/rman.h> 52 53 #include <crypto/sha1.h> 54 #include <opencrypto/cryptodev.h> 55 #include <opencrypto/cryptosoft.h> 56 #include <sys/md5.h> 57 #include <sys/random.h> 58 #include <sys/kobj.h> 59 60 #include "cryptodev_if.h" 61 62 #include <bus/pci/pcivar.h> 63 #include <bus/pci/pcireg.h> 64 65 #ifdef SAFE_RNDTEST 66 #include <dev/crypto/rndtest/rndtest.h> 67 #endif 68 #include <dev/crypto/safe/safereg.h> 69 #include <dev/crypto/safe/safevar.h> 70 71 #ifndef bswap32 72 #define bswap32 NTOHL 73 #endif 74 75 /* 76 * Prototypes and count for the pci_device structure 77 */ 78 static int safe_probe(device_t); 79 static int safe_attach(device_t); 80 static int safe_detach(device_t); 81 static int safe_suspend(device_t); 82 static int safe_resume(device_t); 83 static int safe_shutdown(device_t); 84 85 static int safe_newsession(device_t, u_int32_t *, struct cryptoini *); 86 static int safe_freesession(device_t, u_int64_t); 87 static int safe_process(device_t, struct cryptop *, int); 88 89 static device_method_t safe_methods[] = { 90 /* Device interface */ 91 DEVMETHOD(device_probe, safe_probe), 92 DEVMETHOD(device_attach, safe_attach), 93 DEVMETHOD(device_detach, safe_detach), 94 DEVMETHOD(device_suspend, safe_suspend), 95 DEVMETHOD(device_resume, safe_resume), 96 DEVMETHOD(device_shutdown, safe_shutdown), 97 98 /* bus interface */ 99 DEVMETHOD(bus_print_child, bus_generic_print_child), 100 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 101 102 /* crypto device methods */ 103 DEVMETHOD(cryptodev_newsession, safe_newsession), 104 DEVMETHOD(cryptodev_freesession,safe_freesession), 105 DEVMETHOD(cryptodev_process, safe_process), 106 107 DEVMETHOD_END 108 }; 109 static driver_t safe_driver = { 110 "safe", 111 safe_methods, 112 sizeof (struct safe_softc) 113 }; 114 static devclass_t safe_devclass; 115 116 DRIVER_MODULE(safe, pci, safe_driver, safe_devclass, NULL, NULL); 117 MODULE_DEPEND(safe, crypto, 1, 1, 1); 118 #ifdef SAFE_RNDTEST 119 MODULE_DEPEND(safe, rndtest, 1, 1, 1); 120 #endif 121 122 static void safe_intr(void *); 123 static void safe_callback(struct safe_softc *, struct safe_ringentry *); 124 static void safe_feed(struct safe_softc *, struct safe_ringentry *); 125 static void safe_mcopy(struct mbuf *, struct mbuf *, u_int); 126 #ifndef SAFE_NO_RNG 127 static void safe_rng_init(struct safe_softc *); 128 static void safe_rng(void *); 129 #endif /* SAFE_NO_RNG */ 130 static int safe_dma_malloc(struct safe_softc *, bus_size_t, 131 struct safe_dma_alloc *, int); 132 #define safe_dma_sync(_dma, _flags) \ 133 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 134 static void safe_dma_free(struct safe_softc *, struct safe_dma_alloc *); 135 static int safe_dmamap_aligned(const struct safe_operand *); 136 static int safe_dmamap_uniform(const struct safe_operand *); 137 138 static void safe_reset_board(struct safe_softc *); 139 static void safe_init_board(struct safe_softc *); 140 static void safe_init_pciregs(device_t dev); 141 static void safe_cleanchip(struct safe_softc *); 142 static void safe_totalreset(struct safe_softc *); 143 144 static int safe_free_entry(struct safe_softc *, struct safe_ringentry *); 145 146 SYSCTL_NODE(_hw, OID_AUTO, safe, CTLFLAG_RD, 0, "SafeNet driver parameters"); 147 148 #ifdef SAFE_DEBUG 149 static void safe_dump_dmastatus(struct safe_softc *, const char *); 150 static void safe_dump_ringstate(struct safe_softc *, const char *); 151 static void safe_dump_intrstate(struct safe_softc *, const char *); 152 static void safe_dump_request(struct safe_softc *, const char *, 153 struct safe_ringentry *); 154 155 static struct safe_softc *safec; /* for use by hw.safe.dump */ 156 157 static int safe_debug = 0; 158 SYSCTL_INT(_hw_safe, OID_AUTO, debug, CTLFLAG_RW, &safe_debug, 159 0, "control debugging msgs"); 160 #define DPRINTF(_x) if (safe_debug) kprintf _x 161 #else 162 #define DPRINTF(_x) 163 #endif 164 165 #define READ_REG(sc,r) \ 166 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 167 168 #define WRITE_REG(sc,reg,val) \ 169 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 170 171 struct safe_stats safestats; 172 SYSCTL_STRUCT(_hw_safe, OID_AUTO, stats, CTLFLAG_RD, &safestats, 173 safe_stats, "driver statistics"); 174 #ifndef SAFE_NO_RNG 175 static int safe_rnginterval = 1; /* poll once a second */ 176 SYSCTL_INT(_hw_safe, OID_AUTO, rnginterval, CTLFLAG_RW, &safe_rnginterval, 177 0, "RNG polling interval (secs)"); 178 static int safe_rngbufsize = 16; /* 64 bytes each poll */ 179 SYSCTL_INT(_hw_safe, OID_AUTO, rngbufsize, CTLFLAG_RW, &safe_rngbufsize, 180 0, "RNG polling buffer size (32-bit words)"); 181 static int safe_rngmaxalarm = 8; /* max alarms before reset */ 182 SYSCTL_INT(_hw_safe, OID_AUTO, rngmaxalarm, CTLFLAG_RW, &safe_rngmaxalarm, 183 0, "RNG max alarms before reset"); 184 #endif /* SAFE_NO_RNG */ 185 186 static int 187 safe_probe(device_t dev) 188 { 189 if (pci_get_vendor(dev) == PCI_VENDOR_SAFENET && 190 pci_get_device(dev) == PCI_PRODUCT_SAFEXCEL) 191 return (BUS_PROBE_DEFAULT); 192 return (ENXIO); 193 } 194 195 static const char* 196 safe_partname(struct safe_softc *sc) 197 { 198 /* XXX sprintf numbers when not decoded */ 199 switch (pci_get_vendor(sc->sc_dev)) { 200 case PCI_VENDOR_SAFENET: 201 switch (pci_get_device(sc->sc_dev)) { 202 case PCI_PRODUCT_SAFEXCEL: return "SafeNet SafeXcel-1141"; 203 } 204 return "SafeNet unknown-part"; 205 } 206 return "Unknown-vendor unknown-part"; 207 } 208 209 #ifndef SAFE_NO_RNG 210 static void 211 default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 212 { 213 add_buffer_randomness_src(buf, count, RAND_SRC_SAFE); 214 } 215 #endif /* SAFE_NO_RNG */ 216 217 static int 218 safe_attach(device_t dev) 219 { 220 struct safe_softc *sc = device_get_softc(dev); 221 u_int32_t raddr; 222 u_int32_t cmd, i, devinfo; 223 int rid; 224 225 bzero(sc, sizeof (*sc)); 226 sc->sc_dev = dev; 227 228 /* XXX handle power management */ 229 230 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 231 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 232 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 233 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 234 235 if (!(cmd & PCIM_CMD_MEMEN)) { 236 device_printf(dev, "failed to enable memory mapping\n"); 237 goto bad; 238 } 239 240 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 241 device_printf(dev, "failed to enable bus mastering\n"); 242 goto bad; 243 } 244 245 /* 246 * Setup memory-mapping of PCI registers. 247 */ 248 rid = BS_BAR; 249 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 250 RF_ACTIVE); 251 if (sc->sc_sr == NULL) { 252 device_printf(dev, "cannot map register space\n"); 253 goto bad; 254 } 255 sc->sc_st = rman_get_bustag(sc->sc_sr); 256 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 257 258 /* 259 * Arrange interrupt line. 260 */ 261 rid = 0; 262 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 263 RF_SHAREABLE|RF_ACTIVE); 264 if (sc->sc_irq == NULL) { 265 device_printf(dev, "could not map interrupt\n"); 266 goto bad1; 267 } 268 /* 269 * NB: Network code assumes we are blocked with splimp() 270 * so make sure the IRQ is mapped appropriately. 271 */ 272 if (bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, 273 safe_intr, sc, &sc->sc_ih, NULL)) { 274 device_printf(dev, "could not establish interrupt\n"); 275 goto bad2; 276 } 277 278 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); 279 if (sc->sc_cid < 0) { 280 device_printf(dev, "could not get crypto driver id\n"); 281 goto bad3; 282 } 283 284 sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & 285 (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); 286 287 /* 288 * Setup DMA descriptor area. 289 */ 290 if (bus_dma_tag_create(NULL, /* parent */ 291 1, /* alignment */ 292 SAFE_DMA_BOUNDARY, /* boundary */ 293 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 294 BUS_SPACE_MAXADDR, /* highaddr */ 295 NULL, NULL, /* filter, filterarg */ 296 SAFE_MAX_DMA, /* maxsize */ 297 SAFE_MAX_PART, /* nsegments */ 298 SAFE_MAX_SSIZE, /* maxsegsize */ 299 BUS_DMA_ALLOCNOW, /* flags */ 300 &sc->sc_srcdmat)) { 301 device_printf(dev, "cannot allocate DMA tag\n"); 302 goto bad4; 303 } 304 if (bus_dma_tag_create(NULL, /* parent */ 305 1, /* alignment */ 306 SAFE_MAX_DSIZE, /* boundary */ 307 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 308 BUS_SPACE_MAXADDR, /* highaddr */ 309 NULL, NULL, /* filter, filterarg */ 310 SAFE_MAX_DMA, /* maxsize */ 311 SAFE_MAX_PART, /* nsegments */ 312 SAFE_MAX_DSIZE, /* maxsegsize */ 313 BUS_DMA_ALLOCNOW, /* flags */ 314 &sc->sc_dstdmat)) { 315 device_printf(dev, "cannot allocate DMA tag\n"); 316 goto bad4; 317 } 318 319 /* 320 * Allocate packet engine descriptors. 321 */ 322 if (safe_dma_malloc(sc, 323 SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), 324 &sc->sc_ringalloc, 0)) { 325 device_printf(dev, "cannot allocate PE descriptor ring\n"); 326 bus_dma_tag_destroy(sc->sc_srcdmat); 327 goto bad4; 328 } 329 /* 330 * Hookup the static portion of all our data structures. 331 */ 332 sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; 333 sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; 334 sc->sc_front = sc->sc_ring; 335 sc->sc_back = sc->sc_ring; 336 raddr = sc->sc_ringalloc.dma_paddr; 337 bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); 338 for (i = 0; i < SAFE_MAX_NQUEUE; i++) { 339 struct safe_ringentry *re = &sc->sc_ring[i]; 340 341 re->re_desc.d_sa = raddr + 342 offsetof(struct safe_ringentry, re_sa); 343 re->re_sa.sa_staterec = raddr + 344 offsetof(struct safe_ringentry, re_sastate); 345 346 raddr += sizeof (struct safe_ringentry); 347 } 348 lockinit(&sc->sc_ringlock, "packet engine ring", 0, LK_CANRECURSE); 349 350 /* 351 * Allocate scatter and gather particle descriptors. 352 */ 353 if (safe_dma_malloc(sc, SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), 354 &sc->sc_spalloc, 0)) { 355 device_printf(dev, "cannot allocate source particle " 356 "descriptor ring\n"); 357 lockuninit(&sc->sc_ringlock); 358 safe_dma_free(sc, &sc->sc_ringalloc); 359 bus_dma_tag_destroy(sc->sc_srcdmat); 360 goto bad4; 361 } 362 sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; 363 sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; 364 sc->sc_spfree = sc->sc_spring; 365 bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); 366 367 if (safe_dma_malloc(sc, SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), 368 &sc->sc_dpalloc, 0)) { 369 device_printf(dev, "cannot allocate destination particle " 370 "descriptor ring\n"); 371 lockuninit(&sc->sc_ringlock); 372 safe_dma_free(sc, &sc->sc_spalloc); 373 safe_dma_free(sc, &sc->sc_ringalloc); 374 bus_dma_tag_destroy(sc->sc_dstdmat); 375 goto bad4; 376 } 377 sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; 378 sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; 379 sc->sc_dpfree = sc->sc_dpring; 380 bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); 381 382 device_printf(sc->sc_dev, "%s", safe_partname(sc)); 383 384 devinfo = READ_REG(sc, SAFE_DEVINFO); 385 if (devinfo & SAFE_DEVINFO_RNG) { 386 sc->sc_flags |= SAFE_FLAGS_RNG; 387 kprintf(" rng"); 388 } 389 if (devinfo & SAFE_DEVINFO_PKEY) { 390 #if 0 391 kprintf(" key"); 392 sc->sc_flags |= SAFE_FLAGS_KEY; 393 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); 394 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); 395 #endif 396 } 397 if (devinfo & SAFE_DEVINFO_DES) { 398 kprintf(" des/3des"); 399 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); 400 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); 401 } 402 if (devinfo & SAFE_DEVINFO_AES) { 403 kprintf(" aes"); 404 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); 405 } 406 if (devinfo & SAFE_DEVINFO_MD5) { 407 kprintf(" md5"); 408 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); 409 } 410 if (devinfo & SAFE_DEVINFO_SHA1) { 411 kprintf(" sha1"); 412 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); 413 } 414 kprintf(" null"); 415 crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0); 416 crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0); 417 /* XXX other supported algorithms */ 418 kprintf("\n"); 419 420 safe_reset_board(sc); /* reset h/w */ 421 safe_init_pciregs(dev); /* init pci settings */ 422 safe_init_board(sc); /* init h/w */ 423 424 #ifndef SAFE_NO_RNG 425 if (sc->sc_flags & SAFE_FLAGS_RNG) { 426 #ifdef SAFE_RNDTEST 427 sc->sc_rndtest = rndtest_attach(dev); 428 if (sc->sc_rndtest) 429 sc->sc_harvest = rndtest_harvest; 430 else 431 sc->sc_harvest = default_harvest; 432 #else 433 sc->sc_harvest = default_harvest; 434 #endif 435 safe_rng_init(sc); 436 437 callout_init_mp(&sc->sc_rngto); 438 callout_reset(&sc->sc_rngto, hz*safe_rnginterval, safe_rng, sc); 439 } 440 #endif /* SAFE_NO_RNG */ 441 #ifdef SAFE_DEBUG 442 safec = sc; /* for use by hw.safe.dump */ 443 #endif 444 return (0); 445 bad4: 446 crypto_unregister_all(sc->sc_cid); 447 bad3: 448 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 449 bad2: 450 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 451 bad1: 452 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 453 bad: 454 return (ENXIO); 455 } 456 457 /* 458 * Detach a device that successfully probed. 459 */ 460 static int 461 safe_detach(device_t dev) 462 { 463 struct safe_softc *sc = device_get_softc(dev); 464 465 /* XXX wait/abort active ops */ 466 467 WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ 468 469 callout_stop(&sc->sc_rngto); 470 471 crypto_unregister_all(sc->sc_cid); 472 473 #ifdef SAFE_RNDTEST 474 if (sc->sc_rndtest) 475 rndtest_detach(sc->sc_rndtest); 476 #endif 477 478 safe_cleanchip(sc); 479 safe_dma_free(sc, &sc->sc_dpalloc); 480 safe_dma_free(sc, &sc->sc_spalloc); 481 lockuninit(&sc->sc_ringlock); 482 safe_dma_free(sc, &sc->sc_ringalloc); 483 484 bus_generic_detach(dev); 485 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 486 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 487 488 bus_dma_tag_destroy(sc->sc_srcdmat); 489 bus_dma_tag_destroy(sc->sc_dstdmat); 490 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 491 492 return (0); 493 } 494 495 /* 496 * Stop all chip i/o so that the kernel's probe routines don't 497 * get confused by errant DMAs when rebooting. 498 */ 499 static int 500 safe_shutdown(device_t dev) 501 { 502 #ifdef notyet 503 safe_stop(device_get_softc(dev)); 504 #endif 505 return (0); 506 } 507 508 /* 509 * Device suspend routine. 510 */ 511 static int 512 safe_suspend(device_t dev) 513 { 514 struct safe_softc *sc = device_get_softc(dev); 515 516 #ifdef notyet 517 /* XXX stop the device and save PCI settings */ 518 #endif 519 sc->sc_suspended = 1; 520 521 return (0); 522 } 523 524 static int 525 safe_resume(device_t dev) 526 { 527 struct safe_softc *sc = device_get_softc(dev); 528 529 #ifdef notyet 530 /* XXX retore PCI settings and start the device */ 531 #endif 532 sc->sc_suspended = 0; 533 return (0); 534 } 535 536 /* 537 * SafeXcel Interrupt routine 538 */ 539 static void 540 safe_intr(void *arg) 541 { 542 struct safe_softc *sc = arg; 543 volatile u_int32_t stat; 544 545 stat = READ_REG(sc, SAFE_HM_STAT); 546 if (stat == 0) /* shared irq, not for us */ 547 return; 548 549 WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ 550 551 if ((stat & SAFE_INT_PE_DDONE)) { 552 /* 553 * Descriptor(s) done; scan the ring and 554 * process completed operations. 555 */ 556 lockmgr(&sc->sc_ringlock, LK_EXCLUSIVE); 557 while (sc->sc_back != sc->sc_front) { 558 struct safe_ringentry *re = sc->sc_back; 559 #ifdef SAFE_DEBUG 560 if (safe_debug) { 561 safe_dump_ringstate(sc, __func__); 562 safe_dump_request(sc, __func__, re); 563 } 564 #endif 565 /* 566 * safe_process marks ring entries that were allocated 567 * but not used with a csr of zero. This insures the 568 * ring front pointer never needs to be set backwards 569 * in the event that an entry is allocated but not used 570 * because of a setup error. 571 */ 572 if (re->re_desc.d_csr != 0) { 573 if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) 574 break; 575 if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) 576 break; 577 sc->sc_nqchip--; 578 safe_callback(sc, re); 579 } 580 if (++(sc->sc_back) == sc->sc_ringtop) 581 sc->sc_back = sc->sc_ring; 582 } 583 lockmgr(&sc->sc_ringlock, LK_RELEASE); 584 } 585 586 /* 587 * Check to see if we got any DMA Error 588 */ 589 if (stat & SAFE_INT_PE_ERROR) { 590 DPRINTF(("dmaerr dmastat %08x\n", 591 READ_REG(sc, SAFE_PE_DMASTAT))); 592 safestats.st_dmaerr++; 593 safe_totalreset(sc); 594 #if 0 595 safe_feed(sc); 596 #endif 597 } 598 599 if (sc->sc_needwakeup) { /* XXX check high watermark */ 600 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 601 DPRINTF(("%s: wakeup crypto %x\n", __func__, 602 sc->sc_needwakeup)); 603 sc->sc_needwakeup &= ~wakeup; 604 crypto_unblock(sc->sc_cid, wakeup); 605 } 606 } 607 608 /* 609 * safe_feed() - post a request to chip 610 */ 611 static void 612 safe_feed(struct safe_softc *sc, struct safe_ringentry *re) 613 { 614 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_PREWRITE); 615 if (re->re_dst_map != NULL) 616 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 617 BUS_DMASYNC_PREREAD); 618 /* XXX have no smaller granularity */ 619 safe_dma_sync(&sc->sc_ringalloc, 620 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 621 safe_dma_sync(&sc->sc_spalloc, BUS_DMASYNC_PREWRITE); 622 safe_dma_sync(&sc->sc_dpalloc, BUS_DMASYNC_PREWRITE); 623 624 #ifdef SAFE_DEBUG 625 if (safe_debug) { 626 safe_dump_ringstate(sc, __func__); 627 safe_dump_request(sc, __func__, re); 628 } 629 #endif 630 sc->sc_nqchip++; 631 if (sc->sc_nqchip > safestats.st_maxqchip) 632 safestats.st_maxqchip = sc->sc_nqchip; 633 /* poke h/w to check descriptor ring, any value can be written */ 634 WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); 635 } 636 637 static void 638 safe_setup_enckey(struct safe_session *ses, caddr_t key) 639 { 640 int i; 641 642 bcopy(key, ses->ses_key, ses->ses_klen / 8); 643 644 /* PE is little-endian, insure proper byte order */ 645 for (i = 0; i < nitems(ses->ses_key); i++) 646 ses->ses_key[i] = htole32(ses->ses_key[i]); 647 } 648 649 static void 650 safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) 651 { 652 MD5_CTX md5ctx; 653 SHA1_CTX sha1ctx; 654 int i; 655 656 657 for (i = 0; i < klen; i++) 658 key[i] ^= HMAC_IPAD_VAL; 659 660 if (algo == CRYPTO_MD5_HMAC) { 661 MD5Init(&md5ctx); 662 MD5Update(&md5ctx, key, klen); 663 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); 664 /* gcc8 craps out on -Warray-bounds w/ optimized bcopy */ 665 _bcopy(&md5ctx.A, ses->ses_hminner, sizeof(md5ctx.A) * 4); 666 } else { 667 SHA1Init(&sha1ctx); 668 SHA1Update(&sha1ctx, key, klen); 669 SHA1Update(&sha1ctx, hmac_ipad_buffer, 670 SHA1_HMAC_BLOCK_LEN - klen); 671 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); 672 } 673 674 for (i = 0; i < klen; i++) 675 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 676 677 if (algo == CRYPTO_MD5_HMAC) { 678 MD5Init(&md5ctx); 679 MD5Update(&md5ctx, key, klen); 680 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); 681 /* gcc8 craps out on -Warray-bounds w/ optimized bcopy */ 682 _bcopy(&md5ctx.A, ses->ses_hmouter, sizeof(md5ctx.A) * 4); 683 } else { 684 SHA1Init(&sha1ctx); 685 SHA1Update(&sha1ctx, key, klen); 686 SHA1Update(&sha1ctx, hmac_opad_buffer, 687 SHA1_HMAC_BLOCK_LEN - klen); 688 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); 689 } 690 691 for (i = 0; i < klen; i++) 692 key[i] ^= HMAC_OPAD_VAL; 693 694 /* PE is little-endian, insure proper byte order */ 695 for (i = 0; i < nitems(ses->ses_hminner); i++) { 696 ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); 697 ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); 698 } 699 } 700 701 /* 702 * Allocate a new 'session' and return an encoded session id. 'sidp' 703 * contains our registration id, and should contain an encoded session 704 * id on successful allocation. 705 */ 706 static int 707 safe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) 708 { 709 struct safe_softc *sc = device_get_softc(dev); 710 struct cryptoini *c, *encini = NULL, *macini = NULL; 711 struct safe_session *ses = NULL; 712 int sesn; 713 714 if (sidp == NULL || cri == NULL || sc == NULL) 715 return (EINVAL); 716 717 for (c = cri; c != NULL; c = c->cri_next) { 718 if (c->cri_alg == CRYPTO_MD5_HMAC || 719 c->cri_alg == CRYPTO_SHA1_HMAC || 720 c->cri_alg == CRYPTO_NULL_HMAC) { 721 if (macini) 722 return (EINVAL); 723 macini = c; 724 } else if (c->cri_alg == CRYPTO_DES_CBC || 725 c->cri_alg == CRYPTO_3DES_CBC || 726 c->cri_alg == CRYPTO_AES_CBC || 727 c->cri_alg == CRYPTO_NULL_CBC) { 728 if (encini) 729 return (EINVAL); 730 encini = c; 731 } else 732 return (EINVAL); 733 } 734 if (encini == NULL && macini == NULL) 735 return (EINVAL); 736 if (encini) { /* validate key length */ 737 switch (encini->cri_alg) { 738 case CRYPTO_DES_CBC: 739 if (encini->cri_klen != 64) 740 return (EINVAL); 741 break; 742 case CRYPTO_3DES_CBC: 743 if (encini->cri_klen != 192) 744 return (EINVAL); 745 break; 746 case CRYPTO_AES_CBC: 747 if (encini->cri_klen != 128 && 748 encini->cri_klen != 192 && 749 encini->cri_klen != 256) 750 return (EINVAL); 751 break; 752 } 753 } 754 755 if (sc->sc_sessions == NULL) { 756 ses = sc->sc_sessions = (struct safe_session *)kmalloc( 757 sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 758 if (ses == NULL) 759 return (ENOMEM); 760 sesn = 0; 761 sc->sc_nsessions = 1; 762 } else { 763 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 764 if (sc->sc_sessions[sesn].ses_used == 0) { 765 ses = &sc->sc_sessions[sesn]; 766 break; 767 } 768 } 769 770 if (ses == NULL) { 771 sesn = sc->sc_nsessions; 772 ses = (struct safe_session *)kmalloc((sesn + 1) * 773 sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 774 if (ses == NULL) 775 return (ENOMEM); 776 bcopy(sc->sc_sessions, ses, sesn * 777 sizeof(struct safe_session)); 778 bzero(sc->sc_sessions, sesn * 779 sizeof(struct safe_session)); 780 kfree(sc->sc_sessions, M_DEVBUF); 781 sc->sc_sessions = ses; 782 ses = &sc->sc_sessions[sesn]; 783 sc->sc_nsessions++; 784 } 785 } 786 787 bzero(ses, sizeof(struct safe_session)); 788 ses->ses_used = 1; 789 790 if (encini) { 791 /* get an IV */ 792 /* XXX may read fewer than requested */ 793 read_random(ses->ses_iv, sizeof(ses->ses_iv), 0); 794 795 ses->ses_klen = encini->cri_klen; 796 if (encini->cri_key != NULL) 797 safe_setup_enckey(ses, encini->cri_key); 798 } 799 800 if (macini) { 801 ses->ses_mlen = macini->cri_mlen; 802 if (ses->ses_mlen == 0) { 803 if (macini->cri_alg == CRYPTO_MD5_HMAC) 804 ses->ses_mlen = MD5_HASH_LEN; 805 else 806 ses->ses_mlen = SHA1_HASH_LEN; 807 } 808 809 if (macini->cri_key != NULL) { 810 safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, 811 macini->cri_klen / 8); 812 } 813 } 814 815 *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); 816 return (0); 817 } 818 819 /* 820 * Deallocate a session. 821 */ 822 static int 823 safe_freesession(device_t dev, u_int64_t tid) 824 { 825 struct safe_softc *sc = device_get_softc(dev); 826 int session, ret; 827 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 828 829 if (sc == NULL) 830 return (EINVAL); 831 832 session = SAFE_SESSION(sid); 833 if (session < sc->sc_nsessions) { 834 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 835 ret = 0; 836 } else 837 ret = EINVAL; 838 return (ret); 839 } 840 841 static void 842 safe_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 843 { 844 struct safe_operand *op = arg; 845 846 DPRINTF(("%s: mapsize %u nsegs %d error %d\n", __func__, 847 (u_int) mapsize, nsegs, error)); 848 if (error != 0) 849 return; 850 op->mapsize = mapsize; 851 op->nsegs = nsegs; 852 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 853 } 854 855 static int 856 safe_process(device_t dev, struct cryptop *crp, int hint) 857 { 858 struct safe_softc *sc = device_get_softc(dev); 859 int err = 0, i, nicealign, uniform; 860 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 861 int bypass, oplen, ivsize; 862 caddr_t iv; 863 int16_t coffset; 864 struct safe_session *ses; 865 struct safe_ringentry *re; 866 struct safe_sarec *sa; 867 struct safe_pdesc *pd; 868 u_int32_t cmd0, cmd1, staterec; 869 870 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 871 safestats.st_invalid++; 872 return (EINVAL); 873 } 874 if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 875 safestats.st_badsession++; 876 return (EINVAL); 877 } 878 879 lockmgr(&sc->sc_ringlock, LK_EXCLUSIVE); 880 if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { 881 safestats.st_ringfull++; 882 sc->sc_needwakeup |= CRYPTO_SYMQ; 883 lockmgr(&sc->sc_ringlock, LK_RELEASE); 884 return (ERESTART); 885 } 886 re = sc->sc_front; 887 888 staterec = re->re_sa.sa_staterec; /* save */ 889 /* NB: zero everything but the PE descriptor */ 890 bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); 891 re->re_sa.sa_staterec = staterec; /* restore */ 892 893 re->re_crp = crp; 894 re->re_sesn = SAFE_SESSION(crp->crp_sid); 895 896 if (crp->crp_flags & CRYPTO_F_IMBUF) { 897 re->re_src_m = (struct mbuf *)crp->crp_buf; 898 re->re_dst_m = (struct mbuf *)crp->crp_buf; 899 } else if (crp->crp_flags & CRYPTO_F_IOV) { 900 re->re_src_io = (struct uio *)crp->crp_buf; 901 re->re_dst_io = (struct uio *)crp->crp_buf; 902 } else { 903 safestats.st_badflags++; 904 err = EINVAL; 905 goto errout; /* XXX we don't handle contiguous blocks! */ 906 } 907 908 sa = &re->re_sa; 909 ses = &sc->sc_sessions[re->re_sesn]; 910 911 crd1 = crp->crp_desc; 912 if (crd1 == NULL) { 913 safestats.st_nodesc++; 914 err = EINVAL; 915 goto errout; 916 } 917 crd2 = crd1->crd_next; 918 919 cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ 920 cmd1 = 0; 921 if (crd2 == NULL) { 922 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 923 crd1->crd_alg == CRYPTO_SHA1_HMAC || 924 crd1->crd_alg == CRYPTO_NULL_HMAC) { 925 maccrd = crd1; 926 enccrd = NULL; 927 cmd0 |= SAFE_SA_CMD0_OP_HASH; 928 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 929 crd1->crd_alg == CRYPTO_3DES_CBC || 930 crd1->crd_alg == CRYPTO_AES_CBC || 931 crd1->crd_alg == CRYPTO_NULL_CBC) { 932 maccrd = NULL; 933 enccrd = crd1; 934 cmd0 |= SAFE_SA_CMD0_OP_CRYPT; 935 } else { 936 safestats.st_badalg++; 937 err = EINVAL; 938 goto errout; 939 } 940 } else { 941 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 942 crd1->crd_alg == CRYPTO_SHA1_HMAC || 943 crd1->crd_alg == CRYPTO_NULL_HMAC) && 944 (crd2->crd_alg == CRYPTO_DES_CBC || 945 crd2->crd_alg == CRYPTO_3DES_CBC || 946 crd2->crd_alg == CRYPTO_AES_CBC || 947 crd2->crd_alg == CRYPTO_NULL_CBC) && 948 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 949 maccrd = crd1; 950 enccrd = crd2; 951 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 952 crd1->crd_alg == CRYPTO_3DES_CBC || 953 crd1->crd_alg == CRYPTO_AES_CBC || 954 crd1->crd_alg == CRYPTO_NULL_CBC) && 955 (crd2->crd_alg == CRYPTO_MD5_HMAC || 956 crd2->crd_alg == CRYPTO_SHA1_HMAC || 957 crd2->crd_alg == CRYPTO_NULL_HMAC) && 958 (crd1->crd_flags & CRD_F_ENCRYPT)) { 959 enccrd = crd1; 960 maccrd = crd2; 961 } else { 962 safestats.st_badalg++; 963 err = EINVAL; 964 goto errout; 965 } 966 cmd0 |= SAFE_SA_CMD0_OP_BOTH; 967 } 968 969 if (enccrd) { 970 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) 971 safe_setup_enckey(ses, enccrd->crd_key); 972 973 if (enccrd->crd_alg == CRYPTO_DES_CBC) { 974 cmd0 |= SAFE_SA_CMD0_DES; 975 cmd1 |= SAFE_SA_CMD1_CBC; 976 ivsize = 2*sizeof(u_int32_t); 977 } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { 978 cmd0 |= SAFE_SA_CMD0_3DES; 979 cmd1 |= SAFE_SA_CMD1_CBC; 980 ivsize = 2*sizeof(u_int32_t); 981 } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { 982 cmd0 |= SAFE_SA_CMD0_AES; 983 cmd1 |= SAFE_SA_CMD1_CBC; 984 if (ses->ses_klen == 128) 985 cmd1 |= SAFE_SA_CMD1_AES128; 986 else if (ses->ses_klen == 192) 987 cmd1 |= SAFE_SA_CMD1_AES192; 988 else 989 cmd1 |= SAFE_SA_CMD1_AES256; 990 ivsize = 4*sizeof(u_int32_t); 991 } else { 992 cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; 993 ivsize = 0; 994 } 995 996 /* 997 * Setup encrypt/decrypt state. When using basic ops 998 * we can't use an inline IV because hash/crypt offset 999 * must be from the end of the IV to the start of the 1000 * crypt data and this leaves out the preceding header 1001 * from the hash calculation. Instead we place the IV 1002 * in the state record and set the hash/crypt offset to 1003 * copy both the header+IV. 1004 */ 1005 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1006 cmd0 |= SAFE_SA_CMD0_OUTBOUND; 1007 1008 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1009 iv = enccrd->crd_iv; 1010 else 1011 iv = (caddr_t) ses->ses_iv; 1012 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1013 crypto_copyback(crp->crp_flags, crp->crp_buf, 1014 enccrd->crd_inject, ivsize, iv); 1015 } 1016 bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); 1017 cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; 1018 re->re_flags |= SAFE_QFLAGS_COPYOUTIV; 1019 } else { 1020 cmd0 |= SAFE_SA_CMD0_INBOUND; 1021 1022 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { 1023 bcopy(enccrd->crd_iv, 1024 re->re_sastate.sa_saved_iv, ivsize); 1025 } else { 1026 crypto_copydata(crp->crp_flags, crp->crp_buf, 1027 enccrd->crd_inject, ivsize, 1028 (caddr_t)re->re_sastate.sa_saved_iv); 1029 } 1030 cmd0 |= SAFE_SA_CMD0_IVLD_STATE; 1031 } 1032 /* 1033 * For basic encryption use the zero pad algorithm. 1034 * This pads results to an 8-byte boundary and 1035 * suppresses padding verification for inbound (i.e. 1036 * decrypt) operations. 1037 * 1038 * NB: Not sure if the 8-byte pad boundary is a problem. 1039 */ 1040 cmd0 |= SAFE_SA_CMD0_PAD_ZERO; 1041 1042 /* XXX assert key bufs have the same size */ 1043 bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); 1044 } 1045 1046 if (maccrd) { 1047 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { 1048 safe_setup_mackey(ses, maccrd->crd_alg, 1049 maccrd->crd_key, maccrd->crd_klen / 8); 1050 } 1051 1052 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { 1053 cmd0 |= SAFE_SA_CMD0_MD5; 1054 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1055 } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { 1056 cmd0 |= SAFE_SA_CMD0_SHA1; 1057 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1058 } else { 1059 cmd0 |= SAFE_SA_CMD0_HASH_NULL; 1060 } 1061 /* 1062 * Digest data is loaded from the SA and the hash 1063 * result is saved to the state block where we 1064 * retrieve it for return to the caller. 1065 */ 1066 /* XXX assert digest bufs have the same size */ 1067 bcopy(ses->ses_hminner, sa->sa_indigest, 1068 sizeof(sa->sa_indigest)); 1069 bcopy(ses->ses_hmouter, sa->sa_outdigest, 1070 sizeof(sa->sa_outdigest)); 1071 1072 cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; 1073 re->re_flags |= SAFE_QFLAGS_COPYOUTICV; 1074 } 1075 1076 if (enccrd && maccrd) { 1077 /* 1078 * The offset from hash data to the start of 1079 * crypt data is the difference in the skips. 1080 */ 1081 bypass = maccrd->crd_skip; 1082 coffset = enccrd->crd_skip - maccrd->crd_skip; 1083 if (coffset < 0) { 1084 DPRINTF(("%s: hash does not precede crypt; " 1085 "mac skip %u enc skip %u\n", 1086 __func__, maccrd->crd_skip, enccrd->crd_skip)); 1087 safestats.st_skipmismatch++; 1088 err = EINVAL; 1089 goto errout; 1090 } 1091 oplen = enccrd->crd_skip + enccrd->crd_len; 1092 if (maccrd->crd_skip + maccrd->crd_len != oplen) { 1093 DPRINTF(("%s: hash amount %u != crypt amount %u\n", 1094 __func__, maccrd->crd_skip + maccrd->crd_len, 1095 oplen)); 1096 safestats.st_lenmismatch++; 1097 err = EINVAL; 1098 goto errout; 1099 } 1100 #ifdef SAFE_DEBUG 1101 if (safe_debug) { 1102 kprintf("mac: skip %d, len %d, inject %d\n", 1103 maccrd->crd_skip, maccrd->crd_len, 1104 maccrd->crd_inject); 1105 kprintf("enc: skip %d, len %d, inject %d\n", 1106 enccrd->crd_skip, enccrd->crd_len, 1107 enccrd->crd_inject); 1108 kprintf("bypass %d coffset %d oplen %d\n", 1109 bypass, coffset, oplen); 1110 } 1111 #endif 1112 if (coffset & 3) { /* offset must be 32-bit aligned */ 1113 DPRINTF(("%s: coffset %u misaligned\n", 1114 __func__, coffset)); 1115 safestats.st_coffmisaligned++; 1116 err = EINVAL; 1117 goto errout; 1118 } 1119 coffset >>= 2; 1120 if (coffset > 255) { /* offset must be <256 dwords */ 1121 DPRINTF(("%s: coffset %u too big\n", 1122 __func__, coffset)); 1123 safestats.st_cofftoobig++; 1124 err = EINVAL; 1125 goto errout; 1126 } 1127 /* 1128 * Tell the hardware to copy the header to the output. 1129 * The header is defined as the data from the end of 1130 * the bypass to the start of data to be encrypted. 1131 * Typically this is the inline IV. Note that you need 1132 * to do this even if src+dst are the same; it appears 1133 * that w/o this bit the crypted data is written 1134 * immediately after the bypass data. 1135 */ 1136 cmd1 |= SAFE_SA_CMD1_HDRCOPY; 1137 /* 1138 * Disable IP header mutable bit handling. This is 1139 * needed to get correct HMAC calculations. 1140 */ 1141 cmd1 |= SAFE_SA_CMD1_MUTABLE; 1142 } else { 1143 if (enccrd) { 1144 bypass = enccrd->crd_skip; 1145 oplen = bypass + enccrd->crd_len; 1146 } else { 1147 bypass = maccrd->crd_skip; 1148 oplen = bypass + maccrd->crd_len; 1149 } 1150 coffset = 0; 1151 } 1152 /* XXX verify multiple of 4 when using s/g */ 1153 if (bypass > 96) { /* bypass offset must be <= 96 bytes */ 1154 DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); 1155 safestats.st_bypasstoobig++; 1156 err = EINVAL; 1157 goto errout; 1158 } 1159 1160 if (bus_dmamap_create(sc->sc_srcdmat, BUS_DMA_NOWAIT, &re->re_src_map)) { 1161 safestats.st_nomap++; 1162 err = ENOMEM; 1163 goto errout; 1164 } 1165 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1166 if (bus_dmamap_load_mbuf(sc->sc_srcdmat, re->re_src_map, 1167 re->re_src_m, safe_op_cb, 1168 &re->re_src, BUS_DMA_NOWAIT) != 0) { 1169 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1170 re->re_src_map = NULL; 1171 safestats.st_noload++; 1172 err = ENOMEM; 1173 goto errout; 1174 } 1175 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1176 if (bus_dmamap_load_uio(sc->sc_srcdmat, re->re_src_map, 1177 re->re_src_io, safe_op_cb, 1178 &re->re_src, BUS_DMA_NOWAIT) != 0) { 1179 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1180 re->re_src_map = NULL; 1181 safestats.st_noload++; 1182 err = ENOMEM; 1183 goto errout; 1184 } 1185 } 1186 nicealign = safe_dmamap_aligned(&re->re_src); 1187 uniform = safe_dmamap_uniform(&re->re_src); 1188 1189 DPRINTF(("src nicealign %u uniform %u nsegs %u\n", 1190 nicealign, uniform, re->re_src.nsegs)); 1191 if (re->re_src.nsegs > 1) { 1192 re->re_desc.d_src = sc->sc_spalloc.dma_paddr + 1193 ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); 1194 for (i = 0; i < re->re_src_nsegs; i++) { 1195 /* NB: no need to check if there's space */ 1196 pd = sc->sc_spfree; 1197 if (++(sc->sc_spfree) == sc->sc_springtop) 1198 sc->sc_spfree = sc->sc_spring; 1199 1200 KASSERT((pd->pd_flags&3) == 0 || 1201 (pd->pd_flags&3) == SAFE_PD_DONE, 1202 ("bogus source particle descriptor; flags %x", 1203 pd->pd_flags)); 1204 pd->pd_addr = re->re_src_segs[i].ds_addr; 1205 pd->pd_size = re->re_src_segs[i].ds_len; 1206 pd->pd_flags = SAFE_PD_READY; 1207 } 1208 cmd0 |= SAFE_SA_CMD0_IGATHER; 1209 } else { 1210 /* 1211 * No need for gather, reference the operand directly. 1212 */ 1213 re->re_desc.d_src = re->re_src_segs[0].ds_addr; 1214 } 1215 1216 if (enccrd == NULL && maccrd != NULL) { 1217 /* 1218 * Hash op; no destination needed. 1219 */ 1220 } else { 1221 if (crp->crp_flags & CRYPTO_F_IOV) { 1222 if (!nicealign) { 1223 safestats.st_iovmisaligned++; 1224 err = EINVAL; 1225 goto errout; 1226 } 1227 if (uniform != 1) { 1228 /* 1229 * Source is not suitable for direct use as 1230 * the destination. Create a new scatter/gather 1231 * list based on the destination requirements 1232 * and check if that's ok. 1233 */ 1234 if (bus_dmamap_create(sc->sc_dstdmat, 1235 BUS_DMA_NOWAIT, &re->re_dst_map)) { 1236 safestats.st_nomap++; 1237 err = ENOMEM; 1238 goto errout; 1239 } 1240 if (bus_dmamap_load_uio(sc->sc_dstdmat, 1241 re->re_dst_map, re->re_dst_io, 1242 safe_op_cb, &re->re_dst, 1243 BUS_DMA_NOWAIT) != 0) { 1244 bus_dmamap_destroy(sc->sc_dstdmat, 1245 re->re_dst_map); 1246 re->re_dst_map = NULL; 1247 safestats.st_noload++; 1248 err = ENOMEM; 1249 goto errout; 1250 } 1251 uniform = safe_dmamap_uniform(&re->re_dst); 1252 if (!uniform) { 1253 /* 1254 * There's no way to handle the DMA 1255 * requirements with this uio. We 1256 * could create a separate DMA area for 1257 * the result and then copy it back, 1258 * but for now we just bail and return 1259 * an error. Note that uio requests 1260 * > SAFE_MAX_DSIZE are handled because 1261 * the DMA map and segment list for the 1262 * destination wil result in a 1263 * destination particle list that does 1264 * the necessary scatter DMA. 1265 */ 1266 safestats.st_iovnotuniform++; 1267 err = EINVAL; 1268 goto errout; 1269 } 1270 } else 1271 re->re_dst = re->re_src; 1272 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1273 if (nicealign && uniform == 1) { 1274 /* 1275 * Source layout is suitable for direct 1276 * sharing of the DMA map and segment list. 1277 */ 1278 re->re_dst = re->re_src; 1279 } else if (nicealign && uniform == 2) { 1280 /* 1281 * The source is properly aligned but requires a 1282 * different particle list to handle DMA of the 1283 * result. Create a new map and do the load to 1284 * create the segment list. The particle 1285 * descriptor setup code below will handle the 1286 * rest. 1287 */ 1288 if (bus_dmamap_create(sc->sc_dstdmat, 1289 BUS_DMA_NOWAIT, &re->re_dst_map)) { 1290 safestats.st_nomap++; 1291 err = ENOMEM; 1292 goto errout; 1293 } 1294 if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1295 re->re_dst_map, re->re_dst_m, 1296 safe_op_cb, &re->re_dst, 1297 BUS_DMA_NOWAIT) != 0) { 1298 bus_dmamap_destroy(sc->sc_dstdmat, 1299 re->re_dst_map); 1300 re->re_dst_map = NULL; 1301 safestats.st_noload++; 1302 err = ENOMEM; 1303 goto errout; 1304 } 1305 } else { /* !(aligned and/or uniform) */ 1306 int totlen, len; 1307 struct mbuf *m, *top, **mp; 1308 1309 /* 1310 * DMA constraints require that we allocate a 1311 * new mbuf chain for the destination. We 1312 * allocate an entire new set of mbufs of 1313 * optimal/required size and then tell the 1314 * hardware to copy any bits that are not 1315 * created as a byproduct of the operation. 1316 */ 1317 if (!nicealign) 1318 safestats.st_unaligned++; 1319 if (!uniform) 1320 safestats.st_notuniform++; 1321 totlen = re->re_src_mapsize; 1322 if (re->re_src_m->m_flags & M_PKTHDR) { 1323 len = MHLEN; 1324 MGETHDR(m, M_NOWAIT, MT_DATA); 1325 if (m && !m_dup_pkthdr(m, re->re_src_m, 1326 M_NOWAIT)) { 1327 m_free(m); 1328 m = NULL; 1329 } 1330 } else { 1331 len = MLEN; 1332 MGET(m, M_NOWAIT, MT_DATA); 1333 } 1334 if (m == NULL) { 1335 safestats.st_nombuf++; 1336 err = sc->sc_nqchip ? ERESTART : ENOMEM; 1337 goto errout; 1338 } 1339 if (totlen >= MINCLSIZE) { 1340 MCLGET(m, M_NOWAIT); 1341 if ((m->m_flags & M_EXT) == 0) { 1342 m_free(m); 1343 safestats.st_nomcl++; 1344 err = sc->sc_nqchip ? 1345 ERESTART : ENOMEM; 1346 goto errout; 1347 } 1348 len = MCLBYTES; 1349 } 1350 m->m_len = len; 1351 top = NULL; 1352 mp = ⊤ 1353 1354 while (totlen > 0) { 1355 if (top) { 1356 MGET(m, M_NOWAIT, MT_DATA); 1357 if (m == NULL) { 1358 m_freem(top); 1359 safestats.st_nombuf++; 1360 err = sc->sc_nqchip ? 1361 ERESTART : ENOMEM; 1362 goto errout; 1363 } 1364 len = MLEN; 1365 } 1366 if (top && totlen >= MINCLSIZE) { 1367 MCLGET(m, M_NOWAIT); 1368 if ((m->m_flags & M_EXT) == 0) { 1369 *mp = m; 1370 m_freem(top); 1371 safestats.st_nomcl++; 1372 err = sc->sc_nqchip ? 1373 ERESTART : ENOMEM; 1374 goto errout; 1375 } 1376 len = MCLBYTES; 1377 } 1378 m->m_len = len = min(totlen, len); 1379 totlen -= len; 1380 *mp = m; 1381 mp = &m->m_next; 1382 } 1383 re->re_dst_m = top; 1384 if (bus_dmamap_create(sc->sc_dstdmat, 1385 BUS_DMA_NOWAIT, &re->re_dst_map) != 0) { 1386 safestats.st_nomap++; 1387 err = ENOMEM; 1388 goto errout; 1389 } 1390 if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1391 re->re_dst_map, re->re_dst_m, 1392 safe_op_cb, &re->re_dst, 1393 BUS_DMA_NOWAIT) != 0) { 1394 bus_dmamap_destroy(sc->sc_dstdmat, 1395 re->re_dst_map); 1396 re->re_dst_map = NULL; 1397 safestats.st_noload++; 1398 err = ENOMEM; 1399 goto errout; 1400 } 1401 if (re->re_src.mapsize > oplen) { 1402 /* 1403 * There's data following what the 1404 * hardware will copy for us. If this 1405 * isn't just the ICV (that's going to 1406 * be written on completion), copy it 1407 * to the new mbufs 1408 */ 1409 if (!(maccrd && 1410 (re->re_src.mapsize-oplen) == 12 && 1411 maccrd->crd_inject == oplen)) 1412 safe_mcopy(re->re_src_m, 1413 re->re_dst_m, 1414 oplen); 1415 else 1416 safestats.st_noicvcopy++; 1417 } 1418 } 1419 } else { 1420 safestats.st_badflags++; 1421 err = EINVAL; 1422 goto errout; 1423 } 1424 1425 if (re->re_dst.nsegs > 1) { 1426 re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + 1427 ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); 1428 for (i = 0; i < re->re_dst_nsegs; i++) { 1429 pd = sc->sc_dpfree; 1430 KASSERT((pd->pd_flags&3) == 0 || 1431 (pd->pd_flags&3) == SAFE_PD_DONE, 1432 ("bogus dest particle descriptor; flags %x", 1433 pd->pd_flags)); 1434 if (++(sc->sc_dpfree) == sc->sc_dpringtop) 1435 sc->sc_dpfree = sc->sc_dpring; 1436 pd->pd_addr = re->re_dst_segs[i].ds_addr; 1437 pd->pd_flags = SAFE_PD_READY; 1438 } 1439 cmd0 |= SAFE_SA_CMD0_OSCATTER; 1440 } else { 1441 /* 1442 * No need for scatter, reference the operand directly. 1443 */ 1444 re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; 1445 } 1446 } 1447 1448 /* 1449 * All done with setup; fillin the SA command words 1450 * and the packet engine descriptor. The operation 1451 * is now ready for submission to the hardware. 1452 */ 1453 sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; 1454 sa->sa_cmd1 = cmd1 1455 | (coffset << SAFE_SA_CMD1_OFFSET_S) 1456 | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ 1457 | SAFE_SA_CMD1_SRPCI 1458 ; 1459 /* 1460 * NB: the order of writes is important here. In case the 1461 * chip is scanning the ring because of an outstanding request 1462 * it might nab this one too. In that case we need to make 1463 * sure the setup is complete before we write the length 1464 * field of the descriptor as it signals the descriptor is 1465 * ready for processing. 1466 */ 1467 re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; 1468 if (maccrd) 1469 re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; 1470 re->re_desc.d_len = oplen 1471 | SAFE_PE_LEN_READY 1472 | (bypass << SAFE_PE_LEN_BYPASS_S) 1473 ; 1474 1475 safestats.st_ipackets++; 1476 safestats.st_ibytes += oplen; 1477 1478 if (++(sc->sc_front) == sc->sc_ringtop) 1479 sc->sc_front = sc->sc_ring; 1480 1481 /* XXX honor batching */ 1482 safe_feed(sc, re); 1483 lockmgr(&sc->sc_ringlock, LK_RELEASE); 1484 return (0); 1485 1486 errout: 1487 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 1488 m_freem(re->re_dst_m); 1489 1490 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1491 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1492 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1493 } 1494 if (re->re_src_map != NULL) { 1495 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1496 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1497 } 1498 lockmgr(&sc->sc_ringlock, LK_RELEASE); 1499 if (err != ERESTART) { 1500 crp->crp_etype = err; 1501 crypto_done(crp); 1502 } else { 1503 sc->sc_needwakeup |= CRYPTO_SYMQ; 1504 } 1505 return (err); 1506 } 1507 1508 static void 1509 safe_callback(struct safe_softc *sc, struct safe_ringentry *re) 1510 { 1511 struct cryptop *crp = (struct cryptop *)re->re_crp; 1512 struct cryptodesc *crd; 1513 1514 safestats.st_opackets++; 1515 safestats.st_obytes += re->re_dst.mapsize; 1516 1517 safe_dma_sync(&sc->sc_ringalloc, 1518 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1519 if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { 1520 device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", 1521 re->re_desc.d_csr, 1522 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); 1523 safestats.st_peoperr++; 1524 crp->crp_etype = EIO; /* something more meaningful? */ 1525 } 1526 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1527 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 1528 BUS_DMASYNC_POSTREAD); 1529 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1530 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1531 } 1532 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_POSTWRITE); 1533 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1534 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1535 1536 /* 1537 * If result was written to a differet mbuf chain, swap 1538 * it in as the return value and reclaim the original. 1539 */ 1540 if ((crp->crp_flags & CRYPTO_F_IMBUF) && re->re_src_m != re->re_dst_m) { 1541 m_freem(re->re_src_m); 1542 crp->crp_buf = (caddr_t)re->re_dst_m; 1543 } 1544 1545 if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) { 1546 /* copy out IV for future use */ 1547 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1548 int ivsize; 1549 1550 if (crd->crd_alg == CRYPTO_DES_CBC || 1551 crd->crd_alg == CRYPTO_3DES_CBC) { 1552 ivsize = 2*sizeof(u_int32_t); 1553 } else if (crd->crd_alg == CRYPTO_AES_CBC) { 1554 ivsize = 4*sizeof(u_int32_t); 1555 } else 1556 continue; 1557 crypto_copydata(crp->crp_flags, crp->crp_buf, 1558 crd->crd_skip + crd->crd_len - ivsize, ivsize, 1559 (caddr_t)sc->sc_sessions[re->re_sesn].ses_iv); 1560 break; 1561 } 1562 } 1563 1564 if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { 1565 /* copy out ICV result */ 1566 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1567 if (!(crd->crd_alg == CRYPTO_MD5_HMAC || 1568 crd->crd_alg == CRYPTO_SHA1_HMAC || 1569 crd->crd_alg == CRYPTO_NULL_HMAC)) 1570 continue; 1571 if (crd->crd_alg == CRYPTO_SHA1_HMAC) { 1572 /* 1573 * SHA-1 ICV's are byte-swapped; fix 'em up 1574 * before copy them to their destination. 1575 */ 1576 re->re_sastate.sa_saved_indigest[0] = 1577 bswap32(re->re_sastate.sa_saved_indigest[0]); 1578 re->re_sastate.sa_saved_indigest[1] = 1579 bswap32(re->re_sastate.sa_saved_indigest[1]); 1580 re->re_sastate.sa_saved_indigest[2] = 1581 bswap32(re->re_sastate.sa_saved_indigest[2]); 1582 } 1583 crypto_copyback(crp->crp_flags, crp->crp_buf, 1584 crd->crd_inject, 1585 sc->sc_sessions[re->re_sesn].ses_mlen, 1586 (caddr_t)re->re_sastate.sa_saved_indigest); 1587 break; 1588 } 1589 } 1590 crypto_done(crp); 1591 } 1592 1593 /* 1594 * Copy all data past offset from srcm to dstm. 1595 */ 1596 static void 1597 safe_mcopy(struct mbuf *srcm, struct mbuf *dstm, u_int offset) 1598 { 1599 u_int j, dlen, slen; 1600 caddr_t dptr, sptr; 1601 1602 /* 1603 * Advance src and dst to offset. 1604 */ 1605 j = offset; 1606 while (j >= 0) { 1607 if (srcm->m_len > j) 1608 break; 1609 j -= srcm->m_len; 1610 srcm = srcm->m_next; 1611 if (srcm == NULL) 1612 return; 1613 } 1614 sptr = mtod(srcm, caddr_t) + j; 1615 slen = srcm->m_len - j; 1616 1617 j = offset; 1618 while (j >= 0) { 1619 if (dstm->m_len > j) 1620 break; 1621 j -= dstm->m_len; 1622 dstm = dstm->m_next; 1623 if (dstm == NULL) 1624 return; 1625 } 1626 dptr = mtod(dstm, caddr_t) + j; 1627 dlen = dstm->m_len - j; 1628 1629 /* 1630 * Copy everything that remains. 1631 */ 1632 for (;;) { 1633 j = min(slen, dlen); 1634 bcopy(sptr, dptr, j); 1635 if (slen == j) { 1636 srcm = srcm->m_next; 1637 if (srcm == NULL) 1638 return; 1639 sptr = srcm->m_data; 1640 slen = srcm->m_len; 1641 } else 1642 sptr += j, slen -= j; 1643 if (dlen == j) { 1644 dstm = dstm->m_next; 1645 if (dstm == NULL) 1646 return; 1647 dptr = dstm->m_data; 1648 dlen = dstm->m_len; 1649 } else 1650 dptr += j, dlen -= j; 1651 } 1652 } 1653 1654 #ifndef SAFE_NO_RNG 1655 #define SAFE_RNG_MAXWAIT 1000 1656 1657 static void 1658 safe_rng_init(struct safe_softc *sc) 1659 { 1660 u_int32_t w, v; 1661 int i; 1662 1663 WRITE_REG(sc, SAFE_RNG_CTRL, 0); 1664 /* use default value according to the manual */ 1665 WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ 1666 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1667 1668 /* 1669 * There is a bug in rev 1.0 of the 1140 that when the RNG 1670 * is brought out of reset the ready status flag does not 1671 * work until the RNG has finished its internal initialization. 1672 * 1673 * So in order to determine the device is through its 1674 * initialization we must read the data register, using the 1675 * status reg in the read in case it is initialized. Then read 1676 * the data register until it changes from the first read. 1677 * Once it changes read the data register until it changes 1678 * again. At this time the RNG is considered initialized. 1679 * This could take between 750ms - 1000ms in time. 1680 */ 1681 i = 0; 1682 w = READ_REG(sc, SAFE_RNG_OUT); 1683 do { 1684 v = READ_REG(sc, SAFE_RNG_OUT); 1685 if (v != w) { 1686 w = v; 1687 break; 1688 } 1689 DELAY(10); 1690 } while (++i < SAFE_RNG_MAXWAIT); 1691 1692 /* Wait Until data changes again */ 1693 i = 0; 1694 do { 1695 v = READ_REG(sc, SAFE_RNG_OUT); 1696 if (v != w) 1697 break; 1698 DELAY(10); 1699 } while (++i < SAFE_RNG_MAXWAIT); 1700 } 1701 1702 static __inline void 1703 safe_rng_disable_short_cycle(struct safe_softc *sc) 1704 { 1705 WRITE_REG(sc, SAFE_RNG_CTRL, 1706 READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); 1707 } 1708 1709 static __inline void 1710 safe_rng_enable_short_cycle(struct safe_softc *sc) 1711 { 1712 WRITE_REG(sc, SAFE_RNG_CTRL, 1713 READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); 1714 } 1715 1716 static __inline u_int32_t 1717 safe_rng_read(struct safe_softc *sc) 1718 { 1719 int i; 1720 1721 i = 0; 1722 while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) 1723 ; 1724 return READ_REG(sc, SAFE_RNG_OUT); 1725 } 1726 1727 static void 1728 safe_rng(void *arg) 1729 { 1730 struct safe_softc *sc = arg; 1731 u_int32_t buf[SAFE_RNG_MAXBUFSIZ]; /* NB: maybe move to softc */ 1732 u_int maxwords; 1733 int i; 1734 1735 safestats.st_rng++; 1736 /* 1737 * Fetch the next block of data. 1738 */ 1739 maxwords = safe_rngbufsize; 1740 if (maxwords > SAFE_RNG_MAXBUFSIZ) 1741 maxwords = SAFE_RNG_MAXBUFSIZ; 1742 retry: 1743 for (i = 0; i < maxwords; i++) 1744 buf[i] = safe_rng_read(sc); 1745 /* 1746 * Check the comparator alarm count and reset the h/w if 1747 * it exceeds our threshold. This guards against the 1748 * hardware oscillators resonating with external signals. 1749 */ 1750 if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { 1751 u_int32_t freq_inc, w; 1752 1753 DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, 1754 READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); 1755 safestats.st_rngalarm++; 1756 safe_rng_enable_short_cycle(sc); 1757 freq_inc = 18; 1758 for (i = 0; i < 64; i++) { 1759 w = READ_REG(sc, SAFE_RNG_CNFG); 1760 freq_inc = ((w + freq_inc) & 0x3fL); 1761 w = ((w & ~0x3fL) | freq_inc); 1762 WRITE_REG(sc, SAFE_RNG_CNFG, w); 1763 1764 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1765 1766 (void) safe_rng_read(sc); 1767 DELAY(25); 1768 1769 if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { 1770 safe_rng_disable_short_cycle(sc); 1771 goto retry; 1772 } 1773 freq_inc = 1; 1774 } 1775 safe_rng_disable_short_cycle(sc); 1776 } else 1777 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1778 1779 (*sc->sc_harvest)(sc->sc_rndtest, buf, maxwords*sizeof (u_int32_t)); 1780 callout_reset(&sc->sc_rngto, 1781 hz * (safe_rnginterval ? safe_rnginterval : 1), safe_rng, sc); 1782 } 1783 #endif /* SAFE_NO_RNG */ 1784 1785 static void 1786 safe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1787 { 1788 bus_addr_t *paddr = (bus_addr_t*) arg; 1789 *paddr = segs->ds_addr; 1790 } 1791 1792 static int 1793 safe_dma_malloc( 1794 struct safe_softc *sc, 1795 bus_size_t size, 1796 struct safe_dma_alloc *dma, 1797 int mapflags 1798 ) 1799 { 1800 int r; 1801 1802 r = bus_dma_tag_create(NULL, /* parent */ 1803 sizeof(u_int32_t), 0, /* alignment, bounds */ 1804 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1805 BUS_SPACE_MAXADDR, /* highaddr */ 1806 NULL, NULL, /* filter, filterarg */ 1807 size, /* maxsize */ 1808 1, /* nsegments */ 1809 size, /* maxsegsize */ 1810 BUS_DMA_ALLOCNOW, /* flags */ 1811 &dma->dma_tag); 1812 if (r != 0) { 1813 device_printf(sc->sc_dev, "safe_dma_malloc: " 1814 "bus_dma_tag_create failed; error %u\n", r); 1815 goto fail_0; 1816 } 1817 1818 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1819 if (r != 0) { 1820 device_printf(sc->sc_dev, "safe_dma_malloc: " 1821 "bus_dmamap_create failed; error %u\n", r); 1822 goto fail_1; 1823 } 1824 1825 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1826 BUS_DMA_NOWAIT, &dma->dma_map); 1827 if (r != 0) { 1828 device_printf(sc->sc_dev, "safe_dma_malloc: " 1829 "bus_dmammem_alloc failed; size %zu, error %u\n", 1830 size, r); 1831 goto fail_2; 1832 } 1833 1834 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1835 size, 1836 safe_dmamap_cb, 1837 &dma->dma_paddr, 1838 mapflags | BUS_DMA_NOWAIT); 1839 if (r != 0) { 1840 device_printf(sc->sc_dev, "safe_dma_malloc: " 1841 "bus_dmamap_load failed; error %u\n", r); 1842 goto fail_3; 1843 } 1844 1845 dma->dma_size = size; 1846 return (0); 1847 1848 fail_3: 1849 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1850 fail_2: 1851 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1852 fail_1: 1853 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1854 bus_dma_tag_destroy(dma->dma_tag); 1855 fail_0: 1856 dma->dma_map = NULL; 1857 dma->dma_tag = NULL; 1858 return (r); 1859 } 1860 1861 static void 1862 safe_dma_free(struct safe_softc *sc, struct safe_dma_alloc *dma) 1863 { 1864 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1865 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1866 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1867 bus_dma_tag_destroy(dma->dma_tag); 1868 } 1869 1870 /* 1871 * Resets the board. Values in the regesters are left as is 1872 * from the reset (i.e. initial values are assigned elsewhere). 1873 */ 1874 static void 1875 safe_reset_board(struct safe_softc *sc) 1876 { 1877 u_int32_t v; 1878 /* 1879 * Reset the device. The manual says no delay 1880 * is needed between marking and clearing reset. 1881 */ 1882 v = READ_REG(sc, SAFE_PE_DMACFG) &~ 1883 (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | 1884 SAFE_PE_DMACFG_SGRESET); 1885 WRITE_REG(sc, SAFE_PE_DMACFG, v 1886 | SAFE_PE_DMACFG_PERESET 1887 | SAFE_PE_DMACFG_PDRRESET 1888 | SAFE_PE_DMACFG_SGRESET); 1889 WRITE_REG(sc, SAFE_PE_DMACFG, v); 1890 } 1891 1892 /* 1893 * Initialize registers we need to touch only once. 1894 */ 1895 static void 1896 safe_init_board(struct safe_softc *sc) 1897 { 1898 u_int32_t v, dwords; 1899 1900 v = READ_REG(sc, SAFE_PE_DMACFG); 1901 v &=~ SAFE_PE_DMACFG_PEMODE; 1902 v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ 1903 | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ 1904 | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ 1905 | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ 1906 | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ 1907 | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ 1908 ; 1909 WRITE_REG(sc, SAFE_PE_DMACFG, v); 1910 #if 0 1911 /* XXX select byte swap based on host byte order */ 1912 WRITE_REG(sc, SAFE_ENDIAN, 0x1b); 1913 #endif 1914 if (sc->sc_chiprev == SAFE_REV(1,0)) { 1915 /* 1916 * Avoid large PCI DMA transfers. Rev 1.0 has a bug where 1917 * "target mode transfers" done while the chip is DMA'ing 1918 * >1020 bytes cause the hardware to lockup. To avoid this 1919 * we reduce the max PCI transfer size and use small source 1920 * particle descriptors (<= 256 bytes). 1921 */ 1922 WRITE_REG(sc, SAFE_DMA_CFG, 256); 1923 device_printf(sc->sc_dev, 1924 "Reduce max DMA size to %u words for rev %u.%u WAR\n", 1925 (READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff, 1926 SAFE_REV_MAJ(sc->sc_chiprev), 1927 SAFE_REV_MIN(sc->sc_chiprev)); 1928 } 1929 1930 /* NB: operands+results are overlaid */ 1931 WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); 1932 WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); 1933 /* 1934 * Configure ring entry size and number of items in the ring. 1935 */ 1936 KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, 1937 ("PE ring entry not 32-bit aligned!")); 1938 dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); 1939 WRITE_REG(sc, SAFE_PE_RINGCFG, 1940 (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); 1941 WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ 1942 1943 WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); 1944 WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); 1945 WRITE_REG(sc, SAFE_PE_PARTSIZE, 1946 (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); 1947 /* 1948 * NB: destination particles are fixed size. We use 1949 * an mbuf cluster and require all results go to 1950 * clusters or smaller. 1951 */ 1952 WRITE_REG(sc, SAFE_PE_PARTCFG, SAFE_MAX_DSIZE); 1953 1954 /* it's now safe to enable PE mode, do it */ 1955 WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); 1956 1957 /* 1958 * Configure hardware to use level-triggered interrupts and 1959 * to interrupt after each descriptor is processed. 1960 */ 1961 WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); 1962 WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); 1963 WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); 1964 } 1965 1966 /* 1967 * Init PCI registers 1968 */ 1969 static void 1970 safe_init_pciregs(device_t dev) 1971 { 1972 } 1973 1974 /* 1975 * Clean up after a chip crash. 1976 * It is assumed that the caller in splimp() 1977 */ 1978 static void 1979 safe_cleanchip(struct safe_softc *sc) 1980 { 1981 1982 if (sc->sc_nqchip != 0) { 1983 struct safe_ringentry *re = sc->sc_back; 1984 1985 while (re != sc->sc_front) { 1986 if (re->re_desc.d_csr != 0) 1987 safe_free_entry(sc, re); 1988 if (++re == sc->sc_ringtop) 1989 re = sc->sc_ring; 1990 } 1991 sc->sc_back = re; 1992 sc->sc_nqchip = 0; 1993 } 1994 } 1995 1996 /* 1997 * free a safe_q 1998 * It is assumed that the caller is within splimp(). 1999 */ 2000 static int 2001 safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) 2002 { 2003 struct cryptop *crp; 2004 2005 /* 2006 * Free header MCR 2007 */ 2008 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 2009 m_freem(re->re_dst_m); 2010 2011 crp = (struct cryptop *)re->re_crp; 2012 2013 re->re_desc.d_csr = 0; 2014 2015 crp->crp_etype = EFAULT; 2016 crypto_done(crp); 2017 return(0); 2018 } 2019 2020 /* 2021 * Routine to reset the chip and clean up. 2022 * It is assumed that the caller is in splimp() 2023 */ 2024 static void 2025 safe_totalreset(struct safe_softc *sc) 2026 { 2027 safe_reset_board(sc); 2028 safe_init_board(sc); 2029 safe_cleanchip(sc); 2030 } 2031 2032 /* 2033 * Is the operand suitable aligned for direct DMA. Each 2034 * segment must be aligned on a 32-bit boundary and all 2035 * but the last segment must be a multiple of 4 bytes. 2036 */ 2037 static int 2038 safe_dmamap_aligned(const struct safe_operand *op) 2039 { 2040 int i; 2041 2042 for (i = 0; i < op->nsegs; i++) { 2043 if (op->segs[i].ds_addr & 3) 2044 return (0); 2045 if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) 2046 return (0); 2047 } 2048 return (1); 2049 } 2050 2051 /* 2052 * Is the operand suitable for direct DMA as the destination 2053 * of an operation. The hardware requires that each ``particle'' 2054 * but the last in an operation result have the same size. We 2055 * fix that size at SAFE_MAX_DSIZE bytes. This routine returns 2056 * 0 if some segment is not a multiple of of this size, 1 if all 2057 * segments are exactly this size, or 2 if segments are at worst 2058 * a multple of this size. 2059 */ 2060 static int 2061 safe_dmamap_uniform(const struct safe_operand *op) 2062 { 2063 int result = 1; 2064 2065 if (op->nsegs > 0) { 2066 int i; 2067 2068 for (i = 0; i < op->nsegs-1; i++) { 2069 if (op->segs[i].ds_len % SAFE_MAX_DSIZE) 2070 return (0); 2071 if (op->segs[i].ds_len != SAFE_MAX_DSIZE) 2072 result = 2; 2073 } 2074 } 2075 return (result); 2076 } 2077 2078 #ifdef SAFE_DEBUG 2079 static void 2080 safe_dump_dmastatus(struct safe_softc *sc, const char *tag) 2081 { 2082 kprintf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" 2083 , tag 2084 , READ_REG(sc, SAFE_DMA_ENDIAN) 2085 , READ_REG(sc, SAFE_DMA_SRCADDR) 2086 , READ_REG(sc, SAFE_DMA_DSTADDR) 2087 , READ_REG(sc, SAFE_DMA_STAT) 2088 ); 2089 } 2090 2091 static void 2092 safe_dump_intrstate(struct safe_softc *sc, const char *tag) 2093 { 2094 kprintf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" 2095 , tag 2096 , READ_REG(sc, SAFE_HI_CFG) 2097 , READ_REG(sc, SAFE_HI_MASK) 2098 , READ_REG(sc, SAFE_HI_DESC_CNT) 2099 , READ_REG(sc, SAFE_HU_STAT) 2100 , READ_REG(sc, SAFE_HM_STAT) 2101 ); 2102 } 2103 2104 static void 2105 safe_dump_ringstate(struct safe_softc *sc, const char *tag) 2106 { 2107 u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); 2108 2109 /* NB: assume caller has lock on ring */ 2110 kprintf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", 2111 tag, 2112 estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), 2113 (unsigned long)(sc->sc_back - sc->sc_ring), 2114 (unsigned long)(sc->sc_front - sc->sc_ring)); 2115 } 2116 2117 static void 2118 safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) 2119 { 2120 int ix, nsegs; 2121 2122 ix = re - sc->sc_ring; 2123 kprintf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" 2124 , tag 2125 , re, ix 2126 , re->re_desc.d_csr 2127 , re->re_desc.d_src 2128 , re->re_desc.d_dst 2129 , re->re_desc.d_sa 2130 , re->re_desc.d_len 2131 ); 2132 if (re->re_src.nsegs > 1) { 2133 ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / 2134 sizeof(struct safe_pdesc); 2135 for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { 2136 kprintf(" spd[%u] %p: %p size %u flags %x" 2137 , ix, &sc->sc_spring[ix] 2138 , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr 2139 , sc->sc_spring[ix].pd_size 2140 , sc->sc_spring[ix].pd_flags 2141 ); 2142 if (sc->sc_spring[ix].pd_size == 0) 2143 kprintf(" (zero!)"); 2144 kprintf("\n"); 2145 if (++ix == SAFE_TOTAL_SPART) 2146 ix = 0; 2147 } 2148 } 2149 if (re->re_dst.nsegs > 1) { 2150 ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / 2151 sizeof(struct safe_pdesc); 2152 for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { 2153 kprintf(" dpd[%u] %p: %p flags %x\n" 2154 , ix, &sc->sc_dpring[ix] 2155 , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr 2156 , sc->sc_dpring[ix].pd_flags 2157 ); 2158 if (++ix == SAFE_TOTAL_DPART) 2159 ix = 0; 2160 } 2161 } 2162 kprintf("sa: cmd0 %08x cmd1 %08x staterec %x\n", 2163 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); 2164 kprintf("sa: key %x %x %x %x %x %x %x %x\n" 2165 , re->re_sa.sa_key[0] 2166 , re->re_sa.sa_key[1] 2167 , re->re_sa.sa_key[2] 2168 , re->re_sa.sa_key[3] 2169 , re->re_sa.sa_key[4] 2170 , re->re_sa.sa_key[5] 2171 , re->re_sa.sa_key[6] 2172 , re->re_sa.sa_key[7] 2173 ); 2174 kprintf("sa: indigest %x %x %x %x %x\n" 2175 , re->re_sa.sa_indigest[0] 2176 , re->re_sa.sa_indigest[1] 2177 , re->re_sa.sa_indigest[2] 2178 , re->re_sa.sa_indigest[3] 2179 , re->re_sa.sa_indigest[4] 2180 ); 2181 kprintf("sa: outdigest %x %x %x %x %x\n" 2182 , re->re_sa.sa_outdigest[0] 2183 , re->re_sa.sa_outdigest[1] 2184 , re->re_sa.sa_outdigest[2] 2185 , re->re_sa.sa_outdigest[3] 2186 , re->re_sa.sa_outdigest[4] 2187 ); 2188 kprintf("sr: iv %x %x %x %x\n" 2189 , re->re_sastate.sa_saved_iv[0] 2190 , re->re_sastate.sa_saved_iv[1] 2191 , re->re_sastate.sa_saved_iv[2] 2192 , re->re_sastate.sa_saved_iv[3] 2193 ); 2194 kprintf("sr: hashbc %u indigest %x %x %x %x %x\n" 2195 , re->re_sastate.sa_saved_hashbc 2196 , re->re_sastate.sa_saved_indigest[0] 2197 , re->re_sastate.sa_saved_indigest[1] 2198 , re->re_sastate.sa_saved_indigest[2] 2199 , re->re_sastate.sa_saved_indigest[3] 2200 , re->re_sastate.sa_saved_indigest[4] 2201 ); 2202 } 2203 2204 static void 2205 safe_dump_ring(struct safe_softc *sc, const char *tag) 2206 { 2207 lockmgr(&sc->sc_ringlock, LK_EXCLUSIVE); 2208 kprintf("\nSafeNet Ring State:\n"); 2209 safe_dump_intrstate(sc, tag); 2210 safe_dump_dmastatus(sc, tag); 2211 safe_dump_ringstate(sc, tag); 2212 if (sc->sc_nqchip) { 2213 struct safe_ringentry *re = sc->sc_back; 2214 do { 2215 safe_dump_request(sc, tag, re); 2216 if (++re == sc->sc_ringtop) 2217 re = sc->sc_ring; 2218 } while (re != sc->sc_front); 2219 } 2220 lockmgr(&sc->sc_ringlock, LK_RELEASE); 2221 } 2222 2223 static int 2224 sysctl_hw_safe_dump(SYSCTL_HANDLER_ARGS) 2225 { 2226 char dmode[64]; 2227 int error; 2228 2229 strncpy(dmode, "", sizeof(dmode) - 1); 2230 dmode[sizeof(dmode) - 1] = '\0'; 2231 error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 2232 2233 if (error == 0 && req->newptr != NULL) { 2234 struct safe_softc *sc = safec; 2235 2236 if (!sc) 2237 return EINVAL; 2238 if (strncmp(dmode, "dma", 3) == 0) 2239 safe_dump_dmastatus(sc, "safe0"); 2240 else if (strncmp(dmode, "int", 3) == 0) 2241 safe_dump_intrstate(sc, "safe0"); 2242 else if (strncmp(dmode, "ring", 4) == 0) 2243 safe_dump_ring(sc, "safe0"); 2244 else 2245 return EINVAL; 2246 } 2247 return error; 2248 } 2249 SYSCTL_PROC(_hw_safe, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 2250 0, 0, sysctl_hw_safe_dump, "A", "Dump driver state"); 2251 #endif /* SAFE_DEBUG */ 2252