1 /* 2 * Copyright (c) 2008, 2009 Michael Shalayeff 3 * Copyright (c) 2009, 2010 Hans-Joerg Hoexer 4 * All rights reserved. 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN 15 * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 16 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $FreeBSD: src/sys/dev/tpm/tpm.c,v 1.1 2010/08/12 00:16:18 takawata Exp $ 19 */ 20 21 /* #define TPM_DEBUG */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/kernel.h> 26 #include <sys/malloc.h> 27 #include <sys/proc.h> 28 29 #include <sys/module.h> 30 #include <sys/conf.h> 31 #include <sys/uio.h> 32 #include <sys/bus.h> 33 #include <sys/device.h> 34 #include <sys/thread2.h> 35 36 #include <sys/rman.h> 37 38 #include <machine/md_var.h> 39 40 #include <bus/isa/isareg.h> 41 #include <bus/isa/isavar.h> 42 43 #include <dev/crypto/tpm/tpmvar.h> 44 45 #define TPM_BUFSIZ 1024 46 47 #define TPM_HDRSIZE 10 48 49 #define TPM_PARAM_SIZE 0x0001 50 51 #define IRQUNK -1 52 53 #define TPM_ACCESS 0x0000 /* acess register */ 54 #define TPM_ACCESS_ESTABLISHMENT 0x01 /* establishment */ 55 #define TPM_ACCESS_REQUEST_USE 0x02 /* request using locality */ 56 #define TPM_ACCESS_REQUEST_PENDING 0x04 /* pending request */ 57 #define TPM_ACCESS_SEIZE 0x08 /* request locality seize */ 58 #define TPM_ACCESS_SEIZED 0x10 /* locality has been seized */ 59 #define TPM_ACCESS_ACTIVE_LOCALITY 0x20 /* locality is active */ 60 #define TPM_ACCESS_VALID 0x80 /* bits are valid */ 61 #define TPM_ACCESS_BITS \ 62 "\020\01EST\02REQ\03PEND\04SEIZE\05SEIZED\06ACT\010VALID" 63 64 #define TPM_INTERRUPT_ENABLE 0x0008 65 #define TPM_GLOBAL_INT_ENABLE 0x80000000 /* enable ints */ 66 #define TPM_CMD_READY_INT 0x00000080 /* cmd ready enable */ 67 #define TPM_INT_EDGE_FALLING 0x00000018 68 #define TPM_INT_EDGE_RISING 0x00000010 69 #define TPM_INT_LEVEL_LOW 0x00000008 70 #define TPM_INT_LEVEL_HIGH 0x00000000 71 #define TPM_LOCALITY_CHANGE_INT 0x00000004 /* locality change enable */ 72 #define TPM_STS_VALID_INT 0x00000002 /* int on TPM_STS_VALID is set */ 73 #define TPM_DATA_AVAIL_INT 0x00000001 /* int on TPM_STS_DATA_AVAIL is set */ 74 #define TPM_INTERRUPT_ENABLE_BITS \ 75 "\020\040ENA\010RDY\03LOCH\02STSV\01DRDY" 76 77 #define TPM_INT_VECTOR 0x000c /* 8 bit reg for 4 bit irq vector */ 78 #define TPM_INT_STATUS 0x0010 /* bits are & 0x87 from TPM_INTERRUPT_ENABLE */ 79 80 #define TPM_INTF_CAPABILITIES 0x0014 /* capability register */ 81 #define TPM_INTF_BURST_COUNT_STATIC 0x0100 /* TPM_STS_BMASK static */ 82 #define TPM_INTF_CMD_READY_INT 0x0080 /* int on ready supported */ 83 #define TPM_INTF_INT_EDGE_FALLING 0x0040 /* falling edge ints supported */ 84 #define TPM_INTF_INT_EDGE_RISING 0x0020 /* rising edge ints supported */ 85 #define TPM_INTF_INT_LEVEL_LOW 0x0010 /* level-low ints supported */ 86 #define TPM_INTF_INT_LEVEL_HIGH 0x0008 /* level-high ints supported */ 87 #define TPM_INTF_LOCALITY_CHANGE_INT 0x0004 /* locality-change int (mb 1) */ 88 #define TPM_INTF_STS_VALID_INT 0x0002 /* TPM_STS_VALID int supported */ 89 #define TPM_INTF_DATA_AVAIL_INT 0x0001 /* TPM_STS_DATA_AVAIL int supported (mb 1) */ 90 #define TPM_CAPSREQ \ 91 (TPM_INTF_DATA_AVAIL_INT|TPM_INTF_LOCALITY_CHANGE_INT|TPM_INTF_INT_LEVEL_LOW) 92 #define TPM_CAPBITS \ 93 "\020\01IDRDY\02ISTSV\03ILOCH\04IHIGH\05ILOW\06IEDGE\07IFALL\010IRDY\011BCST" 94 95 #define TPM_STS 0x0018 /* status register */ 96 #define TPM_STS_MASK 0x000000ff /* status bits */ 97 #define TPM_STS_BMASK 0x00ffff00 /* ro io burst size */ 98 #define TPM_STS_VALID 0x00000080 /* ro other bits are valid */ 99 #define TPM_STS_CMD_READY 0x00000040 /* rw chip/signal ready */ 100 #define TPM_STS_GO 0x00000020 /* wo start the command */ 101 #define TPM_STS_DATA_AVAIL 0x00000010 /* ro data available */ 102 #define TPM_STS_DATA_EXPECT 0x00000008 /* ro more data to be written */ 103 #define TPM_STS_RESP_RETRY 0x00000002 /* wo resend the response */ 104 #define TPM_STS_BITS "\020\010VALID\07RDY\06GO\05DRDY\04EXPECT\02RETRY" 105 106 #define TPM_DATA 0x0024 107 #define TPM_ID 0x0f00 108 #define TPM_REV 0x0f04 109 #define TPM_SIZE 0x5000 /* five pages of the above */ 110 111 #define TPM_ACCESS_TMO 2000 /* 2sec */ 112 #define TPM_READY_TMO 2000 /* 2sec */ 113 #define TPM_READ_TMO 120000 /* 2 minutes */ 114 #define TPM_BURST_TMO 2000 /* 2sec */ 115 116 #define TPM_LEGACY_BUSY 0x01 117 #define TPM_LEGACY_ABRT 0x01 118 #define TPM_LEGACY_DA 0x02 119 #define TPM_LEGACY_RE 0x04 120 #define TPM_LEGACY_LAST 0x04 121 #define TPM_LEGACY_BITS "\020\01BUSY\2DA\3RE\4LAST" 122 #define TPM_LEGACY_TMO (2*60) /* sec */ 123 #define TPM_LEGACY_SLEEP 5 /* ticks */ 124 #define TPM_LEGACY_DELAY 100 125 126 /* Set when enabling legacy interface in host bridge. */ 127 int tpm_enabled; 128 129 130 #define TPMSOFTC(dev) \ 131 ((struct tpm_softc *)dev->si_drv1) 132 133 d_open_t tpmopen; 134 d_close_t tpmclose; 135 d_read_t tpmread; 136 d_write_t tpmwrite; 137 d_ioctl_t tpmioctl; 138 139 static struct dev_ops tpm_ops = { 140 { "tpm", 0, 0 }, 141 .d_open = tpmopen, 142 .d_close = tpmclose, 143 .d_read = tpmread, 144 .d_write = tpmwrite, 145 .d_ioctl = tpmioctl, 146 }; 147 148 const struct { 149 u_int32_t devid; 150 char name[32]; 151 int flags; 152 #define TPM_DEV_NOINTS 0x0001 153 } tpm_devs[] = { 154 { 0x000615d1, "IFX SLD 9630 TT 1.1", 0 }, 155 { 0x000b15d1, "IFX SLB 9635 TT 1.2", 0 }, 156 { 0x100214e4, "Broadcom BCM0102", TPM_DEV_NOINTS }, 157 { 0x00fe1050, "WEC WPCT200", 0 }, 158 { 0x687119fa, "SNS SSX35", 0 }, 159 { 0x2e4d5453, "STM ST19WP18", 0 }, 160 { 0x32021114, "ATML 97SC3203", TPM_DEV_NOINTS }, 161 { 0x10408086, "INTEL INTC0102", 0 }, 162 { 0, "", TPM_DEV_NOINTS }, 163 }; 164 165 int tpm_tis12_irqinit(struct tpm_softc *, int, int); 166 int tpm_tis12_init(struct tpm_softc *, int, const char *); 167 int tpm_tis12_start(struct tpm_softc *, int); 168 int tpm_tis12_read(struct tpm_softc *, void *, int, size_t *, int); 169 int tpm_tis12_write(struct tpm_softc *, void *, int); 170 int tpm_tis12_end(struct tpm_softc *, int, int); 171 172 void tpm_intr(void *); 173 174 int tpm_waitfor_poll(struct tpm_softc *, u_int8_t, int, void *); 175 int tpm_waitfor_int(struct tpm_softc *, u_int8_t, int, void *, int); 176 int tpm_waitfor(struct tpm_softc *, u_int8_t, int, void *); 177 int tpm_request_locality(struct tpm_softc *, int); 178 int tpm_getburst(struct tpm_softc *); 179 u_int8_t tpm_status(struct tpm_softc *); 180 int tpm_tmotohz(int); 181 182 int tpm_legacy_probe(bus_space_tag_t, bus_addr_t); 183 int tpm_legacy_init(struct tpm_softc *, int, const char *); 184 int tpm_legacy_start(struct tpm_softc *, int); 185 int tpm_legacy_read(struct tpm_softc *, void *, int, size_t *, int); 186 int tpm_legacy_write(struct tpm_softc *, void *, int); 187 int tpm_legacy_end(struct tpm_softc *, int, int); 188 189 /* 190 * FreeBSD specific code for probing and attaching TPM to device tree. 191 */ 192 #if 0 193 static void 194 tpm_identify(driver_t *driver, device_t parent) 195 { 196 BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "tpm", 0); 197 } 198 #endif 199 200 201 int 202 tpm_attach(device_t dev) 203 { 204 struct tpm_softc *sc = device_get_softc(dev); 205 int irq; 206 207 sc->mem_rid = 0; 208 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 209 RF_ACTIVE); 210 if (sc->mem_res == NULL) 211 return ENXIO; 212 213 sc->sc_bt = rman_get_bustag(sc->mem_res); 214 sc->sc_bh = rman_get_bushandle(sc->mem_res); 215 216 sc->irq_rid = 0; 217 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 218 RF_ACTIVE | RF_SHAREABLE); 219 if (sc->irq_res != NULL) 220 irq = rman_get_start(sc->irq_res); 221 else 222 irq = IRQUNK; 223 224 /* In case PnP probe this may contain some initialization. */ 225 tpm_tis12_probe(sc->sc_bt, sc->sc_bh); 226 227 if (tpm_legacy_probe(sc->sc_bt, sc->sc_bh)) { 228 sc->sc_init = tpm_legacy_init; 229 sc->sc_start = tpm_legacy_start; 230 sc->sc_read = tpm_legacy_read; 231 sc->sc_write = tpm_legacy_write; 232 sc->sc_end = tpm_legacy_end; 233 } else { 234 sc->sc_init = tpm_tis12_init; 235 sc->sc_start = tpm_tis12_start; 236 sc->sc_read = tpm_tis12_read; 237 sc->sc_write = tpm_tis12_write; 238 sc->sc_end = tpm_tis12_end; 239 } 240 241 kprintf("%s", device_get_name(dev)); 242 if ((sc->sc_init)(sc, irq, "tpm")) { 243 tpm_detach(dev); 244 return ENXIO; 245 } 246 247 if (sc->sc_init == tpm_tis12_init && sc->irq_res != NULL && 248 bus_setup_intr(dev, sc->irq_res, 0, 249 tpm_intr, sc, &sc->intr_cookie, NULL) != 0) { 250 tpm_detach(dev); 251 kprintf(": cannot establish interrupt\n"); 252 return 1; 253 } 254 255 sc->sc_cdev = make_dev(&tpm_ops, device_get_unit(dev), 256 UID_ROOT, GID_WHEEL, 0600, "tpm"); 257 sc->sc_cdev->si_drv1 = sc; 258 259 return 0; 260 } 261 262 int 263 tpm_detach(device_t dev) 264 { 265 struct tpm_softc * sc = device_get_softc(dev); 266 267 if(sc->intr_cookie){ 268 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 269 } 270 271 if(sc->mem_res){ 272 bus_release_resource(dev, SYS_RES_MEMORY, 273 sc->mem_rid, sc->mem_res); 274 } 275 276 if(sc->irq_res){ 277 bus_release_resource(dev, SYS_RES_IRQ, 278 sc->irq_rid, sc->irq_res); 279 } 280 if(sc->sc_cdev){ 281 destroy_dev(sc->sc_cdev); 282 } 283 284 return 0; 285 } 286 287 /* Probe TPM using TIS 1.2 interface. */ 288 int 289 tpm_tis12_probe(bus_space_tag_t bt, bus_space_handle_t bh) 290 { 291 u_int32_t r; 292 u_int8_t save, reg; 293 294 r = bus_space_read_4(bt, bh, TPM_INTF_CAPABILITIES); 295 if (r == 0xffffffff) 296 return 0; 297 298 #ifdef TPM_DEBUG 299 kprintf("tpm: caps=%pb%i\n", TPM_CAPBITS, r); 300 #endif 301 if ((r & TPM_CAPSREQ) != TPM_CAPSREQ || 302 !(r & (TPM_INTF_INT_EDGE_RISING | TPM_INTF_INT_LEVEL_LOW))) { 303 #ifdef TPM_DEBUG 304 kprintf("tpm: caps too low (caps=%pb%i)\n", TPM_CAPBITS, r); 305 #endif 306 return 0; 307 } 308 309 save = bus_space_read_1(bt, bh, TPM_ACCESS); 310 bus_space_write_1(bt, bh, TPM_ACCESS, TPM_ACCESS_REQUEST_USE); 311 reg = bus_space_read_1(bt, bh, TPM_ACCESS); 312 if ((reg & TPM_ACCESS_VALID) && (reg & TPM_ACCESS_ACTIVE_LOCALITY) && 313 bus_space_read_4(bt, bh, TPM_ID) != 0xffffffff) 314 return 1; 315 316 bus_space_write_1(bt, bh, TPM_ACCESS, save); 317 return 0; 318 } 319 320 /* 321 * Setup interrupt vector if one is provided and interrupts are know to 322 * work on that particular chip. 323 */ 324 int 325 tpm_tis12_irqinit(struct tpm_softc *sc, int irq, int idx) 326 { 327 u_int32_t r; 328 329 if ((irq == IRQUNK) || (tpm_devs[idx].flags & TPM_DEV_NOINTS)) { 330 sc->sc_vector = IRQUNK; 331 return 0; 332 } 333 334 /* Ack and disable all interrupts. */ 335 bus_space_write_4(sc->sc_bt, sc->sc_bh, TPM_INTERRUPT_ENABLE, 336 bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_INTERRUPT_ENABLE) & 337 ~TPM_GLOBAL_INT_ENABLE); 338 bus_space_write_4(sc->sc_bt, sc->sc_bh, TPM_INT_STATUS, 339 bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_INT_STATUS)); 340 341 /* Program interrupt vector. */ 342 bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_INT_VECTOR, irq); 343 sc->sc_vector = irq; 344 345 /* Program interrupt type. */ 346 if (sc->sc_capabilities & TPM_INTF_INT_EDGE_RISING) 347 r = TPM_INT_EDGE_RISING; 348 else if (sc->sc_capabilities & TPM_INTF_INT_LEVEL_HIGH) 349 r = TPM_INT_LEVEL_HIGH; 350 else 351 r = TPM_INT_LEVEL_LOW; 352 bus_space_write_4(sc->sc_bt, sc->sc_bh, TPM_INTERRUPT_ENABLE, r); 353 354 return 0; 355 } 356 357 /* Setup TPM using TIS 1.2 interface. */ 358 int 359 tpm_tis12_init(struct tpm_softc *sc, int irq, const char *name) 360 { 361 u_int32_t r; 362 int i; 363 364 r = bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_INTF_CAPABILITIES); 365 #ifdef TPM_DEBUG 366 kprintf(" caps=%pb%i ", TPM_CAPBITS, r); 367 #endif 368 if ((r & TPM_CAPSREQ) != TPM_CAPSREQ || 369 !(r & (TPM_INTF_INT_EDGE_RISING | TPM_INTF_INT_LEVEL_LOW))) { 370 kprintf(": capabilities too low (caps=%pb%i)\n", 371 TPM_CAPBITS, r); 372 return 1; 373 } 374 sc->sc_capabilities = r; 375 376 sc->sc_devid = bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_ID); 377 sc->sc_rev = bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_REV); 378 379 for (i = 0; tpm_devs[i].devid; i++) 380 if (tpm_devs[i].devid == sc->sc_devid) 381 break; 382 383 if (tpm_devs[i].devid) 384 kprintf(": %s rev 0x%x\n", tpm_devs[i].name, sc->sc_rev); 385 else 386 kprintf(": device 0x%08x rev 0x%x\n", sc->sc_devid, sc->sc_rev); 387 388 if (tpm_tis12_irqinit(sc, irq, i)) 389 return 1; 390 391 if (tpm_request_locality(sc, 0)) 392 return 1; 393 394 /* Abort whatever it thought it was doing. */ 395 bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS, TPM_STS_CMD_READY); 396 397 return 0; 398 } 399 400 int 401 tpm_request_locality(struct tpm_softc *sc, int l) 402 { 403 u_int32_t r; 404 int to, rv; 405 406 if (l != 0) 407 return EINVAL; 408 409 if ((bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_ACCESS) & 410 (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) == 411 (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) 412 return 0; 413 414 bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_ACCESS, 415 TPM_ACCESS_REQUEST_USE); 416 417 to = tpm_tmotohz(TPM_ACCESS_TMO); 418 419 while ((r = bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_ACCESS) & 420 (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) != 421 (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY) && to--) { 422 rv = tsleep(sc->sc_init, PCATCH, "tpm_locality", 1); 423 if (rv && rv != EWOULDBLOCK) { 424 #ifdef TPM_DEBUG 425 kprintf("%s: interrupted %d\n", __func__, rv); 426 #endif 427 return rv; 428 } 429 } 430 431 if ((r & (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) != 432 (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) { 433 #ifdef TPM_DEBUG 434 kprintf("%s: access %pb%i\n", __func__, TPM_ACCESS_BITS, r); 435 #endif 436 return EBUSY; 437 } 438 439 return 0; 440 } 441 442 int 443 tpm_getburst(struct tpm_softc *sc) 444 { 445 int burst, to, rv; 446 447 to = tpm_tmotohz(TPM_BURST_TMO); 448 449 burst = 0; 450 while (burst == 0 && to--) { 451 /* 452 * Burst count has to be read from bits 8 to 23 without 453 * touching any other bits, eg. the actual status bits 0 454 * to 7. 455 */ 456 burst = bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_STS + 1); 457 burst |= bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_STS + 2) 458 << 8; 459 #ifdef TPM_DEBUG 460 kprintf("%s: read %d\n", __func__, burst); 461 #endif 462 if (burst) 463 return burst; 464 465 rv = tsleep(sc, PCATCH, "tpm_getburst", 1); 466 if (rv && rv != EWOULDBLOCK) { 467 return 0; 468 } 469 } 470 471 return 0; 472 } 473 474 u_int8_t 475 tpm_status(struct tpm_softc *sc) 476 { 477 u_int8_t status; 478 479 status = bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_STS) & 480 TPM_STS_MASK; 481 482 return status; 483 } 484 485 int 486 tpm_tmotohz(int tmo) 487 { 488 struct timeval tv; 489 490 tv.tv_sec = tmo / 1000; 491 tv.tv_usec = 1000 * (tmo % 1000); 492 493 return tvtohz_high(&tv); 494 } 495 496 /* Save TPM state on suspend. */ 497 int 498 tpm_suspend(device_t dev) 499 { 500 struct tpm_softc *sc = device_get_softc(dev); 501 int why = 1; 502 u_int8_t command[] = { 503 0, 193, /* TPM_TAG_RQU_COMMAND */ 504 0, 0, 0, 10, /* Length in bytes */ 505 0, 0, 0, 156 /* TPM_ORD_SaveStates */ 506 }; 507 508 /* 509 * Power down: We have to issue the SaveStates command. 510 */ 511 sc->sc_write(sc, &command, sizeof(command)); 512 sc->sc_read(sc, &command, sizeof(command), NULL, TPM_HDRSIZE); 513 #ifdef TPM_DEBUG 514 kprintf("%s: power down: %d -> %d\n", __func__, sc->sc_suspend, why); 515 #endif 516 sc->sc_suspend = why; 517 518 return 0; 519 } 520 521 /* 522 * Handle resume event. Actually nothing to do as the BIOS is supposed 523 * to restore the previously saved state. 524 */ 525 int 526 tpm_resume(device_t dev) 527 { 528 struct tpm_softc *sc = device_get_softc(dev); 529 int why = 0; 530 531 #ifdef TPM_DEBUG 532 kprintf("%s: resume: %d -> %d\n", __func__, sc->sc_suspend, why); 533 #endif 534 sc->sc_suspend = why; 535 536 return 0; 537 } 538 539 /* Wait for given status bits using polling. */ 540 int 541 tpm_waitfor_poll(struct tpm_softc *sc, u_int8_t mask, int tmo, void *c) 542 { 543 int rv; 544 545 /* 546 * Poll until either the requested condition or a time out is 547 * met. 548 */ 549 while (((sc->sc_stat = tpm_status(sc)) & mask) != mask && tmo--) { 550 rv = tsleep(c, PCATCH, "tpm_poll", 1); 551 if (rv && rv != EWOULDBLOCK) { 552 #ifdef TPM_DEBUG 553 kprintf("%s: interrupted %d\n", __func__, rv); 554 #endif 555 return rv; 556 } 557 } 558 559 return 0; 560 } 561 562 /* Wait for given status bits using interrupts. */ 563 int 564 tpm_waitfor_int(struct tpm_softc *sc, u_int8_t mask, int tmo, void *c, 565 int inttype) 566 { 567 int rv, to; 568 569 /* Poll and return when condition is already met. */ 570 sc->sc_stat = tpm_status(sc); 571 if ((sc->sc_stat & mask) == mask) 572 return 0; 573 574 /* 575 * Enable interrupt on tpm chip. Note that interrupts on our 576 * level (SPL_TTY) are disabled (see tpm{read,write} et al) and 577 * will not be delivered to the cpu until we call tsleep(9) below. 578 */ 579 bus_space_write_4(sc->sc_bt, sc->sc_bh, TPM_INTERRUPT_ENABLE, 580 bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_INTERRUPT_ENABLE) | 581 inttype); 582 bus_space_write_4(sc->sc_bt, sc->sc_bh, TPM_INTERRUPT_ENABLE, 583 bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_INTERRUPT_ENABLE) | 584 TPM_GLOBAL_INT_ENABLE); 585 586 /* 587 * Poll once more to remedy the race between previous polling 588 * and enabling interrupts on the tpm chip. 589 */ 590 sc->sc_stat = tpm_status(sc); 591 if ((sc->sc_stat & mask) == mask) { 592 rv = 0; 593 goto out; 594 } 595 596 to = tpm_tmotohz(tmo); 597 #ifdef TPM_DEBUG 598 kprintf("%s: sleeping for %d ticks on %p\n", __func__, to, c); 599 #endif 600 /* 601 * tsleep(9) enables interrupts on the cpu and returns after 602 * wake up with interrupts disabled again. Note that interrupts 603 * generated by the tpm chip while being at SPL_TTY are not lost 604 * but held and delivered as soon as the cpu goes below SPL_TTY. 605 */ 606 rv = tsleep(c, PCATCH, "tpm_intr", to); 607 608 sc->sc_stat = tpm_status(sc); 609 #ifdef TPM_DEBUG 610 kprintf("%s: woke up with rv %d stat %pb%i\n", __func__, rv, 611 TPM_STS_BITS, sc->sc_stat); 612 #endif 613 if ((sc->sc_stat & mask) == mask) 614 rv = 0; 615 616 /* Disable interrupts on tpm chip again. */ 617 out: bus_space_write_4(sc->sc_bt, sc->sc_bh, TPM_INTERRUPT_ENABLE, 618 bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_INTERRUPT_ENABLE) & 619 ~TPM_GLOBAL_INT_ENABLE); 620 bus_space_write_4(sc->sc_bt, sc->sc_bh, TPM_INTERRUPT_ENABLE, 621 bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_INTERRUPT_ENABLE) & 622 ~inttype); 623 624 return rv; 625 } 626 627 /* 628 * Wait on given status bits, uses interrupts where possible, otherwise polls. 629 */ 630 int 631 tpm_waitfor(struct tpm_softc *sc, u_int8_t b0, int tmo, void *c) 632 { 633 u_int8_t b; 634 int re, to, rv; 635 636 #ifdef TPM_DEBUG 637 kprintf("%s: b0 %pb%i\n", __func__, TPM_STS_BITS, b0); 638 #endif 639 640 /* 641 * If possible, use interrupts, otherwise poll. 642 * 643 * We use interrupts for TPM_STS_VALID and TPM_STS_DATA_AVAIL (if 644 * the tpm chips supports them) as waiting for those can take 645 * really long. The other TPM_STS* are not needed very often 646 * so we do not support them. 647 */ 648 if (sc->sc_vector != IRQUNK) { 649 b = b0; 650 651 /* 652 * Wait for data ready. This interrupt only occures 653 * when both TPM_STS_VALID and TPM_STS_DATA_AVAIL are asserted. 654 * Thus we don't have to bother with TPM_STS_VALID 655 * separately and can just return. 656 * 657 * This only holds for interrupts! When using polling 658 * both flags have to be waited for, see below. 659 */ 660 if ((b & TPM_STS_DATA_AVAIL) && (sc->sc_capabilities & 661 TPM_INTF_DATA_AVAIL_INT)) 662 return tpm_waitfor_int(sc, b, tmo, c, 663 TPM_DATA_AVAIL_INT); 664 665 /* Wait for status valid bit. */ 666 if ((b & TPM_STS_VALID) && (sc->sc_capabilities & 667 TPM_INTF_STS_VALID_INT)) { 668 rv = tpm_waitfor_int(sc, b, tmo, c, TPM_STS_VALID_INT); 669 if (rv != 0) 670 return rv; 671 else 672 b = b0 & ~TPM_STS_VALID; 673 } 674 675 /* 676 * When all flags are taken care of, return. Otherwise 677 * use polling for eg. TPM_STS_CMD_READY. 678 */ 679 if (b == 0) 680 return 0; 681 } 682 683 re = 3; 684 restart: 685 /* 686 * If requested wait for TPM_STS_VALID before dealing with 687 * any other flag. Eg. when both TPM_STS_DATA_AVAIL and TPM_STS_VALID 688 * are requested, wait for the latter first. 689 */ 690 b = b0; 691 if (b0 & TPM_STS_VALID) 692 b = TPM_STS_VALID; 693 694 to = tpm_tmotohz(tmo); 695 again: 696 if ((rv = tpm_waitfor_poll(sc, b, to, c)) != 0) 697 return rv; 698 699 if ((b & sc->sc_stat) == TPM_STS_VALID) { 700 /* Now wait for other flags. */ 701 b = b0 & ~TPM_STS_VALID; 702 to++; 703 goto again; 704 } 705 706 if ((sc->sc_stat & b) != b) { 707 #ifdef TPM_DEBUG 708 kprintf("%s: timeout: stat=%pb%i b=%pb%i\n", __func__, 709 TPM_STS_BITS, sc->sc_stat, TPM_STS_BITS, b); 710 #endif 711 if (re-- && (b0 & TPM_STS_VALID)) { 712 bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS, 713 TPM_STS_RESP_RETRY); 714 goto restart; 715 } 716 return EIO; 717 } 718 719 return 0; 720 } 721 722 /* Start transaction. */ 723 int 724 tpm_tis12_start(struct tpm_softc *sc, int flag) 725 { 726 int rv; 727 728 if (flag == UIO_READ) { 729 rv = tpm_waitfor(sc, TPM_STS_DATA_AVAIL | TPM_STS_VALID, 730 TPM_READ_TMO, sc->sc_read); 731 return rv; 732 } 733 734 /* Own our (0th) locality. */ 735 if ((rv = tpm_request_locality(sc, 0)) != 0) 736 return rv; 737 738 sc->sc_stat = tpm_status(sc); 739 if (sc->sc_stat & TPM_STS_CMD_READY) { 740 #ifdef TPM_DEBUG 741 kprintf("%s: UIO_WRITE status %pb%i\n", __func__, 742 TPM_STS_BITS, sc->sc_stat); 743 #endif 744 return 0; 745 } 746 747 #ifdef TPM_DEBUG 748 kprintf("%s: UIO_WRITE readying chip\n", __func__); 749 #endif 750 751 /* Abort previous and restart. */ 752 bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS, TPM_STS_CMD_READY); 753 if ((rv = tpm_waitfor(sc, TPM_STS_CMD_READY, TPM_READY_TMO, 754 sc->sc_write))) { 755 #ifdef TPM_DEBUG 756 kprintf("%s: UIO_WRITE readying failed %d\n", __func__, rv); 757 #endif 758 return rv; 759 } 760 761 #ifdef TPM_DEBUG 762 kprintf("%s: UIO_WRITE readying done\n", __func__); 763 #endif 764 765 return 0; 766 } 767 768 int 769 tpm_tis12_read(struct tpm_softc *sc, void *buf, int len, size_t *count, 770 int flags) 771 { 772 u_int8_t *p = buf; 773 size_t cnt; 774 int rv, n, bcnt; 775 776 #ifdef TPM_DEBUG 777 kprintf("%s: len %d\n", __func__, len); 778 #endif 779 cnt = 0; 780 while (len > 0) { 781 if ((rv = tpm_waitfor(sc, TPM_STS_DATA_AVAIL | TPM_STS_VALID, 782 TPM_READ_TMO, sc->sc_read))) 783 return rv; 784 785 bcnt = tpm_getburst(sc); 786 n = MIN(len, bcnt); 787 #ifdef TPM_DEBUG 788 kprintf("%s: fetching %d, burst is %d\n", __func__, n, bcnt); 789 #endif 790 for (; n--; len--) { 791 *p++ = bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_DATA); 792 cnt++; 793 } 794 795 if ((flags & TPM_PARAM_SIZE) == 0 && cnt >= 6) 796 break; 797 } 798 #ifdef TPM_DEBUG 799 kprintf("%s: read %zd bytes, len %d\n", __func__, cnt, len); 800 #endif 801 802 if (count) 803 *count = cnt; 804 805 return 0; 806 } 807 808 int 809 tpm_tis12_write(struct tpm_softc *sc, void *buf, int len) 810 { 811 u_int8_t *p = buf; 812 size_t cnt; 813 int rv, r; 814 815 #ifdef TPM_DEBUG 816 kprintf("%s: sc %p buf %p len %d\n", __func__, sc, buf, len); 817 #endif 818 819 if ((rv = tpm_request_locality(sc, 0)) != 0) 820 return rv; 821 822 cnt = 0; 823 while (cnt < len - 1) { 824 for (r = tpm_getburst(sc); r > 0 && cnt < len - 1; r--) { 825 bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_DATA, *p++); 826 cnt++; 827 } 828 if ((rv = tpm_waitfor(sc, TPM_STS_VALID, TPM_READ_TMO, sc))) { 829 #ifdef TPM_DEBUG 830 kprintf("%s: failed burst rv %d\n", __func__, rv); 831 #endif 832 return rv; 833 } 834 sc->sc_stat = tpm_status(sc); 835 if (!(sc->sc_stat & TPM_STS_DATA_EXPECT)) { 836 #ifdef TPM_DEBUG 837 kprintf("%s: failed rv %d stat=%pb%i\n", __func__, rv, 838 TPM_STS_BITS, sc->sc_stat); 839 #endif 840 return EIO; 841 } 842 } 843 844 bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_DATA, *p++); 845 cnt++; 846 847 if ((rv = tpm_waitfor(sc, TPM_STS_VALID, TPM_READ_TMO, sc))) { 848 #ifdef TPM_DEBUG 849 kprintf("%s: failed last byte rv %d\n", __func__, rv); 850 #endif 851 return rv; 852 } 853 if ((sc->sc_stat & TPM_STS_DATA_EXPECT) != 0) { 854 #ifdef TPM_DEBUG 855 kprintf("%s: failed rv %d stat=%pb%i\n", __func__, rv, 856 TPM_STS_BITS, sc->sc_stat); 857 #endif 858 return EIO; 859 } 860 861 #ifdef TPM_DEBUG 862 kprintf("%s: wrote %zd byte\n", __func__, cnt); 863 #endif 864 865 return 0; 866 } 867 868 /* Finish transaction. */ 869 int 870 tpm_tis12_end(struct tpm_softc *sc, int flag, int err) 871 { 872 int rv = 0; 873 874 if (flag == UIO_READ) { 875 if ((rv = tpm_waitfor(sc, TPM_STS_VALID, TPM_READ_TMO, 876 sc->sc_read))) 877 return rv; 878 879 /* Still more data? */ 880 sc->sc_stat = tpm_status(sc); 881 if (!err && ((sc->sc_stat & TPM_STS_DATA_AVAIL) == TPM_STS_DATA_AVAIL)) { 882 #ifdef TPM_DEBUG 883 kprintf("%s: read failed stat=%pb%i\n", __func__, 884 TPM_STS_BITS, sc->sc_stat); 885 #endif 886 rv = EIO; 887 } 888 889 bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS, 890 TPM_STS_CMD_READY); 891 892 /* Release our (0th) locality. */ 893 bus_space_write_1(sc->sc_bt, sc->sc_bh,TPM_ACCESS, 894 TPM_ACCESS_ACTIVE_LOCALITY); 895 } else { 896 /* Hungry for more? */ 897 sc->sc_stat = tpm_status(sc); 898 if (!err && (sc->sc_stat & TPM_STS_DATA_EXPECT)) { 899 #ifdef TPM_DEBUG 900 kprintf("%s: write failed stat=%pb%i\n", __func__, 901 TPM_STS_BITS, sc->sc_stat); 902 #endif 903 rv = EIO; 904 } 905 906 bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS, 907 err ? TPM_STS_CMD_READY : TPM_STS_GO); 908 } 909 910 return rv; 911 } 912 913 void 914 tpm_intr(void *v) 915 { 916 struct tpm_softc *sc = v; 917 u_int32_t r; 918 #ifdef TPM_DEBUG 919 static int cnt = 0; 920 #endif 921 922 r = bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_INT_STATUS); 923 #ifdef TPM_DEBUG 924 if (r != 0) 925 kprintf("%s: int=%pb%i (%d)\n", __func__, 926 TPM_INTERRUPT_ENABLE_BITS, r, cnt); 927 else 928 cnt++; 929 #endif 930 if (!(r & (TPM_CMD_READY_INT | TPM_LOCALITY_CHANGE_INT | 931 TPM_STS_VALID_INT | TPM_DATA_AVAIL_INT))) 932 return; 933 934 if (r & TPM_STS_VALID_INT) 935 wakeup(sc); 936 937 if (r & TPM_CMD_READY_INT) 938 wakeup(sc->sc_write); 939 940 if (r & TPM_DATA_AVAIL_INT) 941 wakeup(sc->sc_read); 942 943 if (r & TPM_LOCALITY_CHANGE_INT) 944 wakeup(sc->sc_init); 945 946 bus_space_write_4(sc->sc_bt, sc->sc_bh, TPM_INT_STATUS, r); 947 948 return; 949 } 950 951 /* Read single byte using legacy interface. */ 952 static inline u_int8_t 953 tpm_legacy_in(bus_space_tag_t iot, bus_space_handle_t ioh, int reg) 954 { 955 bus_space_write_1(iot, ioh, 0, reg); 956 return bus_space_read_1(iot, ioh, 1); 957 } 958 959 /* Write single byte using legacy interface. */ 960 static inline void 961 tpm_legacy_out(bus_space_tag_t iot, bus_space_handle_t ioh, int reg, u_int8_t v) 962 { 963 bus_space_write_1(iot, ioh, 0, reg); 964 bus_space_write_1(iot, ioh, 1, v); 965 } 966 967 /* Probe for TPM using legacy interface. */ 968 int 969 tpm_legacy_probe(bus_space_tag_t iot, bus_addr_t iobase) 970 { 971 bus_space_handle_t ioh; 972 u_int8_t r, v; 973 int i, rv = 0; 974 char id[8]; 975 976 if (!tpm_enabled || iobase == -1) 977 return 0; 978 979 #if 0 /* XXX swildner*/ 980 if (bus_space_map(iot, iobase, 2, 0, &ioh)) 981 return 0; 982 #else 983 ioh = iobase; 984 #endif 985 986 v = bus_space_read_1(iot, ioh, 0); 987 if (v == 0xff) { 988 bus_space_unmap(iot, ioh, 2); 989 return 0; 990 } 991 r = bus_space_read_1(iot, ioh, 1); 992 993 for (i = sizeof(id); i--; ) 994 id[i] = tpm_legacy_in(iot, ioh, TPM_ID + i); 995 996 #ifdef TPM_DEBUG 997 kprintf("%s: %.4s %d.%d.%d.%d\n", __func__, 998 &id[4], id[0], id[1], id[2], id[3]); 999 #endif 1000 /* 1001 * The only chips using the legacy interface we are aware of are 1002 * by Atmel. For other chips more signature would have to be added. 1003 */ 1004 if (!bcmp(&id[4], "ATML", 4)) 1005 rv = 1; 1006 1007 if (!rv) { 1008 bus_space_write_1(iot, ioh, r, 1); 1009 bus_space_write_1(iot, ioh, v, 0); 1010 } 1011 bus_space_unmap(iot, ioh, 2); 1012 1013 return rv; 1014 } 1015 1016 /* Setup TPM using legacy interface. */ 1017 int 1018 tpm_legacy_init(struct tpm_softc *sc, int irq, const char *name) 1019 { 1020 char id[8]; 1021 u_int8_t ioh, iol; 1022 int i; 1023 1024 #if 0 /* XXX swildner*/ 1025 if ((i = bus_space_map(sc->sc_batm, tpm_enabled, 2, 0, &sc->sc_bahm))) { 1026 kprintf(": cannot map tpm registers (%d)\n", i); 1027 tpm_enabled = 0; 1028 return 1; 1029 } 1030 #else 1031 sc->sc_bahm = tpm_enabled; 1032 #endif 1033 1034 for (i = sizeof(id); i--; ) 1035 id[i] = tpm_legacy_in(sc->sc_bt, sc->sc_bh, TPM_ID + i); 1036 1037 kprintf(": %.4s %d.%d @0x%x\n", &id[4], id[0], id[1], tpm_enabled); 1038 iol = tpm_enabled & 0xff; 1039 ioh = tpm_enabled >> 16; 1040 tpm_enabled = 0; 1041 1042 return 0; 1043 } 1044 1045 /* Start transaction. */ 1046 int 1047 tpm_legacy_start(struct tpm_softc *sc, int flag) 1048 { 1049 struct timeval tv; 1050 u_int8_t bits, r; 1051 int to, rv; 1052 1053 bits = flag == UIO_READ ? TPM_LEGACY_DA : 0; 1054 tv.tv_sec = TPM_LEGACY_TMO; 1055 tv.tv_usec = 0; 1056 to = tvtohz_high(&tv) / TPM_LEGACY_SLEEP; 1057 while (((r = bus_space_read_1(sc->sc_batm, sc->sc_bahm, 1)) & 1058 (TPM_LEGACY_BUSY|bits)) != bits && to--) { 1059 rv = tsleep(sc, PCATCH, "legacy_tpm_start", 1060 TPM_LEGACY_SLEEP); 1061 if (rv && rv != EWOULDBLOCK) 1062 return rv; 1063 } 1064 1065 if ((r & (TPM_LEGACY_BUSY|bits)) != bits) 1066 return EIO; 1067 1068 return 0; 1069 } 1070 1071 int 1072 tpm_legacy_read(struct tpm_softc *sc, void *buf, int len, size_t *count, 1073 int flags) 1074 { 1075 u_int8_t *p; 1076 size_t cnt; 1077 int to, rv; 1078 1079 cnt = rv = 0; 1080 for (p = buf; !rv && len > 0; len--) { 1081 for (to = 1000; 1082 !(bus_space_read_1(sc->sc_batm, sc->sc_bahm, 1) & 1083 TPM_LEGACY_DA); DELAY(1)) 1084 if (!to--) 1085 return EIO; 1086 1087 DELAY(TPM_LEGACY_DELAY); 1088 *p++ = bus_space_read_1(sc->sc_batm, sc->sc_bahm, 0); 1089 cnt++; 1090 } 1091 1092 *count = cnt; 1093 return 0; 1094 } 1095 1096 int 1097 tpm_legacy_write(struct tpm_softc *sc, void *buf, int len) 1098 { 1099 u_int8_t *p; 1100 int n; 1101 1102 for (p = buf, n = len; n--; DELAY(TPM_LEGACY_DELAY)) { 1103 if (!n && len != TPM_BUFSIZ) { 1104 bus_space_write_1(sc->sc_batm, sc->sc_bahm, 1, 1105 TPM_LEGACY_LAST); 1106 DELAY(TPM_LEGACY_DELAY); 1107 } 1108 bus_space_write_1(sc->sc_batm, sc->sc_bahm, 0, *p++); 1109 } 1110 1111 return 0; 1112 } 1113 1114 /* Finish transaction. */ 1115 int 1116 tpm_legacy_end(struct tpm_softc *sc, int flag, int rv) 1117 { 1118 struct timeval tv; 1119 u_int8_t r; 1120 int to; 1121 1122 if (rv || flag == UIO_READ) 1123 bus_space_write_1(sc->sc_batm, sc->sc_bahm, 1, TPM_LEGACY_ABRT); 1124 else { 1125 tv.tv_sec = TPM_LEGACY_TMO; 1126 tv.tv_usec = 0; 1127 to = tvtohz_high(&tv) / TPM_LEGACY_SLEEP; 1128 while(((r = bus_space_read_1(sc->sc_batm, sc->sc_bahm, 1)) & 1129 TPM_LEGACY_BUSY) && to--) { 1130 rv = tsleep(sc, PCATCH, "legacy_tpm_end", 1131 TPM_LEGACY_SLEEP); 1132 if (rv && rv != EWOULDBLOCK) 1133 return rv; 1134 } 1135 1136 if (r & TPM_LEGACY_BUSY) 1137 return EIO; 1138 1139 if (r & TPM_LEGACY_RE) 1140 return EIO; /* XXX Retry the loop? */ 1141 } 1142 1143 return rv; 1144 } 1145 1146 int 1147 tpmopen(struct dev_open_args *ap) 1148 { 1149 cdev_t dev = ap->a_head.a_dev; 1150 struct tpm_softc *sc = TPMSOFTC(dev); 1151 1152 if (!sc) 1153 return ENXIO; 1154 1155 if (sc->sc_flags & TPM_OPEN) 1156 return EBUSY; 1157 1158 sc->sc_flags |= TPM_OPEN; 1159 1160 return 0; 1161 } 1162 1163 int 1164 tpmclose(struct dev_close_args *ap) 1165 { 1166 cdev_t dev = ap->a_head.a_dev; 1167 struct tpm_softc *sc = TPMSOFTC(dev); 1168 1169 if (!sc) 1170 return ENXIO; 1171 1172 if (!(sc->sc_flags & TPM_OPEN)) 1173 return EINVAL; 1174 1175 sc->sc_flags &= ~TPM_OPEN; 1176 1177 return 0; 1178 } 1179 1180 int 1181 tpmread(struct dev_read_args *ap) 1182 { 1183 cdev_t dev = ap->a_head.a_dev; 1184 struct uio *uio = ap->a_uio; 1185 struct tpm_softc *sc = TPMSOFTC(dev); 1186 u_int8_t buf[TPM_BUFSIZ], *p; 1187 size_t cnt; 1188 int n, len, rv; 1189 1190 if (!sc) 1191 return ENXIO; 1192 1193 crit_enter(); 1194 if ((rv = (sc->sc_start)(sc, UIO_READ))) { 1195 crit_exit(); 1196 return rv; 1197 } 1198 1199 #ifdef TPM_DEBUG 1200 kprintf("%s: getting header\n", __func__); 1201 #endif 1202 if ((rv = (sc->sc_read)(sc, buf, TPM_HDRSIZE, &cnt, 0))) { 1203 (sc->sc_end)(sc, UIO_READ, rv); 1204 crit_exit(); 1205 return rv; 1206 } 1207 1208 len = (buf[2] << 24) | (buf[3] << 16) | (buf[4] << 8) | buf[5]; 1209 #ifdef TPM_DEBUG 1210 kprintf("%s: len %d, io count %zd\n", __func__, len, uio->uio_resid); 1211 #endif 1212 if (len > uio->uio_resid) { 1213 rv = EIO; 1214 (sc->sc_end)(sc, UIO_READ, rv); 1215 #ifdef TPM_DEBUG 1216 kprintf("%s: bad residual io count 0x%zx\n", __func__, 1217 uio->uio_resid); 1218 #endif 1219 crit_exit(); 1220 return rv; 1221 } 1222 1223 /* Copy out header. */ 1224 if ((rv = uiomove((caddr_t)buf, cnt, uio))) { 1225 (sc->sc_end)(sc, UIO_READ, rv); 1226 crit_exit(); 1227 return rv; 1228 } 1229 1230 /* Get remaining part of the answer (if anything is left). */ 1231 for (len -= cnt, p = buf, n = sizeof(buf); len > 0; p = buf, len -= n, 1232 n = sizeof(buf)) { 1233 n = MIN(n, len); 1234 #ifdef TPM_DEBUG 1235 kprintf("%s: n %d len %d\n", __func__, n, len); 1236 #endif 1237 if ((rv = (sc->sc_read)(sc, p, n, NULL, TPM_PARAM_SIZE))) { 1238 (sc->sc_end)(sc, UIO_READ, rv); 1239 crit_exit(); 1240 return rv; 1241 } 1242 p += n; 1243 if ((rv = uiomove((caddr_t)buf, p - buf, uio))) { 1244 (sc->sc_end)(sc, UIO_READ, rv); 1245 crit_exit(); 1246 return rv; 1247 } 1248 } 1249 1250 rv = (sc->sc_end)(sc, UIO_READ, rv); 1251 crit_exit(); 1252 return rv; 1253 } 1254 1255 int 1256 tpmwrite(struct dev_write_args *ap) 1257 { 1258 cdev_t dev = ap->a_head.a_dev; 1259 struct uio *uio = ap->a_uio; 1260 struct tpm_softc *sc = TPMSOFTC(dev); 1261 u_int8_t buf[TPM_BUFSIZ]; 1262 int n, rv; 1263 1264 if (!sc) 1265 return ENXIO; 1266 1267 crit_enter(); 1268 1269 #ifdef TPM_DEBUG 1270 kprintf("%s: io count %zd\n", __func__, uio->uio_resid); 1271 #endif 1272 1273 n = MIN(sizeof(buf), uio->uio_resid); 1274 if ((rv = uiomove((caddr_t)buf, n, uio))) { 1275 crit_exit(); 1276 return rv; 1277 } 1278 1279 if ((rv = (sc->sc_start)(sc, UIO_WRITE))) { 1280 crit_exit(); 1281 return rv; 1282 } 1283 1284 if ((rv = (sc->sc_write(sc, buf, n)))) { 1285 crit_exit(); 1286 return rv; 1287 } 1288 1289 rv = (sc->sc_end)(sc, UIO_WRITE, rv); 1290 crit_exit(); 1291 return rv; 1292 } 1293 1294 int 1295 tpmioctl(struct dev_ioctl_args *ap) 1296 { 1297 return ENOTTY; 1298 } 1299