1 /* 2 * Device probe and attach routines for the following 3 * Advanced Systems Inc. SCSI controllers: 4 * 5 * Connectivity Products: 6 * ABP902/3902 - Bus-Master PCI (16 CDB) 7 * ABP3905 - Bus-Master PCI (16 CDB) 8 * ABP915 - Bus-Master PCI (16 CDB) 9 * ABP920 - Bus-Master PCI (16 CDB) 10 * ABP3922 - Bus-Master PCI (16 CDB) 11 * ABP3925 - Bus-Master PCI (16 CDB) 12 * ABP930 - Bus-Master PCI (16 CDB) * 13 * ABP930U - Bus-Master PCI Ultra (16 CDB) 14 * ABP930UA - Bus-Master PCI Ultra (16 CDB) 15 * ABP960 - Bus-Master PCI MAC/PC (16 CDB) ** 16 * ABP960U - Bus-Master PCI MAC/PC (16 CDB) ** 17 * 18 * Single Channel Products: 19 * ABP940 - Bus-Master PCI (240 CDB) 20 * ABP940U - Bus-Master PCI Ultra (240 CDB) 21 * ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB) 22 * ABP3960UA - Bus-Master PCI MAC/PC (240 CDB) 23 * ABP970 - Bus-Master PCI MAC/PC (240 CDB) 24 * ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB) 25 * 26 * Dual Channel Products: 27 * ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel) 28 * ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel) 29 * ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel) 30 * ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.) 31 * 32 * Footnotes: 33 * * This board has been sold by SIIG as the Fast SCSI Pro PCI. 34 * ** This board has been sold by Iomega as a Jaz Jet PCI adapter. 35 * 36 * Copyright (c) 1997 Justin Gibbs. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions, and the following disclaimer, 44 * without modification. 45 * 2. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 52 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * $FreeBSD: src/sys/dev/advansys/adv_pci.c,v 1.11.2.3 2001/06/02 04:38:10 nyan Exp $ 61 * $DragonFly: src/sys/dev/disk/advansys/adv_pci.c,v 1.5 2005/10/12 17:35:49 dillon Exp $ 62 */ 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/kernel.h> 67 68 #include <machine/bus_pio.h> 69 #include <machine/bus.h> 70 #include <machine/resource.h> 71 #include <sys/bus.h> 72 #include <sys/rman.h> 73 74 #include <bus/pci/pcireg.h> 75 #include <bus/pci/pcivar.h> 76 77 #include "advansys.h" 78 79 #define PCI_BASEADR0 PCIR_MAPS /* I/O Address */ 80 #define PCI_BASEADR1 PCIR_MAPS + 4 /* Mem I/O Address */ 81 82 #define PCI_DEVICE_ID_ADVANSYS_1200A 0x110010CD 83 #define PCI_DEVICE_ID_ADVANSYS_1200B 0x120010CD 84 #define PCI_DEVICE_ID_ADVANSYS_3000 0x130010CD 85 #define PCI_DEVICE_REV_ADVANSYS_3150 0x02 86 #define PCI_DEVICE_REV_ADVANSYS_3050 0x03 87 88 #define ADV_PCI_MAX_DMA_ADDR (0xFFFFFFFFL) 89 #define ADV_PCI_MAX_DMA_COUNT (0xFFFFFFFFL) 90 91 static int adv_pci_probe(device_t); 92 static int adv_pci_attach(device_t); 93 94 /* 95 * The overrun buffer shared amongst all PCI adapters. 96 */ 97 static u_int8_t* overrun_buf; 98 static bus_dma_tag_t overrun_dmat; 99 static bus_dmamap_t overrun_dmamap; 100 static bus_addr_t overrun_physbase; 101 102 static int 103 adv_pci_probe(device_t dev) 104 { 105 int rev = pci_get_revid(dev); 106 107 switch (pci_get_devid(dev)) { 108 case PCI_DEVICE_ID_ADVANSYS_1200A: 109 device_set_desc(dev, "AdvanSys ASC1200A SCSI controller"); 110 return 0; 111 case PCI_DEVICE_ID_ADVANSYS_1200B: 112 device_set_desc(dev, "AdvanSys ASC1200B SCSI controller"); 113 return 0; 114 case PCI_DEVICE_ID_ADVANSYS_3000: 115 if (rev == PCI_DEVICE_REV_ADVANSYS_3150) { 116 device_set_desc(dev, 117 "AdvanSys ASC3150 SCSI controller"); 118 return 0; 119 } else if (rev == PCI_DEVICE_REV_ADVANSYS_3050) { 120 device_set_desc(dev, 121 "AdvanSys ASC3030/50 SCSI controller"); 122 return 0; 123 } else if (rev >= PCI_DEVICE_REV_ADVANSYS_3150) { 124 device_set_desc(dev, "Unknown AdvanSys controller"); 125 return 0; 126 } 127 break; 128 default: 129 break; 130 } 131 return ENXIO; 132 } 133 134 static int 135 adv_pci_attach(device_t dev) 136 { 137 struct adv_softc *adv; 138 u_int32_t id; 139 u_int32_t command; 140 int error, rid, irqrid; 141 void *ih; 142 struct resource *iores, *irqres; 143 144 /* 145 * Determine the chip version. 146 */ 147 id = pci_read_config(dev, PCIR_DEVVENDOR, /*bytes*/4); 148 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 149 150 /* 151 * These cards do not allow memory mapped accesses, so we must 152 * ensure that I/O accesses are available or we won't be able 153 * to talk to them. 154 */ 155 if ((command & (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN)) 156 != (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN)) { 157 command |= PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN; 158 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); 159 } 160 161 /* 162 * Early chips can't handle non-zero latency timer settings. 163 */ 164 if (id == PCI_DEVICE_ID_ADVANSYS_1200A 165 || id == PCI_DEVICE_ID_ADVANSYS_1200B) { 166 pci_write_config(dev, PCIR_LATTIMER, /*value*/0, /*bytes*/1); 167 } 168 169 rid = PCI_BASEADR0; 170 iores = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1, 171 RF_ACTIVE); 172 if (iores == NULL) 173 return ENXIO; 174 175 if (adv_find_signature(rman_get_bustag(iores), 176 rman_get_bushandle(iores)) == 0) { 177 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 178 return ENXIO; 179 } 180 181 adv = adv_alloc(dev, rman_get_bustag(iores), rman_get_bushandle(iores)); 182 if (adv == NULL) { 183 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 184 return ENXIO; 185 } 186 187 /* Allocate a dmatag for our transfer DMA maps */ 188 /* XXX Should be a child of the PCI bus dma tag */ 189 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1, 190 /*boundary*/0, 191 /*lowaddr*/ADV_PCI_MAX_DMA_ADDR, 192 /*highaddr*/BUS_SPACE_MAXADDR, 193 /*filter*/NULL, /*filterarg*/NULL, 194 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT, 195 /*nsegments*/BUS_SPACE_UNRESTRICTED, 196 /*maxsegsz*/ADV_PCI_MAX_DMA_COUNT, 197 /*flags*/0, 198 &adv->parent_dmat); 199 200 if (error != 0) { 201 printf("%s: Could not allocate DMA tag - error %d\n", 202 adv_name(adv), error); 203 adv_free(adv); 204 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 205 return ENXIO; 206 } 207 208 adv->init_level++; 209 210 if (overrun_buf == NULL) { 211 /* Need to allocate our overrun buffer */ 212 if (bus_dma_tag_create(adv->parent_dmat, 213 /*alignment*/8, /*boundary*/0, 214 ADV_PCI_MAX_DMA_ADDR, BUS_SPACE_MAXADDR, 215 /*filter*/NULL, /*filterarg*/NULL, 216 ADV_OVERRUN_BSIZE, /*nsegments*/1, 217 BUS_SPACE_MAXSIZE_32BIT, /*flags*/0, 218 &overrun_dmat) != 0) { 219 bus_dma_tag_destroy(adv->parent_dmat); 220 adv_free(adv); 221 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 222 return ENXIO; 223 } 224 if (bus_dmamem_alloc(overrun_dmat, 225 (void **)&overrun_buf, 226 BUS_DMA_NOWAIT, 227 &overrun_dmamap) != 0) { 228 bus_dma_tag_destroy(overrun_dmat); 229 bus_dma_tag_destroy(adv->parent_dmat); 230 adv_free(adv); 231 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 232 return ENXIO; 233 } 234 /* And permanently map it in */ 235 bus_dmamap_load(overrun_dmat, overrun_dmamap, 236 overrun_buf, ADV_OVERRUN_BSIZE, 237 adv_map, &overrun_physbase, 238 /*flags*/0); 239 } 240 241 adv->overrun_physbase = overrun_physbase; 242 243 /* 244 * Stop the chip. 245 */ 246 ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT); 247 ADV_OUTW(adv, ADV_CHIP_STATUS, 0); 248 249 adv->chip_version = ADV_INB(adv, ADV_NONEISA_CHIP_REVISION); 250 adv->type = ADV_PCI; 251 252 /* 253 * Setup active negation and signal filtering. 254 */ 255 { 256 u_int8_t extra_cfg; 257 258 if (adv->chip_version >= ADV_CHIP_VER_PCI_ULTRA_3150) 259 adv->type |= ADV_ULTRA; 260 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050) 261 extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_WR_EN_FILTER; 262 else 263 extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_SLEW_RATE; 264 ADV_OUTB(adv, ADV_REG_IFC, extra_cfg); 265 } 266 267 if (adv_init(adv) != 0) { 268 adv_free(adv); 269 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 270 return ENXIO; 271 } 272 273 adv->max_dma_count = ADV_PCI_MAX_DMA_COUNT; 274 adv->max_dma_addr = ADV_PCI_MAX_DMA_ADDR; 275 276 #if CC_DISABLE_PCI_PARITY_INT 277 { 278 u_int16_t config_msw; 279 280 config_msw = ADV_INW(adv, ADV_CONFIG_MSW); 281 config_msw &= 0xFFC0; 282 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw); 283 } 284 #endif 285 286 if (id == PCI_DEVICE_ID_ADVANSYS_1200A 287 || id == PCI_DEVICE_ID_ADVANSYS_1200B) { 288 adv->bug_fix_control |= ADV_BUG_FIX_IF_NOT_DWB; 289 adv->bug_fix_control |= ADV_BUG_FIX_ASYN_USE_SYN; 290 adv->fix_asyn_xfer = ~0; 291 } 292 293 irqrid = 0; 294 irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &irqrid, 0, ~0, 1, 295 RF_SHAREABLE | RF_ACTIVE); 296 if (irqres == NULL || 297 bus_setup_intr(dev, irqres, 0, adv_intr, adv, &ih, NULL)) { 298 adv_free(adv); 299 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 300 return ENXIO; 301 } 302 303 adv_attach(adv); 304 return 0; 305 } 306 307 static device_method_t adv_pci_methods[] = { 308 /* Device interface */ 309 DEVMETHOD(device_probe, adv_pci_probe), 310 DEVMETHOD(device_attach, adv_pci_attach), 311 { 0, 0 } 312 }; 313 314 static driver_t adv_pci_driver = { 315 "adv", adv_pci_methods, sizeof(struct adv_softc) 316 }; 317 318 static devclass_t adv_pci_devclass; 319 DRIVER_MODULE(adv, pci, adv_pci_driver, adv_pci_devclass, 0, 0); 320