1 /* 2 * Generic driver for the Advanced Systems Inc. SCSI controllers 3 * Product specific probe and attach routines can be found in: 4 * 5 * i386/isa/adv_isa.c ABP5140, ABP542, ABP5150, ABP842, ABP852 6 * i386/eisa/adv_eisa.c ABP742, ABP752 7 * pci/adv_pci.c ABP920, ABP930, ABP930U, ABP930UA, ABP940, ABP940U, 8 * ABP940UA, ABP950, ABP960, ABP960U, ABP960UA, 9 * ABP970, ABP970U 10 * 11 * Copyright (c) 1996-2000 Justin Gibbs. 12 * All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions, and the following disclaimer, 19 * without modification, immediately at the beginning of the file. 20 * 2. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/advansys/advansys.c,v 1.14.2.4 2002/01/06 21:21:42 dwmalone Exp $ 36 * $DragonFly: src/sys/dev/disk/advansys/advansys.c,v 1.15 2008/05/18 20:30:20 pavalos Exp $ 37 */ 38 /* 39 * Ported from: 40 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 41 * 42 * Copyright (c) 1995-1997 Advanced System Products, Inc. 43 * All Rights Reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that redistributions of source 47 * code retain the above copyright notice and this comment without 48 * modification. 49 */ 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/thread2.h> 56 #include <sys/bus.h> 57 #include <sys/rman.h> 58 59 #include <bus/cam/cam.h> 60 #include <bus/cam/cam_ccb.h> 61 #include <bus/cam/cam_sim.h> 62 #include <bus/cam/cam_xpt_sim.h> 63 #include <bus/cam/cam_xpt_periph.h> 64 #include <bus/cam/cam_debug.h> 65 66 #include <bus/cam/scsi/scsi_all.h> 67 #include <bus/cam/scsi/scsi_message.h> 68 69 #include <vm/vm.h> 70 #include <vm/vm_param.h> 71 #include <vm/pmap.h> 72 73 #include "advansys.h" 74 75 static void adv_action(struct cam_sim *sim, union ccb *ccb); 76 static void adv_execute_ccb(void *arg, bus_dma_segment_t *dm_segs, 77 int nsegments, int error); 78 static void adv_poll(struct cam_sim *sim); 79 static void adv_run_doneq(struct adv_softc *adv); 80 static struct adv_ccb_info * 81 adv_alloc_ccb_info(struct adv_softc *adv); 82 static void adv_destroy_ccb_info(struct adv_softc *adv, 83 struct adv_ccb_info *cinfo); 84 static __inline struct adv_ccb_info * 85 adv_get_ccb_info(struct adv_softc *adv); 86 static __inline void adv_free_ccb_info(struct adv_softc *adv, 87 struct adv_ccb_info *cinfo); 88 static __inline void adv_set_state(struct adv_softc *adv, adv_state state); 89 static __inline void adv_clear_state(struct adv_softc *adv, union ccb* ccb); 90 static void adv_clear_state_really(struct adv_softc *adv, union ccb* ccb); 91 92 static __inline struct adv_ccb_info * 93 adv_get_ccb_info(struct adv_softc *adv) 94 { 95 struct adv_ccb_info *cinfo; 96 97 crit_enter(); 98 if ((cinfo = SLIST_FIRST(&adv->free_ccb_infos)) != NULL) { 99 SLIST_REMOVE_HEAD(&adv->free_ccb_infos, links); 100 } else { 101 cinfo = adv_alloc_ccb_info(adv); 102 } 103 crit_exit(); 104 105 return (cinfo); 106 } 107 108 static __inline void 109 adv_free_ccb_info(struct adv_softc *adv, struct adv_ccb_info *cinfo) 110 { 111 crit_enter(); 112 cinfo->state = ACCB_FREE; 113 SLIST_INSERT_HEAD(&adv->free_ccb_infos, cinfo, links); 114 crit_exit(); 115 } 116 117 static __inline void 118 adv_set_state(struct adv_softc *adv, adv_state state) 119 { 120 if (adv->state == 0) 121 xpt_freeze_simq(adv->sim, /*count*/1); 122 adv->state |= state; 123 } 124 125 static __inline void 126 adv_clear_state(struct adv_softc *adv, union ccb* ccb) 127 { 128 if (adv->state != 0) 129 adv_clear_state_really(adv, ccb); 130 } 131 132 static void 133 adv_clear_state_really(struct adv_softc *adv, union ccb* ccb) 134 { 135 if ((adv->state & ADV_BUSDMA_BLOCK_CLEARED) != 0) 136 adv->state &= ~(ADV_BUSDMA_BLOCK_CLEARED|ADV_BUSDMA_BLOCK); 137 if ((adv->state & ADV_RESOURCE_SHORTAGE) != 0) { 138 int openings; 139 140 openings = adv->max_openings - adv->cur_active - ADV_MIN_FREE_Q; 141 if (openings >= adv->openings_needed) { 142 adv->state &= ~ADV_RESOURCE_SHORTAGE; 143 adv->openings_needed = 0; 144 } 145 } 146 147 if ((adv->state & ADV_IN_TIMEOUT) != 0) { 148 struct adv_ccb_info *cinfo; 149 150 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr; 151 if ((cinfo->state & ACCB_RECOVERY_CCB) != 0) { 152 struct ccb_hdr *ccb_h; 153 154 /* 155 * We now traverse our list of pending CCBs 156 * and reinstate their timeouts. 157 */ 158 ccb_h = LIST_FIRST(&adv->pending_ccbs); 159 while (ccb_h != NULL) { 160 callout_reset(&ccb_h->timeout_ch, 161 (ccb_h->timeout * hz) / 1000, 162 adv_timeout, ccb_h); 163 ccb_h = LIST_NEXT(ccb_h, sim_links.le); 164 } 165 adv->state &= ~ADV_IN_TIMEOUT; 166 kprintf("%s: No longer in timeout\n", adv_name(adv)); 167 } 168 } 169 if (adv->state == 0) 170 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 171 } 172 173 void 174 adv_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 175 { 176 bus_addr_t* physaddr; 177 178 physaddr = (bus_addr_t*)arg; 179 *physaddr = segs->ds_addr; 180 } 181 182 char * 183 adv_name(struct adv_softc *adv) 184 { 185 static char name[10]; 186 187 ksnprintf(name, sizeof(name), "adv%d", adv->unit); 188 return (name); 189 } 190 191 static void 192 adv_action(struct cam_sim *sim, union ccb *ccb) 193 { 194 struct adv_softc *adv; 195 196 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("adv_action\n")); 197 198 adv = (struct adv_softc *)cam_sim_softc(sim); 199 200 switch (ccb->ccb_h.func_code) { 201 /* Common cases first */ 202 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 203 { 204 struct ccb_hdr *ccb_h; 205 struct ccb_scsiio *csio; 206 struct adv_ccb_info *cinfo; 207 208 ccb_h = &ccb->ccb_h; 209 csio = &ccb->csio; 210 cinfo = adv_get_ccb_info(adv); 211 if (cinfo == NULL) 212 panic("XXX Handle CCB info error!!!"); 213 214 ccb_h->ccb_cinfo_ptr = cinfo; 215 cinfo->ccb = ccb; 216 217 /* Only use S/G if there is a transfer */ 218 if ((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 219 if ((ccb_h->flags & CAM_SCATTER_VALID) == 0) { 220 /* 221 * We've been given a pointer 222 * to a single buffer 223 */ 224 if ((ccb_h->flags & CAM_DATA_PHYS) == 0) { 225 int error; 226 227 crit_enter(); 228 error = 229 bus_dmamap_load(adv->buffer_dmat, 230 cinfo->dmamap, 231 csio->data_ptr, 232 csio->dxfer_len, 233 adv_execute_ccb, 234 csio, /*flags*/0); 235 if (error == EINPROGRESS) { 236 /* 237 * So as to maintain ordering, 238 * freeze the controller queue 239 * until our mapping is 240 * returned. 241 */ 242 adv_set_state(adv, 243 ADV_BUSDMA_BLOCK); 244 } 245 crit_exit(); 246 } else { 247 struct bus_dma_segment seg; 248 249 /* Pointer to physical buffer */ 250 seg.ds_addr = 251 (bus_addr_t)csio->data_ptr; 252 seg.ds_len = csio->dxfer_len; 253 adv_execute_ccb(csio, &seg, 1, 0); 254 } 255 } else { 256 struct bus_dma_segment *segs; 257 if ((ccb_h->flags & CAM_DATA_PHYS) != 0) 258 panic("adv_setup_data - Physical " 259 "segment pointers unsupported"); 260 261 if ((ccb_h->flags & CAM_SG_LIST_PHYS) == 0) 262 panic("adv_setup_data - Virtual " 263 "segment addresses unsupported"); 264 265 /* Just use the segments provided */ 266 segs = (struct bus_dma_segment *)csio->data_ptr; 267 adv_execute_ccb(ccb, segs, csio->sglist_cnt, 0); 268 } 269 } else { 270 adv_execute_ccb(ccb, NULL, 0, 0); 271 } 272 break; 273 } 274 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 275 case XPT_TARGET_IO: /* Execute target I/O request */ 276 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 277 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 278 case XPT_EN_LUN: /* Enable LUN as a target */ 279 case XPT_ABORT: /* Abort the specified CCB */ 280 /* XXX Implement */ 281 ccb->ccb_h.status = CAM_REQ_INVALID; 282 xpt_done(ccb); 283 break; 284 #define IS_CURRENT_SETTINGS(c) (c->type == CTS_TYPE_CURRENT_SETTINGS) 285 #define IS_USER_SETTINGS(c) (c->type == CTS_TYPE_USER_SETTINGS) 286 case XPT_SET_TRAN_SETTINGS: 287 { 288 struct ccb_trans_settings_scsi *scsi; 289 struct ccb_trans_settings_spi *spi; 290 struct ccb_trans_settings *cts; 291 target_bit_vector targ_mask; 292 struct adv_transinfo *tconf; 293 u_int update_type; 294 295 cts = &ccb->cts; 296 targ_mask = ADV_TID_TO_TARGET_MASK(cts->ccb_h.target_id); 297 update_type = 0; 298 299 /* 300 * The user must specify which type of settings he wishes 301 * to change. 302 */ 303 if (IS_CURRENT_SETTINGS(cts) && !IS_USER_SETTINGS(cts)) { 304 tconf = &adv->tinfo[cts->ccb_h.target_id].current; 305 update_type |= ADV_TRANS_GOAL; 306 } else if (IS_USER_SETTINGS(cts) && !IS_CURRENT_SETTINGS(cts)) { 307 tconf = &adv->tinfo[cts->ccb_h.target_id].user; 308 update_type |= ADV_TRANS_USER; 309 } else { 310 ccb->ccb_h.status = CAM_REQ_INVALID; 311 break; 312 } 313 314 crit_enter(); 315 scsi = &cts->proto_specific.scsi; 316 spi = &cts->xport_specific.spi; 317 if ((update_type & ADV_TRANS_GOAL) != 0) { 318 if ((spi->valid & CTS_SPI_VALID_DISC) != 0) { 319 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0) 320 adv->disc_enable |= targ_mask; 321 else 322 adv->disc_enable &= ~targ_mask; 323 adv_write_lram_8(adv, ADVV_DISC_ENABLE_B, 324 adv->disc_enable); 325 } 326 327 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 328 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0) 329 adv->cmd_qng_enabled |= targ_mask; 330 else 331 adv->cmd_qng_enabled &= ~targ_mask; 332 } 333 } 334 335 if ((update_type & ADV_TRANS_USER) != 0) { 336 if ((spi->valid & CTS_SPI_VALID_DISC) != 0) { 337 if ((spi->flags & CTS_SPI_VALID_DISC) != 0) 338 adv->user_disc_enable |= targ_mask; 339 else 340 adv->user_disc_enable &= ~targ_mask; 341 } 342 343 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 344 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0) 345 adv->user_cmd_qng_enabled |= targ_mask; 346 else 347 adv->user_cmd_qng_enabled &= ~targ_mask; 348 } 349 } 350 351 /* 352 * If the user specifies either the sync rate, or offset, 353 * but not both, the unspecified parameter defaults to its 354 * current value in transfer negotiations. 355 */ 356 if (((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) 357 || ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0)) { 358 /* 359 * If the user provided a sync rate but no offset, 360 * use the current offset. 361 */ 362 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) == 0) 363 spi->sync_offset = tconf->offset; 364 365 /* 366 * If the user provided an offset but no sync rate, 367 * use the current sync rate. 368 */ 369 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) == 0) 370 spi->sync_period = tconf->period; 371 372 adv_period_offset_to_sdtr(adv, &spi->sync_period, 373 &spi->sync_offset, 374 cts->ccb_h.target_id); 375 376 adv_set_syncrate(adv, /*struct cam_path */NULL, 377 cts->ccb_h.target_id, spi->sync_period, 378 spi->sync_offset, update_type); 379 } 380 381 crit_exit(); 382 ccb->ccb_h.status = CAM_REQ_CMP; 383 xpt_done(ccb); 384 break; 385 } 386 case XPT_GET_TRAN_SETTINGS: 387 /* Get default/user set transfer settings for the target */ 388 { 389 struct ccb_trans_settings_scsi *scsi; 390 struct ccb_trans_settings_spi *spi; 391 struct ccb_trans_settings *cts; 392 struct adv_transinfo *tconf; 393 target_bit_vector target_mask; 394 395 cts = &ccb->cts; 396 target_mask = ADV_TID_TO_TARGET_MASK(cts->ccb_h.target_id); 397 398 scsi = &cts->proto_specific.scsi; 399 spi = &cts->xport_specific.spi; 400 401 cts->protocol = PROTO_SCSI; 402 cts->protocol_version = SCSI_REV_2; 403 cts->transport = XPORT_SPI; 404 cts->transport_version = 2; 405 406 scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB; 407 spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB; 408 409 crit_enter(); 410 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 411 tconf = &adv->tinfo[cts->ccb_h.target_id].current; 412 if ((adv->disc_enable & target_mask) != 0) 413 spi->flags |= CTS_SPI_FLAGS_DISC_ENB; 414 if ((adv->cmd_qng_enabled & target_mask) != 0) 415 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 416 } else { 417 tconf = &adv->tinfo[cts->ccb_h.target_id].user; 418 if ((adv->user_disc_enable & target_mask) != 0) 419 spi->flags |= CTS_SPI_FLAGS_DISC_ENB; 420 if ((adv->user_cmd_qng_enabled & target_mask) != 0) 421 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 422 } 423 spi->sync_period = tconf->period; 424 spi->sync_offset = tconf->offset; 425 crit_exit(); 426 spi->bus_width = MSG_EXT_WDTR_BUS_8_BIT; 427 spi->valid = CTS_SPI_VALID_SYNC_RATE 428 | CTS_SPI_VALID_SYNC_OFFSET 429 | CTS_SPI_VALID_BUS_WIDTH 430 | CTS_SPI_VALID_DISC; 431 scsi->valid = CTS_SCSI_VALID_TQ; 432 ccb->ccb_h.status = CAM_REQ_CMP; 433 xpt_done(ccb); 434 break; 435 } 436 case XPT_CALC_GEOMETRY: 437 { 438 struct ccb_calc_geometry *ccg; 439 u_int32_t size_mb; 440 u_int32_t secs_per_cylinder; 441 int extended; 442 443 ccg = &ccb->ccg; 444 size_mb = ccg->volume_size 445 / ((1024L * 1024L) / ccg->block_size); 446 extended = (adv->control & ADV_CNTL_BIOS_GT_1GB) != 0; 447 448 if (size_mb > 1024 && extended) { 449 ccg->heads = 255; 450 ccg->secs_per_track = 63; 451 } else { 452 ccg->heads = 64; 453 ccg->secs_per_track = 32; 454 } 455 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 456 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 457 ccb->ccb_h.status = CAM_REQ_CMP; 458 xpt_done(ccb); 459 break; 460 } 461 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 462 { 463 crit_enter(); 464 adv_stop_execution(adv); 465 adv_reset_bus(adv, /*initiate_reset*/TRUE); 466 adv_start_execution(adv); 467 crit_exit(); 468 469 ccb->ccb_h.status = CAM_REQ_CMP; 470 xpt_done(ccb); 471 break; 472 } 473 case XPT_TERM_IO: /* Terminate the I/O process */ 474 /* XXX Implement */ 475 ccb->ccb_h.status = CAM_REQ_INVALID; 476 xpt_done(ccb); 477 break; 478 case XPT_PATH_INQ: /* Path routing inquiry */ 479 { 480 struct ccb_pathinq *cpi = &ccb->cpi; 481 482 cpi->version_num = 1; /* XXX??? */ 483 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE; 484 cpi->target_sprt = 0; 485 cpi->hba_misc = 0; 486 cpi->hba_eng_cnt = 0; 487 cpi->max_target = 7; 488 cpi->max_lun = 7; 489 cpi->initiator_id = adv->scsi_id; 490 cpi->bus_id = cam_sim_bus(sim); 491 cpi->base_transfer_speed = 3300; 492 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 493 strncpy(cpi->hba_vid, "Advansys", HBA_IDLEN); 494 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 495 cpi->unit_number = cam_sim_unit(sim); 496 cpi->ccb_h.status = CAM_REQ_CMP; 497 cpi->transport = XPORT_SPI; 498 cpi->transport_version = 2; 499 cpi->protocol = PROTO_SCSI; 500 cpi->protocol_version = SCSI_REV_2; 501 xpt_done(ccb); 502 break; 503 } 504 default: 505 ccb->ccb_h.status = CAM_REQ_INVALID; 506 xpt_done(ccb); 507 break; 508 } 509 } 510 511 /* 512 * Currently, the output of bus_dmammap_load suits our needs just 513 * fine, but should it change, we'd need to do something here. 514 */ 515 #define adv_fixup_dmasegs(adv, dm_segs) (struct adv_sg_entry *)(dm_segs) 516 517 static void 518 adv_execute_ccb(void *arg, bus_dma_segment_t *dm_segs, 519 int nsegments, int error) 520 { 521 struct ccb_scsiio *csio; 522 struct ccb_hdr *ccb_h; 523 struct cam_sim *sim; 524 struct adv_softc *adv; 525 struct adv_ccb_info *cinfo; 526 struct adv_scsi_q scsiq; 527 struct adv_sg_head sghead; 528 529 csio = (struct ccb_scsiio *)arg; 530 ccb_h = &csio->ccb_h; 531 sim = xpt_path_sim(ccb_h->path); 532 adv = (struct adv_softc *)cam_sim_softc(sim); 533 cinfo = (struct adv_ccb_info *)csio->ccb_h.ccb_cinfo_ptr; 534 535 /* 536 * Setup our done routine to release the simq on 537 * the next ccb that completes. 538 */ 539 if ((adv->state & ADV_BUSDMA_BLOCK) != 0) 540 adv->state |= ADV_BUSDMA_BLOCK_CLEARED; 541 542 if ((ccb_h->flags & CAM_CDB_POINTER) != 0) { 543 if ((ccb_h->flags & CAM_CDB_PHYS) == 0) { 544 /* XXX Need phystovirt!!!! */ 545 /* How about pmap_kenter??? */ 546 scsiq.cdbptr = csio->cdb_io.cdb_ptr; 547 } else { 548 scsiq.cdbptr = csio->cdb_io.cdb_ptr; 549 } 550 } else { 551 scsiq.cdbptr = csio->cdb_io.cdb_bytes; 552 } 553 /* 554 * Build up the request 555 */ 556 scsiq.q1.status = 0; 557 scsiq.q1.q_no = 0; 558 scsiq.q1.cntl = 0; 559 scsiq.q1.sg_queue_cnt = 0; 560 scsiq.q1.target_id = ADV_TID_TO_TARGET_MASK(ccb_h->target_id); 561 scsiq.q1.target_lun = ccb_h->target_lun; 562 scsiq.q1.sense_len = csio->sense_len; 563 scsiq.q1.extra_bytes = 0; 564 scsiq.q2.ccb_index = cinfo - adv->ccb_infos; 565 scsiq.q2.target_ix = ADV_TIDLUN_TO_IX(ccb_h->target_id, 566 ccb_h->target_lun); 567 scsiq.q2.flag = 0; 568 scsiq.q2.cdb_len = csio->cdb_len; 569 if ((ccb_h->flags & CAM_TAG_ACTION_VALID) != 0) 570 scsiq.q2.tag_code = csio->tag_action; 571 else 572 scsiq.q2.tag_code = 0; 573 scsiq.q2.vm_id = 0; 574 575 if (nsegments != 0) { 576 bus_dmasync_op_t op; 577 578 scsiq.q1.data_addr = dm_segs->ds_addr; 579 scsiq.q1.data_cnt = dm_segs->ds_len; 580 if (nsegments > 1) { 581 scsiq.q1.cntl |= QC_SG_HEAD; 582 sghead.entry_cnt 583 = sghead.entry_to_copy 584 = nsegments; 585 sghead.res = 0; 586 sghead.sg_list = adv_fixup_dmasegs(adv, dm_segs); 587 scsiq.sg_head = &sghead; 588 } else { 589 scsiq.sg_head = NULL; 590 } 591 if ((ccb_h->flags & CAM_DIR_MASK) == CAM_DIR_IN) 592 op = BUS_DMASYNC_PREREAD; 593 else 594 op = BUS_DMASYNC_PREWRITE; 595 bus_dmamap_sync(adv->buffer_dmat, cinfo->dmamap, op); 596 } else { 597 scsiq.q1.data_addr = 0; 598 scsiq.q1.data_cnt = 0; 599 scsiq.sg_head = NULL; 600 } 601 602 603 crit_enter(); 604 /* 605 * Last time we need to check if this SCB needs to 606 * be aborted. 607 */ 608 if (ccb_h->status != CAM_REQ_INPROG) { 609 if (nsegments != 0) 610 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap); 611 adv_clear_state(adv, (union ccb *)csio); 612 adv_free_ccb_info(adv, cinfo); 613 xpt_done((union ccb *)csio); 614 crit_exit(); 615 return; 616 } 617 618 if (adv_execute_scsi_queue(adv, &scsiq, csio->dxfer_len) != 0) { 619 /* Temporary resource shortage */ 620 adv_set_state(adv, ADV_RESOURCE_SHORTAGE); 621 if (nsegments != 0) 622 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap); 623 csio->ccb_h.status = CAM_REQUEUE_REQ; 624 adv_clear_state(adv, (union ccb *)csio); 625 adv_free_ccb_info(adv, cinfo); 626 xpt_done((union ccb *)csio); 627 crit_exit(); 628 return; 629 } 630 cinfo->state |= ACCB_ACTIVE; 631 ccb_h->status |= CAM_SIM_QUEUED; 632 LIST_INSERT_HEAD(&adv->pending_ccbs, ccb_h, sim_links.le); 633 /* Schedule our timeout */ 634 callout_reset(&ccb_h->timeout_ch, (ccb_h->timeout * hz)/1000, 635 adv_timeout, csio); 636 crit_exit(); 637 } 638 639 static struct adv_ccb_info * 640 adv_alloc_ccb_info(struct adv_softc *adv) 641 { 642 int error; 643 struct adv_ccb_info *cinfo; 644 645 cinfo = &adv->ccb_infos[adv->ccb_infos_allocated]; 646 cinfo->state = ACCB_FREE; 647 error = bus_dmamap_create(adv->buffer_dmat, /*flags*/0, 648 &cinfo->dmamap); 649 if (error != 0) { 650 kprintf("%s: Unable to allocate CCB info " 651 "dmamap - error %d\n", adv_name(adv), error); 652 return (NULL); 653 } 654 adv->ccb_infos_allocated++; 655 return (cinfo); 656 } 657 658 static void 659 adv_destroy_ccb_info(struct adv_softc *adv, struct adv_ccb_info *cinfo) 660 { 661 bus_dmamap_destroy(adv->buffer_dmat, cinfo->dmamap); 662 } 663 664 void 665 adv_timeout(void *arg) 666 { 667 union ccb *ccb; 668 struct adv_softc *adv; 669 struct adv_ccb_info *cinfo; 670 671 ccb = (union ccb *)arg; 672 adv = (struct adv_softc *)xpt_path_sim(ccb->ccb_h.path)->softc; 673 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr; 674 675 xpt_print_path(ccb->ccb_h.path); 676 kprintf("Timed out\n"); 677 678 crit_enter(); 679 /* Have we been taken care of already?? */ 680 if (cinfo == NULL || cinfo->state == ACCB_FREE) { 681 crit_exit(); 682 return; 683 } 684 685 adv_stop_execution(adv); 686 687 if ((cinfo->state & ACCB_ABORT_QUEUED) == 0) { 688 struct ccb_hdr *ccb_h; 689 690 /* 691 * In order to simplify the recovery process, we ask the XPT 692 * layer to halt the queue of new transactions and we traverse 693 * the list of pending CCBs and remove their timeouts. This 694 * means that the driver attempts to clear only one error 695 * condition at a time. In general, timeouts that occur 696 * close together are related anyway, so there is no benefit 697 * in attempting to handle errors in parrallel. Timeouts will 698 * be reinstated when the recovery process ends. 699 */ 700 adv_set_state(adv, ADV_IN_TIMEOUT); 701 702 /* This CCB is the CCB representing our recovery actions */ 703 cinfo->state |= ACCB_RECOVERY_CCB|ACCB_ABORT_QUEUED; 704 705 ccb_h = LIST_FIRST(&adv->pending_ccbs); 706 while (ccb_h != NULL) { 707 callout_stop(&ccb_h->timeout_ch); 708 ccb_h = LIST_NEXT(ccb_h, sim_links.le); 709 } 710 711 /* XXX Should send a BDR */ 712 /* Attempt an abort as our first tact */ 713 xpt_print_path(ccb->ccb_h.path); 714 kprintf("Attempting abort\n"); 715 adv_abort_ccb(adv, ccb->ccb_h.target_id, 716 ccb->ccb_h.target_lun, ccb, 717 CAM_CMD_TIMEOUT, /*queued_only*/FALSE); 718 callout_reset(&ccb->ccb_h.timeout_ch, 2 * hz, adv_timeout, ccb); 719 } else { 720 /* Our attempt to perform an abort failed, go for a reset */ 721 xpt_print_path(ccb->ccb_h.path); 722 kprintf("Resetting bus\n"); 723 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 724 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 725 adv_reset_bus(adv, /*initiate_reset*/TRUE); 726 } 727 adv_start_execution(adv); 728 crit_exit(); 729 } 730 731 struct adv_softc * 732 adv_alloc(device_t dev, bus_space_tag_t tag, bus_space_handle_t bsh) 733 { 734 struct adv_softc *adv = device_get_softc(dev); 735 736 /* 737 * Allocate a storage area for us 738 */ 739 LIST_INIT(&adv->pending_ccbs); 740 SLIST_INIT(&adv->free_ccb_infos); 741 adv->dev = dev; 742 adv->unit = device_get_unit(dev); 743 adv->tag = tag; 744 adv->bsh = bsh; 745 746 return(adv); 747 } 748 749 void 750 adv_free(struct adv_softc *adv) 751 { 752 switch (adv->init_level) { 753 case 6: 754 { 755 struct adv_ccb_info *cinfo; 756 757 while ((cinfo = SLIST_FIRST(&adv->free_ccb_infos)) != NULL) { 758 SLIST_REMOVE_HEAD(&adv->free_ccb_infos, links); 759 adv_destroy_ccb_info(adv, cinfo); 760 } 761 762 bus_dmamap_unload(adv->sense_dmat, adv->sense_dmamap); 763 } 764 case 5: 765 bus_dmamem_free(adv->sense_dmat, adv->sense_buffers, 766 adv->sense_dmamap); 767 case 4: 768 bus_dma_tag_destroy(adv->sense_dmat); 769 case 3: 770 bus_dma_tag_destroy(adv->buffer_dmat); 771 case 2: 772 bus_dma_tag_destroy(adv->parent_dmat); 773 case 1: 774 if (adv->ccb_infos != NULL) 775 kfree(adv->ccb_infos, M_DEVBUF); 776 case 0: 777 break; 778 } 779 } 780 781 int 782 adv_init(struct adv_softc *adv) 783 { 784 struct adv_eeprom_config eeprom_config; 785 int checksum, i; 786 int max_sync; 787 u_int16_t config_lsw; 788 u_int16_t config_msw; 789 790 adv_lib_init(adv); 791 792 /* 793 * Stop script execution. 794 */ 795 adv_write_lram_16(adv, ADV_HALTCODE_W, 0x00FE); 796 adv_stop_execution(adv); 797 if (adv_stop_chip(adv) == 0 || adv_is_chip_halted(adv) == 0) { 798 kprintf("adv%d: Unable to halt adapter. Initialization" 799 "failed\n", adv->unit); 800 return (1); 801 } 802 ADV_OUTW(adv, ADV_REG_PROG_COUNTER, ADV_MCODE_START_ADDR); 803 if (ADV_INW(adv, ADV_REG_PROG_COUNTER) != ADV_MCODE_START_ADDR) { 804 kprintf("adv%d: Unable to set program counter. Initialization" 805 "failed\n", adv->unit); 806 return (1); 807 } 808 809 config_msw = ADV_INW(adv, ADV_CONFIG_MSW); 810 config_lsw = ADV_INW(adv, ADV_CONFIG_LSW); 811 812 if ((config_msw & ADV_CFG_MSW_CLR_MASK) != 0) { 813 config_msw &= ~ADV_CFG_MSW_CLR_MASK; 814 /* 815 * XXX The Linux code flags this as an error, 816 * but what should we report to the user??? 817 * It seems that clearing the config register 818 * makes this error recoverable. 819 */ 820 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw); 821 } 822 823 /* Suck in the configuration from the EEProm */ 824 checksum = adv_get_eeprom_config(adv, &eeprom_config); 825 826 if (ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_AUTO_CONFIG) { 827 /* 828 * XXX The Linux code sets a warning level for this 829 * condition, yet nothing of meaning is printed to 830 * the user. What does this mean??? 831 */ 832 if (adv->chip_version == 3) { 833 if (eeprom_config.cfg_lsw != config_lsw) 834 eeprom_config.cfg_lsw = config_lsw; 835 if (eeprom_config.cfg_msw != config_msw) { 836 eeprom_config.cfg_msw = config_msw; 837 } 838 } 839 } 840 if (checksum == eeprom_config.chksum) { 841 842 /* Range/Sanity checking */ 843 if (eeprom_config.max_total_qng < ADV_MIN_TOTAL_QNG) { 844 eeprom_config.max_total_qng = ADV_MIN_TOTAL_QNG; 845 } 846 if (eeprom_config.max_total_qng > ADV_MAX_TOTAL_QNG) { 847 eeprom_config.max_total_qng = ADV_MAX_TOTAL_QNG; 848 } 849 if (eeprom_config.max_tag_qng > eeprom_config.max_total_qng) { 850 eeprom_config.max_tag_qng = eeprom_config.max_total_qng; 851 } 852 if (eeprom_config.max_tag_qng < ADV_MIN_TAG_Q_PER_DVC) { 853 eeprom_config.max_tag_qng = ADV_MIN_TAG_Q_PER_DVC; 854 } 855 adv->max_openings = eeprom_config.max_total_qng; 856 adv->user_disc_enable = eeprom_config.disc_enable; 857 adv->user_cmd_qng_enabled = eeprom_config.use_cmd_qng; 858 adv->isa_dma_speed = EEPROM_DMA_SPEED(eeprom_config); 859 adv->scsi_id = EEPROM_SCSIID(eeprom_config) & ADV_MAX_TID; 860 EEPROM_SET_SCSIID(eeprom_config, adv->scsi_id); 861 adv->control = eeprom_config.cntl; 862 for (i = 0; i <= ADV_MAX_TID; i++) { 863 u_int8_t sync_data; 864 865 if ((eeprom_config.init_sdtr & (0x1 << i)) == 0) 866 sync_data = 0; 867 else 868 sync_data = eeprom_config.sdtr_data[i]; 869 adv_sdtr_to_period_offset(adv, 870 sync_data, 871 &adv->tinfo[i].user.period, 872 &adv->tinfo[i].user.offset, 873 i); 874 } 875 config_lsw = eeprom_config.cfg_lsw; 876 eeprom_config.cfg_msw = config_msw; 877 } else { 878 u_int8_t sync_data; 879 880 kprintf("adv%d: Warning EEPROM Checksum mismatch. " 881 "Using default device parameters\n", adv->unit); 882 883 /* Set reasonable defaults since we can't read the EEPROM */ 884 adv->isa_dma_speed = /*ADV_DEF_ISA_DMA_SPEED*/1; 885 adv->max_openings = ADV_DEF_MAX_TOTAL_QNG; 886 adv->disc_enable = TARGET_BIT_VECTOR_SET; 887 adv->user_disc_enable = TARGET_BIT_VECTOR_SET; 888 adv->cmd_qng_enabled = TARGET_BIT_VECTOR_SET; 889 adv->user_cmd_qng_enabled = TARGET_BIT_VECTOR_SET; 890 adv->scsi_id = 7; 891 adv->control = 0xFFFF; 892 893 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050) 894 /* Default to no Ultra to support the 3030 */ 895 adv->control &= ~ADV_CNTL_SDTR_ENABLE_ULTRA; 896 sync_data = ADV_DEF_SDTR_OFFSET | (ADV_DEF_SDTR_INDEX << 4); 897 for (i = 0; i <= ADV_MAX_TID; i++) { 898 adv_sdtr_to_period_offset(adv, sync_data, 899 &adv->tinfo[i].user.period, 900 &adv->tinfo[i].user.offset, 901 i); 902 } 903 config_lsw |= ADV_CFG_LSW_SCSI_PARITY_ON; 904 } 905 config_msw &= ~ADV_CFG_MSW_CLR_MASK; 906 config_lsw |= ADV_CFG_LSW_HOST_INT_ON; 907 if ((adv->type & (ADV_PCI|ADV_ULTRA)) == (ADV_PCI|ADV_ULTRA) 908 && (adv->control & ADV_CNTL_SDTR_ENABLE_ULTRA) == 0) 909 /* 25ns or 10MHz */ 910 max_sync = 25; 911 else 912 /* Unlimited */ 913 max_sync = 0; 914 for (i = 0; i <= ADV_MAX_TID; i++) { 915 if (adv->tinfo[i].user.period < max_sync) 916 adv->tinfo[i].user.period = max_sync; 917 } 918 919 if (adv_test_external_lram(adv) == 0) { 920 if ((adv->type & (ADV_PCI|ADV_ULTRA)) == (ADV_PCI|ADV_ULTRA)) { 921 eeprom_config.max_total_qng = 922 ADV_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 923 eeprom_config.max_tag_qng = 924 ADV_MAX_PCI_ULTRA_INRAM_TAG_QNG; 925 } else { 926 eeprom_config.cfg_msw |= 0x0800; 927 config_msw |= 0x0800; 928 eeprom_config.max_total_qng = 929 ADV_MAX_PCI_INRAM_TOTAL_QNG; 930 eeprom_config.max_tag_qng = ADV_MAX_INRAM_TAG_QNG; 931 } 932 adv->max_openings = eeprom_config.max_total_qng; 933 } 934 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw); 935 ADV_OUTW(adv, ADV_CONFIG_LSW, config_lsw); 936 #if 0 937 /* 938 * Don't write the eeprom data back for now. 939 * I'd rather not mess up the user's card. We also don't 940 * fully sanitize the eeprom settings above for the write-back 941 * to be 100% correct. 942 */ 943 if (adv_set_eeprom_config(adv, &eeprom_config) != 0) 944 kprintf("%s: WARNING! Failure writing to EEPROM.\n", 945 adv_name(adv)); 946 #endif 947 948 adv_set_chip_scsiid(adv, adv->scsi_id); 949 if (adv_init_lram_and_mcode(adv)) 950 return (1); 951 952 adv->disc_enable = adv->user_disc_enable; 953 954 adv_write_lram_8(adv, ADVV_DISC_ENABLE_B, adv->disc_enable); 955 for (i = 0; i <= ADV_MAX_TID; i++) { 956 /* 957 * Start off in async mode. 958 */ 959 adv_set_syncrate(adv, /*struct cam_path */NULL, 960 i, /*period*/0, /*offset*/0, 961 ADV_TRANS_CUR); 962 /* 963 * Enable the use of tagged commands on all targets. 964 * This allows the kernel driver to make up it's own mind 965 * as it sees fit to tag queue instead of having the 966 * firmware try and second guess the tag_code settins. 967 */ 968 adv_write_lram_8(adv, ADVV_MAX_DVC_QNG_BEG + i, 969 adv->max_openings); 970 } 971 adv_write_lram_8(adv, ADVV_USE_TAGGED_QNG_B, TARGET_BIT_VECTOR_SET); 972 adv_write_lram_8(adv, ADVV_CAN_TAGGED_QNG_B, TARGET_BIT_VECTOR_SET); 973 kprintf("adv%d: AdvanSys %s Host Adapter, SCSI ID %d, queue depth %d\n", 974 adv->unit, (adv->type & ADV_ULTRA) && (max_sync == 0) 975 ? "Ultra SCSI" : "SCSI", 976 adv->scsi_id, adv->max_openings); 977 return (0); 978 } 979 980 void 981 adv_intr(void *arg) 982 { 983 struct adv_softc *adv; 984 u_int16_t chipstat; 985 u_int16_t saved_ram_addr; 986 u_int8_t ctrl_reg; 987 u_int8_t saved_ctrl_reg; 988 u_int8_t host_flag; 989 990 adv = (struct adv_softc *)arg; 991 992 chipstat = ADV_INW(adv, ADV_CHIP_STATUS); 993 994 /* Is it for us? */ 995 if ((chipstat & (ADV_CSW_INT_PENDING|ADV_CSW_SCSI_RESET_LATCH)) == 0) 996 return; 997 998 ctrl_reg = ADV_INB(adv, ADV_CHIP_CTRL); 999 saved_ctrl_reg = ctrl_reg & (~(ADV_CC_SCSI_RESET | ADV_CC_CHIP_RESET | 1000 ADV_CC_SINGLE_STEP | ADV_CC_DIAG | 1001 ADV_CC_TEST)); 1002 1003 if ((chipstat & (ADV_CSW_SCSI_RESET_LATCH|ADV_CSW_SCSI_RESET_ACTIVE))) { 1004 kprintf("Detected Bus Reset\n"); 1005 adv_reset_bus(adv, /*initiate_reset*/FALSE); 1006 return; 1007 } 1008 1009 if ((chipstat & ADV_CSW_INT_PENDING) != 0) { 1010 1011 saved_ram_addr = ADV_INW(adv, ADV_LRAM_ADDR); 1012 host_flag = adv_read_lram_8(adv, ADVV_HOST_FLAG_B); 1013 adv_write_lram_8(adv, ADVV_HOST_FLAG_B, 1014 host_flag | ADV_HOST_FLAG_IN_ISR); 1015 1016 adv_ack_interrupt(adv); 1017 1018 if ((chipstat & ADV_CSW_HALTED) != 0 1019 && (ctrl_reg & ADV_CC_SINGLE_STEP) != 0) { 1020 adv_isr_chip_halted(adv); 1021 saved_ctrl_reg &= ~ADV_CC_HALT; 1022 } else { 1023 adv_run_doneq(adv); 1024 } 1025 ADV_OUTW(adv, ADV_LRAM_ADDR, saved_ram_addr); 1026 #ifdef DIAGNOSTIC 1027 if (ADV_INW(adv, ADV_LRAM_ADDR) != saved_ram_addr) 1028 panic("adv_intr: Unable to set LRAM addr"); 1029 #endif 1030 adv_write_lram_8(adv, ADVV_HOST_FLAG_B, host_flag); 1031 } 1032 1033 ADV_OUTB(adv, ADV_CHIP_CTRL, saved_ctrl_reg); 1034 } 1035 1036 void 1037 adv_run_doneq(struct adv_softc *adv) 1038 { 1039 struct adv_q_done_info scsiq; 1040 u_int doneq_head; 1041 u_int done_qno; 1042 1043 doneq_head = adv_read_lram_16(adv, ADVV_DONE_Q_TAIL_W) & 0xFF; 1044 done_qno = adv_read_lram_8(adv, ADV_QNO_TO_QADDR(doneq_head) 1045 + ADV_SCSIQ_B_FWD); 1046 while (done_qno != ADV_QLINK_END) { 1047 union ccb* ccb; 1048 struct adv_ccb_info *cinfo; 1049 u_int done_qaddr; 1050 u_int sg_queue_cnt; 1051 int aborted; 1052 1053 done_qaddr = ADV_QNO_TO_QADDR(done_qno); 1054 1055 /* Pull status from this request */ 1056 sg_queue_cnt = adv_copy_lram_doneq(adv, done_qaddr, &scsiq, 1057 adv->max_dma_count); 1058 1059 /* Mark it as free */ 1060 adv_write_lram_8(adv, done_qaddr + ADV_SCSIQ_B_STATUS, 1061 scsiq.q_status & ~(QS_READY|QS_ABORTED)); 1062 1063 /* Process request based on retrieved info */ 1064 if ((scsiq.cntl & QC_SG_HEAD) != 0) { 1065 u_int i; 1066 1067 /* 1068 * S/G based request. Free all of the queue 1069 * structures that contained S/G information. 1070 */ 1071 for (i = 0; i < sg_queue_cnt; i++) { 1072 done_qno = adv_read_lram_8(adv, done_qaddr 1073 + ADV_SCSIQ_B_FWD); 1074 1075 #ifdef DIAGNOSTIC 1076 if (done_qno == ADV_QLINK_END) { 1077 panic("adv_qdone: Corrupted SG " 1078 "list encountered"); 1079 } 1080 #endif 1081 done_qaddr = ADV_QNO_TO_QADDR(done_qno); 1082 1083 /* Mark SG queue as free */ 1084 adv_write_lram_8(adv, done_qaddr 1085 + ADV_SCSIQ_B_STATUS, QS_FREE); 1086 } 1087 } else 1088 sg_queue_cnt = 0; 1089 #ifdef DIAGNOSTIC 1090 if (adv->cur_active < (sg_queue_cnt + 1)) 1091 panic("adv_qdone: Attempting to free more " 1092 "queues than are active"); 1093 #endif 1094 adv->cur_active -= sg_queue_cnt + 1; 1095 1096 aborted = (scsiq.q_status & QS_ABORTED) != 0; 1097 1098 if ((scsiq.q_status != QS_DONE) 1099 && (scsiq.q_status & QS_ABORTED) == 0) 1100 panic("adv_qdone: completed scsiq with unknown status"); 1101 1102 scsiq.remain_bytes += scsiq.extra_bytes; 1103 1104 if ((scsiq.d3.done_stat == QD_WITH_ERROR) && 1105 (scsiq.d3.host_stat == QHSTA_M_DATA_OVER_RUN)) { 1106 if ((scsiq.cntl & (QC_DATA_IN|QC_DATA_OUT)) == 0) { 1107 scsiq.d3.done_stat = QD_NO_ERROR; 1108 scsiq.d3.host_stat = QHSTA_NO_ERROR; 1109 } 1110 } 1111 1112 cinfo = &adv->ccb_infos[scsiq.d2.ccb_index]; 1113 ccb = cinfo->ccb; 1114 ccb->csio.resid = scsiq.remain_bytes; 1115 adv_done(adv, ccb, 1116 scsiq.d3.done_stat, scsiq.d3.host_stat, 1117 scsiq.d3.scsi_stat, scsiq.q_no); 1118 1119 doneq_head = done_qno; 1120 done_qno = adv_read_lram_8(adv, done_qaddr + ADV_SCSIQ_B_FWD); 1121 } 1122 adv_write_lram_16(adv, ADVV_DONE_Q_TAIL_W, doneq_head); 1123 } 1124 1125 1126 void 1127 adv_done(struct adv_softc *adv, union ccb *ccb, u_int done_stat, 1128 u_int host_stat, u_int scsi_status, u_int q_no) 1129 { 1130 struct adv_ccb_info *cinfo; 1131 1132 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr; 1133 LIST_REMOVE(&ccb->ccb_h, sim_links.le); 1134 callout_stop(&ccb->ccb_h.timeout_ch); 1135 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1136 bus_dmasync_op_t op; 1137 1138 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 1139 op = BUS_DMASYNC_POSTREAD; 1140 else 1141 op = BUS_DMASYNC_POSTWRITE; 1142 bus_dmamap_sync(adv->buffer_dmat, cinfo->dmamap, op); 1143 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap); 1144 } 1145 1146 switch (done_stat) { 1147 case QD_NO_ERROR: 1148 if (host_stat == QHSTA_NO_ERROR) { 1149 ccb->ccb_h.status = CAM_REQ_CMP; 1150 break; 1151 } 1152 xpt_print_path(ccb->ccb_h.path); 1153 kprintf("adv_done - queue done without error, " 1154 "but host status non-zero(%x)\n", host_stat); 1155 /*FALLTHROUGH*/ 1156 case QD_WITH_ERROR: 1157 switch (host_stat) { 1158 case QHSTA_M_TARGET_STATUS_BUSY: 1159 case QHSTA_M_BAD_QUEUE_FULL_OR_BUSY: 1160 /* 1161 * Assume that if we were a tagged transaction 1162 * the target reported queue full. Otherwise, 1163 * report busy. The firmware really should just 1164 * pass the original status back up to us even 1165 * if it thinks the target was in error for 1166 * returning this status as no other transactions 1167 * from this initiator are in effect, but this 1168 * ignores multi-initiator setups and there is 1169 * evidence that the firmware gets its per-device 1170 * transaction counts screwed up occassionally. 1171 */ 1172 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1173 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0 1174 && host_stat != QHSTA_M_TARGET_STATUS_BUSY) 1175 scsi_status = SCSI_STATUS_QUEUE_FULL; 1176 else 1177 scsi_status = SCSI_STATUS_BUSY; 1178 adv_abort_ccb(adv, ccb->ccb_h.target_id, 1179 ccb->ccb_h.target_lun, 1180 /*ccb*/NULL, CAM_REQUEUE_REQ, 1181 /*queued_only*/TRUE); 1182 /*FALLTHROUGH*/ 1183 case QHSTA_M_NO_AUTO_REQ_SENSE: 1184 case QHSTA_NO_ERROR: 1185 ccb->csio.scsi_status = scsi_status; 1186 switch (scsi_status) { 1187 case SCSI_STATUS_CHECK_COND: 1188 case SCSI_STATUS_CMD_TERMINATED: 1189 ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 1190 /* Structure copy */ 1191 ccb->csio.sense_data = 1192 adv->sense_buffers[q_no - 1]; 1193 /* FALLTHROUGH */ 1194 case SCSI_STATUS_BUSY: 1195 case SCSI_STATUS_RESERV_CONFLICT: 1196 case SCSI_STATUS_QUEUE_FULL: 1197 case SCSI_STATUS_COND_MET: 1198 case SCSI_STATUS_INTERMED: 1199 case SCSI_STATUS_INTERMED_COND_MET: 1200 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1201 break; 1202 case SCSI_STATUS_OK: 1203 ccb->ccb_h.status |= CAM_REQ_CMP; 1204 break; 1205 } 1206 break; 1207 case QHSTA_M_SEL_TIMEOUT: 1208 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 1209 break; 1210 case QHSTA_M_DATA_OVER_RUN: 1211 ccb->ccb_h.status = CAM_DATA_RUN_ERR; 1212 break; 1213 case QHSTA_M_UNEXPECTED_BUS_FREE: 1214 ccb->ccb_h.status = CAM_UNEXP_BUSFREE; 1215 break; 1216 case QHSTA_M_BAD_BUS_PHASE_SEQ: 1217 ccb->ccb_h.status = CAM_SEQUENCE_FAIL; 1218 break; 1219 case QHSTA_M_BAD_CMPL_STATUS_IN: 1220 /* No command complete after a status message */ 1221 ccb->ccb_h.status = CAM_SEQUENCE_FAIL; 1222 break; 1223 case QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT: 1224 case QHSTA_M_WTM_TIMEOUT: 1225 case QHSTA_M_HUNG_REQ_SCSI_BUS_RESET: 1226 /* The SCSI bus hung in a phase */ 1227 ccb->ccb_h.status = CAM_SEQUENCE_FAIL; 1228 adv_reset_bus(adv, /*initiate_reset*/TRUE); 1229 break; 1230 case QHSTA_M_AUTO_REQ_SENSE_FAIL: 1231 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL; 1232 break; 1233 case QHSTA_D_QDONE_SG_LIST_CORRUPTED: 1234 case QHSTA_D_ASC_DVC_ERROR_CODE_SET: 1235 case QHSTA_D_HOST_ABORT_FAILED: 1236 case QHSTA_D_EXE_SCSI_Q_FAILED: 1237 case QHSTA_D_ASPI_NO_BUF_POOL: 1238 case QHSTA_M_BAD_TAG_CODE: 1239 case QHSTA_D_LRAM_CMP_ERROR: 1240 case QHSTA_M_MICRO_CODE_ERROR_HALT: 1241 default: 1242 panic("%s: Unhandled Host status error %x", 1243 adv_name(adv), host_stat); 1244 /* NOTREACHED */ 1245 } 1246 break; 1247 1248 case QD_ABORTED_BY_HOST: 1249 /* Don't clobber any, more explicit, error codes we've set */ 1250 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) 1251 ccb->ccb_h.status = CAM_REQ_ABORTED; 1252 break; 1253 1254 default: 1255 xpt_print_path(ccb->ccb_h.path); 1256 kprintf("adv_done - queue done with unknown status %x:%x\n", 1257 done_stat, host_stat); 1258 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 1259 break; 1260 } 1261 adv_clear_state(adv, ccb); 1262 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP 1263 && (ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) { 1264 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); 1265 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1266 } 1267 adv_free_ccb_info(adv, cinfo); 1268 /* 1269 * Null this out so that we catch driver bugs that cause a 1270 * ccb to be completed twice. 1271 */ 1272 ccb->ccb_h.ccb_cinfo_ptr = NULL; 1273 ccb->ccb_h.status &= ~CAM_SIM_QUEUED; 1274 xpt_done(ccb); 1275 } 1276 1277 /* 1278 * Function to poll for command completion when 1279 * interrupts are disabled (crash dumps) 1280 */ 1281 static void 1282 adv_poll(struct cam_sim *sim) 1283 { 1284 adv_intr(cam_sim_softc(sim)); 1285 } 1286 1287 /* 1288 * Attach all the sub-devices we can find 1289 */ 1290 int 1291 adv_attach(struct adv_softc *adv) 1292 { 1293 struct ccb_setasync csa; 1294 int max_sg; 1295 1296 /* 1297 * Allocate an array of ccb mapping structures. We put the 1298 * index of the ccb_info structure into the queue representing 1299 * a transaction and use it for mapping the queue to the 1300 * upper level SCSI transaction it represents. 1301 */ 1302 adv->ccb_infos = kmalloc(sizeof(*adv->ccb_infos) * adv->max_openings, 1303 M_DEVBUF, M_WAITOK); 1304 adv->init_level++; 1305 1306 /* 1307 * Create our DMA tags. These tags define the kinds of device 1308 * accessible memory allocations and memory mappings we will 1309 * need to perform during normal operation. 1310 * 1311 * Unless we need to further restrict the allocation, we rely 1312 * on the restrictions of the parent dmat, hence the common 1313 * use of MAXADDR and MAXSIZE. 1314 * 1315 * The ASC boards use chains of "queues" (the transactional 1316 * resources on the board) to represent long S/G lists. 1317 * The first queue represents the command and holds a 1318 * single address and data pair. The queues that follow 1319 * can each hold ADV_SG_LIST_PER_Q entries. Given the 1320 * total number of queues, we can express the largest 1321 * transaction we can map. We reserve a few queues for 1322 * error recovery. Take those into account as well. 1323 * 1324 * There is a way to take an interrupt to download the 1325 * next batch of S/G entries if there are more than 255 1326 * of them (the counter in the queue structure is a u_int8_t). 1327 * We don't use this feature, so limit the S/G list size 1328 * accordingly. 1329 */ 1330 max_sg = (adv->max_openings - ADV_MIN_FREE_Q - 1) * ADV_SG_LIST_PER_Q; 1331 if (max_sg > 255) 1332 max_sg = 255; 1333 1334 /* DMA tag for mapping buffers into device visible space. */ 1335 if (bus_dma_tag_create(adv->parent_dmat, /*alignment*/1, /*boundary*/0, 1336 /*lowaddr*/BUS_SPACE_MAXADDR, 1337 /*highaddr*/BUS_SPACE_MAXADDR, 1338 /*filter*/NULL, /*filterarg*/NULL, 1339 /*maxsize*/MAXPHYS, 1340 /*nsegments*/max_sg, 1341 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 1342 /*flags*/BUS_DMA_ALLOCNOW, 1343 &adv->buffer_dmat) != 0) { 1344 return (ENXIO); 1345 } 1346 adv->init_level++; 1347 1348 /* DMA tag for our sense buffers */ 1349 if (bus_dma_tag_create(adv->parent_dmat, /*alignment*/1, /*boundary*/0, 1350 /*lowaddr*/BUS_SPACE_MAXADDR, 1351 /*highaddr*/BUS_SPACE_MAXADDR, 1352 /*filter*/NULL, /*filterarg*/NULL, 1353 sizeof(struct scsi_sense_data)*adv->max_openings, 1354 /*nsegments*/1, 1355 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 1356 /*flags*/0, &adv->sense_dmat) != 0) { 1357 return (ENXIO); 1358 } 1359 1360 adv->init_level++; 1361 1362 /* Allocation for our sense buffers */ 1363 if (bus_dmamem_alloc(adv->sense_dmat, (void **)&adv->sense_buffers, 1364 BUS_DMA_NOWAIT, &adv->sense_dmamap) != 0) { 1365 return (ENOMEM); 1366 } 1367 1368 adv->init_level++; 1369 1370 /* And permanently map them */ 1371 bus_dmamap_load(adv->sense_dmat, adv->sense_dmamap, 1372 adv->sense_buffers, 1373 sizeof(struct scsi_sense_data)*adv->max_openings, 1374 adv_map, &adv->sense_physbase, /*flags*/0); 1375 1376 adv->init_level++; 1377 1378 /* 1379 * Fire up the chip 1380 */ 1381 if (adv_start_chip(adv) != 1) { 1382 kprintf("adv%d: Unable to start on board processor. Aborting.\n", 1383 adv->unit); 1384 return (ENXIO); 1385 } 1386 1387 /* 1388 * Construct our SIM entry. 1389 */ 1390 adv->sim = cam_sim_alloc(adv_action, adv_poll, "adv", adv, adv->unit, 1391 &sim_mplock, 1, adv->max_openings, NULL); 1392 if (adv->sim == NULL) 1393 return (ENOMEM); 1394 1395 /* 1396 * Register the bus. 1397 * 1398 * XXX Twin Channel EISA Cards??? 1399 */ 1400 if (xpt_bus_register(adv->sim, 0) != CAM_SUCCESS) { 1401 cam_sim_free(adv->sim); 1402 return (ENXIO); 1403 } 1404 1405 if (xpt_create_path(&adv->path, /*periph*/NULL, cam_sim_path(adv->sim), 1406 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) 1407 != CAM_REQ_CMP) { 1408 xpt_bus_deregister(cam_sim_path(adv->sim)); 1409 cam_sim_free(adv->sim); 1410 return (ENXIO); 1411 } 1412 1413 xpt_setup_ccb(&csa.ccb_h, adv->path, /*priority*/5); 1414 csa.ccb_h.func_code = XPT_SASYNC_CB; 1415 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 1416 csa.callback = advasync; 1417 csa.callback_arg = adv; 1418 xpt_action((union ccb *)&csa); 1419 return (0); 1420 } 1421