1 /* 2 * Device probe and attach routines for the following 3 * Advanced Systems Inc. SCSI controllers: 4 * 5 * ABP[3]940UW - Bus-Master PCI Ultra-Wide (253 CDB) 6 * ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB/Channel) 7 * ABP970UW - Bus-Master PCI Ultra-Wide (253 CDB) 8 * ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB) 9 * ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB) 10 * 11 * Copyright (c) 1998, 1999, 2000 Justin Gibbs. 12 * All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions, and the following disclaimer, 19 * without modification. 20 * 2. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/advansys/adw_pci.c,v 1.12.2.1 2000/08/02 22:22:40 peter Exp $ 36 * $DragonFly: src/sys/dev/disk/advansys/adw_pci.c,v 1.3 2003/08/07 21:16:50 dillon Exp $ 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/module.h> 43 #include <sys/bus.h> 44 45 #include <machine/bus_pio.h> 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 49 #include <sys/rman.h> 50 51 #include <bus/pci/pcireg.h> 52 #include <bus/pci/pcivar.h> 53 54 #include <bus/cam/cam.h> 55 #include <bus/cam/scsi/scsi_all.h> 56 57 #include "adwvar.h" 58 #include "adwlib.h" 59 #include "adwmcode.h" 60 61 #define ADW_PCI_IOBASE PCIR_MAPS /* I/O Address */ 62 #define ADW_PCI_MEMBASE PCIR_MAPS + 4 /* Mem I/O Address */ 63 64 #define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull 65 #define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull 66 #define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull 67 #define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 68 #define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 69 70 struct adw_pci_identity; 71 typedef int (adw_device_setup_t)(device_t, struct adw_pci_identity *, 72 struct adw_softc *adw); 73 74 struct adw_pci_identity { 75 u_int64_t full_id; 76 u_int64_t id_mask; 77 char *name; 78 adw_device_setup_t *setup; 79 const struct adw_mcode *mcode_data; 80 const struct adw_eeprom *default_eeprom; 81 }; 82 83 static adw_device_setup_t adw_asc3550_setup; 84 static adw_device_setup_t adw_asc38C0800_setup; 85 #ifdef NOTYET 86 static adw_device_setup_t adw_asc38C1600_setup; 87 #endif 88 89 struct adw_pci_identity adw_pci_ident_table[] = 90 { 91 /* asc3550 based controllers */ 92 { 93 PCI_ID_ADVANSYS_3550, 94 PCI_ID_DEV_VENDOR_MASK, 95 "AdvanSys 3550 Ultra SCSI Adapter", 96 adw_asc3550_setup, 97 &adw_asc3550_mcode_data, 98 &adw_asc3550_default_eeprom 99 }, 100 /* asc38C0800 based controllers */ 101 { 102 PCI_ID_ADVANSYS_38C0800_REV1, 103 PCI_ID_DEV_VENDOR_MASK, 104 "AdvanSys 38C0800 Ultra2 SCSI Adapter", 105 adw_asc38C0800_setup, 106 &adw_asc38C0800_mcode_data, 107 &adw_asc38C0800_default_eeprom 108 }, 109 #if NOTYET 110 /* XXX Disabled until I have hardware to test with */ 111 /* asc38C1600 based controllers */ 112 { 113 PCI_ID_ADVANSYS_38C1600_REV1, 114 PCI_ID_DEV_VENDOR_MASK, 115 "AdvanSys 38C1600 Ultra160 SCSI Adapter", 116 adw_asc38C1600_setup, 117 NULL, /* None provided by vendor thus far */ 118 NULL /* None provided by vendor thus far */ 119 } 120 #endif 121 }; 122 123 static const int adw_num_pci_devs = 124 sizeof(adw_pci_ident_table) / sizeof(*adw_pci_ident_table); 125 126 #define ADW_PCI_MAX_DMA_ADDR (0xFFFFFFFFUL) 127 #define ADW_PCI_MAX_DMA_COUNT (0xFFFFFFFFUL) 128 129 static int adw_pci_probe(device_t dev); 130 static int adw_pci_attach(device_t dev); 131 132 static device_method_t adw_pci_methods[] = { 133 /* Device interface */ 134 DEVMETHOD(device_probe, adw_pci_probe), 135 DEVMETHOD(device_attach, adw_pci_attach), 136 { 0, 0 } 137 }; 138 139 static driver_t adw_pci_driver = { 140 "adw", 141 adw_pci_methods, 142 sizeof(struct adw_softc) 143 }; 144 145 static devclass_t adw_devclass; 146 147 DRIVER_MODULE(adw, pci, adw_pci_driver, adw_devclass, 0, 0); 148 149 static __inline u_int64_t 150 adw_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 151 { 152 u_int64_t id; 153 154 id = subvendor 155 | (subdevice << 16) 156 | ((u_int64_t)vendor << 32) 157 | ((u_int64_t)device << 48); 158 159 return (id); 160 } 161 162 static struct adw_pci_identity * 163 adw_find_pci_device(device_t dev) 164 { 165 u_int64_t full_id; 166 struct adw_pci_identity *entry; 167 u_int i; 168 169 full_id = adw_compose_id(pci_get_device(dev), 170 pci_get_vendor(dev), 171 pci_get_subdevice(dev), 172 pci_get_subvendor(dev)); 173 174 for (i = 0; i < adw_num_pci_devs; i++) { 175 entry = &adw_pci_ident_table[i]; 176 if (entry->full_id == (full_id & entry->id_mask)) 177 return (entry); 178 } 179 return (NULL); 180 } 181 182 static int 183 adw_pci_probe(device_t dev) 184 { 185 struct adw_pci_identity *entry; 186 187 entry = adw_find_pci_device(dev); 188 if (entry != NULL) { 189 device_set_desc(dev, entry->name); 190 return (0); 191 } 192 return (ENXIO); 193 } 194 195 static int 196 adw_pci_attach(device_t dev) 197 { 198 struct adw_softc *adw; 199 struct adw_pci_identity *entry; 200 u_int32_t command; 201 struct resource *regs; 202 int regs_type; 203 int regs_id; 204 int error; 205 int zero; 206 207 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 208 entry = adw_find_pci_device(dev); 209 if (entry == NULL) 210 return (ENXIO); 211 regs = NULL; 212 regs_type = 0; 213 regs_id = 0; 214 #ifdef ADW_ALLOW_MEMIO 215 if ((command & PCIM_CMD_MEMEN) != 0) { 216 regs_type = SYS_RES_MEMORY; 217 regs_id = ADW_PCI_MEMBASE; 218 regs = bus_alloc_resource(dev, regs_type, 219 ®s_id, 0, ~0, 1, RF_ACTIVE); 220 } 221 #endif 222 if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) { 223 regs_type = SYS_RES_IOPORT; 224 regs_id = ADW_PCI_IOBASE; 225 regs = bus_alloc_resource(dev, regs_type, 226 ®s_id, 0, ~0, 1, RF_ACTIVE); 227 } 228 229 if (regs == NULL) { 230 device_printf(dev, "can't allocate register resources\n"); 231 return (ENOMEM); 232 } 233 234 adw = adw_alloc(dev, regs, regs_type, regs_id); 235 if (adw == NULL) 236 return(ENOMEM); 237 238 /* 239 * Now that we have access to our registers, just verify that 240 * this really is an AdvanSys device. 241 */ 242 if (adw_find_signature(adw) == 0) { 243 adw_free(adw); 244 return (ENXIO); 245 } 246 247 adw_reset_chip(adw); 248 249 error = entry->setup(dev, entry, adw); 250 251 if (error != 0) 252 return (error); 253 254 /* Ensure busmastering is enabled */ 255 command |= PCIM_CMD_BUSMASTEREN; 256 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); 257 258 /* Allocate a dmatag for our transfer DMA maps */ 259 /* XXX Should be a child of the PCI bus dma tag */ 260 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1, 261 /*boundary*/0, 262 /*lowaddr*/ADW_PCI_MAX_DMA_ADDR, 263 /*highaddr*/BUS_SPACE_MAXADDR, 264 /*filter*/NULL, /*filterarg*/NULL, 265 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT, 266 /*nsegments*/BUS_SPACE_UNRESTRICTED, 267 /*maxsegsz*/ADW_PCI_MAX_DMA_COUNT, 268 /*flags*/0, 269 &adw->parent_dmat); 270 271 adw->init_level++; 272 273 if (error != 0) { 274 printf("%s: Could not allocate DMA tag - error %d\n", 275 adw_name(adw), error); 276 adw_free(adw); 277 return (error); 278 } 279 280 adw->init_level++; 281 282 error = adw_init(adw); 283 if (error != 0) { 284 adw_free(adw); 285 return (error); 286 } 287 288 /* 289 * If the PCI Configuration Command Register "Parity Error Response 290 * Control" Bit was clear (0), then set the microcode variable 291 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 292 * to ignore DMA parity errors. 293 */ 294 if ((command & PCIM_CMD_PERRESPEN) == 0) 295 adw_lram_write_16(adw, ADW_MC_CONTROL_FLAG, 296 adw_lram_read_16(adw, ADW_MC_CONTROL_FLAG) 297 | ADW_MC_CONTROL_IGN_PERR); 298 299 zero = 0; 300 adw->irq_res_type = SYS_RES_IRQ; 301 adw->irq = bus_alloc_resource(dev, adw->irq_res_type, &zero, 302 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 303 if (adw->irq == NULL) { 304 adw_free(adw); 305 return (ENOMEM); 306 } 307 308 error = adw_attach(adw); 309 if (error != 0) 310 adw_free(adw); 311 return (error); 312 } 313 314 static int 315 adw_generic_setup(device_t dev, struct adw_pci_identity *entry, 316 struct adw_softc *adw) 317 { 318 adw->channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 319 adw->chip = ADW_CHIP_NONE; 320 adw->features = ADW_FENONE; 321 adw->flags = ADW_FNONE; 322 adw->mcode_data = entry->mcode_data; 323 adw->default_eeprom = entry->default_eeprom; 324 return (0); 325 } 326 327 static int 328 adw_asc3550_setup(device_t dev, struct adw_pci_identity *entry, 329 struct adw_softc *adw) 330 { 331 int error; 332 333 error = adw_generic_setup(dev, entry, adw); 334 if (error != 0) 335 return (error); 336 adw->chip = ADW_CHIP_ASC3550; 337 adw->features = ADW_ASC3550_FE; 338 adw->memsize = ADW_3550_MEMSIZE; 339 /* 340 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits 341 * sets a FIFO threshold of 128 bytes. This register is 342 * only accessible to the host. 343 */ 344 adw_outb(adw, ADW_DMA_CFG0, 345 ADW_DMA_CFG0_START_CTL_EM_FU|ADW_DMA_CFG0_READ_CMD_MRM); 346 adw_outb(adw, ADW_MEM_CFG, 347 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_8KB); 348 return (0); 349 } 350 351 static int 352 adw_asc38C0800_setup(device_t dev, struct adw_pci_identity *entry, 353 struct adw_softc *adw) 354 { 355 int error; 356 357 error = adw_generic_setup(dev, entry, adw); 358 if (error != 0) 359 return (error); 360 /* 361 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 362 * START_CTL_TH [3:2] bits for the default FIFO threshold. 363 * 364 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes. 365 * 366 * For DMA Errata #4 set the BC_THRESH_ENB bit. 367 */ 368 adw_outb(adw, ADW_DMA_CFG0, 369 ADW_DMA_CFG0_BC_THRESH_ENB|ADW_DMA_CFG0_FIFO_THRESH_80B 370 |ADW_DMA_CFG0_START_CTL_TH|ADW_DMA_CFG0_READ_CMD_MRM); 371 adw_outb(adw, ADW_MEM_CFG, 372 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_16KB); 373 adw->chip = ADW_CHIP_ASC38C0800; 374 adw->features = ADW_ASC38C0800_FE; 375 adw->memsize = ADW_38C0800_MEMSIZE; 376 return (error); 377 } 378 379 #ifdef NOTYET 380 static int 381 adw_asc38C1600_setup(device_t dev, struct adw_pci_identity *entry, 382 struct adw_softc *adw) 383 { 384 int error; 385 386 error = adw_generic_setup(dev, entry, adw); 387 if (error != 0) 388 return (error); 389 adw->chip = ADW_CHIP_ASC38C1600; 390 adw->features = ADW_ASC38C1600_FE; 391 adw->memsize = ADW_38C1600_MEMSIZE; 392 return (error); 393 } 394 #endif 395