1 /* 2 * Definitions for low level routines and data structures 3 * for the Advanced Systems Inc. SCSI controllers chips. 4 * 5 * Copyright (c) 1998, 1999, 2000 Justin T. Gibbs. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/dev/advansys/adwlib.h,v 1.4 2000/03/02 00:08:35 gibbs Exp $ 33 * $DragonFly: src/sys/dev/disk/advansys/adwlib.h,v 1.2 2003/06/17 04:28:21 dillon Exp $ 34 */ 35 /* 36 * Ported from: 37 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 38 * 39 * Copyright (c) 1995-1998 Advanced System Products, Inc. 40 * All Rights Reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that redistributions of source 44 * code retain the above copyright notice and this comment without 45 * modification. 46 */ 47 48 #ifndef _ADWLIB_H_ 49 #define _ADWLIB_H_ 50 51 #include "opt_adw.h" 52 53 #include <stddef.h> /* for offsetof */ 54 55 #include <dev/advansys/adwmcode.h> 56 57 #define ADW_DEF_MAX_HOST_QNG 253 58 #define ADW_DEF_MIN_HOST_QNG 16 59 #define ADW_DEF_MAX_DVC_QNG 63 60 #define ADW_DEF_MIN_DVC_QNG 4 61 62 #define ADW_MAX_TID 15 63 #define ADW_MAX_LUN 7 64 65 #define ADW_ALL_TARGETS 0xFFFF 66 67 #define ADW_TARGET_GROUP(tid) ((tid) & ~0x3) 68 #define ADW_TARGET_GROUP_SHIFT(tid) (((tid) & 0x3) * 4) 69 #define ADW_TARGET_GROUP_MASK(tid) (0xF << ADW_TARGET_GROUP_SHIFT(tid)) 70 71 /* 72 * Board Register offsets. 73 */ 74 #define ADW_INTR_STATUS_REG 0x0000 75 #define ADW_INTR_STATUS_INTRA 0x01 76 #define ADW_INTR_STATUS_INTRB 0x02 77 #define ADW_INTR_STATUS_INTRC 0x04 78 #define ADW_INTR_STATUS_INTRALL 0x07 79 80 81 #define ADW_SIGNATURE_WORD 0x0000 82 #define ADW_CHIP_ID_WORD 0x04C1 83 84 #define ADW_SIGNATURE_BYTE 0x0001 85 #define ADW_CHIP_ID_BYTE 0x25 86 87 #define ADW_INTR_ENABLES 0x0002 /*8 bit */ 88 #define ADW_INTR_ENABLE_HOST_INTR 0x01 89 #define ADW_INTR_ENABLE_SEL_INTR 0x02 90 #define ADW_INTR_ENABLE_DPR_INTR 0x04 91 #define ADW_INTR_ENABLE_RTA_INTR 0x08 92 #define ADW_INTR_ENABLE_RMA_INTR 0x10 93 #define ADW_INTR_ENABLE_RST_INTR 0x20 94 #define ADW_INTR_ENABLE_DPE_INTR 0x40 95 #define ADW_INTR_ENABLE_GLOBAL_INTR 0x80 96 97 #define ADW_CTRL_REG 0x0002 /*16 bit*/ 98 #define ADW_CTRL_REG_HOST_INTR 0x0100 99 #define ADW_CTRL_REG_SEL_INTR 0x0200 100 #define ADW_CTRL_REG_DPR_INTR 0x0400 101 #define ADW_CTRL_REG_RTA_INTR 0x0800 102 #define ADW_CTRL_REG_RMA_INTR 0x1000 103 #define ADW_CTRL_REG_RES_BIT14 0x2000 104 #define ADW_CTRL_REG_DPE_INTR 0x4000 105 #define ADW_CTRL_REG_POWER_DONE 0x8000 106 #define ADW_CTRL_REG_ANY_INTR 0xFF00 107 #define ADW_CTRL_REG_CMD_RESET 0x00C6 108 #define ADW_CTRL_REG_CMD_WR_IO_REG 0x00C5 109 #define ADW_CTRL_REG_CMD_RD_IO_REG 0x00C4 110 #define ADW_CTRL_REG_CMD_WR_PCI_CFG 0x00C3 111 #define ADW_CTRL_REG_CMD_RD_PCI_CFG 0x00C2 112 113 #define ADW_RAM_ADDR 0x0004 114 #define ADW_RAM_DATA 0x0006 115 116 #define ADW_RISC_CSR 0x000A 117 #define ADW_RISC_CSR_STOP 0x0000 118 #define ADW_RISC_TEST_COND 0x2000 119 #define ADW_RISC_CSR_RUN 0x4000 120 #define ADW_RISC_CSR_SINGLE_STEP 0x8000 121 122 #define ADW_SCSI_CFG0 0x000C 123 #define ADW_SCSI_CFG0_TIMER_MODEAB 0xC000 /* 124 * Watchdog, Second, 125 * and Selto timer CFG 126 */ 127 #define ADW_SCSI_CFG0_PARITY_EN 0x2000 128 #define ADW_SCSI_CFG0_EVEN_PARITY 0x1000 129 #define ADW_SCSI_CFG0_WD_LONG 0x0800 /* 130 * Watchdog Interval, 131 * 1: 57 min, 0: 13 sec 132 */ 133 #define ADW_SCSI_CFG0_QUEUE_128 0x0400 /* 134 * Queue Size, 135 * 1: 128 byte, 136 * 0: 64 byte 137 */ 138 #define ADW_SCSI_CFG0_PRIM_MODE 0x0100 139 #define ADW_SCSI_CFG0_SCAM_EN 0x0080 140 #define ADW_SCSI_CFG0_SEL_TMO_LONG 0x0040 /* 141 * Sel/Resel Timeout, 142 * 1: 400 ms, 143 * 0: 1.6 ms 144 */ 145 #define ADW_SCSI_CFG0_CFRM_ID 0x0020 /* SCAM id sel. */ 146 #define ADW_SCSI_CFG0_OUR_ID_EN 0x0010 147 #define ADW_SCSI_CFG0_OUR_ID 0x000F 148 149 150 #define ADW_SCSI_CFG1 0x000E 151 #define ADW_SCSI_CFG1_BIG_ENDIAN 0x8000 152 #define ADW_SCSI_CFG1_TERM_POL 0x2000 153 #define ADW_SCSI_CFG1_SLEW_RATE 0x1000 154 #define ADW_SCSI_CFG1_FILTER_MASK 0x0C00 155 #define ADW_SCSI_CFG1_FLTR_DISABLE 0x0000 156 #define ADW_SCSI_CFG1_FLTR_11_TO_20NS 0x0800 157 #define ADW_SCSI_CFG1_FLTR_21_TO_39NS 0x0C00 158 #define ADW_SCSI_CFG1_DIS_ACTIVE_NEG 0x0200 159 #define ADW_SCSI_CFG1_DIFF_MODE 0x0100 160 #define ADW_SCSI_CFG1_DIFF_SENSE 0x0080 161 #define ADW_SCSI_CFG1_TERM_CTL_MANUAL 0x0040 /* Global Term Switch */ 162 #define ADW_SCSI_CFG1_TERM_CTL_MASK 0x0030 163 #define ADW_SCSI_CFG1_TERM_CTL_H 0x0020 /* Enable SCSI-H */ 164 #define ADW_SCSI_CFG1_TERM_CTL_L 0x0010 /* Enable SCSI-L */ 165 #define ADW_SCSI_CFG1_CABLE_DETECT 0x000F 166 #define ADW_SCSI_CFG1_EXT16_MASK 0x0008 /* Ext16 cable pres */ 167 #define ADW_SCSI_CFG1_EXT8_MASK 0x0004 /* Ext8 cable pres */ 168 #define ADW_SCSI_CFG1_INT8_MASK 0x0002 /* Int8 cable pres */ 169 #define ADW_SCSI_CFG1_INT16_MASK 0x0001 /* Int16 cable pres */ 170 #define ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_A_MASK \ 171 (ADW_SCSI_CFG1_EXT16_MASK|ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_INT16_MASK) 172 #define ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_B_MASK \ 173 (ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_INT16_MASK) 174 175 /* 176 * Addendum for ASC-38C0800 Chip 177 */ 178 #define ADW2_SCSI_CFG1_DIS_TERM_DRV 0x4000 /* 179 * The Terminators 180 * must be disabled 181 * in order to detect 182 * cable presence 183 */ 184 185 #define ADW2_SCSI_CFG1_DEV_DETECT 0x1C00 186 #define ADW2_SCSI_CFG1_DEV_DETECT_HVD 0x1000 187 #define ADW2_SCSI_CFG1_DEV_DETECT_LVD 0x0800 188 #define ADW2_SCSI_CFG1_DEV_DETECT_SE 0x0400 189 190 #define ADW2_SCSI_CFG1_TERM_CTL_LVD 0x00C0 /* Ultra2 Only */ 191 #define ADW2_SCSI_CFG1_TERM_LVD_HI 0x0080 192 #define ADW2_SCSI_CFG1_TERM_LVD_LO 0x0040 193 #define ADW2_SCSI_CFG1_EXTLVD_MASK 0x0008 /* ExtLVD cable pres */ 194 #define ADW2_SCSI_CFG1_INTLVD_MASK 0x0004 /* IntLVD cable pres */ 195 196 #define ADW_MEM_CFG 0x0010 197 #define ADW_MEM_CFG_BIOS_EN 0x40 198 #define ADW_MEM_CFG_FAST_EE_CLK 0x20 /* Diagnostic Bit */ 199 #define ADW_MEM_CFG_RAM_SZ_MASK 0x1C /* RISC RAM Size */ 200 #define ADW_MEM_CFG_RAM_SZ_2KB 0x00 201 #define ADW_MEM_CFG_RAM_SZ_4KB 0x04 202 #define ADW_MEM_CFG_RAM_SZ_8KB 0x08 203 #define ADW_MEM_CFG_RAM_SZ_16KB 0x0C 204 #define ADW_MEM_CFG_RAM_SZ_32KB 0x10 205 #define ADW_MEM_CFG_RAM_SZ_64KB 0x14 206 207 #define ADW_GPIO_CNTL 0x0011 208 #define ADW_GPIO_DATA 0x0012 209 210 #define ADW_COMMA 0x0014 211 #define ADW_COMMB 0x0018 212 213 #define ADW_EEP_CMD 0x001A 214 #define ADW_EEP_CMD_READ 0x0080 /* or in address */ 215 #define ADW_EEP_CMD_WRITE 0x0040 /* or in address */ 216 #define ADW_EEP_CMD_WRITE_ABLE 0x0030 217 #define ADW_EEP_CMD_WRITE_DISABLE 0x0000 218 #define ADW_EEP_CMD_DONE 0x0200 219 #define ADW_EEP_CMD_DONE_ERR 0x0001 220 #define ADW_EEP_DELAY_MS 100 221 222 #define ADW_EEP_DATA 0x001C 223 224 #define ADW_DMA_CFG0 0x0020 225 #define ADW_DMA_CFG0_BC_THRESH_ENB 0x80 226 #define ADW_DMA_CFG0_FIFO_THRESH 0x70 227 #define ADW_DMA_CFG0_FIFO_THRESH_16B 0x00 228 #define ADW_DMA_CFG0_FIFO_THRESH_32B 0x20 229 #define ADW_DMA_CFG0_FIFO_THRESH_48B 0x30 230 #define ADW_DMA_CFG0_FIFO_THRESH_64B 0x40 231 #define ADW_DMA_CFG0_FIFO_THRESH_80B 0x50 232 #define ADW_DMA_CFG0_FIFO_THRESH_96B 0x60 233 #define ADW_DMA_CFG0_FIFO_THRESH_112B 0x70 234 #define ADW_DMA_CFG0_START_CTL_MASK 0x0C 235 #define ADW_DMA_CFG0_START_CTL_TH 0x00 /* Start on thresh */ 236 #define ADW_DMA_CFG0_START_CTL_IDLE 0x04 /* Start when idle */ 237 #define ADW_DMA_CFG0_START_CTL_TH_IDLE 0x08 /* Either */ 238 #define ADW_DMA_CFG0_START_CTL_EM_FU 0x0C /* Start on full/empty */ 239 #define ADW_DMA_CFG0_READ_CMD_MASK 0x03 240 #define ADW_DMA_CFG0_READ_CMD_MR 0x00 241 #define ADW_DMA_CFG0_READ_CMD_MRL 0x02 242 #define ADW_DMA_CFG0_READ_CMD_MRM 0x03 243 244 #define ADW_TICKLE 0x0022 245 #define ADW_TICKLE_NOP 0x00 246 #define ADW_TICKLE_A 0x01 247 #define ADW_TICKLE_B 0x02 248 #define ADW_TICKLE_C 0x03 249 250 /* Program Counter */ 251 #define ADW_PC 0x2A 252 253 #define ADW_SCSI_CTRL 0x0034 254 #define ADW_SCSI_CTRL_RSTOUT 0x2000 255 256 /* 257 * ASC-38C0800 RAM BIST Register bit definitions 258 */ 259 #define ADW_RAM_BIST 0x0038 260 #define ADW_RAM_BIST_RAM_TEST_MODE 0x80 261 #define ADW_RAM_BIST_PRE_TEST_MODE 0x40 262 #define ADW_RAM_BIST_NORMAL_MODE 0x00 263 #define ADW_RAM_BIST_RAM_TEST_DONE 0x10 264 #define ADW_RAM_BIST_RAM_TEST_STATUS 0x0F 265 #define ADW_RAM_BIST_RAM_TEST_HOST_ERR 0x08 266 #define ADW_RAM_BIST_RAM_TEST_RAM_ERR 0x04 267 #define ADW_RAM_BIST_RAM_TEST_RISC_ERR 0x02 268 #define ADW_RAM_BIST_RAM_TEST_SCSI_ERR 0x01 269 #define ADW_RAM_BIST_RAM_TEST_SUCCESS 0x00 270 #define ADW_RAM_BIST_PRE_TEST_VALUE 0x05 271 #define ADW_RAM_BIST_NORMAL_VALUE 0x00 272 #define ADW_PLL_TEST 0x0039 273 274 #define ADW_SCSI_RESET_HOLD_TIME_US 60 275 276 /* LRAM Constants */ 277 #define ADW_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */ 278 #define ADW_3550_IOLEN 0x40 /* I/O Port Range in bytes */ 279 280 #define ADW_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 281 #define ADW_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */ 282 283 #define ADW_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 284 #define ADW_38C1600_IOLEN 0x100 /* I/O Port Range in bytes */ 285 #define ADW_38C1600_MEMLEN 0x1000 /* Memory Range 4KB */ 286 287 #define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ 288 #define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ 289 290 #define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull 291 #define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull 292 #define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull 293 #define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 294 #define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 295 296 /* ====================== SCSI Request Structures =========================== */ 297 298 #define ADW_NO_OF_SG_PER_BLOCK 15 299 300 /* 301 * Although the adapter can deal with S/G lists of indefinite size, 302 * we limit the list to 30 to conserve space as the kernel can only send 303 * us buffers of at most 64KB currently. 304 */ 305 #define ADW_SG_BLOCKCNT 2 306 #define ADW_SGSIZE (ADW_NO_OF_SG_PER_BLOCK * ADW_SG_BLOCKCNT) 307 308 struct adw_sg_elm { 309 u_int32_t sg_addr; 310 u_int32_t sg_count; 311 }; 312 313 /* sg block structure used by the microcode */ 314 struct adw_sg_block { 315 u_int8_t reserved1; 316 u_int8_t reserved2; 317 u_int8_t reserved3; 318 u_int8_t sg_cnt; /* Valid entries in this block */ 319 u_int32_t sg_busaddr_next; /* link to the next sg block */ 320 struct adw_sg_elm sg_list[ADW_NO_OF_SG_PER_BLOCK]; 321 }; 322 323 /* Structure representing a single allocation block of adw sg blocks */ 324 struct sg_map_node { 325 bus_dmamap_t sg_dmamap; 326 bus_addr_t sg_physaddr; 327 struct adw_sg_block* sg_vaddr; 328 SLIST_ENTRY(sg_map_node) links; 329 }; 330 331 typedef enum { 332 QHSTA_NO_ERROR = 0x00, 333 QHSTA_M_SEL_TIMEOUT = 0x11, 334 QHSTA_M_DATA_OVER_RUN = 0x12, 335 QHSTA_M_UNEXPECTED_BUS_FREE = 0x13, 336 QHSTA_M_QUEUE_ABORTED = 0x15, 337 QHSTA_M_SXFR_SDMA_ERR = 0x16, /* SCSI DMA Error */ 338 QHSTA_M_SXFR_SXFR_PERR = 0x17, /* SCSI Bus Parity Error */ 339 QHSTA_M_RDMA_PERR = 0x18, /* RISC PCI DMA parity error */ 340 QHSTA_M_SXFR_OFF_UFLW = 0x19, /* Offset Underflow */ 341 QHSTA_M_SXFR_OFF_OFLW = 0x20, /* Offset Overflow */ 342 QHSTA_M_SXFR_WD_TMO = 0x21, /* Watchdog Timeout */ 343 QHSTA_M_SXFR_DESELECTED = 0x22, /* Deselected */ 344 QHSTA_M_SXFR_XFR_PH_ERR = 0x24, /* Transfer Phase Error */ 345 QHSTA_M_SXFR_UNKNOWN_ERROR = 0x25, /* SXFR_STATUS Unknown Error */ 346 QHSTA_M_SCSI_BUS_RESET = 0x30, /* Request aborted from SBR */ 347 QHSTA_M_SCSI_BUS_RESET_UNSOL= 0x31, /* Request aborted from unsol. SBR*/ 348 QHSTA_M_BUS_DEVICE_RESET = 0x32, /* Request aborted from BDR */ 349 QHSTA_M_DIRECTION_ERR = 0x35, /* Data Phase mismatch */ 350 QHSTA_M_DIRECTION_ERR_HUNG = 0x36, /* Data Phase mismatch - bus hang */ 351 QHSTA_M_WTM_TIMEOUT = 0x41, 352 QHSTA_M_BAD_CMPL_STATUS_IN = 0x42, 353 QHSTA_M_NO_AUTO_REQ_SENSE = 0x43, 354 QHSTA_M_AUTO_REQ_SENSE_FAIL = 0x44, 355 QHSTA_M_INVALID_DEVICE = 0x45, /* Bad target ID */ 356 QHSTA_M_FROZEN_TIDQ = 0x46, /* TID Queue frozen. */ 357 QHSTA_M_SGBACKUP_ERROR = 0x47 /* Scatter-Gather backup error */ 358 } host_status_t; 359 360 typedef enum { 361 QD_NO_STATUS = 0x00, /* Request not completed yet. */ 362 QD_NO_ERROR = 0x01, 363 QD_ABORTED_BY_HOST = 0x02, 364 QD_WITH_ERROR = 0x04 365 } done_status_t; 366 367 /* 368 * Microcode request structure 369 * 370 * All fields in this structure are used by the microcode so their 371 * size and ordering cannot be changed. 372 */ 373 struct adw_scsi_req_q { 374 u_int8_t cntl; /* Ucode flags and state. */ 375 u_int8_t target_cmd; 376 u_int8_t target_id; /* Device target identifier. */ 377 u_int8_t target_lun; /* Device target logical unit number. */ 378 u_int32_t data_addr; /* Data buffer physical address. */ 379 u_int32_t data_cnt; /* Data count. Ucode sets to residual. */ 380 u_int32_t sense_baddr; /* Sense buffer bus address. */ 381 u_int32_t carrier_baddr; /* Carrier bus address. */ 382 u_int8_t mflag; /* microcode flag field. */ 383 u_int8_t sense_len; /* Auto-sense length. Residual on complete. */ 384 u_int8_t cdb_len; /* SCSI CDB length. */ 385 u_int8_t scsi_cntl; /* SCSI command control flags (tags, nego) */ 386 #define ADW_QSC_NO_DISC 0x01 387 #define ADW_QSC_NO_TAGMSG 0x02 388 #define ADW_QSC_NO_SYNC 0x04 389 #define ADW_QSC_NO_WIDE 0x08 390 #define ADW_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR */ 391 #define ADW_QSC_SIMPLE_Q_TAG 0x00 392 #define ADW_QSC_HEAD_OF_Q_TAG 0x40 393 #define ADW_QSC_ORDERED_Q_TAG 0x80 394 u_int8_t done_status; /* Completion status. */ 395 u_int8_t scsi_status; /* SCSI status byte. */ 396 u_int8_t host_status; /* Ucode host status. */ 397 u_int8_t sg_wk_ix; /* Microcode working SG index. */ 398 u_int8_t cdb[12]; /* SCSI command block. */ 399 u_int32_t sg_real_addr; /* SG list physical address. */ 400 u_int32_t scsi_req_baddr; /* Bus address of this structure. */ 401 u_int32_t sg_wk_data_cnt; /* Saved data count at disconnection. */ 402 /* 403 * The 'tokens' placed in these two fields are 404 * used to identify the scsi request and the next 405 * carrier in the response queue, *not* physical 406 * addresses. This driver uses byte offsets for 407 * portability and speed of mapping back to either 408 * a virtual or physical address. 409 */ 410 u_int32_t scsi_req_bo; /* byte offset of this structure */ 411 u_int32_t carrier_bo; /* byte offst of our carrier. */ 412 }; 413 414 typedef enum { 415 ACB_FREE = 0x00, 416 ACB_ACTIVE = 0x01, 417 ACB_RELEASE_SIMQ = 0x02, 418 ACB_RECOVERY_ACB = 0x04 419 } acb_state; 420 421 struct acb { 422 struct adw_scsi_req_q queue; 423 bus_dmamap_t dmamap; 424 acb_state state; 425 union ccb *ccb; 426 struct adw_sg_block* sg_blocks; 427 bus_addr_t sg_busaddr; 428 struct scsi_sense_data sense_data; 429 SLIST_ENTRY(acb) links; 430 }; 431 432 /* 433 * EEPROM configuration format 434 * 435 * Field naming convention: 436 * 437 * *_enable indicates the field enables or disables the feature. The 438 * value is never reset. 439 * 440 * *_able indicates both whether a feature should be enabled or disabled 441 * and whether a device is capable of the feature. At initialization 442 * this field may be set, but later if a device is found to be incapable 443 * of the feature, the field is cleared. 444 * 445 * Default values are maintained in a_init.c in the structure 446 * Default_EEPROM_Config. 447 */ 448 struct adw_eeprom 449 { 450 u_int16_t cfg_lsw; /* 00 power up initialization */ 451 #define ADW_EEPROM_BIG_ENDIAN 0x8000 452 #define ADW_EEPROM_BIOS_ENABLE 0x4000 453 #define ADW_EEPROM_TERM_POL 0x2000 454 #define ADW_EEPROM_CIS_LD 0x1000 455 456 /* bit 13 set - Term Polarity Control */ 457 /* bit 14 set - BIOS Enable */ 458 /* bit 15 set - Big Endian Mode */ 459 u_int16_t cfg_msw; /* unused */ 460 u_int16_t disc_enable; 461 u_int16_t wdtr_able; 462 union { 463 /* 464 * sync enable bits for UW cards, 465 * actual sync rate for TID 0-3 466 * on U2W and U160 cards. 467 */ 468 u_int16_t sync_enable; 469 u_int16_t sdtr1; 470 } sync1; 471 u_int16_t start_motor; 472 u_int16_t tagqng_able; 473 u_int16_t bios_scan; 474 u_int16_t scam_tolerant; 475 476 u_int8_t adapter_scsi_id; 477 u_int8_t bios_boot_delay; 478 479 u_int8_t scsi_reset_delay; 480 u_int8_t bios_id_lun; /* high nibble is lun */ 481 /* low nibble is scsi id */ 482 483 u_int8_t termination_se; /* 0 - automatic */ 484 #define ADW_EEPROM_TERM_AUTO 0 485 #define ADW_EEPROM_TERM_OFF 1 486 #define ADW_EEPROM_TERM_HIGH_ON 2 487 #define ADW_EEPROM_TERM_BOTH_ON 3 488 489 u_int8_t termination_lvd; 490 u_int16_t bios_ctrl; 491 #define ADW_BIOS_INIT_DIS 0x0001 /* Don't act as initiator */ 492 #define ADW_BIOS_EXT_TRANS 0x0002 /* > 1 GB support */ 493 #define ADW_BIOS_MORE_2DISK 0x0004 /* > 1 GB support */ 494 #define ADW_BIOS_NO_REMOVABLE 0x0008 /* don't support removable media */ 495 #define ADW_BIOS_CD_BOOT 0x0010 /* support bootable CD */ 496 #define ADW_BIOS_SCAN_EN 0x0020 /* BIOS SCAN enabled */ 497 #define ADW_BIOS_MULTI_LUN 0x0040 /* probe luns */ 498 #define ADW_BIOS_MESSAGE 0x0080 /* display BIOS message */ 499 #define ADW_BIOS_RESET_BUS 0x0200 /* reset SCSI bus durint init */ 500 #define ADW_BIOS_QUIET 0x0800 /* No verbose initialization */ 501 #define ADW_BIOS_SCSI_PAR_EN 0x1000 /* SCSI parity enabled */ 502 503 union { 504 /* 13 505 * ultra enable bits for UW cards, 506 * actual sync rate for TID 4-7 507 * on U2W and U160 cards. 508 */ 509 u_int16_t ultra_enable; 510 u_int16_t sdtr2; 511 } sync2; 512 union { 513 /* 14 514 * reserved for UW cards, 515 * actual sync rate for TID 8-11 516 * on U2W and U160 cards. 517 */ 518 u_int16_t reserved; 519 u_int16_t sdtr3; 520 } sync3; 521 u_int8_t max_host_qng; /* 15 maximum host queuing */ 522 u_int8_t max_dvc_qng; /* maximum per device queuing */ 523 u_int16_t dvc_cntl; /* 16 control bit for driver */ 524 union { 525 /* 17 526 * reserved for UW cards, 527 * actual sync rate for TID 12-15 528 * on U2W and U160 cards. 529 */ 530 u_int16_t reserved; 531 u_int16_t sdtr4; 532 } sync4; 533 u_int16_t serial_number[3]; /* 18-20 */ 534 u_int16_t checksum; /* 21 */ 535 u_int8_t oem_name[16]; /* 22 - 29 */ 536 u_int16_t dvc_err_code; /* 30 */ 537 u_int16_t adv_err_code; /* 31 */ 538 u_int16_t adv_err_addr; /* 32 */ 539 u_int16_t saved_dvc_err_code; /* 33 */ 540 u_int16_t saved_adv_err_code; /* 34 */ 541 u_int16_t saved_adv_err_addr; /* 35 */ 542 u_int16_t reserved[20]; /* 36 - 55 */ 543 u_int16_t cisptr_lsw; /* 56 CIS data */ 544 u_int16_t cisptr_msw; /* 57 CIS data */ 545 u_int32_t subid; /* 58-59 SubSystem Vendor/Dev ID */ 546 u_int16_t reserved2[4]; 547 }; 548 549 /* EEProm Addresses */ 550 #define ADW_EEP_DVC_CFG_BEGIN 0x00 551 #define ADW_EEP_DVC_CFG_END (offsetof(struct adw_eeprom, checksum)/2) 552 #define ADW_EEP_DVC_CTL_BEGIN (offsetof(struct adw_eeprom, oem_name)/2) 553 #define ADW_EEP_MAX_WORD_ADDR (sizeof(struct adw_eeprom)/2) 554 555 #define ADW_BUS_RESET_HOLD_DELAY_US 100 556 557 typedef enum { 558 ADW_CHIP_NONE, 559 ADW_CHIP_ASC3550, /* Ultra-Wide IC */ 560 ADW_CHIP_ASC38C0800, /* Ultra2-Wide/LVD IC */ 561 ADW_CHIP_ASC38C1600 /* Ultra3-Wide/LVD2 IC */ 562 } adw_chip; 563 564 typedef enum { 565 ADW_FENONE = 0x0000, 566 ADW_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 567 ADW_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 568 ADW_DT = 0x0004, /* Supports Double Transistion REQ/ACK*/ 569 ADW_WIDE = 0x0008, /* Wide Channel */ 570 ADW_ASC3550_FE = ADW_ULTRA, 571 ADW_ASC38C0800_FE = ADW_ULTRA2, 572 ADW_ASC38C1600_FE = ADW_ULTRA2|ADW_DT 573 } adw_feature; 574 575 typedef enum { 576 ADW_FNONE = 0x0000, 577 ADW_EEPROM_FAILED = 0x0001 578 } adw_flag; 579 580 typedef enum { 581 ADW_STATE_NORMAL = 0x00, 582 ADW_RESOURCE_SHORTAGE = 0x01 583 } adw_state; 584 585 typedef enum { 586 ADW_MC_SDTR_ASYNC, 587 ADW_MC_SDTR_5, 588 ADW_MC_SDTR_10, 589 ADW_MC_SDTR_20, 590 ADW_MC_SDTR_40, 591 ADW_MC_SDTR_80 592 } adw_mc_sdtr; 593 594 struct adw_syncrate 595 { 596 adw_mc_sdtr mc_sdtr; 597 u_int8_t period; 598 char *rate; 599 }; 600 601 /* We have an input and output queue for our carrier structures */ 602 #define ADW_OUTPUT_QUEUE 0 /* Offset into carriers member */ 603 #define ADW_INPUT_QUEUE 1 /* Offset into carriers member */ 604 #define ADW_NUM_CARRIER_QUEUES 2 605 struct adw_softc 606 { 607 bus_space_tag_t tag; 608 bus_space_handle_t bsh; 609 adw_state state; 610 bus_dma_tag_t buffer_dmat; 611 struct acb *acbs; 612 struct adw_carrier *carriers; 613 struct adw_carrier *free_carriers; 614 struct adw_carrier *commandq; 615 struct adw_carrier *responseq; 616 LIST_HEAD(, ccb_hdr) pending_ccbs; 617 SLIST_HEAD(, acb) free_acb_list; 618 bus_dma_tag_t parent_dmat; 619 bus_dma_tag_t carrier_dmat; /* dmat for our acb carriers*/ 620 bus_dmamap_t carrier_dmamap; 621 bus_dma_tag_t acb_dmat; /* dmat for our ccb array */ 622 bus_dmamap_t acb_dmamap; 623 bus_dma_tag_t sg_dmat; /* dmat for our sg maps */ 624 SLIST_HEAD(, sg_map_node) sg_maps; 625 bus_addr_t acb_busbase; 626 bus_addr_t carrier_busbase; 627 adw_chip chip; 628 adw_feature features; 629 adw_flag flags; 630 u_int memsize; 631 char channel; 632 struct cam_path *path; 633 struct cam_sim *sim; 634 struct resource *regs; 635 struct resource *irq; 636 void *ih; 637 const struct adw_mcode *mcode_data; 638 const struct adw_eeprom *default_eeprom; 639 device_t device; 640 int regs_res_type; 641 int regs_res_id; 642 int irq_res_type; 643 u_int max_acbs; 644 u_int num_acbs; 645 u_int initiator_id; 646 u_int init_level; 647 u_int unit; 648 char* name; 649 cam_status last_reset; /* Last reset type */ 650 u_int16_t bios_ctrl; 651 u_int16_t user_wdtr; 652 u_int16_t user_sdtr[4]; /* A nibble per-device */ 653 u_int16_t user_tagenb; 654 u_int16_t tagenb; 655 u_int16_t user_discenb; 656 u_int16_t serial_number[3]; 657 }; 658 659 extern const struct adw_eeprom adw_asc3550_default_eeprom; 660 extern const struct adw_eeprom adw_asc38C0800_default_eeprom; 661 extern const struct adw_syncrate adw_syncrates[]; 662 extern const int adw_num_syncrates; 663 664 #define adw_inb(adw, port) \ 665 bus_space_read_1((adw)->tag, (adw)->bsh, port) 666 #define adw_inw(adw, port) \ 667 bus_space_read_2((adw)->tag, (adw)->bsh, port) 668 #define adw_inl(adw, port) \ 669 bus_space_read_4((adw)->tag, (adw)->bsh, port) 670 671 #define adw_outb(adw, port, value) \ 672 bus_space_write_1((adw)->tag, (adw)->bsh, port, value) 673 #define adw_outw(adw, port, value) \ 674 bus_space_write_2((adw)->tag, (adw)->bsh, port, value) 675 #define adw_outl(adw, port, value) \ 676 bus_space_write_4((adw)->tag, (adw)->bsh, port, value) 677 678 #define adw_set_multi_2(adw, port, value, count) \ 679 bus_space_set_multi_2((adw)->tag, (adw)->bsh, port, value, count) 680 681 static __inline const char* adw_name(struct adw_softc *adw); 682 static __inline u_int adw_lram_read_8(struct adw_softc *adw, u_int addr); 683 static __inline u_int adw_lram_read_16(struct adw_softc *adw, u_int addr); 684 static __inline u_int adw_lram_read_32(struct adw_softc *adw, u_int addr); 685 static __inline void adw_lram_write_8(struct adw_softc *adw, u_int addr, 686 u_int value); 687 static __inline void adw_lram_write_16(struct adw_softc *adw, u_int addr, 688 u_int value); 689 static __inline void adw_lram_write_32(struct adw_softc *adw, u_int addr, 690 u_int value); 691 692 static __inline u_int32_t acbvtobo(struct adw_softc *adw, 693 struct acb *acb); 694 static __inline u_int32_t acbvtob(struct adw_softc *adw, 695 struct acb *acb); 696 static __inline struct acb * acbbotov(struct adw_softc *adw, 697 u_int32_t busaddr); 698 static __inline struct acb * acbbtov(struct adw_softc *adw, 699 u_int32_t busaddr); 700 static __inline u_int32_t carriervtobo(struct adw_softc *adw, 701 struct adw_carrier *carrier); 702 static __inline u_int32_t carriervtob(struct adw_softc *adw, 703 struct adw_carrier *carrier); 704 static __inline struct adw_carrier * 705 carrierbotov(struct adw_softc *adw, 706 u_int32_t byte_offset); 707 static __inline struct adw_carrier * 708 carrierbtov(struct adw_softc *adw, 709 u_int32_t baddr); 710 711 static __inline const char* 712 adw_name(struct adw_softc *adw) 713 { 714 return (adw->name); 715 } 716 717 static __inline u_int 718 adw_lram_read_8(struct adw_softc *adw, u_int addr) 719 { 720 adw_outw(adw, ADW_RAM_ADDR, addr); 721 return (adw_inb(adw, ADW_RAM_DATA)); 722 } 723 724 static __inline u_int 725 adw_lram_read_16(struct adw_softc *adw, u_int addr) 726 { 727 adw_outw(adw, ADW_RAM_ADDR, addr); 728 return (adw_inw(adw, ADW_RAM_DATA)); 729 } 730 731 static __inline u_int 732 adw_lram_read_32(struct adw_softc *adw, u_int addr) 733 { 734 u_int retval; 735 736 adw_outw(adw, ADW_RAM_ADDR, addr); 737 retval = adw_inw(adw, ADW_RAM_DATA); 738 retval |= (adw_inw(adw, ADW_RAM_DATA) << 16); 739 return (retval); 740 } 741 742 static __inline void 743 adw_lram_write_8(struct adw_softc *adw, u_int addr, u_int value) 744 { 745 adw_outw(adw, ADW_RAM_ADDR, addr); 746 adw_outb(adw, ADW_RAM_DATA, value); 747 } 748 749 static __inline void 750 adw_lram_write_16(struct adw_softc *adw, u_int addr, u_int value) 751 { 752 adw_outw(adw, ADW_RAM_ADDR, addr); 753 adw_outw(adw, ADW_RAM_DATA, value); 754 } 755 756 static __inline void 757 adw_lram_write_32(struct adw_softc *adw, u_int addr, u_int value) 758 { 759 adw_outw(adw, ADW_RAM_ADDR, addr); 760 adw_outw(adw, ADW_RAM_DATA, value); 761 adw_outw(adw, ADW_RAM_DATA, value >> 16); 762 } 763 764 static __inline u_int32_t 765 acbvtobo(struct adw_softc *adw, struct acb *acb) 766 { 767 return ((u_int32_t)((caddr_t)acb - (caddr_t)adw->acbs)); 768 } 769 770 static __inline u_int32_t 771 acbvtob(struct adw_softc *adw, struct acb *acb) 772 { 773 return (adw->acb_busbase + acbvtobo(adw, acb)); 774 } 775 776 static __inline struct acb * 777 acbbotov(struct adw_softc *adw, u_int32_t byteoffset) 778 { 779 return ((struct acb *)((caddr_t)adw->acbs + byteoffset)); 780 } 781 782 static __inline struct acb * 783 acbbtov(struct adw_softc *adw, u_int32_t busaddr) 784 { 785 return (acbbotov(adw, busaddr - adw->acb_busbase)); 786 } 787 788 /* 789 * Return the byte offset for a carrier relative to our array of carriers. 790 */ 791 static __inline u_int32_t 792 carriervtobo(struct adw_softc *adw, struct adw_carrier *carrier) 793 { 794 return ((u_int32_t)((caddr_t)carrier - (caddr_t)adw->carriers)); 795 } 796 797 static __inline u_int32_t 798 carriervtob(struct adw_softc *adw, struct adw_carrier *carrier) 799 { 800 return (adw->carrier_busbase + carriervtobo(adw, carrier)); 801 } 802 803 static __inline struct adw_carrier * 804 carrierbotov(struct adw_softc *adw, u_int32_t byte_offset) 805 { 806 return ((struct adw_carrier *)((caddr_t)adw->carriers + byte_offset)); 807 } 808 809 static __inline struct adw_carrier * 810 carrierbtov(struct adw_softc *adw, u_int32_t baddr) 811 { 812 return (carrierbotov(adw, baddr - adw->carrier_busbase)); 813 } 814 815 /* Intialization */ 816 int adw_find_signature(struct adw_softc *adw); 817 void adw_reset_chip(struct adw_softc *adw); 818 int adw_reset_bus(struct adw_softc *adw); 819 u_int16_t adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *buf); 820 void adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *buf); 821 int adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1); 822 void adw_set_user_sdtr(struct adw_softc *adw, 823 u_int tid, u_int mc_sdtr); 824 u_int adw_get_user_sdtr(struct adw_softc *adw, u_int tid); 825 void adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr); 826 u_int adw_get_chip_sdtr(struct adw_softc *adw, u_int tid); 827 u_int adw_find_sdtr(struct adw_softc *adw, u_int period); 828 u_int adw_find_period(struct adw_softc *adw, u_int mc_sdtr); 829 u_int adw_hshk_cfg_period_factor(u_int tinfo); 830 831 /* Idle Commands */ 832 adw_idle_cmd_status_t adw_idle_cmd_send(struct adw_softc *adw, u_int cmd, 833 u_int parameter); 834 835 /* SCSI Transaction Processing */ 836 static __inline void adw_send_acb(struct adw_softc *adw, struct acb *acb, 837 u_int32_t acb_baddr); 838 839 static __inline void adw_tickle_risc(struct adw_softc *adw, u_int value) 840 { 841 /* 842 * Tickle the RISC to tell it to read its Command Queue Head pointer. 843 */ 844 adw_outb(adw, ADW_TICKLE, value); 845 if (adw->chip == ADW_CHIP_ASC3550) { 846 /* 847 * Clear the tickle value. In the ASC-3550 the RISC flag 848 * command 'clr_tickle_a' does not work unless the host 849 * value is cleared. 850 */ 851 adw_outb(adw, ADW_TICKLE, ADW_TICKLE_NOP); 852 } 853 } 854 855 static __inline void 856 adw_send_acb(struct adw_softc *adw, struct acb *acb, u_int32_t acb_baddr) 857 { 858 struct adw_carrier *new_cq; 859 860 new_cq = adw->free_carriers; 861 adw->free_carriers = carrierbotov(adw, new_cq->next_ba); 862 new_cq->next_ba = ADW_CQ_STOPPER; 863 864 acb->queue.carrier_baddr = adw->commandq->carr_ba; 865 acb->queue.carrier_bo = adw->commandq->carr_offset; 866 adw->commandq->areq_ba = acbvtob(adw, acb); 867 adw->commandq->next_ba = new_cq->carr_ba; 868 #if 0 869 printf("EnQ 0x%x 0x%x 0x%x 0x%x\n", 870 adw->commandq->carr_offset, 871 adw->commandq->carr_ba, 872 adw->commandq->areq_ba, 873 adw->commandq->next_ba); 874 #endif 875 adw->commandq = new_cq; 876 877 878 adw_tickle_risc(adw, ADW_TICKLE_A); 879 } 880 881 #endif /* _ADWLIB_H_ */ 882