1 /* 2 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $ 17 */ 18 19 #if defined(__DragonFly__) 20 #include "ahci_dragonfly.h" 21 #else 22 #error "build for OS unknown" 23 #endif 24 #include "pmreg.h" 25 #include "atascsi.h" 26 27 /* change to AHCI_DEBUG for dmesg spam */ 28 #define NO_AHCI_DEBUG 29 30 #ifdef AHCI_DEBUG 31 #define DPRINTF(m, f...) do { if ((ahcidebug & (m)) == (m)) kprintf(f); } \ 32 while (0) 33 #define AHCI_D_TIMEOUT 0x00 34 #define AHCI_D_VERBOSE 0x01 35 #define AHCI_D_INTR 0x02 36 #define AHCI_D_XFER 0x08 37 int ahcidebug = AHCI_D_VERBOSE; 38 #else 39 #define DPRINTF(m, f...) 40 #endif 41 42 #define AHCI_PCI_ATI_SB600_MAGIC 0x40 43 #define AHCI_PCI_ATI_SB600_LOCKED 0x01 44 45 #define AHCI_REG_CAP 0x000 /* HBA Capabilities */ 46 #define AHCI_REG_CAP_NP(_r) (((_r) & 0x1f)+1) /* Number of Ports */ 47 #define AHCI_REG_CAP_SXS (1<<5) /* External SATA */ 48 #define AHCI_REG_CAP_EMS (1<<6) /* Enclosure Mgmt */ 49 #define AHCI_REG_CAP_CCCS (1<<7) /* Cmd Coalescing */ 50 #define AHCI_REG_CAP_NCS(_r) ((((_r) & 0x1f00)>>8)+1) /* NCmds*/ 51 #define AHCI_REG_CAP_PSC (1<<13) /* Partial State Capable */ 52 #define AHCI_REG_CAP_SSC (1<<14) /* Slumber State Capable */ 53 #define AHCI_REG_CAP_PMD (1<<15) /* PIO Multiple DRQ Block */ 54 #define AHCI_REG_CAP_FBSS (1<<16) /* FIS-Based Switching */ 55 #define AHCI_REG_CAP_SPM (1<<17) /* Port Multiplier */ 56 #define AHCI_REG_CAP_SAM (1<<18) /* AHCI Only mode */ 57 #define AHCI_REG_CAP_SNZO (1<<19) /* Non Zero DMA Offsets */ 58 #define AHCI_REG_CAP_ISS (0xf<<20) /* Interface Speed Support */ 59 #define AHCI_REG_CAP_ISS_G1 (0x1<<20) /* Gen 1 (1.5 Gbps) */ 60 #define AHCI_REG_CAP_ISS_G1_2 (0x2<<20) /* Gen 1 and 2 (3 Gbps) */ 61 #define AHCI_REG_CAP_SCLO (1<<24) /* Cmd List Override */ 62 #define AHCI_REG_CAP_SAL (1<<25) /* Activity LED */ 63 #define AHCI_REG_CAP_SALP (1<<26) /* Aggressive Link Pwr Mgmt */ 64 #define AHCI_REG_CAP_SSS (1<<27) /* Staggered Spinup */ 65 #define AHCI_REG_CAP_SMPS (1<<28) /* Mech Presence Switch */ 66 #define AHCI_REG_CAP_SSNTF (1<<29) /* SNotification Register */ 67 #define AHCI_REG_CAP_SNCQ (1<<30) /* Native Cmd Queuing */ 68 #define AHCI_REG_CAP_S64A (1<<31) /* 64bit Addressing */ 69 #define AHCI_FMT_CAP "\020" "\040S64A" "\037NCQ" "\036SSNTF" \ 70 "\035SMPS" "\034SSS" "\033SALP" "\032SAL" \ 71 "\031SCLO" "\024SNZO" "\023SAM" "\022SPM" \ 72 "\021FBSS" "\020PMD" "\017SSC" "\016PSC" \ 73 "\010CCCS" "\007EMS" "\006SXS" 74 75 #define AHCI_REG_GHC 0x004 /* Global HBA Control */ 76 #define AHCI_REG_GHC_HR (1<<0) /* HBA Reset */ 77 #define AHCI_REG_GHC_IE (1<<1) /* Interrupt Enable */ 78 #define AHCI_REG_GHC_MRSM (1<<2) /* MSI Revert to Single Msg */ 79 #define AHCI_REG_GHC_AE (1<<31) /* AHCI Enable */ 80 #define AHCI_FMT_GHC "\020" "\040AE" "\003MRSM" "\002IE" "\001HR" 81 82 #define AHCI_REG_IS 0x008 /* Interrupt Status */ 83 #define AHCI_REG_PI 0x00c /* Ports Implemented */ 84 85 #define AHCI_REG_VS 0x010 /* AHCI Version */ 86 #define AHCI_REG_VS_0_95 0x00000905 /* 0.95 */ 87 #define AHCI_REG_VS_1_0 0x00010000 /* 1.0 */ 88 #define AHCI_REG_VS_1_1 0x00010100 /* 1.1 */ 89 #define AHCI_REG_VS_1_2 0x00010200 /* 1.2 */ 90 #define AHCI_REG_VS_1_3 0x00010300 /* 1.3 */ 91 #define AHCI_REG_VS_1_4 0x00010400 /* 1.4 */ 92 #define AHCI_REG_VS_1_5 0x00010500 /* 1.5 (future...) */ 93 94 #define AHCI_REG_CCC_CTL 0x014 /* Coalescing Control */ 95 #define AHCI_REG_CCC_CTL_INT(_r) (((_r) & 0xf8) >> 3) /* CCC INT slot */ 96 97 #define AHCI_REG_CCC_PORTS 0x018 /* Coalescing Ports */ 98 #define AHCI_REG_EM_LOC 0x01c /* Enclosure Mgmt Location */ 99 #define AHCI_REG_EM_CTL 0x020 /* Enclosure Mgmt Control */ 100 101 #define AHCI_PORT_REGION(_p) (0x100 + ((_p) * 0x80)) 102 #define AHCI_PORT_SIZE 0x80 103 104 #define AHCI_PREG_CLB 0x00 /* Cmd List Base Addr */ 105 #define AHCI_PREG_CLBU 0x04 /* Cmd List Base Hi Addr */ 106 #define AHCI_PREG_FB 0x08 /* FIS Base Addr */ 107 #define AHCI_PREG_FBU 0x0c /* FIS Base Hi Addr */ 108 109 #define AHCI_PREG_IS 0x10 /* Interrupt Status */ 110 #define AHCI_PREG_IS_DHRS (1<<0) /* Device to Host FIS */ 111 #define AHCI_PREG_IS_PSS (1<<1) /* PIO Setup FIS */ 112 #define AHCI_PREG_IS_DSS (1<<2) /* DMA Setup FIS */ 113 #define AHCI_PREG_IS_SDBS (1<<3) /* Set Device Bits FIS */ 114 #define AHCI_PREG_IS_UFS (1<<4) /* Unknown FIS */ 115 #define AHCI_PREG_IS_DPS (1<<5) /* Descriptor Processed */ 116 #define AHCI_PREG_IS_PCS (1<<6) /* Port Change */ 117 #define AHCI_PREG_IS_DMPS (1<<7) /* Device Mechanical Presence */ 118 #define AHCI_PREG_IS_PRCS (1<<22) /* PhyRdy Change */ 119 #define AHCI_PREG_IS_IPMS (1<<23) /* Incorrect Port Multiplier */ 120 #define AHCI_PREG_IS_OFS (1<<24) /* Overflow */ 121 #define AHCI_PREG_IS_INFS (1<<26) /* Interface Non-fatal Error */ 122 #define AHCI_PREG_IS_IFS (1<<27) /* Interface Fatal Error */ 123 #define AHCI_PREG_IS_HBDS (1<<28) /* Host Bus Data Error */ 124 #define AHCI_PREG_IS_HBFS (1<<29) /* Host Bus Fatal Error */ 125 #define AHCI_PREG_IS_TFES (1<<30) /* Task File Error */ 126 #define AHCI_PREG_IS_CPDS (1<<31) /* Cold Presence Detect */ 127 #define AHCI_PFMT_IS "\20" "\040CPDS" "\037TFES" "\036HBFS" \ 128 "\035HBDS" "\034IFS" "\033INFS" "\031OFS" \ 129 "\030IPMS" "\027PRCS" "\010DMPS" "\006DPS" \ 130 "\007PCS" "\005UFS" "\004SDBS" "\003DSS" \ 131 "\002PSS" "\001DHRS" 132 133 #define AHCI_PREG_IE 0x14 /* Interrupt Enable */ 134 #define AHCI_PREG_IE_DHRE (1<<0) /* Device to Host FIS */ 135 #define AHCI_PREG_IE_PSE (1<<1) /* PIO Setup FIS */ 136 #define AHCI_PREG_IE_DSE (1<<2) /* DMA Setup FIS */ 137 #define AHCI_PREG_IE_SDBE (1<<3) /* Set Device Bits FIS */ 138 #define AHCI_PREG_IE_UFE (1<<4) /* Unknown FIS */ 139 #define AHCI_PREG_IE_DPE (1<<5) /* Descriptor Processed */ 140 #define AHCI_PREG_IE_PCE (1<<6) /* Port Change */ 141 #define AHCI_PREG_IE_DMPE (1<<7) /* Device Mechanical Presence */ 142 #define AHCI_PREG_IE_PRCE (1<<22) /* PhyRdy Change */ 143 #define AHCI_PREG_IE_IPME (1<<23) /* Incorrect Port Multiplier */ 144 #define AHCI_PREG_IE_OFE (1<<24) /* Overflow */ 145 #define AHCI_PREG_IE_INFE (1<<26) /* Interface Non-fatal Error */ 146 #define AHCI_PREG_IE_IFE (1<<27) /* Interface Fatal Error */ 147 #define AHCI_PREG_IE_HBDE (1<<28) /* Host Bus Data Error */ 148 #define AHCI_PREG_IE_HBFE (1<<29) /* Host Bus Fatal Error */ 149 #define AHCI_PREG_IE_TFEE (1<<30) /* Task File Error */ 150 #define AHCI_PREG_IE_CPDE (1<<31) /* Cold Presence Detect */ 151 #define AHCI_PFMT_IE "\20" "\040CPDE" "\037TFEE" "\036HBFE" \ 152 "\035HBDE" "\034IFE" "\033INFE" "\031OFE" \ 153 "\030IPME" "\027PRCE" "\010DMPE" "\007PCE" \ 154 "\006DPE" "\005UFE" "\004SDBE" "\003DSE" \ 155 "\002PSE" "\001DHRE" 156 157 #define AHCI_PREG_CMD 0x18 /* Command and Status */ 158 #define AHCI_PREG_CMD_ST (1<<0) /* Start */ 159 #define AHCI_PREG_CMD_SUD (1<<1) /* Spin Up Device */ 160 #define AHCI_PREG_CMD_POD (1<<2) /* Power On Device */ 161 #define AHCI_PREG_CMD_CLO (1<<3) /* Command List Override */ 162 #define AHCI_PREG_CMD_FRE (1<<4) /* FIS Receive Enable */ 163 #define AHCI_PREG_CMD_CCS(_r) (((_r) >> 8) & 0x1f) /* Curr CmdSlot# */ 164 #define AHCI_PREG_CMD_MPSS (1<<13) /* Mech Presence State */ 165 #define AHCI_PREG_CMD_FR (1<<14) /* FIS Receive Running */ 166 #define AHCI_PREG_CMD_CR (1<<15) /* Command List Running */ 167 #define AHCI_PREG_CMD_CPS (1<<16) /* Cold Presence State */ 168 #define AHCI_PREG_CMD_PMA (1<<17) /* Port Multiplier Attached */ 169 #define AHCI_PREG_CMD_HPCP (1<<18) /* Hot Plug Capable */ 170 #define AHCI_PREG_CMD_MPSP (1<<19) /* Mech Presence Switch */ 171 #define AHCI_PREG_CMD_CPD (1<<20) /* Cold Presence Detection */ 172 #define AHCI_PREG_CMD_ESP (1<<21) /* External SATA Port */ 173 #define AHCI_PREG_CMD_ATAPI (1<<24) /* Device is ATAPI */ 174 #define AHCI_PREG_CMD_DLAE (1<<25) /* Drv LED on ATAPI Enable */ 175 #define AHCI_PREG_CMD_ALPE (1<<26) /* Aggro Pwr Mgmt Enable */ 176 #define AHCI_PREG_CMD_ASP (1<<27) /* Aggro Slumber/Partial */ 177 #define AHCI_PREG_CMD_ICC 0xf0000000 /* Interface Comm Ctrl */ 178 #define AHCI_PREG_CMD_ICC_SLUMBER 0x60000000 179 #define AHCI_PREG_CMD_ICC_PARTIAL 0x20000000 180 #define AHCI_PREG_CMD_ICC_ACTIVE 0x10000000 181 #define AHCI_PREG_CMD_ICC_IDLE 0x00000000 182 #define AHCI_PFMT_CMD "\020" "\034ASP" "\033ALPE" "\032DLAE" \ 183 "\031ATAPI" "\026ESP" "\025CPD" "\024MPSP" \ 184 "\023HPCP" "\022PMA" "\021CPS" "\020CR" \ 185 "\017FR" "\016MPSS" "\005FRE" "\004CLO" \ 186 "\003POD" "\002SUD" "\001ST" 187 188 #define AHCI_PREG_TFD 0x20 /* Task File Data*/ 189 #define AHCI_PREG_TFD_STS 0xff 190 #define AHCI_PREG_TFD_STS_ERR (1<<0) 191 #define AHCI_PREG_TFD_STS_DRQ (1<<3) 192 #define AHCI_PREG_TFD_STS_BSY (1<<7) 193 #define AHCI_PREG_TFD_ERR 0xff00 194 195 #define AHCI_PFMT_TFD_STS "\20" "\010BSY" "\004DRQ" "\001ERR" 196 #define AHCI_PREG_SIG 0x24 /* Signature */ 197 198 #define AHCI_PREG_SSTS 0x28 /* SATA Status */ 199 #define AHCI_PREG_SSTS_DET 0xf /* Device Detection */ 200 #define AHCI_PREG_SSTS_DET_NONE 0x0 201 #define AHCI_PREG_SSTS_DET_DEV_NE 0x1 202 #define AHCI_PREG_SSTS_DET_DEV 0x3 203 #define AHCI_PREG_SSTS_DET_PHYOFFLINE 0x4 204 #define AHCI_PREG_SSTS_SPD 0xf0 /* Current Interface Speed */ 205 #define AHCI_PREG_SSTS_SPD_NONE 0x00 206 #define AHCI_PREG_SSTS_SPD_GEN1 0x10 207 #define AHCI_PREG_SSTS_SPD_GEN2 0x20 208 #define AHCI_PREG_SSTS_IPM 0xf00 /* Interface Power Management */ 209 #define AHCI_PREG_SSTS_IPM_NONE 0x000 210 #define AHCI_PREG_SSTS_IPM_ACTIVE 0x100 211 #define AHCI_PREG_SSTS_IPM_PARTIAL 0x200 212 #define AHCI_PREG_SSTS_IPM_SLUMBER 0x600 213 214 #define AHCI_PREG_SCTL 0x2c /* SATA Control */ 215 #define AHCI_PREG_SCTL_DET 0xf /* Device Detection */ 216 #define AHCI_PREG_SCTL_DET_NONE 0x0 217 #define AHCI_PREG_SCTL_DET_INIT 0x1 218 #define AHCI_PREG_SCTL_DET_DISABLE 0x4 219 #define AHCI_PREG_SCTL_SPD 0xf0 /* Speed Allowed */ 220 #define AHCI_PREG_SCTL_SPD_ANY 0x00 221 #define AHCI_PREG_SCTL_SPD_GEN1 0x10 222 #define AHCI_PREG_SCTL_SPD_GEN2 0x20 223 #define AHCI_PREG_SCTL_IPM 0xf00 /* Interface Power Management */ 224 #define AHCI_PREG_SCTL_IPM_NONE 0x000 225 #define AHCI_PREG_SCTL_IPM_NOPARTIAL 0x100 226 #define AHCI_PREG_SCTL_IPM_NOSLUMBER 0x200 227 #define AHCI_PREG_SCTL_IPM_DISABLED 0x300 228 #define AHCI_PREG_SCTL_SPM 0xf000 /* Select Power Management */ 229 #define AHCI_PREG_SCTL_SPM_NONE 0x0000 230 #define AHCI_PREG_SCTL_SPM_NOPARTIAL 0x1000 231 #define AHCI_PREG_SCTL_SPM_NOSLUMBER 0x2000 232 #define AHCI_PREG_SCTL_SPM_DISABLED 0x3000 233 #define AHCI_PREG_SCTL_PMP 0xf0000 /* Set PM port for xmit FISes */ 234 #define AHCI_PREG_SCTL_PMP_SHIFT 16 235 236 #define AHCI_PREG_SERR 0x30 /* SATA Error */ 237 #define AHCI_PREG_SERR_ERR_I (1<<0) /* Recovered Data Integrity */ 238 #define AHCI_PREG_SERR_ERR_M (1<<1) /* Recovered Communications */ 239 #define AHCI_PREG_SERR_ERR_T (1<<8) /* Transient Data Integrity */ 240 #define AHCI_PREG_SERR_ERR_C (1<<9) /* Persistent Comm/Data */ 241 #define AHCI_PREG_SERR_ERR_P (1<<10) /* Protocol */ 242 #define AHCI_PREG_SERR_ERR_E (1<<11) /* Internal */ 243 #define AHCI_PREG_SERR_DIAG_N (1<<16) /* PhyRdy Change */ 244 #define AHCI_PREG_SERR_DIAG_I (1<<17) /* Phy Internal Error */ 245 #define AHCI_PREG_SERR_DIAG_W (1<<18) /* Comm Wake */ 246 #define AHCI_PREG_SERR_DIAG_B (1<<19) /* 10B to 8B Decode Error */ 247 #define AHCI_PREG_SERR_DIAG_D (1<<20) /* Disparity Error */ 248 #define AHCI_PREG_SERR_DIAG_C (1<<21) /* CRC Error */ 249 #define AHCI_PREG_SERR_DIAG_H (1<<22) /* Handshake Error */ 250 #define AHCI_PREG_SERR_DIAG_S (1<<23) /* Link Sequence Error */ 251 #define AHCI_PREG_SERR_DIAG_T (1<<24) /* Transport State Trans Err */ 252 #define AHCI_PREG_SERR_DIAG_F (1<<25) /* Unknown FIS Type */ 253 #define AHCI_PREG_SERR_DIAG_X (1<<26) /* Exchanged */ 254 255 #define AHCI_PFMT_SERR "\020" \ 256 "\033DIAG.X" "\032DIAG.F" "\031DIAG.T" "\030DIAG.S" \ 257 "\027DIAG.H" "\026DIAG.C" "\025DIAG.D" "\024DIAG.B" \ 258 "\023DIAG.W" "\022DIAG.I" "\021DIAG.N" \ 259 "\014ERR.E" "\013ERR.P" "\012ERR.C" "\011ERR.T" \ 260 "\002ERR.M" "\001ERR.I" 261 262 #define AHCI_PREG_SACT 0x34 /* SATA Active */ 263 #define AHCI_PREG_CI 0x38 /* Command Issue */ 264 #define AHCI_PREG_CI_ALL_SLOTS 0xffffffff 265 #define AHCI_PREG_SNTF 0x3c /* SNotification */ 266 267 /* 268 * AHCI mapped structures 269 */ 270 struct ahci_cmd_hdr { 271 u_int16_t flags; 272 #define AHCI_CMD_LIST_FLAG_CFL 0x001f /* Command FIS Length */ 273 #define AHCI_CMD_LIST_FLAG_A (1<<5) /* ATAPI */ 274 #define AHCI_CMD_LIST_FLAG_W (1<<6) /* Write */ 275 #define AHCI_CMD_LIST_FLAG_P (1<<7) /* Prefetchable */ 276 #define AHCI_CMD_LIST_FLAG_R (1<<8) /* Reset */ 277 #define AHCI_CMD_LIST_FLAG_B (1<<9) /* BIST */ 278 #define AHCI_CMD_LIST_FLAG_C (1<<10) /* Clear Busy upon R_OK */ 279 #define AHCI_CMD_LIST_FLAG_PMP 0xf000 /* Port Multiplier Port */ 280 #define AHCI_CMD_LIST_FLAG_PMP_SHIFT 12 281 u_int16_t prdtl; /* sgl len */ 282 283 u_int32_t prdbc; /* transferred byte count */ 284 285 u_int32_t ctba_lo; 286 u_int32_t ctba_hi; 287 288 u_int32_t reserved[4]; 289 } __packed; 290 291 struct ahci_rfis { 292 u_int8_t dsfis[28]; 293 u_int8_t reserved1[4]; 294 u_int8_t psfis[24]; 295 u_int8_t reserved2[8]; 296 u_int8_t rfis[24]; 297 u_int8_t reserved3[4]; 298 u_int8_t sdbfis[4]; 299 u_int8_t ufis[64]; 300 u_int8_t reserved4[96]; 301 } __packed; 302 303 struct ahci_prdt { 304 u_int32_t dba_lo; 305 u_int32_t dba_hi; 306 u_int32_t reserved; 307 u_int32_t flags; 308 #define AHCI_PRDT_FLAG_INTR (1<<31) /* interrupt on completion */ 309 } __packed; 310 311 /* 312 * The base command table structure is 128 bytes. Each prdt is 16 bytes. 313 * We need to accomodate MAXPHYS (128K) which is at least 32 entries, 314 * plus one for page slop. 315 * 316 * Making the ahci_cmd_table 1024 bytes (a reasonable power of 2) 317 * thus requires MAX_PRDT to be set to 56. 318 */ 319 #define AHCI_MAX_PRDT 56 320 #define AHCI_MAX_PMPORTS 16 321 322 #if MAXPHYS / PAGE_SIZE + 1 > AHCI_MAX_PRDT 323 #error "AHCI_MAX_PRDT is not big enough" 324 #endif 325 326 struct ahci_cmd_table { 327 u_int8_t cfis[64]; /* Command FIS */ 328 u_int8_t acmd[16]; /* ATAPI Command */ 329 u_int8_t reserved[48]; 330 331 struct ahci_prdt prdt[AHCI_MAX_PRDT]; 332 } __packed; 333 334 #define AHCI_MAX_PORTS 32 335 336 struct ahci_dmamem { 337 bus_dma_tag_t adm_tag; 338 bus_dmamap_t adm_map; 339 bus_dma_segment_t adm_seg; 340 bus_addr_t adm_busaddr; 341 caddr_t adm_kva; 342 }; 343 #define AHCI_DMA_MAP(_adm) ((_adm)->adm_map) 344 #define AHCI_DMA_DVA(_adm) ((_adm)->adm_busaddr) 345 #define AHCI_DMA_KVA(_adm) ((void *)(_adm)->adm_kva) 346 347 struct ahci_softc; 348 struct ahci_port; 349 struct ahci_device; 350 351 struct ahci_ccb { 352 /* ATA xfer associated with this CCB. Must be 1st struct member. */ 353 struct ata_xfer ccb_xa; 354 struct callout ccb_timeout; 355 356 int ccb_slot; 357 struct ahci_port *ccb_port; 358 359 bus_dmamap_t ccb_dmamap; 360 struct ahci_cmd_hdr *ccb_cmd_hdr; 361 struct ahci_cmd_table *ccb_cmd_table; 362 363 void (*ccb_done)(struct ahci_ccb *); 364 365 TAILQ_ENTRY(ahci_ccb) ccb_entry; 366 }; 367 368 struct ahci_port { 369 struct ahci_softc *ap_sc; 370 bus_space_handle_t ap_ioh; 371 372 int ap_num; 373 int ap_pmcount; 374 int ap_flags; 375 #define AP_F_BUS_REGISTERED 0x0001 376 #define AP_F_CAM_ATTACHED 0x0002 377 #define AP_F_IN_RESET 0x0004 378 #define AP_F_SCAN_RUNNING 0x0008 379 #define AP_F_SCAN_REQUESTED 0x0010 380 #define AP_F_SCAN_COMPLETED 0x0020 381 #define AP_F_IGNORE_IFS 0x0040 382 #define AP_F_IFS_IGNORED 0x0080 383 #define AP_F_UNUSED_0100 0x0100 384 #define AP_F_EXCLUSIVE_ACCESS 0x0200 385 #define AP_F_ERR_CCB_RESERVED 0x0400 386 #define AP_F_HARSH_REINIT 0x0800 387 int ap_signal; /* os per-port thread sig */ 388 thread_t ap_thread; /* os per-port thread */ 389 struct lock ap_lock; /* os per-port lock */ 390 struct lock ap_sim_lock; /* cam sim lock */ 391 struct lock ap_sig_lock; /* signal thread */ 392 #define AP_SIGF_INIT 0x0001 393 #define AP_SIGF_TIMEOUT 0x0002 394 #define AP_SIGF_PORTINT 0x0004 395 #define AP_SIGF_THREAD_SYNC 0x0008 396 #define AP_SIGF_STOP 0x8000 397 struct cam_sim *ap_sim; 398 399 struct ahci_rfis *ap_rfis; 400 struct ahci_dmamem *ap_dmamem_rfis; 401 402 struct ahci_dmamem *ap_dmamem_cmd_list; 403 struct ahci_dmamem *ap_dmamem_cmd_table; 404 405 u_int32_t ap_active; /* active CI command bmask */ 406 u_int32_t ap_active_cnt; /* active CI command count */ 407 u_int32_t ap_sactive; /* active SACT command bmask */ 408 u_int32_t ap_expired; /* deferred expired bmask */ 409 u_int32_t ap_intmask; /* interrupts we care about */ 410 struct ahci_ccb *ap_ccbs; 411 struct ahci_ccb *ap_err_ccb; /* always CCB SLOT 1 */ 412 int ap_run_flags; /* used to check excl mode */ 413 414 TAILQ_HEAD(, ahci_ccb) ap_ccb_free; 415 TAILQ_HEAD(, ahci_ccb) ap_ccb_pending; 416 struct lock ap_ccb_lock; 417 418 int ap_type; /* ATA_PORT_T_xxx */ 419 int ap_probe; /* ATA_PROBE_xxx */ 420 struct ata_port *ap_ata[AHCI_MAX_PMPORTS]; 421 422 u_int32_t ap_state; 423 #define AP_S_NORMAL 0 424 #define AP_S_FATAL_ERROR 1 425 426 /* For error recovery. */ 427 u_int32_t ap_err_saved_sactive; 428 u_int32_t ap_err_saved_active; 429 u_int32_t ap_err_saved_active_cnt; 430 431 u_int8_t *ap_err_scratch; 432 433 int link_pwr_mgmt; 434 435 struct sysctl_ctx_list sysctl_ctx; 436 struct sysctl_oid *sysctl_tree; 437 438 char ap_name[16]; 439 }; 440 441 #define PORTNAME(_ap) ((_ap)->ap_name) 442 #define ATANAME(_ap, _at) ((_at) ? (_at)->at_name : (_ap)->ap_name) 443 444 struct ahci_softc { 445 device_t sc_dev; 446 const struct ahci_device *sc_ad; /* special casing */ 447 448 struct resource *sc_irq; /* bus resources */ 449 struct resource *sc_regs; /* bus resources */ 450 bus_space_tag_t sc_iot; /* split from sc_regs */ 451 bus_space_handle_t sc_ioh; /* split from sc_regs */ 452 453 int sc_rid_irq; /* saved bus RIDs */ 454 int sc_rid_regs; 455 u_int32_t sc_cap; /* capabilities */ 456 int sc_numports; 457 u_int32_t sc_portmask; 458 459 void *sc_irq_handle; /* installed irq vector */ 460 461 bus_dma_tag_t sc_tag_rfis; /* bus DMA tags */ 462 bus_dma_tag_t sc_tag_cmdh; 463 bus_dma_tag_t sc_tag_cmdt; 464 bus_dma_tag_t sc_tag_data; 465 466 int sc_flags; 467 #define AHCI_F_NO_NCQ (1<<0) 468 #define AHCI_F_IGN_FR (1<<1) 469 #define AHCI_F_INT_GOOD (1<<2) 470 471 u_int sc_ncmds; 472 473 struct ahci_port *sc_ports[AHCI_MAX_PORTS]; 474 475 #ifdef AHCI_COALESCE 476 u_int32_t sc_ccc_mask; 477 u_int32_t sc_ccc_ports; 478 u_int32_t sc_ccc_ports_cur; 479 #endif 480 481 struct sysctl_ctx_list sysctl_ctx; 482 struct sysctl_oid *sysctl_tree; 483 }; 484 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 485 486 struct ahci_device { 487 pci_vendor_id_t ad_vendor; 488 pci_product_id_t ad_product; 489 int (*ad_attach)(device_t dev); 490 int (*ad_detach)(device_t dev); 491 char *name; 492 }; 493 494 /* Wait for all bits in _b to be cleared */ 495 #define ahci_pwait_clr(_ap, _r, _b) \ 496 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), 0) 497 #define ahci_pwait_clr_to(_ap, _to, _r, _b) \ 498 ahci_pwait_eq((_ap), _to, (_r), (_b), 0) 499 500 /* Wait for all bits in _b to be set */ 501 #define ahci_pwait_set(_ap, _r, _b) \ 502 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), (_b)) 503 #define ahci_pwait_set_to(_ap, _to, _r, _b) \ 504 ahci_pwait_eq((_ap), _to, (_r), (_b), (_b)) 505 506 #define AHCI_PWAIT_TIMEOUT 1000 507 508 const struct ahci_device *ahci_lookup_device(device_t dev); 509 int ahci_init(struct ahci_softc *); 510 int ahci_port_init(struct ahci_port *ap); 511 int ahci_port_alloc(struct ahci_softc *, u_int); 512 void ahci_port_state_machine(struct ahci_port *ap, int initial); 513 void ahci_port_free(struct ahci_softc *, u_int); 514 int ahci_port_reset(struct ahci_port *, struct ata_port *at, int); 515 void ahci_port_link_pwr_mgmt(struct ahci_port *, int link_pwr_mgmt); 516 int ahci_port_link_pwr_state(struct ahci_port *); 517 518 u_int32_t ahci_read(struct ahci_softc *, bus_size_t); 519 void ahci_write(struct ahci_softc *, bus_size_t, u_int32_t); 520 int ahci_wait_ne(struct ahci_softc *, bus_size_t, u_int32_t, u_int32_t); 521 u_int32_t ahci_pread(struct ahci_port *, bus_size_t); 522 void ahci_pwrite(struct ahci_port *, bus_size_t, u_int32_t); 523 int ahci_pwait_eq(struct ahci_port *, int, bus_size_t, 524 u_int32_t, u_int32_t); 525 void ahci_intr(void *); 526 void ahci_port_intr(struct ahci_port *ap, int blockable); 527 528 int ahci_port_start(struct ahci_port *ap); 529 int ahci_port_stop(struct ahci_port *ap, int stop_fis_rx); 530 int ahci_port_clo(struct ahci_port *ap); 531 void ahci_flush_tfd(struct ahci_port *ap); 532 int ahci_set_feature(struct ahci_port *ap, struct ata_port *atx, 533 int feature, int enable); 534 535 int ahci_cam_attach(struct ahci_port *ap); 536 void ahci_cam_changed(struct ahci_port *ap, struct ata_port *at, int found); 537 void ahci_cam_detach(struct ahci_port *ap); 538 int ahci_cam_probe(struct ahci_port *ap, struct ata_port *at); 539 540 struct ata_xfer *ahci_ata_get_xfer(struct ahci_port *ap, struct ata_port *at); 541 void ahci_ata_put_xfer(struct ata_xfer *xa); 542 int ahci_ata_cmd(struct ata_xfer *xa); 543 544 int ahci_pm_port_probe(struct ahci_port *ap, int); 545 int ahci_pm_port_init(struct ahci_port *ap, struct ata_port *at); 546 int ahci_pm_identify(struct ahci_port *ap); 547 int ahci_pm_hardreset(struct ahci_port *ap, int target, int hard); 548 int ahci_pm_softreset(struct ahci_port *ap, int target); 549 int ahci_pm_phy_status(struct ahci_port *ap, int target, u_int32_t *datap); 550 int ahci_pm_read(struct ahci_port *ap, int target, 551 int which, u_int32_t *res); 552 int ahci_pm_write(struct ahci_port *ap, int target, 553 int which, u_int32_t data); 554 void ahci_pm_check_good(struct ahci_port *ap, int target); 555 void ahci_ata_cmd_timeout(struct ahci_ccb *ccb); 556 void ahci_quick_timeout(struct ahci_ccb *ccb); 557 struct ahci_ccb *ahci_get_ccb(struct ahci_port *ap); 558 void ahci_put_ccb(struct ahci_ccb *ccb); 559 struct ahci_ccb *ahci_get_err_ccb(struct ahci_port *); 560 void ahci_put_err_ccb(struct ahci_ccb *); 561 int ahci_poll(struct ahci_ccb *ccb, int timeout, 562 void (*timeout_fn)(struct ahci_ccb *)); 563 564 int ahci_port_signature_detect(struct ahci_port *ap, struct ata_port *at); 565 void ahci_port_thread_core(struct ahci_port *ap, int mask); 566 567 void ahci_os_sleep(int ms); 568 void ahci_os_hardsleep(int us); 569 int ahci_os_softsleep(void); 570 void ahci_os_start_port(struct ahci_port *ap); 571 void ahci_os_stop_port(struct ahci_port *ap); 572 void ahci_os_signal_port_thread(struct ahci_port *ap, int mask); 573 void ahci_os_lock_port(struct ahci_port *ap); 574 int ahci_os_lock_port_nb(struct ahci_port *ap); 575 void ahci_os_unlock_port(struct ahci_port *ap); 576 577 extern u_int32_t AhciForceGen1; 578 extern u_int32_t AhciNoFeatures; 579 580 enum {AHCI_LINK_PWR_MGMT_NONE, AHCI_LINK_PWR_MGMT_MEDIUM, 581 AHCI_LINK_PWR_MGMT_AGGR}; 582