1 /* 2 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $ 17 */ 18 19 #if defined(__DragonFly__) 20 #include "ahci_dragonfly.h" 21 #else 22 #error "build for OS unknown" 23 #endif 24 #include "pmreg.h" 25 #include "atascsi.h" 26 27 /* change to AHCI_DEBUG for dmesg spam */ 28 #define NO_AHCI_DEBUG 29 30 #ifdef AHCI_DEBUG 31 #define DPRINTF(m, f...) do { if ((ahcidebug & (m)) == (m)) kprintf(f); } \ 32 while (0) 33 #define AHCI_D_TIMEOUT 0x00 34 #define AHCI_D_VERBOSE 0x01 35 #define AHCI_D_INTR 0x02 36 #define AHCI_D_XFER 0x08 37 int ahcidebug = AHCI_D_VERBOSE; 38 #else 39 #define DPRINTF(m, f...) 40 #endif 41 42 #define AHCI_PCI_ATI_SB600_MAGIC 0x40 43 #define AHCI_PCI_ATI_SB600_LOCKED 0x01 44 45 #define AHCI_REG_CAP 0x000 /* HBA Capabilities */ 46 #define AHCI_REG_CAP_NP(_r) (((_r) & 0x1f)+1) /* Number of Ports */ 47 #define AHCI_REG_CAP_SXS (1<<5) /* External SATA */ 48 #define AHCI_REG_CAP_EMS (1<<6) /* Enclosure Mgmt */ 49 #define AHCI_REG_CAP_CCCS (1<<7) /* Cmd Coalescing */ 50 #define AHCI_REG_CAP_NCS(_r) ((((_r) & 0x1f00)>>8)+1) /* NCmds*/ 51 #define AHCI_REG_CAP_PSC (1<<13) /* Partial State Capable */ 52 #define AHCI_REG_CAP_SSC (1<<14) /* Slumber State Capable */ 53 #define AHCI_REG_CAP_PMD (1<<15) /* PIO Multiple DRQ Block */ 54 #define AHCI_REG_CAP_FBSS (1<<16) /* FIS-Based Switching Supp */ 55 #define AHCI_REG_CAP_SPM (1<<17) /* Port Multiplier */ 56 #define AHCI_REG_CAP_SAM (1<<18) /* AHCI Only mode */ 57 #define AHCI_REG_CAP_SNZO (1<<19) /* Non Zero DMA Offsets */ 58 #define AHCI_REG_CAP_ISS (0xf<<20) /* Interface Speed Support */ 59 #define AHCI_REG_CAP_ISS_G1 (0x1<<20) /* Gen 1 (1.5 Gbps) */ 60 #define AHCI_REG_CAP_ISS_G2 (0x2<<20) /* Gen 2 (3 Gbps) */ 61 #define AHCI_REG_CAP_ISS_G3 (0x3<<20) /* Gen 3 (6 Gbps) */ 62 #define AHCI_REG_CAP_SCLO (1<<24) /* Cmd List Override */ 63 #define AHCI_REG_CAP_SAL (1<<25) /* Activity LED */ 64 #define AHCI_REG_CAP_SALP (1<<26) /* Aggressive Link Pwr Mgmt */ 65 #define AHCI_REG_CAP_SSS (1<<27) /* Staggered Spinup */ 66 #define AHCI_REG_CAP_SMPS (1<<28) /* Mech Presence Switch */ 67 #define AHCI_REG_CAP_SSNTF (1<<29) /* SNotification Register */ 68 #define AHCI_REG_CAP_SNCQ (1<<30) /* Native Cmd Queuing */ 69 #define AHCI_REG_CAP_S64A (1<<31) /* 64bit Addressing */ 70 #define AHCI_FMT_CAP "\020" "\040S64A" "\037NCQ" "\036SSNTF" \ 71 "\035SMPS" "\034SSS" "\033SALP" "\032SAL" \ 72 "\031SCLO" "\024SNZO" "\023SAM" "\022SPM" \ 73 "\021FBSS" "\020PMD" "\017SSC" "\016PSC" \ 74 "\010CCCS" "\007EMS" "\006SXS" 75 76 #define AHCI_REG_GHC 0x004 /* Global HBA Control */ 77 #define AHCI_REG_GHC_HR (1<<0) /* HBA Reset */ 78 #define AHCI_REG_GHC_IE (1<<1) /* Interrupt Enable */ 79 #define AHCI_REG_GHC_MRSM (1<<2) /* MSI Revert to Single Msg */ 80 #define AHCI_REG_GHC_AE (1<<31) /* AHCI Enable */ 81 #define AHCI_FMT_GHC "\020" "\040AE" "\003MRSM" "\002IE" "\001HR" 82 83 #define AHCI_REG_IS 0x008 /* Interrupt Status */ 84 #define AHCI_REG_PI 0x00c /* Ports Implemented */ 85 86 #define AHCI_REG_VS 0x010 /* AHCI Version */ 87 #define AHCI_REG_VS_0_95 0x00000905 /* 0.95 */ 88 #define AHCI_REG_VS_1_0 0x00010000 /* 1.0 */ 89 #define AHCI_REG_VS_1_1 0x00010100 /* 1.1 */ 90 #define AHCI_REG_VS_1_2 0x00010200 /* 1.2 */ 91 #define AHCI_REG_VS_1_3 0x00010300 /* 1.3 */ 92 #define AHCI_REG_VS_1_4 0x00010400 /* 1.4 */ 93 #define AHCI_REG_VS_1_5 0x00010500 /* 1.5 (future...) */ 94 95 #define AHCI_REG_CCC_CTL 0x014 /* Coalescing Control */ 96 #define AHCI_REG_CCC_CTL_INT(_r) (((_r) & 0xf8) >> 3) /* CCC INT slot */ 97 98 #define AHCI_REG_CCC_PORTS 0x018 /* Coalescing Ports */ 99 #define AHCI_REG_EM_LOC 0x01c /* Enclosure Mgmt Location */ 100 #define AHCI_REG_EM_CTL 0x020 /* Enclosure Mgmt Control */ 101 102 #define AHCI_REG_CAP2 0x024 /* Host Capabilities Extended */ 103 #define AHCI_REG_CAP2_BOH (1<<0) /* BIOS/OS Handoff */ 104 #define AHCI_REG_CAP2_NVMP (1<<1) /* NVMHCI Present */ 105 #define AHCI_REG_CAP2_APST (1<<2) /* A-Partial to Slumber Trans */ 106 #define AHCI_FMT_CAP2 "\020" "\003BOH" "\002NVMP" "\001BOH" 107 108 #define AHCI_REG_BOHC 0x028 /* BIOS/OS Handoff Control and Status */ 109 #define AHCI_REG_BOHC_BOS (1<<0) /* BIOS Owned Semaphore */ 110 #define AHCI_REG_BOHC_OOS (1<<1) /* OS Owned Semaphore */ 111 #define AHCI_REG_BOHC_SOOE (1<<2) /* SMI on OS Own chg enable */ 112 #define AHCI_REG_BOHC_OOC (1<<3) /* OS Ownership Change */ 113 #define AHCI_REG_BOHC_BB (1<<4) /* BIOS Busy */ 114 #define AHCI_FMT_BOHC "\020" "\005BB" "\004OOC" "\003SOOE" \ 115 "\002OOS" "\001BOS" 116 117 #define AHCI_PORT_REGION(_p) (0x100 + ((_p) * 0x80)) 118 #define AHCI_PORT_SIZE 0x80 119 120 #define AHCI_PREG_CLB 0x00 /* Cmd List Base Addr */ 121 #define AHCI_PREG_CLBU 0x04 /* Cmd List Base Hi Addr */ 122 #define AHCI_PREG_FB 0x08 /* FIS Base Addr */ 123 #define AHCI_PREG_FBU 0x0c /* FIS Base Hi Addr */ 124 125 #define AHCI_PREG_IS 0x10 /* Interrupt Status */ 126 #define AHCI_PREG_IS_DHRS (1<<0) /* Device to Host FIS */ 127 #define AHCI_PREG_IS_PSS (1<<1) /* PIO Setup FIS */ 128 #define AHCI_PREG_IS_DSS (1<<2) /* DMA Setup FIS */ 129 #define AHCI_PREG_IS_SDBS (1<<3) /* Set Device Bits FIS */ 130 #define AHCI_PREG_IS_UFS (1<<4) /* Unknown FIS */ 131 #define AHCI_PREG_IS_DPS (1<<5) /* Descriptor Processed */ 132 #define AHCI_PREG_IS_PCS (1<<6) /* Port Change */ 133 #define AHCI_PREG_IS_DMPS (1<<7) /* Device Mechanical Presence */ 134 #define AHCI_PREG_IS_PRCS (1<<22) /* PhyRdy Change */ 135 #define AHCI_PREG_IS_IPMS (1<<23) /* Incorrect Port Multiplier */ 136 #define AHCI_PREG_IS_OFS (1<<24) /* Overflow */ 137 #define AHCI_PREG_IS_INFS (1<<26) /* Interface Non-fatal Error */ 138 #define AHCI_PREG_IS_IFS (1<<27) /* Interface Fatal Error */ 139 #define AHCI_PREG_IS_HBDS (1<<28) /* Host Bus Data Error */ 140 #define AHCI_PREG_IS_HBFS (1<<29) /* Host Bus Fatal Error */ 141 #define AHCI_PREG_IS_TFES (1<<30) /* Task File Error */ 142 #define AHCI_PREG_IS_CPDS (1<<31) /* Cold Presence Detect */ 143 #define AHCI_PFMT_IS "\20" "\040CPDS" "\037TFES" "\036HBFS" \ 144 "\035HBDS" "\034IFS" "\033INFS" "\031OFS" \ 145 "\030IPMS" "\027PRCS" "\010DMPS" "\006DPS" \ 146 "\007PCS" "\005UFS" "\004SDBS" "\003DSS" \ 147 "\002PSS" "\001DHRS" 148 149 #define AHCI_PREG_IE 0x14 /* Interrupt Enable */ 150 #define AHCI_PREG_IE_DHRE (1<<0) /* Device to Host FIS */ 151 #define AHCI_PREG_IE_PSE (1<<1) /* PIO Setup FIS */ 152 #define AHCI_PREG_IE_DSE (1<<2) /* DMA Setup FIS */ 153 #define AHCI_PREG_IE_SDBE (1<<3) /* Set Device Bits FIS */ 154 #define AHCI_PREG_IE_UFE (1<<4) /* Unknown FIS */ 155 #define AHCI_PREG_IE_DPE (1<<5) /* Descriptor Processed */ 156 #define AHCI_PREG_IE_PCE (1<<6) /* Port Change */ 157 #define AHCI_PREG_IE_DMPE (1<<7) /* Device Mechanical Presence */ 158 #define AHCI_PREG_IE_PRCE (1<<22) /* PhyRdy Change */ 159 #define AHCI_PREG_IE_IPME (1<<23) /* Incorrect Port Multiplier */ 160 #define AHCI_PREG_IE_OFE (1<<24) /* Overflow */ 161 #define AHCI_PREG_IE_INFE (1<<26) /* Interface Non-fatal Error */ 162 #define AHCI_PREG_IE_IFE (1<<27) /* Interface Fatal Error */ 163 #define AHCI_PREG_IE_HBDE (1<<28) /* Host Bus Data Error */ 164 #define AHCI_PREG_IE_HBFE (1<<29) /* Host Bus Fatal Error */ 165 #define AHCI_PREG_IE_TFEE (1<<30) /* Task File Error */ 166 #define AHCI_PREG_IE_CPDE (1<<31) /* Cold Presence Detect */ 167 #define AHCI_PFMT_IE "\20" "\040CPDE" "\037TFEE" "\036HBFE" \ 168 "\035HBDE" "\034IFE" "\033INFE" "\031OFE" \ 169 "\030IPME" "\027PRCE" "\010DMPE" "\007PCE" \ 170 "\006DPE" "\005UFE" "\004SDBE" "\003DSE" \ 171 "\002PSE" "\001DHRE" 172 173 /* 174 * NOTE: bits 22, 21, 20, 19, 18, 16, 15, 14, 13, 12:08, 07:05 are always 175 * read-only. Other bits may be read-only when the related feature 176 * is not supported by the HBA. 177 */ 178 #define AHCI_PREG_CMD 0x18 /* Command and Status */ 179 #define AHCI_PREG_CMD_ST (1<<0) /* Start */ 180 #define AHCI_PREG_CMD_SUD (1<<1) /* Spin Up Device */ 181 #define AHCI_PREG_CMD_POD (1<<2) /* Power On Device */ 182 #define AHCI_PREG_CMD_CLO (1<<3) /* Command List Override */ 183 #define AHCI_PREG_CMD_FRE (1<<4) /* FIS Receive Enable */ 184 #define AHCI_PREG_CMD_CCS(_r) (((_r) >> 8) & 0x1f) /* Curr CmdSlot# */ 185 #define AHCI_PREG_CMD_MPSS (1<<13) /* Mech Presence State */ 186 #define AHCI_PREG_CMD_FR (1<<14) /* FIS Receive Running */ 187 #define AHCI_PREG_CMD_CR (1<<15) /* Command List Running */ 188 #define AHCI_PREG_CMD_CPS (1<<16) /* Cold Presence State */ 189 #define AHCI_PREG_CMD_PMA (1<<17) /* Port Multiplier Attached */ 190 #define AHCI_PREG_CMD_HPCP (1<<18) /* Hot Plug Capable */ 191 #define AHCI_PREG_CMD_MPSP (1<<19) /* Mech Presence Switch */ 192 #define AHCI_PREG_CMD_CPD (1<<20) /* Cold Presence Detection */ 193 #define AHCI_PREG_CMD_ESP (1<<21) /* External SATA Port */ 194 #define AHCI_PREG_CMD_FBSCP (1<<22) /* FIS-based sw capable port */ 195 #define AHCI_PREG_CMD_APSTE (1<<23) /* Auto Partial to Slumber */ 196 #define AHCI_PREG_CMD_ATAPI (1<<24) /* Device is ATAPI */ 197 #define AHCI_PREG_CMD_DLAE (1<<25) /* Drv LED on ATAPI Enable */ 198 #define AHCI_PREG_CMD_ALPE (1<<26) /* Aggro Pwr Mgmt Enable */ 199 #define AHCI_PREG_CMD_ASP (1<<27) /* Aggro Slumber/Partial */ 200 #define AHCI_PREG_CMD_ICC 0xf0000000 /* Interface Comm Ctrl */ 201 #define AHCI_PREG_CMD_ICC_SLUMBER 0x60000000 202 #define AHCI_PREG_CMD_ICC_PARTIAL 0x20000000 203 #define AHCI_PREG_CMD_ICC_ACTIVE 0x10000000 204 #define AHCI_PREG_CMD_ICC_IDLE 0x00000000 205 #define AHCI_PFMT_CMD "\020" "\034ASP" "\033ALPE" "\032DLAE" \ 206 "\031ATAPI" "\030APSTE" "\027FBSCP" \ 207 "\026ESP" "\025CPD" "\024MPSP" \ 208 "\023HPCP" "\022PMA" "\021CPS" "\020CR" \ 209 "\017FR" "\016MPSS" "\005FRE" "\004CLO" \ 210 "\003POD" "\002SUD" "\001ST" 211 212 #define AHCI_PREG_TFD 0x20 /* Task File Data*/ 213 #define AHCI_PREG_TFD_STS 0xff 214 #define AHCI_PREG_TFD_STS_ERR (1<<0) 215 #define AHCI_PREG_TFD_STS_DRQ (1<<3) 216 #define AHCI_PREG_TFD_STS_BSY (1<<7) 217 #define AHCI_PREG_TFD_ERR 0xff00 218 219 #define AHCI_PFMT_TFD_STS "\20" "\010BSY" "\004DRQ" "\001ERR" 220 #define AHCI_PREG_SIG 0x24 /* Signature */ 221 222 #define AHCI_PREG_SSTS 0x28 /* SATA Status */ 223 #define AHCI_PREG_SSTS_DET 0xf /* Device Detection */ 224 #define AHCI_PREG_SSTS_DET_NONE 0x0 225 #define AHCI_PREG_SSTS_DET_DEV_NE 0x1 226 #define AHCI_PREG_SSTS_DET_DEV 0x3 227 #define AHCI_PREG_SSTS_DET_PHYOFFLINE 0x4 228 #define AHCI_PREG_SSTS_SPD 0xf0 /* Current Interface Speed */ 229 #define AHCI_PREG_SSTS_SPD_NONE 0x00 230 #define AHCI_PREG_SSTS_SPD_GEN1 0x10 231 #define AHCI_PREG_SSTS_SPD_GEN2 0x20 232 #define AHCI_PREG_SSTS_SPD_GEN3 0x30 233 #define AHCI_PREG_SSTS_IPM 0xf00 /* Interface Power Management */ 234 #define AHCI_PREG_SSTS_IPM_NONE 0x000 235 #define AHCI_PREG_SSTS_IPM_ACTIVE 0x100 236 #define AHCI_PREG_SSTS_IPM_PARTIAL 0x200 237 #define AHCI_PREG_SSTS_IPM_SLUMBER 0x600 238 239 #define AHCI_PREG_SCTL 0x2c /* SATA Control */ 240 #define AHCI_PREG_SCTL_DET 0xf /* Device Detection */ 241 #define AHCI_PREG_SCTL_DET_NONE 0x0 242 #define AHCI_PREG_SCTL_DET_INIT 0x1 243 #define AHCI_PREG_SCTL_DET_DISABLE 0x4 244 #define AHCI_PREG_SCTL_SPD 0xf0 /* Speed Allowed */ 245 #define AHCI_PREG_SCTL_SPD_ANY 0x00 246 #define AHCI_PREG_SCTL_SPD_GEN1 0x10 247 #define AHCI_PREG_SCTL_SPD_GEN2 0x20 248 #define AHCI_PREG_SCTL_SPD_GEN3 0x30 249 #define AHCI_PREG_SCTL_IPM 0xf00 /* Interface Power Management */ 250 #define AHCI_PREG_SCTL_IPM_NONE 0x000 251 #define AHCI_PREG_SCTL_IPM_NOPARTIAL 0x100 252 #define AHCI_PREG_SCTL_IPM_NOSLUMBER 0x200 253 #define AHCI_PREG_SCTL_IPM_DISABLED 0x300 254 #define AHCI_PREG_SCTL_SPM 0xf000 /* Select Power Management */ 255 #define AHCI_PREG_SCTL_SPM_NONE 0x0000 256 #define AHCI_PREG_SCTL_SPM_NOPARTIAL 0x1000 257 #define AHCI_PREG_SCTL_SPM_NOSLUMBER 0x2000 258 #define AHCI_PREG_SCTL_SPM_DISABLED 0x3000 259 #define AHCI_PREG_SCTL_PMP 0xf0000 /* Set PM port for xmit FISes */ 260 #define AHCI_PREG_SCTL_PMP_SHIFT 16 261 262 #define AHCI_PREG_SERR 0x30 /* SATA Error */ 263 #define AHCI_PREG_SERR_ERR_I (1<<0) /* Recovered Data Integrity */ 264 #define AHCI_PREG_SERR_ERR_M (1<<1) /* Recovered Communications */ 265 #define AHCI_PREG_SERR_ERR_T (1<<8) /* Transient Data Integrity */ 266 #define AHCI_PREG_SERR_ERR_C (1<<9) /* Persistent Comm/Data */ 267 #define AHCI_PREG_SERR_ERR_P (1<<10) /* Protocol */ 268 #define AHCI_PREG_SERR_ERR_E (1<<11) /* Internal */ 269 #define AHCI_PREG_SERR_DIAG_N (1<<16) /* PhyRdy Change */ 270 #define AHCI_PREG_SERR_DIAG_I (1<<17) /* Phy Internal Error */ 271 #define AHCI_PREG_SERR_DIAG_W (1<<18) /* Comm Wake */ 272 #define AHCI_PREG_SERR_DIAG_B (1<<19) /* 10B to 8B Decode Error */ 273 #define AHCI_PREG_SERR_DIAG_D (1<<20) /* Disparity Error */ 274 #define AHCI_PREG_SERR_DIAG_C (1<<21) /* CRC Error */ 275 #define AHCI_PREG_SERR_DIAG_H (1<<22) /* Handshake Error */ 276 #define AHCI_PREG_SERR_DIAG_S (1<<23) /* Link Sequence Error */ 277 #define AHCI_PREG_SERR_DIAG_T (1<<24) /* Transport State Trans Err */ 278 #define AHCI_PREG_SERR_DIAG_F (1<<25) /* Unknown FIS Type */ 279 #define AHCI_PREG_SERR_DIAG_X (1<<26) /* Exchanged */ 280 281 #define AHCI_PFMT_SERR "\020" \ 282 "\033DIAG.X" "\032DIAG.F" "\031DIAG.T" "\030DIAG.S" \ 283 "\027DIAG.H" "\026DIAG.C" "\025DIAG.D" "\024DIAG.B" \ 284 "\023DIAG.W" "\022DIAG.I" "\021DIAG.N" \ 285 "\014ERR.E" "\013ERR.P" "\012ERR.C" "\011ERR.T" \ 286 "\002ERR.M" "\001ERR.I" 287 288 #define AHCI_PREG_SACT 0x34 /* SATA Active */ 289 #define AHCI_PREG_CI 0x38 /* Command Issue */ 290 #define AHCI_PREG_CI_ALL_SLOTS 0xffffffff 291 #define AHCI_PREG_SNTF 0x3c /* SNotification */ 292 293 /* 294 * EN - Enable FIS based switch, can only be changed when ST is clear 295 * 296 * DEC - Device Error Clear, state machine. Set to 1 by software only 297 * for the EN+SDE case, then poll until hardware sets it back to 0. 298 * Writing 0 has no effect. 299 * 300 * SDE - Set by hardware indicating a single device error occurred. If 301 * not set and an error occurred then the error was whole-port. 302 * 303 * DEV - Set by software to the PM target of the next command to issue 304 * via the PREG_CI registers. Software should not issue multiple 305 * commands covering different targets in a single write. This 306 * basically causes writes to PREG_CI to index within the hardware. 307 * 308 * ADO - (read only) Indicate how many concurrent devices commands may 309 * be issued to at once. Degredation may occur if commands are 310 * issued to more devices but the case is allowed. 311 * 312 * DWE - (read only) Only valid on SDE errors. Hardware indicates which 313 * PM target generated the error in this field. 314 * 315 */ 316 #define AHCI_PREG_FBS 0x40 /* FIS-Based Switching Control */ 317 #define AHCI_PREG_FBS_EN (1<<0) /* FIS-Based switching enable */ 318 #define AHCI_PREG_FBS_DEC (1<<1) /* Device Error Clear */ 319 #define AHCI_PREG_FBS_SDE (1<<2) /* Single-device Error */ 320 #define AHCI_PREG_FBS_DEV 0x00000F00 /* Device to Issue mask */ 321 #define AHCI_PREG_FBS_ADO 0x0000F000 /* Active Dev Optimize */ 322 #define AHCI_PREG_FBS_DWE 0x000F0000 /* Device With Error */ 323 #define AHCI_PREG_FBS_DEV_SHIFT 8 324 #define AHCI_PREG_FBS_ADO_SHIFT 12 325 #define AHCI_PREG_FBS_DWE_SHIFT 16 326 327 /* 328 * AHCI mapped structures 329 */ 330 struct ahci_cmd_hdr { 331 u_int16_t flags; 332 #define AHCI_CMD_LIST_FLAG_CFL 0x001f /* Command FIS Length */ 333 #define AHCI_CMD_LIST_FLAG_A (1<<5) /* ATAPI */ 334 #define AHCI_CMD_LIST_FLAG_W (1<<6) /* Write */ 335 #define AHCI_CMD_LIST_FLAG_P (1<<7) /* Prefetchable */ 336 #define AHCI_CMD_LIST_FLAG_R (1<<8) /* Reset */ 337 #define AHCI_CMD_LIST_FLAG_B (1<<9) /* BIST */ 338 #define AHCI_CMD_LIST_FLAG_C (1<<10) /* Clear Busy upon R_OK */ 339 #define AHCI_CMD_LIST_FLAG_PMP 0xf000 /* Port Multiplier Port */ 340 #define AHCI_CMD_LIST_FLAG_PMP_SHIFT 12 341 u_int16_t prdtl; /* sgl len */ 342 343 u_int32_t prdbc; /* transferred byte count */ 344 345 u_int32_t ctba_lo; 346 u_int32_t ctba_hi; 347 348 u_int32_t reserved[4]; 349 } __packed; 350 351 struct ahci_rfis { 352 u_int8_t dsfis[28]; 353 u_int8_t reserved1[4]; 354 u_int8_t psfis[24]; 355 u_int8_t reserved2[8]; 356 u_int8_t rfis[24]; 357 u_int8_t reserved3[4]; 358 u_int8_t sdbfis[4]; 359 u_int8_t ufis[64]; 360 u_int8_t reserved4[96]; 361 } __packed; 362 363 struct ahci_prdt { 364 u_int32_t dba_lo; 365 u_int32_t dba_hi; 366 u_int32_t reserved; 367 u_int32_t flags; 368 #define AHCI_PRDT_FLAG_INTR (1<<31) /* interrupt on completion */ 369 } __packed; 370 371 /* 372 * The base command table structure is 128 bytes. Each prdt is 16 bytes. 373 * We need to accomodate a 2MB maximum I/O transfer size, which is at least 374 * 512 entries, plus one for page slop. 375 * 376 * Making the ahci_cmd_table 16384 bytes (a reasonable power of 2) 377 * thus requires MAX_PRDT to be set to 1016. 378 */ 379 #define AHCI_MAX_PRDT 1016 380 #define AHCI_MAX_PMPORTS 16 381 382 #define AHCI_MAXPHYS (2 * 1024 * 1024) /* 2MB */ 383 #if AHCI_MAXPHYS / PAGE_SIZE + 1 > AHCI_MAX_PRDT 384 #error "AHCI_MAX_PRDT is not big enough" 385 #endif 386 387 struct ahci_cmd_table { 388 u_int8_t cfis[64]; /* Command FIS */ 389 u_int8_t acmd[16]; /* ATAPI Command */ 390 u_int8_t reserved[48]; 391 392 struct ahci_prdt prdt[AHCI_MAX_PRDT]; 393 } __packed; 394 395 #define AHCI_MAX_PORTS 32 396 397 struct ahci_dmamem { 398 bus_dma_tag_t adm_tag; 399 bus_dmamap_t adm_map; 400 bus_dma_segment_t adm_seg; 401 bus_addr_t adm_busaddr; 402 caddr_t adm_kva; 403 }; 404 #define AHCI_DMA_MAP(_adm) ((_adm)->adm_map) 405 #define AHCI_DMA_DVA(_adm) ((_adm)->adm_busaddr) 406 #define AHCI_DMA_KVA(_adm) ((void *)(_adm)->adm_kva) 407 408 struct ahci_softc; 409 struct ahci_port; 410 struct ahci_device; 411 412 struct ahci_ccb { 413 /* ATA xfer associated with this CCB. Must be 1st struct member. */ 414 struct ata_xfer ccb_xa; 415 struct callout ccb_timeout; 416 417 int ccb_slot; 418 struct ahci_port *ccb_port; 419 420 bus_dmamap_t ccb_dmamap; 421 struct ahci_cmd_hdr *ccb_cmd_hdr; 422 struct ahci_cmd_table *ccb_cmd_table; 423 424 void (*ccb_done)(struct ahci_ccb *); 425 426 TAILQ_ENTRY(ahci_ccb) ccb_entry; 427 }; 428 429 struct ahci_port { 430 struct ahci_softc *ap_sc; 431 bus_space_handle_t ap_ioh; 432 433 int ap_num; 434 int ap_pmcount; 435 int ap_flags; 436 #define AP_F_BUS_REGISTERED 0x0001 437 #define AP_F_CAM_ATTACHED 0x0002 438 #define AP_F_IN_RESET 0x0004 439 #define AP_F_SCAN_RUNNING 0x0008 440 #define AP_F_SCAN_REQUESTED 0x0010 441 #define AP_F_SCAN_COMPLETED 0x0020 442 #define AP_F_IGNORE_IFS 0x0040 443 #define AP_F_IFS_IGNORED 0x0080 444 #define AP_F_UNUSED_0100 0x0100 445 #define AP_F_EXCLUSIVE_ACCESS 0x0200 446 #define AP_F_ERR_CCB_RESERVED 0x0400 447 #define AP_F_HARSH_REINIT 0x0800 448 int ap_signal; /* os per-port thread sig */ 449 thread_t ap_thread; /* os per-port thread */ 450 struct lock ap_lock; /* os per-port lock */ 451 struct lock ap_sim_lock; /* cam sim lock */ 452 struct lock ap_sig_lock; /* signal thread */ 453 #define AP_SIGF_INIT 0x0001 454 #define AP_SIGF_TIMEOUT 0x0002 455 #define AP_SIGF_PORTINT 0x0004 456 #define AP_SIGF_THREAD_SYNC 0x0008 457 #define AP_SIGF_STOP 0x8000 458 struct cam_sim *ap_sim; 459 460 struct ahci_rfis *ap_rfis; 461 struct ahci_dmamem *ap_dmamem_rfis; 462 463 struct ahci_dmamem *ap_dmamem_cmd_list; 464 struct ahci_dmamem *ap_dmamem_cmd_table; 465 466 u_int32_t ap_active; /* active CI command bmask */ 467 u_int32_t ap_active_cnt; /* active CI command count */ 468 u_int32_t ap_sactive; /* active SACT command bmask */ 469 u_int32_t ap_expired; /* deferred expired bmask */ 470 u_int32_t ap_intmask; /* interrupts we care about */ 471 struct ahci_ccb *ap_ccbs; 472 struct ahci_ccb *ap_err_ccb; /* always CCB SLOT 1 */ 473 int ap_run_flags; /* used to check excl mode */ 474 475 TAILQ_HEAD(, ahci_ccb) ap_ccb_free; 476 TAILQ_HEAD(, ahci_ccb) ap_ccb_pending; 477 struct lock ap_ccb_lock; 478 479 int ap_type; /* ATA_PORT_T_xxx */ 480 int ap_probe; /* ATA_PROBE_xxx */ 481 struct ata_port *ap_ata[AHCI_MAX_PMPORTS]; 482 483 u_int32_t ap_state; 484 #define AP_S_NORMAL 0 485 #define AP_S_FATAL_ERROR 1 486 487 /* For error recovery. */ 488 u_int32_t ap_err_saved_sactive; 489 u_int32_t ap_err_saved_active; 490 u_int32_t ap_err_saved_active_cnt; 491 492 u_int8_t *ap_err_scratch; 493 494 int link_pwr_mgmt; 495 496 struct sysctl_ctx_list sysctl_ctx; 497 struct sysctl_oid *sysctl_tree; 498 499 char ap_name[16]; 500 }; 501 502 #define PORTNAME(_ap) ((_ap)->ap_name) 503 #define ATANAME(_ap, _at) ((_at) ? (_at)->at_name : (_ap)->ap_name) 504 505 struct ahci_softc { 506 device_t sc_dev; 507 const struct ahci_device *sc_ad; /* special casing */ 508 509 struct resource *sc_irq; /* bus resources */ 510 struct resource *sc_regs; /* bus resources */ 511 bus_space_tag_t sc_iot; /* split from sc_regs */ 512 bus_space_handle_t sc_ioh; /* split from sc_regs */ 513 514 int sc_irq_type; 515 int sc_rid_irq; /* saved bus RIDs */ 516 int sc_rid_regs; 517 u_int32_t sc_cap; /* capabilities */ 518 u_int32_t sc_cap2; /* capabilities */ 519 u_int32_t sc_vers; /* AHCI version */ 520 int sc_numports; 521 u_int32_t sc_portmask; 522 523 void *sc_irq_handle; /* installed irq vector */ 524 525 bus_dma_tag_t sc_tag_rfis; /* bus DMA tags */ 526 bus_dma_tag_t sc_tag_cmdh; 527 bus_dma_tag_t sc_tag_cmdt; 528 bus_dma_tag_t sc_tag_data; 529 530 int sc_flags; 531 #define AHCI_F_NO_NCQ 0x00000001 532 #define AHCI_F_IGN_FR 0x00000002 533 #define AHCI_F_INT_GOOD 0x00000004 534 #define AHCI_F_FORCE_FBSS 0x00000008 535 536 u_int sc_ncmds; 537 538 struct ahci_port *sc_ports[AHCI_MAX_PORTS]; 539 540 #ifdef AHCI_COALESCE 541 u_int32_t sc_ccc_mask; 542 u_int32_t sc_ccc_ports; 543 u_int32_t sc_ccc_ports_cur; 544 #endif 545 546 struct sysctl_ctx_list sysctl_ctx; 547 struct sysctl_oid *sysctl_tree; 548 }; 549 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 550 551 struct ahci_device { 552 pci_vendor_id_t ad_vendor; 553 pci_product_id_t ad_product; 554 int (*ad_attach)(device_t dev); 555 int (*ad_detach)(device_t dev); 556 char *name; 557 }; 558 559 /* Wait for all bits in _b to be cleared */ 560 #define ahci_pwait_clr(_ap, _r, _b) \ 561 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), 0) 562 #define ahci_pwait_clr_to(_ap, _to, _r, _b) \ 563 ahci_pwait_eq((_ap), _to, (_r), (_b), 0) 564 565 /* Wait for all bits in _b to be set */ 566 #define ahci_pwait_set(_ap, _r, _b) \ 567 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), (_b)) 568 #define ahci_pwait_set_to(_ap, _to, _r, _b) \ 569 ahci_pwait_eq((_ap), _to, (_r), (_b), (_b)) 570 571 #define AHCI_PWAIT_TIMEOUT 1000 572 573 const struct ahci_device *ahci_lookup_device(device_t dev); 574 int ahci_init(struct ahci_softc *); 575 int ahci_port_init(struct ahci_port *ap); 576 int ahci_port_alloc(struct ahci_softc *, u_int); 577 void ahci_port_state_machine(struct ahci_port *ap, int initial); 578 void ahci_port_free(struct ahci_softc *, u_int); 579 int ahci_port_reset(struct ahci_port *, struct ata_port *at, int); 580 void ahci_port_link_pwr_mgmt(struct ahci_port *, int link_pwr_mgmt); 581 int ahci_port_link_pwr_state(struct ahci_port *); 582 583 u_int32_t ahci_read(struct ahci_softc *, bus_size_t); 584 void ahci_write(struct ahci_softc *, bus_size_t, u_int32_t); 585 int ahci_wait_ne(struct ahci_softc *, bus_size_t, u_int32_t, u_int32_t); 586 u_int32_t ahci_pread(struct ahci_port *, bus_size_t); 587 void ahci_pwrite(struct ahci_port *, bus_size_t, u_int32_t); 588 int ahci_pwait_eq(struct ahci_port *, int, bus_size_t, 589 u_int32_t, u_int32_t); 590 void ahci_intr(void *); 591 void ahci_port_intr(struct ahci_port *ap, int blockable); 592 593 int ahci_port_start(struct ahci_port *ap); 594 int ahci_port_stop(struct ahci_port *ap, int stop_fis_rx); 595 int ahci_port_clo(struct ahci_port *ap); 596 void ahci_flush_tfd(struct ahci_port *ap); 597 int ahci_set_feature(struct ahci_port *ap, struct ata_port *atx, 598 int feature, int enable); 599 600 int ahci_cam_attach(struct ahci_port *ap); 601 void ahci_cam_changed(struct ahci_port *ap, struct ata_port *at, int found); 602 void ahci_cam_detach(struct ahci_port *ap); 603 int ahci_cam_probe(struct ahci_port *ap, struct ata_port *at); 604 605 struct ata_xfer *ahci_ata_get_xfer(struct ahci_port *ap, struct ata_port *at); 606 void ahci_ata_put_xfer(struct ata_xfer *xa); 607 int ahci_ata_cmd(struct ata_xfer *xa); 608 609 int ahci_pm_port_probe(struct ahci_port *ap, int); 610 int ahci_pm_port_init(struct ahci_port *ap, struct ata_port *at); 611 int ahci_pm_identify(struct ahci_port *ap); 612 int ahci_pm_hardreset(struct ahci_port *ap, int target, int hard); 613 int ahci_pm_softreset(struct ahci_port *ap, int target); 614 int ahci_pm_phy_status(struct ahci_port *ap, int target, u_int32_t *datap); 615 int ahci_pm_read(struct ahci_port *ap, int target, 616 int which, u_int32_t *res); 617 int ahci_pm_write(struct ahci_port *ap, int target, 618 int which, u_int32_t data); 619 void ahci_pm_check_good(struct ahci_port *ap, int target); 620 void ahci_ata_cmd_timeout(struct ahci_ccb *ccb); 621 void ahci_quick_timeout(struct ahci_ccb *ccb); 622 struct ahci_ccb *ahci_get_ccb(struct ahci_port *ap); 623 void ahci_put_ccb(struct ahci_ccb *ccb); 624 struct ahci_ccb *ahci_get_err_ccb(struct ahci_port *); 625 void ahci_put_err_ccb(struct ahci_ccb *); 626 int ahci_poll(struct ahci_ccb *ccb, int timeout, 627 void (*timeout_fn)(struct ahci_ccb *)); 628 629 int ahci_port_signature_detect(struct ahci_port *ap, struct ata_port *at); 630 void ahci_port_thread_core(struct ahci_port *ap, int mask); 631 632 void ahci_os_sleep(int ms); 633 void ahci_os_hardsleep(int us); 634 int ahci_os_softsleep(void); 635 void ahci_os_start_port(struct ahci_port *ap); 636 void ahci_os_stop_port(struct ahci_port *ap); 637 void ahci_os_signal_port_thread(struct ahci_port *ap, int mask); 638 void ahci_os_lock_port(struct ahci_port *ap); 639 int ahci_os_lock_port_nb(struct ahci_port *ap); 640 void ahci_os_unlock_port(struct ahci_port *ap); 641 642 extern u_int32_t AhciForceGen; 643 extern u_int32_t AhciNoFeatures; 644 645 enum {AHCI_LINK_PWR_MGMT_NONE, AHCI_LINK_PWR_MGMT_MEDIUM, 646 AHCI_LINK_PWR_MGMT_AGGR}; 647