1258223a3SMatthew Dillon /* 2fb00c6edSMatthew Dillon * (MPSAFE) 3fb00c6edSMatthew Dillon * 4258223a3SMatthew Dillon * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> 5258223a3SMatthew Dillon * 6258223a3SMatthew Dillon * Permission to use, copy, modify, and distribute this software for any 7258223a3SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above 8258223a3SMatthew Dillon * copyright notice and this permission notice appear in all copies. 9258223a3SMatthew Dillon * 10258223a3SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11258223a3SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12258223a3SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13258223a3SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14258223a3SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15258223a3SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16258223a3SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17258223a3SMatthew Dillon * 18258223a3SMatthew Dillon * 19258223a3SMatthew Dillon * Copyright (c) 2009 The DragonFly Project. All rights reserved. 20258223a3SMatthew Dillon * 21258223a3SMatthew Dillon * This code is derived from software contributed to The DragonFly Project 22258223a3SMatthew Dillon * by Matthew Dillon <dillon@backplane.com> 23258223a3SMatthew Dillon * 24258223a3SMatthew Dillon * Redistribution and use in source and binary forms, with or without 25258223a3SMatthew Dillon * modification, are permitted provided that the following conditions 26258223a3SMatthew Dillon * are met: 27258223a3SMatthew Dillon * 28258223a3SMatthew Dillon * 1. Redistributions of source code must retain the above copyright 29258223a3SMatthew Dillon * notice, this list of conditions and the following disclaimer. 30258223a3SMatthew Dillon * 2. Redistributions in binary form must reproduce the above copyright 31258223a3SMatthew Dillon * notice, this list of conditions and the following disclaimer in 32258223a3SMatthew Dillon * the documentation and/or other materials provided with the 33258223a3SMatthew Dillon * distribution. 34258223a3SMatthew Dillon * 3. Neither the name of The DragonFly Project nor the names of its 35258223a3SMatthew Dillon * contributors may be used to endorse or promote products derived 36258223a3SMatthew Dillon * from this software without specific, prior written permission. 37258223a3SMatthew Dillon * 38258223a3SMatthew Dillon * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 39258223a3SMatthew Dillon * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 40258223a3SMatthew Dillon * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 41258223a3SMatthew Dillon * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 42258223a3SMatthew Dillon * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 43258223a3SMatthew Dillon * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 44258223a3SMatthew Dillon * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 45258223a3SMatthew Dillon * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 46258223a3SMatthew Dillon * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 47258223a3SMatthew Dillon * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 48258223a3SMatthew Dillon * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 49258223a3SMatthew Dillon * SUCH DAMAGE. 50258223a3SMatthew Dillon * 51258223a3SMatthew Dillon * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $ 52258223a3SMatthew Dillon */ 53258223a3SMatthew Dillon 54258223a3SMatthew Dillon #include "ahci.h" 55258223a3SMatthew Dillon 56258223a3SMatthew Dillon static int ahci_vt8251_attach(device_t); 57258223a3SMatthew Dillon static int ahci_ati_sb600_attach(device_t); 58258223a3SMatthew Dillon static int ahci_nvidia_mcp_attach(device_t); 59258223a3SMatthew Dillon static int ahci_pci_attach(device_t); 60258223a3SMatthew Dillon static int ahci_pci_detach(device_t); 61258223a3SMatthew Dillon 62258223a3SMatthew Dillon static const struct ahci_device ahci_devices[] = { 63258223a3SMatthew Dillon { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA, 64258223a3SMatthew Dillon ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" }, 65258223a3SMatthew Dillon { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA, 66258223a3SMatthew Dillon ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" }, 67258223a3SMatthew Dillon { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 68258223a3SMatthew Dillon ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" }, 69258223a3SMatthew Dillon { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1, 70258223a3SMatthew Dillon ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" }, 71258223a3SMatthew Dillon { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 72258223a3SMatthew Dillon ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" }, 73f1d54ca5SSascha Wildner { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1, 74f1d54ca5SSascha Wildner ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP79-SATA" }, 75258223a3SMatthew Dillon { 0, 0, 76258223a3SMatthew Dillon ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" } 77258223a3SMatthew Dillon }; 78258223a3SMatthew Dillon 79887d793aSSepherosa Ziehau struct ahci_pciid { 80887d793aSSepherosa Ziehau uint16_t ahci_vid; 81887d793aSSepherosa Ziehau uint16_t ahci_did; 82c7f4c6e4SSepherosa Ziehau int ahci_rev; 83887d793aSSepherosa Ziehau }; 84887d793aSSepherosa Ziehau 85887d793aSSepherosa Ziehau static const struct ahci_pciid ahci_msi_blacklist[] = { 86c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA, -1 }, 87c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_AHCI, -1 }, 88c7f4c6e4SSepherosa Ziehau 89c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, -1 }, 90c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145, -1 }, 91c7f4c6e4SSepherosa Ziehau 92c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 0xa1 }, 93c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 0xa1 }, 94c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 0xa1 }, 95c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 0xa1 }, 96c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_5, 0xa1 }, 97c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_6, 0xa1 }, 98c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_7, 0xa1 }, 99c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_8, 0xa1 }, 100c7f4c6e4SSepherosa Ziehau 101c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 0xa2 }, 102c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 0xa2 }, 103c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 0xa2 }, 104c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 0xa2 }, 105c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_5, 0xa2 }, 106c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_6, 0xa2 }, 107c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_7, 0xa2 }, 108c7f4c6e4SSepherosa Ziehau { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_8, 0xa2 } 109887d793aSSepherosa Ziehau }; 110887d793aSSepherosa Ziehau 1119783883aSSepherosa Ziehau static int ahci_msi_enable = 1; 1129783883aSSepherosa Ziehau TUNABLE_INT("hw.ahci.msi.enable", &ahci_msi_enable); 1139783883aSSepherosa Ziehau 114258223a3SMatthew Dillon /* 115258223a3SMatthew Dillon * Match during probe and attach. The device does not yet have a softc. 116258223a3SMatthew Dillon */ 117258223a3SMatthew Dillon const struct ahci_device * 118258223a3SMatthew Dillon ahci_lookup_device(device_t dev) 119258223a3SMatthew Dillon { 120258223a3SMatthew Dillon const struct ahci_device *ad; 121258223a3SMatthew Dillon u_int16_t vendor = pci_get_vendor(dev); 122258223a3SMatthew Dillon u_int16_t product = pci_get_device(dev); 123258223a3SMatthew Dillon u_int8_t class = pci_get_class(dev); 124258223a3SMatthew Dillon u_int8_t subclass = pci_get_subclass(dev); 125258223a3SMatthew Dillon u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1); 126e95151e4SMatthew Dillon int is_ahci; 127258223a3SMatthew Dillon 128e95151e4SMatthew Dillon /* 129e95151e4SMatthew Dillon * Generally speaking if the pci device does not identify as 130e95151e4SMatthew Dillon * AHCI we skip it. 131e95151e4SMatthew Dillon */ 132e95151e4SMatthew Dillon if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA && 133e95151e4SMatthew Dillon progif == PCIP_STORAGE_SATA_AHCI_1_0) { 134e95151e4SMatthew Dillon is_ahci = 1; 135e95151e4SMatthew Dillon } else { 136e95151e4SMatthew Dillon is_ahci = 0; 137e95151e4SMatthew Dillon } 13812feb904SMatthew Dillon 139258223a3SMatthew Dillon for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) { 140258223a3SMatthew Dillon if (ad->ad_vendor == vendor && ad->ad_product == product) 141258223a3SMatthew Dillon return (ad); 142258223a3SMatthew Dillon } 143258223a3SMatthew Dillon 144258223a3SMatthew Dillon /* 145258223a3SMatthew Dillon * Last ad is the default match if the PCI device matches SATA. 146258223a3SMatthew Dillon */ 147e95151e4SMatthew Dillon if (is_ahci == 0) 148e95151e4SMatthew Dillon ad = NULL; 149258223a3SMatthew Dillon return (ad); 150258223a3SMatthew Dillon } 151258223a3SMatthew Dillon 152258223a3SMatthew Dillon /* 153258223a3SMatthew Dillon * Attach functions. They all eventually fall through to ahci_pci_attach(). 154258223a3SMatthew Dillon */ 155258223a3SMatthew Dillon static int 156258223a3SMatthew Dillon ahci_vt8251_attach(device_t dev) 157258223a3SMatthew Dillon { 158258223a3SMatthew Dillon struct ahci_softc *sc = device_get_softc(dev); 159258223a3SMatthew Dillon 160258223a3SMatthew Dillon sc->sc_flags |= AHCI_F_NO_NCQ; 161258223a3SMatthew Dillon return (ahci_pci_attach(dev)); 162258223a3SMatthew Dillon } 163258223a3SMatthew Dillon 164258223a3SMatthew Dillon static int 165258223a3SMatthew Dillon ahci_ati_sb600_attach(device_t dev) 166258223a3SMatthew Dillon { 167258223a3SMatthew Dillon struct ahci_softc *sc = device_get_softc(dev); 168258223a3SMatthew Dillon pcireg_t magic; 169258223a3SMatthew Dillon u_int8_t subclass = pci_get_subclass(dev); 170258223a3SMatthew Dillon u_int8_t revid; 171258223a3SMatthew Dillon 172258223a3SMatthew Dillon if (subclass == PCIS_STORAGE_IDE) { 173258223a3SMatthew Dillon revid = pci_read_config(dev, PCIR_REVID, 1); 174258223a3SMatthew Dillon magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4); 175258223a3SMatthew Dillon pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 176258223a3SMatthew Dillon magic | AHCI_PCI_ATI_SB600_LOCKED, 4); 177258223a3SMatthew Dillon pci_write_config(dev, PCIR_REVID, 178258223a3SMatthew Dillon (PCIC_STORAGE << 24) | 179258223a3SMatthew Dillon (PCIS_STORAGE_SATA << 16) | 180258223a3SMatthew Dillon (PCIP_STORAGE_SATA_AHCI_1_0 << 8) | 181258223a3SMatthew Dillon revid, 4); 182258223a3SMatthew Dillon pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4); 183258223a3SMatthew Dillon } 184258223a3SMatthew Dillon 185258223a3SMatthew Dillon sc->sc_flags |= AHCI_F_IGN_FR; 186258223a3SMatthew Dillon return (ahci_pci_attach(dev)); 187258223a3SMatthew Dillon } 188258223a3SMatthew Dillon 189258223a3SMatthew Dillon static int 190258223a3SMatthew Dillon ahci_nvidia_mcp_attach(device_t dev) 191258223a3SMatthew Dillon { 192258223a3SMatthew Dillon struct ahci_softc *sc = device_get_softc(dev); 193258223a3SMatthew Dillon 194258223a3SMatthew Dillon sc->sc_flags |= AHCI_F_IGN_FR; 195258223a3SMatthew Dillon return (ahci_pci_attach(dev)); 196258223a3SMatthew Dillon } 197258223a3SMatthew Dillon 198258223a3SMatthew Dillon static int 199258223a3SMatthew Dillon ahci_pci_attach(device_t dev) 200258223a3SMatthew Dillon { 201258223a3SMatthew Dillon struct ahci_softc *sc = device_get_softc(dev); 202f4553de1SMatthew Dillon struct ahci_port *ap; 203258223a3SMatthew Dillon const char *gen; 204887d793aSSepherosa Ziehau uint16_t vid, did; 2054b450139SMatthew Dillon u_int32_t pi, reg; 2064b450139SMatthew Dillon u_int32_t cap, cap2; 2079783883aSSepherosa Ziehau u_int irq_flags; 208258223a3SMatthew Dillon bus_addr_t addr; 2094b450139SMatthew Dillon int i, error, msi_enable, rev, fbs; 210258223a3SMatthew Dillon const char *revision; 211*e20b81f0SMatthew Dillon char revbuf[32]; 212258223a3SMatthew Dillon 21312feb904SMatthew Dillon if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) { 21477f3425bSMatthew Dillon device_printf(dev, "BIOS disabled PCI interrupt, " 21577f3425bSMatthew Dillon "re-enabling\n"); 21612feb904SMatthew Dillon pci_write_config(dev, PCIR_COMMAND, 21712feb904SMatthew Dillon pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 21812feb904SMatthew Dillon } 21912feb904SMatthew Dillon 2209783883aSSepherosa Ziehau sc->sc_dev = dev; 22112feb904SMatthew Dillon 222258223a3SMatthew Dillon /* 223258223a3SMatthew Dillon * Map the AHCI controller's IRQ and BAR(5) (hardware registers) 224258223a3SMatthew Dillon */ 225887d793aSSepherosa Ziehau 226887d793aSSepherosa Ziehau msi_enable = ahci_msi_enable; 227887d793aSSepherosa Ziehau 228887d793aSSepherosa Ziehau vid = pci_get_vendor(dev); 229887d793aSSepherosa Ziehau did = pci_get_device(dev); 230c7f4c6e4SSepherosa Ziehau rev = pci_get_revid(dev); 231887d793aSSepherosa Ziehau for (i = 0; i < NELEM(ahci_msi_blacklist); ++i) { 232c7f4c6e4SSepherosa Ziehau const struct ahci_pciid *id = &ahci_msi_blacklist[i]; 233c7f4c6e4SSepherosa Ziehau 234c7f4c6e4SSepherosa Ziehau if (vid == id->ahci_vid && did == id->ahci_did) { 235c7f4c6e4SSepherosa Ziehau if (id->ahci_rev < 0 || id->ahci_rev == rev) { 236887d793aSSepherosa Ziehau msi_enable = 0; 237887d793aSSepherosa Ziehau break; 238887d793aSSepherosa Ziehau } 239887d793aSSepherosa Ziehau } 240c7f4c6e4SSepherosa Ziehau } 241887d793aSSepherosa Ziehau 242887d793aSSepherosa Ziehau sc->sc_irq_type = pci_alloc_1intr(dev, msi_enable, 2437fb43956SSepherosa Ziehau &sc->sc_rid_irq, &irq_flags); 2449783883aSSepherosa Ziehau 245258223a3SMatthew Dillon sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq, 2469783883aSSepherosa Ziehau irq_flags); 247258223a3SMatthew Dillon if (sc->sc_irq == NULL) { 248258223a3SMatthew Dillon device_printf(dev, "unable to map interrupt\n"); 249258223a3SMatthew Dillon ahci_pci_detach(dev); 250258223a3SMatthew Dillon return (ENXIO); 251258223a3SMatthew Dillon } 252258223a3SMatthew Dillon 253258223a3SMatthew Dillon /* 254258223a3SMatthew Dillon * When mapping the register window store the tag and handle 255258223a3SMatthew Dillon * separately so we can use the tag with per-port bus handle 256258223a3SMatthew Dillon * sub-spaces. 257258223a3SMatthew Dillon */ 258258223a3SMatthew Dillon sc->sc_rid_regs = PCIR_BAR(5); 259258223a3SMatthew Dillon sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 260258223a3SMatthew Dillon &sc->sc_rid_regs, RF_ACTIVE); 261258223a3SMatthew Dillon if (sc->sc_regs == NULL) { 262258223a3SMatthew Dillon device_printf(dev, "unable to map registers\n"); 263258223a3SMatthew Dillon ahci_pci_detach(dev); 264258223a3SMatthew Dillon return (ENXIO); 265258223a3SMatthew Dillon } 266258223a3SMatthew Dillon sc->sc_iot = rman_get_bustag(sc->sc_regs); 267258223a3SMatthew Dillon sc->sc_ioh = rman_get_bushandle(sc->sc_regs); 268258223a3SMatthew Dillon 269258223a3SMatthew Dillon /* 270258223a3SMatthew Dillon * Initialize the chipset and then set the interrupt vector up 271258223a3SMatthew Dillon */ 272258223a3SMatthew Dillon error = ahci_init(sc); 273258223a3SMatthew Dillon if (error) { 274258223a3SMatthew Dillon ahci_pci_detach(dev); 275258223a3SMatthew Dillon return (ENXIO); 276258223a3SMatthew Dillon } 277258223a3SMatthew Dillon 278258223a3SMatthew Dillon /* 279258223a3SMatthew Dillon * Get the AHCI capabilities and max number of concurrent 2804b450139SMatthew Dillon * command tags and set up the DMA tags. Adjust the saved 2814b450139SMatthew Dillon * sc_cap according to override flags. 282258223a3SMatthew Dillon */ 2834b450139SMatthew Dillon cap = sc->sc_cap = ahci_read(sc, AHCI_REG_CAP); 284258223a3SMatthew Dillon if (sc->sc_flags & AHCI_F_NO_NCQ) 2854b450139SMatthew Dillon sc->sc_cap &= ~AHCI_REG_CAP_SNCQ; 2864b450139SMatthew Dillon if (sc->sc_flags & AHCI_F_FORCE_FBSS) 2874b450139SMatthew Dillon sc->sc_cap |= AHCI_REG_CAP_FBSS; 2881067474aSMatthew Dillon 2891067474aSMatthew Dillon /* 2901067474aSMatthew Dillon * We assume at least 4 commands. 2911067474aSMatthew Dillon */ 292258223a3SMatthew Dillon sc->sc_ncmds = AHCI_REG_CAP_NCS(cap); 2931067474aSMatthew Dillon if (sc->sc_ncmds < 4) { 2941067474aSMatthew Dillon device_printf(dev, "NCS must probe a value >= 4\n"); 2951067474aSMatthew Dillon ahci_pci_detach(dev); 2961067474aSMatthew Dillon return (ENXIO); 2971067474aSMatthew Dillon } 298258223a3SMatthew Dillon 299258223a3SMatthew Dillon addr = (cap & AHCI_REG_CAP_S64A) ? 300258223a3SMatthew Dillon BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT; 301258223a3SMatthew Dillon 302258223a3SMatthew Dillon /* 303258223a3SMatthew Dillon * DMA tags for allocation of DMA memory buffers, lists, and so 304258223a3SMatthew Dillon * forth. These are typically per-port. 3054b450139SMatthew Dillon * 3064b450139SMatthew Dillon * When FIS-based switching is supported we need a rfis for 3074b450139SMatthew Dillon * each target (4K total). The spec also requires 4K alignment 3084b450139SMatthew Dillon * for this case. 309258223a3SMatthew Dillon */ 3104b450139SMatthew Dillon fbs = (cap & AHCI_REG_CAP_FBSS) ? 16 : 1; 311258223a3SMatthew Dillon error = 0; 3124b450139SMatthew Dillon 313258223a3SMatthew Dillon error += bus_dma_tag_create( 314258223a3SMatthew Dillon NULL, /* parent tag */ 3154b450139SMatthew Dillon 256 * fbs, /* alignment */ 316258223a3SMatthew Dillon PAGE_SIZE, /* boundary */ 317258223a3SMatthew Dillon addr, /* loaddr? */ 318258223a3SMatthew Dillon BUS_SPACE_MAXADDR, /* hiaddr */ 319258223a3SMatthew Dillon NULL, /* filter */ 320258223a3SMatthew Dillon NULL, /* filterarg */ 3214b450139SMatthew Dillon sizeof(struct ahci_rfis) * fbs, /* [max]size */ 322258223a3SMatthew Dillon 1, /* maxsegs */ 3234b450139SMatthew Dillon sizeof(struct ahci_rfis) * fbs, /* maxsegsz */ 324258223a3SMatthew Dillon 0, /* flags */ 325258223a3SMatthew Dillon &sc->sc_tag_rfis); /* return tag */ 326258223a3SMatthew Dillon 327258223a3SMatthew Dillon error += bus_dma_tag_create( 328258223a3SMatthew Dillon NULL, /* parent tag */ 329258223a3SMatthew Dillon 32, /* alignment */ 330258223a3SMatthew Dillon 4096 * 1024, /* boundary */ 331258223a3SMatthew Dillon addr, /* loaddr? */ 332258223a3SMatthew Dillon BUS_SPACE_MAXADDR, /* hiaddr */ 333258223a3SMatthew Dillon NULL, /* filter */ 334258223a3SMatthew Dillon NULL, /* filterarg */ 335258223a3SMatthew Dillon sc->sc_ncmds * sizeof(struct ahci_cmd_hdr), 336258223a3SMatthew Dillon 1, /* maxsegs */ 337258223a3SMatthew Dillon sc->sc_ncmds * sizeof(struct ahci_cmd_hdr), 338258223a3SMatthew Dillon 0, /* flags */ 339258223a3SMatthew Dillon &sc->sc_tag_cmdh); /* return tag */ 340258223a3SMatthew Dillon 341258223a3SMatthew Dillon /* 342258223a3SMatthew Dillon * NOTE: ahci_cmd_table is sized to a power of 2 343258223a3SMatthew Dillon */ 344258223a3SMatthew Dillon error += bus_dma_tag_create( 345258223a3SMatthew Dillon NULL, /* parent tag */ 346258223a3SMatthew Dillon sizeof(struct ahci_cmd_table), /* alignment */ 347258223a3SMatthew Dillon 4096 * 1024, /* boundary */ 348258223a3SMatthew Dillon addr, /* loaddr? */ 349258223a3SMatthew Dillon BUS_SPACE_MAXADDR, /* hiaddr */ 350258223a3SMatthew Dillon NULL, /* filter */ 351258223a3SMatthew Dillon NULL, /* filterarg */ 352258223a3SMatthew Dillon sc->sc_ncmds * sizeof(struct ahci_cmd_table), 353258223a3SMatthew Dillon 1, /* maxsegs */ 354258223a3SMatthew Dillon sc->sc_ncmds * sizeof(struct ahci_cmd_table), 355258223a3SMatthew Dillon 0, /* flags */ 356258223a3SMatthew Dillon &sc->sc_tag_cmdt); /* return tag */ 357258223a3SMatthew Dillon 358258223a3SMatthew Dillon /* 359258223a3SMatthew Dillon * The data tag is used for later dmamaps and not immediately 360258223a3SMatthew Dillon * allocated. 361258223a3SMatthew Dillon */ 362258223a3SMatthew Dillon error += bus_dma_tag_create( 363258223a3SMatthew Dillon NULL, /* parent tag */ 364258223a3SMatthew Dillon 4, /* alignment */ 365258223a3SMatthew Dillon 0, /* boundary */ 366258223a3SMatthew Dillon addr, /* loaddr? */ 367258223a3SMatthew Dillon BUS_SPACE_MAXADDR, /* hiaddr */ 368258223a3SMatthew Dillon NULL, /* filter */ 369258223a3SMatthew Dillon NULL, /* filterarg */ 370258223a3SMatthew Dillon 4096 * 1024, /* maxiosize */ 371258223a3SMatthew Dillon AHCI_MAX_PRDT, /* maxsegs */ 372258223a3SMatthew Dillon 65536, /* maxsegsz */ 373258223a3SMatthew Dillon 0, /* flags */ 374258223a3SMatthew Dillon &sc->sc_tag_data); /* return tag */ 375258223a3SMatthew Dillon 376258223a3SMatthew Dillon if (error) { 377258223a3SMatthew Dillon device_printf(dev, "unable to create dma tags\n"); 378258223a3SMatthew Dillon ahci_pci_detach(dev); 379258223a3SMatthew Dillon return (ENXIO); 380258223a3SMatthew Dillon } 381258223a3SMatthew Dillon 382258223a3SMatthew Dillon switch (cap & AHCI_REG_CAP_ISS) { 383258223a3SMatthew Dillon case AHCI_REG_CAP_ISS_G1: 384258223a3SMatthew Dillon gen = "1 (1.5Gbps)"; 385258223a3SMatthew Dillon break; 3868986d351SMatthew Dillon case AHCI_REG_CAP_ISS_G2: 3878986d351SMatthew Dillon gen = "2 (3Gbps)"; 3888986d351SMatthew Dillon break; 3898986d351SMatthew Dillon case AHCI_REG_CAP_ISS_G3: 3908986d351SMatthew Dillon gen = "3 (6Gbps)"; 391258223a3SMatthew Dillon break; 392258223a3SMatthew Dillon default: 393258223a3SMatthew Dillon gen = "unknown"; 394258223a3SMatthew Dillon break; 395258223a3SMatthew Dillon } 396258223a3SMatthew Dillon 397258223a3SMatthew Dillon /* check the revision */ 398258223a3SMatthew Dillon reg = ahci_read(sc, AHCI_REG_VS); 3994b450139SMatthew Dillon 400*e20b81f0SMatthew Dillon if (reg & 0x0000FF) { 401*e20b81f0SMatthew Dillon ksnprintf(revbuf, sizeof(revbuf), "AHCI %d.%d.%d", 402*e20b81f0SMatthew Dillon (reg >> 16), (uint8_t)(reg >> 8), (uint8_t)reg); 403*e20b81f0SMatthew Dillon } else { 404*e20b81f0SMatthew Dillon ksnprintf(revbuf, sizeof(revbuf), "AHCI %d.%d", 405*e20b81f0SMatthew Dillon (reg >> 16), (uint8_t)(reg >> 8)); 406258223a3SMatthew Dillon } 407*e20b81f0SMatthew Dillon revision = kstrdup(revbuf, M_DEVBUF); 4084b450139SMatthew Dillon sc->sc_vers = reg; 409258223a3SMatthew Dillon 4104b450139SMatthew Dillon if (reg >= AHCI_REG_VS_1_3) { 4114b450139SMatthew Dillon cap2 = ahci_read(sc, AHCI_REG_CAP2); 412258223a3SMatthew Dillon device_printf(dev, 4134b450139SMatthew Dillon "%s cap 0x%b cap2 0x%b, %d ports, " 4144b450139SMatthew Dillon "%d tags/port, gen %s\n", 4154b450139SMatthew Dillon revision, 4164b450139SMatthew Dillon cap, AHCI_FMT_CAP, 4174b450139SMatthew Dillon cap2, AHCI_FMT_CAP2, 4184b450139SMatthew Dillon AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen); 4194b450139SMatthew Dillon } else { 4204b450139SMatthew Dillon cap2 = 0; 4214b450139SMatthew Dillon device_printf(dev, 4224b450139SMatthew Dillon "%s cap 0x%b, %d ports, " 4234b450139SMatthew Dillon "%d tags/port, gen %s\n", 424258223a3SMatthew Dillon revision, 425258223a3SMatthew Dillon cap, AHCI_FMT_CAP, 426258223a3SMatthew Dillon AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen); 4274b450139SMatthew Dillon } 4284b450139SMatthew Dillon sc->sc_cap2 = cap2; 429258223a3SMatthew Dillon 430258223a3SMatthew Dillon pi = ahci_read(sc, AHCI_REG_PI); 431258223a3SMatthew Dillon DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n", 432258223a3SMatthew Dillon DEVNAME(sc), pi); 433258223a3SMatthew Dillon 434258223a3SMatthew Dillon #ifdef AHCI_COALESCE 435258223a3SMatthew Dillon /* Naive coalescing support - enable for all ports. */ 436258223a3SMatthew Dillon if (cap & AHCI_REG_CAP_CCCS) { 437258223a3SMatthew Dillon u_int16_t ccc_timeout = 20; 438258223a3SMatthew Dillon u_int8_t ccc_numcomplete = 12; 439258223a3SMatthew Dillon u_int32_t ccc_ctl; 440258223a3SMatthew Dillon 441258223a3SMatthew Dillon /* disable coalescing during reconfiguration. */ 442258223a3SMatthew Dillon ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL); 443258223a3SMatthew Dillon ccc_ctl &= ~0x00000001; 444258223a3SMatthew Dillon ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl); 445258223a3SMatthew Dillon 446258223a3SMatthew Dillon sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl); 447258223a3SMatthew Dillon if (pi & sc->sc_ccc_mask) { 448258223a3SMatthew Dillon /* A conflict with the implemented port list? */ 449258223a3SMatthew Dillon printf("%s: coalescing interrupt/implemented port list " 450258223a3SMatthew Dillon "conflict, PI: %08x, ccc_mask: %08x\n", 451258223a3SMatthew Dillon DEVNAME(sc), pi, sc->sc_ccc_mask); 452258223a3SMatthew Dillon sc->sc_ccc_mask = 0; 453258223a3SMatthew Dillon goto noccc; 454258223a3SMatthew Dillon } 455258223a3SMatthew Dillon 456258223a3SMatthew Dillon /* ahci_port_start will enable each port when it starts. */ 457258223a3SMatthew Dillon sc->sc_ccc_ports = pi; 458258223a3SMatthew Dillon sc->sc_ccc_ports_cur = 0; 459258223a3SMatthew Dillon 460258223a3SMatthew Dillon /* program thresholds and enable overall coalescing. */ 461258223a3SMatthew Dillon ccc_ctl &= ~0xffffff00; 462258223a3SMatthew Dillon ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8); 463258223a3SMatthew Dillon ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl); 464258223a3SMatthew Dillon ahci_write(sc, AHCI_REG_CCC_PORTS, 0); 465258223a3SMatthew Dillon ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1); 466258223a3SMatthew Dillon } 467258223a3SMatthew Dillon noccc: 468258223a3SMatthew Dillon #endif 469258223a3SMatthew Dillon /* 470258223a3SMatthew Dillon * Allocate per-port resources 471258223a3SMatthew Dillon * 472258223a3SMatthew Dillon * Ignore attach errors, leave the port intact for 473258223a3SMatthew Dillon * rescan and continue the loop. 474f4553de1SMatthew Dillon * 475f4553de1SMatthew Dillon * All ports are attached in parallel but the CAM scan-bus 476f4553de1SMatthew Dillon * is held up until all ports are attached so we get a deterministic 477f4553de1SMatthew Dillon * order. 478258223a3SMatthew Dillon */ 479258223a3SMatthew Dillon for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) { 480258223a3SMatthew Dillon if ((pi & (1 << i)) == 0) { 481258223a3SMatthew Dillon /* dont allocate stuff if the port isnt implemented */ 482258223a3SMatthew Dillon continue; 483258223a3SMatthew Dillon } 484258223a3SMatthew Dillon error = ahci_port_alloc(sc, i); 485258223a3SMatthew Dillon } 486258223a3SMatthew Dillon 487258223a3SMatthew Dillon /* 488258223a3SMatthew Dillon * Setup the interrupt vector and enable interrupts. Note that 489258223a3SMatthew Dillon * since the irq may be shared we do not set it up until we are 490258223a3SMatthew Dillon * ready to go. 491258223a3SMatthew Dillon */ 492258223a3SMatthew Dillon if (error == 0) { 493fb00c6edSMatthew Dillon error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, 494fb00c6edSMatthew Dillon ahci_intr, sc, 495f4553de1SMatthew Dillon &sc->sc_irq_handle, NULL); 496258223a3SMatthew Dillon } 497258223a3SMatthew Dillon 498258223a3SMatthew Dillon if (error) { 499258223a3SMatthew Dillon device_printf(dev, "unable to install interrupt\n"); 500258223a3SMatthew Dillon ahci_pci_detach(dev); 501258223a3SMatthew Dillon return (ENXIO); 502258223a3SMatthew Dillon } 503f4553de1SMatthew Dillon 504f4553de1SMatthew Dillon /* 505e8cf3f55SMatthew Dillon * Before marking the sc as good, which allows the interrupt 506e8cf3f55SMatthew Dillon * subsystem to operate on the ports, wait for all the port threads 507e8cf3f55SMatthew Dillon * to get past their initial pre-probe init. Otherwise an interrupt 508e8cf3f55SMatthew Dillon * may try to process the port before it has been initialized. 509e8cf3f55SMatthew Dillon */ 510e8cf3f55SMatthew Dillon for (i = 0; i < AHCI_MAX_PORTS; i++) { 511e8cf3f55SMatthew Dillon if ((ap = sc->sc_ports[i]) != NULL) { 512e8cf3f55SMatthew Dillon while (ap->ap_signal & AP_SIGF_THREAD_SYNC) 513e8cf3f55SMatthew Dillon tsleep(&ap->ap_signal, 0, "ahprb1", hz); 514e8cf3f55SMatthew Dillon } 515e8cf3f55SMatthew Dillon } 516e8cf3f55SMatthew Dillon 517e8cf3f55SMatthew Dillon /* 518f4553de1SMatthew Dillon * Master interrupt enable, and call ahci_intr() in case we race 519f4553de1SMatthew Dillon * our AHCI_F_INT_GOOD flag. 520f4553de1SMatthew Dillon */ 521f4553de1SMatthew Dillon crit_enter(); 522258223a3SMatthew Dillon ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE); 523f4553de1SMatthew Dillon sc->sc_flags |= AHCI_F_INT_GOOD; 524f4553de1SMatthew Dillon crit_exit(); 525f4553de1SMatthew Dillon ahci_intr(sc); 526f4553de1SMatthew Dillon 527f4553de1SMatthew Dillon /* 528f4553de1SMatthew Dillon * All ports are probing in parallel. Wait for them to finish 529f4553de1SMatthew Dillon * and then issue the cam attachment and bus scan serially so 530f4553de1SMatthew Dillon * the 'da' assignments are deterministic. 531f4553de1SMatthew Dillon */ 532f4553de1SMatthew Dillon for (i = 0; i < AHCI_MAX_PORTS; i++) { 533f4553de1SMatthew Dillon if ((ap = sc->sc_ports[i]) != NULL) { 534f4553de1SMatthew Dillon while (ap->ap_signal & AP_SIGF_INIT) 535e8cf3f55SMatthew Dillon tsleep(&ap->ap_signal, 0, "ahprb2", hz); 536831bc9e3SMatthew Dillon ahci_os_lock_port(ap); 537f4553de1SMatthew Dillon if (ahci_cam_attach(ap) == 0) { 538f4553de1SMatthew Dillon ahci_cam_changed(ap, NULL, -1); 539831bc9e3SMatthew Dillon ahci_os_unlock_port(ap); 540f4553de1SMatthew Dillon while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) { 541f4553de1SMatthew Dillon tsleep(&ap->ap_flags, 0, "ahprb2", hz); 542f4553de1SMatthew Dillon } 543831bc9e3SMatthew Dillon } else { 544831bc9e3SMatthew Dillon ahci_os_unlock_port(ap); 545f4553de1SMatthew Dillon } 546f4553de1SMatthew Dillon } 547f4553de1SMatthew Dillon } 548258223a3SMatthew Dillon 549258223a3SMatthew Dillon return(0); 550258223a3SMatthew Dillon } 551258223a3SMatthew Dillon 552258223a3SMatthew Dillon /* 553258223a3SMatthew Dillon * Device unload / detachment 554258223a3SMatthew Dillon */ 555258223a3SMatthew Dillon static int 556258223a3SMatthew Dillon ahci_pci_detach(device_t dev) 557258223a3SMatthew Dillon { 558258223a3SMatthew Dillon struct ahci_softc *sc = device_get_softc(dev); 559258223a3SMatthew Dillon struct ahci_port *ap; 560258223a3SMatthew Dillon int i; 561258223a3SMatthew Dillon 562258223a3SMatthew Dillon /* 563258223a3SMatthew Dillon * Disable the controller and de-register the interrupt, if any. 564258223a3SMatthew Dillon * 565f4553de1SMatthew Dillon * XXX interlock last interrupt? 566258223a3SMatthew Dillon */ 567f4553de1SMatthew Dillon sc->sc_flags &= ~AHCI_F_INT_GOOD; 568f4553de1SMatthew Dillon if (sc->sc_regs) 569258223a3SMatthew Dillon ahci_write(sc, AHCI_REG_GHC, 0); 570f4553de1SMatthew Dillon 571258223a3SMatthew Dillon if (sc->sc_irq_handle) { 572258223a3SMatthew Dillon bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle); 573258223a3SMatthew Dillon sc->sc_irq_handle = NULL; 574258223a3SMatthew Dillon } 575258223a3SMatthew Dillon 576258223a3SMatthew Dillon /* 577258223a3SMatthew Dillon * Free port structures and DMA memory 578258223a3SMatthew Dillon */ 579258223a3SMatthew Dillon for (i = 0; i < AHCI_MAX_PORTS; i++) { 580258223a3SMatthew Dillon ap = sc->sc_ports[i]; 581258223a3SMatthew Dillon if (ap) { 582258223a3SMatthew Dillon ahci_cam_detach(ap); 583258223a3SMatthew Dillon ahci_port_free(sc, i); 584258223a3SMatthew Dillon } 585258223a3SMatthew Dillon } 586258223a3SMatthew Dillon 587258223a3SMatthew Dillon /* 588258223a3SMatthew Dillon * Clean up the bus space 589258223a3SMatthew Dillon */ 590258223a3SMatthew Dillon if (sc->sc_irq) { 591258223a3SMatthew Dillon bus_release_resource(dev, SYS_RES_IRQ, 592258223a3SMatthew Dillon sc->sc_rid_irq, sc->sc_irq); 593258223a3SMatthew Dillon sc->sc_irq = NULL; 594258223a3SMatthew Dillon } 5959783883aSSepherosa Ziehau 5967fb43956SSepherosa Ziehau if (sc->sc_irq_type == PCI_INTR_TYPE_MSI) 5979783883aSSepherosa Ziehau pci_release_msi(dev); 5989783883aSSepherosa Ziehau 599258223a3SMatthew Dillon if (sc->sc_regs) { 600258223a3SMatthew Dillon bus_release_resource(dev, SYS_RES_MEMORY, 601258223a3SMatthew Dillon sc->sc_rid_regs, sc->sc_regs); 602258223a3SMatthew Dillon sc->sc_regs = NULL; 603258223a3SMatthew Dillon } 604258223a3SMatthew Dillon 605258223a3SMatthew Dillon if (sc->sc_tag_rfis) { 606258223a3SMatthew Dillon bus_dma_tag_destroy(sc->sc_tag_rfis); 607258223a3SMatthew Dillon sc->sc_tag_rfis = NULL; 608258223a3SMatthew Dillon } 609258223a3SMatthew Dillon if (sc->sc_tag_cmdh) { 610258223a3SMatthew Dillon bus_dma_tag_destroy(sc->sc_tag_cmdh); 611258223a3SMatthew Dillon sc->sc_tag_cmdh = NULL; 612258223a3SMatthew Dillon } 613258223a3SMatthew Dillon if (sc->sc_tag_cmdt) { 614258223a3SMatthew Dillon bus_dma_tag_destroy(sc->sc_tag_cmdt); 615258223a3SMatthew Dillon sc->sc_tag_cmdt = NULL; 616258223a3SMatthew Dillon } 617258223a3SMatthew Dillon if (sc->sc_tag_data) { 618258223a3SMatthew Dillon bus_dma_tag_destroy(sc->sc_tag_data); 619258223a3SMatthew Dillon sc->sc_tag_data = NULL; 620258223a3SMatthew Dillon } 621258223a3SMatthew Dillon 622258223a3SMatthew Dillon return (0); 623258223a3SMatthew Dillon } 624