1 /* 2 * (MPSAFE) 3 * 4 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * 19 * Copyright (c) 2009 The DragonFly Project. All rights reserved. 20 * 21 * This code is derived from software contributed to The DragonFly Project 22 * by Matthew Dillon <dillon@backplane.com> 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 28 * 1. Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * 2. Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in 32 * the documentation and/or other materials provided with the 33 * distribution. 34 * 3. Neither the name of The DragonFly Project nor the names of its 35 * contributors may be used to endorse or promote products derived 36 * from this software without specific, prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 39 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 41 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 42 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 43 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 48 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 49 * SUCH DAMAGE. 50 * 51 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $ 52 */ 53 54 #include "ahci.h" 55 56 static int ahci_vt8251_attach(device_t); 57 static int ahci_ati_sb600_attach(device_t); 58 static int ahci_nvidia_mcp_attach(device_t); 59 static int ahci_pci_attach(device_t); 60 static int ahci_pci_detach(device_t); 61 62 static const struct ahci_device ahci_devices[] = { 63 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA, 64 ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" }, 65 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA, 66 ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" }, 67 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 68 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" }, 69 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1, 70 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" }, 71 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 72 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" }, 73 { 0, 0, 74 ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" } 75 }; 76 77 /* 78 * Match during probe and attach. The device does not yet have a softc. 79 */ 80 const struct ahci_device * 81 ahci_lookup_device(device_t dev) 82 { 83 const struct ahci_device *ad; 84 u_int16_t vendor = pci_get_vendor(dev); 85 u_int16_t product = pci_get_device(dev); 86 u_int8_t class = pci_get_class(dev); 87 u_int8_t subclass = pci_get_subclass(dev); 88 u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1); 89 int is_ahci; 90 91 /* 92 * Generally speaking if the pci device does not identify as 93 * AHCI we skip it. 94 */ 95 if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA && 96 progif == PCIP_STORAGE_SATA_AHCI_1_0) { 97 is_ahci = 1; 98 } else { 99 is_ahci = 0; 100 } 101 102 for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) { 103 if (ad->ad_vendor == vendor && ad->ad_product == product) 104 return (ad); 105 } 106 107 /* 108 * Last ad is the default match if the PCI device matches SATA. 109 */ 110 if (is_ahci == 0) 111 ad = NULL; 112 return (ad); 113 } 114 115 /* 116 * Attach functions. They all eventually fall through to ahci_pci_attach(). 117 */ 118 static int 119 ahci_vt8251_attach(device_t dev) 120 { 121 struct ahci_softc *sc = device_get_softc(dev); 122 123 sc->sc_flags |= AHCI_F_NO_NCQ; 124 return (ahci_pci_attach(dev)); 125 } 126 127 static int 128 ahci_ati_sb600_attach(device_t dev) 129 { 130 struct ahci_softc *sc = device_get_softc(dev); 131 pcireg_t magic; 132 u_int8_t subclass = pci_get_subclass(dev); 133 u_int8_t revid; 134 135 if (subclass == PCIS_STORAGE_IDE) { 136 revid = pci_read_config(dev, PCIR_REVID, 1); 137 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4); 138 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 139 magic | AHCI_PCI_ATI_SB600_LOCKED, 4); 140 pci_write_config(dev, PCIR_REVID, 141 (PCIC_STORAGE << 24) | 142 (PCIS_STORAGE_SATA << 16) | 143 (PCIP_STORAGE_SATA_AHCI_1_0 << 8) | 144 revid, 4); 145 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4); 146 } 147 148 sc->sc_flags |= AHCI_F_IGN_FR; 149 return (ahci_pci_attach(dev)); 150 } 151 152 static int 153 ahci_nvidia_mcp_attach(device_t dev) 154 { 155 struct ahci_softc *sc = device_get_softc(dev); 156 157 sc->sc_flags |= AHCI_F_IGN_FR; 158 return (ahci_pci_attach(dev)); 159 } 160 161 static int 162 ahci_pci_attach(device_t dev) 163 { 164 struct ahci_softc *sc = device_get_softc(dev); 165 struct ahci_port *ap; 166 const char *gen; 167 u_int32_t cap, pi, reg; 168 bus_addr_t addr; 169 int i; 170 int error; 171 const char *revision; 172 173 if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) { 174 device_printf(dev, "BIOS disabled PCI interrupt, " 175 "re-enabling\n"); 176 pci_write_config(dev, PCIR_COMMAND, 177 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 178 } 179 180 181 /* 182 * Map the AHCI controller's IRQ and BAR(5) (hardware registers) 183 */ 184 sc->sc_dev = dev; 185 sc->sc_rid_irq = AHCI_IRQ_RID; 186 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq, 187 RF_SHAREABLE | RF_ACTIVE); 188 if (sc->sc_irq == NULL) { 189 device_printf(dev, "unable to map interrupt\n"); 190 ahci_pci_detach(dev); 191 return (ENXIO); 192 } 193 194 /* 195 * When mapping the register window store the tag and handle 196 * separately so we can use the tag with per-port bus handle 197 * sub-spaces. 198 */ 199 sc->sc_rid_regs = PCIR_BAR(5); 200 sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 201 &sc->sc_rid_regs, RF_ACTIVE); 202 if (sc->sc_regs == NULL) { 203 device_printf(dev, "unable to map registers\n"); 204 ahci_pci_detach(dev); 205 return (ENXIO); 206 } 207 sc->sc_iot = rman_get_bustag(sc->sc_regs); 208 sc->sc_ioh = rman_get_bushandle(sc->sc_regs); 209 210 /* 211 * Initialize the chipset and then set the interrupt vector up 212 */ 213 error = ahci_init(sc); 214 if (error) { 215 ahci_pci_detach(dev); 216 return (ENXIO); 217 } 218 219 /* 220 * Get the AHCI capabilities and max number of concurrent 221 * command tags and set up the DMA tags. 222 */ 223 cap = ahci_read(sc, AHCI_REG_CAP); 224 if (sc->sc_flags & AHCI_F_NO_NCQ) 225 cap &= ~AHCI_REG_CAP_SNCQ; 226 sc->sc_cap = cap; 227 228 /* 229 * We assume at least 4 commands. 230 */ 231 sc->sc_ncmds = AHCI_REG_CAP_NCS(cap); 232 if (sc->sc_ncmds < 4) { 233 device_printf(dev, "NCS must probe a value >= 4\n"); 234 ahci_pci_detach(dev); 235 return (ENXIO); 236 } 237 238 addr = (cap & AHCI_REG_CAP_S64A) ? 239 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT; 240 241 /* 242 * DMA tags for allocation of DMA memory buffers, lists, and so 243 * forth. These are typically per-port. 244 */ 245 error = 0; 246 error += bus_dma_tag_create( 247 NULL, /* parent tag */ 248 256, /* alignment */ 249 PAGE_SIZE, /* boundary */ 250 addr, /* loaddr? */ 251 BUS_SPACE_MAXADDR, /* hiaddr */ 252 NULL, /* filter */ 253 NULL, /* filterarg */ 254 sizeof(struct ahci_rfis), /* [max]size */ 255 1, /* maxsegs */ 256 sizeof(struct ahci_rfis), /* maxsegsz */ 257 0, /* flags */ 258 &sc->sc_tag_rfis); /* return tag */ 259 260 error += bus_dma_tag_create( 261 NULL, /* parent tag */ 262 32, /* alignment */ 263 4096 * 1024, /* boundary */ 264 addr, /* loaddr? */ 265 BUS_SPACE_MAXADDR, /* hiaddr */ 266 NULL, /* filter */ 267 NULL, /* filterarg */ 268 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr), 269 1, /* maxsegs */ 270 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr), 271 0, /* flags */ 272 &sc->sc_tag_cmdh); /* return tag */ 273 274 /* 275 * NOTE: ahci_cmd_table is sized to a power of 2 276 */ 277 error += bus_dma_tag_create( 278 NULL, /* parent tag */ 279 sizeof(struct ahci_cmd_table), /* alignment */ 280 4096 * 1024, /* boundary */ 281 addr, /* loaddr? */ 282 BUS_SPACE_MAXADDR, /* hiaddr */ 283 NULL, /* filter */ 284 NULL, /* filterarg */ 285 sc->sc_ncmds * sizeof(struct ahci_cmd_table), 286 1, /* maxsegs */ 287 sc->sc_ncmds * sizeof(struct ahci_cmd_table), 288 0, /* flags */ 289 &sc->sc_tag_cmdt); /* return tag */ 290 291 /* 292 * The data tag is used for later dmamaps and not immediately 293 * allocated. 294 */ 295 error += bus_dma_tag_create( 296 NULL, /* parent tag */ 297 4, /* alignment */ 298 0, /* boundary */ 299 addr, /* loaddr? */ 300 BUS_SPACE_MAXADDR, /* hiaddr */ 301 NULL, /* filter */ 302 NULL, /* filterarg */ 303 4096 * 1024, /* maxiosize */ 304 AHCI_MAX_PRDT, /* maxsegs */ 305 65536, /* maxsegsz */ 306 0, /* flags */ 307 &sc->sc_tag_data); /* return tag */ 308 309 if (error) { 310 device_printf(dev, "unable to create dma tags\n"); 311 ahci_pci_detach(dev); 312 return (ENXIO); 313 } 314 315 switch (cap & AHCI_REG_CAP_ISS) { 316 case AHCI_REG_CAP_ISS_G1: 317 gen = "1 (1.5Gbps)"; 318 break; 319 case AHCI_REG_CAP_ISS_G1_2: 320 gen = "1 (1.5Gbps) and 2 (3Gbps)"; 321 break; 322 default: 323 gen = "unknown"; 324 break; 325 } 326 327 /* check the revision */ 328 reg = ahci_read(sc, AHCI_REG_VS); 329 switch (reg) { 330 case AHCI_REG_VS_0_95: 331 revision = "AHCI 0.95"; 332 break; 333 case AHCI_REG_VS_1_0: 334 revision = "AHCI 1.0"; 335 break; 336 case AHCI_REG_VS_1_1: 337 revision = "AHCI 1.1"; 338 break; 339 case AHCI_REG_VS_1_2: 340 revision = "AHCI 1.2"; 341 break; 342 default: 343 device_printf(sc->sc_dev, 344 "Warning: Unknown AHCI revision 0x%08x\n", reg); 345 revision = "AHCI <unknown>"; 346 break; 347 } 348 349 device_printf(dev, 350 "%s capabilities 0x%b, %d ports, %d tags/port, gen %s\n", 351 revision, 352 cap, AHCI_FMT_CAP, 353 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen); 354 355 pi = ahci_read(sc, AHCI_REG_PI); 356 DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n", 357 DEVNAME(sc), pi); 358 359 #ifdef AHCI_COALESCE 360 /* Naive coalescing support - enable for all ports. */ 361 if (cap & AHCI_REG_CAP_CCCS) { 362 u_int16_t ccc_timeout = 20; 363 u_int8_t ccc_numcomplete = 12; 364 u_int32_t ccc_ctl; 365 366 /* disable coalescing during reconfiguration. */ 367 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL); 368 ccc_ctl &= ~0x00000001; 369 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl); 370 371 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl); 372 if (pi & sc->sc_ccc_mask) { 373 /* A conflict with the implemented port list? */ 374 printf("%s: coalescing interrupt/implemented port list " 375 "conflict, PI: %08x, ccc_mask: %08x\n", 376 DEVNAME(sc), pi, sc->sc_ccc_mask); 377 sc->sc_ccc_mask = 0; 378 goto noccc; 379 } 380 381 /* ahci_port_start will enable each port when it starts. */ 382 sc->sc_ccc_ports = pi; 383 sc->sc_ccc_ports_cur = 0; 384 385 /* program thresholds and enable overall coalescing. */ 386 ccc_ctl &= ~0xffffff00; 387 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8); 388 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl); 389 ahci_write(sc, AHCI_REG_CCC_PORTS, 0); 390 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1); 391 } 392 noccc: 393 #endif 394 /* 395 * Allocate per-port resources 396 * 397 * Ignore attach errors, leave the port intact for 398 * rescan and continue the loop. 399 * 400 * All ports are attached in parallel but the CAM scan-bus 401 * is held up until all ports are attached so we get a deterministic 402 * order. 403 */ 404 for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) { 405 if ((pi & (1 << i)) == 0) { 406 /* dont allocate stuff if the port isnt implemented */ 407 continue; 408 } 409 error = ahci_port_alloc(sc, i); 410 } 411 412 /* 413 * Setup the interrupt vector and enable interrupts. Note that 414 * since the irq may be shared we do not set it up until we are 415 * ready to go. 416 */ 417 if (error == 0) { 418 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, 419 ahci_intr, sc, 420 &sc->sc_irq_handle, NULL); 421 } 422 423 if (error) { 424 device_printf(dev, "unable to install interrupt\n"); 425 ahci_pci_detach(dev); 426 return (ENXIO); 427 } 428 429 /* 430 * Before marking the sc as good, which allows the interrupt 431 * subsystem to operate on the ports, wait for all the port threads 432 * to get past their initial pre-probe init. Otherwise an interrupt 433 * may try to process the port before it has been initialized. 434 */ 435 for (i = 0; i < AHCI_MAX_PORTS; i++) { 436 if ((ap = sc->sc_ports[i]) != NULL) { 437 while (ap->ap_signal & AP_SIGF_THREAD_SYNC) 438 tsleep(&ap->ap_signal, 0, "ahprb1", hz); 439 } 440 } 441 442 /* 443 * Master interrupt enable, and call ahci_intr() in case we race 444 * our AHCI_F_INT_GOOD flag. 445 */ 446 crit_enter(); 447 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE); 448 sc->sc_flags |= AHCI_F_INT_GOOD; 449 crit_exit(); 450 ahci_intr(sc); 451 452 /* 453 * All ports are probing in parallel. Wait for them to finish 454 * and then issue the cam attachment and bus scan serially so 455 * the 'da' assignments are deterministic. 456 */ 457 for (i = 0; i < AHCI_MAX_PORTS; i++) { 458 if ((ap = sc->sc_ports[i]) != NULL) { 459 while (ap->ap_signal & AP_SIGF_INIT) 460 tsleep(&ap->ap_signal, 0, "ahprb2", hz); 461 ahci_os_lock_port(ap); 462 if (ahci_cam_attach(ap) == 0) { 463 ahci_cam_changed(ap, NULL, -1); 464 ahci_os_unlock_port(ap); 465 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) { 466 tsleep(&ap->ap_flags, 0, "ahprb2", hz); 467 } 468 } else { 469 ahci_os_unlock_port(ap); 470 } 471 } 472 } 473 474 return(0); 475 } 476 477 /* 478 * Device unload / detachment 479 */ 480 static int 481 ahci_pci_detach(device_t dev) 482 { 483 struct ahci_softc *sc = device_get_softc(dev); 484 struct ahci_port *ap; 485 int i; 486 487 /* 488 * Disable the controller and de-register the interrupt, if any. 489 * 490 * XXX interlock last interrupt? 491 */ 492 sc->sc_flags &= ~AHCI_F_INT_GOOD; 493 if (sc->sc_regs) 494 ahci_write(sc, AHCI_REG_GHC, 0); 495 496 if (sc->sc_irq_handle) { 497 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle); 498 sc->sc_irq_handle = NULL; 499 } 500 501 /* 502 * Free port structures and DMA memory 503 */ 504 for (i = 0; i < AHCI_MAX_PORTS; i++) { 505 ap = sc->sc_ports[i]; 506 if (ap) { 507 ahci_cam_detach(ap); 508 ahci_port_free(sc, i); 509 } 510 } 511 512 /* 513 * Clean up the bus space 514 */ 515 if (sc->sc_irq) { 516 bus_release_resource(dev, SYS_RES_IRQ, 517 sc->sc_rid_irq, sc->sc_irq); 518 sc->sc_irq = NULL; 519 } 520 if (sc->sc_regs) { 521 bus_release_resource(dev, SYS_RES_MEMORY, 522 sc->sc_rid_regs, sc->sc_regs); 523 sc->sc_regs = NULL; 524 } 525 526 if (sc->sc_tag_rfis) { 527 bus_dma_tag_destroy(sc->sc_tag_rfis); 528 sc->sc_tag_rfis = NULL; 529 } 530 if (sc->sc_tag_cmdh) { 531 bus_dma_tag_destroy(sc->sc_tag_cmdh); 532 sc->sc_tag_cmdh = NULL; 533 } 534 if (sc->sc_tag_cmdt) { 535 bus_dma_tag_destroy(sc->sc_tag_cmdt); 536 sc->sc_tag_cmdt = NULL; 537 } 538 if (sc->sc_tag_data) { 539 bus_dma_tag_destroy(sc->sc_tag_data); 540 sc->sc_tag_data = NULL; 541 } 542 543 return (0); 544 } 545