1 /* 2 * (MPSAFE) 3 * 4 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * 19 * Copyright (c) 2009 The DragonFly Project. All rights reserved. 20 * 21 * This code is derived from software contributed to The DragonFly Project 22 * by Matthew Dillon <dillon@backplane.com> 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 28 * 1. Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * 2. Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in 32 * the documentation and/or other materials provided with the 33 * distribution. 34 * 3. Neither the name of The DragonFly Project nor the names of its 35 * contributors may be used to endorse or promote products derived 36 * from this software without specific, prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 39 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 41 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 42 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 43 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 48 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 49 * SUCH DAMAGE. 50 * 51 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $ 52 */ 53 54 #include "ahci.h" 55 56 static int ahci_vt8251_attach(device_t); 57 static int ahci_ati_sb600_attach(device_t); 58 static int ahci_nvidia_mcp_attach(device_t); 59 static int ahci_pci_attach(device_t); 60 static int ahci_pci_detach(device_t); 61 62 static const struct ahci_device ahci_devices[] = { 63 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA, 64 ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" }, 65 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA, 66 ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" }, 67 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 68 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" }, 69 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1, 70 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" }, 71 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 72 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" }, 73 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1, 74 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP79-SATA" }, 75 { 0, 0, 76 ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" } 77 }; 78 79 struct ahci_pciid { 80 uint16_t ahci_vid; 81 uint16_t ahci_did; 82 int ahci_rev; 83 }; 84 85 static const struct ahci_pciid ahci_msi_blacklist[] = { 86 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA, -1 }, 87 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_AHCI, -1 }, 88 89 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, -1 }, 90 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145, -1 }, 91 92 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 0xa1 }, 93 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 0xa1 }, 94 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 0xa1 }, 95 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 0xa1 }, 96 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_5, 0xa1 }, 97 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_6, 0xa1 }, 98 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_7, 0xa1 }, 99 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_8, 0xa1 }, 100 101 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 0xa2 }, 102 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 0xa2 }, 103 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 0xa2 }, 104 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 0xa2 }, 105 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_5, 0xa2 }, 106 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_6, 0xa2 }, 107 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_7, 0xa2 }, 108 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_8, 0xa2 } 109 }; 110 111 static int ahci_msi_enable = 1; 112 int ahci_synchronous_boot = 1; 113 TUNABLE_INT("hw.ahci.msi.enable", &ahci_msi_enable); 114 TUNABLE_INT("hw.ahci.synchronous_boot", &ahci_synchronous_boot); 115 116 /* 117 * Match during probe and attach. The device does not yet have a softc. 118 */ 119 const struct ahci_device * 120 ahci_lookup_device(device_t dev) 121 { 122 const struct ahci_device *ad; 123 u_int16_t vendor = pci_get_vendor(dev); 124 u_int16_t product = pci_get_device(dev); 125 u_int8_t class = pci_get_class(dev); 126 u_int8_t subclass = pci_get_subclass(dev); 127 u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1); 128 int is_ahci; 129 130 /* 131 * Generally speaking if the pci device does not identify as 132 * AHCI we skip it. 133 */ 134 if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA && 135 progif == PCIP_STORAGE_SATA_AHCI_1_0) { 136 is_ahci = 1; 137 } else { 138 is_ahci = 0; 139 } 140 141 for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) { 142 if (ad->ad_vendor == vendor && ad->ad_product == product) 143 return (ad); 144 } 145 146 /* 147 * Last ad is the default match if the PCI device matches SATA. 148 */ 149 if (is_ahci == 0) 150 ad = NULL; 151 return (ad); 152 } 153 154 /* 155 * Attach functions. They all eventually fall through to ahci_pci_attach(). 156 */ 157 static int 158 ahci_vt8251_attach(device_t dev) 159 { 160 struct ahci_softc *sc = device_get_softc(dev); 161 162 sc->sc_flags |= AHCI_F_NO_NCQ; 163 return (ahci_pci_attach(dev)); 164 } 165 166 static int 167 ahci_ati_sb600_attach(device_t dev) 168 { 169 struct ahci_softc *sc = device_get_softc(dev); 170 pcireg_t magic; 171 u_int8_t subclass = pci_get_subclass(dev); 172 u_int8_t revid; 173 174 if (subclass == PCIS_STORAGE_IDE) { 175 revid = pci_read_config(dev, PCIR_REVID, 1); 176 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4); 177 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 178 magic | AHCI_PCI_ATI_SB600_LOCKED, 4); 179 pci_write_config(dev, PCIR_REVID, 180 (PCIC_STORAGE << 24) | 181 (PCIS_STORAGE_SATA << 16) | 182 (PCIP_STORAGE_SATA_AHCI_1_0 << 8) | 183 revid, 4); 184 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4); 185 } 186 187 sc->sc_flags |= AHCI_F_IGN_FR; 188 return (ahci_pci_attach(dev)); 189 } 190 191 static int 192 ahci_nvidia_mcp_attach(device_t dev) 193 { 194 struct ahci_softc *sc = device_get_softc(dev); 195 196 sc->sc_flags |= AHCI_F_IGN_FR; 197 return (ahci_pci_attach(dev)); 198 } 199 200 static int 201 ahci_pci_attach(device_t dev) 202 { 203 struct ahci_softc *sc = device_get_softc(dev); 204 struct ahci_port *ap; 205 const char *gen; 206 uint16_t vid, did; 207 u_int32_t pi, reg; 208 u_int32_t cap, cap2; 209 u_int32_t chip; 210 u_int irq_flags; 211 bus_addr_t addr; 212 int i, error, msi_enable, rev, fbs; 213 char revbuf[32]; 214 215 if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) { 216 device_printf(dev, "BIOS disabled PCI interrupt, " 217 "re-enabling\n"); 218 pci_write_config(dev, PCIR_COMMAND, 219 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 220 } 221 222 /* 223 * Chip quirks. Sigh. The AHCI spec is not in the least confusing 224 * when it comes to how the FR and CR bits work, but some AHCI 225 * chipsets (aka Marvell) either don't have the bits at all or they 226 * implement them poorly. 227 */ 228 chip = ((uint16_t)pci_get_device(dev) << 16) | 229 (uint16_t)pci_get_vendor(dev); 230 231 switch(chip) { 232 case 0x91721b4b: 233 device_printf(dev, 234 "Enable 88SE9172 workarounds for broken chip\n"); 235 sc->sc_flags |= AHCI_F_IGN_FR; 236 sc->sc_flags |= AHCI_F_IGN_CR; 237 break; 238 case 0x92151b4b: 239 device_printf(dev, 240 "Enable 88SE9215 workarounds for broken chip\n"); 241 sc->sc_flags |= AHCI_F_IGN_FR; 242 sc->sc_flags |= AHCI_F_IGN_CR; 243 break; 244 case 0x92301b4b: 245 device_printf(dev, 246 "Enable 88SE9230 workarounds for broken chip\n"); 247 sc->sc_flags |= AHCI_F_CYCLE_FR; 248 break; 249 } 250 251 sc->sc_dev = dev; 252 253 /* 254 * Map the AHCI controller's IRQ and BAR(5) (hardware registers) 255 */ 256 msi_enable = ahci_msi_enable; 257 258 vid = pci_get_vendor(dev); 259 did = pci_get_device(dev); 260 rev = pci_get_revid(dev); 261 for (i = 0; i < NELEM(ahci_msi_blacklist); ++i) { 262 const struct ahci_pciid *id = &ahci_msi_blacklist[i]; 263 264 if (vid == id->ahci_vid && did == id->ahci_did) { 265 if (id->ahci_rev < 0 || id->ahci_rev == rev) { 266 msi_enable = 0; 267 break; 268 } 269 } 270 } 271 272 sc->sc_irq_type = pci_alloc_1intr(dev, msi_enable, 273 &sc->sc_rid_irq, &irq_flags); 274 275 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq, 276 irq_flags); 277 if (sc->sc_irq == NULL) { 278 device_printf(dev, "unable to map interrupt\n"); 279 ahci_pci_detach(dev); 280 return (ENXIO); 281 } 282 283 /* 284 * When mapping the register window store the tag and handle 285 * separately so we can use the tag with per-port bus handle 286 * sub-spaces. 287 */ 288 sc->sc_rid_regs = PCIR_BAR(5); 289 sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 290 &sc->sc_rid_regs, RF_ACTIVE); 291 if (sc->sc_regs == NULL) { 292 device_printf(dev, "unable to map registers\n"); 293 ahci_pci_detach(dev); 294 return (ENXIO); 295 } 296 sc->sc_iot = rman_get_bustag(sc->sc_regs); 297 sc->sc_ioh = rman_get_bushandle(sc->sc_regs); 298 299 /* 300 * Initialize the chipset and then set the interrupt vector up 301 */ 302 error = ahci_init(sc); 303 if (error) { 304 ahci_pci_detach(dev); 305 return (ENXIO); 306 } 307 308 /* 309 * Get the AHCI capabilities and max number of concurrent 310 * command tags and set up the DMA tags. Adjust the saved 311 * sc_cap according to override flags. 312 */ 313 cap = ahci_read(sc, AHCI_REG_CAP); 314 if (sc->sc_flags & AHCI_F_NO_NCQ) 315 cap &= ~AHCI_REG_CAP_SNCQ; 316 if (sc->sc_flags & AHCI_F_FORCE_FBSS) 317 cap |= AHCI_REG_CAP_FBSS; 318 if (sc->sc_flags & AHCI_F_FORCE_SCLO) 319 cap |= AHCI_REG_CAP_SCLO; 320 sc->sc_cap = cap; 321 322 /* 323 * We assume at least 4 commands. 324 */ 325 sc->sc_ncmds = AHCI_REG_CAP_NCS(cap); 326 if (sc->sc_ncmds < 4) { 327 device_printf(dev, "NCS must probe a value >= 4\n"); 328 ahci_pci_detach(dev); 329 return (ENXIO); 330 } 331 332 addr = (cap & AHCI_REG_CAP_S64A) ? 333 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT; 334 335 /* 336 * DMA tags for allocation of DMA memory buffers, lists, and so 337 * forth. These are typically per-port. 338 * 339 * When FIS-based switching is supported we need a rfis for 340 * each target (4K total). The spec also requires 4K alignment 341 * for this case. 342 */ 343 fbs = (cap & AHCI_REG_CAP_FBSS) ? 16 : 1; 344 error = 0; 345 346 sc->sc_rfis_size = sizeof(struct ahci_rfis) * fbs; 347 348 error += bus_dma_tag_create( 349 NULL, /* parent tag */ 350 sc->sc_rfis_size, /* alignment */ 351 PAGE_SIZE, /* boundary */ 352 addr, /* loaddr? */ 353 BUS_SPACE_MAXADDR, /* hiaddr */ 354 NULL, /* filter */ 355 NULL, /* filterarg */ 356 sc->sc_rfis_size, /* [max]size */ 357 1, /* maxsegs */ 358 sc->sc_rfis_size, /* maxsegsz */ 359 0, /* flags */ 360 &sc->sc_tag_rfis); /* return tag */ 361 362 sc->sc_cmdlist_size = sc->sc_ncmds * sizeof(struct ahci_cmd_hdr); 363 364 error += bus_dma_tag_create( 365 NULL, /* parent tag */ 366 32, /* alignment */ 367 4096 * 1024, /* boundary */ 368 addr, /* loaddr? */ 369 BUS_SPACE_MAXADDR, /* hiaddr */ 370 NULL, /* filter */ 371 NULL, /* filterarg */ 372 sc->sc_cmdlist_size, 373 1, /* maxsegs */ 374 sc->sc_cmdlist_size, 375 0, /* flags */ 376 &sc->sc_tag_cmdh); /* return tag */ 377 378 /* 379 * NOTE: ahci_cmd_table is sized to a power of 2 380 */ 381 error += bus_dma_tag_create( 382 NULL, /* parent tag */ 383 sizeof(struct ahci_cmd_table), /* alignment */ 384 4096 * 1024, /* boundary */ 385 addr, /* loaddr? */ 386 BUS_SPACE_MAXADDR, /* hiaddr */ 387 NULL, /* filter */ 388 NULL, /* filterarg */ 389 sc->sc_ncmds * sizeof(struct ahci_cmd_table), 390 1, /* maxsegs */ 391 sc->sc_ncmds * sizeof(struct ahci_cmd_table), 392 0, /* flags */ 393 &sc->sc_tag_cmdt); /* return tag */ 394 395 /* 396 * The data tag is used for later dmamaps and not immediately 397 * allocated. 398 */ 399 error += bus_dma_tag_create( 400 NULL, /* parent tag */ 401 4, /* alignment */ 402 0, /* boundary */ 403 addr, /* loaddr? */ 404 BUS_SPACE_MAXADDR, /* hiaddr */ 405 NULL, /* filter */ 406 NULL, /* filterarg */ 407 4096 * 1024, /* maxiosize */ 408 AHCI_MAX_PRDT, /* maxsegs */ 409 65536, /* maxsegsz */ 410 0, /* flags */ 411 &sc->sc_tag_data); /* return tag */ 412 413 if (error) { 414 device_printf(dev, "unable to create dma tags\n"); 415 ahci_pci_detach(dev); 416 return (ENXIO); 417 } 418 419 switch (cap & AHCI_REG_CAP_ISS) { 420 case AHCI_REG_CAP_ISS_G1: 421 gen = "1 (1.5Gbps)"; 422 break; 423 case AHCI_REG_CAP_ISS_G2: 424 gen = "2 (3Gbps)"; 425 break; 426 case AHCI_REG_CAP_ISS_G3: 427 gen = "3 (6Gbps)"; 428 break; 429 default: 430 gen = "unknown"; 431 break; 432 } 433 434 /* check the revision */ 435 reg = ahci_read(sc, AHCI_REG_VS); 436 437 if (reg & 0x0000FF) { 438 ksnprintf(revbuf, sizeof(revbuf), "AHCI %d.%d.%d", 439 (reg >> 16), (uint8_t)(reg >> 8), (uint8_t)reg); 440 } else { 441 ksnprintf(revbuf, sizeof(revbuf), "AHCI %d.%d", 442 (reg >> 16), (uint8_t)(reg >> 8)); 443 } 444 sc->sc_vers = reg; 445 446 if (reg >= AHCI_REG_VS_1_3) { 447 cap2 = ahci_read(sc, AHCI_REG_CAP2); 448 device_printf(dev, 449 "%s cap 0x%b cap2 0x%b, %d ports, " 450 "%d tags/port, gen %s\n", 451 revbuf, 452 cap, AHCI_FMT_CAP, 453 cap2, AHCI_FMT_CAP2, 454 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen); 455 } else { 456 cap2 = 0; 457 device_printf(dev, 458 "%s cap 0x%b, %d ports, " 459 "%d tags/port, gen %s\n", 460 revbuf, 461 cap, AHCI_FMT_CAP, 462 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen); 463 } 464 sc->sc_cap2 = cap2; 465 466 pi = ahci_read(sc, AHCI_REG_PI); 467 DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n", 468 DEVNAME(sc), pi); 469 470 sc->sc_ipm_disable = AHCI_PREG_SCTL_IPM_NOPARTIAL | 471 AHCI_PREG_SCTL_IPM_NOSLUMBER; 472 if (sc->sc_cap2 & AHCI_REG_CAP2_SDS) 473 sc->sc_ipm_disable |= AHCI_PREG_SCTL_IPM_NODEVSLP; 474 475 #ifdef AHCI_COALESCE 476 /* Naive coalescing support - enable for all ports. */ 477 if (cap & AHCI_REG_CAP_CCCS) { 478 u_int16_t ccc_timeout = 20; 479 u_int8_t ccc_numcomplete = 12; 480 u_int32_t ccc_ctl; 481 482 /* disable coalescing during reconfiguration. */ 483 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL); 484 ccc_ctl &= ~0x00000001; 485 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl); 486 487 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl); 488 if (pi & sc->sc_ccc_mask) { 489 /* A conflict with the implemented port list? */ 490 printf("%s: coalescing interrupt/implemented port list " 491 "conflict, PI: %08x, ccc_mask: %08x\n", 492 DEVNAME(sc), pi, sc->sc_ccc_mask); 493 sc->sc_ccc_mask = 0; 494 goto noccc; 495 } 496 497 /* ahci_port_start will enable each port when it starts. */ 498 sc->sc_ccc_ports = pi; 499 sc->sc_ccc_ports_cur = 0; 500 501 /* program thresholds and enable overall coalescing. */ 502 ccc_ctl &= ~0xffffff00; 503 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8); 504 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl); 505 ahci_write(sc, AHCI_REG_CCC_PORTS, 0); 506 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1); 507 } 508 noccc: 509 #endif 510 /* 511 * Allocate per-port resources 512 * 513 * Ignore attach errors, leave the port intact for 514 * rescan and continue the loop. 515 * 516 * All ports are attached in parallel but the CAM scan-bus 517 * is held up until all ports are attached so we get a deterministic 518 * order. 519 */ 520 for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) { 521 if ((pi & (1 << i)) == 0) { 522 /* dont allocate stuff if the port isnt implemented */ 523 continue; 524 } 525 error = ahci_port_alloc(sc, i); 526 } 527 528 /* 529 * Setup the interrupt vector and enable interrupts. Note that 530 * since the irq may be shared we do not set it up until we are 531 * ready to go. 532 */ 533 if (error == 0) { 534 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, 535 ahci_intr, sc, 536 &sc->sc_irq_handle, NULL); 537 } 538 539 if (error) { 540 device_printf(dev, "unable to install interrupt\n"); 541 ahci_pci_detach(dev); 542 return (ENXIO); 543 } 544 545 /* 546 * Before marking the sc as good, which allows the interrupt 547 * subsystem to operate on the ports, wait for all the port threads 548 * to get past their initial pre-probe init. Otherwise an interrupt 549 * may try to process the port before it has been initialized. 550 */ 551 for (i = 0; i < AHCI_MAX_PORTS; i++) { 552 if ((ap = sc->sc_ports[i]) != NULL) { 553 while (ap->ap_signal & AP_SIGF_THREAD_SYNC) 554 tsleep(&ap->ap_signal, 0, "ahprb1", hz); 555 } 556 } 557 558 /* 559 * Master interrupt enable, and call ahci_intr() in case we race 560 * our AHCI_F_INT_GOOD flag. 561 */ 562 crit_enter(); 563 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE); 564 sc->sc_flags |= AHCI_F_INT_GOOD; 565 crit_exit(); 566 ahci_intr(sc); 567 568 /* 569 * Synchronously wait for some of the AHCI devices to initialize. 570 * 571 * All ports are probing in parallel. Wait for them to finish 572 * and then issue the cam attachment and bus scan serially so 573 * the 'da' assignments are deterministic. 574 */ 575 for (i = 0; i < AHCI_MAX_PORTS && ahci_synchronous_boot; i++) { 576 if ((ap = sc->sc_ports[i]) != NULL) { 577 while (ap->ap_signal & AP_SIGF_INIT) 578 tsleep(&ap->ap_signal, 0, "ahprb2", hz); 579 ahci_os_lock_port(ap); 580 if (ahci_cam_attach(ap) == 0) { 581 ahci_cam_changed(ap, NULL, -1); 582 ahci_os_unlock_port(ap); 583 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) { 584 tsleep(&ap->ap_flags, 0, "ahprb3", hz); 585 } 586 } else { 587 ahci_os_unlock_port(ap); 588 } 589 } 590 } 591 592 return(0); 593 } 594 595 /* 596 * Device unload / detachment 597 */ 598 static int 599 ahci_pci_detach(device_t dev) 600 { 601 struct ahci_softc *sc = device_get_softc(dev); 602 struct ahci_port *ap; 603 int i; 604 605 /* 606 * Disable the controller and de-register the interrupt, if any. 607 * 608 * XXX interlock last interrupt? 609 */ 610 sc->sc_flags &= ~AHCI_F_INT_GOOD; 611 if (sc->sc_regs) 612 ahci_write(sc, AHCI_REG_GHC, 0); 613 614 if (sc->sc_irq_handle) { 615 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle); 616 sc->sc_irq_handle = NULL; 617 } 618 619 /* 620 * Free port structures and DMA memory 621 */ 622 for (i = 0; i < AHCI_MAX_PORTS; i++) { 623 ap = sc->sc_ports[i]; 624 if (ap) { 625 ahci_cam_detach(ap); 626 ahci_port_free(sc, i); 627 } 628 } 629 630 /* 631 * Clean up the bus space 632 */ 633 if (sc->sc_irq) { 634 bus_release_resource(dev, SYS_RES_IRQ, 635 sc->sc_rid_irq, sc->sc_irq); 636 sc->sc_irq = NULL; 637 } 638 639 if (sc->sc_irq_type == PCI_INTR_TYPE_MSI) 640 pci_release_msi(dev); 641 642 if (sc->sc_regs) { 643 bus_release_resource(dev, SYS_RES_MEMORY, 644 sc->sc_rid_regs, sc->sc_regs); 645 sc->sc_regs = NULL; 646 } 647 648 if (sc->sc_tag_rfis) { 649 bus_dma_tag_destroy(sc->sc_tag_rfis); 650 sc->sc_tag_rfis = NULL; 651 } 652 if (sc->sc_tag_cmdh) { 653 bus_dma_tag_destroy(sc->sc_tag_cmdh); 654 sc->sc_tag_cmdh = NULL; 655 } 656 if (sc->sc_tag_cmdt) { 657 bus_dma_tag_destroy(sc->sc_tag_cmdt); 658 sc->sc_tag_cmdt = NULL; 659 } 660 if (sc->sc_tag_data) { 661 bus_dma_tag_destroy(sc->sc_tag_data); 662 sc->sc_tag_data = NULL; 663 } 664 665 return (0); 666 } 667