1 /* 2 * (MPSAFE) 3 * 4 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * 19 * Copyright (c) 2009 The DragonFly Project. All rights reserved. 20 * 21 * This code is derived from software contributed to The DragonFly Project 22 * by Matthew Dillon <dillon@backplane.com> 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 28 * 1. Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * 2. Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in 32 * the documentation and/or other materials provided with the 33 * distribution. 34 * 3. Neither the name of The DragonFly Project nor the names of its 35 * contributors may be used to endorse or promote products derived 36 * from this software without specific, prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 39 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 41 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 42 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 43 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 48 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 49 * SUCH DAMAGE. 50 * 51 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $ 52 */ 53 54 #include "ahci.h" 55 56 static int ahci_vt8251_attach(device_t); 57 static int ahci_ati_sb600_attach(device_t); 58 static int ahci_nvidia_mcp_attach(device_t); 59 static int ahci_pci_attach(device_t); 60 static int ahci_pci_detach(device_t); 61 62 static const struct ahci_device ahci_devices[] = { 63 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA, 64 ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" }, 65 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA, 66 ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" }, 67 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 68 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" }, 69 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1, 70 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" }, 71 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 72 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" }, 73 { 0, 0, 74 ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" } 75 }; 76 77 struct ahci_pciid { 78 uint16_t ahci_vid; 79 uint16_t ahci_did; 80 int ahci_rev; 81 }; 82 83 static const struct ahci_pciid ahci_msi_blacklist[] = { 84 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA, -1 }, 85 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_AHCI, -1 }, 86 87 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, -1 }, 88 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145, -1 }, 89 90 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 0xa1 }, 91 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 0xa1 }, 92 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 0xa1 }, 93 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 0xa1 }, 94 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_5, 0xa1 }, 95 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_6, 0xa1 }, 96 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_7, 0xa1 }, 97 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_8, 0xa1 }, 98 99 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 0xa2 }, 100 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 0xa2 }, 101 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 0xa2 }, 102 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 0xa2 }, 103 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_5, 0xa2 }, 104 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_6, 0xa2 }, 105 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_7, 0xa2 }, 106 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_8, 0xa2 } 107 }; 108 109 static int ahci_msi_enable = 1; 110 TUNABLE_INT("hw.ahci.msi.enable", &ahci_msi_enable); 111 112 /* 113 * Match during probe and attach. The device does not yet have a softc. 114 */ 115 const struct ahci_device * 116 ahci_lookup_device(device_t dev) 117 { 118 const struct ahci_device *ad; 119 u_int16_t vendor = pci_get_vendor(dev); 120 u_int16_t product = pci_get_device(dev); 121 u_int8_t class = pci_get_class(dev); 122 u_int8_t subclass = pci_get_subclass(dev); 123 u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1); 124 int is_ahci; 125 126 /* 127 * Generally speaking if the pci device does not identify as 128 * AHCI we skip it. 129 */ 130 if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA && 131 progif == PCIP_STORAGE_SATA_AHCI_1_0) { 132 is_ahci = 1; 133 } else { 134 is_ahci = 0; 135 } 136 137 for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) { 138 if (ad->ad_vendor == vendor && ad->ad_product == product) 139 return (ad); 140 } 141 142 /* 143 * Last ad is the default match if the PCI device matches SATA. 144 */ 145 if (is_ahci == 0) 146 ad = NULL; 147 return (ad); 148 } 149 150 /* 151 * Attach functions. They all eventually fall through to ahci_pci_attach(). 152 */ 153 static int 154 ahci_vt8251_attach(device_t dev) 155 { 156 struct ahci_softc *sc = device_get_softc(dev); 157 158 sc->sc_flags |= AHCI_F_NO_NCQ; 159 return (ahci_pci_attach(dev)); 160 } 161 162 static int 163 ahci_ati_sb600_attach(device_t dev) 164 { 165 struct ahci_softc *sc = device_get_softc(dev); 166 pcireg_t magic; 167 u_int8_t subclass = pci_get_subclass(dev); 168 u_int8_t revid; 169 170 if (subclass == PCIS_STORAGE_IDE) { 171 revid = pci_read_config(dev, PCIR_REVID, 1); 172 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4); 173 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 174 magic | AHCI_PCI_ATI_SB600_LOCKED, 4); 175 pci_write_config(dev, PCIR_REVID, 176 (PCIC_STORAGE << 24) | 177 (PCIS_STORAGE_SATA << 16) | 178 (PCIP_STORAGE_SATA_AHCI_1_0 << 8) | 179 revid, 4); 180 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4); 181 } 182 183 sc->sc_flags |= AHCI_F_IGN_FR; 184 return (ahci_pci_attach(dev)); 185 } 186 187 static int 188 ahci_nvidia_mcp_attach(device_t dev) 189 { 190 struct ahci_softc *sc = device_get_softc(dev); 191 192 sc->sc_flags |= AHCI_F_IGN_FR; 193 return (ahci_pci_attach(dev)); 194 } 195 196 static int 197 ahci_pci_attach(device_t dev) 198 { 199 struct ahci_softc *sc = device_get_softc(dev); 200 struct ahci_port *ap; 201 const char *gen; 202 uint16_t vid, did; 203 u_int32_t cap, pi, reg; 204 u_int irq_flags; 205 bus_addr_t addr; 206 int i, error, msi_enable, rev; 207 const char *revision; 208 209 if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) { 210 device_printf(dev, "BIOS disabled PCI interrupt, " 211 "re-enabling\n"); 212 pci_write_config(dev, PCIR_COMMAND, 213 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 214 } 215 216 sc->sc_dev = dev; 217 218 /* 219 * Map the AHCI controller's IRQ and BAR(5) (hardware registers) 220 */ 221 222 msi_enable = ahci_msi_enable; 223 224 vid = pci_get_vendor(dev); 225 did = pci_get_device(dev); 226 rev = pci_get_revid(dev); 227 for (i = 0; i < NELEM(ahci_msi_blacklist); ++i) { 228 const struct ahci_pciid *id = &ahci_msi_blacklist[i]; 229 230 if (vid == id->ahci_vid && did == id->ahci_did) { 231 if (id->ahci_rev < 0 || id->ahci_rev == rev) { 232 msi_enable = 0; 233 break; 234 } 235 } 236 } 237 238 sc->sc_irq_type = pci_alloc_1intr(dev, msi_enable, 239 &sc->sc_rid_irq, &irq_flags); 240 241 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq, 242 irq_flags); 243 if (sc->sc_irq == NULL) { 244 device_printf(dev, "unable to map interrupt\n"); 245 ahci_pci_detach(dev); 246 return (ENXIO); 247 } 248 249 /* 250 * When mapping the register window store the tag and handle 251 * separately so we can use the tag with per-port bus handle 252 * sub-spaces. 253 */ 254 sc->sc_rid_regs = PCIR_BAR(5); 255 sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 256 &sc->sc_rid_regs, RF_ACTIVE); 257 if (sc->sc_regs == NULL) { 258 device_printf(dev, "unable to map registers\n"); 259 ahci_pci_detach(dev); 260 return (ENXIO); 261 } 262 sc->sc_iot = rman_get_bustag(sc->sc_regs); 263 sc->sc_ioh = rman_get_bushandle(sc->sc_regs); 264 265 /* 266 * Initialize the chipset and then set the interrupt vector up 267 */ 268 error = ahci_init(sc); 269 if (error) { 270 ahci_pci_detach(dev); 271 return (ENXIO); 272 } 273 274 /* 275 * Get the AHCI capabilities and max number of concurrent 276 * command tags and set up the DMA tags. 277 */ 278 cap = ahci_read(sc, AHCI_REG_CAP); 279 if (sc->sc_flags & AHCI_F_NO_NCQ) 280 cap &= ~AHCI_REG_CAP_SNCQ; 281 sc->sc_cap = cap; 282 283 /* 284 * We assume at least 4 commands. 285 */ 286 sc->sc_ncmds = AHCI_REG_CAP_NCS(cap); 287 if (sc->sc_ncmds < 4) { 288 device_printf(dev, "NCS must probe a value >= 4\n"); 289 ahci_pci_detach(dev); 290 return (ENXIO); 291 } 292 293 addr = (cap & AHCI_REG_CAP_S64A) ? 294 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT; 295 296 /* 297 * DMA tags for allocation of DMA memory buffers, lists, and so 298 * forth. These are typically per-port. 299 */ 300 error = 0; 301 error += bus_dma_tag_create( 302 NULL, /* parent tag */ 303 256, /* alignment */ 304 PAGE_SIZE, /* boundary */ 305 addr, /* loaddr? */ 306 BUS_SPACE_MAXADDR, /* hiaddr */ 307 NULL, /* filter */ 308 NULL, /* filterarg */ 309 sizeof(struct ahci_rfis), /* [max]size */ 310 1, /* maxsegs */ 311 sizeof(struct ahci_rfis), /* maxsegsz */ 312 0, /* flags */ 313 &sc->sc_tag_rfis); /* return tag */ 314 315 error += bus_dma_tag_create( 316 NULL, /* parent tag */ 317 32, /* alignment */ 318 4096 * 1024, /* boundary */ 319 addr, /* loaddr? */ 320 BUS_SPACE_MAXADDR, /* hiaddr */ 321 NULL, /* filter */ 322 NULL, /* filterarg */ 323 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr), 324 1, /* maxsegs */ 325 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr), 326 0, /* flags */ 327 &sc->sc_tag_cmdh); /* return tag */ 328 329 /* 330 * NOTE: ahci_cmd_table is sized to a power of 2 331 */ 332 error += bus_dma_tag_create( 333 NULL, /* parent tag */ 334 sizeof(struct ahci_cmd_table), /* alignment */ 335 4096 * 1024, /* boundary */ 336 addr, /* loaddr? */ 337 BUS_SPACE_MAXADDR, /* hiaddr */ 338 NULL, /* filter */ 339 NULL, /* filterarg */ 340 sc->sc_ncmds * sizeof(struct ahci_cmd_table), 341 1, /* maxsegs */ 342 sc->sc_ncmds * sizeof(struct ahci_cmd_table), 343 0, /* flags */ 344 &sc->sc_tag_cmdt); /* return tag */ 345 346 /* 347 * The data tag is used for later dmamaps and not immediately 348 * allocated. 349 */ 350 error += bus_dma_tag_create( 351 NULL, /* parent tag */ 352 4, /* alignment */ 353 0, /* boundary */ 354 addr, /* loaddr? */ 355 BUS_SPACE_MAXADDR, /* hiaddr */ 356 NULL, /* filter */ 357 NULL, /* filterarg */ 358 4096 * 1024, /* maxiosize */ 359 AHCI_MAX_PRDT, /* maxsegs */ 360 65536, /* maxsegsz */ 361 0, /* flags */ 362 &sc->sc_tag_data); /* return tag */ 363 364 if (error) { 365 device_printf(dev, "unable to create dma tags\n"); 366 ahci_pci_detach(dev); 367 return (ENXIO); 368 } 369 370 switch (cap & AHCI_REG_CAP_ISS) { 371 case AHCI_REG_CAP_ISS_G1: 372 gen = "1 (1.5Gbps)"; 373 break; 374 case AHCI_REG_CAP_ISS_G2: 375 gen = "2 (3Gbps)"; 376 break; 377 case AHCI_REG_CAP_ISS_G3: 378 gen = "3 (6Gbps)"; 379 break; 380 default: 381 gen = "unknown"; 382 break; 383 } 384 385 /* check the revision */ 386 reg = ahci_read(sc, AHCI_REG_VS); 387 switch (reg) { 388 case AHCI_REG_VS_0_95: 389 revision = "AHCI 0.95"; 390 break; 391 case AHCI_REG_VS_1_0: 392 revision = "AHCI 1.0"; 393 break; 394 case AHCI_REG_VS_1_1: 395 revision = "AHCI 1.1"; 396 break; 397 case AHCI_REG_VS_1_2: 398 revision = "AHCI 1.2"; 399 break; 400 case AHCI_REG_VS_1_3: 401 revision = "AHCI 1.3"; 402 break; 403 case AHCI_REG_VS_1_4: 404 revision = "AHCI 1.4"; 405 break; 406 case AHCI_REG_VS_1_5: 407 revision = "AHCI 1.5"; /* future will catch up to us */ 408 break; 409 default: 410 device_printf(sc->sc_dev, 411 "Warning: Unknown AHCI revision 0x%08x\n", reg); 412 revision = "AHCI <unknown>"; 413 break; 414 } 415 416 device_printf(dev, 417 "%s capabilities 0x%b, %d ports, %d tags/port, gen %s\n", 418 revision, 419 cap, AHCI_FMT_CAP, 420 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen); 421 422 pi = ahci_read(sc, AHCI_REG_PI); 423 DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n", 424 DEVNAME(sc), pi); 425 426 #ifdef AHCI_COALESCE 427 /* Naive coalescing support - enable for all ports. */ 428 if (cap & AHCI_REG_CAP_CCCS) { 429 u_int16_t ccc_timeout = 20; 430 u_int8_t ccc_numcomplete = 12; 431 u_int32_t ccc_ctl; 432 433 /* disable coalescing during reconfiguration. */ 434 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL); 435 ccc_ctl &= ~0x00000001; 436 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl); 437 438 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl); 439 if (pi & sc->sc_ccc_mask) { 440 /* A conflict with the implemented port list? */ 441 printf("%s: coalescing interrupt/implemented port list " 442 "conflict, PI: %08x, ccc_mask: %08x\n", 443 DEVNAME(sc), pi, sc->sc_ccc_mask); 444 sc->sc_ccc_mask = 0; 445 goto noccc; 446 } 447 448 /* ahci_port_start will enable each port when it starts. */ 449 sc->sc_ccc_ports = pi; 450 sc->sc_ccc_ports_cur = 0; 451 452 /* program thresholds and enable overall coalescing. */ 453 ccc_ctl &= ~0xffffff00; 454 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8); 455 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl); 456 ahci_write(sc, AHCI_REG_CCC_PORTS, 0); 457 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1); 458 } 459 noccc: 460 #endif 461 /* 462 * Allocate per-port resources 463 * 464 * Ignore attach errors, leave the port intact for 465 * rescan and continue the loop. 466 * 467 * All ports are attached in parallel but the CAM scan-bus 468 * is held up until all ports are attached so we get a deterministic 469 * order. 470 */ 471 for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) { 472 if ((pi & (1 << i)) == 0) { 473 /* dont allocate stuff if the port isnt implemented */ 474 continue; 475 } 476 error = ahci_port_alloc(sc, i); 477 } 478 479 /* 480 * Setup the interrupt vector and enable interrupts. Note that 481 * since the irq may be shared we do not set it up until we are 482 * ready to go. 483 */ 484 if (error == 0) { 485 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, 486 ahci_intr, sc, 487 &sc->sc_irq_handle, NULL); 488 } 489 490 if (error) { 491 device_printf(dev, "unable to install interrupt\n"); 492 ahci_pci_detach(dev); 493 return (ENXIO); 494 } 495 496 /* 497 * Before marking the sc as good, which allows the interrupt 498 * subsystem to operate on the ports, wait for all the port threads 499 * to get past their initial pre-probe init. Otherwise an interrupt 500 * may try to process the port before it has been initialized. 501 */ 502 for (i = 0; i < AHCI_MAX_PORTS; i++) { 503 if ((ap = sc->sc_ports[i]) != NULL) { 504 while (ap->ap_signal & AP_SIGF_THREAD_SYNC) 505 tsleep(&ap->ap_signal, 0, "ahprb1", hz); 506 } 507 } 508 509 /* 510 * Master interrupt enable, and call ahci_intr() in case we race 511 * our AHCI_F_INT_GOOD flag. 512 */ 513 crit_enter(); 514 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE); 515 sc->sc_flags |= AHCI_F_INT_GOOD; 516 crit_exit(); 517 ahci_intr(sc); 518 519 /* 520 * All ports are probing in parallel. Wait for them to finish 521 * and then issue the cam attachment and bus scan serially so 522 * the 'da' assignments are deterministic. 523 */ 524 for (i = 0; i < AHCI_MAX_PORTS; i++) { 525 if ((ap = sc->sc_ports[i]) != NULL) { 526 while (ap->ap_signal & AP_SIGF_INIT) 527 tsleep(&ap->ap_signal, 0, "ahprb2", hz); 528 ahci_os_lock_port(ap); 529 if (ahci_cam_attach(ap) == 0) { 530 ahci_cam_changed(ap, NULL, -1); 531 ahci_os_unlock_port(ap); 532 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) { 533 tsleep(&ap->ap_flags, 0, "ahprb2", hz); 534 } 535 } else { 536 ahci_os_unlock_port(ap); 537 } 538 } 539 } 540 541 return(0); 542 } 543 544 /* 545 * Device unload / detachment 546 */ 547 static int 548 ahci_pci_detach(device_t dev) 549 { 550 struct ahci_softc *sc = device_get_softc(dev); 551 struct ahci_port *ap; 552 int i; 553 554 /* 555 * Disable the controller and de-register the interrupt, if any. 556 * 557 * XXX interlock last interrupt? 558 */ 559 sc->sc_flags &= ~AHCI_F_INT_GOOD; 560 if (sc->sc_regs) 561 ahci_write(sc, AHCI_REG_GHC, 0); 562 563 if (sc->sc_irq_handle) { 564 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle); 565 sc->sc_irq_handle = NULL; 566 } 567 568 /* 569 * Free port structures and DMA memory 570 */ 571 for (i = 0; i < AHCI_MAX_PORTS; i++) { 572 ap = sc->sc_ports[i]; 573 if (ap) { 574 ahci_cam_detach(ap); 575 ahci_port_free(sc, i); 576 } 577 } 578 579 /* 580 * Clean up the bus space 581 */ 582 if (sc->sc_irq) { 583 bus_release_resource(dev, SYS_RES_IRQ, 584 sc->sc_rid_irq, sc->sc_irq); 585 sc->sc_irq = NULL; 586 } 587 588 if (sc->sc_irq_type == PCI_INTR_TYPE_MSI) 589 pci_release_msi(dev); 590 591 if (sc->sc_regs) { 592 bus_release_resource(dev, SYS_RES_MEMORY, 593 sc->sc_rid_regs, sc->sc_regs); 594 sc->sc_regs = NULL; 595 } 596 597 if (sc->sc_tag_rfis) { 598 bus_dma_tag_destroy(sc->sc_tag_rfis); 599 sc->sc_tag_rfis = NULL; 600 } 601 if (sc->sc_tag_cmdh) { 602 bus_dma_tag_destroy(sc->sc_tag_cmdh); 603 sc->sc_tag_cmdh = NULL; 604 } 605 if (sc->sc_tag_cmdt) { 606 bus_dma_tag_destroy(sc->sc_tag_cmdt); 607 sc->sc_tag_cmdt = NULL; 608 } 609 if (sc->sc_tag_data) { 610 bus_dma_tag_destroy(sc->sc_tag_data); 611 sc->sc_tag_data = NULL; 612 } 613 614 return (0); 615 } 616