1 /* 2 * Generic register and struct definitions for the BusLogic 3 * MultiMaster SCSI host adapters. Product specific probe and 4 * attach routines can be found in: 5 * sys/dev/buslogic/bt_isa.c BT-54X, BT-445 cards 6 * sys/dev/buslogic/bt_pci.c BT-946, BT-948, BT-956, BT-958 cards 7 * 8 * Copyright (c) 1998, 1999 Justin T. Gibbs. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification, immediately at the beginning of the file. 17 * 2. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/dev/buslogic/btreg.h,v 1.10.2.2 2001/09/03 02:45:22 peter Exp $ 33 */ 34 35 #ifndef _BTREG_H_ 36 #define _BTREG_H_ 37 38 #include <sys/queue.h> 39 40 #define BT_MAXTRANSFER_SIZE 0xffffffff /* limited by 32bit counter */ 41 #define BT_NSEG 32 /* The number of dma segments supported. 42 * BT_NSEG can be maxed out at 8192 entries, 43 * but the kernel will never need to transfer 44 * such a large request. To reduce the 45 * driver's memory consumption, we reduce the 46 * max to 32. 16 would work if all transfers 47 * are paged alined since the kernel will only 48 * generate at most a 64k transfer, but to 49 * handle non-page aligned transfers, you need 50 * 17, so we round to the next power of two 51 * to make allocating SG space easy and 52 * efficient. 53 */ 54 55 #define ALL_TARGETS (~0) 56 57 /* 58 * Control Register pp. 1-8, 1-9 (Write Only) 59 */ 60 #define CONTROL_REG 0x00 61 #define HARD_RESET 0x80 /* Hard Reset - return to POST state */ 62 #define SOFT_RESET 0x40 /* Soft Reset - Clears Adapter state */ 63 #define RESET_INTR 0x20 /* Reset/Ack Interrupt */ 64 #define RESET_SBUS 0x10 /* Drive SCSI bus reset signal */ 65 66 /* 67 * Status Register pp. 1-9, 1-10 (Read Only) 68 */ 69 #define STATUS_REG 0x00 70 #define DIAG_ACTIVE 0x80 /* Performing Internal Diags */ 71 #define DIAG_FAIL 0x40 /* Internal Diags failed */ 72 #define INIT_REQUIRED 0x20 /* MBOXes need initialization */ 73 #define HA_READY 0x10 /* HA ready for new commands */ 74 #define CMD_REG_BUSY 0x08 /* HA busy with last cmd byte */ 75 #define DATAIN_REG_READY 0x04 /* Data-in Byte available */ 76 #define STATUS_REG_RSVD 0x02 77 #define CMD_INVALID 0x01 /* Invalid Command detected */ 78 79 /* 80 * Command/Parameter Register pp. 1-10, 1-11 (Write Only) 81 */ 82 #define COMMAND_REG 0x01 83 84 /* 85 * Data in Register p. 1-11 (Read Only) 86 */ 87 #define DATAIN_REG 0x01 88 89 /* 90 * Interrupt Status Register pp. 1-12 -> 1-14 (Read Only) 91 */ 92 #define INTSTAT_REG 0x02 93 #define INTR_PENDING 0x80 /* There is a pending INTR */ 94 #define INTSTAT_REG_RSVD 0x70 95 #define SCSI_BUS_RESET 0x08 /* Bus Reset detected */ 96 #define CMD_COMPLETE 0x04 97 #define OMB_READY 0x02 /* Outgoin Mailbox Ready */ 98 #define IMB_LOADED 0x01 /* Incoming Mailbox loaded */ 99 100 /* 101 * Definitions for the "undocumented" geometry register 102 */ 103 typedef enum { 104 GEOM_NODISK, 105 GEOM_64x32, 106 GEOM_128x32, 107 GEOM_255x32 108 } disk_geom_t; 109 110 #define GEOMETRY_REG 0x03 111 #define DISK0_GEOMETRY 0x03 112 #define DISK1_GEOMETRY 0x0c 113 #define EXTENDED_TRANSLATION 0x80 114 #define GEOMETRY_DISK0(g_reg) (greg & DISK0_GEOMETRY) 115 #define GEOMETRY_DISK1(g_reg) ((greg & DISK1_GEOMETRY) >> 2) 116 117 #define BT_NREGS (4) 118 /* 119 * Opcodes for Adapter commands. 120 * pp 1-18 -> 1-20 121 */ 122 typedef enum { 123 BOP_TEST_CMDC_INTR = 0x00, 124 BOP_INITIALIZE_24BMBOX = 0x01, 125 BOP_START_MBOX = 0x02, 126 BOP_EXECUTE_BIOS_CMD = 0x03, 127 BOP_INQUIRE_BOARD_ID = 0x04, 128 BOP_ENABLE_OMBR_INT = 0x05, 129 BOP_SET_SEL_TIMOUT = 0x06, 130 BOP_SET_TIME_ON_BUS = 0x07, 131 BOP_SET_TIME_OFF_BUS = 0x08, 132 BOP_SET_BUS_TRANS_RATE = 0x09, 133 BOP_INQUIRE_INST_LDEVS = 0x0A, 134 BOP_INQUIRE_CONFIG = 0x0B, 135 BOP_ENABLE_TARGET_MODE = 0x0C, 136 BOP_INQUIRE_SETUP_INFO = 0x0D, 137 BOP_WRITE_LRAM = 0x1A, 138 BOP_READ_LRAM = 0x1B, 139 BOP_WRITE_CHIP_FIFO = 0x1C, 140 BOP_READ_CHIP_FIFO = 0x1C, 141 BOP_ECHO_DATA_BYTE = 0x1F, 142 BOP_ADAPTER_DIAGNOSTICS = 0x20, 143 BOP_SET_ADAPTER_OPTIONS = 0x21, 144 BOP_INQUIRE_INST_HDEVS = 0x23, 145 BOP_INQUIRE_TARG_DEVS = 0x24, 146 BOP_DISABLE_HAC_INTR = 0x25, 147 BOP_INITIALIZE_32BMBOX = 0x81, 148 BOP_EXECUTE_SCSI_CMD = 0x83, 149 BOP_INQUIRE_FW_VER_3DIG = 0x84, 150 BOP_INQUIRE_FW_VER_4DIG = 0x85, 151 BOP_INQUIRE_PCI_INFO = 0x86, 152 BOP_INQUIRE_MODEL = 0x8B, 153 BOP_TARG_SYNC_INFO = 0x8C, 154 BOP_INQUIRE_ESETUP_INFO = 0x8D, 155 BOP_ENABLE_STRICT_RR = 0x8F, 156 BOP_STORE_LRAM = 0x90, 157 BOP_FETCH_LRAM = 0x91, 158 BOP_SAVE_TO_EEPROM = 0x92, 159 BOP_UPLOAD_AUTO_SCSI = 0x94, 160 BOP_MODIFY_IO_ADDR = 0x95, 161 BOP_SET_CCB_FORMAT = 0x96, 162 BOP_FLASH_ROM_DOWNLOAD = 0x97, 163 BOP_FLASH_WRITE_ENABLE = 0x98, 164 BOP_WRITE_INQ_BUFFER = 0x9A, 165 BOP_READ_INQ_BUFFER = 0x9B, 166 BOP_FLASH_UP_DOWNLOAD = 0xA7, 167 BOP_READ_SCAM_DATA = 0xA8, 168 BOP_WRITE_SCAM_DATA = 0xA9 169 } bt_op_t; 170 171 /************** Definitions of Multi-byte commands and responses ************/ 172 173 typedef struct { 174 u_int8_t num_mboxes; 175 u_int8_t base_addr[3]; 176 } init_24b_mbox_params_t; 177 178 typedef struct { 179 u_int8_t board_type; 180 #define BOARD_TYPE_NON_MCA 0x41 181 #define BOARD_TYPE_MCA 0x42 182 u_int8_t cust_features; 183 #define FEATURES_STANDARD 0x41 184 u_int8_t firmware_rev_major; 185 u_int8_t firmware_rev_minor; 186 } board_id_data_t; 187 188 typedef struct { 189 u_int8_t enable; 190 } enable_ombr_intr_params_t; 191 192 typedef struct { 193 u_int8_t enable; 194 u_int8_t reserved; 195 u_int8_t timeout[2]; /* timeout in milliseconds */ 196 } set_selto_parmas_t; 197 198 typedef struct { 199 u_int8_t time; /* time in milliseconds (2-15) */ 200 } set_timeon_bus_params_t; 201 202 typedef struct { 203 u_int8_t time; /* time in milliseconds (2-15) */ 204 } set_timeoff_bus_params_t; 205 206 typedef struct { 207 u_int8_t rate; 208 } set_bus_trasfer_rate_params_t; 209 210 typedef struct { 211 u_int8_t targets[8]; 212 } installed_ldevs_data_t; 213 214 typedef struct { 215 u_int8_t dma_chan; 216 #define DMA_CHAN_5 0x20 217 #define DMA_CHAN_6 0x40 218 #define DMA_CHAN_7 0x80 219 u_int8_t irq; 220 #define IRQ_9 0x01 221 #define IRQ_10 0x02 222 #define IRQ_11 0x04 223 #define IRQ_12 0x08 224 #define IRQ_14 0x20 225 #define IRQ_15 0x40 226 u_int8_t scsi_id; 227 } config_data_t; 228 229 typedef struct { 230 u_int8_t enable; 231 } target_mode_params_t; 232 233 typedef struct { 234 u_int8_t offset : 4, 235 period : 3, 236 sync : 1; 237 } targ_syncinfo_t; 238 239 typedef enum { 240 HAB_ISA = 'A', 241 HAB_MCA = 'B', 242 HAB_EISA = 'C', 243 HAB_NUBUS = 'D', 244 HAB_VESA = 'E', 245 HAB_PCI = 'F' 246 } ha_type_t; 247 248 typedef struct { 249 u_int8_t initiate_sync : 1, 250 parity_enable : 1, 251 : 6; 252 253 u_int8_t bus_transfer_rate; 254 u_int8_t time_on_bus; 255 u_int8_t time_off_bus; 256 u_int8_t num_mboxes; 257 u_int8_t mbox_base_addr[3]; 258 targ_syncinfo_t low_syncinfo[8]; /* For fast and ultra, use 8C */ 259 u_int8_t low_discinfo; 260 u_int8_t customer_sig; 261 u_int8_t letter_d; 262 u_int8_t ha_type; 263 u_int8_t low_wide_allowed; 264 u_int8_t low_wide_active; 265 targ_syncinfo_t high_syncinfo[8]; 266 u_int8_t high_discinfo; 267 u_int8_t high_wide_allowed; 268 u_int8_t high_wide_active; 269 } setup_data_t; 270 271 typedef struct { 272 u_int8_t phys_addr[3]; 273 } write_adapter_lram_params_t; 274 275 typedef struct { 276 u_int8_t phys_addr[3]; 277 } read_adapter_lram_params_t; 278 279 typedef struct { 280 u_int8_t phys_addr[3]; 281 } write_chip_fifo_params_t; 282 283 typedef struct { 284 u_int8_t phys_addr[3]; 285 } read_chip_fifo_params_t; 286 287 typedef struct { 288 u_int8_t length; /* Excludes this member */ 289 u_int8_t low_disc_disable; 290 u_int8_t low_busy_retry_disable; 291 u_int8_t high_disc_disable; 292 u_int8_t high_busy_retry_disable; 293 } set_adapter_options_params_t; 294 295 typedef struct { 296 u_int8_t targets[8]; 297 } installed_hdevs_data_t; 298 299 typedef struct { 300 u_int8_t low_devs; 301 u_int8_t high_devs; 302 } target_devs_data_t; 303 304 typedef struct { 305 u_int8_t enable; 306 } enable_hac_interrupt_params_t; 307 308 typedef struct { 309 u_int8_t num_boxes; 310 u_int8_t base_addr[4]; 311 } init_32b_mbox_params_t; 312 313 typedef u_int8_t fw_ver_3dig_data_t; 314 315 typedef u_int8_t fw_ver_4dig_data_t; 316 317 typedef struct { 318 u_int8_t offset; 319 u_int8_t response_len; 320 } fetch_lram_params_t; 321 322 #define AUTO_SCSI_BYTE_OFFSET 64 323 typedef struct { 324 u_int8_t factory_sig[2]; 325 u_int8_t auto_scsi_data_size; /* 2 -> 64 bytes */ 326 u_int8_t model_num[6]; 327 u_int8_t adapter_ioport; 328 u_int8_t floppy_enabled :1, 329 floppy_secondary :1, 330 level_trigger :1, 331 :2, 332 system_ram_area :3; 333 u_int8_t dma_channel :7, 334 dma_autoconf :1; 335 u_int8_t irq_channel :7, 336 irq_autoconf :1; 337 u_int8_t dma_trans_rate; 338 u_int8_t scsi_id; 339 u_int8_t low_termination :1, 340 scsi_parity :1, 341 high_termination :1, 342 req_ack_filter :1, 343 fast_sync :1, 344 bus_reset :1, 345 :1, 346 active_negation :1; 347 u_int8_t bus_on_delay; 348 u_int8_t bus_off_delay; 349 u_int8_t bios_enabled :1, 350 int19h_redirect :1, 351 extended_trans :1, 352 removable_drives :1, 353 :1, 354 morethan2disks :1, 355 interrupt_mode :1, 356 floptical_support:1; 357 u_int8_t low_device_enabled; 358 u_int8_t high_device_enabled; 359 u_int8_t low_wide_permitted; 360 u_int8_t high_wide_permitted; 361 u_int8_t low_fast_permitted; 362 u_int8_t high_fast_permitted; 363 u_int8_t low_sync_permitted; 364 u_int8_t high_sync_permitted; 365 u_int8_t low_disc_permitted; 366 u_int8_t high_disc_permitted; 367 u_int8_t low_send_start_unit; 368 u_int8_t high_send_start_unit; 369 u_int8_t low_ignore_in_bios_scan; 370 u_int8_t high_ignore_in_bios_scan; 371 u_int8_t pci_int_pin :2, 372 host_ioport :2, 373 round_robin :1, 374 vesa_bus_over_33 :1, 375 vesa_burst_write :1, 376 vesa_burst_read :1; 377 u_int8_t low_ultra_permitted; 378 u_int8_t high_ultra_permitted; 379 u_int8_t reserved[5]; 380 u_int8_t auto_scsi_max_lun; 381 u_int8_t :1, 382 scam_dominant :1, 383 scam_enabled :1, 384 scam_level2 :1, 385 :4; 386 u_int8_t int13_extensions :1, 387 :1, 388 cdrom_boot :1, 389 :2, 390 multi_boot :1, 391 :2; 392 u_int8_t boot_target_id :4, 393 boot_channel :4; 394 u_int8_t force_dev_scan :1, 395 :7; 396 u_int8_t low_tagged_lun_independance; 397 u_int8_t high_tagged_lun_independance; 398 u_int8_t low_renegotiate_after_cc; 399 u_int8_t high_renegotiate_after_cc; 400 u_int8_t reserverd2[10]; 401 u_int8_t manufacturing_diagnotic[2]; 402 u_int8_t checksum[2]; 403 } auto_scsi_data_t; 404 405 struct bt_isa_port { 406 u_int16_t addr; 407 u_int8_t probed; 408 u_int8_t bio; 409 }; 410 411 extern struct bt_isa_port bt_isa_ports[]; 412 413 #define BT_NUM_ISAPORTS 6 414 415 typedef enum { 416 BIO_330 = 0, 417 BIO_334 = 1, 418 BIO_230 = 2, 419 BIO_234 = 3, 420 BIO_130 = 4, 421 BIO_134 = 5, 422 BIO_DISABLED = 6, 423 BIO_DISABLED2 = 7 424 } isa_compat_io_t; 425 426 typedef struct { 427 u_int8_t io_port; 428 u_int8_t irq_num; 429 u_int8_t low_byte_term :1, 430 high_byte_term :1, 431 :2, 432 jp1_status :1, 433 jp2_status :1, 434 jp3_status :1, 435 :1; 436 u_int8_t reserved; 437 } pci_info_data_t; 438 439 typedef struct { 440 u_int8_t ascii_model[5]; /* Fifth byte is always 0 */ 441 } ha_model_data_t; 442 443 typedef struct { 444 u_int8_t sync_rate[16]; /* Sync in 10ns units */ 445 } target_sync_info_data_t; 446 447 typedef struct { 448 u_int8_t bus_type; 449 u_int8_t bios_addr; 450 u_int16_t max_sg; 451 u_int8_t num_mboxes; 452 u_int8_t mbox_base[4]; 453 u_int8_t :2, 454 sync_neg10MB :1, 455 floppy_disable :1, 456 floppy_secondary_port :1, 457 burst_mode_enabled :1, 458 level_trigger_ints :1, 459 :1; 460 u_int8_t fw_ver_bytes_2_to_4[3]; 461 u_int8_t wide_bus :1, 462 diff_bus :1, 463 scam_capable :1, 464 ultra_scsi :1, 465 auto_term :1, 466 :3; 467 } esetup_info_data_t; 468 469 typedef struct { 470 u_int32_t len; 471 u_int32_t addr; 472 } bt_sg_t; 473 474 /********************** Mail Box definitions *******************************/ 475 476 typedef enum { 477 BMBO_FREE = 0x0, /* MBO intry is free */ 478 BMBO_START = 0x1, /* MBO activate entry */ 479 BMBO_ABORT = 0x2 /* MBO abort entry */ 480 } bt_mbo_action_code_t; 481 482 typedef struct bt_mbox_out { 483 u_int32_t ccb_addr; 484 u_int8_t reserved[3]; 485 u_int8_t action_code; 486 } bt_mbox_out_t; 487 488 typedef enum { 489 BMBI_FREE = 0x0, /* MBI entry is free */ 490 BMBI_OK = 0x1, /* completed without error */ 491 BMBI_ABORT = 0x2, /* aborted ccb */ 492 BMBI_NOT_FOUND = 0x3, /* Tried to abort invalid CCB */ 493 BMBI_ERROR = 0x4 /* Completed with error */ 494 } bt_mbi_comp_code_t; 495 496 typedef struct bt_mbox_in { 497 u_int32_t ccb_addr; 498 u_int8_t btstat; 499 u_int8_t sdstat; 500 u_int8_t reserved; 501 u_int8_t comp_code; 502 } bt_mbox_in_t; 503 504 /***************** Compiled Probe Information *******************************/ 505 struct bt_probe_info { 506 int drq; 507 int irq; 508 }; 509 510 /****************** Hardware CCB definition *********************************/ 511 typedef enum { 512 INITIATOR_CCB = 0x00, 513 INITIATOR_SG_CCB = 0x02, 514 INITIATOR_CCB_WRESID = 0x03, 515 INITIATOR_SG_CCB_WRESID = 0x04, 516 INITIATOR_BUS_DEV_RESET = 0x81 517 } bt_ccb_opcode_t; 518 519 typedef enum { 520 BTSTAT_NOERROR = 0x00, 521 BTSTAT_LINKED_CMD_COMPLETE = 0x0A, 522 BTSTAT_LINKED_CMD_FLAG_COMPLETE = 0x0B, 523 BTSTAT_DATAUNDERUN_ERROR = 0x0C, 524 BTSTAT_SELTIMEOUT = 0x11, 525 BTSTAT_DATARUN_ERROR = 0x12, 526 BTSTAT_UNEXPECTED_BUSFREE = 0x13, 527 BTSTAT_INVALID_PHASE = 0x14, 528 BTSTAT_INVALID_ACTION_CODE = 0x15, 529 BTSTAT_INVALID_OPCODE = 0x16, 530 BTSTAT_LINKED_CCB_LUN_MISMATCH = 0x17, 531 BTSTAT_INVALID_CCB_OR_SG_PARAM = 0x1A, 532 BTSTAT_AUTOSENSE_FAILED = 0x1B, 533 BTSTAT_TAGGED_MSG_REJECTED = 0x1C, 534 BTSTAT_UNSUPPORTED_MSG_RECEIVED = 0x1D, 535 BTSTAT_HARDWARE_FAILURE = 0x20, 536 BTSTAT_TARGET_IGNORED_ATN = 0x21, 537 BTSTAT_HA_SCSI_BUS_RESET = 0x22, 538 BTSTAT_OTHER_SCSI_BUS_RESET = 0x23, 539 BTSTAT_INVALID_RECONNECT = 0x24, 540 BTSTAT_HA_BDR = 0x25, 541 BTSTAT_ABORT_QUEUE_GENERATED = 0x26, 542 BTSTAT_HA_SOFTWARE_ERROR = 0x27, 543 BTSTAT_HA_WATCHDOG_ERROR = 0x28, 544 BTSTAT_SCSI_PERROR_DETECTED = 0x30 545 } btstat_t; 546 547 struct bt_hccb { 548 u_int8_t opcode; 549 u_int8_t :3, 550 datain :1, 551 dataout :1, 552 wide_tag_enable :1, /* Wide Lun CCB format */ 553 wide_tag_type :2; /* Wide Lun CCB format */ 554 u_int8_t cmd_len; 555 u_int8_t sense_len; 556 int32_t data_len; /* residuals can be negative */ 557 u_int32_t data_addr; 558 u_int8_t reserved[2]; 559 u_int8_t btstat; 560 u_int8_t sdstat; 561 u_int8_t target_id; 562 u_int8_t target_lun :5, 563 tag_enable :1, 564 tag_type :2; 565 u_int8_t scsi_cdb[12]; 566 u_int8_t reserved2[6]; 567 u_int32_t sense_addr; 568 }; 569 570 typedef enum { 571 BCCB_FREE = 0x0, 572 BCCB_ACTIVE = 0x1, 573 BCCB_DEVICE_RESET = 0x2, 574 BCCB_RELEASE_SIMQ = 0x4 575 } bccb_flags_t; 576 577 struct bt_ccb { 578 struct bt_hccb hccb; 579 SLIST_ENTRY(bt_ccb) links; 580 u_int32_t flags; 581 union ccb *ccb; 582 bus_dmamap_t dmamap; 583 bt_sg_t *sg_list; 584 u_int32_t sg_list_phys; 585 }; 586 587 struct sg_map_node { 588 bus_dmamap_t sg_dmamap; 589 bus_addr_t sg_physaddr; 590 bt_sg_t* sg_vaddr; 591 SLIST_ENTRY(sg_map_node) links; 592 }; 593 594 struct bt_softc { 595 struct device *dev; 596 struct resource *port; 597 struct resource *irq; 598 struct resource *drq; 599 void *ih; 600 bus_space_tag_t tag; 601 bus_space_handle_t bsh; 602 struct cam_sim *sim; 603 struct cam_path *path; 604 bt_mbox_out_t *cur_outbox; 605 bt_mbox_in_t *cur_inbox; 606 bt_mbox_out_t *last_outbox; 607 bt_mbox_in_t *last_inbox; 608 struct bt_ccb *bt_ccb_array; 609 SLIST_HEAD(,bt_ccb) free_bt_ccbs; 610 LIST_HEAD(,ccb_hdr) pending_ccbs; 611 u_int active_ccbs; 612 u_int32_t bt_ccb_physbase; 613 bt_mbox_in_t *in_boxes; 614 bt_mbox_out_t *out_boxes; 615 struct scsi_sense_data *sense_buffers; 616 u_int32_t sense_buffers_physbase; 617 struct bt_ccb *recovery_bccb; 618 u_int num_boxes; 619 bus_dma_tag_t parent_dmat; /* 620 * All dmat's derive from 621 * the dmat defined by our 622 * bus. 623 */ 624 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 625 bus_dma_tag_t mailbox_dmat; /* dmat for our mailboxes */ 626 bus_dmamap_t mailbox_dmamap; 627 bus_dma_tag_t ccb_dmat; /* dmat for our ccb array */ 628 bus_dmamap_t ccb_dmamap; 629 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 630 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 631 bus_dmamap_t sense_dmamap; 632 SLIST_HEAD(, sg_map_node) sg_maps; 633 bus_addr_t mailbox_physbase; 634 u_int num_ccbs; /* Number of CCBs malloc'd */ 635 u_int max_ccbs; /* Maximum allocatable CCBs */ 636 u_int max_sg; 637 u_int unit; 638 u_int scsi_id; 639 u_int32_t extended_trans :1, 640 wide_bus :1, 641 diff_bus :1, 642 ultra_scsi :1, 643 extended_lun :1, 644 strict_rr :1, 645 tag_capable :1, 646 wide_lun_ccb :1, 647 resource_shortage :1, 648 level_trigger_ints:1, 649 :22; 650 u_int16_t tags_permitted; 651 u_int16_t disc_permitted; 652 u_int16_t sync_permitted; 653 u_int16_t fast_permitted; 654 u_int16_t ultra_permitted; 655 u_int16_t wide_permitted; 656 u_int8_t init_level; 657 volatile u_int8_t command_cmp; 658 volatile u_int8_t latched_status; 659 u_int32_t bios_addr; 660 char firmware_ver[6]; 661 char model[5]; 662 }; 663 664 extern u_long bt_unit; 665 666 #define BT_TEMP_UNIT 0xFF /* Unit for probes */ 667 void bt_init_softc(device_t dev, 668 struct resource *port, 669 struct resource *irq, 670 struct resource *drq); 671 void bt_free_softc(device_t dev); 672 int bt_port_probe(device_t dev, 673 struct bt_probe_info *info); 674 int bt_probe(device_t dev); 675 int bt_fetch_adapter_info(device_t dev); 676 int bt_init(device_t dev); 677 int bt_attach(device_t dev); 678 void bt_intr(void *arg); 679 int bt_check_probed_iop(u_int ioport); 680 void bt_mark_probed_bio(isa_compat_io_t port); 681 void bt_mark_probed_iop(u_int ioport); 682 void bt_find_probe_range(int ioport, 683 int *port_index, 684 int *max_port_index); 685 686 int bt_iop_from_bio(isa_compat_io_t bio_index); 687 688 #define DEFAULT_CMD_TIMEOUT 100000 /* 10 sec */ 689 int bt_cmd(struct bt_softc *bt, bt_op_t opcode, 690 u_int8_t *params, u_int param_len, 691 u_int8_t *reply_data, u_int reply_len, 692 u_int cmd_timeout); 693 694 #define bt_name(bt) device_get_nameunit(bt->dev) 695 696 #define bt_inb(bt, port) \ 697 bus_space_read_1((bt)->tag, (bt)->bsh, port) 698 699 #define bt_outb(bt, port, value) \ 700 bus_space_write_1((bt)->tag, (bt)->bsh, port, value) 701 702 #endif /* _BT_H_ */ 703