1 /*- 2 * Copyright (c) 1997-2008 by Matthew Jacob 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/isp/isp_pci.c,v 1.159 2011/11/16 02:52:24 mjacob Exp $ 27 */ 28 /* 29 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 30 * FreeBSD Version. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/linker.h> 38 #include <sys/firmware.h> 39 #include <sys/bus.h> 40 #include <sys/stdint.h> 41 #include <bus/pci/pcireg.h> 42 #include <bus/pci/pcivar.h> 43 #include <sys/rman.h> 44 #include <sys/malloc.h> 45 #include <sys/uio.h> 46 47 #include <dev/disk/isp/isp_freebsd.h> 48 49 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 50 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 51 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 52 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 53 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 54 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 55 static int isp_pci_rd_isr(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 56 static int isp_pci_rd_isr_2300(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 57 static int isp_pci_rd_isr_2400(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 58 static int isp_pci_mbxdma(ispsoftc_t *); 59 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *); 60 61 62 static void isp_pci_reset0(ispsoftc_t *); 63 static void isp_pci_reset1(ispsoftc_t *); 64 static void isp_pci_dumpregs(ispsoftc_t *, const char *); 65 66 static struct ispmdvec mdvec = { 67 isp_pci_rd_isr, 68 isp_pci_rd_reg, 69 isp_pci_wr_reg, 70 isp_pci_mbxdma, 71 isp_pci_dmasetup, 72 isp_common_dmateardown, 73 isp_pci_reset0, 74 isp_pci_reset1, 75 isp_pci_dumpregs, 76 NULL, 77 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 78 }; 79 80 static struct ispmdvec mdvec_1080 = { 81 isp_pci_rd_isr, 82 isp_pci_rd_reg_1080, 83 isp_pci_wr_reg_1080, 84 isp_pci_mbxdma, 85 isp_pci_dmasetup, 86 isp_common_dmateardown, 87 isp_pci_reset0, 88 isp_pci_reset1, 89 isp_pci_dumpregs, 90 NULL, 91 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 92 }; 93 94 static struct ispmdvec mdvec_12160 = { 95 isp_pci_rd_isr, 96 isp_pci_rd_reg_1080, 97 isp_pci_wr_reg_1080, 98 isp_pci_mbxdma, 99 isp_pci_dmasetup, 100 isp_common_dmateardown, 101 isp_pci_reset0, 102 isp_pci_reset1, 103 isp_pci_dumpregs, 104 NULL, 105 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 106 }; 107 108 static struct ispmdvec mdvec_2100 = { 109 isp_pci_rd_isr, 110 isp_pci_rd_reg, 111 isp_pci_wr_reg, 112 isp_pci_mbxdma, 113 isp_pci_dmasetup, 114 isp_common_dmateardown, 115 isp_pci_reset0, 116 isp_pci_reset1, 117 isp_pci_dumpregs 118 }; 119 120 static struct ispmdvec mdvec_2200 = { 121 isp_pci_rd_isr, 122 isp_pci_rd_reg, 123 isp_pci_wr_reg, 124 isp_pci_mbxdma, 125 isp_pci_dmasetup, 126 isp_common_dmateardown, 127 isp_pci_reset0, 128 isp_pci_reset1, 129 isp_pci_dumpregs 130 }; 131 132 static struct ispmdvec mdvec_2300 = { 133 isp_pci_rd_isr_2300, 134 isp_pci_rd_reg, 135 isp_pci_wr_reg, 136 isp_pci_mbxdma, 137 isp_pci_dmasetup, 138 isp_common_dmateardown, 139 isp_pci_reset0, 140 isp_pci_reset1, 141 isp_pci_dumpregs 142 }; 143 144 static struct ispmdvec mdvec_2400 = { 145 isp_pci_rd_isr_2400, 146 isp_pci_rd_reg_2400, 147 isp_pci_wr_reg_2400, 148 isp_pci_mbxdma, 149 isp_pci_dmasetup, 150 isp_common_dmateardown, 151 isp_pci_reset0, 152 isp_pci_reset1, 153 NULL 154 }; 155 156 static struct ispmdvec mdvec_2500 = { 157 isp_pci_rd_isr_2400, 158 isp_pci_rd_reg_2400, 159 isp_pci_wr_reg_2400, 160 isp_pci_mbxdma, 161 isp_pci_dmasetup, 162 isp_common_dmateardown, 163 isp_pci_reset0, 164 isp_pci_reset1, 165 NULL 166 }; 167 168 #ifndef PCIM_CMD_INVEN 169 #define PCIM_CMD_INVEN 0x10 170 #endif 171 #ifndef PCIM_CMD_BUSMASTEREN 172 #define PCIM_CMD_BUSMASTEREN 0x0004 173 #endif 174 #ifndef PCIM_CMD_PERRESPEN 175 #define PCIM_CMD_PERRESPEN 0x0040 176 #endif 177 #ifndef PCIM_CMD_SEREN 178 #define PCIM_CMD_SEREN 0x0100 179 #endif 180 #ifndef PCIM_CMD_INTX_DISABLE 181 #define PCIM_CMD_INTX_DISABLE 0x0400 182 #endif 183 184 #ifndef PCIR_COMMAND 185 #define PCIR_COMMAND 0x04 186 #endif 187 188 #ifndef PCIR_CACHELNSZ 189 #define PCIR_CACHELNSZ 0x0c 190 #endif 191 192 #ifndef PCIR_LATTIMER 193 #define PCIR_LATTIMER 0x0d 194 #endif 195 196 #ifndef PCIR_ROMADDR 197 #define PCIR_ROMADDR 0x30 198 #endif 199 200 #ifndef PCI_VENDOR_QLOGIC 201 #define PCI_VENDOR_QLOGIC 0x1077 202 #endif 203 204 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 205 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 206 #endif 207 208 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 209 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 210 #endif 211 212 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 213 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 214 #endif 215 216 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 217 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 218 #endif 219 220 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 221 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 222 #endif 223 224 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 225 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 226 #endif 227 228 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 229 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 230 #endif 231 232 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 233 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 234 #endif 235 236 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 237 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 238 #endif 239 240 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 241 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 242 #endif 243 244 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 245 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 246 #endif 247 248 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 249 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 250 #endif 251 252 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 253 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 254 #endif 255 256 #ifndef PCI_PRODUCT_QLOGIC_ISP2532 257 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 258 #endif 259 260 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 261 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 262 #endif 263 264 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 265 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 266 #endif 267 268 #ifndef PCI_PRODUCT_QLOGIC_ISP5432 269 #define PCI_PRODUCT_QLOGIC_ISP5432 0x5432 270 #endif 271 272 #define PCI_QLOGIC_ISP5432 \ 273 ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC) 274 275 #define PCI_QLOGIC_ISP1020 \ 276 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 277 278 #define PCI_QLOGIC_ISP1080 \ 279 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 280 281 #define PCI_QLOGIC_ISP10160 \ 282 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 283 284 #define PCI_QLOGIC_ISP12160 \ 285 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 286 287 #define PCI_QLOGIC_ISP1240 \ 288 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 289 290 #define PCI_QLOGIC_ISP1280 \ 291 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 292 293 #define PCI_QLOGIC_ISP2100 \ 294 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 295 296 #define PCI_QLOGIC_ISP2200 \ 297 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 298 299 #define PCI_QLOGIC_ISP2300 \ 300 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 301 302 #define PCI_QLOGIC_ISP2312 \ 303 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 304 305 #define PCI_QLOGIC_ISP2322 \ 306 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 307 308 #define PCI_QLOGIC_ISP2422 \ 309 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 310 311 #define PCI_QLOGIC_ISP2432 \ 312 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 313 314 #define PCI_QLOGIC_ISP2532 \ 315 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 316 317 #define PCI_QLOGIC_ISP6312 \ 318 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 319 320 #define PCI_QLOGIC_ISP6322 \ 321 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 322 323 /* 324 * Odd case for some AMI raid cards... We need to *not* attach to this. 325 */ 326 #define AMI_RAID_SUBVENDOR_ID 0x101e 327 328 #define IO_MAP_REG 0x10 329 #define MEM_MAP_REG 0x14 330 331 #define PCI_DFLT_LTNCY 0x40 332 #define PCI_DFLT_LNSZ 0x10 333 334 static int isp_pci_probe (device_t); 335 static int isp_pci_attach (device_t); 336 static int isp_pci_detach (device_t); 337 338 339 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 340 struct isp_pcisoftc { 341 ispsoftc_t pci_isp; 342 device_t pci_dev; 343 struct resource * regs; 344 void * irq; 345 int irq_type; 346 int iqd; 347 int rtp; 348 int rgd; 349 void * ih; 350 int16_t pci_poff[_NREG_BLKS]; 351 bus_dma_tag_t dmat; 352 }; 353 354 static int isp_msi_enable = 1; 355 TUNABLE_INT("hw.isp.msi.enable", &isp_msi_enable); 356 357 static device_method_t isp_pci_methods[] = { 358 /* Device interface */ 359 DEVMETHOD(device_probe, isp_pci_probe), 360 DEVMETHOD(device_attach, isp_pci_attach), 361 DEVMETHOD(device_detach, isp_pci_detach), 362 DEVMETHOD_END 363 }; 364 365 static driver_t isp_pci_driver = { 366 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 367 }; 368 static devclass_t isp_devclass; 369 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, NULL, NULL); 370 371 static int 372 isp_pci_probe(device_t dev) 373 { 374 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 375 case PCI_QLOGIC_ISP1020: 376 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 377 break; 378 case PCI_QLOGIC_ISP1080: 379 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 380 break; 381 case PCI_QLOGIC_ISP1240: 382 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 383 break; 384 case PCI_QLOGIC_ISP1280: 385 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 386 break; 387 case PCI_QLOGIC_ISP10160: 388 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 389 break; 390 case PCI_QLOGIC_ISP12160: 391 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 392 return (ENXIO); 393 } 394 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 395 break; 396 case PCI_QLOGIC_ISP2100: 397 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 398 break; 399 case PCI_QLOGIC_ISP2200: 400 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 401 break; 402 case PCI_QLOGIC_ISP2300: 403 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 404 break; 405 case PCI_QLOGIC_ISP2312: 406 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 407 break; 408 case PCI_QLOGIC_ISP2322: 409 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 410 break; 411 case PCI_QLOGIC_ISP2422: 412 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 413 break; 414 case PCI_QLOGIC_ISP2432: 415 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 416 break; 417 case PCI_QLOGIC_ISP2532: 418 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter"); 419 break; 420 case PCI_QLOGIC_ISP5432: 421 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter"); 422 break; 423 case PCI_QLOGIC_ISP6312: 424 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 425 break; 426 case PCI_QLOGIC_ISP6322: 427 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 428 break; 429 default: 430 return (ENXIO); 431 } 432 if (isp_announced == 0 && bootverbose) { 433 kprintf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 434 "Core Version %d.%d\n", 435 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 436 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 437 isp_announced++; 438 } 439 /* 440 * XXXX: Here is where we might load the f/w module 441 * XXXX: (or increase a reference count to it). 442 */ 443 return (BUS_PROBE_DEFAULT); 444 } 445 446 static void 447 isp_get_generic_options(device_t dev, ispsoftc_t *isp, int *nvp) 448 { 449 int tval; 450 451 /* 452 * Figure out if we're supposed to skip this one. 453 */ 454 tval = 0; 455 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "disable", &tval) == 0 && tval) { 456 device_printf(dev, "disabled at user request\n"); 457 isp->isp_osinfo.disabled = 1; 458 return; 459 } 460 461 tval = 0; 462 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) { 463 isp->isp_confopts |= ISP_CFG_NORELOAD; 464 } 465 tval = 0; 466 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) { 467 isp->isp_confopts |= ISP_CFG_NONVRAM; 468 } 469 tval = 0; 470 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval); 471 if (tval) { 472 isp->isp_dblev = tval; 473 } else { 474 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 475 } 476 if (bootverbose) { 477 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 478 } 479 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval); 480 if (tval > 0 && tval < 127) { 481 *nvp = tval; 482 } else { 483 *nvp = 0; 484 } 485 tval = 1; 486 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "autoconfig", &tval); 487 isp_autoconfig = tval; 488 tval = 7; 489 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval); 490 isp_quickboot_time = tval; 491 492 tval = 0; 493 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "forcemulti", &tval) == 0 && tval != 0) { 494 isp->isp_osinfo.forcemulti = 1; 495 } 496 } 497 498 static void 499 isp_get_pci_options(device_t dev, int *m1, int *m2) 500 { 501 int tval; 502 /* 503 * Which we should try first - memory mapping or i/o mapping? 504 * 505 * We used to try memory first followed by i/o on alpha, otherwise 506 * the reverse, but we should just try memory first all the time now. 507 */ 508 *m1 = PCIM_CMD_MEMEN; 509 *m2 = PCIM_CMD_PORTEN; 510 511 tval = 0; 512 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &tval) == 0 && tval != 0) { 513 *m1 = PCIM_CMD_PORTEN; 514 *m2 = PCIM_CMD_MEMEN; 515 } 516 tval = 0; 517 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_memmap", &tval) == 0 && tval != 0) { 518 *m1 = PCIM_CMD_MEMEN; 519 *m2 = PCIM_CMD_PORTEN; 520 } 521 } 522 523 static void 524 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp) 525 { 526 const char *sptr; 527 int tval; 528 529 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "iid", &tval)) { 530 if (IS_FC(isp)) { 531 ISP_FC_PC(isp, chan)->default_id = 109 - chan; 532 } else { 533 #ifdef __sparc64__ 534 ISP_SPI_PC(isp, chan)->iid = OF_getscsinitid(dev); 535 #else 536 ISP_SPI_PC(isp, chan)->iid = 7; 537 #endif 538 } 539 } else { 540 if (IS_FC(isp)) { 541 ISP_FC_PC(isp, chan)->default_id = tval - chan; 542 } else { 543 ISP_SPI_PC(isp, chan)->iid = tval; 544 } 545 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 546 } 547 548 tval = -1; 549 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "role", &tval) == 0) { 550 switch (tval) { 551 case ISP_ROLE_NONE: 552 case ISP_ROLE_INITIATOR: 553 case ISP_ROLE_TARGET: 554 case ISP_ROLE_INITIATOR|ISP_ROLE_TARGET: 555 device_printf(dev, "setting role to 0x%x\n", tval); 556 break; 557 default: 558 tval = -1; 559 break; 560 } 561 } 562 if (tval == -1) { 563 tval = ISP_DEFAULT_ROLES; 564 } 565 566 if (IS_SCSI(isp)) { 567 ISP_SPI_PC(isp, chan)->def_role = tval; 568 return; 569 } 570 ISP_FC_PC(isp, chan)->def_role = tval; 571 572 tval = 0; 573 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fullduplex", &tval) == 0 && tval != 0) { 574 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 575 } 576 sptr = NULL; 577 if (resource_string_value(device_get_name(dev), device_get_unit(dev), "topology", &sptr) == 0 && sptr != NULL) { 578 if (strcmp(sptr, "lport") == 0) { 579 isp->isp_confopts |= ISP_CFG_LPORT; 580 } else if (strcmp(sptr, "nport") == 0) { 581 isp->isp_confopts |= ISP_CFG_NPORT; 582 } else if (strcmp(sptr, "lport-only") == 0) { 583 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 584 } else if (strcmp(sptr, "nport-only") == 0) { 585 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 586 } 587 } 588 589 /* 590 * Because the resource_*_value functions can neither return 591 * 64 bit integer values, nor can they be directly coerced 592 * to interpret the right hand side of the assignment as 593 * you want them to interpret it, we have to force WWN 594 * hint replacement to specify WWN strings with a leading 595 * 'w' (e..g w50000000aaaa0001). Sigh. 596 */ 597 sptr = NULL; 598 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "portwwn", &sptr); 599 if (tval == 0 && sptr != NULL && *sptr++ == 'w') { 600 char *eptr = NULL; 601 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16); 602 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) { 603 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 604 ISP_FC_PC(isp, chan)->def_wwpn = 0; 605 } 606 } 607 608 sptr = NULL; 609 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "nodewwn", &sptr); 610 if (tval == 0 && sptr != NULL && *sptr++ == 'w') { 611 char *eptr = NULL; 612 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16); 613 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) { 614 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 615 ISP_FC_PC(isp, chan)->def_wwnn = 0; 616 } 617 } 618 619 tval = 0; 620 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "hysteresis", &tval); 621 if (tval >= 0 && tval < 256) { 622 ISP_FC_PC(isp, chan)->hysteresis = tval; 623 } else { 624 ISP_FC_PC(isp, chan)->hysteresis = isp_fabric_hysteresis; 625 } 626 627 tval = -1; 628 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "loop_down_limit", &tval); 629 if (tval >= 0 && tval < 0xffff) { 630 ISP_FC_PC(isp, chan)->loop_down_limit = tval; 631 } else { 632 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit; 633 } 634 635 tval = -1; 636 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "gone_device_time", &tval); 637 if (tval >= 0 && tval < 0xffff) { 638 ISP_FC_PC(isp, chan)->gone_device_time = tval; 639 } else { 640 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time; 641 } 642 } 643 644 static int 645 isp_pci_attach(device_t dev) 646 { 647 int i, m1, m2, locksetup = 0; 648 int isp_nvports = 0; 649 uint32_t data, cmd, linesz, did; 650 struct isp_pcisoftc *pcs; 651 ispsoftc_t *isp; 652 size_t psize, xsize; 653 char fwname[32]; 654 u_int irq_flags; 655 656 pcs = device_get_softc(dev); 657 if (pcs == NULL) { 658 device_printf(dev, "cannot get softc\n"); 659 return (ENOMEM); 660 } 661 memset(pcs, 0, sizeof (*pcs)); 662 663 pcs->pci_dev = dev; 664 isp = &pcs->pci_isp; 665 isp->isp_dev = dev; 666 isp->isp_nchan = 1; 667 668 /* 669 * Get Generic Options 670 */ 671 isp_get_generic_options(dev, isp, &isp_nvports); 672 673 /* 674 * Check to see if options have us disabled 675 */ 676 if (isp->isp_osinfo.disabled) { 677 /* 678 * But return zero to preserve unit numbering 679 */ 680 return (0); 681 } 682 683 /* 684 * Get PCI options- which in this case are just mapping preferences. 685 */ 686 isp_get_pci_options(dev, &m1, &m2); 687 688 linesz = PCI_DFLT_LNSZ; 689 pcs->irq = pcs->regs = NULL; 690 pcs->rgd = pcs->rtp = pcs->iqd = 0; 691 692 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 693 if (cmd & m1) { 694 pcs->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 695 pcs->rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 696 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 697 } 698 if (pcs->regs == NULL && (cmd & m2)) { 699 pcs->rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 700 pcs->rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 701 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 702 } 703 if (pcs->regs == NULL) { 704 device_printf(dev, "unable to map any ports\n"); 705 goto bad; 706 } 707 if (bootverbose) { 708 device_printf(dev, "using %s space register mapping\n", (pcs->rgd == IO_MAP_REG)? "I/O" : "Memory"); 709 } 710 isp->isp_bus_tag = rman_get_bustag(pcs->regs); 711 isp->isp_bus_handle = rman_get_bushandle(pcs->regs); 712 713 pcs->pci_dev = dev; 714 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 715 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 716 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 717 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 718 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 719 720 switch (pci_get_devid(dev)) { 721 case PCI_QLOGIC_ISP1020: 722 did = 0x1040; 723 isp->isp_mdvec = &mdvec; 724 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 725 break; 726 case PCI_QLOGIC_ISP1080: 727 did = 0x1080; 728 isp->isp_mdvec = &mdvec_1080; 729 isp->isp_type = ISP_HA_SCSI_1080; 730 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 731 break; 732 case PCI_QLOGIC_ISP1240: 733 did = 0x1080; 734 isp->isp_mdvec = &mdvec_1080; 735 isp->isp_type = ISP_HA_SCSI_1240; 736 isp->isp_nchan = 2; 737 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 738 break; 739 case PCI_QLOGIC_ISP1280: 740 did = 0x1080; 741 isp->isp_mdvec = &mdvec_1080; 742 isp->isp_type = ISP_HA_SCSI_1280; 743 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 744 break; 745 case PCI_QLOGIC_ISP10160: 746 did = 0x12160; 747 isp->isp_mdvec = &mdvec_12160; 748 isp->isp_type = ISP_HA_SCSI_10160; 749 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 750 break; 751 case PCI_QLOGIC_ISP12160: 752 did = 0x12160; 753 isp->isp_nchan = 2; 754 isp->isp_mdvec = &mdvec_12160; 755 isp->isp_type = ISP_HA_SCSI_12160; 756 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 757 break; 758 case PCI_QLOGIC_ISP2100: 759 did = 0x2100; 760 isp->isp_mdvec = &mdvec_2100; 761 isp->isp_type = ISP_HA_FC_2100; 762 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 763 if (pci_get_revid(dev) < 3) { 764 /* 765 * XXX: Need to get the actual revision 766 * XXX: number of the 2100 FB. At any rate, 767 * XXX: lower cache line size for early revision 768 * XXX; boards. 769 */ 770 linesz = 1; 771 } 772 break; 773 case PCI_QLOGIC_ISP2200: 774 did = 0x2200; 775 isp->isp_mdvec = &mdvec_2200; 776 isp->isp_type = ISP_HA_FC_2200; 777 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 778 break; 779 case PCI_QLOGIC_ISP2300: 780 did = 0x2300; 781 isp->isp_mdvec = &mdvec_2300; 782 isp->isp_type = ISP_HA_FC_2300; 783 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 784 break; 785 case PCI_QLOGIC_ISP2312: 786 case PCI_QLOGIC_ISP6312: 787 did = 0x2300; 788 isp->isp_mdvec = &mdvec_2300; 789 isp->isp_type = ISP_HA_FC_2312; 790 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 791 break; 792 case PCI_QLOGIC_ISP2322: 793 case PCI_QLOGIC_ISP6322: 794 did = 0x2322; 795 isp->isp_mdvec = &mdvec_2300; 796 isp->isp_type = ISP_HA_FC_2322; 797 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 798 break; 799 case PCI_QLOGIC_ISP2422: 800 case PCI_QLOGIC_ISP2432: 801 did = 0x2400; 802 isp->isp_nchan += isp_nvports; 803 isp->isp_mdvec = &mdvec_2400; 804 isp->isp_type = ISP_HA_FC_2400; 805 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 806 break; 807 case PCI_QLOGIC_ISP2532: 808 did = 0x2500; 809 isp->isp_nchan += isp_nvports; 810 isp->isp_mdvec = &mdvec_2500; 811 isp->isp_type = ISP_HA_FC_2500; 812 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 813 break; 814 case PCI_QLOGIC_ISP5432: 815 did = 0x2500; 816 isp->isp_mdvec = &mdvec_2500; 817 isp->isp_type = ISP_HA_FC_2500; 818 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 819 break; 820 default: 821 device_printf(dev, "unknown device type\n"); 822 goto bad; 823 break; 824 } 825 isp->isp_revision = pci_get_revid(dev); 826 827 if (IS_FC(isp)) { 828 psize = sizeof (fcparam); 829 xsize = sizeof (struct isp_fc); 830 } else { 831 psize = sizeof (sdparam); 832 xsize = sizeof (struct isp_spi); 833 } 834 psize *= isp->isp_nchan; 835 xsize *= isp->isp_nchan; 836 isp->isp_param = kmalloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 837 if (isp->isp_param == NULL) { 838 device_printf(dev, "cannot allocate parameter data\n"); 839 goto bad; 840 } 841 isp->isp_osinfo.pc.ptr = kmalloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO); 842 if (isp->isp_osinfo.pc.ptr == NULL) { 843 device_printf(dev, "cannot allocate parameter data\n"); 844 goto bad; 845 } 846 847 /* 848 * Now that we know who we are (roughly) get/set specific options 849 */ 850 for (i = 0; i < isp->isp_nchan; i++) { 851 isp_get_specific_options(dev, i, isp); 852 } 853 854 /* 855 * The 'it' suffix really only matters for SCSI cards in target mode. 856 */ 857 isp->isp_osinfo.fw = NULL; 858 if (IS_SCSI(isp) && (ISP_SPI_PC(isp, 0)->def_role & ISP_ROLE_TARGET)) { 859 ksnprintf(fwname, sizeof (fwname), "isp_%04x_it", did); 860 isp->isp_osinfo.fw = firmware_get(fwname); 861 } else if (IS_24XX(isp) && (isp->isp_nchan > 1 || isp->isp_osinfo.forcemulti)) { 862 ksnprintf(fwname, sizeof (fwname), "isp_%04x_multi", did); 863 isp->isp_osinfo.fw = firmware_get(fwname); 864 } 865 if (isp->isp_osinfo.fw == NULL) { 866 ksnprintf(fwname, sizeof (fwname), "isp_%04x", did); 867 isp->isp_osinfo.fw = firmware_get(fwname); 868 } 869 if (isp->isp_osinfo.fw != NULL) { 870 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 871 } 872 873 /* 874 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 875 * are set. 876 */ 877 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 878 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 879 880 if (IS_2300(isp)) { /* per QLogic errata */ 881 cmd &= ~PCIM_CMD_INVEN; 882 } 883 884 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 885 cmd &= ~PCIM_CMD_INTX_DISABLE; 886 } 887 888 if (IS_24XX(isp)) { 889 cmd &= ~PCIM_CMD_INTX_DISABLE; 890 } 891 892 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 893 894 /* 895 * Make sure the Cache Line Size register is set sensibly. 896 */ 897 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 898 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 899 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d from %d", linesz, data); 900 data = linesz; 901 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 902 } 903 904 /* 905 * Make sure the Latency Timer is sane. 906 */ 907 data = pci_read_config(dev, PCIR_LATTIMER, 1); 908 if (data < PCI_DFLT_LTNCY) { 909 data = PCI_DFLT_LTNCY; 910 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 911 pci_write_config(dev, PCIR_LATTIMER, data, 1); 912 } 913 914 /* 915 * Make sure we've disabled the ROM. 916 */ 917 data = pci_read_config(dev, PCIR_ROMADDR, 4); 918 data &= ~1; 919 pci_write_config(dev, PCIR_ROMADDR, data, 4); 920 921 pcs->irq_type = pci_alloc_1intr(dev, isp_msi_enable, &pcs->iqd, 922 &irq_flags); 923 pcs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &pcs->iqd, 924 irq_flags); 925 if (pcs->irq == NULL) { 926 device_printf(dev, "could not allocate interrupt\n"); 927 goto bad; 928 } 929 930 /* Make sure the lock is set up. */ 931 lockinit(&isp->isp_osinfo.lock, "isp", 0, LK_CANRECURSE); 932 locksetup++; 933 934 if (isp_setup_intr(dev, pcs->irq, ISP_IFLAGS, isp_platform_intr, isp, &pcs->ih, NULL)) { 935 device_printf(dev, "could not setup interrupt\n"); 936 goto bad; 937 } 938 939 /* 940 * Last minute checks... 941 */ 942 if (IS_23XX(isp) || IS_24XX(isp)) { 943 isp->isp_port = pci_get_function(dev); 944 } 945 946 /* 947 * Make sure we're in reset state. 948 */ 949 ISP_LOCK(isp); 950 isp_reset(isp, 1); 951 if (isp->isp_state != ISP_RESETSTATE) { 952 ISP_UNLOCK(isp); 953 goto bad; 954 } 955 isp_init(isp); 956 if (isp->isp_state == ISP_INITSTATE) { 957 isp->isp_state = ISP_RUNSTATE; 958 } 959 ISP_UNLOCK(isp); 960 if (isp_attach(isp)) { 961 ISP_LOCK(isp); 962 isp_uninit(isp); 963 ISP_UNLOCK(isp); 964 goto bad; 965 } 966 return (0); 967 968 bad: 969 if (pcs->ih) { 970 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 971 } 972 if (locksetup) { 973 lockuninit(&isp->isp_osinfo.lock); 974 } 975 if (pcs->irq) { 976 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 977 } 978 if (pcs->irq_type == PCI_INTR_TYPE_MSI) { 979 pci_release_msi(dev); 980 } 981 if (pcs->regs) { 982 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 983 } 984 if (pcs->pci_isp.isp_param) { 985 kfree(pcs->pci_isp.isp_param, M_DEVBUF); 986 pcs->pci_isp.isp_param = NULL; 987 } 988 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 989 kfree(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 990 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 991 } 992 return (ENXIO); 993 } 994 995 static int 996 isp_pci_detach(device_t dev) 997 { 998 struct isp_pcisoftc *pcs; 999 ispsoftc_t *isp; 1000 int status; 1001 1002 pcs = device_get_softc(dev); 1003 if (pcs == NULL) { 1004 return (ENXIO); 1005 } 1006 isp = (ispsoftc_t *) pcs; 1007 status = isp_detach(isp); 1008 if (status) 1009 return (status); 1010 ISP_LOCK(isp); 1011 isp_uninit(isp); 1012 if (pcs->ih) { 1013 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 1014 } 1015 ISP_UNLOCK(isp); 1016 lockuninit(&isp->isp_osinfo.lock); 1017 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 1018 if (pcs->irq_type == PCI_INTR_TYPE_MSI) { 1019 pci_release_msi(dev); 1020 } 1021 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 1022 if (pcs->pci_isp.isp_param) { 1023 kfree(pcs->pci_isp.isp_param, M_DEVBUF); 1024 pcs->pci_isp.isp_param = NULL; 1025 } 1026 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1027 kfree(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1028 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1029 } 1030 return (0); 1031 } 1032 1033 #define IspVirt2Off(a, x) \ 1034 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1035 _BLK_REG_SHFT] + ((x) & 0xfff)) 1036 1037 #define BXR2(isp, off) \ 1038 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off) 1039 #define BXW2(isp, off, v) \ 1040 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1041 #define BXR4(isp, off) \ 1042 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off) 1043 #define BXW4(isp, off, v) \ 1044 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1045 1046 1047 static ISP_INLINE int 1048 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp) 1049 { 1050 uint32_t val0, val1; 1051 int i = 0; 1052 1053 do { 1054 val0 = BXR2(isp, IspVirt2Off(isp, off)); 1055 val1 = BXR2(isp, IspVirt2Off(isp, off)); 1056 } while (val0 != val1 && ++i < 1000); 1057 if (val0 != val1) { 1058 return (1); 1059 } 1060 *rp = val0; 1061 return (0); 1062 } 1063 1064 static int 1065 isp_pci_rd_isr(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbp) 1066 { 1067 uint16_t isr, sema; 1068 1069 if (IS_2100(isp)) { 1070 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 1071 return (0); 1072 } 1073 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 1074 return (0); 1075 } 1076 } else { 1077 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1078 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1079 } 1080 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1081 isr &= INT_PENDING_MASK(isp); 1082 sema &= BIU_SEMA_LOCK; 1083 if (isr == 0 && sema == 0) { 1084 return (0); 1085 } 1086 *isrp = isr; 1087 if ((*semap = sema) != 0) { 1088 if (IS_2100(isp)) { 1089 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 1090 return (0); 1091 } 1092 } else { 1093 *mbp = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1094 } 1095 } 1096 return (1); 1097 } 1098 1099 static int 1100 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1101 { 1102 uint32_t hccr; 1103 uint32_t r2hisr; 1104 1105 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 1106 *isrp = 0; 1107 return (0); 1108 } 1109 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1110 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1111 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1112 *isrp = 0; 1113 return (0); 1114 } 1115 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 1116 case ISPR2HST_ROM_MBX_OK: 1117 case ISPR2HST_ROM_MBX_FAIL: 1118 case ISPR2HST_MBX_OK: 1119 case ISPR2HST_MBX_FAIL: 1120 case ISPR2HST_ASYNC_EVENT: 1121 *isrp = r2hisr & 0xffff; 1122 *mbox0p = (r2hisr >> 16); 1123 *semap = 1; 1124 return (1); 1125 case ISPR2HST_RIO_16: 1126 *isrp = r2hisr & 0xffff; 1127 *mbox0p = ASYNC_RIO16_1; 1128 *semap = 1; 1129 return (1); 1130 case ISPR2HST_FPOST: 1131 *isrp = r2hisr & 0xffff; 1132 *mbox0p = ASYNC_CMD_CMPLT; 1133 *semap = 1; 1134 return (1); 1135 case ISPR2HST_FPOST_CTIO: 1136 *isrp = r2hisr & 0xffff; 1137 *mbox0p = ASYNC_CTIO_DONE; 1138 *semap = 1; 1139 return (1); 1140 case ISPR2HST_RSPQ_UPDATE: 1141 *isrp = r2hisr & 0xffff; 1142 *mbox0p = 0; 1143 *semap = 0; 1144 return (1); 1145 default: 1146 hccr = ISP_READ(isp, HCCR); 1147 if (hccr & HCCR_PAUSE) { 1148 ISP_WRITE(isp, HCCR, HCCR_RESET); 1149 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR)); 1150 ISP_WRITE(isp, BIU_ICR, 0); 1151 } else { 1152 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1153 } 1154 return (0); 1155 } 1156 } 1157 1158 static int 1159 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1160 { 1161 uint32_t r2hisr; 1162 1163 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1164 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1165 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 1166 *isrp = 0; 1167 return (0); 1168 } 1169 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 1170 case ISP2400R2HST_ROM_MBX_OK: 1171 case ISP2400R2HST_ROM_MBX_FAIL: 1172 case ISP2400R2HST_MBX_OK: 1173 case ISP2400R2HST_MBX_FAIL: 1174 case ISP2400R2HST_ASYNC_EVENT: 1175 *isrp = r2hisr & 0xffff; 1176 *mbox0p = (r2hisr >> 16); 1177 *semap = 1; 1178 return (1); 1179 case ISP2400R2HST_RSPQ_UPDATE: 1180 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 1181 case ISP2400R2HST_ATIO_RQST_UPDATE: 1182 *isrp = r2hisr & 0xffff; 1183 *mbox0p = 0; 1184 *semap = 0; 1185 return (1); 1186 default: 1187 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1188 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1189 return (0); 1190 } 1191 } 1192 1193 static uint32_t 1194 isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1195 { 1196 uint16_t rv; 1197 int oldconf = 0; 1198 1199 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1200 /* 1201 * We will assume that someone has paused the RISC processor. 1202 */ 1203 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1204 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); 1205 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1206 } 1207 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1208 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1209 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1210 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1211 } 1212 return (rv); 1213 } 1214 1215 static void 1216 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1217 { 1218 int oldconf = 0; 1219 1220 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1221 /* 1222 * We will assume that someone has paused the RISC processor. 1223 */ 1224 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1225 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1226 oldconf | BIU_PCI_CONF1_SXP); 1227 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1228 } 1229 BXW2(isp, IspVirt2Off(isp, regoff), val); 1230 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1231 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1232 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1233 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1234 } 1235 1236 } 1237 1238 static uint32_t 1239 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1240 { 1241 uint32_t rv, oc = 0; 1242 1243 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1244 uint32_t tc; 1245 /* 1246 * We will assume that someone has paused the RISC processor. 1247 */ 1248 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1249 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1250 if (regoff & SXP_BANK1_SELECT) 1251 tc |= BIU_PCI1080_CONF1_SXP1; 1252 else 1253 tc |= BIU_PCI1080_CONF1_SXP0; 1254 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1255 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1256 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1257 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1258 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1259 oc | BIU_PCI1080_CONF1_DMA); 1260 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1261 } 1262 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1263 if (oc) { 1264 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1265 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1266 } 1267 return (rv); 1268 } 1269 1270 static void 1271 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1272 { 1273 int oc = 0; 1274 1275 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1276 uint32_t tc; 1277 /* 1278 * We will assume that someone has paused the RISC processor. 1279 */ 1280 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1281 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1282 if (regoff & SXP_BANK1_SELECT) 1283 tc |= BIU_PCI1080_CONF1_SXP1; 1284 else 1285 tc |= BIU_PCI1080_CONF1_SXP0; 1286 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1287 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1288 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1289 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1290 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1291 oc | BIU_PCI1080_CONF1_DMA); 1292 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1293 } 1294 BXW2(isp, IspVirt2Off(isp, regoff), val); 1295 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1296 if (oc) { 1297 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1298 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1299 } 1300 } 1301 1302 static uint32_t 1303 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1304 { 1305 uint32_t rv; 1306 int block = regoff & _BLK_REG_MASK; 1307 1308 switch (block) { 1309 case BIU_BLOCK: 1310 break; 1311 case MBOX_BLOCK: 1312 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1313 case SXP_BLOCK: 1314 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 1315 return (0xffffffff); 1316 case RISC_BLOCK: 1317 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 1318 return (0xffffffff); 1319 case DMA_BLOCK: 1320 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 1321 return (0xffffffff); 1322 default: 1323 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 1324 return (0xffffffff); 1325 } 1326 1327 1328 switch (regoff) { 1329 case BIU2400_FLASH_ADDR: 1330 case BIU2400_FLASH_DATA: 1331 case BIU2400_ICR: 1332 case BIU2400_ISR: 1333 case BIU2400_CSR: 1334 case BIU2400_REQINP: 1335 case BIU2400_REQOUTP: 1336 case BIU2400_RSPINP: 1337 case BIU2400_RSPOUTP: 1338 case BIU2400_PRI_REQINP: 1339 case BIU2400_PRI_REQOUTP: 1340 case BIU2400_ATIO_RSPINP: 1341 case BIU2400_ATIO_RSPOUTP: 1342 case BIU2400_HCCR: 1343 case BIU2400_GPIOD: 1344 case BIU2400_GPIOE: 1345 case BIU2400_HSEMA: 1346 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1347 break; 1348 case BIU2400_R2HSTSLO: 1349 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1350 break; 1351 case BIU2400_R2HSTSHI: 1352 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1353 break; 1354 default: 1355 isp_prt(isp, ISP_LOGERR, 1356 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1357 rv = 0xffffffff; 1358 break; 1359 } 1360 return (rv); 1361 } 1362 1363 static void 1364 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1365 { 1366 int block = regoff & _BLK_REG_MASK; 1367 1368 switch (block) { 1369 case BIU_BLOCK: 1370 break; 1371 case MBOX_BLOCK: 1372 BXW2(isp, IspVirt2Off(isp, regoff), val); 1373 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1374 return; 1375 case SXP_BLOCK: 1376 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1377 return; 1378 case RISC_BLOCK: 1379 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1380 return; 1381 case DMA_BLOCK: 1382 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1383 return; 1384 default: 1385 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1386 regoff); 1387 break; 1388 } 1389 1390 switch (regoff) { 1391 case BIU2400_FLASH_ADDR: 1392 case BIU2400_FLASH_DATA: 1393 case BIU2400_ICR: 1394 case BIU2400_ISR: 1395 case BIU2400_CSR: 1396 case BIU2400_REQINP: 1397 case BIU2400_REQOUTP: 1398 case BIU2400_RSPINP: 1399 case BIU2400_RSPOUTP: 1400 case BIU2400_PRI_REQINP: 1401 case BIU2400_PRI_REQOUTP: 1402 case BIU2400_ATIO_RSPINP: 1403 case BIU2400_ATIO_RSPOUTP: 1404 case BIU2400_HCCR: 1405 case BIU2400_GPIOD: 1406 case BIU2400_GPIOE: 1407 case BIU2400_HSEMA: 1408 BXW4(isp, IspVirt2Off(isp, regoff), val); 1409 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1); 1410 break; 1411 default: 1412 isp_prt(isp, ISP_LOGERR, 1413 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1414 break; 1415 } 1416 } 1417 1418 1419 struct imush { 1420 ispsoftc_t *isp; 1421 caddr_t vbase; 1422 int chan; 1423 int error; 1424 }; 1425 1426 static void imc(void *, bus_dma_segment_t *, int, int); 1427 static void imc1(void *, bus_dma_segment_t *, int, int); 1428 1429 static void 1430 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1431 { 1432 struct imush *imushp = (struct imush *) arg; 1433 1434 if (error) { 1435 imushp->error = error; 1436 return; 1437 } 1438 if (nseg != 1) { 1439 imushp->error = EINVAL; 1440 return; 1441 } 1442 isp_prt(imushp->isp, ISP_LOGDEBUG0, "request/result area @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1443 imushp->isp->isp_rquest = imushp->vbase; 1444 imushp->isp->isp_rquest_dma = segs->ds_addr; 1445 segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1446 imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1447 imushp->isp->isp_result_dma = segs->ds_addr; 1448 imushp->isp->isp_result = imushp->vbase; 1449 1450 #ifdef ISP_TARGET_MODE 1451 if (IS_24XX(imushp->isp)) { 1452 segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1453 imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1454 imushp->isp->isp_atioq_dma = segs->ds_addr; 1455 imushp->isp->isp_atioq = imushp->vbase; 1456 } 1457 #endif 1458 } 1459 1460 static void 1461 imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1462 { 1463 struct imush *imushp = (struct imush *) arg; 1464 if (error) { 1465 imushp->error = error; 1466 return; 1467 } 1468 if (nseg != 1) { 1469 imushp->error = EINVAL; 1470 return; 1471 } 1472 isp_prt(imushp->isp, ISP_LOGDEBUG0, "scdma @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1473 FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr; 1474 FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase; 1475 } 1476 1477 static int 1478 isp_pci_mbxdma(ispsoftc_t *isp) 1479 { 1480 caddr_t base; 1481 uint32_t len; 1482 int i, error, ns, cmap = 0; 1483 bus_size_t slim; /* segment size */ 1484 bus_addr_t llim; /* low limit of unavailable dma */ 1485 bus_addr_t hlim; /* high limit of unavailable dma */ 1486 struct imush im; 1487 1488 /* 1489 * Already been here? If so, leave... 1490 */ 1491 if (isp->isp_rquest) { 1492 return (0); 1493 } 1494 ISP_UNLOCK(isp); 1495 1496 if (isp->isp_maxcmds == 0) { 1497 isp_prt(isp, ISP_LOGERR, "maxcmds not set"); 1498 ISP_LOCK(isp); 1499 return (1); 1500 } 1501 1502 hlim = BUS_SPACE_MAXADDR; 1503 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1504 if (sizeof (bus_size_t) > 4) { 1505 slim = (bus_size_t) (1ULL << 32); 1506 } else { 1507 slim = (bus_size_t) (1UL << 31); 1508 } 1509 llim = BUS_SPACE_MAXADDR; 1510 } else { 1511 llim = BUS_SPACE_MAXADDR_32BIT; 1512 slim = (1UL << 24); 1513 } 1514 1515 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1516 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) kmalloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1517 if (isp->isp_osinfo.pcmd_pool == NULL) { 1518 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds"); 1519 ISP_LOCK(isp); 1520 return (1); 1521 } 1522 1523 /* 1524 * XXX: We don't really support 64 bit target mode for parallel scsi yet 1525 */ 1526 #ifdef ISP_TARGET_MODE 1527 if (IS_SCSI(isp) && sizeof (bus_addr_t) > 4) { 1528 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1529 isp_prt(isp, ISP_LOGERR, "we cannot do DAC for SPI cards yet"); 1530 ISP_LOCK(isp); 1531 return (1); 1532 } 1533 #endif 1534 1535 if (isp_dma_tag_create(NULL, 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, slim, 0, &isp->isp_osinfo.dmat)) { 1536 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1537 ISP_LOCK(isp); 1538 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1539 return (1); 1540 } 1541 1542 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1543 isp->isp_xflist = (isp_hdl_t *) kmalloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1544 if (isp->isp_xflist == NULL) { 1545 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1546 ISP_LOCK(isp); 1547 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1548 return (1); 1549 } 1550 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1551 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1552 } 1553 isp->isp_xffree = isp->isp_xflist; 1554 #ifdef ISP_TARGET_MODE 1555 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1556 isp->isp_tgtlist = (isp_hdl_t *) kmalloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1557 if (isp->isp_tgtlist == NULL) { 1558 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1559 kfree(isp->isp_xflist, M_DEVBUF); 1560 ISP_LOCK(isp); 1561 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array"); 1562 return (1); 1563 } 1564 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1565 isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1]; 1566 } 1567 isp->isp_tgtfree = isp->isp_tgtlist; 1568 #endif 1569 1570 /* 1571 * Allocate and map the request and result queues (and ATIO queue 1572 * if we're a 2400 supporting target mode). 1573 */ 1574 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1575 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1576 #ifdef ISP_TARGET_MODE 1577 if (IS_24XX(isp)) { 1578 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1579 } 1580 #endif 1581 1582 ns = (len / PAGE_SIZE) + 1; 1583 1584 /* 1585 * Create a tag for the control spaces. We don't always need this 1586 * to be 32 bits, but we do this for simplicity and speed's sake. 1587 */ 1588 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, ns, slim, 0, &isp->isp_osinfo.cdmat)) { 1589 isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces"); 1590 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1591 kfree(isp->isp_xflist, M_DEVBUF); 1592 #ifdef ISP_TARGET_MODE 1593 kfree(isp->isp_tgtlist, M_DEVBUF); 1594 #endif 1595 ISP_LOCK(isp); 1596 return (1); 1597 } 1598 1599 if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &isp->isp_osinfo.cdmap) != 0) { 1600 isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len); 1601 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1602 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1603 kfree(isp->isp_xflist, M_DEVBUF); 1604 #ifdef ISP_TARGET_MODE 1605 kfree(isp->isp_tgtlist, M_DEVBUF); 1606 #endif 1607 ISP_LOCK(isp); 1608 return (1); 1609 } 1610 1611 im.isp = isp; 1612 im.chan = 0; 1613 im.vbase = base; 1614 im.error = 0; 1615 1616 bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0); 1617 if (im.error) { 1618 isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error); 1619 goto bad; 1620 } 1621 1622 if (IS_FC(isp)) { 1623 for (cmap = 0; cmap < isp->isp_nchan; cmap++) { 1624 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1625 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) { 1626 goto bad; 1627 } 1628 if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &fc->tdmap) != 0) { 1629 bus_dma_tag_destroy(fc->tdmat); 1630 goto bad; 1631 } 1632 im.isp = isp; 1633 im.chan = cmap; 1634 im.vbase = base; 1635 im.error = 0; 1636 bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0); 1637 if (im.error) { 1638 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1639 bus_dma_tag_destroy(fc->tdmat); 1640 goto bad; 1641 } 1642 } 1643 } 1644 1645 for (i = 0; i < isp->isp_maxcmds; i++) { 1646 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1647 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1648 if (error) { 1649 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error); 1650 while (--i >= 0) { 1651 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap); 1652 } 1653 goto bad; 1654 } 1655 callout_init(&pcmd->wdog); 1656 if (i == isp->isp_maxcmds-1) { 1657 pcmd->next = NULL; 1658 } else { 1659 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1660 } 1661 } 1662 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1663 ISP_LOCK(isp); 1664 return (0); 1665 1666 bad: 1667 while (--cmap >= 0) { 1668 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1669 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1670 bus_dma_tag_destroy(fc->tdmat); 1671 } 1672 bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap); 1673 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1674 kfree(isp->isp_xflist, M_DEVBUF); 1675 #ifdef ISP_TARGET_MODE 1676 kfree(isp->isp_tgtlist, M_DEVBUF); 1677 #endif 1678 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1679 isp->isp_rquest = NULL; 1680 ISP_LOCK(isp); 1681 return (1); 1682 } 1683 1684 typedef struct { 1685 ispsoftc_t *isp; 1686 void *cmd_token; 1687 void *rq; /* original request */ 1688 int error; 1689 bus_size_t mapsize; 1690 } mush_t; 1691 1692 #define MUSHERR_NOQENTRIES -2 1693 1694 #ifdef ISP_TARGET_MODE 1695 static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1696 static void tdma2(void *, bus_dma_segment_t *, int, int); 1697 1698 static void 1699 tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1700 { 1701 mush_t *mp; 1702 mp = (mush_t *)arg; 1703 mp->mapsize = mapsize; 1704 tdma2(arg, dm_segs, nseg, error); 1705 } 1706 1707 static void 1708 tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1709 { 1710 mush_t *mp; 1711 ispsoftc_t *isp; 1712 struct ccb_scsiio *csio; 1713 isp_ddir_t ddir; 1714 ispreq_t *rq; 1715 1716 mp = (mush_t *) arg; 1717 if (error) { 1718 mp->error = error; 1719 return; 1720 } 1721 csio = mp->cmd_token; 1722 isp = mp->isp; 1723 rq = mp->rq; 1724 if (nseg) { 1725 if (sizeof (bus_addr_t) > 4) { 1726 if (nseg >= ISP_NSEG64_MAX) { 1727 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1728 mp->error = EFAULT; 1729 return; 1730 } 1731 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) { 1732 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3; 1733 } 1734 } else { 1735 if (nseg >= ISP_NSEG_MAX) { 1736 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1737 mp->error = EFAULT; 1738 return; 1739 } 1740 } 1741 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1742 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1743 ddir = ISP_TO_DEVICE; 1744 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1745 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1746 ddir = ISP_FROM_DEVICE; 1747 } else { 1748 dm_segs = NULL; 1749 nseg = 0; 1750 ddir = ISP_NOXFR; 1751 } 1752 } else { 1753 dm_segs = NULL; 1754 nseg = 0; 1755 ddir = ISP_NOXFR; 1756 } 1757 1758 if (isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len) != CMD_QUEUED) { 1759 mp->error = MUSHERR_NOQENTRIES; 1760 } 1761 } 1762 #endif 1763 1764 static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1765 static void dma2(void *, bus_dma_segment_t *, int, int); 1766 1767 static void 1768 dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1769 { 1770 mush_t *mp; 1771 mp = (mush_t *)arg; 1772 mp->mapsize = mapsize; 1773 dma2(arg, dm_segs, nseg, error); 1774 } 1775 1776 static void 1777 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1778 { 1779 mush_t *mp; 1780 ispsoftc_t *isp; 1781 struct ccb_scsiio *csio; 1782 isp_ddir_t ddir; 1783 ispreq_t *rq; 1784 1785 mp = (mush_t *) arg; 1786 if (error) { 1787 mp->error = error; 1788 return; 1789 } 1790 csio = mp->cmd_token; 1791 isp = mp->isp; 1792 rq = mp->rq; 1793 if (nseg) { 1794 if (sizeof (bus_addr_t) > 4) { 1795 if (nseg >= ISP_NSEG64_MAX) { 1796 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1797 mp->error = EFAULT; 1798 return; 1799 } 1800 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1801 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1802 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1803 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1804 } 1805 } else { 1806 if (nseg >= ISP_NSEG_MAX) { 1807 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1808 mp->error = EFAULT; 1809 return; 1810 } 1811 } 1812 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1813 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1814 ddir = ISP_FROM_DEVICE; 1815 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1816 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1817 ddir = ISP_TO_DEVICE; 1818 } else { 1819 ddir = ISP_NOXFR; 1820 } 1821 } else { 1822 dm_segs = NULL; 1823 nseg = 0; 1824 ddir = ISP_NOXFR; 1825 } 1826 1827 if (isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir) != CMD_QUEUED) { 1828 mp->error = MUSHERR_NOQENTRIES; 1829 } 1830 } 1831 1832 static int 1833 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) 1834 { 1835 mush_t mush, *mp; 1836 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1837 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int); 1838 1839 mp = &mush; 1840 mp->isp = isp; 1841 mp->cmd_token = csio; 1842 mp->rq = ff; 1843 mp->error = 0; 1844 mp->mapsize = 0; 1845 1846 #ifdef ISP_TARGET_MODE 1847 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1848 eptr = tdma2; 1849 eptr2 = tdma2_2; 1850 } else 1851 #endif 1852 { 1853 eptr = dma2; 1854 eptr2 = dma2_2; 1855 } 1856 1857 1858 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || (csio->dxfer_len == 0)) { 1859 (*eptr)(mp, NULL, 0, 0); 1860 } else if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1861 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1862 int error; 1863 error = bus_dmamap_load(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1864 #if 0 1865 xpt_print(csio->ccb_h.path, "%s: bus_dmamap_load " "ptr %p len %d returned %d\n", __func__, csio->data_ptr, csio->dxfer_len, error); 1866 #endif 1867 1868 if (error == EINPROGRESS) { 1869 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); 1870 mp->error = EINVAL; 1871 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported"); 1872 } else if (error && mp->error == 0) { 1873 #ifdef DIAGNOSTIC 1874 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1875 #endif 1876 mp->error = error; 1877 } 1878 } else { 1879 /* Pointer to physical buffer */ 1880 struct bus_dma_segment seg; 1881 seg.ds_addr = (bus_addr_t)(vm_offset_t)csio->data_ptr; 1882 seg.ds_len = csio->dxfer_len; 1883 (*eptr)(mp, &seg, 1, 0); 1884 } 1885 } else { 1886 struct bus_dma_segment *segs; 1887 1888 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1889 isp_prt(isp, ISP_LOGERR, "Physical segment pointers unsupported"); 1890 mp->error = EINVAL; 1891 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1892 struct uio sguio; 1893 int error; 1894 1895 /* 1896 * We're taking advantage of the fact that 1897 * the pointer/length sizes and layout of the iovec 1898 * structure are the same as the bus_dma_segment 1899 * structure. This might be a little dangerous, 1900 * but only if they change the structures, which 1901 * seems unlikely. 1902 */ 1903 KASSERT((sizeof (sguio.uio_iov) == sizeof (csio->data_ptr) && 1904 sizeof (sguio.uio_iovcnt) >= sizeof (csio->sglist_cnt) && 1905 sizeof (sguio.uio_resid) >= sizeof (csio->dxfer_len)), ("Ken's assumption failed")); 1906 sguio.uio_iov = (struct iovec *)csio->data_ptr; 1907 sguio.uio_iovcnt = csio->sglist_cnt; 1908 sguio.uio_resid = csio->dxfer_len; 1909 sguio.uio_segflg = UIO_SYSSPACE; 1910 1911 error = bus_dmamap_load_uio(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, &sguio, eptr2, mp, 0); 1912 1913 if (error != 0 && mp->error == 0) { 1914 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1915 mp->error = error; 1916 } 1917 } else { 1918 /* Just use the segments provided */ 1919 segs = (struct bus_dma_segment *) csio->data_ptr; 1920 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1921 } 1922 } 1923 if (mp->error) { 1924 int retval = CMD_COMPLETE; 1925 if (mp->error == MUSHERR_NOQENTRIES) { 1926 retval = CMD_EAGAIN; 1927 } else if (mp->error == EFBIG) { 1928 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1929 } else if (mp->error == EINVAL) { 1930 XS_SETERR(csio, CAM_REQ_INVALID); 1931 } else { 1932 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1933 } 1934 return (retval); 1935 } 1936 return (CMD_QUEUED); 1937 } 1938 1939 static void 1940 isp_pci_reset0(ispsoftc_t *isp) 1941 { 1942 ISP_DISABLE_INTS(isp); 1943 } 1944 1945 static void 1946 isp_pci_reset1(ispsoftc_t *isp) 1947 { 1948 if (!IS_24XX(isp)) { 1949 /* Make sure the BIOS is disabled */ 1950 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1951 } 1952 /* and enable interrupts */ 1953 ISP_ENABLE_INTS(isp); 1954 } 1955 1956 static void 1957 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 1958 { 1959 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1960 if (msg) 1961 kprintf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1962 else 1963 kprintf("%s:\n", device_get_nameunit(isp->isp_dev)); 1964 if (IS_SCSI(isp)) 1965 kprintf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1966 else 1967 kprintf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1968 kprintf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1969 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1970 kprintf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1971 1972 1973 if (IS_SCSI(isp)) { 1974 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1975 kprintf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1976 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1977 ISP_READ(isp, CDMA_FIFO_STS)); 1978 kprintf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1979 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1980 ISP_READ(isp, DDMA_FIFO_STS)); 1981 kprintf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1982 ISP_READ(isp, SXP_INTERRUPT), 1983 ISP_READ(isp, SXP_GROSS_ERR), 1984 ISP_READ(isp, SXP_PINS_CTRL)); 1985 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1986 } 1987 kprintf(" mbox regs: %x %x %x %x %x\n", 1988 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1989 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1990 ISP_READ(isp, OUTMAILBOX4)); 1991 kprintf(" PCI Status Command/Status=%x\n", 1992 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 1993 } 1994