1 /* $FreeBSD: src/sys/dev/isp/isp_pci.c,v 1.78.2.4 2002/10/11 18:50:53 mjacob Exp $ */ 2 /* $DragonFly: src/sys/dev/disk/isp/isp_pci.c,v 1.7 2005/06/06 22:51:54 corecode Exp $ */ 3 /* 4 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 5 * FreeBSD Version. 6 * 7 * Copyright (c) 1997, 1998, 1999, 2000, 2001 by Matthew Jacob 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice immediately at the beginning of the file, without modification, 14 * this list of conditions, and the following disclaimer. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/bus.h> 36 37 #include <bus/pci/pcireg.h> 38 #include <bus/pci/pcivar.h> 39 40 #include <machine/bus_memio.h> 41 #include <machine/bus_pio.h> 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 #include <sys/rman.h> 45 #include <sys/malloc.h> 46 47 #include "isp_freebsd.h" 48 49 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); 50 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); 51 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 52 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); 53 static int 54 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 55 static int 56 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 57 static int isp_pci_mbxdma(struct ispsoftc *); 58 static int 59 isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, u_int16_t *, u_int16_t); 60 static void 61 isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); 62 63 static void isp_pci_reset1(struct ispsoftc *); 64 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 65 66 static struct ispmdvec mdvec = { 67 isp_pci_rd_isr, 68 isp_pci_rd_reg, 69 isp_pci_wr_reg, 70 isp_pci_mbxdma, 71 isp_pci_dmasetup, 72 isp_pci_dmateardown, 73 NULL, 74 isp_pci_reset1, 75 isp_pci_dumpregs, 76 NULL, 77 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 78 }; 79 80 static struct ispmdvec mdvec_1080 = { 81 isp_pci_rd_isr, 82 isp_pci_rd_reg_1080, 83 isp_pci_wr_reg_1080, 84 isp_pci_mbxdma, 85 isp_pci_dmasetup, 86 isp_pci_dmateardown, 87 NULL, 88 isp_pci_reset1, 89 isp_pci_dumpregs, 90 NULL, 91 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 92 }; 93 94 static struct ispmdvec mdvec_12160 = { 95 isp_pci_rd_isr, 96 isp_pci_rd_reg_1080, 97 isp_pci_wr_reg_1080, 98 isp_pci_mbxdma, 99 isp_pci_dmasetup, 100 isp_pci_dmateardown, 101 NULL, 102 isp_pci_reset1, 103 isp_pci_dumpregs, 104 NULL, 105 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 106 }; 107 108 static struct ispmdvec mdvec_2100 = { 109 isp_pci_rd_isr, 110 isp_pci_rd_reg, 111 isp_pci_wr_reg, 112 isp_pci_mbxdma, 113 isp_pci_dmasetup, 114 isp_pci_dmateardown, 115 NULL, 116 isp_pci_reset1, 117 isp_pci_dumpregs 118 }; 119 120 static struct ispmdvec mdvec_2200 = { 121 isp_pci_rd_isr, 122 isp_pci_rd_reg, 123 isp_pci_wr_reg, 124 isp_pci_mbxdma, 125 isp_pci_dmasetup, 126 isp_pci_dmateardown, 127 NULL, 128 isp_pci_reset1, 129 isp_pci_dumpregs 130 }; 131 132 static struct ispmdvec mdvec_2300 = { 133 isp_pci_rd_isr_2300, 134 isp_pci_rd_reg, 135 isp_pci_wr_reg, 136 isp_pci_mbxdma, 137 isp_pci_dmasetup, 138 isp_pci_dmateardown, 139 NULL, 140 isp_pci_reset1, 141 isp_pci_dumpregs 142 }; 143 144 #ifndef PCIM_CMD_INVEN 145 #define PCIM_CMD_INVEN 0x10 146 #endif 147 #ifndef PCIM_CMD_BUSMASTEREN 148 #define PCIM_CMD_BUSMASTEREN 0x0004 149 #endif 150 #ifndef PCIM_CMD_PERRESPEN 151 #define PCIM_CMD_PERRESPEN 0x0040 152 #endif 153 #ifndef PCIM_CMD_SEREN 154 #define PCIM_CMD_SEREN 0x0100 155 #endif 156 157 #ifndef PCIR_COMMAND 158 #define PCIR_COMMAND 0x04 159 #endif 160 161 #ifndef PCIR_CACHELNSZ 162 #define PCIR_CACHELNSZ 0x0c 163 #endif 164 165 #ifndef PCIR_LATTIMER 166 #define PCIR_LATTIMER 0x0d 167 #endif 168 169 #ifndef PCIR_ROMADDR 170 #define PCIR_ROMADDR 0x30 171 #endif 172 173 #ifndef PCI_VENDOR_QLOGIC 174 #define PCI_VENDOR_QLOGIC 0x1077 175 #endif 176 177 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 178 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 179 #endif 180 181 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 182 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 183 #endif 184 185 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 186 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 187 #endif 188 189 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 190 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 191 #endif 192 193 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 194 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 195 #endif 196 197 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 198 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 199 #endif 200 201 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 202 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 203 #endif 204 205 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 206 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 207 #endif 208 209 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 210 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 211 #endif 212 213 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 214 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 215 #endif 216 217 #define PCI_QLOGIC_ISP1020 \ 218 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 219 220 #define PCI_QLOGIC_ISP1080 \ 221 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 222 223 #define PCI_QLOGIC_ISP10160 \ 224 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 225 226 #define PCI_QLOGIC_ISP12160 \ 227 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 228 229 #define PCI_QLOGIC_ISP1240 \ 230 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 231 232 #define PCI_QLOGIC_ISP1280 \ 233 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 234 235 #define PCI_QLOGIC_ISP2100 \ 236 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 237 238 #define PCI_QLOGIC_ISP2200 \ 239 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 240 241 #define PCI_QLOGIC_ISP2300 \ 242 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 243 244 #define PCI_QLOGIC_ISP2312 \ 245 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 246 247 /* 248 * Odd case for some AMI raid cards... We need to *not* attach to this. 249 */ 250 #define AMI_RAID_SUBVENDOR_ID 0x101e 251 252 #define IO_MAP_REG 0x10 253 #define MEM_MAP_REG 0x14 254 255 #define PCI_DFLT_LTNCY 0x40 256 #define PCI_DFLT_LNSZ 0x10 257 258 static int isp_pci_probe (device_t); 259 static int isp_pci_attach (device_t); 260 261 262 struct isp_pcisoftc { 263 struct ispsoftc pci_isp; 264 device_t pci_dev; 265 struct resource * pci_reg; 266 bus_space_tag_t pci_st; 267 bus_space_handle_t pci_sh; 268 void * ih; 269 int16_t pci_poff[_NREG_BLKS]; 270 bus_dma_tag_t dmat; 271 bus_dmamap_t *dmaps; 272 }; 273 ispfwfunc *isp_get_firmware_p = NULL; 274 275 static device_method_t isp_pci_methods[] = { 276 /* Device interface */ 277 DEVMETHOD(device_probe, isp_pci_probe), 278 DEVMETHOD(device_attach, isp_pci_attach), 279 { 0, 0 } 280 }; 281 static void isp_pci_intr(void *); 282 283 static driver_t isp_pci_driver = { 284 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 285 }; 286 static devclass_t isp_devclass; 287 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 288 MODULE_VERSION(isp, 1); 289 290 static int 291 isp_pci_probe(device_t dev) 292 { 293 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 294 case PCI_QLOGIC_ISP1020: 295 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 296 break; 297 case PCI_QLOGIC_ISP1080: 298 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 299 break; 300 case PCI_QLOGIC_ISP1240: 301 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 302 break; 303 case PCI_QLOGIC_ISP1280: 304 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 305 break; 306 case PCI_QLOGIC_ISP10160: 307 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 308 break; 309 case PCI_QLOGIC_ISP12160: 310 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 311 return (ENXIO); 312 } 313 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 314 break; 315 case PCI_QLOGIC_ISP2100: 316 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 317 break; 318 case PCI_QLOGIC_ISP2200: 319 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 320 break; 321 case PCI_QLOGIC_ISP2300: 322 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 323 break; 324 case PCI_QLOGIC_ISP2312: 325 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 326 break; 327 default: 328 return (ENXIO); 329 } 330 if (device_get_unit(dev) == 0 && bootverbose) { 331 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 332 "Core Version %d.%d\n", 333 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 334 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 335 } 336 /* 337 * XXXX: Here is where we might load the f/w module 338 * XXXX: (or increase a reference count to it). 339 */ 340 return (0); 341 } 342 343 static int 344 isp_pci_attach(device_t dev) 345 { 346 struct resource *regs, *irq; 347 int unit, bitmap, rtp, rgd, iqd, m1, m2, isp_debug; 348 u_int32_t data, cmd, linesz, psize, basetype; 349 struct isp_pcisoftc *pcs; 350 struct ispsoftc *isp = NULL; 351 struct ispmdvec *mdvp; 352 quad_t wwn; 353 bus_size_t lim; 354 355 /* 356 * Figure out if we're supposed to skip this one. 357 */ 358 unit = device_get_unit(dev); 359 if (getenv_int("isp_disable", &bitmap)) { 360 if (bitmap & (1 << unit)) { 361 device_printf(dev, "not configuring\n"); 362 /* 363 * But return '0' to preserve HBA numbering. 364 */ 365 return (0); 366 } 367 } 368 369 pcs = malloc(sizeof (struct isp_pcisoftc), M_DEVBUF, M_WAITOK | M_ZERO); 370 371 /* 372 * Figure out which we should try first - memory mapping or i/o mapping? 373 */ 374 m1 = PCIM_CMD_PORTEN; 375 m2 = PCIM_CMD_MEMEN; 376 bitmap = 0; 377 if (getenv_int("isp_mem_map", &bitmap)) { 378 if (bitmap & (1 << unit)) { 379 m1 = PCIM_CMD_MEMEN; 380 m2 = PCIM_CMD_PORTEN; 381 } 382 } 383 bitmap = 0; 384 if (getenv_int("isp_io_map", &bitmap)) { 385 if (bitmap & (1 << unit)) { 386 m1 = PCIM_CMD_PORTEN; 387 m2 = PCIM_CMD_MEMEN; 388 } 389 } 390 391 linesz = PCI_DFLT_LNSZ; 392 irq = regs = NULL; 393 rgd = rtp = iqd = 0; 394 395 cmd = pci_read_config(dev, PCIR_COMMAND, 1); 396 if (cmd & m1) { 397 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 398 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 399 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 400 } 401 if (regs == NULL && (cmd & m2)) { 402 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 403 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 404 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 405 } 406 if (regs == NULL) { 407 device_printf(dev, "unable to map any ports\n"); 408 goto bad; 409 } 410 if (bootverbose) 411 device_printf(dev, "using %s space register mapping\n", 412 (rgd == IO_MAP_REG)? "I/O" : "Memory"); 413 pcs->pci_dev = dev; 414 pcs->pci_reg = regs; 415 pcs->pci_st = rman_get_bustag(regs); 416 pcs->pci_sh = rman_get_bushandle(regs); 417 418 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 419 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 420 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 421 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 422 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 423 mdvp = &mdvec; 424 basetype = ISP_HA_SCSI_UNKNOWN; 425 psize = sizeof (sdparam); 426 lim = BUS_SPACE_MAXSIZE_32BIT; 427 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1020) { 428 mdvp = &mdvec; 429 basetype = ISP_HA_SCSI_UNKNOWN; 430 psize = sizeof (sdparam); 431 lim = BUS_SPACE_MAXSIZE_24BIT; 432 } 433 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1080) { 434 mdvp = &mdvec_1080; 435 basetype = ISP_HA_SCSI_1080; 436 psize = sizeof (sdparam); 437 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 438 ISP1080_DMA_REGS_OFF; 439 } 440 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1240) { 441 mdvp = &mdvec_1080; 442 basetype = ISP_HA_SCSI_1240; 443 psize = 2 * sizeof (sdparam); 444 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 445 ISP1080_DMA_REGS_OFF; 446 } 447 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1280) { 448 mdvp = &mdvec_1080; 449 basetype = ISP_HA_SCSI_1280; 450 psize = 2 * sizeof (sdparam); 451 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 452 ISP1080_DMA_REGS_OFF; 453 } 454 if (pci_get_devid(dev) == PCI_QLOGIC_ISP10160) { 455 mdvp = &mdvec_12160; 456 basetype = ISP_HA_SCSI_10160; 457 psize = sizeof (sdparam); 458 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 459 ISP1080_DMA_REGS_OFF; 460 } 461 if (pci_get_devid(dev) == PCI_QLOGIC_ISP12160) { 462 mdvp = &mdvec_12160; 463 basetype = ISP_HA_SCSI_12160; 464 psize = 2 * sizeof (sdparam); 465 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 466 ISP1080_DMA_REGS_OFF; 467 } 468 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2100) { 469 mdvp = &mdvec_2100; 470 basetype = ISP_HA_FC_2100; 471 psize = sizeof (fcparam); 472 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 473 PCI_MBOX_REGS2100_OFF; 474 if (pci_get_revid(dev) < 3) { 475 /* 476 * XXX: Need to get the actual revision 477 * XXX: number of the 2100 FB. At any rate, 478 * XXX: lower cache line size for early revision 479 * XXX; boards. 480 */ 481 linesz = 1; 482 } 483 } 484 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2200) { 485 mdvp = &mdvec_2200; 486 basetype = ISP_HA_FC_2200; 487 psize = sizeof (fcparam); 488 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 489 PCI_MBOX_REGS2100_OFF; 490 } 491 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2300) { 492 mdvp = &mdvec_2300; 493 basetype = ISP_HA_FC_2300; 494 psize = sizeof (fcparam); 495 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 496 PCI_MBOX_REGS2300_OFF; 497 } 498 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2312) { 499 mdvp = &mdvec_2300; 500 basetype = ISP_HA_FC_2312; 501 psize = sizeof (fcparam); 502 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 503 PCI_MBOX_REGS2300_OFF; 504 } 505 isp = &pcs->pci_isp; 506 isp->isp_param = malloc(psize, M_DEVBUF, M_WAITOK | M_ZERO); 507 isp->isp_mdvec = mdvp; 508 isp->isp_type = basetype; 509 isp->isp_revision = pci_get_revid(dev); 510 #ifdef ISP_TARGET_MODE 511 isp->isp_role = ISP_ROLE_BOTH; 512 #else 513 isp->isp_role = ISP_DEFAULT_ROLES; 514 #endif 515 isp->isp_dev = dev; 516 517 518 /* 519 * Try and find firmware for this device. 520 */ 521 522 if (isp_get_firmware_p) { 523 int device = (int) pci_get_device(dev); 524 #ifdef ISP_TARGET_MODE 525 (*isp_get_firmware_p)(0, 1, device, &mdvp->dv_ispfw); 526 #else 527 (*isp_get_firmware_p)(0, 0, device, &mdvp->dv_ispfw); 528 #endif 529 } 530 531 /* 532 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 533 * are set. 534 */ 535 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 536 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 537 if (IS_2300(isp)) { /* per QLogic errata */ 538 cmd &= ~PCIM_CMD_INVEN; 539 } 540 if (IS_23XX(isp)) { 541 /* 542 * Can't tell if ROM will hang on 'ABOUT FIRMWARE' command. 543 */ 544 isp->isp_touched = 1; 545 546 } 547 pci_write_config(dev, PCIR_COMMAND, cmd, 1); 548 549 /* 550 * Make sure the Cache Line Size register is set sensibly. 551 */ 552 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 553 if (data != linesz) { 554 data = PCI_DFLT_LNSZ; 555 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d", data); 556 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 557 } 558 559 /* 560 * Make sure the Latency Timer is sane. 561 */ 562 data = pci_read_config(dev, PCIR_LATTIMER, 1); 563 if (data < PCI_DFLT_LTNCY) { 564 data = PCI_DFLT_LTNCY; 565 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 566 pci_write_config(dev, PCIR_LATTIMER, data, 1); 567 } 568 569 /* 570 * Make sure we've disabled the ROM. 571 */ 572 data = pci_read_config(dev, PCIR_ROMADDR, 4); 573 data &= ~1; 574 pci_write_config(dev, PCIR_ROMADDR, data, 4); 575 576 iqd = 0; 577 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &iqd, 0, ~0, 578 1, RF_ACTIVE | RF_SHAREABLE); 579 if (irq == NULL) { 580 device_printf(dev, "could not allocate interrupt\n"); 581 goto bad; 582 } 583 584 if (getenv_int("isp_no_fwload", &bitmap)) { 585 if (bitmap & (1 << unit)) 586 isp->isp_confopts |= ISP_CFG_NORELOAD; 587 } 588 if (getenv_int("isp_fwload", &bitmap)) { 589 if (bitmap & (1 << unit)) 590 isp->isp_confopts &= ~ISP_CFG_NORELOAD; 591 } 592 if (getenv_int("isp_no_nvram", &bitmap)) { 593 if (bitmap & (1 << unit)) 594 isp->isp_confopts |= ISP_CFG_NONVRAM; 595 } 596 if (getenv_int("isp_nvram", &bitmap)) { 597 if (bitmap & (1 << unit)) 598 isp->isp_confopts &= ~ISP_CFG_NONVRAM; 599 } 600 if (getenv_int("isp_fcduplex", &bitmap)) { 601 if (bitmap & (1 << unit)) 602 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 603 } 604 if (getenv_int("isp_no_fcduplex", &bitmap)) { 605 if (bitmap & (1 << unit)) 606 isp->isp_confopts &= ~ISP_CFG_FULL_DUPLEX; 607 } 608 if (getenv_int("isp_nport", &bitmap)) { 609 if (bitmap & (1 << unit)) 610 isp->isp_confopts |= ISP_CFG_NPORT; 611 } 612 613 /* 614 * Because the resource_*_value functions can neither return 615 * 64 bit integer values, nor can they be directly coerced 616 * to interpret the right hand side of the assignment as 617 * you want them to interpret it, we have to force WWN 618 * hint replacement to specify WWN strings with a leading 619 * 'w' (e..g w50000000aaaa0001). Sigh. 620 */ 621 if (getenv_quad("isp_portwwn", &wwn)) { 622 isp->isp_osinfo.default_port_wwn = wwn; 623 isp->isp_confopts |= ISP_CFG_OWNWWPN; 624 } 625 if (isp->isp_osinfo.default_port_wwn == 0) { 626 isp->isp_osinfo.default_port_wwn = 0x400000007F000009ull; 627 } 628 629 if (getenv_quad("isp_nodewwn", &wwn)) { 630 isp->isp_osinfo.default_node_wwn = wwn; 631 isp->isp_confopts |= ISP_CFG_OWNWWNN; 632 } 633 if (isp->isp_osinfo.default_node_wwn == 0) { 634 isp->isp_osinfo.default_node_wwn = 0x400000007F000009ull; 635 } 636 637 isp_debug = 0; 638 (void) getenv_int("isp_debug", &isp_debug); 639 if (bus_setup_intr(dev, irq, INTR_TYPE_CAM, isp_pci_intr, 640 isp, &pcs->ih, NULL)) { 641 device_printf(dev, "could not setup interrupt\n"); 642 goto bad; 643 } 644 645 #ifdef ISP_FW_CRASH_DUMP 646 bitmap = 0; 647 if (getenv_int("isp_fw_dump_enable", &bitmap)) { 648 if (bitmap & (1 << unit) { 649 size_t amt = 0; 650 if (IS_2200(isp)) { 651 amt = QLA2200_RISC_IMAGE_DUMP_SIZE; 652 } else if (IS_23XX(isp)) { 653 amt = QLA2300_RISC_IMAGE_DUMP_SIZE; 654 } 655 if (amt) { 656 FCPARAM(isp)->isp_dump_data = 657 malloc(amt, M_DEVBUF, M_WAITOK); 658 bzero(FCPARAM(isp)->isp_dump_data, amt); 659 } else { 660 device_printf(dev, 661 "f/w crash dumps not supported for card\n"); 662 } 663 } 664 } 665 #endif 666 667 if (IS_2312(isp)) { 668 isp->isp_port = pci_get_function(dev); 669 } 670 671 /* 672 * Set up logging levels. 673 */ 674 if (isp_debug) { 675 isp->isp_dblev = isp_debug; 676 } else { 677 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 678 } 679 if (bootverbose) 680 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 681 682 /* 683 * Make sure we're in reset state. 684 */ 685 ISP_LOCK(isp); 686 isp_reset(isp); 687 688 if (isp->isp_state != ISP_RESETSTATE) { 689 ISP_UNLOCK(isp); 690 goto bad; 691 } 692 isp_init(isp); 693 if (isp->isp_state != ISP_INITSTATE) { 694 /* If we're a Fibre Channel Card, we allow deferred attach */ 695 if (IS_SCSI(isp)) { 696 isp_uninit(isp); 697 ISP_UNLOCK(isp); 698 goto bad; 699 } 700 } 701 isp_attach(isp); 702 if (isp->isp_state != ISP_RUNSTATE) { 703 /* If we're a Fibre Channel Card, we allow deferred attach */ 704 if (IS_SCSI(isp)) { 705 isp_uninit(isp); 706 ISP_UNLOCK(isp); 707 goto bad; 708 } 709 } 710 /* 711 * XXXX: Here is where we might unload the f/w module 712 * XXXX: (or decrease the reference count to it). 713 */ 714 ISP_UNLOCK(isp); 715 return (0); 716 717 bad: 718 719 if (pcs && pcs->ih) { 720 (void) bus_teardown_intr(dev, irq, pcs->ih); 721 } 722 723 if (irq) { 724 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 725 } 726 727 728 if (regs) { 729 (void) bus_release_resource(dev, rtp, rgd, regs); 730 } 731 732 if (pcs) { 733 if (pcs->pci_isp.isp_param) 734 free(pcs->pci_isp.isp_param, M_DEVBUF); 735 free(pcs, M_DEVBUF); 736 } 737 738 /* 739 * XXXX: Here is where we might unload the f/w module 740 * XXXX: (or decrease the reference count to it). 741 */ 742 return (ENXIO); 743 } 744 745 static void 746 isp_pci_intr(void *arg) 747 { 748 struct ispsoftc *isp = arg; 749 u_int16_t isr, sema, mbox; 750 751 ISP_LOCK(isp); 752 isp->isp_intcnt++; 753 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 754 isp->isp_intbogus++; 755 } else { 756 int iok = isp->isp_osinfo.intsok; 757 isp->isp_osinfo.intsok = 0; 758 isp_intr(isp, isr, sema, mbox); 759 isp->isp_osinfo.intsok = iok; 760 } 761 ISP_UNLOCK(isp); 762 } 763 764 765 #define IspVirt2Off(a, x) \ 766 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 767 _BLK_REG_SHFT] + ((x) & 0xff)) 768 769 #define BXR2(pcs, off) \ 770 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 771 #define BXW2(pcs, off, v) \ 772 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 773 774 775 static INLINE int 776 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp) 777 { 778 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 779 u_int16_t val0, val1; 780 int i = 0; 781 782 do { 783 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 784 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 785 } while (val0 != val1 && ++i < 1000); 786 if (val0 != val1) { 787 return (1); 788 } 789 *rp = val0; 790 return (0); 791 } 792 793 static int 794 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, 795 u_int16_t *semap, u_int16_t *mbp) 796 { 797 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 798 u_int16_t isr, sema; 799 800 if (IS_2100(isp)) { 801 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 802 return (0); 803 } 804 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 805 return (0); 806 } 807 } else { 808 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 809 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 810 } 811 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 812 isr &= INT_PENDING_MASK(isp); 813 sema &= BIU_SEMA_LOCK; 814 if (isr == 0 && sema == 0) { 815 return (0); 816 } 817 *isrp = isr; 818 if ((*semap = sema) != 0) { 819 if (IS_2100(isp)) { 820 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 821 return (0); 822 } 823 } else { 824 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 825 } 826 } 827 return (1); 828 } 829 830 static int 831 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, 832 u_int16_t *semap, u_int16_t *mbox0p) 833 { 834 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 835 u_int32_t r2hisr; 836 837 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 838 *isrp = 0; 839 return (0); 840 } 841 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 842 IspVirt2Off(pcs, BIU_R2HSTSLO)); 843 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 844 if ((r2hisr & BIU_R2HST_INTR) == 0) { 845 *isrp = 0; 846 return (0); 847 } 848 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 849 case ISPR2HST_ROM_MBX_OK: 850 case ISPR2HST_ROM_MBX_FAIL: 851 case ISPR2HST_MBX_OK: 852 case ISPR2HST_MBX_FAIL: 853 case ISPR2HST_ASYNC_EVENT: 854 *isrp = r2hisr & 0xffff; 855 *mbox0p = (r2hisr >> 16); 856 *semap = 1; 857 return (1); 858 case ISPR2HST_RIO_16: 859 *isrp = r2hisr & 0xffff; 860 *mbox0p = ASYNC_RIO1; 861 *semap = 1; 862 return (1); 863 case ISPR2HST_FPOST: 864 *isrp = r2hisr & 0xffff; 865 *mbox0p = ASYNC_CMD_CMPLT; 866 *semap = 1; 867 return (1); 868 case ISPR2HST_FPOST_CTIO: 869 *isrp = r2hisr & 0xffff; 870 *mbox0p = ASYNC_CTIO_DONE; 871 *semap = 1; 872 return (1); 873 case ISPR2HST_RSPQ_UPDATE: 874 *isrp = r2hisr & 0xffff; 875 *mbox0p = 0; 876 *semap = 0; 877 return (1); 878 default: 879 return (0); 880 } 881 } 882 883 static u_int16_t 884 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 885 { 886 u_int16_t rv; 887 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 888 int oldconf = 0; 889 890 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 891 /* 892 * We will assume that someone has paused the RISC processor. 893 */ 894 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 895 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 896 oldconf | BIU_PCI_CONF1_SXP); 897 } 898 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 899 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 900 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 901 } 902 return (rv); 903 } 904 905 static void 906 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) 907 { 908 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 909 int oldconf = 0; 910 911 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 912 /* 913 * We will assume that someone has paused the RISC processor. 914 */ 915 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 916 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 917 oldconf | BIU_PCI_CONF1_SXP); 918 } 919 BXW2(pcs, IspVirt2Off(isp, regoff), val); 920 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 921 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 922 } 923 } 924 925 static u_int16_t 926 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 927 { 928 u_int16_t rv, oc = 0; 929 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 930 931 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 932 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 933 u_int16_t tc; 934 /* 935 * We will assume that someone has paused the RISC processor. 936 */ 937 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 938 tc = oc & ~BIU_PCI1080_CONF1_DMA; 939 if (regoff & SXP_BANK1_SELECT) 940 tc |= BIU_PCI1080_CONF1_SXP1; 941 else 942 tc |= BIU_PCI1080_CONF1_SXP0; 943 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 944 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 945 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 946 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 947 oc | BIU_PCI1080_CONF1_DMA); 948 } 949 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 950 if (oc) { 951 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 952 } 953 return (rv); 954 } 955 956 static void 957 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) 958 { 959 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 960 int oc = 0; 961 962 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 963 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 964 u_int16_t tc; 965 /* 966 * We will assume that someone has paused the RISC processor. 967 */ 968 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 969 tc = oc & ~BIU_PCI1080_CONF1_DMA; 970 if (regoff & SXP_BANK1_SELECT) 971 tc |= BIU_PCI1080_CONF1_SXP1; 972 else 973 tc |= BIU_PCI1080_CONF1_SXP0; 974 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 975 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 976 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 977 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 978 oc | BIU_PCI1080_CONF1_DMA); 979 } 980 BXW2(pcs, IspVirt2Off(isp, regoff), val); 981 if (oc) { 982 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 983 } 984 } 985 986 987 struct imush { 988 struct ispsoftc *isp; 989 int error; 990 }; 991 992 static void imc(void *, bus_dma_segment_t *, int, int); 993 994 static void 995 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 996 { 997 struct imush *imushp = (struct imush *) arg; 998 if (error) { 999 imushp->error = error; 1000 } else { 1001 struct ispsoftc *isp =imushp->isp; 1002 bus_addr_t addr = segs->ds_addr; 1003 1004 isp->isp_rquest_dma = addr; 1005 addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1006 isp->isp_result_dma = addr; 1007 if (IS_FC(isp)) { 1008 addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1009 FCPARAM(isp)->isp_scdma = addr; 1010 } 1011 } 1012 } 1013 1014 /* 1015 * Should be BUS_SPACE_MAXSIZE, but MAXPHYS is larger than BUS_SPACE_MAXSIZE 1016 */ 1017 #define ISP_NSEGS ((MAXPHYS / PAGE_SIZE) + 1) 1018 1019 static int 1020 isp_pci_mbxdma(struct ispsoftc *isp) 1021 { 1022 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1023 caddr_t base; 1024 u_int32_t len; 1025 int i, error, ns; 1026 bus_size_t alim, slim; 1027 struct imush im; 1028 1029 /* 1030 * Already been here? If so, leave... 1031 */ 1032 if (isp->isp_rquest) { 1033 return (0); 1034 } 1035 1036 #ifdef ISP_DAC_SUPPORTED 1037 alim = BUS_SPACE_UNRESTRICTED; 1038 #else 1039 alim = BUS_SPACE_MAXADDR_32BIT; 1040 #endif 1041 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1042 slim = BUS_SPACE_MAXADDR_32BIT; 1043 } else { 1044 slim = BUS_SPACE_MAXADDR_24BIT; 1045 } 1046 1047 ISP_UNLOCK(isp); 1048 if (bus_dma_tag_create(NULL, 1, slim+1, alim, alim, 1049 NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, slim, 0, &pcs->dmat)) { 1050 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1051 ISP_LOCK(isp); 1052 return(1); 1053 } 1054 1055 1056 len = sizeof (XS_T **) * isp->isp_maxcmds; 1057 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1058 if (isp->isp_xflist == NULL) { 1059 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1060 ISP_LOCK(isp); 1061 return (1); 1062 } 1063 len = sizeof (bus_dmamap_t) * isp->isp_maxcmds; 1064 pcs->dmaps = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 1065 if (pcs->dmaps == NULL) { 1066 isp_prt(isp, ISP_LOGERR, "can't alloc dma map storage"); 1067 free(isp->isp_xflist, M_DEVBUF); 1068 ISP_LOCK(isp); 1069 return (1); 1070 } 1071 1072 /* 1073 * Allocate and map the request, result queues, plus FC scratch area. 1074 */ 1075 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1076 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1077 if (IS_FC(isp)) { 1078 len += ISP2100_SCRLEN; 1079 } 1080 1081 ns = (len / PAGE_SIZE) + 1; 1082 if (bus_dma_tag_create(pcs->dmat, QENTRY_LEN, slim+1, alim, alim, 1083 NULL, NULL, len, ns, slim, 0, &isp->isp_cdmat)) { 1084 isp_prt(isp, ISP_LOGERR, 1085 "cannot create a dma tag for control spaces"); 1086 free(pcs->dmaps, M_DEVBUF); 1087 free(isp->isp_xflist, M_DEVBUF); 1088 ISP_LOCK(isp); 1089 return (1); 1090 } 1091 1092 if (bus_dmamem_alloc(isp->isp_cdmat, (void **)&base, BUS_DMA_NOWAIT, 1093 &isp->isp_cdmap) != 0) { 1094 isp_prt(isp, ISP_LOGERR, 1095 "cannot allocate %d bytes of CCB memory", len); 1096 bus_dma_tag_destroy(isp->isp_cdmat); 1097 free(isp->isp_xflist, M_DEVBUF); 1098 free(pcs->dmaps, M_DEVBUF); 1099 ISP_LOCK(isp); 1100 return (1); 1101 } 1102 1103 for (i = 0; i < isp->isp_maxcmds; i++) { 1104 error = bus_dmamap_create(pcs->dmat, 0, &pcs->dmaps[i]); 1105 if (error) { 1106 isp_prt(isp, ISP_LOGERR, 1107 "error %d creating per-cmd DMA maps", error); 1108 while (--i >= 0) { 1109 bus_dmamap_destroy(pcs->dmat, pcs->dmaps[i]); 1110 } 1111 goto bad; 1112 } 1113 } 1114 1115 im.isp = isp; 1116 im.error = 0; 1117 bus_dmamap_load(isp->isp_cdmat, isp->isp_cdmap, base, len, imc, &im, 0); 1118 if (im.error) { 1119 isp_prt(isp, ISP_LOGERR, 1120 "error %d loading dma map for control areas", im.error); 1121 goto bad; 1122 } 1123 1124 isp->isp_rquest = base; 1125 base += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1126 isp->isp_result = base; 1127 if (IS_FC(isp)) { 1128 base += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1129 FCPARAM(isp)->isp_scratch = base; 1130 } 1131 ISP_LOCK(isp); 1132 return (0); 1133 1134 bad: 1135 bus_dmamem_free(isp->isp_cdmat, base, isp->isp_cdmap); 1136 bus_dma_tag_destroy(isp->isp_cdmat); 1137 free(isp->isp_xflist, M_DEVBUF); 1138 free(pcs->dmaps, M_DEVBUF); 1139 ISP_LOCK(isp); 1140 isp->isp_rquest = NULL; 1141 return (1); 1142 } 1143 1144 typedef struct { 1145 struct ispsoftc *isp; 1146 void *cmd_token; 1147 void *rq; 1148 u_int16_t *nxtip; 1149 u_int16_t optr; 1150 u_int error; 1151 } mush_t; 1152 1153 #define MUSHERR_NOQENTRIES -2 1154 1155 #ifdef ISP_TARGET_MODE 1156 /* 1157 * We need to handle DMA for target mode differently from initiator mode. 1158 * 1159 * DMA mapping and construction and submission of CTIO Request Entries 1160 * and rendevous for completion are very tightly coupled because we start 1161 * out by knowing (per platform) how much data we have to move, but we 1162 * don't know, up front, how many DMA mapping segments will have to be used 1163 * cover that data, so we don't know how many CTIO Request Entries we 1164 * will end up using. Further, for performance reasons we may want to 1165 * (on the last CTIO for Fibre Channel), send status too (if all went well). 1166 * 1167 * The standard vector still goes through isp_pci_dmasetup, but the callback 1168 * for the DMA mapping routines comes here instead with the whole transfer 1169 * mapped and a pointer to a partially filled in already allocated request 1170 * queue entry. We finish the job. 1171 */ 1172 static void tdma_mk(void *, bus_dma_segment_t *, int, int); 1173 static void tdma_mkfc(void *, bus_dma_segment_t *, int, int); 1174 1175 #define STATUS_WITH_DATA 1 1176 1177 static void 1178 tdma_mk(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1179 { 1180 mush_t *mp; 1181 struct ccb_scsiio *csio; 1182 struct ispsoftc *isp; 1183 struct isp_pcisoftc *pcs; 1184 bus_dmamap_t *dp; 1185 ct_entry_t *cto, *qe; 1186 u_int8_t scsi_status; 1187 u_int16_t curi, nxti, handle; 1188 u_int32_t sflags; 1189 int32_t resid; 1190 int nth_ctio, nctios, send_status; 1191 1192 mp = (mush_t *) arg; 1193 if (error) { 1194 mp->error = error; 1195 return; 1196 } 1197 1198 isp = mp->isp; 1199 csio = mp->cmd_token; 1200 cto = mp->rq; 1201 curi = isp->isp_reqidx; 1202 qe = (ct_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 1203 1204 cto->ct_xfrlen = 0; 1205 cto->ct_seg_count = 0; 1206 cto->ct_header.rqs_entry_count = 1; 1207 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1208 1209 if (nseg == 0) { 1210 cto->ct_header.rqs_seqno = 1; 1211 isp_prt(isp, ISP_LOGTDEBUG1, 1212 "CTIO[%x] lun%d iid%d tag %x flgs %x sts %x ssts %x res %d", 1213 cto->ct_fwhandle, csio->ccb_h.target_lun, cto->ct_iid, 1214 cto->ct_tag_val, cto->ct_flags, cto->ct_status, 1215 cto->ct_scsi_status, cto->ct_resid); 1216 ISP_TDQE(isp, "tdma_mk[no data]", curi, cto); 1217 isp_put_ctio(isp, cto, qe); 1218 return; 1219 } 1220 1221 nctios = nseg / ISP_RQDSEG; 1222 if (nseg % ISP_RQDSEG) { 1223 nctios++; 1224 } 1225 1226 /* 1227 * Save syshandle, and potentially any SCSI status, which we'll 1228 * reinsert on the last CTIO we're going to send. 1229 */ 1230 1231 handle = cto->ct_syshandle; 1232 cto->ct_syshandle = 0; 1233 cto->ct_header.rqs_seqno = 0; 1234 send_status = (cto->ct_flags & CT_SENDSTATUS) != 0; 1235 1236 if (send_status) { 1237 sflags = cto->ct_flags & (CT_SENDSTATUS | CT_CCINCR); 1238 cto->ct_flags &= ~(CT_SENDSTATUS | CT_CCINCR); 1239 /* 1240 * Preserve residual. 1241 */ 1242 resid = cto->ct_resid; 1243 1244 /* 1245 * Save actual SCSI status. 1246 */ 1247 scsi_status = cto->ct_scsi_status; 1248 1249 #ifndef STATUS_WITH_DATA 1250 sflags |= CT_NO_DATA; 1251 /* 1252 * We can't do a status at the same time as a data CTIO, so 1253 * we need to synthesize an extra CTIO at this level. 1254 */ 1255 nctios++; 1256 #endif 1257 } else { 1258 sflags = scsi_status = resid = 0; 1259 } 1260 1261 cto->ct_resid = 0; 1262 cto->ct_scsi_status = 0; 1263 1264 pcs = (struct isp_pcisoftc *)isp; 1265 dp = &pcs->dmaps[isp_handle_index(handle)]; 1266 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1267 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREREAD); 1268 } else { 1269 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREWRITE); 1270 } 1271 1272 nxti = *mp->nxtip; 1273 1274 for (nth_ctio = 0; nth_ctio < nctios; nth_ctio++) { 1275 int seglim; 1276 1277 seglim = nseg; 1278 if (seglim) { 1279 int seg; 1280 1281 if (seglim > ISP_RQDSEG) 1282 seglim = ISP_RQDSEG; 1283 1284 for (seg = 0; seg < seglim; seg++, nseg--) { 1285 /* 1286 * Unlike normal initiator commands, we don't 1287 * do any swizzling here. 1288 */ 1289 cto->ct_dataseg[seg].ds_count = dm_segs->ds_len; 1290 cto->ct_dataseg[seg].ds_base = dm_segs->ds_addr; 1291 cto->ct_xfrlen += dm_segs->ds_len; 1292 dm_segs++; 1293 } 1294 cto->ct_seg_count = seg; 1295 } else { 1296 /* 1297 * This case should only happen when we're sending an 1298 * extra CTIO with final status. 1299 */ 1300 if (send_status == 0) { 1301 isp_prt(isp, ISP_LOGWARN, 1302 "tdma_mk ran out of segments"); 1303 mp->error = EINVAL; 1304 return; 1305 } 1306 } 1307 1308 /* 1309 * At this point, the fields ct_lun, ct_iid, ct_tagval, 1310 * ct_tagtype, and ct_timeout have been carried over 1311 * unchanged from what our caller had set. 1312 * 1313 * The dataseg fields and the seg_count fields we just got 1314 * through setting. The data direction we've preserved all 1315 * along and only clear it if we're now sending status. 1316 */ 1317 1318 if (nth_ctio == nctios - 1) { 1319 /* 1320 * We're the last in a sequence of CTIOs, so mark 1321 * this CTIO and save the handle to the CCB such that 1322 * when this CTIO completes we can free dma resources 1323 * and do whatever else we need to do to finish the 1324 * rest of the command. We *don't* give this to the 1325 * firmware to work on- the caller will do that. 1326 */ 1327 1328 cto->ct_syshandle = handle; 1329 cto->ct_header.rqs_seqno = 1; 1330 1331 if (send_status) { 1332 cto->ct_scsi_status = scsi_status; 1333 cto->ct_flags |= sflags; 1334 cto->ct_resid = resid; 1335 } 1336 if (send_status) { 1337 isp_prt(isp, ISP_LOGTDEBUG1, 1338 "CTIO[%x] lun%d iid %d tag %x ct_flags %x " 1339 "scsi status %x resid %d", 1340 cto->ct_fwhandle, csio->ccb_h.target_lun, 1341 cto->ct_iid, cto->ct_tag_val, cto->ct_flags, 1342 cto->ct_scsi_status, cto->ct_resid); 1343 } else { 1344 isp_prt(isp, ISP_LOGTDEBUG1, 1345 "CTIO[%x] lun%d iid%d tag %x ct_flags 0x%x", 1346 cto->ct_fwhandle, csio->ccb_h.target_lun, 1347 cto->ct_iid, cto->ct_tag_val, 1348 cto->ct_flags); 1349 } 1350 isp_put_ctio(isp, cto, qe); 1351 ISP_TDQE(isp, "last tdma_mk", curi, cto); 1352 if (nctios > 1) { 1353 MEMORYBARRIER(isp, SYNC_REQUEST, 1354 curi, QENTRY_LEN); 1355 } 1356 } else { 1357 ct_entry_t *oqe = qe; 1358 1359 /* 1360 * Make sure syshandle fields are clean 1361 */ 1362 cto->ct_syshandle = 0; 1363 cto->ct_header.rqs_seqno = 0; 1364 1365 isp_prt(isp, ISP_LOGTDEBUG1, 1366 "CTIO[%x] lun%d for ID%d ct_flags 0x%x", 1367 cto->ct_fwhandle, csio->ccb_h.target_lun, 1368 cto->ct_iid, cto->ct_flags); 1369 1370 /* 1371 * Get a new CTIO 1372 */ 1373 qe = (ct_entry_t *) 1374 ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1375 nxti = ISP_NXT_QENTRY(nxti, RQUEST_QUEUE_LEN(isp)); 1376 if (nxti == mp->optr) { 1377 isp_prt(isp, ISP_LOGTDEBUG0, 1378 "Queue Overflow in tdma_mk"); 1379 mp->error = MUSHERR_NOQENTRIES; 1380 return; 1381 } 1382 1383 /* 1384 * Now that we're done with the old CTIO, 1385 * flush it out to the request queue. 1386 */ 1387 ISP_TDQE(isp, "dma_tgt_fc", curi, cto); 1388 isp_put_ctio(isp, cto, oqe); 1389 if (nth_ctio != 0) { 1390 MEMORYBARRIER(isp, SYNC_REQUEST, curi, 1391 QENTRY_LEN); 1392 } 1393 curi = ISP_NXT_QENTRY(curi, RQUEST_QUEUE_LEN(isp)); 1394 1395 /* 1396 * Reset some fields in the CTIO so we can reuse 1397 * for the next one we'll flush to the request 1398 * queue. 1399 */ 1400 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; 1401 cto->ct_header.rqs_entry_count = 1; 1402 cto->ct_header.rqs_flags = 0; 1403 cto->ct_status = 0; 1404 cto->ct_scsi_status = 0; 1405 cto->ct_xfrlen = 0; 1406 cto->ct_resid = 0; 1407 cto->ct_seg_count = 0; 1408 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1409 } 1410 } 1411 *mp->nxtip = nxti; 1412 } 1413 1414 /* 1415 * We don't have to do multiple CTIOs here. Instead, we can just do 1416 * continuation segments as needed. This greatly simplifies the code 1417 * improves performance. 1418 */ 1419 1420 static void 1421 tdma_mkfc(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1422 { 1423 mush_t *mp; 1424 struct ccb_scsiio *csio; 1425 struct ispsoftc *isp; 1426 ct2_entry_t *cto, *qe; 1427 u_int16_t curi, nxti; 1428 int segcnt; 1429 1430 mp = (mush_t *) arg; 1431 if (error) { 1432 mp->error = error; 1433 return; 1434 } 1435 1436 isp = mp->isp; 1437 csio = mp->cmd_token; 1438 cto = mp->rq; 1439 1440 curi = isp->isp_reqidx; 1441 qe = (ct2_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 1442 1443 if (nseg == 0) { 1444 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE1) { 1445 isp_prt(isp, ISP_LOGWARN, 1446 "dma2_tgt_fc, a status CTIO2 without MODE1 " 1447 "set (0x%x)", cto->ct_flags); 1448 mp->error = EINVAL; 1449 return; 1450 } 1451 /* 1452 * We preserve ct_lun, ct_iid, ct_rxid. We set the data 1453 * flags to NO DATA and clear relative offset flags. 1454 * We preserve the ct_resid and the response area. 1455 */ 1456 cto->ct_header.rqs_seqno = 1; 1457 cto->ct_seg_count = 0; 1458 cto->ct_reloff = 0; 1459 isp_prt(isp, ISP_LOGTDEBUG1, 1460 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts " 1461 "0x%x res %d", cto->ct_rxid, csio->ccb_h.target_lun, 1462 cto->ct_iid, cto->ct_flags, cto->ct_status, 1463 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1464 isp_put_ctio2(isp, cto, qe); 1465 ISP_TDQE(isp, "dma2_tgt_fc[no data]", curi, qe); 1466 return; 1467 } 1468 1469 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE0) { 1470 isp_prt(isp, ISP_LOGERR, 1471 "dma2_tgt_fc, a data CTIO2 without MODE0 set " 1472 "(0x%x)", cto->ct_flags); 1473 mp->error = EINVAL; 1474 return; 1475 } 1476 1477 1478 nxti = *mp->nxtip; 1479 1480 /* 1481 * Set up the CTIO2 data segments. 1482 */ 1483 for (segcnt = 0; cto->ct_seg_count < ISP_RQDSEG_T2 && segcnt < nseg; 1484 cto->ct_seg_count++, segcnt++) { 1485 cto->rsp.m0.ct_dataseg[cto->ct_seg_count].ds_base = 1486 dm_segs[segcnt].ds_addr; 1487 cto->rsp.m0.ct_dataseg[cto->ct_seg_count].ds_count = 1488 dm_segs[segcnt].ds_len; 1489 cto->rsp.m0.ct_xfrlen += dm_segs[segcnt].ds_len; 1490 isp_prt(isp, ISP_LOGTDEBUG1, "isp_send_ctio2: ent0[%d]0x%x:%d", 1491 cto->ct_seg_count, dm_segs[segcnt].ds_addr, 1492 dm_segs[segcnt].ds_len); 1493 } 1494 1495 while (segcnt < nseg) { 1496 u_int16_t curip; 1497 int seg; 1498 ispcontreq_t local, *crq = &local, *qep; 1499 1500 qep = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1501 curip = nxti; 1502 nxti = ISP_NXT_QENTRY(curip, RQUEST_QUEUE_LEN(isp)); 1503 if (nxti == mp->optr) { 1504 ISP_UNLOCK(isp); 1505 isp_prt(isp, ISP_LOGTDEBUG0, 1506 "tdma_mkfc: request queue overflow"); 1507 mp->error = MUSHERR_NOQENTRIES; 1508 return; 1509 } 1510 cto->ct_header.rqs_entry_count++; 1511 MEMZERO((void *)crq, sizeof (*crq)); 1512 crq->req_header.rqs_entry_count = 1; 1513 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1514 for (seg = 0; segcnt < nseg && seg < ISP_CDSEG; 1515 segcnt++, seg++) { 1516 crq->req_dataseg[seg].ds_base = dm_segs[segcnt].ds_addr; 1517 crq->req_dataseg[seg].ds_count = dm_segs[segcnt].ds_len; 1518 isp_prt(isp, ISP_LOGTDEBUG1, 1519 "isp_send_ctio2: ent%d[%d]%x:%u", 1520 cto->ct_header.rqs_entry_count-1, seg, 1521 dm_segs[segcnt].ds_addr, dm_segs[segcnt].ds_len); 1522 cto->rsp.m0.ct_xfrlen += dm_segs[segcnt].ds_len; 1523 cto->ct_seg_count++; 1524 } 1525 MEMORYBARRIER(isp, SYNC_REQUEST, curip, QENTRY_LEN); 1526 isp_put_cont_req(isp, crq, qep); 1527 ISP_TDQE(isp, "cont entry", curi, qep); 1528 } 1529 1530 /* 1531 * No do final twiddling for the CTIO itself. 1532 */ 1533 cto->ct_header.rqs_seqno = 1; 1534 isp_prt(isp, ISP_LOGTDEBUG1, 1535 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts 0x%x resid %d", 1536 cto->ct_rxid, csio->ccb_h.target_lun, (int) cto->ct_iid, 1537 cto->ct_flags, cto->ct_status, cto->rsp.m1.ct_scsi_status, 1538 cto->ct_resid); 1539 isp_put_ctio2(isp, cto, qe); 1540 ISP_TDQE(isp, "last dma2_tgt_fc", curi, qe); 1541 *mp->nxtip = nxti; 1542 } 1543 #endif 1544 1545 static void dma2(void *, bus_dma_segment_t *, int, int); 1546 1547 static void 1548 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1549 { 1550 mush_t *mp; 1551 struct ispsoftc *isp; 1552 struct ccb_scsiio *csio; 1553 struct isp_pcisoftc *pcs; 1554 bus_dmamap_t *dp; 1555 bus_dma_segment_t *eseg; 1556 ispreq_t *rq; 1557 int seglim, datalen; 1558 u_int16_t nxti; 1559 1560 mp = (mush_t *) arg; 1561 if (error) { 1562 mp->error = error; 1563 return; 1564 } 1565 1566 if (nseg < 1) { 1567 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg); 1568 mp->error = EFAULT; 1569 return; 1570 } 1571 csio = mp->cmd_token; 1572 isp = mp->isp; 1573 rq = mp->rq; 1574 pcs = (struct isp_pcisoftc *)mp->isp; 1575 dp = &pcs->dmaps[isp_handle_index(rq->req_handle)]; 1576 nxti = *mp->nxtip; 1577 1578 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1579 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREREAD); 1580 } else { 1581 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREWRITE); 1582 } 1583 1584 datalen = XS_XFRLEN(csio); 1585 1586 /* 1587 * We're passed an initial partially filled in entry that 1588 * has most fields filled in except for data transfer 1589 * related values. 1590 * 1591 * Our job is to fill in the initial request queue entry and 1592 * then to start allocating and filling in continuation entries 1593 * until we've covered the entire transfer. 1594 */ 1595 1596 if (IS_FC(isp)) { 1597 seglim = ISP_RQDSEG_T2; 1598 ((ispreqt2_t *)rq)->req_totalcnt = datalen; 1599 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1600 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_IN; 1601 } else { 1602 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_OUT; 1603 } 1604 } else { 1605 if (csio->cdb_len > 12) { 1606 seglim = 0; 1607 } else { 1608 seglim = ISP_RQDSEG; 1609 } 1610 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1611 rq->req_flags |= REQFLAG_DATA_IN; 1612 } else { 1613 rq->req_flags |= REQFLAG_DATA_OUT; 1614 } 1615 } 1616 1617 eseg = dm_segs + nseg; 1618 1619 while (datalen != 0 && rq->req_seg_count < seglim && dm_segs != eseg) { 1620 if (IS_FC(isp)) { 1621 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1622 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1623 dm_segs->ds_addr; 1624 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1625 dm_segs->ds_len; 1626 } else { 1627 rq->req_dataseg[rq->req_seg_count].ds_base = 1628 dm_segs->ds_addr; 1629 rq->req_dataseg[rq->req_seg_count].ds_count = 1630 dm_segs->ds_len; 1631 } 1632 datalen -= dm_segs->ds_len; 1633 rq->req_seg_count++; 1634 dm_segs++; 1635 } 1636 1637 while (datalen > 0 && dm_segs != eseg) { 1638 u_int16_t onxti; 1639 ispcontreq_t local, *crq = &local, *cqe; 1640 1641 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1642 onxti = nxti; 1643 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 1644 if (nxti == mp->optr) { 1645 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 1646 mp->error = MUSHERR_NOQENTRIES; 1647 return; 1648 } 1649 rq->req_header.rqs_entry_count++; 1650 MEMZERO((void *)crq, sizeof (*crq)); 1651 crq->req_header.rqs_entry_count = 1; 1652 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1653 1654 seglim = 0; 1655 while (datalen > 0 && seglim < ISP_CDSEG && dm_segs != eseg) { 1656 crq->req_dataseg[seglim].ds_base = 1657 dm_segs->ds_addr; 1658 crq->req_dataseg[seglim].ds_count = 1659 dm_segs->ds_len; 1660 rq->req_seg_count++; 1661 dm_segs++; 1662 seglim++; 1663 datalen -= dm_segs->ds_len; 1664 } 1665 isp_put_cont_req(isp, crq, cqe); 1666 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 1667 } 1668 *mp->nxtip = nxti; 1669 } 1670 1671 static int 1672 isp_pci_dmasetup(struct ispsoftc *isp, struct ccb_scsiio *csio, ispreq_t *rq, 1673 u_int16_t *nxtip, u_int16_t optr) 1674 { 1675 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1676 ispreq_t *qep; 1677 bus_dmamap_t *dp = NULL; 1678 mush_t mush, *mp; 1679 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1680 1681 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, isp->isp_reqidx); 1682 #ifdef ISP_TARGET_MODE 1683 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1684 if (IS_FC(isp)) { 1685 eptr = tdma_mkfc; 1686 } else { 1687 eptr = tdma_mk; 1688 } 1689 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1690 (csio->dxfer_len == 0)) { 1691 mp = &mush; 1692 mp->isp = isp; 1693 mp->cmd_token = csio; 1694 mp->rq = rq; /* really a ct_entry_t or ct2_entry_t */ 1695 mp->nxtip = nxtip; 1696 mp->optr = optr; 1697 mp->error = 0; 1698 (*eptr)(mp, NULL, 0, 0); 1699 goto mbxsync; 1700 } 1701 } else 1702 #endif 1703 eptr = dma2; 1704 1705 1706 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1707 (csio->dxfer_len == 0)) { 1708 rq->req_seg_count = 1; 1709 goto mbxsync; 1710 } 1711 1712 /* 1713 * Do a virtual grapevine step to collect info for 1714 * the callback dma allocation that we have to use... 1715 */ 1716 mp = &mush; 1717 mp->isp = isp; 1718 mp->cmd_token = csio; 1719 mp->rq = rq; 1720 mp->nxtip = nxtip; 1721 mp->optr = optr; 1722 mp->error = 0; 1723 1724 if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1725 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1726 int error; 1727 dp = &pcs->dmaps[isp_handle_index(rq->req_handle)]; 1728 crit_enter(); 1729 error = bus_dmamap_load(pcs->dmat, *dp, 1730 csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1731 if (error == EINPROGRESS) { 1732 bus_dmamap_unload(pcs->dmat, *dp); 1733 mp->error = EINVAL; 1734 isp_prt(isp, ISP_LOGERR, 1735 "deferred dma allocation not supported"); 1736 } else if (error && mp->error == 0) { 1737 #ifdef DIAGNOSTIC 1738 isp_prt(isp, ISP_LOGERR, 1739 "error %d in dma mapping code", error); 1740 #endif 1741 mp->error = error; 1742 } 1743 crit_exit(); 1744 } else { 1745 /* Pointer to physical buffer */ 1746 struct bus_dma_segment seg; 1747 seg.ds_addr = (bus_addr_t)csio->data_ptr; 1748 seg.ds_len = csio->dxfer_len; 1749 (*eptr)(mp, &seg, 1, 0); 1750 } 1751 } else { 1752 struct bus_dma_segment *segs; 1753 1754 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1755 isp_prt(isp, ISP_LOGERR, 1756 "Physical segment pointers unsupported"); 1757 mp->error = EINVAL; 1758 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1759 isp_prt(isp, ISP_LOGERR, 1760 "Virtual segment addresses unsupported"); 1761 mp->error = EINVAL; 1762 } else { 1763 /* Just use the segments provided */ 1764 segs = (struct bus_dma_segment *) csio->data_ptr; 1765 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1766 } 1767 } 1768 if (mp->error) { 1769 int retval = CMD_COMPLETE; 1770 if (mp->error == MUSHERR_NOQENTRIES) { 1771 retval = CMD_EAGAIN; 1772 } else if (mp->error == EFBIG) { 1773 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1774 } else if (mp->error == EINVAL) { 1775 XS_SETERR(csio, CAM_REQ_INVALID); 1776 } else { 1777 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1778 } 1779 return (retval); 1780 } 1781 mbxsync: 1782 switch (rq->req_header.rqs_entry_type) { 1783 case RQSTYPE_REQUEST: 1784 isp_put_request(isp, rq, qep); 1785 break; 1786 case RQSTYPE_CMDONLY: 1787 isp_put_extended_request(isp, (ispextreq_t *)rq, 1788 (ispextreq_t *)qep); 1789 break; 1790 case RQSTYPE_T2RQS: 1791 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep); 1792 break; 1793 } 1794 return (CMD_QUEUED); 1795 } 1796 1797 static void 1798 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1799 { 1800 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1801 bus_dmamap_t *dp = &pcs->dmaps[isp_handle_index(handle)]; 1802 if ((xs->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1803 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTREAD); 1804 } else { 1805 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTWRITE); 1806 } 1807 bus_dmamap_unload(pcs->dmat, *dp); 1808 } 1809 1810 1811 static void 1812 isp_pci_reset1(struct ispsoftc *isp) 1813 { 1814 /* Make sure the BIOS is disabled */ 1815 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1816 /* and enable interrupts */ 1817 ENABLE_INTS(isp); 1818 } 1819 1820 static void 1821 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1822 { 1823 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1824 if (msg) 1825 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1826 else 1827 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 1828 if (IS_SCSI(isp)) 1829 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1830 else 1831 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1832 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1833 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1834 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1835 1836 1837 if (IS_SCSI(isp)) { 1838 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1839 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1840 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1841 ISP_READ(isp, CDMA_FIFO_STS)); 1842 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1843 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1844 ISP_READ(isp, DDMA_FIFO_STS)); 1845 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1846 ISP_READ(isp, SXP_INTERRUPT), 1847 ISP_READ(isp, SXP_GROSS_ERR), 1848 ISP_READ(isp, SXP_PINS_CTRL)); 1849 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1850 } 1851 printf(" mbox regs: %x %x %x %x %x\n", 1852 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1853 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1854 ISP_READ(isp, OUTMAILBOX4)); 1855 printf(" PCI Status Command/Status=%x\n", 1856 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 1857 } 1858