1 /*- 2 * Copyright (c) 1997-2008 by Matthew Jacob 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/isp/isp_pci.c,v 1.159 2011/11/16 02:52:24 mjacob Exp $ 27 */ 28 /* 29 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 30 * FreeBSD Version. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/linker.h> 38 #include <sys/firmware.h> 39 #include <sys/bus.h> 40 #include <sys/stdint.h> 41 #include <bus/pci/pcireg.h> 42 #include <bus/pci/pcivar.h> 43 #include <sys/rman.h> 44 #include <sys/malloc.h> 45 #include <sys/uio.h> 46 47 #include <dev/disk/isp/isp_freebsd.h> 48 49 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 50 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 51 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 52 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 53 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 54 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 55 static int isp_pci_rd_isr(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 56 static int isp_pci_rd_isr_2300(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 57 static int isp_pci_rd_isr_2400(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 58 static int isp_pci_mbxdma(ispsoftc_t *); 59 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *); 60 61 62 static void isp_pci_reset0(ispsoftc_t *); 63 static void isp_pci_reset1(ispsoftc_t *); 64 static void isp_pci_dumpregs(ispsoftc_t *, const char *); 65 66 static struct ispmdvec mdvec = { 67 isp_pci_rd_isr, 68 isp_pci_rd_reg, 69 isp_pci_wr_reg, 70 isp_pci_mbxdma, 71 isp_pci_dmasetup, 72 isp_common_dmateardown, 73 isp_pci_reset0, 74 isp_pci_reset1, 75 isp_pci_dumpregs, 76 NULL, 77 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 78 }; 79 80 static struct ispmdvec mdvec_1080 = { 81 isp_pci_rd_isr, 82 isp_pci_rd_reg_1080, 83 isp_pci_wr_reg_1080, 84 isp_pci_mbxdma, 85 isp_pci_dmasetup, 86 isp_common_dmateardown, 87 isp_pci_reset0, 88 isp_pci_reset1, 89 isp_pci_dumpregs, 90 NULL, 91 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 92 }; 93 94 static struct ispmdvec mdvec_12160 = { 95 isp_pci_rd_isr, 96 isp_pci_rd_reg_1080, 97 isp_pci_wr_reg_1080, 98 isp_pci_mbxdma, 99 isp_pci_dmasetup, 100 isp_common_dmateardown, 101 isp_pci_reset0, 102 isp_pci_reset1, 103 isp_pci_dumpregs, 104 NULL, 105 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 106 }; 107 108 static struct ispmdvec mdvec_2100 = { 109 isp_pci_rd_isr, 110 isp_pci_rd_reg, 111 isp_pci_wr_reg, 112 isp_pci_mbxdma, 113 isp_pci_dmasetup, 114 isp_common_dmateardown, 115 isp_pci_reset0, 116 isp_pci_reset1, 117 isp_pci_dumpregs 118 }; 119 120 static struct ispmdvec mdvec_2200 = { 121 isp_pci_rd_isr, 122 isp_pci_rd_reg, 123 isp_pci_wr_reg, 124 isp_pci_mbxdma, 125 isp_pci_dmasetup, 126 isp_common_dmateardown, 127 isp_pci_reset0, 128 isp_pci_reset1, 129 isp_pci_dumpregs 130 }; 131 132 static struct ispmdvec mdvec_2300 = { 133 isp_pci_rd_isr_2300, 134 isp_pci_rd_reg, 135 isp_pci_wr_reg, 136 isp_pci_mbxdma, 137 isp_pci_dmasetup, 138 isp_common_dmateardown, 139 isp_pci_reset0, 140 isp_pci_reset1, 141 isp_pci_dumpregs 142 }; 143 144 static struct ispmdvec mdvec_2400 = { 145 isp_pci_rd_isr_2400, 146 isp_pci_rd_reg_2400, 147 isp_pci_wr_reg_2400, 148 isp_pci_mbxdma, 149 isp_pci_dmasetup, 150 isp_common_dmateardown, 151 isp_pci_reset0, 152 isp_pci_reset1, 153 NULL 154 }; 155 156 static struct ispmdvec mdvec_2500 = { 157 isp_pci_rd_isr_2400, 158 isp_pci_rd_reg_2400, 159 isp_pci_wr_reg_2400, 160 isp_pci_mbxdma, 161 isp_pci_dmasetup, 162 isp_common_dmateardown, 163 isp_pci_reset0, 164 isp_pci_reset1, 165 NULL 166 }; 167 168 #ifndef PCIM_CMD_INVEN 169 #define PCIM_CMD_INVEN 0x10 170 #endif 171 #ifndef PCIM_CMD_BUSMASTEREN 172 #define PCIM_CMD_BUSMASTEREN 0x0004 173 #endif 174 #ifndef PCIM_CMD_PERRESPEN 175 #define PCIM_CMD_PERRESPEN 0x0040 176 #endif 177 #ifndef PCIM_CMD_SEREN 178 #define PCIM_CMD_SEREN 0x0100 179 #endif 180 #ifndef PCIM_CMD_INTX_DISABLE 181 #define PCIM_CMD_INTX_DISABLE 0x0400 182 #endif 183 184 #ifndef PCIR_COMMAND 185 #define PCIR_COMMAND 0x04 186 #endif 187 188 #ifndef PCIR_CACHELNSZ 189 #define PCIR_CACHELNSZ 0x0c 190 #endif 191 192 #ifndef PCIR_LATTIMER 193 #define PCIR_LATTIMER 0x0d 194 #endif 195 196 #ifndef PCIR_ROMADDR 197 #define PCIR_ROMADDR 0x30 198 #endif 199 200 #ifndef PCI_VENDOR_QLOGIC 201 #define PCI_VENDOR_QLOGIC 0x1077 202 #endif 203 204 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 205 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 206 #endif 207 208 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 209 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 210 #endif 211 212 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 213 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 214 #endif 215 216 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 217 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 218 #endif 219 220 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 221 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 222 #endif 223 224 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 225 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 226 #endif 227 228 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 229 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 230 #endif 231 232 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 233 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 234 #endif 235 236 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 237 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 238 #endif 239 240 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 241 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 242 #endif 243 244 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 245 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 246 #endif 247 248 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 249 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 250 #endif 251 252 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 253 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 254 #endif 255 256 #ifndef PCI_PRODUCT_QLOGIC_ISP2532 257 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 258 #endif 259 260 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 261 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 262 #endif 263 264 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 265 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 266 #endif 267 268 #ifndef PCI_PRODUCT_QLOGIC_ISP5432 269 #define PCI_PRODUCT_QLOGIC_ISP5432 0x5432 270 #endif 271 272 #define PCI_QLOGIC_ISP5432 \ 273 ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC) 274 275 #define PCI_QLOGIC_ISP1020 \ 276 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 277 278 #define PCI_QLOGIC_ISP1080 \ 279 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 280 281 #define PCI_QLOGIC_ISP10160 \ 282 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 283 284 #define PCI_QLOGIC_ISP12160 \ 285 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 286 287 #define PCI_QLOGIC_ISP1240 \ 288 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 289 290 #define PCI_QLOGIC_ISP1280 \ 291 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 292 293 #define PCI_QLOGIC_ISP2100 \ 294 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 295 296 #define PCI_QLOGIC_ISP2200 \ 297 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 298 299 #define PCI_QLOGIC_ISP2300 \ 300 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 301 302 #define PCI_QLOGIC_ISP2312 \ 303 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 304 305 #define PCI_QLOGIC_ISP2322 \ 306 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 307 308 #define PCI_QLOGIC_ISP2422 \ 309 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 310 311 #define PCI_QLOGIC_ISP2432 \ 312 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 313 314 #define PCI_QLOGIC_ISP2532 \ 315 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 316 317 #define PCI_QLOGIC_ISP6312 \ 318 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 319 320 #define PCI_QLOGIC_ISP6322 \ 321 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 322 323 /* 324 * Odd case for some AMI raid cards... We need to *not* attach to this. 325 */ 326 #define AMI_RAID_SUBVENDOR_ID 0x101e 327 328 #define IO_MAP_REG 0x10 329 #define MEM_MAP_REG 0x14 330 331 #define PCI_DFLT_LTNCY 0x40 332 #define PCI_DFLT_LNSZ 0x10 333 334 static int isp_pci_probe (device_t); 335 static int isp_pci_attach (device_t); 336 static int isp_pci_detach (device_t); 337 338 339 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 340 struct isp_pcisoftc { 341 ispsoftc_t pci_isp; 342 device_t pci_dev; 343 struct resource * regs; 344 void * irq; 345 int irq_type; 346 int iqd; 347 int rtp; 348 int rgd; 349 void * ih; 350 int16_t pci_poff[_NREG_BLKS]; 351 bus_dma_tag_t dmat; 352 }; 353 354 static int isp_msi_enable = 1; 355 TUNABLE_INT("hw.isp.msi.enable", &isp_msi_enable); 356 357 static device_method_t isp_pci_methods[] = { 358 /* Device interface */ 359 DEVMETHOD(device_probe, isp_pci_probe), 360 DEVMETHOD(device_attach, isp_pci_attach), 361 DEVMETHOD(device_detach, isp_pci_detach), 362 DEVMETHOD_END 363 }; 364 365 static driver_t isp_pci_driver = { 366 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 367 }; 368 static devclass_t isp_devclass; 369 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, NULL, NULL); 370 371 static int 372 isp_pci_probe(device_t dev) 373 { 374 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 375 case PCI_QLOGIC_ISP1020: 376 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 377 break; 378 case PCI_QLOGIC_ISP1080: 379 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 380 break; 381 case PCI_QLOGIC_ISP1240: 382 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 383 break; 384 case PCI_QLOGIC_ISP1280: 385 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 386 break; 387 case PCI_QLOGIC_ISP10160: 388 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 389 break; 390 case PCI_QLOGIC_ISP12160: 391 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 392 return (ENXIO); 393 } 394 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 395 break; 396 case PCI_QLOGIC_ISP2100: 397 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 398 break; 399 case PCI_QLOGIC_ISP2200: 400 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 401 break; 402 case PCI_QLOGIC_ISP2300: 403 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 404 break; 405 case PCI_QLOGIC_ISP2312: 406 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 407 break; 408 case PCI_QLOGIC_ISP2322: 409 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 410 break; 411 case PCI_QLOGIC_ISP2422: 412 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 413 break; 414 case PCI_QLOGIC_ISP2432: 415 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 416 break; 417 case PCI_QLOGIC_ISP2532: 418 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter"); 419 break; 420 case PCI_QLOGIC_ISP5432: 421 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter"); 422 break; 423 case PCI_QLOGIC_ISP6312: 424 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 425 break; 426 case PCI_QLOGIC_ISP6322: 427 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 428 break; 429 default: 430 return (ENXIO); 431 } 432 if (isp_announced == 0 && bootverbose) { 433 kprintf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 434 "Core Version %d.%d\n", 435 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 436 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 437 isp_announced++; 438 } 439 /* 440 * XXXX: Here is where we might load the f/w module 441 * XXXX: (or increase a reference count to it). 442 */ 443 return (BUS_PROBE_DEFAULT); 444 } 445 446 static void 447 isp_get_generic_options(device_t dev, ispsoftc_t *isp, int *nvp) 448 { 449 int tval; 450 451 /* 452 * Figure out if we're supposed to skip this one. 453 */ 454 tval = 0; 455 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "disable", &tval) == 0 && tval) { 456 device_printf(dev, "disabled at user request\n"); 457 isp->isp_osinfo.disabled = 1; 458 return; 459 } 460 461 tval = 0; 462 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) { 463 isp->isp_confopts |= ISP_CFG_NORELOAD; 464 } 465 tval = 0; 466 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) { 467 isp->isp_confopts |= ISP_CFG_NONVRAM; 468 } 469 tval = 0; 470 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval); 471 if (tval) { 472 isp->isp_dblev = tval; 473 } else { 474 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 475 } 476 if (bootverbose) { 477 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 478 } 479 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval); 480 if (tval > 0 && tval < 127) { 481 *nvp = tval; 482 } else { 483 *nvp = 0; 484 } 485 tval = 1; 486 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "autoconfig", &tval); 487 isp_autoconfig = tval; 488 tval = 7; 489 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval); 490 isp_quickboot_time = tval; 491 492 tval = 0; 493 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "forcemulti", &tval) == 0 && tval != 0) { 494 isp->isp_osinfo.forcemulti = 1; 495 } 496 } 497 498 static void 499 isp_get_pci_options(device_t dev, int *m1, int *m2) 500 { 501 int tval; 502 /* 503 * Which we should try first - memory mapping or i/o mapping? 504 * 505 * We used to try memory first followed by i/o on alpha, otherwise 506 * the reverse, but we should just try memory first all the time now. 507 */ 508 *m1 = PCIM_CMD_MEMEN; 509 *m2 = PCIM_CMD_PORTEN; 510 511 tval = 0; 512 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &tval) == 0 && tval != 0) { 513 *m1 = PCIM_CMD_PORTEN; 514 *m2 = PCIM_CMD_MEMEN; 515 } 516 tval = 0; 517 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_memmap", &tval) == 0 && tval != 0) { 518 *m1 = PCIM_CMD_MEMEN; 519 *m2 = PCIM_CMD_PORTEN; 520 } 521 } 522 523 static void 524 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp) 525 { 526 const char *sptr; 527 int tval; 528 529 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "iid", &tval)) { 530 if (IS_FC(isp)) { 531 ISP_FC_PC(isp, chan)->default_id = 109 - chan; 532 } else { 533 ISP_SPI_PC(isp, chan)->iid = 7; 534 } 535 } else { 536 if (IS_FC(isp)) { 537 ISP_FC_PC(isp, chan)->default_id = tval - chan; 538 } else { 539 ISP_SPI_PC(isp, chan)->iid = tval; 540 } 541 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 542 } 543 544 tval = -1; 545 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "role", &tval) == 0) { 546 switch (tval) { 547 case ISP_ROLE_NONE: 548 case ISP_ROLE_INITIATOR: 549 case ISP_ROLE_TARGET: 550 case ISP_ROLE_INITIATOR|ISP_ROLE_TARGET: 551 device_printf(dev, "setting role to 0x%x\n", tval); 552 break; 553 default: 554 tval = -1; 555 break; 556 } 557 } 558 if (tval == -1) { 559 tval = ISP_DEFAULT_ROLES; 560 } 561 562 if (IS_SCSI(isp)) { 563 ISP_SPI_PC(isp, chan)->def_role = tval; 564 return; 565 } 566 ISP_FC_PC(isp, chan)->def_role = tval; 567 568 tval = 0; 569 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fullduplex", &tval) == 0 && tval != 0) { 570 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 571 } 572 sptr = NULL; 573 if (resource_string_value(device_get_name(dev), device_get_unit(dev), "topology", &sptr) == 0 && sptr != NULL) { 574 if (strcmp(sptr, "lport") == 0) { 575 isp->isp_confopts |= ISP_CFG_LPORT; 576 } else if (strcmp(sptr, "nport") == 0) { 577 isp->isp_confopts |= ISP_CFG_NPORT; 578 } else if (strcmp(sptr, "lport-only") == 0) { 579 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 580 } else if (strcmp(sptr, "nport-only") == 0) { 581 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 582 } 583 } 584 585 /* 586 * Because the resource_*_value functions can neither return 587 * 64 bit integer values, nor can they be directly coerced 588 * to interpret the right hand side of the assignment as 589 * you want them to interpret it, we have to force WWN 590 * hint replacement to specify WWN strings with a leading 591 * 'w' (e..g w50000000aaaa0001). Sigh. 592 */ 593 sptr = NULL; 594 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "portwwn", &sptr); 595 if (tval == 0 && sptr != NULL && *sptr++ == 'w') { 596 char *eptr = NULL; 597 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16); 598 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) { 599 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 600 ISP_FC_PC(isp, chan)->def_wwpn = 0; 601 } 602 } 603 604 sptr = NULL; 605 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "nodewwn", &sptr); 606 if (tval == 0 && sptr != NULL && *sptr++ == 'w') { 607 char *eptr = NULL; 608 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16); 609 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) { 610 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 611 ISP_FC_PC(isp, chan)->def_wwnn = 0; 612 } 613 } 614 615 tval = 0; 616 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "hysteresis", &tval); 617 if (tval >= 0 && tval < 256) { 618 ISP_FC_PC(isp, chan)->hysteresis = tval; 619 } else { 620 ISP_FC_PC(isp, chan)->hysteresis = isp_fabric_hysteresis; 621 } 622 623 tval = -1; 624 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "loop_down_limit", &tval); 625 if (tval >= 0 && tval < 0xffff) { 626 ISP_FC_PC(isp, chan)->loop_down_limit = tval; 627 } else { 628 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit; 629 } 630 631 tval = -1; 632 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "gone_device_time", &tval); 633 if (tval >= 0 && tval < 0xffff) { 634 ISP_FC_PC(isp, chan)->gone_device_time = tval; 635 } else { 636 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time; 637 } 638 } 639 640 static int 641 isp_pci_attach(device_t dev) 642 { 643 int i, m1, m2, locksetup = 0; 644 int isp_nvports = 0; 645 uint32_t data, cmd, linesz, did; 646 struct isp_pcisoftc *pcs; 647 ispsoftc_t *isp; 648 size_t psize, xsize; 649 char fwname[32]; 650 u_int irq_flags; 651 652 pcs = device_get_softc(dev); 653 if (pcs == NULL) { 654 device_printf(dev, "cannot get softc\n"); 655 return (ENOMEM); 656 } 657 memset(pcs, 0, sizeof (*pcs)); 658 659 pcs->pci_dev = dev; 660 isp = &pcs->pci_isp; 661 isp->isp_dev = dev; 662 isp->isp_nchan = 1; 663 664 /* 665 * Get Generic Options 666 */ 667 isp_get_generic_options(dev, isp, &isp_nvports); 668 669 /* 670 * Check to see if options have us disabled 671 */ 672 if (isp->isp_osinfo.disabled) { 673 /* 674 * But return zero to preserve unit numbering 675 */ 676 return (0); 677 } 678 679 /* 680 * Get PCI options- which in this case are just mapping preferences. 681 */ 682 isp_get_pci_options(dev, &m1, &m2); 683 684 linesz = PCI_DFLT_LNSZ; 685 pcs->irq = pcs->regs = NULL; 686 pcs->rgd = pcs->rtp = pcs->iqd = 0; 687 688 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 689 if (cmd & m1) { 690 pcs->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 691 pcs->rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 692 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 693 } 694 if (pcs->regs == NULL && (cmd & m2)) { 695 pcs->rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 696 pcs->rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 697 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 698 } 699 if (pcs->regs == NULL) { 700 device_printf(dev, "unable to map any ports\n"); 701 goto bad; 702 } 703 if (bootverbose) { 704 device_printf(dev, "using %s space register mapping\n", (pcs->rgd == IO_MAP_REG)? "I/O" : "Memory"); 705 } 706 isp->isp_bus_tag = rman_get_bustag(pcs->regs); 707 isp->isp_bus_handle = rman_get_bushandle(pcs->regs); 708 709 pcs->pci_dev = dev; 710 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 711 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 712 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 713 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 714 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 715 716 switch (pci_get_devid(dev)) { 717 case PCI_QLOGIC_ISP1020: 718 did = 0x1040; 719 isp->isp_mdvec = &mdvec; 720 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 721 break; 722 case PCI_QLOGIC_ISP1080: 723 did = 0x1080; 724 isp->isp_mdvec = &mdvec_1080; 725 isp->isp_type = ISP_HA_SCSI_1080; 726 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 727 break; 728 case PCI_QLOGIC_ISP1240: 729 did = 0x1080; 730 isp->isp_mdvec = &mdvec_1080; 731 isp->isp_type = ISP_HA_SCSI_1240; 732 isp->isp_nchan = 2; 733 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 734 break; 735 case PCI_QLOGIC_ISP1280: 736 did = 0x1080; 737 isp->isp_mdvec = &mdvec_1080; 738 isp->isp_type = ISP_HA_SCSI_1280; 739 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 740 break; 741 case PCI_QLOGIC_ISP10160: 742 did = 0x12160; 743 isp->isp_mdvec = &mdvec_12160; 744 isp->isp_type = ISP_HA_SCSI_10160; 745 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 746 break; 747 case PCI_QLOGIC_ISP12160: 748 did = 0x12160; 749 isp->isp_nchan = 2; 750 isp->isp_mdvec = &mdvec_12160; 751 isp->isp_type = ISP_HA_SCSI_12160; 752 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 753 break; 754 case PCI_QLOGIC_ISP2100: 755 did = 0x2100; 756 isp->isp_mdvec = &mdvec_2100; 757 isp->isp_type = ISP_HA_FC_2100; 758 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 759 if (pci_get_revid(dev) < 3) { 760 /* 761 * XXX: Need to get the actual revision 762 * XXX: number of the 2100 FB. At any rate, 763 * XXX: lower cache line size for early revision 764 * XXX; boards. 765 */ 766 linesz = 1; 767 } 768 break; 769 case PCI_QLOGIC_ISP2200: 770 did = 0x2200; 771 isp->isp_mdvec = &mdvec_2200; 772 isp->isp_type = ISP_HA_FC_2200; 773 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 774 break; 775 case PCI_QLOGIC_ISP2300: 776 did = 0x2300; 777 isp->isp_mdvec = &mdvec_2300; 778 isp->isp_type = ISP_HA_FC_2300; 779 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 780 break; 781 case PCI_QLOGIC_ISP2312: 782 case PCI_QLOGIC_ISP6312: 783 did = 0x2300; 784 isp->isp_mdvec = &mdvec_2300; 785 isp->isp_type = ISP_HA_FC_2312; 786 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 787 break; 788 case PCI_QLOGIC_ISP2322: 789 case PCI_QLOGIC_ISP6322: 790 did = 0x2322; 791 isp->isp_mdvec = &mdvec_2300; 792 isp->isp_type = ISP_HA_FC_2322; 793 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 794 break; 795 case PCI_QLOGIC_ISP2422: 796 case PCI_QLOGIC_ISP2432: 797 did = 0x2400; 798 isp->isp_nchan += isp_nvports; 799 isp->isp_mdvec = &mdvec_2400; 800 isp->isp_type = ISP_HA_FC_2400; 801 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 802 break; 803 case PCI_QLOGIC_ISP2532: 804 did = 0x2500; 805 isp->isp_nchan += isp_nvports; 806 isp->isp_mdvec = &mdvec_2500; 807 isp->isp_type = ISP_HA_FC_2500; 808 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 809 break; 810 case PCI_QLOGIC_ISP5432: 811 did = 0x2500; 812 isp->isp_mdvec = &mdvec_2500; 813 isp->isp_type = ISP_HA_FC_2500; 814 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 815 break; 816 default: 817 device_printf(dev, "unknown device type\n"); 818 goto bad; 819 break; 820 } 821 isp->isp_revision = pci_get_revid(dev); 822 823 if (IS_FC(isp)) { 824 psize = sizeof (fcparam); 825 xsize = sizeof (struct isp_fc); 826 } else { 827 psize = sizeof (sdparam); 828 xsize = sizeof (struct isp_spi); 829 } 830 psize *= isp->isp_nchan; 831 xsize *= isp->isp_nchan; 832 isp->isp_param = kmalloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 833 if (isp->isp_param == NULL) { 834 device_printf(dev, "cannot allocate parameter data\n"); 835 goto bad; 836 } 837 isp->isp_osinfo.pc.ptr = kmalloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO); 838 if (isp->isp_osinfo.pc.ptr == NULL) { 839 device_printf(dev, "cannot allocate parameter data\n"); 840 goto bad; 841 } 842 843 /* 844 * Now that we know who we are (roughly) get/set specific options 845 */ 846 for (i = 0; i < isp->isp_nchan; i++) { 847 isp_get_specific_options(dev, i, isp); 848 } 849 850 /* 851 * The 'it' suffix really only matters for SCSI cards in target mode. 852 */ 853 isp->isp_osinfo.fw = NULL; 854 if (IS_SCSI(isp) && (ISP_SPI_PC(isp, 0)->def_role & ISP_ROLE_TARGET)) { 855 ksnprintf(fwname, sizeof (fwname), "isp_%04x_it", did); 856 isp->isp_osinfo.fw = firmware_get(fwname); 857 } else if (IS_24XX(isp) && (isp->isp_nchan > 1 || isp->isp_osinfo.forcemulti)) { 858 ksnprintf(fwname, sizeof (fwname), "isp_%04x_multi", did); 859 isp->isp_osinfo.fw = firmware_get(fwname); 860 } 861 if (isp->isp_osinfo.fw == NULL) { 862 ksnprintf(fwname, sizeof (fwname), "isp_%04x", did); 863 isp->isp_osinfo.fw = firmware_get(fwname); 864 } 865 if (isp->isp_osinfo.fw != NULL) { 866 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 867 } 868 869 /* 870 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 871 * are set. 872 */ 873 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 874 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 875 876 if (IS_2300(isp)) { /* per QLogic errata */ 877 cmd &= ~PCIM_CMD_INVEN; 878 } 879 880 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 881 cmd &= ~PCIM_CMD_INTX_DISABLE; 882 } 883 884 if (IS_24XX(isp)) { 885 cmd &= ~PCIM_CMD_INTX_DISABLE; 886 } 887 888 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 889 890 /* 891 * Make sure the Cache Line Size register is set sensibly. 892 */ 893 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 894 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 895 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d from %d", linesz, data); 896 data = linesz; 897 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 898 } 899 900 /* 901 * Make sure the Latency Timer is sane. 902 */ 903 data = pci_read_config(dev, PCIR_LATTIMER, 1); 904 if (data < PCI_DFLT_LTNCY) { 905 data = PCI_DFLT_LTNCY; 906 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 907 pci_write_config(dev, PCIR_LATTIMER, data, 1); 908 } 909 910 /* 911 * Make sure we've disabled the ROM. 912 */ 913 data = pci_read_config(dev, PCIR_ROMADDR, 4); 914 data &= ~1; 915 pci_write_config(dev, PCIR_ROMADDR, data, 4); 916 917 pcs->irq_type = pci_alloc_1intr(dev, isp_msi_enable, &pcs->iqd, 918 &irq_flags); 919 pcs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &pcs->iqd, 920 irq_flags); 921 if (pcs->irq == NULL) { 922 device_printf(dev, "could not allocate interrupt\n"); 923 goto bad; 924 } 925 926 /* Make sure the lock is set up. */ 927 lockinit(&isp->isp_osinfo.lock, "isp", 0, LK_CANRECURSE); 928 locksetup++; 929 930 if (isp_setup_intr(dev, pcs->irq, ISP_IFLAGS, isp_platform_intr, isp, &pcs->ih, NULL)) { 931 device_printf(dev, "could not setup interrupt\n"); 932 goto bad; 933 } 934 935 /* 936 * Last minute checks... 937 */ 938 if (IS_23XX(isp) || IS_24XX(isp)) { 939 isp->isp_port = pci_get_function(dev); 940 } 941 942 /* 943 * Make sure we're in reset state. 944 */ 945 ISP_LOCK(isp); 946 isp_reset(isp, 1); 947 if (isp->isp_state != ISP_RESETSTATE) { 948 ISP_UNLOCK(isp); 949 goto bad; 950 } 951 isp_init(isp); 952 if (isp->isp_state == ISP_INITSTATE) { 953 isp->isp_state = ISP_RUNSTATE; 954 } 955 ISP_UNLOCK(isp); 956 if (isp_attach(isp)) { 957 ISP_LOCK(isp); 958 isp_uninit(isp); 959 ISP_UNLOCK(isp); 960 goto bad; 961 } 962 return (0); 963 964 bad: 965 if (pcs->ih) { 966 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 967 } 968 if (locksetup) { 969 lockuninit(&isp->isp_osinfo.lock); 970 } 971 if (pcs->irq) { 972 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 973 } 974 if (pcs->irq_type == PCI_INTR_TYPE_MSI) { 975 pci_release_msi(dev); 976 } 977 if (pcs->regs) { 978 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 979 } 980 if (pcs->pci_isp.isp_param) { 981 kfree(pcs->pci_isp.isp_param, M_DEVBUF); 982 pcs->pci_isp.isp_param = NULL; 983 } 984 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 985 kfree(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 986 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 987 } 988 return (ENXIO); 989 } 990 991 static int 992 isp_pci_detach(device_t dev) 993 { 994 struct isp_pcisoftc *pcs; 995 ispsoftc_t *isp; 996 int status; 997 998 pcs = device_get_softc(dev); 999 if (pcs == NULL) { 1000 return (ENXIO); 1001 } 1002 isp = (ispsoftc_t *) pcs; 1003 status = isp_detach(isp); 1004 if (status) 1005 return (status); 1006 ISP_LOCK(isp); 1007 isp_uninit(isp); 1008 if (pcs->ih) { 1009 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 1010 } 1011 ISP_UNLOCK(isp); 1012 lockuninit(&isp->isp_osinfo.lock); 1013 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 1014 if (pcs->irq_type == PCI_INTR_TYPE_MSI) { 1015 pci_release_msi(dev); 1016 } 1017 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 1018 if (pcs->pci_isp.isp_param) { 1019 kfree(pcs->pci_isp.isp_param, M_DEVBUF); 1020 pcs->pci_isp.isp_param = NULL; 1021 } 1022 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1023 kfree(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1024 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1025 } 1026 return (0); 1027 } 1028 1029 #define IspVirt2Off(a, x) \ 1030 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1031 _BLK_REG_SHFT] + ((x) & 0xfff)) 1032 1033 #define BXR2(isp, off) \ 1034 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off) 1035 #define BXW2(isp, off, v) \ 1036 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1037 #define BXR4(isp, off) \ 1038 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off) 1039 #define BXW4(isp, off, v) \ 1040 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1041 1042 1043 static ISP_INLINE int 1044 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp) 1045 { 1046 uint32_t val0, val1; 1047 int i = 0; 1048 1049 do { 1050 val0 = BXR2(isp, IspVirt2Off(isp, off)); 1051 val1 = BXR2(isp, IspVirt2Off(isp, off)); 1052 } while (val0 != val1 && ++i < 1000); 1053 if (val0 != val1) { 1054 return (1); 1055 } 1056 *rp = val0; 1057 return (0); 1058 } 1059 1060 static int 1061 isp_pci_rd_isr(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbp) 1062 { 1063 uint16_t isr, sema; 1064 1065 if (IS_2100(isp)) { 1066 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 1067 return (0); 1068 } 1069 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 1070 return (0); 1071 } 1072 } else { 1073 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1074 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1075 } 1076 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1077 isr &= INT_PENDING_MASK(isp); 1078 sema &= BIU_SEMA_LOCK; 1079 if (isr == 0 && sema == 0) { 1080 return (0); 1081 } 1082 *isrp = isr; 1083 if ((*semap = sema) != 0) { 1084 if (IS_2100(isp)) { 1085 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 1086 return (0); 1087 } 1088 } else { 1089 *mbp = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1090 } 1091 } 1092 return (1); 1093 } 1094 1095 static int 1096 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1097 { 1098 uint32_t hccr; 1099 uint32_t r2hisr; 1100 1101 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 1102 *isrp = 0; 1103 return (0); 1104 } 1105 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1106 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1107 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1108 *isrp = 0; 1109 return (0); 1110 } 1111 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 1112 case ISPR2HST_ROM_MBX_OK: 1113 case ISPR2HST_ROM_MBX_FAIL: 1114 case ISPR2HST_MBX_OK: 1115 case ISPR2HST_MBX_FAIL: 1116 case ISPR2HST_ASYNC_EVENT: 1117 *isrp = r2hisr & 0xffff; 1118 *mbox0p = (r2hisr >> 16); 1119 *semap = 1; 1120 return (1); 1121 case ISPR2HST_RIO_16: 1122 *isrp = r2hisr & 0xffff; 1123 *mbox0p = ASYNC_RIO16_1; 1124 *semap = 1; 1125 return (1); 1126 case ISPR2HST_FPOST: 1127 *isrp = r2hisr & 0xffff; 1128 *mbox0p = ASYNC_CMD_CMPLT; 1129 *semap = 1; 1130 return (1); 1131 case ISPR2HST_FPOST_CTIO: 1132 *isrp = r2hisr & 0xffff; 1133 *mbox0p = ASYNC_CTIO_DONE; 1134 *semap = 1; 1135 return (1); 1136 case ISPR2HST_RSPQ_UPDATE: 1137 *isrp = r2hisr & 0xffff; 1138 *mbox0p = 0; 1139 *semap = 0; 1140 return (1); 1141 default: 1142 hccr = ISP_READ(isp, HCCR); 1143 if (hccr & HCCR_PAUSE) { 1144 ISP_WRITE(isp, HCCR, HCCR_RESET); 1145 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR)); 1146 ISP_WRITE(isp, BIU_ICR, 0); 1147 } else { 1148 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1149 } 1150 return (0); 1151 } 1152 } 1153 1154 static int 1155 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1156 { 1157 uint32_t r2hisr; 1158 1159 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1160 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1161 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 1162 *isrp = 0; 1163 return (0); 1164 } 1165 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 1166 case ISP2400R2HST_ROM_MBX_OK: 1167 case ISP2400R2HST_ROM_MBX_FAIL: 1168 case ISP2400R2HST_MBX_OK: 1169 case ISP2400R2HST_MBX_FAIL: 1170 case ISP2400R2HST_ASYNC_EVENT: 1171 *isrp = r2hisr & 0xffff; 1172 *mbox0p = (r2hisr >> 16); 1173 *semap = 1; 1174 return (1); 1175 case ISP2400R2HST_RSPQ_UPDATE: 1176 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 1177 case ISP2400R2HST_ATIO_RQST_UPDATE: 1178 *isrp = r2hisr & 0xffff; 1179 *mbox0p = 0; 1180 *semap = 0; 1181 return (1); 1182 default: 1183 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1184 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1185 return (0); 1186 } 1187 } 1188 1189 static uint32_t 1190 isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1191 { 1192 uint16_t rv; 1193 int oldconf = 0; 1194 1195 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1196 /* 1197 * We will assume that someone has paused the RISC processor. 1198 */ 1199 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1200 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); 1201 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1202 } 1203 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1204 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1205 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1206 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1207 } 1208 return (rv); 1209 } 1210 1211 static void 1212 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1213 { 1214 int oldconf = 0; 1215 1216 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1217 /* 1218 * We will assume that someone has paused the RISC processor. 1219 */ 1220 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1221 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1222 oldconf | BIU_PCI_CONF1_SXP); 1223 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1224 } 1225 BXW2(isp, IspVirt2Off(isp, regoff), val); 1226 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1227 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1228 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1229 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1230 } 1231 1232 } 1233 1234 static uint32_t 1235 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1236 { 1237 uint32_t rv, oc = 0; 1238 1239 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1240 uint32_t tc; 1241 /* 1242 * We will assume that someone has paused the RISC processor. 1243 */ 1244 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1245 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1246 if (regoff & SXP_BANK1_SELECT) 1247 tc |= BIU_PCI1080_CONF1_SXP1; 1248 else 1249 tc |= BIU_PCI1080_CONF1_SXP0; 1250 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1251 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1252 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1253 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1254 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1255 oc | BIU_PCI1080_CONF1_DMA); 1256 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1257 } 1258 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1259 if (oc) { 1260 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1261 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1262 } 1263 return (rv); 1264 } 1265 1266 static void 1267 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1268 { 1269 int oc = 0; 1270 1271 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1272 uint32_t tc; 1273 /* 1274 * We will assume that someone has paused the RISC processor. 1275 */ 1276 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1277 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1278 if (regoff & SXP_BANK1_SELECT) 1279 tc |= BIU_PCI1080_CONF1_SXP1; 1280 else 1281 tc |= BIU_PCI1080_CONF1_SXP0; 1282 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1283 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1284 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1285 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1286 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1287 oc | BIU_PCI1080_CONF1_DMA); 1288 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1289 } 1290 BXW2(isp, IspVirt2Off(isp, regoff), val); 1291 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1292 if (oc) { 1293 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1294 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1295 } 1296 } 1297 1298 static uint32_t 1299 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1300 { 1301 uint32_t rv; 1302 int block = regoff & _BLK_REG_MASK; 1303 1304 switch (block) { 1305 case BIU_BLOCK: 1306 break; 1307 case MBOX_BLOCK: 1308 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1309 case SXP_BLOCK: 1310 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 1311 return (0xffffffff); 1312 case RISC_BLOCK: 1313 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 1314 return (0xffffffff); 1315 case DMA_BLOCK: 1316 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 1317 return (0xffffffff); 1318 default: 1319 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 1320 return (0xffffffff); 1321 } 1322 1323 1324 switch (regoff) { 1325 case BIU2400_FLASH_ADDR: 1326 case BIU2400_FLASH_DATA: 1327 case BIU2400_ICR: 1328 case BIU2400_ISR: 1329 case BIU2400_CSR: 1330 case BIU2400_REQINP: 1331 case BIU2400_REQOUTP: 1332 case BIU2400_RSPINP: 1333 case BIU2400_RSPOUTP: 1334 case BIU2400_PRI_REQINP: 1335 case BIU2400_PRI_REQOUTP: 1336 case BIU2400_ATIO_RSPINP: 1337 case BIU2400_ATIO_RSPOUTP: 1338 case BIU2400_HCCR: 1339 case BIU2400_GPIOD: 1340 case BIU2400_GPIOE: 1341 case BIU2400_HSEMA: 1342 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1343 break; 1344 case BIU2400_R2HSTSLO: 1345 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1346 break; 1347 case BIU2400_R2HSTSHI: 1348 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1349 break; 1350 default: 1351 isp_prt(isp, ISP_LOGERR, 1352 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1353 rv = 0xffffffff; 1354 break; 1355 } 1356 return (rv); 1357 } 1358 1359 static void 1360 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1361 { 1362 int block = regoff & _BLK_REG_MASK; 1363 1364 switch (block) { 1365 case BIU_BLOCK: 1366 break; 1367 case MBOX_BLOCK: 1368 BXW2(isp, IspVirt2Off(isp, regoff), val); 1369 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1370 return; 1371 case SXP_BLOCK: 1372 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1373 return; 1374 case RISC_BLOCK: 1375 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1376 return; 1377 case DMA_BLOCK: 1378 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1379 return; 1380 default: 1381 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1382 regoff); 1383 break; 1384 } 1385 1386 switch (regoff) { 1387 case BIU2400_FLASH_ADDR: 1388 case BIU2400_FLASH_DATA: 1389 case BIU2400_ICR: 1390 case BIU2400_ISR: 1391 case BIU2400_CSR: 1392 case BIU2400_REQINP: 1393 case BIU2400_REQOUTP: 1394 case BIU2400_RSPINP: 1395 case BIU2400_RSPOUTP: 1396 case BIU2400_PRI_REQINP: 1397 case BIU2400_PRI_REQOUTP: 1398 case BIU2400_ATIO_RSPINP: 1399 case BIU2400_ATIO_RSPOUTP: 1400 case BIU2400_HCCR: 1401 case BIU2400_GPIOD: 1402 case BIU2400_GPIOE: 1403 case BIU2400_HSEMA: 1404 BXW4(isp, IspVirt2Off(isp, regoff), val); 1405 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1); 1406 break; 1407 default: 1408 isp_prt(isp, ISP_LOGERR, 1409 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1410 break; 1411 } 1412 } 1413 1414 1415 struct imush { 1416 ispsoftc_t *isp; 1417 caddr_t vbase; 1418 int chan; 1419 int error; 1420 }; 1421 1422 static void imc(void *, bus_dma_segment_t *, int, int); 1423 static void imc1(void *, bus_dma_segment_t *, int, int); 1424 1425 static void 1426 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1427 { 1428 struct imush *imushp = (struct imush *) arg; 1429 1430 if (error) { 1431 imushp->error = error; 1432 return; 1433 } 1434 if (nseg != 1) { 1435 imushp->error = EINVAL; 1436 return; 1437 } 1438 isp_prt(imushp->isp, ISP_LOGDEBUG0, "request/result area @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1439 imushp->isp->isp_rquest = imushp->vbase; 1440 imushp->isp->isp_rquest_dma = segs->ds_addr; 1441 segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1442 imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1443 imushp->isp->isp_result_dma = segs->ds_addr; 1444 imushp->isp->isp_result = imushp->vbase; 1445 1446 #ifdef ISP_TARGET_MODE 1447 if (IS_24XX(imushp->isp)) { 1448 segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1449 imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1450 imushp->isp->isp_atioq_dma = segs->ds_addr; 1451 imushp->isp->isp_atioq = imushp->vbase; 1452 } 1453 #endif 1454 } 1455 1456 static void 1457 imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1458 { 1459 struct imush *imushp = (struct imush *) arg; 1460 if (error) { 1461 imushp->error = error; 1462 return; 1463 } 1464 if (nseg != 1) { 1465 imushp->error = EINVAL; 1466 return; 1467 } 1468 isp_prt(imushp->isp, ISP_LOGDEBUG0, "scdma @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1469 FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr; 1470 FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase; 1471 } 1472 1473 static int 1474 isp_pci_mbxdma(ispsoftc_t *isp) 1475 { 1476 caddr_t base; 1477 uint32_t len; 1478 int i, error, ns, cmap = 0; 1479 bus_size_t slim; /* segment size */ 1480 bus_addr_t llim; /* low limit of unavailable dma */ 1481 bus_addr_t hlim; /* high limit of unavailable dma */ 1482 struct imush im; 1483 1484 /* 1485 * Already been here? If so, leave... 1486 */ 1487 if (isp->isp_rquest) { 1488 return (0); 1489 } 1490 ISP_UNLOCK(isp); 1491 1492 if (isp->isp_maxcmds == 0) { 1493 isp_prt(isp, ISP_LOGERR, "maxcmds not set"); 1494 ISP_LOCK(isp); 1495 return (1); 1496 } 1497 1498 hlim = BUS_SPACE_MAXADDR; 1499 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1500 if (sizeof (bus_size_t) > 4) { 1501 slim = (bus_size_t) (1ULL << 32); 1502 } else { 1503 slim = (bus_size_t) (1UL << 31); 1504 } 1505 llim = BUS_SPACE_MAXADDR; 1506 } else { 1507 llim = BUS_SPACE_MAXADDR_32BIT; 1508 slim = (1UL << 24); 1509 } 1510 1511 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1512 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) kmalloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1513 if (isp->isp_osinfo.pcmd_pool == NULL) { 1514 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds"); 1515 ISP_LOCK(isp); 1516 return (1); 1517 } 1518 1519 /* 1520 * XXX: We don't really support 64 bit target mode for parallel scsi yet 1521 */ 1522 #ifdef ISP_TARGET_MODE 1523 if (IS_SCSI(isp) && sizeof (bus_addr_t) > 4) { 1524 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1525 isp_prt(isp, ISP_LOGERR, "we cannot do DAC for SPI cards yet"); 1526 ISP_LOCK(isp); 1527 return (1); 1528 } 1529 #endif 1530 1531 if (isp_dma_tag_create(NULL, 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, slim, 0, &isp->isp_osinfo.dmat)) { 1532 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1533 ISP_LOCK(isp); 1534 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1535 return (1); 1536 } 1537 1538 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1539 isp->isp_xflist = (isp_hdl_t *) kmalloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1540 if (isp->isp_xflist == NULL) { 1541 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1542 ISP_LOCK(isp); 1543 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1544 return (1); 1545 } 1546 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1547 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1548 } 1549 isp->isp_xffree = isp->isp_xflist; 1550 #ifdef ISP_TARGET_MODE 1551 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1552 isp->isp_tgtlist = (isp_hdl_t *) kmalloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1553 if (isp->isp_tgtlist == NULL) { 1554 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1555 kfree(isp->isp_xflist, M_DEVBUF); 1556 ISP_LOCK(isp); 1557 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array"); 1558 return (1); 1559 } 1560 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1561 isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1]; 1562 } 1563 isp->isp_tgtfree = isp->isp_tgtlist; 1564 #endif 1565 1566 /* 1567 * Allocate and map the request and result queues (and ATIO queue 1568 * if we're a 2400 supporting target mode). 1569 */ 1570 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1571 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1572 #ifdef ISP_TARGET_MODE 1573 if (IS_24XX(isp)) { 1574 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1575 } 1576 #endif 1577 1578 ns = (len / PAGE_SIZE) + 1; 1579 1580 /* 1581 * Create a tag for the control spaces. We don't always need this 1582 * to be 32 bits, but we do this for simplicity and speed's sake. 1583 */ 1584 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, ns, slim, 0, &isp->isp_osinfo.cdmat)) { 1585 isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces"); 1586 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1587 kfree(isp->isp_xflist, M_DEVBUF); 1588 #ifdef ISP_TARGET_MODE 1589 kfree(isp->isp_tgtlist, M_DEVBUF); 1590 #endif 1591 ISP_LOCK(isp); 1592 return (1); 1593 } 1594 1595 if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &isp->isp_osinfo.cdmap) != 0) { 1596 isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len); 1597 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1598 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1599 kfree(isp->isp_xflist, M_DEVBUF); 1600 #ifdef ISP_TARGET_MODE 1601 kfree(isp->isp_tgtlist, M_DEVBUF); 1602 #endif 1603 ISP_LOCK(isp); 1604 return (1); 1605 } 1606 1607 im.isp = isp; 1608 im.chan = 0; 1609 im.vbase = base; 1610 im.error = 0; 1611 1612 bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0); 1613 if (im.error) { 1614 isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error); 1615 goto bad; 1616 } 1617 1618 if (IS_FC(isp)) { 1619 for (cmap = 0; cmap < isp->isp_nchan; cmap++) { 1620 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1621 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) { 1622 goto bad; 1623 } 1624 if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &fc->tdmap) != 0) { 1625 bus_dma_tag_destroy(fc->tdmat); 1626 goto bad; 1627 } 1628 im.isp = isp; 1629 im.chan = cmap; 1630 im.vbase = base; 1631 im.error = 0; 1632 bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0); 1633 if (im.error) { 1634 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1635 bus_dma_tag_destroy(fc->tdmat); 1636 goto bad; 1637 } 1638 } 1639 } 1640 1641 for (i = 0; i < isp->isp_maxcmds; i++) { 1642 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1643 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1644 if (error) { 1645 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error); 1646 while (--i >= 0) { 1647 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap); 1648 } 1649 goto bad; 1650 } 1651 callout_init(&pcmd->wdog); 1652 if (i == isp->isp_maxcmds-1) { 1653 pcmd->next = NULL; 1654 } else { 1655 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1656 } 1657 } 1658 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1659 ISP_LOCK(isp); 1660 return (0); 1661 1662 bad: 1663 while (--cmap >= 0) { 1664 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1665 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1666 bus_dma_tag_destroy(fc->tdmat); 1667 } 1668 bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap); 1669 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1670 kfree(isp->isp_xflist, M_DEVBUF); 1671 #ifdef ISP_TARGET_MODE 1672 kfree(isp->isp_tgtlist, M_DEVBUF); 1673 #endif 1674 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1675 isp->isp_rquest = NULL; 1676 ISP_LOCK(isp); 1677 return (1); 1678 } 1679 1680 typedef struct { 1681 ispsoftc_t *isp; 1682 void *cmd_token; 1683 void *rq; /* original request */ 1684 int error; 1685 bus_size_t mapsize; 1686 } mush_t; 1687 1688 #define MUSHERR_NOQENTRIES -2 1689 1690 #ifdef ISP_TARGET_MODE 1691 static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1692 static void tdma2(void *, bus_dma_segment_t *, int, int); 1693 1694 static void 1695 tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1696 { 1697 mush_t *mp; 1698 mp = (mush_t *)arg; 1699 mp->mapsize = mapsize; 1700 tdma2(arg, dm_segs, nseg, error); 1701 } 1702 1703 static void 1704 tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1705 { 1706 mush_t *mp; 1707 ispsoftc_t *isp; 1708 struct ccb_scsiio *csio; 1709 isp_ddir_t ddir; 1710 ispreq_t *rq; 1711 1712 mp = (mush_t *) arg; 1713 if (error) { 1714 mp->error = error; 1715 return; 1716 } 1717 csio = mp->cmd_token; 1718 isp = mp->isp; 1719 rq = mp->rq; 1720 if (nseg) { 1721 if (sizeof (bus_addr_t) > 4) { 1722 if (nseg >= ISP_NSEG64_MAX) { 1723 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1724 mp->error = EFAULT; 1725 return; 1726 } 1727 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) { 1728 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3; 1729 } 1730 } else { 1731 if (nseg >= ISP_NSEG_MAX) { 1732 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1733 mp->error = EFAULT; 1734 return; 1735 } 1736 } 1737 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1738 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1739 ddir = ISP_TO_DEVICE; 1740 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1741 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1742 ddir = ISP_FROM_DEVICE; 1743 } else { 1744 dm_segs = NULL; 1745 nseg = 0; 1746 ddir = ISP_NOXFR; 1747 } 1748 } else { 1749 dm_segs = NULL; 1750 nseg = 0; 1751 ddir = ISP_NOXFR; 1752 } 1753 1754 if (isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len) != CMD_QUEUED) { 1755 mp->error = MUSHERR_NOQENTRIES; 1756 } 1757 } 1758 #endif 1759 1760 static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1761 static void dma2(void *, bus_dma_segment_t *, int, int); 1762 1763 static void 1764 dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1765 { 1766 mush_t *mp; 1767 mp = (mush_t *)arg; 1768 mp->mapsize = mapsize; 1769 dma2(arg, dm_segs, nseg, error); 1770 } 1771 1772 static void 1773 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1774 { 1775 mush_t *mp; 1776 ispsoftc_t *isp; 1777 struct ccb_scsiio *csio; 1778 isp_ddir_t ddir; 1779 ispreq_t *rq; 1780 1781 mp = (mush_t *) arg; 1782 if (error) { 1783 mp->error = error; 1784 return; 1785 } 1786 csio = mp->cmd_token; 1787 isp = mp->isp; 1788 rq = mp->rq; 1789 if (nseg) { 1790 if (sizeof (bus_addr_t) > 4) { 1791 if (nseg >= ISP_NSEG64_MAX) { 1792 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1793 mp->error = EFAULT; 1794 return; 1795 } 1796 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1797 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1798 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1799 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1800 } 1801 } else { 1802 if (nseg >= ISP_NSEG_MAX) { 1803 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1804 mp->error = EFAULT; 1805 return; 1806 } 1807 } 1808 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1809 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1810 ddir = ISP_FROM_DEVICE; 1811 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1812 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1813 ddir = ISP_TO_DEVICE; 1814 } else { 1815 ddir = ISP_NOXFR; 1816 } 1817 } else { 1818 dm_segs = NULL; 1819 nseg = 0; 1820 ddir = ISP_NOXFR; 1821 } 1822 1823 if (isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir) != CMD_QUEUED) { 1824 mp->error = MUSHERR_NOQENTRIES; 1825 } 1826 } 1827 1828 static int 1829 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) 1830 { 1831 mush_t mush, *mp; 1832 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1833 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int); 1834 1835 mp = &mush; 1836 mp->isp = isp; 1837 mp->cmd_token = csio; 1838 mp->rq = ff; 1839 mp->error = 0; 1840 mp->mapsize = 0; 1841 1842 #ifdef ISP_TARGET_MODE 1843 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1844 eptr = tdma2; 1845 eptr2 = tdma2_2; 1846 } else 1847 #endif 1848 { 1849 eptr = dma2; 1850 eptr2 = dma2_2; 1851 } 1852 1853 1854 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || (csio->dxfer_len == 0)) { 1855 (*eptr)(mp, NULL, 0, 0); 1856 } else if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1857 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1858 int error; 1859 error = bus_dmamap_load(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1860 #if 0 1861 xpt_print(csio->ccb_h.path, "%s: bus_dmamap_load " "ptr %p len %d returned %d\n", __func__, csio->data_ptr, csio->dxfer_len, error); 1862 #endif 1863 1864 if (error == EINPROGRESS) { 1865 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); 1866 mp->error = EINVAL; 1867 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported"); 1868 } else if (error && mp->error == 0) { 1869 #ifdef DIAGNOSTIC 1870 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1871 #endif 1872 mp->error = error; 1873 } 1874 } else { 1875 /* Pointer to physical buffer */ 1876 struct bus_dma_segment seg; 1877 seg.ds_addr = (bus_addr_t)(vm_offset_t)csio->data_ptr; 1878 seg.ds_len = csio->dxfer_len; 1879 (*eptr)(mp, &seg, 1, 0); 1880 } 1881 } else { 1882 struct bus_dma_segment *segs; 1883 1884 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1885 isp_prt(isp, ISP_LOGERR, "Physical segment pointers unsupported"); 1886 mp->error = EINVAL; 1887 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1888 struct uio sguio; 1889 int error; 1890 1891 /* 1892 * We're taking advantage of the fact that 1893 * the pointer/length sizes and layout of the iovec 1894 * structure are the same as the bus_dma_segment 1895 * structure. This might be a little dangerous, 1896 * but only if they change the structures, which 1897 * seems unlikely. 1898 */ 1899 KASSERT((sizeof (sguio.uio_iov) == sizeof (csio->data_ptr) && 1900 sizeof (sguio.uio_iovcnt) >= sizeof (csio->sglist_cnt) && 1901 sizeof (sguio.uio_resid) >= sizeof (csio->dxfer_len)), ("Ken's assumption failed")); 1902 sguio.uio_iov = (struct iovec *)csio->data_ptr; 1903 sguio.uio_iovcnt = csio->sglist_cnt; 1904 sguio.uio_resid = csio->dxfer_len; 1905 sguio.uio_segflg = UIO_SYSSPACE; 1906 1907 error = bus_dmamap_load_uio(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, &sguio, eptr2, mp, 0); 1908 1909 if (error != 0 && mp->error == 0) { 1910 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1911 mp->error = error; 1912 } 1913 } else { 1914 /* Just use the segments provided */ 1915 segs = (struct bus_dma_segment *) csio->data_ptr; 1916 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1917 } 1918 } 1919 if (mp->error) { 1920 int retval = CMD_COMPLETE; 1921 if (mp->error == MUSHERR_NOQENTRIES) { 1922 retval = CMD_EAGAIN; 1923 } else if (mp->error == EFBIG) { 1924 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1925 } else if (mp->error == EINVAL) { 1926 XS_SETERR(csio, CAM_REQ_INVALID); 1927 } else { 1928 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1929 } 1930 return (retval); 1931 } 1932 return (CMD_QUEUED); 1933 } 1934 1935 static void 1936 isp_pci_reset0(ispsoftc_t *isp) 1937 { 1938 ISP_DISABLE_INTS(isp); 1939 } 1940 1941 static void 1942 isp_pci_reset1(ispsoftc_t *isp) 1943 { 1944 if (!IS_24XX(isp)) { 1945 /* Make sure the BIOS is disabled */ 1946 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1947 } 1948 /* and enable interrupts */ 1949 ISP_ENABLE_INTS(isp); 1950 } 1951 1952 static void 1953 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 1954 { 1955 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1956 if (msg) 1957 kprintf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1958 else 1959 kprintf("%s:\n", device_get_nameunit(isp->isp_dev)); 1960 if (IS_SCSI(isp)) 1961 kprintf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1962 else 1963 kprintf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1964 kprintf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1965 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1966 kprintf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1967 1968 1969 if (IS_SCSI(isp)) { 1970 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1971 kprintf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1972 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1973 ISP_READ(isp, CDMA_FIFO_STS)); 1974 kprintf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1975 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1976 ISP_READ(isp, DDMA_FIFO_STS)); 1977 kprintf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1978 ISP_READ(isp, SXP_INTERRUPT), 1979 ISP_READ(isp, SXP_GROSS_ERR), 1980 ISP_READ(isp, SXP_PINS_CTRL)); 1981 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1982 } 1983 kprintf(" mbox regs: %x %x %x %x %x\n", 1984 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1985 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1986 ISP_READ(isp, OUTMAILBOX4)); 1987 kprintf(" PCI Status Command/Status=%x\n", 1988 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 1989 } 1990