1 /* $FreeBSD: src/sys/dev/isp/ispreg.h,v 1.31 2010/02/27 05:41:23 mjacob Exp $ */ 2 /*- 3 * Copyright (c) 1997-2009 by Matthew Jacob 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 /* 30 * Machine Independent (well, as best as possible) register 31 * definitions for Qlogic ISP SCSI adapters. 32 */ 33 #ifndef _ISPREG_H 34 #define _ISPREG_H 35 36 /* 37 * Hardware definitions for the Qlogic ISP registers. 38 */ 39 40 /* 41 * This defines types of access to various registers. 42 * 43 * R: Read Only 44 * W: Write Only 45 * RW: Read/Write 46 * 47 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 48 * if RISC processor in ISP is paused. 49 */ 50 51 /* 52 * Offsets for various register blocks. 53 * 54 * Sad but true, different architectures have different offsets. 55 * 56 * Don't be alarmed if none of this makes sense. The original register 57 * layout set some defines in a certain pattern. Everything else has been 58 * grafted on since. For example, the ISP1080 manual will state that DMA 59 * registers start at 0x80 from the base of the register address space. 60 * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080 61 * to start at offset 0x60 because the DMA registers are all defined to 62 * be DMA_BLOCK+0x20 and so on. Clear? 63 */ 64 65 #define BIU_REGS_OFF 0x00 66 67 #define PCI_MBOX_REGS_OFF 0x70 68 #define PCI_MBOX_REGS2100_OFF 0x10 69 #define PCI_MBOX_REGS2300_OFF 0x40 70 #define PCI_MBOX_REGS2400_OFF 0x80 71 #define SBUS_MBOX_REGS_OFF 0x80 72 73 #define PCI_SXP_REGS_OFF 0x80 74 #define SBUS_SXP_REGS_OFF 0x200 75 76 #define PCI_RISC_REGS_OFF 0x80 77 #define SBUS_RISC_REGS_OFF 0x400 78 79 /* Bless me! Chip designers have putzed it again! */ 80 #define ISP1080_DMA_REGS_OFF 0x60 81 #define DMA_REGS_OFF 0x00 /* same as BIU block */ 82 83 #define SBUS_REGSIZE 0x450 84 #define PCI_REGSIZE 0x100 85 86 /* 87 * NB: The *_BLOCK definitions have no specific hardware meaning. 88 * They serve simply to note to the MD layer which block of 89 * registers offsets are being accessed. 90 */ 91 #define _NREG_BLKS 5 92 #define _BLK_REG_SHFT 13 93 #define _BLK_REG_MASK (7 << _BLK_REG_SHFT) 94 #define BIU_BLOCK (0 << _BLK_REG_SHFT) 95 #define MBOX_BLOCK (1 << _BLK_REG_SHFT) 96 #define SXP_BLOCK (2 << _BLK_REG_SHFT) 97 #define RISC_BLOCK (3 << _BLK_REG_SHFT) 98 #define DMA_BLOCK (4 << _BLK_REG_SHFT) 99 100 /* 101 * Bus Interface Block Register Offsets 102 */ 103 104 #define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */ 105 #define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0) 106 #define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */ 107 #define BIU2100_FLASH_DATA (BIU_BLOCK+0x2) 108 #define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */ 109 #define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */ 110 #define BIU2100_CSR (BIU_BLOCK+0x6) 111 #define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */ 112 #define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */ 113 #define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */ 114 #define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */ 115 /* 116 * These are specific to the 2300. 117 */ 118 #define BIU_REQINP (BIU_BLOCK+0x10) /* Request Queue In */ 119 #define BIU_REQOUTP (BIU_BLOCK+0x12) /* Request Queue Out */ 120 #define BIU_RSPINP (BIU_BLOCK+0x14) /* Response Queue In */ 121 #define BIU_RSPOUTP (BIU_BLOCK+0x16) /* Response Queue Out */ 122 123 #define BIU_R2HSTSLO (BIU_BLOCK+0x18) 124 #define BIU_R2HSTSHI (BIU_BLOCK+0x1A) 125 126 #define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */ 127 #define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */ 128 #define BIU_R2HST_ISTAT_MASK 0x3f /* intr information && status */ 129 #define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */ 130 #define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */ 131 #define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */ 132 #define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */ 133 #define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */ 134 #define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */ 135 #define ISPR2HST_RQST_UPDATE 0x14 /* Resquest Queue Update */ 136 #define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */ 137 #define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */ 138 #define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */ 139 140 /* fifo command stuff- mostly for SPI */ 141 #define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */ 142 #define RDMA2100_CONTROL DFIFO_COMMAND 143 #define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */ 144 145 /* 146 * Putzed DMA register layouts. 147 */ 148 #define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */ 149 #define CDMA2100_CONTROL CDMA_CONF 150 #define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */ 151 #define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */ 152 #define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */ 153 #define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */ 154 #define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */ 155 #define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */ 156 #define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */ 157 #define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */ 158 159 #define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */ 160 #define TDMA2100_CONTROL DDMA_CONF 161 #define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */ 162 #define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */ 163 #define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */ 164 #define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */ 165 #define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */ 166 #define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */ 167 #define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */ 168 /* these are for the 1040A cards */ 169 #define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */ 170 #define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */ 171 172 173 /* 174 * Bus Interface Block Register Definitions 175 */ 176 /* BUS CONFIGURATION REGISTER #0 */ 177 #define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 178 /* BUS CONFIGURATION REGISTER #1 */ 179 180 #define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 181 #define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 182 183 #define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 184 #define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 185 #define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 186 #define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 187 #define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 188 #define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 189 #define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 190 #define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 191 #define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 192 #define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 193 #define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 194 195 #define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */ 196 #define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */ 197 #define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ 198 199 /* ISP2100 Bus Control/Status Register */ 200 201 #define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 202 #define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 203 #define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 204 #define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 205 #define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 206 #define BIU2100_NVRAM_OFFSET (1 << 14) 207 #define BIU2100_FLASH_UPPER_64K 0x04 /* RW: Upper 64K Bank Select */ 208 #define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 209 #define BIU2100_SOFT_RESET 0x01 210 /* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 211 212 213 /* BUS CONTROL REGISTER */ 214 #define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 215 #define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 216 #define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 217 #define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 218 #define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 219 #define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 220 221 #define BIU_IMASK (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS) 222 223 #define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 224 #define BIU2100_ICR_ENA_FPM_INT 0x0020 225 #define BIU2100_ICR_ENA_FB_INT 0x0010 226 #define BIU2100_ICR_ENA_RISC_INT 0x0008 227 #define BIU2100_ICR_ENA_CDMA_INT 0x0004 228 #define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 229 #define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 230 #define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 231 232 #define BIU2100_IMASK (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS) 233 234 /* BUS STATUS REGISTER */ 235 #define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 236 #define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 237 #define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 238 #define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 239 #define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 240 241 #define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 242 #define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 243 #define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 244 #define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 245 #define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 246 #define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 247 #define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 248 249 #define INT_PENDING(isp, isr) \ 250 IS_FC(isp)? \ 251 (IS_24XX(isp)? (isr & BIU2400_ISR_RISC_INT) : (isr & BIU2100_ISR_RISC_INT)) :\ 252 (isr & BIU_ISR_RISC_INT) 253 254 #define INT_PENDING_MASK(isp) \ 255 (IS_FC(isp)? (IS_24XX(isp)? BIU2400_ISR_RISC_INT : BIU2100_ISR_RISC_INT) : \ 256 (BIU_ISR_RISC_INT)) 257 258 /* BUS SEMAPHORE REGISTER */ 259 #define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 260 #define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 261 262 /* NVRAM SEMAPHORE REGISTER */ 263 #define BIU_NVRAM_CLOCK 0x0001 264 #define BIU_NVRAM_SELECT 0x0002 265 #define BIU_NVRAM_DATAOUT 0x0004 266 #define BIU_NVRAM_DATAIN 0x0008 267 #define BIU_NVRAM_BUSY 0x0080 /* 2322/24xx only */ 268 #define ISP_NVRAM_READ 6 269 270 /* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 271 #define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 272 #define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 273 #define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 274 #define DMA_DMA_DIRECTION 0x0001 /* 275 * Set DMA direction: 276 * 0 - DMA FIFO to host 277 * 1 - Host to DMA FIFO 278 */ 279 280 /* COMMAND && DATA DMA CONTROL REGISTER */ 281 #define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 282 #define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 283 * Clear FIFO and DMA Channel, 284 * reset DMA registers 285 */ 286 #define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 287 #define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 288 #define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 289 290 /* 291 * Variants of same for 2100 292 */ 293 #define DMA_CNTRL2100_CLEAR_CHAN 0x0004 294 #define DMA_CNTRL2100_RESET_INT 0x0002 295 296 297 298 /* DMA STATUS REGISTER */ 299 #define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 300 #define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 301 #define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 302 #define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 303 #define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 304 #define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 305 306 #define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 307 #define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 308 #define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 309 #define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 310 #define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 311 #define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 312 #define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 313 #define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 314 #define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 315 #define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 316 #define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 317 318 /* DMA Status Register, pipeline status bits */ 319 #define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 320 #define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 321 #define DMA_SBUS_PIPE_STAGE1 0x0040 /* 322 * Pipeline stage 1 Loaded, 323 * stage 2 empty 324 */ 325 #define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 326 #define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 327 #define DMA_PCI_PIPE_STAGE1 0x0001 /* 328 * Pipeline stage 1 Loaded, 329 * stage 2 empty 330 */ 331 #define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 332 333 /* DMA Status Register, channel status bits */ 334 #define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 335 #define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 336 #define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 337 #define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 338 #define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 339 #define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 340 #define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 341 342 343 /* DMA FIFO STATUS REGISTER */ 344 #define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 345 #define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 346 #define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 347 #define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 348 349 /* 350 * 2400 Interface Offsets and Register Definitions 351 * 352 * The 2400 looks quite different in terms of registers from other QLogic cards. 353 * It is getting to be a genuine pain and challenge to keep the same model 354 * for all. 355 */ 356 #define BIU2400_FLASH_ADDR (BIU_BLOCK+0x00) 357 #define BIU2400_FLASH_DATA (BIU_BLOCK+0x04) 358 #define BIU2400_CSR (BIU_BLOCK+0x08) 359 #define BIU2400_ICR (BIU_BLOCK+0x0C) 360 #define BIU2400_ISR (BIU_BLOCK+0x10) 361 362 #define BIU2400_REQINP (BIU_BLOCK+0x1C) /* Request Queue In */ 363 #define BIU2400_REQOUTP (BIU_BLOCK+0x20) /* Request Queue Out */ 364 #define BIU2400_RSPINP (BIU_BLOCK+0x24) /* Response Queue In */ 365 #define BIU2400_RSPOUTP (BIU_BLOCK+0x28) /* Response Queue Out */ 366 367 #define BIU2400_PRI_REQINP (BIU_BLOCK+0x2C) /* Priority Request Q In */ 368 #define BIU2400_PRI_REQOUTP (BIU_BLOCK+0x30) /* Priority Request Q Out */ 369 370 #define BIU2400_ATIO_RSPINP (BIU_BLOCK+0x3C) /* ATIO Queue In */ 371 #define BIU2400_ATIO_RSPOUTP (BIU_BLOCK+0x40) /* ATIO Queue Out */ 372 373 #define BIU2400_R2HSTSLO (BIU_BLOCK+0x44) 374 #define BIU2400_R2HSTSHI (BIU_BLOCK+0x46) 375 376 #define BIU2400_HCCR (BIU_BLOCK+0x48) 377 #define BIU2400_GPIOD (BIU_BLOCK+0x4C) 378 #define BIU2400_GPIOE (BIU_BLOCK+0x50) 379 #define BIU2400_HSEMA (BIU_BLOCK+0x58) 380 381 /* BIU2400_FLASH_ADDR definitions */ 382 #define BIU2400_FLASH_DFLAG (1 << 30) 383 384 /* BIU2400_CSR definitions */ 385 #define BIU2400_NVERR (1 << 18) 386 #define BIU2400_DMA_ACTIVE (1 << 17) /* RO */ 387 #define BIU2400_DMA_STOP (1 << 16) 388 #define BIU2400_FUNCTION (1 << 15) /* RO */ 389 #define BIU2400_PCIX_MODE(x) (((x) >> 8) & 0xf) /* RO */ 390 #define BIU2400_CSR_64BIT (1 << 2) /* RO */ 391 #define BIU2400_FLASH_ENABLE (1 << 1) 392 #define BIU2400_SOFT_RESET (1 << 0) 393 394 /* BIU2400_ICR definitions */ 395 #define BIU2400_ICR_ENA_RISC_INT 0x8 396 #define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT) 397 398 /* BIU2400_ISR definitions */ 399 #define BIU2400_ISR_RISC_INT 0x8 400 401 #define BIU2400_R2HST_INTR BIU_R2HST_INTR 402 #define BIU2400_R2HST_PAUSED BIU_R2HST_PAUSED 403 #define BIU2400_R2HST_ISTAT_MASK 0x1f 404 /* interrupt status meanings */ 405 #define ISP2400R2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */ 406 #define ISP2400R2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */ 407 #define ISP2400R2HST_MBX_OK 0x10 /* mailbox cmd done ok */ 408 #define ISP2400R2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */ 409 #define ISP2400R2HST_ASYNC_EVENT 0x12 /* Async Event */ 410 #define ISP2400R2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */ 411 #define ISP2400R2HST_ATIO_RSPQ_UPDATE 0x1C /* ATIO Response Queue Update */ 412 #define ISP2400R2HST_ATIO_RQST_UPDATE 0x1D /* ATIO Request Queue Update */ 413 414 /* BIU2400_HCCR definitions */ 415 416 #define HCCR_2400_CMD_NOP 0x00000000 417 #define HCCR_2400_CMD_RESET 0x10000000 418 #define HCCR_2400_CMD_CLEAR_RESET 0x20000000 419 #define HCCR_2400_CMD_PAUSE 0x30000000 420 #define HCCR_2400_CMD_RELEASE 0x40000000 421 #define HCCR_2400_CMD_SET_HOST_INT 0x50000000 422 #define HCCR_2400_CMD_CLEAR_HOST_INT 0x60000000 423 #define HCCR_2400_CMD_CLEAR_RISC_INT 0xA0000000 424 425 #define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */ 426 #define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */ 427 #define HCCR_2400_RISC_RESET (1 << 5) /* RO */ 428 429 430 /* 431 * Mailbox Block Register Offsets 432 */ 433 434 #define INMAILBOX0 (MBOX_BLOCK+0x0) 435 #define INMAILBOX1 (MBOX_BLOCK+0x2) 436 #define INMAILBOX2 (MBOX_BLOCK+0x4) 437 #define INMAILBOX3 (MBOX_BLOCK+0x6) 438 #define INMAILBOX4 (MBOX_BLOCK+0x8) 439 #define INMAILBOX5 (MBOX_BLOCK+0xA) 440 #define INMAILBOX6 (MBOX_BLOCK+0xC) 441 #define INMAILBOX7 (MBOX_BLOCK+0xE) 442 443 #define OUTMAILBOX0 (MBOX_BLOCK+0x0) 444 #define OUTMAILBOX1 (MBOX_BLOCK+0x2) 445 #define OUTMAILBOX2 (MBOX_BLOCK+0x4) 446 #define OUTMAILBOX3 (MBOX_BLOCK+0x6) 447 #define OUTMAILBOX4 (MBOX_BLOCK+0x8) 448 #define OUTMAILBOX5 (MBOX_BLOCK+0xA) 449 #define OUTMAILBOX6 (MBOX_BLOCK+0xC) 450 #define OUTMAILBOX7 (MBOX_BLOCK+0xE) 451 452 /* 453 * Strictly speaking, it's 454 * SCSI && 2100 : 8 MBOX registers 455 * 2200: 24 MBOX registers 456 * 2300/2400: 32 MBOX registers 457 */ 458 #define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) 459 #define NMBOX(isp) \ 460 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 461 ((isp)->isp_type & ISP_HA_FC))? 12 : 6) 462 #define NMBOX_BMASK(isp) \ 463 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 464 ((isp)->isp_type & ISP_HA_FC))? 0xfff : 0x3f) 465 466 #define MAX_MAILBOX(isp) ((IS_FC(isp))? 12 : 8) 467 #define MAILBOX_STORAGE 12 468 /* if timeout == 0, then default timeout is picked */ 469 #define MBCMD_DEFAULT_TIMEOUT 100000 /* 100 ms */ 470 typedef struct { 471 uint16_t param[MAILBOX_STORAGE]; 472 uint16_t ibits; 473 uint16_t obits; 474 uint32_t 475 lineno : 16, 476 : 12, 477 logval : 4; 478 uint32_t timeout; 479 const char *func; 480 } mbreg_t; 481 #define MBSINIT(mbxp, code, loglev, timo) \ 482 ISP_MEMZERO((mbxp), sizeof (mbreg_t)); \ 483 (mbxp)->param[0] = code; \ 484 (mbxp)->lineno = __LINE__; \ 485 (mbxp)->func = __func__; \ 486 (mbxp)->logval = loglev; \ 487 (mbxp)->timeout = timo 488 489 490 /* 491 * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00). 492 * NB: The RISC processor must be paused and the appropriate register 493 * bank selected via BIU2100_CSR bits. 494 */ 495 496 #define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96) 497 #define FPM_SOFT_RESET 0x0100 498 499 #define FBM_CMD (BIU_BLOCK + 0xB8) 500 #define FBMCMD_FIFO_RESET_ALL 0xA000 501 502 503 /* 504 * SXP Block Register Offsets 505 */ 506 #define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ 507 #define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */ 508 #define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */ 509 #define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */ 510 #define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */ 511 #define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */ 512 #define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */ 513 #define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */ 514 #define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */ 515 #define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */ 516 #define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */ 517 #define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */ 518 #define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */ 519 #define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */ 520 #define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */ 521 #define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */ 522 #define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */ 523 #define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */ 524 #define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */ 525 #define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */ 526 #define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */ 527 #define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */ 528 #define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */ 529 #define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */ 530 #define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */ 531 #define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */ 532 #define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */ 533 #define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ 534 #define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ 535 #define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ 536 #define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */ 537 #define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ 538 #define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ 539 #define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ 540 #define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */ 541 #define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */ 542 #define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */ 543 #define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */ 544 #define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */ 545 546 /* for 1080/1280/1240 only */ 547 #define SXP_BANK1_SELECT 0x100 548 549 550 /* SXP CONF1 REGISTER */ 551 #define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 552 #define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 553 #define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 554 #define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 555 #define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 556 557 /* SXP CONF2 REGISTER */ 558 #define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 559 #define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 560 #define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 561 #define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 562 #define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 563 #define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 564 565 /* SXP INTERRUPT REGISTER */ 566 #define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 567 #define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 568 #define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 569 #define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 570 #define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 571 #define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 572 #define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 573 #define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 574 #define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 575 #define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 576 577 578 /* SXP GROSS ERROR REGISTER */ 579 #define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 580 #define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 581 #define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 582 #define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 583 #define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 584 #define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 585 #define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 586 587 /* SXP EXCEPTION REGISTER */ 588 #define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 589 #define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 590 #define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 591 #define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 592 #define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 593 #define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 594 #define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 595 #define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 596 #define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 597 #define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 598 599 /* SXP OVERRIDE REGISTER */ 600 #define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 601 #define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 602 #define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 603 #define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 604 #define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 605 #define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 606 #define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 607 #define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 608 #define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 609 #define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 610 #define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 611 #define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 612 #define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 613 614 /* SXP COMMANDS */ 615 #define SXP_RESET_BUS_CMD 0x300b 616 617 /* SXP SCSI ID REGISTER */ 618 #define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 619 #define SXP_SELECT_ID 0x000F /* Select id */ 620 621 /* SXP DEV CONFIG1 REGISTER */ 622 #define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 623 #define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 624 #define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 625 626 627 /* SXP DEV CONFIG2 REGISTER */ 628 #define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 629 #define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 630 #define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 631 #define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 632 #define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 633 634 635 /* SXP PHASE POINTER REGISTER */ 636 #define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 637 #define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 638 #define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 639 #define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 640 641 642 /* SXP FIFO STATUS REGISTER */ 643 #define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 644 #define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 645 #define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 646 #define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 647 648 649 /* SXP CONTROL PINS REGISTER */ 650 #define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 651 #define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 652 #define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 653 #define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 654 #define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 655 #define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 656 #define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 657 #define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 658 #define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 659 #define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 660 #define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 661 #define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 662 663 /* 664 * Set the hold time for the SCSI Bus Reset to be 250 ms 665 */ 666 #define SXP_SCSI_BUS_RESET_HOLD_TIME 250 667 668 /* SXP DIFF PINS REGISTER */ 669 #define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 670 #define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 671 #define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 672 #define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 673 #define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 674 #define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 675 676 /* Ultra2 only */ 677 #define SXP_PINS_LVD_MODE 0x1000 678 #define SXP_PINS_HVD_MODE 0x0800 679 #define SXP_PINS_SE_MODE 0x0400 680 #define SXP_PINS_MODE_MASK (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE) 681 682 /* The above have to be put together with the DIFFM pin to make sense */ 683 #define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 684 #define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 685 #define ISP1080_SE_MODE (SXP_PINS_SE_MODE) 686 #define ISP1080_MODE_MASK (SXP_PINS_MODE_MASK|SXP_PINS_DIFF_MODE) 687 688 /* 689 * RISC and Host Command and Control Block Register Offsets 690 */ 691 692 #define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 693 #define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 694 #define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 695 #define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 696 #define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 697 #define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 698 #define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 699 #define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 700 #define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 701 #define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 702 #define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 703 #define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 704 #define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 705 #define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 706 #define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 707 #define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 708 #define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 709 #define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 710 #define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 711 #define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 712 #define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 713 #define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 714 #define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 715 #define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 716 #define RISC_MTR2100 RISC_BLOCK+0x30 717 718 #define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 719 #define DUAL_BANK 8 720 #define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 721 #define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 722 #define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 723 #define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 724 #define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 725 #define TCR RISC_BLOCK+0x46 /* W : Test Control */ 726 #define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 727 728 729 /* PROCESSOR STATUS REGISTER */ 730 #define RISC_PSR_FORCE_TRUE 0x8000 731 #define RISC_PSR_LOOP_COUNT_DONE 0x4000 732 #define RISC_PSR_RISC_INT 0x2000 733 #define RISC_PSR_TIMER_ROLLOVER 0x1000 734 #define RISC_PSR_ALU_OVERFLOW 0x0800 735 #define RISC_PSR_ALU_MSB 0x0400 736 #define RISC_PSR_ALU_CARRY 0x0200 737 #define RISC_PSR_ALU_ZERO 0x0100 738 739 #define RISC_PSR_PCI_ULTRA 0x0080 740 #define RISC_PSR_SBUS_ULTRA 0x0020 741 742 #define RISC_PSR_DMA_INT 0x0010 743 #define RISC_PSR_SXP_INT 0x0008 744 #define RISC_PSR_HOST_INT 0x0004 745 #define RISC_PSR_INT_PENDING 0x0002 746 #define RISC_PSR_FORCE_FALSE 0x0001 747 748 749 /* Host Command and Control */ 750 #define HCCR_CMD_NOP 0x0000 /* NOP */ 751 #define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 752 #define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 753 #define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 754 #define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 755 #define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /* 756 * Disable RISC pause on FPM 757 * parity error. 758 */ 759 #define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 760 #define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 761 #define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 762 #define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 763 #define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 764 #define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 765 #define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 766 #define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 767 768 769 #define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 770 #define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 771 #define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 772 #define ISP2100_HCCR_PARITY 0x0001 773 774 #define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 775 #define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 776 #define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 777 778 #define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 779 #define HCCR_RESET 0x0040 /* R : reset in progress */ 780 #define HCCR_PAUSE 0x0020 /* R : RISC paused */ 781 782 #define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 783 784 /* 785 * Defines for Interrupts 786 */ 787 #define ISP_INTS_ENABLED(isp) \ 788 ((IS_SCSI(isp))? \ 789 (ISP_READ(isp, BIU_ICR) & BIU_IMASK) : \ 790 (IS_24XX(isp)? (ISP_READ(isp, BIU2400_ICR) & BIU2400_IMASK) : \ 791 (ISP_READ(isp, BIU_ICR) & BIU2100_IMASK))) 792 793 #define ISP_ENABLE_INTS(isp) \ 794 (IS_SCSI(isp) ? \ 795 ISP_WRITE(isp, BIU_ICR, BIU_IMASK) : \ 796 (IS_24XX(isp) ? \ 797 (ISP_WRITE(isp, BIU2400_ICR, BIU2400_IMASK)) : \ 798 (ISP_WRITE(isp, BIU_ICR, BIU2100_IMASK)))) 799 800 #define ISP_DISABLE_INTS(isp) \ 801 IS_24XX(isp)? ISP_WRITE(isp, BIU2400_ICR, 0) : ISP_WRITE(isp, BIU_ICR, 0) 802 803 /* 804 * NVRAM Definitions (PCI cards only) 805 */ 806 807 #define ISPBSMX(c, byte, shift, mask) \ 808 (((c)[(byte)] >> (shift)) & (mask)) 809 /* 810 * Qlogic 1020/1040 NVRAM is an array of 128 bytes. 811 * 812 * Some portion of the front of this is for general host adapter properties 813 * This is followed by an array of per-target parameters, and is tailed off 814 * with a checksum xor byte at offset 127. For non-byte entities data is 815 * stored in Little Endian order. 816 */ 817 818 #define ISP_NVRAM_SIZE 128 819 820 #define ISP_NVRAM_VERSION(c) (c)[4] 821 #define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 822 #define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 823 #define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 824 #define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 825 #define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 826 #define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 827 #define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 828 #define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 829 #define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 830 #define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 831 #define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 832 #define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 833 #define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 834 #define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 835 #define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 836 #define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 837 #define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 838 #define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 839 #define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 840 #define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 841 #define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 842 #define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 843 #define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 844 #define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 845 #define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 846 #define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 847 #define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 848 #define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 849 #define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 850 851 #define ISP_NVRAM_TARGOFF 28 852 #define ISP_NVRAM_TARGSIZE 6 853 #define _IxT(tgt, tidx) \ 854 (ISP_NVRAM_TARGOFF + (ISP_NVRAM_TARGSIZE * (tgt)) + (tidx)) 855 #define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 856 #define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 857 #define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 858 #define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 859 #define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 860 #define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 861 #define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 862 #define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 863 #define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 864 #define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 865 #define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 866 #define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 867 #define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 868 869 /* 870 * Qlogic 1080/1240 NVRAM is an array of 256 bytes. 871 * 872 * Some portion of the front of this is for general host adapter properties 873 * This is followed by an array of per-target parameters, and is tailed off 874 * with a checksum xor byte at offset 256. For non-byte entities data is 875 * stored in Little Endian order. 876 */ 877 878 #define ISP1080_NVRAM_SIZE 256 879 880 #define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) 881 882 /* Offset 5 */ 883 /* 884 uint8_t bios_configuration_mode :2; 885 uint8_t bios_disable :1; 886 uint8_t selectable_scsi_boot_enable :1; 887 uint8_t cd_rom_boot_enable :1; 888 uint8_t disable_loading_risc_code :1; 889 uint8_t enable_64bit_addressing :1; 890 uint8_t unused_7 :1; 891 */ 892 893 /* Offsets 6, 7 */ 894 /* 895 uint8_t boot_lun_number :5; 896 uint8_t scsi_bus_number :1; 897 uint8_t unused_6 :1; 898 uint8_t unused_7 :1; 899 uint8_t boot_target_number :4; 900 uint8_t unused_12 :1; 901 uint8_t unused_13 :1; 902 uint8_t unused_14 :1; 903 uint8_t unused_15 :1; 904 */ 905 906 #define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) 907 908 #define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) 909 #define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) 910 911 #define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) 912 #define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) 913 #define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) 914 915 #define ISP1080_ISP_PARAMETER(c) \ 916 (((c)[18]) | ((c)[19] << 8)) 917 918 #define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01) 919 #define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01) 920 921 #define ISP1080_BUS1_OFF 112 922 923 #define ISP1080_NVRAM_INITIATOR_ID(c, b) \ 924 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) 925 #define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ 926 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] 927 #define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ 928 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] 929 #define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ 930 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] 931 932 #define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ 933 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) 934 #define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ 935 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) 936 #define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ 937 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) 938 #define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ 939 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ 940 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) 941 #define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ 942 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ 943 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) 944 945 #define ISP1080_NVRAM_TARGOFF(b) \ 946 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) 947 #define ISP1080_NVRAM_TARGSIZE 6 948 #define _IxT8(tgt, tidx, b) \ 949 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) 950 951 #define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ 952 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) 953 #define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ 954 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) 955 #define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ 956 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) 957 #define ISP1080_NVRAM_TGT_TQING(c, t, b) \ 958 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) 959 #define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ 960 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) 961 #define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ 962 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) 963 #define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ 964 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) 965 #define ISP1080_NVRAM_TGT_DISC(c, t, b) \ 966 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) 967 #define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 968 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) 969 #define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 970 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) 971 #define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 972 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) 973 #define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 974 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) 975 #define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ 976 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) 977 978 #define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE 979 #define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE 980 #define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD 981 #define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT 982 #define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE 983 #define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE 984 #define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER 985 #define ISP12160_FAST_POST ISP1080_FAST_POST 986 #define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION 987 988 #define ISP12160_NVRAM_INITIATOR_ID \ 989 ISP1080_NVRAM_INITIATOR_ID 990 #define ISP12160_NVRAM_BUS_RESET_DELAY \ 991 ISP1080_NVRAM_BUS_RESET_DELAY 992 #define ISP12160_NVRAM_BUS_RETRY_COUNT \ 993 ISP1080_NVRAM_BUS_RETRY_COUNT 994 #define ISP12160_NVRAM_BUS_RETRY_DELAY \ 995 ISP1080_NVRAM_BUS_RETRY_DELAY 996 #define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \ 997 ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME 998 #define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \ 999 ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION 1000 #define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \ 1001 ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION 1002 #define ISP12160_NVRAM_SELECTION_TIMEOUT \ 1003 ISP1080_NVRAM_SELECTION_TIMEOUT 1004 #define ISP12160_NVRAM_MAX_QUEUE_DEPTH \ 1005 ISP1080_NVRAM_MAX_QUEUE_DEPTH 1006 1007 1008 #define ISP12160_BUS0_OFF 24 1009 #define ISP12160_BUS1_OFF 136 1010 1011 #define ISP12160_NVRAM_TARGOFF(b) \ 1012 (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16) 1013 1014 #define ISP12160_NVRAM_TARGSIZE 6 1015 #define _IxT16(tgt, tidx, b) \ 1016 (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx)) 1017 1018 #define ISP12160_NVRAM_TGT_RENEG(c, t, b) \ 1019 ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01) 1020 #define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \ 1021 ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01) 1022 #define ISP12160_NVRAM_TGT_ARQ(c, t, b) \ 1023 ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01) 1024 #define ISP12160_NVRAM_TGT_TQING(c, t, b) \ 1025 ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01) 1026 #define ISP12160_NVRAM_TGT_SYNC(c, t, b) \ 1027 ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01) 1028 #define ISP12160_NVRAM_TGT_WIDE(c, t, b) \ 1029 ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01) 1030 #define ISP12160_NVRAM_TGT_PARITY(c, t, b) \ 1031 ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01) 1032 #define ISP12160_NVRAM_TGT_DISC(c, t, b) \ 1033 ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01) 1034 1035 #define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 1036 ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff) 1037 #define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 1038 ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff) 1039 1040 #define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 1041 ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f) 1042 #define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 1043 ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01) 1044 1045 #define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \ 1046 ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f) 1047 #define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \ 1048 ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03) 1049 #define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \ 1050 ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01) 1051 1052 /* 1053 * Qlogic 2100 thru 2300 NVRAM is an array of 256 bytes. 1054 * 1055 * Some portion of the front of this is for general RISC engine parameters, 1056 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 1057 * 1058 * This is followed by some general host adapter parameters, and ends with 1059 * a checksum xor byte at offset 255. For non-byte entities data is stored 1060 * in Little Endian order. 1061 */ 1062 #define ISP2100_NVRAM_SIZE 256 1063 /* ISP_NVRAM_VERSION is in same overall place */ 1064 #define ISP2100_NVRAM_RISCVER(c) (c)[6] 1065 #define ISP2100_NVRAM_OPTIONS(c) ((c)[8] | ((c)[9] << 8)) 1066 #define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 1067 #define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 1068 #define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 1069 #define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 1070 #define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 1071 1072 #define ISP2100_NVRAM_PORT_NAME(c) (\ 1073 (((uint64_t)(c)[18]) << 56) | \ 1074 (((uint64_t)(c)[19]) << 48) | \ 1075 (((uint64_t)(c)[20]) << 40) | \ 1076 (((uint64_t)(c)[21]) << 32) | \ 1077 (((uint64_t)(c)[22]) << 24) | \ 1078 (((uint64_t)(c)[23]) << 16) | \ 1079 (((uint64_t)(c)[24]) << 8) | \ 1080 (((uint64_t)(c)[25]) << 0)) 1081 1082 #define ISP2100_NVRAM_HARDLOOPID(c) ((c)[26] | ((c)[27] << 8)) 1083 #define ISP2100_NVRAM_TOV(c) ((c)[29]) 1084 1085 #define ISP2100_NVRAM_NODE_NAME(c) (\ 1086 (((uint64_t)(c)[30]) << 56) | \ 1087 (((uint64_t)(c)[31]) << 48) | \ 1088 (((uint64_t)(c)[32]) << 40) | \ 1089 (((uint64_t)(c)[33]) << 32) | \ 1090 (((uint64_t)(c)[34]) << 24) | \ 1091 (((uint64_t)(c)[35]) << 16) | \ 1092 (((uint64_t)(c)[36]) << 8) | \ 1093 (((uint64_t)(c)[37]) << 0)) 1094 1095 #define ISP2100_XFW_OPTIONS(c) ((c)[38] | ((c)[39] << 8)) 1096 1097 #define ISP2100_RACC_TIMER(c) (c)[40] 1098 #define ISP2100_IDELAY_TIMER(c) (c)[41] 1099 1100 #define ISP2100_ZFW_OPTIONS(c) ((c)[42] | ((c)[43] << 8)) 1101 1102 #define ISP2100_SERIAL_LINK(c) ((c)[68] | ((c)[69] << 8)) 1103 1104 #define ISP2100_NVRAM_HBA_OPTIONS(c) ((c)[70] | ((c)[71] << 8)) 1105 #define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 1106 #define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 1107 #define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 1108 #define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 1109 #define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 1110 #define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 1111 1112 #define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 1113 (((uint64_t)(c)[72]) << 56) | \ 1114 (((uint64_t)(c)[73]) << 48) | \ 1115 (((uint64_t)(c)[74]) << 40) | \ 1116 (((uint64_t)(c)[75]) << 32) | \ 1117 (((uint64_t)(c)[76]) << 24) | \ 1118 (((uint64_t)(c)[77]) << 16) | \ 1119 (((uint64_t)(c)[78]) << 8) | \ 1120 (((uint64_t)(c)[79]) << 0)) 1121 1122 #define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 1123 #define ISP2100_RESET_DELAY(c) (c)[81] 1124 1125 #define ISP2100_HBA_FEATURES(c) ((c)[232] | ((c)[233] << 8)) 1126 1127 /* 1128 * Qlogic 2400 NVRAM is an array of 512 bytes with a 32 bit checksum. 1129 */ 1130 #define ISP2400_NVRAM_PORT0_ADDR 0x80 1131 #define ISP2400_NVRAM_PORT1_ADDR 0x180 1132 #define ISP2400_NVRAM_SIZE 512 1133 1134 #define ISP2400_NVRAM_VERSION(c) ((c)[4] | ((c)[5] << 8)) 1135 #define ISP2400_NVRAM_MAXFRAMELENGTH(c) (((c)[12]) | ((c)[13] << 8)) 1136 #define ISP2400_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 1137 #define ISP2400_NVRAM_EXCHANGE_COUNT(c) (((c)[16]) | ((c)[17] << 8)) 1138 #define ISP2400_NVRAM_HARDLOOPID(c) ((c)[18] | ((c)[19] << 8)) 1139 1140 #define ISP2400_NVRAM_PORT_NAME(c) (\ 1141 (((uint64_t)(c)[20]) << 56) | \ 1142 (((uint64_t)(c)[21]) << 48) | \ 1143 (((uint64_t)(c)[22]) << 40) | \ 1144 (((uint64_t)(c)[23]) << 32) | \ 1145 (((uint64_t)(c)[24]) << 24) | \ 1146 (((uint64_t)(c)[25]) << 16) | \ 1147 (((uint64_t)(c)[26]) << 8) | \ 1148 (((uint64_t)(c)[27]) << 0)) 1149 1150 #define ISP2400_NVRAM_NODE_NAME(c) (\ 1151 (((uint64_t)(c)[28]) << 56) | \ 1152 (((uint64_t)(c)[29]) << 48) | \ 1153 (((uint64_t)(c)[30]) << 40) | \ 1154 (((uint64_t)(c)[31]) << 32) | \ 1155 (((uint64_t)(c)[32]) << 24) | \ 1156 (((uint64_t)(c)[33]) << 16) | \ 1157 (((uint64_t)(c)[34]) << 8) | \ 1158 (((uint64_t)(c)[35]) << 0)) 1159 1160 #define ISP2400_NVRAM_LOGIN_RETRY_CNT(c) ((c)[36] | ((c)[37] << 8)) 1161 #define ISP2400_NVRAM_LINK_DOWN_ON_NOS(c) ((c)[38] | ((c)[39] << 8)) 1162 #define ISP2400_NVRAM_INTERRUPT_DELAY(c) ((c)[40] | ((c)[41] << 8)) 1163 #define ISP2400_NVRAM_LOGIN_TIMEOUT(c) ((c)[42] | ((c)[43] << 8)) 1164 1165 #define ISP2400_NVRAM_FIRMWARE_OPTIONS1(c) \ 1166 ((c)[44] | ((c)[45] << 8) | ((c)[46] << 16) | ((c)[47] << 24)) 1167 #define ISP2400_NVRAM_FIRMWARE_OPTIONS2(c) \ 1168 ((c)[48] | ((c)[49] << 8) | ((c)[50] << 16) | ((c)[51] << 24)) 1169 #define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \ 1170 ((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24)) 1171 1172 /* 1173 * Firmware Crash Dump 1174 * 1175 * QLogic needs specific information format when they look at firmware crashes. 1176 * 1177 * This is incredibly kernel memory consumptive (to say the least), so this 1178 * code is only compiled in when needed. 1179 */ 1180 1181 #define QLA2200_RISC_IMAGE_DUMP_SIZE \ 1182 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \ 1183 (352 * sizeof (uint16_t)) + /* RISC registers */ \ 1184 (61440 * sizeof (uint16_t)) /* RISC SRAM (offset 0x1000..0xffff) */ 1185 #define QLA2300_RISC_IMAGE_DUMP_SIZE \ 1186 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \ 1187 (464 * sizeof (uint16_t)) + /* RISC registers */ \ 1188 (63488 * sizeof (uint16_t)) + /* RISC SRAM (0x0800..0xffff) */ \ 1189 (4096 * sizeof (uint16_t)) + /* RISC SRAM (0x10000..0x10FFF) */ \ 1190 (61440 * sizeof (uint16_t)) /* RISC SRAM (0x11000..0x1FFFF) */ 1191 /* the larger of the two */ 1192 #define ISP_CRASH_IMAGE_SIZE QLA2300_RISC_IMAGE_DUMP_SIZE 1193 #endif /* _ISPREG_H */ 1194