1 /*- 2 * Copyright (c) 1998 - 2006 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.196 2007/04/08 19:18:51 sos Exp $ 27 * $DragonFly: src/sys/dev/disk/nata/ata-chipset.c,v 1.15 2008/07/12 16:38:10 mneumann Exp $ 28 */ 29 30 #include "opt_ata.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/bus_dma.h> 35 #include <sys/bus_resource.h> 36 #include <sys/callout.h> 37 #include <sys/endian.h> 38 #include <sys/libkern.h> 39 #include <sys/lock.h> /* for {get,rel}_mplock() */ 40 #include <sys/malloc.h> 41 #include <sys/nata.h> 42 #include <sys/queue.h> 43 #include <sys/rman.h> 44 #include <sys/spinlock.h> 45 #include <sys/spinlock2.h> 46 #include <sys/systm.h> 47 #include <sys/taskqueue.h> 48 49 #include <machine/bus_dma.h> 50 51 #include <bus/pci/pcireg.h> 52 #include <bus/pci/pcivar.h> 53 54 #include "ata-all.h" 55 #include "ata-pci.h" 56 #include "ata_if.h" 57 58 /* local prototypes */ 59 /* ata-chipset.c */ 60 static int ata_generic_chipinit(device_t dev); 61 static void ata_generic_intr(void *data); 62 static void ata_generic_setmode(device_t dev, int mode); 63 static void ata_sata_phy_check_events(device_t dev); 64 static void ata_sata_phy_event(void *context, int dummy); 65 static int ata_sata_phy_reset(device_t dev); 66 static int ata_sata_connect(struct ata_channel *ch); 67 static void ata_sata_setmode(device_t dev, int mode); 68 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); 69 static int ata_ahci_chipinit(device_t dev); 70 static int ata_ahci_allocate(device_t dev); 71 static int ata_ahci_status(device_t dev); 72 static int ata_ahci_begin_transaction(struct ata_request *request); 73 static int ata_ahci_end_transaction(struct ata_request *request); 74 static void ata_ahci_reset(device_t dev); 75 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 76 static void ata_ahci_dmainit(device_t dev); 77 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request); 78 static int ata_acard_chipinit(device_t dev); 79 static int ata_acard_allocate(device_t dev); 80 static int ata_acard_status(device_t dev); 81 static void ata_acard_850_setmode(device_t dev, int mode); 82 static void ata_acard_86X_setmode(device_t dev, int mode); 83 static int ata_ali_chipinit(device_t dev); 84 static int ata_ali_allocate(device_t dev); 85 static int ata_ali_sata_allocate(device_t dev); 86 static void ata_ali_reset(device_t dev); 87 static void ata_ali_setmode(device_t dev, int mode); 88 static int ata_amd_chipinit(device_t dev); 89 static int ata_ati_chipinit(device_t dev); 90 static void ata_ati_setmode(device_t dev, int mode); 91 static int ata_cyrix_chipinit(device_t dev); 92 static void ata_cyrix_setmode(device_t dev, int mode); 93 static int ata_cypress_chipinit(device_t dev); 94 static void ata_cypress_setmode(device_t dev, int mode); 95 static int ata_highpoint_chipinit(device_t dev); 96 static int ata_highpoint_allocate(device_t dev); 97 static void ata_highpoint_setmode(device_t dev, int mode); 98 static int ata_highpoint_check_80pin(device_t dev, int mode); 99 static int ata_intel_chipinit(device_t dev); 100 static int ata_intel_allocate(device_t dev); 101 static void ata_intel_reset(device_t dev); 102 static void ata_intel_old_setmode(device_t dev, int mode); 103 static void ata_intel_new_setmode(device_t dev, int mode); 104 static void ata_intel_sata_setmode(device_t dev, int mode); 105 static int ata_intel_31244_allocate(device_t dev); 106 static int ata_intel_31244_status(device_t dev); 107 static int ata_intel_31244_command(struct ata_request *request); 108 static void ata_intel_31244_reset(device_t dev); 109 static int ata_ite_chipinit(device_t dev); 110 static void ata_ite_setmode(device_t dev, int mode); 111 static int ata_jmicron_chipinit(device_t dev); 112 static int ata_jmicron_allocate(device_t dev); 113 static void ata_jmicron_reset(device_t dev); 114 static void ata_jmicron_dmainit(device_t dev); 115 static void ata_jmicron_setmode(device_t dev, int mode); 116 static int ata_marvell_pata_chipinit(device_t dev); 117 static int ata_marvell_pata_allocate(device_t dev); 118 static void ata_marvell_pata_setmode(device_t dev, int mode); 119 static int ata_marvell_edma_chipinit(device_t dev); 120 static int ata_marvell_edma_allocate(device_t dev); 121 static int ata_marvell_edma_status(device_t dev); 122 static int ata_marvell_edma_begin_transaction(struct ata_request *request); 123 static int ata_marvell_edma_end_transaction(struct ata_request *request); 124 static void ata_marvell_edma_reset(device_t dev); 125 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 126 static void ata_marvell_edma_dmainit(device_t dev); 127 static int ata_national_chipinit(device_t dev); 128 static void ata_national_setmode(device_t dev, int mode); 129 static int ata_netcell_chipinit(device_t dev); 130 static int ata_netcell_allocate(device_t dev); 131 static int ata_nvidia_chipinit(device_t dev); 132 static int ata_nvidia_allocate(device_t dev); 133 static int ata_nvidia_status(device_t dev); 134 static void ata_nvidia_reset(device_t dev); 135 static int ata_promise_chipinit(device_t dev); 136 static int ata_promise_allocate(device_t dev); 137 static int ata_promise_status(device_t dev); 138 static int ata_promise_dmastart(device_t dev); 139 static int ata_promise_dmastop(device_t dev); 140 static void ata_promise_dmareset(device_t dev); 141 static void ata_promise_dmainit(device_t dev); 142 static void ata_promise_setmode(device_t dev, int mode); 143 static int ata_promise_tx2_allocate(device_t dev); 144 static int ata_promise_tx2_status(device_t dev); 145 static int ata_promise_mio_allocate(device_t dev); 146 static void ata_promise_mio_intr(void *data); 147 static int ata_promise_mio_status(device_t dev); 148 static int ata_promise_mio_command(struct ata_request *request); 149 static void ata_promise_mio_reset(device_t dev); 150 static void ata_promise_mio_dmainit(device_t dev); 151 static void ata_promise_mio_setmode(device_t dev, int mode); 152 static void ata_promise_sx4_intr(void *data); 153 static int ata_promise_sx4_command(struct ata_request *request); 154 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 155 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 156 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 157 static int ata_serverworks_chipinit(device_t dev); 158 static int ata_serverworks_allocate(device_t dev); 159 static void ata_serverworks_setmode(device_t dev, int mode); 160 static int ata_sii_chipinit(device_t dev); 161 static int ata_cmd_allocate(device_t dev); 162 static int ata_cmd_status(device_t dev); 163 static void ata_cmd_setmode(device_t dev, int mode); 164 static int ata_sii_allocate(device_t dev); 165 static int ata_sii_status(device_t dev); 166 static void ata_sii_reset(device_t dev); 167 static void ata_sii_setmode(device_t dev, int mode); 168 static int ata_siiprb_allocate(device_t dev); 169 static int ata_siiprb_status(device_t dev); 170 static int ata_siiprb_begin_transaction(struct ata_request *request); 171 static int ata_siiprb_end_transaction(struct ata_request *request); 172 static void ata_siiprb_reset(device_t dev); 173 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 174 static void ata_siiprb_dmainit(device_t dev); 175 static int ata_sis_chipinit(device_t dev); 176 static int ata_sis_allocate(device_t dev); 177 static void ata_sis_reset(device_t dev); 178 static void ata_sis_setmode(device_t dev, int mode); 179 static int ata_via_chipinit(device_t dev); 180 static int ata_via_allocate(device_t dev); 181 static void ata_via_reset(device_t dev); 182 static void ata_via_setmode(device_t dev, int mode); 183 static void ata_via_southbridge_fixup(device_t dev); 184 static void ata_via_family_setmode(device_t dev, int mode); 185 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index); 186 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot); 187 static int ata_setup_interrupt(device_t dev); 188 static int ata_serialize(device_t dev, int flags); 189 static void ata_print_cable(device_t dev, u_int8_t *who); 190 static int ata_atapi(device_t dev); 191 static int ata_check_80pin(device_t dev, int mode); 192 static int ata_mode2idx(int mode); 193 194 195 /* 196 * generic ATA support functions 197 */ 198 int 199 ata_generic_ident(device_t dev) 200 { 201 struct ata_pci_controller *ctlr = device_get_softc(dev); 202 char buffer[64]; 203 204 ksnprintf(buffer, sizeof(buffer), 205 "%s ATA controller", ata_pcivendor2str(dev)); 206 device_set_desc_copy(dev, buffer); 207 ctlr->chipinit = ata_generic_chipinit; 208 return 0; 209 } 210 211 static int 212 ata_generic_chipinit(device_t dev) 213 { 214 struct ata_pci_controller *ctlr = device_get_softc(dev); 215 216 if (ata_setup_interrupt(dev)) 217 return ENXIO; 218 ctlr->setmode = ata_generic_setmode; 219 return 0; 220 } 221 222 static void 223 ata_generic_intr(void *data) 224 { 225 struct ata_pci_controller *ctlr = data; 226 struct ata_channel *ch; 227 int unit; 228 229 for (unit = 0; unit < ctlr->channels; unit++) { 230 if ((ch = ctlr->interrupt[unit].argument)) 231 ctlr->interrupt[unit].function(ch); 232 } 233 } 234 235 static void 236 ata_generic_setmode(device_t dev, int mode) 237 { 238 struct ata_device *atadev = device_get_softc(dev); 239 240 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 241 mode = ata_check_80pin(dev, mode); 242 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 243 atadev->mode = mode; 244 } 245 246 247 /* 248 * SATA support functions 249 */ 250 static void 251 ata_sata_phy_check_events(device_t dev) 252 { 253 struct ata_channel *ch = device_get_softc(dev); 254 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR); 255 256 /* clear error bits/interrupt */ 257 ATA_IDX_OUTL(ch, ATA_SERROR, error); 258 259 /* do we have any events flagged ? */ 260 if (error) { 261 struct ata_connect_task *tp; 262 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS); 263 264 /* if we have a connection event deal with it */ 265 if ((error & ATA_SE_PHY_CHANGED) && 266 (tp = (struct ata_connect_task *) 267 kmalloc(sizeof(struct ata_connect_task), 268 M_ATA, M_INTWAIT | M_ZERO))) { 269 270 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) || 271 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) { 272 if (bootverbose) 273 device_printf(ch->dev, "CONNECT requested\n"); 274 tp->action = ATA_C_ATTACH; 275 } 276 else { 277 if (bootverbose) 278 device_printf(ch->dev, "DISCONNECT requested\n"); 279 tp->action = ATA_C_DETACH; 280 } 281 tp->dev = ch->dev; 282 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 283 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 284 } 285 } 286 } 287 288 static void 289 ata_sata_phy_event(void *context, int dummy) 290 { 291 struct ata_connect_task *tp = (struct ata_connect_task *)context; 292 struct ata_channel *ch = device_get_softc(tp->dev); 293 device_t *children; 294 int nchildren, i; 295 296 get_mplock(); 297 if (tp->action == ATA_C_ATTACH) { 298 if (bootverbose) 299 device_printf(tp->dev, "CONNECTED\n"); 300 ATA_RESET(tp->dev); 301 ata_identify(tp->dev); 302 } 303 if (tp->action == ATA_C_DETACH) { 304 if (!device_get_children(tp->dev, &children, &nchildren)) { 305 for (i = 0; i < nchildren; i++) 306 if (children[i]) 307 device_delete_child(tp->dev, children[i]); 308 kfree(children, M_TEMP); 309 } 310 spin_lock_wr(&ch->state_mtx); 311 ch->state = ATA_IDLE; 312 spin_unlock_wr(&ch->state_mtx); 313 if (bootverbose) 314 device_printf(tp->dev, "DISCONNECTED\n"); 315 } 316 rel_mplock(); 317 kfree(tp, M_ATA); 318 } 319 320 static int 321 ata_sata_phy_reset(device_t dev) 322 { 323 struct ata_channel *ch = device_get_softc(dev); 324 int loop, retry; 325 326 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 327 return ata_sata_connect(ch); 328 329 for (retry = 0; retry < 10; retry++) { 330 for (loop = 0; loop < 10; loop++) { 331 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET); 332 ata_udelay(100); 333 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & 334 ATA_SC_DET_MASK) == ATA_SC_DET_RESET) 335 break; 336 } 337 ata_udelay(5000); 338 for (loop = 0; loop < 10; loop++) { 339 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE | 340 ATA_SC_IPM_DIS_PARTIAL | 341 ATA_SC_IPM_DIS_SLUMBER); 342 ata_udelay(100); 343 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0) 344 return ata_sata_connect(ch); 345 } 346 } 347 return 0; 348 } 349 350 static int 351 ata_sata_connect(struct ata_channel *ch) 352 { 353 u_int32_t status; 354 int timeout; 355 356 /* wait up to 1 second for "connect well" */ 357 for (timeout = 0; timeout < 100 ; timeout++) { 358 status = ATA_IDX_INL(ch, ATA_SSTATUS); 359 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 || 360 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2) 361 break; 362 ata_udelay(10000); 363 } 364 if (timeout >= 100) { 365 if (bootverbose) 366 device_printf(ch->dev, "SATA connect status=%08x\n", status); 367 return 0; 368 } 369 370 if (bootverbose) 371 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10); 372 373 /* clear SATA error register */ 374 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 375 376 return 1; 377 } 378 379 static void 380 ata_sata_setmode(device_t dev, int mode) 381 { 382 struct ata_device *atadev = device_get_softc(dev); 383 384 /* 385 * if we detect that the device isn't a real SATA device we limit 386 * the transfer mode to UDMA5/ATA100. 387 * this works around the problems some devices has with the 388 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133. 389 */ 390 if (atadev->param.satacapabilities != 0x0000 && 391 atadev->param.satacapabilities != 0xffff) { 392 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 393 394 /* on some drives we need to set the transfer mode */ 395 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 396 ata_limit_mode(dev, mode, ATA_UDMA6)); 397 398 /* query SATA STATUS for the speed */ 399 if (ch->r_io[ATA_SSTATUS].res && 400 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) == 401 ATA_SS_CONWELL_GEN2)) 402 atadev->mode = ATA_SA300; 403 else 404 atadev->mode = ATA_SA150; 405 } 406 else { 407 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 408 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 409 atadev->mode = mode; 410 } 411 } 412 413 static int 414 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis) 415 { 416 struct ata_device *atadev = device_get_softc(request->dev); 417 418 if (request->flags & ATA_R_ATAPI) { 419 fis[0] = 0x27; /* host to device */ 420 fis[1] = 0x80; /* command FIS (note PM goes here) */ 421 fis[2] = ATA_PACKET_CMD; 422 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) 423 fis[3] = ATA_F_DMA; 424 else { 425 fis[5] = request->transfersize; 426 fis[6] = request->transfersize >> 8; 427 } 428 fis[7] = ATA_D_LBA | atadev->unit; 429 fis[15] = ATA_A_4BIT; 430 return 20; 431 } 432 else { 433 ata_modify_if_48bit(request); 434 fis[0] = 0x27; /* host to device */ 435 fis[1] = 0x80; /* command FIS (note PM goes here) */ 436 fis[2] = request->u.ata.command; 437 fis[3] = request->u.ata.feature; 438 fis[4] = request->u.ata.lba; 439 fis[5] = request->u.ata.lba >> 8; 440 fis[6] = request->u.ata.lba >> 16; 441 fis[7] = ATA_D_LBA | atadev->unit; 442 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 443 fis[7] |= (request->u.ata.lba >> 24 & 0x0f); 444 fis[8] = request->u.ata.lba >> 24; 445 fis[9] = request->u.ata.lba >> 32; 446 fis[10] = request->u.ata.lba >> 40; 447 fis[11] = request->u.ata.feature >> 8; 448 fis[12] = request->u.ata.count; 449 fis[13] = request->u.ata.count >> 8; 450 fis[15] = ATA_A_4BIT; 451 return 20; 452 } 453 return 0; 454 } 455 456 /* 457 * AHCI v1.x compliant SATA chipset support functions 458 */ 459 int 460 ata_ahci_ident(device_t dev) 461 { 462 struct ata_pci_controller *ctlr = device_get_softc(dev); 463 static struct ata_chip_id id = {0, 0, 0, 0x00, ATA_SA300, "AHCI"}; 464 char buffer[64]; 465 466 if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0) 467 return ENXIO; 468 469 if (bootverbose) 470 ksnprintf(buffer, sizeof(buffer), "%s (ID=%08x) AHCI controller", 471 ata_pcivendor2str(dev), pci_get_devid(dev)); 472 else 473 ksnprintf(buffer, sizeof(buffer), "%s AHCI controller", 474 ata_pcivendor2str(dev)); 475 device_set_desc_copy(dev, buffer); 476 ctlr->chip = &id; 477 ctlr->chipinit = ata_ahci_chipinit; 478 return 0; 479 } 480 481 482 /* 483 * AHCI v1.x compliant SATA chipset support functions 484 */ 485 int 486 ata_ahci_chipinit(device_t dev) 487 { 488 struct ata_pci_controller *ctlr = device_get_softc(dev); 489 u_int32_t version; 490 int unit; 491 492 /* if we have a memory BAR(5) we are likely on an AHCI part */ 493 ctlr->r_type2 = SYS_RES_MEMORY; 494 ctlr->r_rid2 = PCIR_BAR(5); 495 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 496 &ctlr->r_rid2, RF_ACTIVE))) 497 return ENXIO; 498 499 /* setup interrupt delivery if not done allready by a vendor driver */ 500 if (!ctlr->r_irq) { 501 if (ata_setup_interrupt(dev)) 502 return ENXIO; 503 } 504 else 505 device_printf(dev, "AHCI called from vendor specific driver\n"); 506 507 /* enable AHCI mode */ 508 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 509 510 /* reset AHCI controller */ 511 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR); 512 DELAY(1000000); 513 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) { 514 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 515 device_printf(dev, "AHCI controller reset failure\n"); 516 return ENXIO; 517 } 518 519 /* reenable AHCI mode */ 520 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 521 522 /* get the number of HW channels */ 523 ctlr->channels = 524 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)), 525 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 526 527 /* disable interrupt sources and clear interrupts */ 528 for (unit = 0; unit < ctlr->channels; unit++) { 529 int offset = unit << 7; 530 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0); 531 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, -1); 532 } 533 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS)); 534 535 /* enable AHCI interrupts */ 536 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 537 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE); 538 539 ctlr->reset = ata_ahci_reset; 540 ctlr->dmainit = ata_ahci_dmainit; 541 ctlr->allocate = ata_ahci_allocate; 542 ctlr->setmode = ata_sata_setmode; 543 544 /* enable PCI interrupt */ 545 pci_write_config(dev, PCIR_COMMAND, 546 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 547 548 /* announce we support the HW */ 549 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS); 550 device_printf(dev, 551 "AHCI Version %x%x.%x%x controller with %d ports detected\n", 552 (version >> 24) & 0xff, (version >> 16) & 0xff, 553 (version >> 8) & 0xff, version & 0xff, 554 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 555 return 0; 556 } 557 558 static int 559 ata_ahci_allocate(device_t dev) 560 { 561 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 562 struct ata_channel *ch = device_get_softc(dev); 563 u_int64_t work; 564 int offset = ch->unit << 7; 565 566 /* set the SATA resources */ 567 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 568 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset; 569 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 570 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset; 571 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 572 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset; 573 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 574 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset; 575 576 ch->hw.status = ata_ahci_status; 577 ch->hw.begin_transaction = ata_ahci_begin_transaction; 578 ch->hw.end_transaction = ata_ahci_end_transaction; 579 ch->hw.command = NULL; /* not used here */ 580 581 /* setup work areas */ 582 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET; 583 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff); 584 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32); 585 586 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET; 587 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff); 588 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32); 589 590 /* enable wanted port interrupts */ 591 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 592 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF | 593 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF | 594 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP | 595 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS | 596 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR)); 597 598 /* start operations on this channel */ 599 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 600 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 601 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 602 return 0; 603 } 604 605 static int 606 ata_ahci_status(device_t dev) 607 { 608 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 609 struct ata_channel *ch = device_get_softc(dev); 610 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS); 611 int offset = ch->unit << 7; 612 int tag = 0; 613 614 if (action & (1 << ch->unit)) { 615 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset); 616 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset); 617 618 /* clear interrupt(s) */ 619 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit)); 620 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus); 621 622 /* do we have any PHY events ? */ 623 /* XXX SOS check istatus phy bits */ 624 ata_sata_phy_check_events(dev); 625 626 /* do we have a potentially hanging engine to take care of? */ 627 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) { 628 629 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 630 int timeout = 0; 631 632 /* kill off all activity on this channel */ 633 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 634 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 635 636 /* XXX SOS this is not entirely wrong */ 637 do { 638 DELAY(1000); 639 if (timeout++ > 500) { 640 device_printf(dev, "stopping AHCI engine failed\n"); 641 break; 642 } 643 } while (ATA_INL(ctlr->r_res2, 644 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 645 646 /* start operations on this channel */ 647 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 648 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 649 650 return 1; 651 } 652 else 653 return (!(cstatus & (1 << tag))); 654 } 655 return 0; 656 } 657 658 /* must be called with ATA channel locked and state_mtx held */ 659 static int 660 ata_ahci_begin_transaction(struct ata_request *request) 661 { 662 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 663 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 664 struct ata_ahci_cmd_tab *ctp; 665 struct ata_ahci_cmd_list *clp; 666 int offset = ch->unit << 7; 667 int tag = 0, entries = 0; 668 int fis_size; 669 670 /* get a piece of the workspace for this request */ 671 ctp = (struct ata_ahci_cmd_tab *) 672 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag)); 673 674 /* setup the FIS for this request */ 675 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) { 676 device_printf(request->dev, "setting up SATA FIS failed\n"); 677 request->result = EIO; 678 return ATA_OP_FINISHED; 679 } 680 681 /* if request moves data setup and load SG list */ 682 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 683 if (ch->dma->load(ch->dev, request->data, request->bytecount, 684 request->flags & ATA_R_READ, 685 ctp->prd_tab, &entries)) { 686 device_printf(request->dev, "setting up DMA failed\n"); 687 request->result = EIO; 688 return ATA_OP_FINISHED; 689 } 690 } 691 692 /* setup the command list entry */ 693 clp = (struct ata_ahci_cmd_list *) 694 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 695 696 clp->prd_length = entries; 697 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) | 698 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) | 699 (fis_size / sizeof(u_int32_t)); 700 clp->bytecount = 0; 701 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET + 702 (ATA_AHCI_CT_SIZE * tag)); 703 704 /* clear eventual ACTIVE bit */ 705 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag)); 706 707 /* set command type bit */ 708 if (request->flags & ATA_R_ATAPI) 709 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 710 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) | 711 ATA_AHCI_P_CMD_ATAPI); 712 else 713 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 714 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & 715 ~ATA_AHCI_P_CMD_ATAPI); 716 717 /* issue command to controller */ 718 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag)); 719 720 if (!(request->flags & ATA_R_ATAPI)) { 721 /* device reset doesn't interrupt */ 722 if (request->u.ata.command == ATA_DEVICE_RESET) { 723 u_int32_t tf_data; 724 int timeout = 1000000; 725 726 do { 727 DELAY(10); 728 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7)); 729 } while ((tf_data & ATA_S_BUSY) && timeout--); 730 if (bootverbose) 731 device_printf(ch->dev, "device_reset timeout=%dus\n", 732 (1000000-timeout)*10); 733 request->status = tf_data; 734 if (request->status & ATA_S_ERROR) 735 request->error = tf_data >> 8; 736 return ATA_OP_FINISHED; 737 } 738 } 739 740 /* start the timeout */ 741 callout_reset(&request->callout, request->timeout * hz, 742 (timeout_t*)ata_timeout, request); 743 return ATA_OP_CONTINUES; 744 } 745 746 /* must be called with ATA channel locked and state_mtx held */ 747 static int 748 ata_ahci_end_transaction(struct ata_request *request) 749 { 750 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 751 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 752 struct ata_ahci_cmd_list *clp; 753 u_int32_t tf_data; 754 int offset = ch->unit << 7; 755 int tag = 0; 756 757 /* kill the timeout */ 758 callout_stop(&request->callout); 759 760 /* get status */ 761 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset); 762 request->status = tf_data; 763 764 /* if error status get details */ 765 if (request->status & ATA_S_ERROR) 766 request->error = tf_data >> 8; 767 768 /* record how much data we actually moved */ 769 clp = (struct ata_ahci_cmd_list *) 770 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 771 request->donecount = clp->bytecount; 772 773 /* release SG list etc */ 774 ch->dma->unload(ch->dev); 775 776 return ATA_OP_FINISHED; 777 } 778 779 static void 780 ata_ahci_reset(device_t dev) 781 { 782 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 783 struct ata_channel *ch = device_get_softc(dev); 784 u_int32_t cmd, signature; 785 int offset = ch->unit << 7; 786 int timeout; 787 788 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) { 789 device_printf(dev, "port not implemented\n"); 790 return; 791 } 792 ch->devices = 0; 793 794 /* kill off all activity on this channel */ 795 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 796 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 797 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 798 799 /* XXX SOS this is not entirely wrong */ 800 timeout = 0; 801 do { 802 DELAY(1000); 803 if (timeout++ > 500) { 804 device_printf(dev, "stopping AHCI engine failed\n"); 805 break; 806 } 807 } 808 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 809 810 /* issue Command List Override if supported */ 811 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) { 812 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 813 cmd |= ATA_AHCI_P_CMD_CLO; 814 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd); 815 timeout = 0; 816 do { 817 DELAY(1000); 818 if (timeout++ > 500) { 819 device_printf(dev, "executing CLO failed\n"); 820 break; 821 } 822 } 823 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO); 824 } 825 826 /* reset PHY and decide what is present */ 827 if (ata_sata_phy_reset(dev)) { 828 829 /* clear any interrupts pending on this channel */ 830 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, 831 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset)); 832 833 /* clear SATA error register */ 834 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 835 836 /* start operations on this channel */ 837 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 838 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 839 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 840 841 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset); 842 switch (signature) { 843 case 0x00000101: 844 ch->devices = ATA_ATA_MASTER; 845 break; 846 case 0x96690101: 847 ch->devices = ATA_PORTMULTIPLIER; 848 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 849 ch->devices = 0; 850 break; 851 case 0xeb140101: 852 ch->devices = ATA_ATAPI_MASTER; 853 break; 854 default: /* SOS XXX */ 855 if (bootverbose) 856 device_printf(ch->dev, "No signature, assuming disk device\n"); 857 ch->devices = ATA_ATA_MASTER; 858 } 859 } 860 if (bootverbose) 861 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices, 862 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 863 } 864 865 static void 866 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 867 { 868 struct ata_dmasetprd_args *args = xsc; 869 struct ata_ahci_dma_prd *prd = args->dmatab; 870 int i; 871 872 if (!(args->error = error)) { 873 for (i = 0; i < nsegs; i++) { 874 prd[i].dba = htole64(segs[i].ds_addr); 875 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK); 876 } 877 } 878 args->nsegs = nsegs; 879 } 880 881 static void 882 ata_ahci_dmainit(device_t dev) 883 { 884 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 885 struct ata_channel *ch = device_get_softc(dev); 886 887 ata_dmainit(dev); 888 if (ch->dma) { 889 /* note start and stop are not used here */ 890 ch->dma->setprd = ata_ahci_dmasetprd; 891 ch->dma->max_iosize = 8192 * DEV_BSIZE; 892 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT) 893 ch->dma->max_address = BUS_SPACE_MAXADDR; 894 } 895 } 896 897 static int 898 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request) 899 { 900 bzero(ctp->cfis, 64); 901 if (request->flags & ATA_R_ATAPI) { 902 bzero(ctp->acmd, 32); 903 bcopy(request->u.atapi.ccb, ctp->acmd, 16); 904 } 905 return ata_request2fis_h2d(request, &ctp->cfis[0]); 906 } 907 908 /* 909 * Acard chipset support functions 910 */ 911 int 912 ata_acard_ident(device_t dev) 913 { 914 struct ata_pci_controller *ctlr = device_get_softc(dev); 915 struct ata_chip_id *idx; 916 static struct ata_chip_id ids[] = 917 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" }, 918 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" }, 919 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" }, 920 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" }, 921 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" }, 922 { 0, 0, 0, 0, 0, 0}}; 923 char buffer[64]; 924 925 if (!(idx = ata_match_chip(dev, ids))) 926 return ENXIO; 927 928 ksprintf(buffer, "Acard %s %s controller", 929 idx->text, ata_mode2str(idx->max_dma)); 930 device_set_desc_copy(dev, buffer); 931 ctlr->chip = idx; 932 ctlr->chipinit = ata_acard_chipinit; 933 return 0; 934 } 935 936 static int 937 ata_acard_chipinit(device_t dev) 938 { 939 struct ata_pci_controller *ctlr = device_get_softc(dev); 940 941 if (ata_setup_interrupt(dev)) 942 return ENXIO; 943 944 ctlr->allocate = ata_acard_allocate; 945 if (ctlr->chip->cfg1 == ATPOLD) { 946 ctlr->setmode = ata_acard_850_setmode; 947 ctlr->locking = ata_serialize; 948 } 949 else 950 ctlr->setmode = ata_acard_86X_setmode; 951 return 0; 952 } 953 954 static int 955 ata_acard_allocate(device_t dev) 956 { 957 struct ata_channel *ch = device_get_softc(dev); 958 959 /* setup the usual register normal pci style */ 960 if (ata_pci_allocate(dev)) 961 return ENXIO; 962 963 ch->hw.status = ata_acard_status; 964 return 0; 965 } 966 967 static int 968 ata_acard_status(device_t dev) 969 { 970 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 971 struct ata_channel *ch = device_get_softc(dev); 972 973 if (ctlr->chip->cfg1 == ATPOLD && 974 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit) 975 return 0; 976 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) { 977 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 978 979 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != 980 ATA_BMSTAT_INTERRUPT) 981 return 0; 982 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR); 983 DELAY(1); 984 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 985 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 986 DELAY(1); 987 } 988 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 989 DELAY(100); 990 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 991 return 0; 992 } 993 return 1; 994 } 995 996 static void 997 ata_acard_850_setmode(device_t dev, int mode) 998 { 999 device_t gparent = GRANDPARENT(dev); 1000 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1001 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1002 struct ata_device *atadev = device_get_softc(dev); 1003 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1004 int error; 1005 1006 mode = ata_limit_mode(dev, mode, 1007 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 1008 1009 /* XXX SOS missing WDMA0+1 + PIO modes */ 1010 if (mode >= ATA_WDMA2) { 1011 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1012 if (bootverbose) 1013 device_printf(dev, "%ssetting %s on %s chip\n", 1014 (error) ? "FAILURE " : "", 1015 ata_mode2str(mode), ctlr->chip->text); 1016 if (!error) { 1017 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1); 1018 1019 reg54 &= ~(0x03 << (devno << 1)); 1020 if (mode >= ATA_UDMA0) 1021 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1)); 1022 pci_write_config(gparent, 0x54, reg54, 1); 1023 pci_write_config(gparent, 0x4a, 0xa6, 1); 1024 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2); 1025 atadev->mode = mode; 1026 return; 1027 } 1028 } 1029 /* we could set PIO mode timings, but we assume the BIOS did that */ 1030 } 1031 1032 static void 1033 ata_acard_86X_setmode(device_t dev, int mode) 1034 { 1035 device_t gparent = GRANDPARENT(dev); 1036 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1037 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1038 struct ata_device *atadev = device_get_softc(dev); 1039 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1040 int error; 1041 1042 1043 mode = ata_limit_mode(dev, mode, 1044 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 1045 1046 mode = ata_check_80pin(dev, mode); 1047 1048 /* XXX SOS missing WDMA0+1 + PIO modes */ 1049 if (mode >= ATA_WDMA2) { 1050 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1051 if (bootverbose) 1052 device_printf(dev, "%ssetting %s on %s chip\n", 1053 (error) ? "FAILURE " : "", 1054 ata_mode2str(mode), ctlr->chip->text); 1055 if (!error) { 1056 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2); 1057 1058 reg44 &= ~(0x000f << (devno << 2)); 1059 if (mode >= ATA_UDMA0) 1060 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2)); 1061 pci_write_config(gparent, 0x44, reg44, 2); 1062 pci_write_config(gparent, 0x4a, 0xa6, 1); 1063 pci_write_config(gparent, 0x40 + devno, 0x31, 1); 1064 atadev->mode = mode; 1065 return; 1066 } 1067 } 1068 /* we could set PIO mode timings, but we assume the BIOS did that */ 1069 } 1070 1071 1072 /* 1073 * Acer Labs Inc (ALI) chipset support functions 1074 */ 1075 int 1076 ata_ali_ident(device_t dev) 1077 { 1078 struct ata_pci_controller *ctlr = device_get_softc(dev); 1079 struct ata_chip_id *idx; 1080 static struct ata_chip_id ids[] = 1081 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" }, 1082 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" }, 1083 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" }, 1084 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" }, 1085 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" }, 1086 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" }, 1087 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" }, 1088 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" }, 1089 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" }, 1090 { 0, 0, 0, 0, 0, 0}}; 1091 char buffer[64]; 1092 1093 if (!(idx = ata_match_chip(dev, ids))) 1094 return ENXIO; 1095 1096 ksprintf(buffer, "AcerLabs %s %s controller", 1097 idx->text, ata_mode2str(idx->max_dma)); 1098 device_set_desc_copy(dev, buffer); 1099 ctlr->chip = idx; 1100 ctlr->chipinit = ata_ali_chipinit; 1101 return 0; 1102 } 1103 1104 static int 1105 ata_ali_chipinit(device_t dev) 1106 { 1107 struct ata_pci_controller *ctlr = device_get_softc(dev); 1108 1109 if (ata_setup_interrupt(dev)) 1110 return ENXIO; 1111 1112 switch (ctlr->chip->cfg2) { 1113 case ALISATA: 1114 ctlr->channels = ctlr->chip->cfg1; 1115 ctlr->allocate = ata_ali_sata_allocate; 1116 ctlr->setmode = ata_sata_setmode; 1117 1118 /* AHCI mode is correctly supported only on the ALi 5288. */ 1119 if ((ctlr->chip->chipid == ATA_ALI_5288) && 1120 (ata_ahci_chipinit(dev) != ENXIO)) 1121 return 0; 1122 1123 /* enable PCI interrupt */ 1124 pci_write_config(dev, PCIR_COMMAND, 1125 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1126 break; 1127 1128 case ALINEW: 1129 /* use device interrupt as byte count end */ 1130 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1); 1131 1132 /* enable cable detection and UDMA support on newer chips */ 1133 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1); 1134 1135 /* enable ATAPI UDMA mode */ 1136 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1); 1137 1138 /* only chips with revision > 0xc4 can do 48bit DMA */ 1139 if (ctlr->chip->chiprev <= 0xc4) 1140 device_printf(dev, 1141 "using PIO transfers above 137GB as workaround for " 1142 "48bit DMA access bug, expect reduced performance\n"); 1143 ctlr->allocate = ata_ali_allocate; 1144 ctlr->reset = ata_ali_reset; 1145 ctlr->setmode = ata_ali_setmode; 1146 break; 1147 1148 case ALIOLD: 1149 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */ 1150 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1); 1151 ctlr->setmode = ata_ali_setmode; 1152 break; 1153 } 1154 return 0; 1155 } 1156 1157 static int 1158 ata_ali_allocate(device_t dev) 1159 { 1160 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1161 struct ata_channel *ch = device_get_softc(dev); 1162 1163 /* setup the usual register normal pci style */ 1164 if (ata_pci_allocate(dev)) 1165 return ENXIO; 1166 1167 /* older chips can't do 48bit DMA transfers */ 1168 if (ctlr->chip->chiprev <= 0xc4) 1169 ch->flags |= ATA_NO_48BIT_DMA; 1170 1171 return 0; 1172 } 1173 1174 static int 1175 ata_ali_sata_allocate(device_t dev) 1176 { 1177 device_t parent = device_get_parent(dev); 1178 struct ata_pci_controller *ctlr = device_get_softc(parent); 1179 struct ata_channel *ch = device_get_softc(dev); 1180 struct resource *io = NULL, *ctlio = NULL; 1181 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 1182 int i, rid; 1183 1184 rid = PCIR_BAR(0) + (unit01 ? 8 : 0); 1185 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1186 if (!io) 1187 return ENXIO; 1188 1189 rid = PCIR_BAR(1) + (unit01 ? 8 : 0); 1190 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1191 if (!ctlio) { 1192 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io); 1193 return ENXIO; 1194 } 1195 1196 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 1197 ch->r_io[i].res = io; 1198 ch->r_io[i].offset = i + (unit10 ? 8 : 0); 1199 } 1200 ch->r_io[ATA_CONTROL].res = ctlio; 1201 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0); 1202 ch->r_io[ATA_IDX_ADDR].res = io; 1203 ata_default_registers(dev); 1204 if (ctlr->r_res1) { 1205 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 1206 ch->r_io[i].res = ctlr->r_res1; 1207 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 1208 } 1209 } 1210 ch->flags |= ATA_NO_SLAVE; 1211 1212 /* XXX SOS PHY handling awkward in ALI chip not supported yet */ 1213 ata_pci_hw(dev); 1214 return 0; 1215 } 1216 1217 static void 1218 ata_ali_reset(device_t dev) 1219 { 1220 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1221 struct ata_channel *ch = device_get_softc(dev); 1222 device_t *children; 1223 int nchildren, i; 1224 1225 ata_generic_reset(dev); 1226 1227 /* 1228 * workaround for datacorruption bug found on at least SUN Blade-100 1229 * find the ISA function on the southbridge and disable then enable 1230 * the ATA channel tristate buffer 1231 */ 1232 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) { 1233 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) { 1234 for (i = 0; i < nchildren; i++) { 1235 if (pci_get_devid(children[i]) == ATA_ALI_1533) { 1236 pci_write_config(children[i], 0x58, 1237 pci_read_config(children[i], 0x58, 1) & 1238 ~(0x04 << ch->unit), 1); 1239 pci_write_config(children[i], 0x58, 1240 pci_read_config(children[i], 0x58, 1) | 1241 (0x04 << ch->unit), 1); 1242 break; 1243 } 1244 } 1245 kfree(children, M_TEMP); 1246 } 1247 } 1248 } 1249 1250 static void 1251 ata_ali_setmode(device_t dev, int mode) 1252 { 1253 device_t gparent = GRANDPARENT(dev); 1254 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1255 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1256 struct ata_device *atadev = device_get_softc(dev); 1257 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1258 int error; 1259 1260 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1261 1262 if (ctlr->chip->cfg2 & ALINEW) { 1263 if (mode > ATA_UDMA2 && 1264 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) { 1265 ata_print_cable(dev, "controller"); 1266 mode = ATA_UDMA2; 1267 } 1268 } 1269 else 1270 mode = ata_check_80pin(dev, mode); 1271 1272 if (ctlr->chip->cfg2 & ALIOLD) { 1273 /* doesn't support ATAPI DMA on write */ 1274 ch->flags |= ATA_ATAPI_DMA_RO; 1275 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) { 1276 /* doesn't support ATAPI DMA on two ATAPI devices */ 1277 device_printf(dev, "two atapi devices on this channel, no DMA\n"); 1278 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1279 } 1280 } 1281 1282 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1283 1284 if (bootverbose) 1285 device_printf(dev, "%ssetting %s on %s chip\n", 1286 (error) ? "FAILURE " : "", 1287 ata_mode2str(mode), ctlr->chip->text); 1288 if (!error) { 1289 if (mode >= ATA_UDMA0) { 1290 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d}; 1291 u_int32_t word54 = pci_read_config(gparent, 0x54, 4); 1292 1293 word54 &= ~(0x000f000f << (devno << 2)); 1294 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2)); 1295 pci_write_config(gparent, 0x54, word54, 4); 1296 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1297 0x00310001, 4); 1298 } 1299 else { 1300 u_int32_t piotimings[] = 1301 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001, 1302 0x00310001, 0x00440001, 0x00330001, 0x00310001}; 1303 1304 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) & 1305 ~(0x0008000f << (devno << 2)), 4); 1306 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1307 piotimings[ata_mode2idx(mode)], 4); 1308 } 1309 atadev->mode = mode; 1310 } 1311 } 1312 1313 1314 /* 1315 * American Micro Devices (AMD) chipset support functions 1316 */ 1317 int 1318 ata_amd_ident(device_t dev) 1319 { 1320 struct ata_pci_controller *ctlr = device_get_softc(dev); 1321 struct ata_chip_id *idx; 1322 static struct ata_chip_id ids[] = 1323 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" }, 1324 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" }, 1325 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" }, 1326 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" }, 1327 { 0, 0, 0, 0, 0, 0}}; 1328 char buffer[64]; 1329 1330 if (!(idx = ata_match_chip(dev, ids))) 1331 return ENXIO; 1332 1333 ksprintf(buffer, "AMD %s %s controller", 1334 idx->text, ata_mode2str(idx->max_dma)); 1335 device_set_desc_copy(dev, buffer); 1336 ctlr->chip = idx; 1337 ctlr->chipinit = ata_amd_chipinit; 1338 return 0; 1339 } 1340 1341 static int 1342 ata_amd_chipinit(device_t dev) 1343 { 1344 struct ata_pci_controller *ctlr = device_get_softc(dev); 1345 1346 if (ata_setup_interrupt(dev)) 1347 return ENXIO; 1348 1349 /* disable/set prefetch, postwrite */ 1350 if (ctlr->chip->cfg2 & AMDBUG) 1351 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1); 1352 else 1353 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); 1354 1355 ctlr->setmode = ata_via_family_setmode; 1356 return 0; 1357 } 1358 1359 1360 /* 1361 * ATI chipset support functions 1362 */ 1363 int 1364 ata_ati_ident(device_t dev) 1365 { 1366 struct ata_pci_controller *ctlr = device_get_softc(dev); 1367 struct ata_chip_id *idx; 1368 static struct ata_chip_id ids[] = 1369 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" }, 1370 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" }, 1371 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" }, 1372 { ATA_ATI_SB600, 0x00, 0, 0, ATA_UDMA6, "SB600" }, 1373 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" }, 1374 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1375 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1376 { ATA_ATI_SB600_S1, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1377 { ATA_ATI_SB600_S2, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1378 { 0, 0, 0, 0, 0, 0}}; 1379 char buffer[64]; 1380 1381 if (!(idx = ata_match_chip(dev, ids))) 1382 return ENXIO; 1383 1384 ksprintf(buffer, "ATI %s %s controller", 1385 idx->text, ata_mode2str(idx->max_dma)); 1386 device_set_desc_copy(dev, buffer); 1387 ctlr->chip = idx; 1388 1389 /* 1390 * The ATI SATA controllers are actually a SiI 3112 controller, except 1391 * for the SB600. 1392 */ 1393 if (ctlr->chip->cfg1 & SIIMEMIO) 1394 ctlr->chipinit = ata_sii_chipinit; 1395 else 1396 ctlr->chipinit = ata_ati_chipinit; 1397 return 0; 1398 } 1399 1400 static int 1401 ata_ati_chipinit(device_t dev) 1402 { 1403 struct ata_pci_controller *ctlr = device_get_softc(dev); 1404 1405 if (ata_setup_interrupt(dev)) 1406 return ENXIO; 1407 1408 /* The SB600 needs special treatment. */ 1409 if (ctlr->chip->cfg1 & ATIAHCI) { 1410 /* Check if the chip is configured as an AHCI part. */ 1411 if ((pci_get_subclass(dev) == PCIS_STORAGE_SATA) && 1412 (pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI_1_0)) { 1413 if (ata_ahci_chipinit(dev) != ENXIO) 1414 return 0; 1415 } 1416 } 1417 1418 ctlr->setmode = ata_ati_setmode; 1419 return 0; 1420 } 1421 1422 static void 1423 ata_ati_setmode(device_t dev, int mode) 1424 { 1425 device_t gparent = GRANDPARENT(dev); 1426 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1427 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1428 struct ata_device *atadev = device_get_softc(dev); 1429 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1430 int offset = (devno ^ 0x01) << 3; 1431 int error; 1432 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 1433 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 1434 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 1435 1436 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1437 1438 mode = ata_check_80pin(dev, mode); 1439 1440 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1441 1442 if (bootverbose) 1443 device_printf(dev, "%ssetting %s on %s chip\n", 1444 (error) ? "FAILURE " : "", 1445 ata_mode2str(mode), ctlr->chip->text); 1446 if (!error) { 1447 if (mode >= ATA_UDMA0) { 1448 pci_write_config(gparent, 0x56, 1449 (pci_read_config(gparent, 0x56, 2) & 1450 ~(0xf << (devno << 2))) | 1451 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 1452 pci_write_config(gparent, 0x54, 1453 pci_read_config(gparent, 0x54, 1) | 1454 (0x01 << devno), 1); 1455 pci_write_config(gparent, 0x44, 1456 (pci_read_config(gparent, 0x44, 4) & 1457 ~(0xff << offset)) | 1458 (dmatimings[2] << offset), 4); 1459 } 1460 else if (mode >= ATA_WDMA0) { 1461 pci_write_config(gparent, 0x54, 1462 pci_read_config(gparent, 0x54, 1) & 1463 ~(0x01 << devno), 1); 1464 pci_write_config(gparent, 0x44, 1465 (pci_read_config(gparent, 0x44, 4) & 1466 ~(0xff << offset)) | 1467 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 1468 } 1469 else 1470 pci_write_config(gparent, 0x54, 1471 pci_read_config(gparent, 0x54, 1) & 1472 ~(0x01 << devno), 1); 1473 1474 pci_write_config(gparent, 0x4a, 1475 (pci_read_config(gparent, 0x4a, 2) & 1476 ~(0xf << (devno << 2))) | 1477 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2); 1478 pci_write_config(gparent, 0x40, 1479 (pci_read_config(gparent, 0x40, 4) & 1480 ~(0xff << offset)) | 1481 (piotimings[ata_mode2idx(mode)] << offset), 4); 1482 atadev->mode = mode; 1483 } 1484 } 1485 1486 /* 1487 * Cyrix chipset support functions 1488 */ 1489 int 1490 ata_cyrix_ident(device_t dev) 1491 { 1492 struct ata_pci_controller *ctlr = device_get_softc(dev); 1493 1494 if (pci_get_devid(dev) == ATA_CYRIX_5530) { 1495 device_set_desc(dev, "Cyrix 5530 ATA33 controller"); 1496 ctlr->chipinit = ata_cyrix_chipinit; 1497 return 0; 1498 } 1499 return ENXIO; 1500 } 1501 1502 static int 1503 ata_cyrix_chipinit(device_t dev) 1504 { 1505 struct ata_pci_controller *ctlr = device_get_softc(dev); 1506 1507 if (ata_setup_interrupt(dev)) 1508 return ENXIO; 1509 1510 if (ctlr->r_res1) 1511 ctlr->setmode = ata_cyrix_setmode; 1512 else 1513 ctlr->setmode = ata_generic_setmode; 1514 return 0; 1515 } 1516 1517 static void 1518 ata_cyrix_setmode(device_t dev, int mode) 1519 { 1520 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1521 struct ata_device *atadev = device_get_softc(dev); 1522 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1523 u_int32_t piotiming[] = 1524 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 }; 1525 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 }; 1526 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 }; 1527 int error; 1528 1529 ch->dma->alignment = 16; 1530 ch->dma->max_iosize = 126 * DEV_BSIZE; 1531 1532 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 1533 1534 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1535 1536 if (bootverbose) 1537 device_printf(dev, "%ssetting %s on Cyrix chip\n", 1538 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1539 if (!error) { 1540 if (mode >= ATA_UDMA0) { 1541 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1542 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]); 1543 } 1544 else if (mode >= ATA_WDMA0) { 1545 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1546 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]); 1547 } 1548 else { 1549 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1550 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]); 1551 } 1552 atadev->mode = mode; 1553 } 1554 } 1555 1556 1557 /* 1558 * Cypress chipset support functions 1559 */ 1560 int 1561 ata_cypress_ident(device_t dev) 1562 { 1563 struct ata_pci_controller *ctlr = device_get_softc(dev); 1564 1565 /* 1566 * the Cypress chip is a mess, it contains two ATA functions, but 1567 * both channels are visible on the first one. 1568 * simply ignore the second function for now, as the right 1569 * solution (ignoring the second channel on the first function) 1570 * doesn't work with the crappy ATA interrupt setup on the alpha. 1571 */ 1572 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 && 1573 pci_get_function(dev) == 1 && 1574 pci_get_subclass(dev) == PCIS_STORAGE_IDE) { 1575 device_set_desc(dev, "Cypress 82C693 ATA controller"); 1576 ctlr->chipinit = ata_cypress_chipinit; 1577 return 0; 1578 } 1579 return ENXIO; 1580 } 1581 1582 static int 1583 ata_cypress_chipinit(device_t dev) 1584 { 1585 struct ata_pci_controller *ctlr = device_get_softc(dev); 1586 1587 if (ata_setup_interrupt(dev)) 1588 return ENXIO; 1589 1590 ctlr->setmode = ata_cypress_setmode; 1591 return 0; 1592 } 1593 1594 static void 1595 ata_cypress_setmode(device_t dev, int mode) 1596 { 1597 device_t gparent = GRANDPARENT(dev); 1598 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1599 struct ata_device *atadev = device_get_softc(dev); 1600 int error; 1601 1602 mode = ata_limit_mode(dev, mode, ATA_WDMA2); 1603 1604 /* XXX SOS missing WDMA0+1 + PIO modes */ 1605 if (mode == ATA_WDMA2) { 1606 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1607 if (bootverbose) 1608 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n", 1609 error ? "FAILURE " : ""); 1610 if (!error) { 1611 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2); 1612 atadev->mode = mode; 1613 return; 1614 } 1615 } 1616 /* we could set PIO mode timings, but we assume the BIOS did that */ 1617 } 1618 1619 1620 /* 1621 * HighPoint chipset support functions 1622 */ 1623 int 1624 ata_highpoint_ident(device_t dev) 1625 { 1626 struct ata_pci_controller *ctlr = device_get_softc(dev); 1627 struct ata_chip_id *idx; 1628 static struct ata_chip_id ids[] = 1629 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" }, 1630 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" }, 1631 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1632 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" }, 1633 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1634 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" }, 1635 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" }, 1636 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" }, 1637 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" }, 1638 { 0, 0, 0, 0, 0, 0}}; 1639 char buffer[64]; 1640 1641 if (!(idx = ata_match_chip(dev, ids))) 1642 return ENXIO; 1643 1644 strcpy(buffer, "HighPoint "); 1645 strcat(buffer, idx->text); 1646 if (idx->cfg1 == HPT374) { 1647 if (pci_get_function(dev) == 0) 1648 strcat(buffer, " (channel 0+1)"); 1649 if (pci_get_function(dev) == 1) 1650 strcat(buffer, " (channel 2+3)"); 1651 } 1652 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 1653 device_set_desc_copy(dev, buffer); 1654 ctlr->chip = idx; 1655 ctlr->chipinit = ata_highpoint_chipinit; 1656 return 0; 1657 } 1658 1659 static int 1660 ata_highpoint_chipinit(device_t dev) 1661 { 1662 struct ata_pci_controller *ctlr = device_get_softc(dev); 1663 1664 if (ata_setup_interrupt(dev)) 1665 return ENXIO; 1666 1667 if (ctlr->chip->cfg2 == HPTOLD) { 1668 /* disable interrupt prediction */ 1669 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 1670 } 1671 else { 1672 /* disable interrupt prediction */ 1673 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 1674 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 1675 1676 /* enable interrupts */ 1677 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 1678 1679 /* set clocks etc */ 1680 if (ctlr->chip->cfg1 < HPT372) 1681 pci_write_config(dev, 0x5b, 0x22, 1); 1682 else 1683 pci_write_config(dev, 0x5b, 1684 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 1685 } 1686 ctlr->allocate = ata_highpoint_allocate; 1687 ctlr->setmode = ata_highpoint_setmode; 1688 return 0; 1689 } 1690 1691 static int 1692 ata_highpoint_allocate(device_t dev) 1693 { 1694 struct ata_channel *ch = device_get_softc(dev); 1695 1696 /* setup the usual register normal pci style */ 1697 if (ata_pci_allocate(dev)) 1698 return ENXIO; 1699 1700 ch->flags |= ATA_ALWAYS_DMASTAT; 1701 return 0; 1702 } 1703 1704 static void 1705 ata_highpoint_setmode(device_t dev, int mode) 1706 { 1707 device_t gparent = GRANDPARENT(dev); 1708 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1709 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1710 struct ata_device *atadev = device_get_softc(dev); 1711 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1712 int error; 1713 u_int32_t timings33[][4] = { 1714 /* HPT366 HPT370 HPT372 HPT374 mode */ 1715 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */ 1716 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */ 1717 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */ 1718 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */ 1719 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */ 1720 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */ 1721 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */ 1722 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */ 1723 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */ 1724 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */ 1725 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */ 1726 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */ 1727 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */ 1728 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */ 1729 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */ 1730 }; 1731 1732 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1733 1734 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev)) 1735 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1736 1737 mode = ata_highpoint_check_80pin(dev, mode); 1738 1739 /* 1740 * most if not all HPT chips cant really handle that the device is 1741 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to 1742 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance 1743 */ 1744 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 1745 ata_limit_mode(dev, mode, ATA_UDMA5)); 1746 if (bootverbose) 1747 device_printf(dev, "%ssetting %s on HighPoint chip\n", 1748 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1749 if (!error) 1750 pci_write_config(gparent, 0x40 + (devno << 2), 1751 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 1752 atadev->mode = mode; 1753 } 1754 1755 static int 1756 ata_highpoint_check_80pin(device_t dev, int mode) 1757 { 1758 device_t gparent = GRANDPARENT(dev); 1759 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1760 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1761 u_int8_t reg, val, res; 1762 1763 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) { 1764 reg = ch->unit ? 0x57 : 0x53; 1765 val = pci_read_config(gparent, reg, 1); 1766 pci_write_config(gparent, reg, val | 0x80, 1); 1767 } 1768 else { 1769 reg = 0x5b; 1770 val = pci_read_config(gparent, reg, 1); 1771 pci_write_config(gparent, reg, val & 0xfe, 1); 1772 } 1773 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2); 1774 pci_write_config(gparent, reg, val, 1); 1775 1776 if (mode > ATA_UDMA2 && res) { 1777 ata_print_cable(dev, "controller"); 1778 mode = ATA_UDMA2; 1779 } 1780 return mode; 1781 } 1782 1783 1784 /* 1785 * Intel chipset support functions 1786 */ 1787 int 1788 ata_intel_ident(device_t dev) 1789 { 1790 struct ata_pci_controller *ctlr = device_get_softc(dev); 1791 struct ata_chip_id *idx; 1792 static struct ata_chip_id ids[] = 1793 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" }, 1794 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" }, 1795 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1796 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1797 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1798 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" }, 1799 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1800 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1801 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1802 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1803 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1804 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1805 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1806 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1807 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" }, 1808 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1809 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1810 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" }, 1811 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1812 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1813 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" }, 1814 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1815 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1816 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" }, 1817 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" }, 1818 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1819 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1820 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1821 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1822 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1823 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1824 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" }, 1825 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1826 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1827 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1828 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1829 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1830 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1831 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1832 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1833 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1834 { ATA_I82801HBM_S1, 0, 0, 0x00, ATA_SA300, "ICH8M" }, 1835 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1836 { ATA_I82801HBM_S3, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1837 { ATA_I82801IB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1838 { ATA_I82801IB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1839 { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1840 { ATA_I82801IB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1841 { ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1842 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" }, 1843 { 0, 0, 0, 0, 0, 0}}; 1844 char buffer[64]; 1845 1846 if (!(idx = ata_match_chip(dev, ids))) 1847 return ENXIO; 1848 1849 ksprintf(buffer, "Intel %s %s controller", 1850 idx->text, ata_mode2str(idx->max_dma)); 1851 device_set_desc_copy(dev, buffer); 1852 ctlr->chip = idx; 1853 ctlr->chipinit = ata_intel_chipinit; 1854 return 0; 1855 } 1856 1857 static int 1858 ata_intel_chipinit(device_t dev) 1859 { 1860 struct ata_pci_controller *ctlr = device_get_softc(dev); 1861 1862 if (ata_setup_interrupt(dev)) 1863 return ENXIO; 1864 1865 /* good old PIIX needs special treatment (not implemented) */ 1866 if (ctlr->chip->chipid == ATA_I82371FB) { 1867 ctlr->setmode = ata_intel_old_setmode; 1868 } 1869 1870 /* the intel 31244 needs special care if in DPA mode */ 1871 else if (ctlr->chip->chipid == ATA_I31244) { 1872 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 1873 ctlr->r_type2 = SYS_RES_MEMORY; 1874 ctlr->r_rid2 = PCIR_BAR(0); 1875 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1876 &ctlr->r_rid2, 1877 RF_ACTIVE))) 1878 return ENXIO; 1879 ctlr->channels = 4; 1880 ctlr->allocate = ata_intel_31244_allocate; 1881 ctlr->reset = ata_intel_31244_reset; 1882 } 1883 ctlr->setmode = ata_sata_setmode; 1884 } 1885 1886 /* non SATA intel chips goes here */ 1887 else if (ctlr->chip->max_dma < ATA_SA150) { 1888 ctlr->allocate = ata_intel_allocate; 1889 ctlr->setmode = ata_intel_new_setmode; 1890 } 1891 1892 /* SATA parts can be either compat or AHCI */ 1893 else { 1894 /* force all ports active "the legacy way" */ 1895 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2); 1896 1897 ctlr->allocate = ata_intel_allocate; 1898 ctlr->reset = ata_intel_reset; 1899 1900 /* 1901 * if we have AHCI capability and BAR(5) as a memory resource 1902 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode 1903 */ 1904 if ((ctlr->chip->cfg1 == AHCI) && 1905 (pci_read_config(dev, 0x90, 1) & 0xc0) && 1906 (ata_ahci_chipinit(dev) != ENXIO)) 1907 return 0; 1908 1909 /* if BAR(5) is IO it should point to SATA interface registers */ 1910 ctlr->r_type2 = SYS_RES_IOPORT; 1911 ctlr->r_rid2 = PCIR_BAR(5); 1912 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1913 &ctlr->r_rid2, RF_ACTIVE))) 1914 ctlr->setmode = ata_intel_sata_setmode; 1915 else 1916 ctlr->setmode = ata_sata_setmode; 1917 1918 /* enable PCI interrupt */ 1919 pci_write_config(dev, PCIR_COMMAND, 1920 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1921 } 1922 return 0; 1923 } 1924 1925 static int 1926 ata_intel_allocate(device_t dev) 1927 { 1928 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1929 struct ata_channel *ch = device_get_softc(dev); 1930 1931 /* setup the usual register normal pci style */ 1932 if (ata_pci_allocate(dev)) 1933 return ENXIO; 1934 1935 /* if r_res2 is valid it points to SATA interface registers */ 1936 if (ctlr->r_res2) { 1937 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 1938 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 1939 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 1940 ch->r_io[ATA_IDX_DATA].offset = 0x04; 1941 } 1942 1943 ch->flags |= ATA_ALWAYS_DMASTAT; 1944 return 0; 1945 } 1946 1947 static void 1948 ata_intel_reset(device_t dev) 1949 { 1950 device_t parent = device_get_parent(dev); 1951 struct ata_pci_controller *ctlr = device_get_softc(parent); 1952 struct ata_channel *ch = device_get_softc(dev); 1953 int mask, timeout; 1954 1955 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */ 1956 if (ctlr->chip->cfg1) { 1957 mask = (0x0005 << ch->unit); 1958 } 1959 else { 1960 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */ 1961 if (pci_read_config(parent, 0x90, 1) & 0x04) 1962 mask = 0x0003; 1963 else { 1964 mask = (0x0001 << ch->unit); 1965 /* XXX SOS should be in intel_allocate if we grow it */ 1966 ch->flags |= ATA_NO_SLAVE; 1967 } 1968 } 1969 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2); 1970 DELAY(10); 1971 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2); 1972 1973 /* wait up to 1 sec for "connect well" */ 1974 for (timeout = 0; timeout < 100 ; timeout++) { 1975 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) && 1976 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 1977 break; 1978 ata_udelay(10000); 1979 } 1980 ata_generic_reset(dev); 1981 } 1982 1983 static void 1984 ata_intel_old_setmode(device_t dev, int mode) 1985 { 1986 /* NOT YET */ 1987 } 1988 1989 static void 1990 ata_intel_new_setmode(device_t dev, int mode) 1991 { 1992 device_t gparent = GRANDPARENT(dev); 1993 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1994 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1995 struct ata_device *atadev = device_get_softc(dev); 1996 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1997 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4); 1998 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1); 1999 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1); 2000 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2); 2001 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2); 2002 u_int32_t mask40 = 0, new40 = 0; 2003 u_int8_t mask44 = 0, new44 = 0; 2004 int error; 2005 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, 2006 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 }; 2007 /* PIO0 PIO1 PIO2 PIO3 PIO4 WDMA0 WDMA1 WDMA2 */ 2008 /* UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 UDMA5 UDMA6 */ 2009 2010 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 2011 2012 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { 2013 ata_print_cable(dev, "controller"); 2014 mode = ATA_UDMA2; 2015 } 2016 2017 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2018 2019 if (bootverbose) 2020 device_printf(dev, "%ssetting %s on %s chip\n", 2021 (error) ? "FAILURE " : "", 2022 ata_mode2str(mode), ctlr->chip->text); 2023 if (error) 2024 return; 2025 2026 /* 2027 * reg48: 1 bit per (primary drive 0, primary drive 1, secondary 2028 * drive 0, secondary drive 1) 2029 * 2030 * 0 Disable Ultra DMA mode 2031 * 1 Enable Ultra DMA mode 2032 * 2033 * reg4a: 4 bits per (primary drive 0, primary drive 1, secondary 2034 * drive 0, secondary drive 1). 2035 * 0000 UDMA mode 0 2036 * 0001 UDMA mode 1, 3, 5 2037 * 0010 UDMA mode 2, 4, reserved 2038 * 0011 reserved 2039 * (top two bits for each drive reserved) 2040 */ 2041 #if 0 2042 device_printf(dev, 2043 "regs before 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 2044 reg40, reg44, reg48 ,reg4a, reg54); 2045 #endif 2046 reg48 &= ~(0x0001 << devno); 2047 reg4a &= ~(0x3 << (devno << 2)); 2048 if (mode >= ATA_UDMA0) { 2049 reg48 |= 0x0001 << devno; 2050 if (mode > ATA_UDMA0) 2051 reg4a |= (1 + !(mode & 0x01)) << (devno << 2); 2052 } 2053 pci_write_config(gparent, 0x48, reg48, 2); 2054 pci_write_config(gparent, 0x4a, reg4a, 2); 2055 2056 /* 2057 * reg54: 2058 * 2059 * 32:20 reserved 2060 * 19:18 Secondary ATA signal mode 2061 * 17:16 Primary ATA signal mode 2062 * 00 = Normal (enabled) 2063 * 01 = Tri-state (disabled) 2064 * 10 = Drive Low (disabled) 2065 * 11 = Reserved 2066 * 2067 * 15 Secondary drive 1 - Base Clock 2068 * 14 Secondary drive 0 - Base Clock 2069 * 13 Primary drive 1 - Base Clock 2070 * 12 Primary drive 0 - Base Clock 2071 * 0 = Select 33 MHz clock 2072 * 1 = Select 100 Mhz clock 2073 * 2074 * 11 Reserved 2075 * 10 Vendor specific (set by BIOS?) 2076 * 09:08 Reserved 2077 * 2078 * 07 Secondary drive 1 - Cable Type 2079 * 06 Secondary drive 0 - Cable Type 2080 * 05 Primary drive 1 - Cable Type 2081 * 04 Primary drive 0 - Cable Type 2082 * 0 = 40 Conductor 2083 * 1 = 80 Conductor (or high speed cable) 2084 * 2085 * 03 Secondary drive 1 - Select 33/66 clock 2086 * 02 Secondary drive 0 - Select 33/66 clock 2087 * 01 Primary drive 1 - Select 33/66 clock 2088 * 00 Primary drive 0 - Select 33/66 clock 2089 * 0 = Select 33 MHz 2090 * 1 = Select 66 MHz 2091 * 2092 * It is unclear what this should be set to when operating 2093 * in 100MHz mode. 2094 * 2095 * NOTE: UDMA2 = 33 MHz 2096 * UDMA3 = 40 MHz (?) - unsupported 2097 * UDMA4 = 66 MHz 2098 * UDMA5 = 100 MHz 2099 * UDMA6 = 133 Mhz 2100 */ 2101 reg54 |= 0x0400; /* set vendor specific bit */ 2102 reg54 &= ~((0x1 << devno) | (0x1000 << devno)); 2103 2104 if (mode >= ATA_UDMA5) 2105 reg54 |= (0x1000 << devno); 2106 else if (mode >= ATA_UDMA3) /* XXX should this be ATA_UDMA3 or 4? */ 2107 reg54 |= (0x1 << devno); 2108 2109 pci_write_config(gparent, 0x54, reg54, 2); 2110 2111 /* 2112 * Reg40 (32 bits... well, actually two 16 bit registers) 2113 * 2114 * Primary channel bits 15:00, Secondary channel bits 31:00. Note 2115 * that slave timings are handled in register 44. 2116 * 2117 * 15 ATA Decode Enable (R/W) 1 = enable decoding of I/O ranges 2118 * 2119 * 14 Slave ATA Timing Register Enable (R/W) 2120 * 2121 * 13:12 IORDY Sample Mode 2122 * 00 PIO-0 2123 * 01 PIO-2, SW-2 2124 * 10 PIO-3, PIO-4, MW-1, MW-2 2125 * 11 Reserved 2126 * 2127 * 11:10 Reserved 2128 * 2129 * 09:08 Recovery Mode 2130 * 00 PIO-0, PIO-2, SW-2 2131 * 01 PIO-3, MW-1 2132 * 10 Reserved 2133 * 11 PIO-4, MW-2 2134 * 2135 * 07:04 Secondary Device Control Bits 2136 * 03:00 Primary Device Control Bits 2137 * 2138 * bit 3 DMA Timing Enable 2139 * 2140 * bit 2 Indicate Presence of ATA(1) or ATAPI(0) device 2141 * 2142 * bit 1 Enable IORDY sample point capability for PIO 2143 * xfers. Always enabled for PIO4 and PIO3, enabled 2144 * for PIO2 if indicated by the device, and otherwise 2145 * probably should be 0. 2146 * 2147 * bit 0 Fast Drive Timing Enable. Enables faster then PIO-0 2148 * timing modes. 2149 */ 2150 2151 /* 2152 * Modify reg40 according to the table 2153 */ 2154 if (atadev->unit == ATA_MASTER) { 2155 mask40 = 0x3300; 2156 new40 = timings[ata_mode2idx(mode)] << 8; 2157 } 2158 else { 2159 mask44 = 0x0f; 2160 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) | 2161 (timings[ata_mode2idx(mode)] & 0x03); 2162 } 2163 2164 /* 2165 * Slave ATA timing register enable 2166 */ 2167 mask40 |= 0x4000; 2168 new40 |= 0x4000; 2169 2170 /* 2171 * Device control bits 3:0 for master, 7:4 for slave. 2172 * 2173 * bit3 DMA Timing enable. 2174 * bit2 Indicate presence of ATA(1) or ATAPI(0) device, set accordingly 2175 * bit1 Enable IORDY sample point capability for PIO xfers. Always 2176 * enabled for PIO4 and PIO3, enabled for PIO2 if indicated by 2177 * the device, and otherwise should be 0. 2178 * bit0 Fast Drive Timing Enable. Enable faster then PIO-0 timing modes. 2179 * 2180 * Set to: 0 x 1 1 2181 */ 2182 2183 if (atadev->unit == ATA_MASTER) { 2184 mask40 |= 0x0F; 2185 new40 |= 0x03; 2186 if (!ata_atapi(dev)) 2187 new40 |= 0x04; 2188 } else { 2189 mask40 |= 0xF0; 2190 new40 |= 0x30; 2191 if (!ata_atapi(dev)) 2192 new40 |= 0x40; 2193 } 2194 /* 2195 reg40 &= ~0x00ff00ff; 2196 reg40 |= 0x40774077; 2197 */ 2198 2199 /* 2200 * Primary or Secondary controller 2201 */ 2202 if (ch->unit) { 2203 mask40 <<= 16; 2204 new40 <<= 16; 2205 mask44 <<= 4; 2206 new44 <<= 4; 2207 } 2208 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4); 2209 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1); 2210 2211 #if 0 2212 reg40 = pci_read_config(gparent, 0x40, 4); 2213 reg44 = pci_read_config(gparent, 0x44, 1); 2214 reg48 = pci_read_config(gparent, 0x48, 1); 2215 reg4a = pci_read_config(gparent, 0x4a, 2); 2216 reg54 = pci_read_config(gparent, 0x54, 2); 2217 device_printf(dev, 2218 "regs after 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 2219 reg40, reg44, reg48 ,reg4a, reg54); 2220 #endif 2221 2222 atadev->mode = mode; 2223 } 2224 2225 static void 2226 ata_intel_sata_setmode(device_t dev, int mode) 2227 { 2228 struct ata_device *atadev = device_get_softc(dev); 2229 2230 if (atadev->param.satacapabilities != 0x0000 && 2231 atadev->param.satacapabilities != 0xffff) { 2232 2233 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2234 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2235 2236 /* on some drives we need to set the transfer mode */ 2237 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 2238 ata_limit_mode(dev, mode, ATA_UDMA6)); 2239 2240 /* set ATA_SSTATUS register offset */ 2241 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100); 2242 2243 /* query SATA STATUS for the speed */ 2244 if ((ATA_IDX_INL(ch, ATA_IDX_DATA) & ATA_SS_CONWELL_MASK) == 2245 ATA_SS_CONWELL_GEN2) 2246 atadev->mode = ATA_SA300; 2247 else 2248 atadev->mode = ATA_SA150; 2249 } 2250 else { 2251 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 2252 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2253 atadev->mode = mode; 2254 } 2255 } 2256 2257 static int 2258 ata_intel_31244_allocate(device_t dev) 2259 { 2260 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2261 struct ata_channel *ch = device_get_softc(dev); 2262 int i; 2263 int ch_offset; 2264 2265 ch_offset = 0x200 + ch->unit * 0x200; 2266 2267 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 2268 ch->r_io[i].res = ctlr->r_res2; 2269 2270 /* setup ATA registers */ 2271 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 2272 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 2273 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 2274 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 2275 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 2276 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 2277 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 2278 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 2279 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 2280 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 2281 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 2282 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 2283 2284 /* setup DMA registers */ 2285 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 2286 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 2287 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 2288 2289 /* setup SATA registers */ 2290 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 2291 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 2292 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 2293 2294 ch->flags |= ATA_NO_SLAVE; 2295 ata_pci_hw(dev); 2296 ch->hw.status = ata_intel_31244_status; 2297 ch->hw.command = ata_intel_31244_command; 2298 2299 /* enable PHY state change interrupt */ 2300 ATA_OUTL(ctlr->r_res2, 0x4, 2301 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 2302 return 0; 2303 } 2304 2305 static int 2306 ata_intel_31244_status(device_t dev) 2307 { 2308 /* do we have any PHY events ? */ 2309 ata_sata_phy_check_events(dev); 2310 2311 /* any drive action to take care of ? */ 2312 return ata_pci_status(dev); 2313 } 2314 2315 static int 2316 ata_intel_31244_command(struct ata_request *request) 2317 { 2318 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2319 struct ata_device *atadev = device_get_softc(request->dev); 2320 u_int64_t lba; 2321 2322 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 2323 return (ata_generic_command(request)); 2324 2325 lba = request->u.ata.lba; 2326 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 2327 /* enable interrupt */ 2328 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 2329 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 2330 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 2331 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff)); 2332 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) | 2333 ((lba >> 8) & 0x00ff)); 2334 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) | 2335 ((lba >> 16) & 0x00ff)); 2336 2337 /* issue command to controller */ 2338 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 2339 2340 return 0; 2341 } 2342 2343 static void 2344 ata_intel_31244_reset(device_t dev) 2345 { 2346 if (ata_sata_phy_reset(dev)) 2347 ata_generic_reset(dev); 2348 } 2349 2350 2351 /* 2352 * Integrated Technology Express Inc. (ITE) chipset support functions 2353 */ 2354 int 2355 ata_ite_ident(device_t dev) 2356 { 2357 struct ata_pci_controller *ctlr = device_get_softc(dev); 2358 struct ata_chip_id *idx; 2359 static struct ata_chip_id ids[] = 2360 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 2361 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 2362 { 0, 0, 0, 0, 0, 0}}; 2363 char buffer[64]; 2364 2365 if (!(idx = ata_match_chip(dev, ids))) 2366 return ENXIO; 2367 2368 ksprintf(buffer, "ITE %s %s controller", 2369 idx->text, ata_mode2str(idx->max_dma)); 2370 device_set_desc_copy(dev, buffer); 2371 ctlr->chip = idx; 2372 ctlr->chipinit = ata_ite_chipinit; 2373 return 0; 2374 } 2375 2376 static int 2377 ata_ite_chipinit(device_t dev) 2378 { 2379 struct ata_pci_controller *ctlr = device_get_softc(dev); 2380 2381 if (ata_setup_interrupt(dev)) 2382 return ENXIO; 2383 2384 ctlr->setmode = ata_ite_setmode; 2385 2386 /* set PCI mode and 66Mhz reference clock */ 2387 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 2388 2389 /* set default active & recover timings */ 2390 pci_write_config(dev, 0x54, 0x31, 1); 2391 pci_write_config(dev, 0x56, 0x31, 1); 2392 return 0; 2393 } 2394 2395 static void 2396 ata_ite_setmode(device_t dev, int mode) 2397 { 2398 device_t gparent = GRANDPARENT(dev); 2399 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2400 struct ata_device *atadev = device_get_softc(dev); 2401 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2402 int error; 2403 2404 /* correct the mode for what the HW supports */ 2405 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2406 2407 /* check the CBLID bits for 80 conductor cable detection */ 2408 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) & 2409 (ch->unit ? (1<<3) : (1<<2)))) { 2410 ata_print_cable(dev, "controller"); 2411 mode = ATA_UDMA2; 2412 } 2413 2414 /* set the wanted mode on the device */ 2415 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2416 2417 if (bootverbose) 2418 device_printf(dev, "%s setting %s on ITE8212F chip\n", 2419 (error) ? "failed" : "success", ata_mode2str(mode)); 2420 2421 /* if the device accepted the mode change, setup the HW accordingly */ 2422 if (!error) { 2423 if (mode >= ATA_UDMA0) { 2424 u_int8_t udmatiming[] = 2425 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 2426 2427 /* enable UDMA mode */ 2428 pci_write_config(gparent, 0x50, 2429 pci_read_config(gparent, 0x50, 1) & 2430 ~(1 << (devno + 3)), 1); 2431 2432 /* set UDMA timing */ 2433 pci_write_config(gparent, 2434 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit), 2435 udmatiming[mode & ATA_MODE_MASK], 1); 2436 } 2437 else { 2438 u_int8_t chtiming[] = 2439 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 2440 2441 /* disable UDMA mode */ 2442 pci_write_config(gparent, 0x50, 2443 pci_read_config(gparent, 0x50, 1) | 2444 (1 << (devno + 3)), 1); 2445 2446 /* set active and recover timing (shared between master & slave) */ 2447 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) < 2448 chtiming[ata_mode2idx(mode)]) 2449 pci_write_config(gparent, 0x54 + (ch->unit << 2), 2450 chtiming[ata_mode2idx(mode)], 1); 2451 } 2452 atadev->mode = mode; 2453 } 2454 } 2455 2456 2457 /* 2458 * JMicron chipset support functions 2459 */ 2460 int 2461 ata_jmicron_ident(device_t dev) 2462 { 2463 struct ata_pci_controller *ctlr = device_get_softc(dev); 2464 struct ata_chip_id *idx; 2465 static struct ata_chip_id ids[] = 2466 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" }, 2467 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" }, 2468 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" }, 2469 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" }, 2470 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" }, 2471 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" }, 2472 { 0, 0, 0, 0, 0, 0}}; 2473 char buffer[64]; 2474 2475 if (!(idx = ata_match_chip(dev, ids))) 2476 return ENXIO; 2477 2478 if ((pci_read_config(dev, 0xdf, 1) & 0x40) && 2479 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1))) 2480 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2481 idx->text, ata_mode2str(ATA_UDMA6)); 2482 else 2483 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2484 idx->text, ata_mode2str(idx->max_dma)); 2485 device_set_desc_copy(dev, buffer); 2486 ctlr->chip = idx; 2487 ctlr->chipinit = ata_jmicron_chipinit; 2488 return 0; 2489 } 2490 2491 static int 2492 ata_jmicron_chipinit(device_t dev) 2493 { 2494 struct ata_pci_controller *ctlr = device_get_softc(dev); 2495 int error; 2496 2497 if (ata_setup_interrupt(dev)) 2498 return ENXIO; 2499 2500 /* do we have multiple PCI functions ? */ 2501 if (pci_read_config(dev, 0xdf, 1) & 0x40) { 2502 /* are we on the AHCI part ? */ 2503 if (ata_ahci_chipinit(dev) != ENXIO) 2504 return 0; 2505 2506 /* otherwise we are on the PATA part */ 2507 ctlr->allocate = ata_pci_allocate; 2508 ctlr->reset = ata_generic_reset; 2509 ctlr->dmainit = ata_pci_dmainit; 2510 ctlr->setmode = ata_jmicron_setmode; 2511 ctlr->channels = ctlr->chip->cfg2; 2512 } 2513 else { 2514 /* set controller configuration to a combined setup we support */ 2515 pci_write_config(dev, 0x40, 0x80c0a131, 4); 2516 pci_write_config(dev, 0x80, 0x01200000, 4); 2517 2518 if ((error = ata_ahci_chipinit(dev))) 2519 return error; 2520 2521 ctlr->allocate = ata_jmicron_allocate; 2522 ctlr->reset = ata_jmicron_reset; 2523 ctlr->dmainit = ata_jmicron_dmainit; 2524 ctlr->setmode = ata_jmicron_setmode; 2525 2526 /* set the number of HW channels */ 2527 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2; 2528 } 2529 return 0; 2530 } 2531 2532 static int 2533 ata_jmicron_allocate(device_t dev) 2534 { 2535 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2536 struct ata_channel *ch = device_get_softc(dev); 2537 int error; 2538 2539 if (ch->unit >= ctlr->chip->cfg1) { 2540 ch->unit -= ctlr->chip->cfg1; 2541 error = ata_pci_allocate(dev); 2542 ch->unit += ctlr->chip->cfg1; 2543 } 2544 else 2545 error = ata_ahci_allocate(dev); 2546 return error; 2547 } 2548 2549 static void 2550 ata_jmicron_reset(device_t dev) 2551 { 2552 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2553 struct ata_channel *ch = device_get_softc(dev); 2554 2555 if (ch->unit >= ctlr->chip->cfg1) 2556 ata_generic_reset(dev); 2557 else 2558 ata_ahci_reset(dev); 2559 } 2560 2561 static void 2562 ata_jmicron_dmainit(device_t dev) 2563 { 2564 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2565 struct ata_channel *ch = device_get_softc(dev); 2566 2567 if (ch->unit >= ctlr->chip->cfg1) 2568 ata_pci_dmainit(dev); 2569 else 2570 ata_ahci_dmainit(dev); 2571 } 2572 2573 static void 2574 ata_jmicron_setmode(device_t dev, int mode) 2575 { 2576 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 2577 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2578 2579 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) { 2580 struct ata_device *atadev = device_get_softc(dev); 2581 2582 /* check for 80pin cable present */ 2583 if (pci_read_config(dev, 0x40, 1) & 0x08) 2584 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 2585 else 2586 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2587 2588 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2589 atadev->mode = mode; 2590 } 2591 else 2592 ata_sata_setmode(dev, mode); 2593 } 2594 2595 2596 /* 2597 * Marvell chipset support functions 2598 */ 2599 #define ATA_MV_HOST_BASE(ch) \ 2600 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000) 2601 #define ATA_MV_EDMA_BASE(ch) \ 2602 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000) 2603 2604 struct ata_marvell_response { 2605 u_int16_t tag; 2606 u_int8_t edma_status; 2607 u_int8_t dev_status; 2608 u_int32_t timestamp; 2609 }; 2610 2611 struct ata_marvell_dma_prdentry { 2612 u_int32_t addrlo; 2613 u_int32_t count; 2614 u_int32_t addrhi; 2615 u_int32_t reserved; 2616 }; 2617 2618 int 2619 ata_marvell_ident(device_t dev) 2620 { 2621 struct ata_pci_controller *ctlr = device_get_softc(dev); 2622 struct ata_chip_id *idx; 2623 static struct ata_chip_id ids[] = 2624 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" }, 2625 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" }, 2626 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" }, 2627 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" }, 2628 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" }, 2629 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" }, 2630 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" }, 2631 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" }, 2632 { 0, 0, 0, 0, 0, 0}}; 2633 char buffer[64]; 2634 2635 if (!(idx = ata_match_chip(dev, ids))) 2636 return ENXIO; 2637 2638 ksprintf(buffer, "Marvell %s %s controller", 2639 idx->text, ata_mode2str(idx->max_dma)); 2640 device_set_desc_copy(dev, buffer); 2641 ctlr->chip = idx; 2642 switch (ctlr->chip->cfg2) { 2643 case MV50XX: 2644 case MV60XX: 2645 ctlr->chipinit = ata_marvell_edma_chipinit; 2646 break; 2647 case MV61XX: 2648 ctlr->chipinit = ata_marvell_pata_chipinit; 2649 break; 2650 } 2651 return 0; 2652 } 2653 2654 static int 2655 ata_marvell_pata_chipinit(device_t dev) 2656 { 2657 struct ata_pci_controller *ctlr = device_get_softc(dev); 2658 2659 if (ata_setup_interrupt(dev)) 2660 return ENXIO; 2661 2662 ctlr->allocate = ata_marvell_pata_allocate; 2663 ctlr->setmode = ata_marvell_pata_setmode; 2664 ctlr->channels = ctlr->chip->cfg1; 2665 return 0; 2666 } 2667 2668 static int 2669 ata_marvell_pata_allocate(device_t dev) 2670 { 2671 struct ata_channel *ch = device_get_softc(dev); 2672 2673 /* setup the usual register normal pci style */ 2674 if (ata_pci_allocate(dev)) 2675 return ENXIO; 2676 2677 /* dont use 32 bit PIO transfers */ 2678 ch->flags |= ATA_USE_16BIT; 2679 2680 return 0; 2681 } 2682 2683 static void 2684 ata_marvell_pata_setmode(device_t dev, int mode) 2685 { 2686 device_t gparent = GRANDPARENT(dev); 2687 struct ata_pci_controller *ctlr = device_get_softc(gparent); 2688 struct ata_device *atadev = device_get_softc(dev); 2689 2690 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 2691 mode = ata_check_80pin(dev, mode); 2692 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2693 atadev->mode = mode; 2694 } 2695 2696 static int 2697 ata_marvell_edma_chipinit(device_t dev) 2698 { 2699 struct ata_pci_controller *ctlr = device_get_softc(dev); 2700 2701 if (ata_setup_interrupt(dev)) 2702 return ENXIO; 2703 2704 ctlr->r_type1 = SYS_RES_MEMORY; 2705 ctlr->r_rid1 = PCIR_BAR(0); 2706 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 2707 &ctlr->r_rid1, RF_ACTIVE))) 2708 return ENXIO; 2709 2710 /* mask all host controller interrupts */ 2711 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000); 2712 2713 /* mask all PCI interrupts */ 2714 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000); 2715 2716 ctlr->allocate = ata_marvell_edma_allocate; 2717 ctlr->reset = ata_marvell_edma_reset; 2718 ctlr->dmainit = ata_marvell_edma_dmainit; 2719 ctlr->setmode = ata_sata_setmode; 2720 ctlr->channels = ctlr->chip->cfg1; 2721 2722 /* clear host controller interrupts */ 2723 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000); 2724 if (ctlr->chip->cfg1 > 4) 2725 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000); 2726 2727 /* clear PCI interrupts */ 2728 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000); 2729 2730 /* unmask PCI interrupts we want */ 2731 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff); 2732 2733 /* unmask host controller interrupts we want */ 2734 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ | 2735 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25)); 2736 2737 /* enable PCI interrupt */ 2738 pci_write_config(dev, PCIR_COMMAND, 2739 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 2740 return 0; 2741 } 2742 2743 static int 2744 ata_marvell_edma_allocate(device_t dev) 2745 { 2746 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2747 struct ata_channel *ch = device_get_softc(dev); 2748 u_int64_t work = ch->dma->work_bus; 2749 int i; 2750 2751 /* clear work area */ 2752 bzero(ch->dma->work, 1024+256); 2753 2754 /* set legacy ATA resources */ 2755 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 2756 ch->r_io[i].res = ctlr->r_res1; 2757 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch); 2758 } 2759 ch->r_io[ATA_CONTROL].res = ctlr->r_res1; 2760 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch); 2761 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1; 2762 ata_default_registers(dev); 2763 2764 /* set SATA resources */ 2765 switch (ctlr->chip->cfg2) { 2766 case MV50XX: 2767 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2768 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch); 2769 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2770 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch); 2771 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2772 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch); 2773 break; 2774 case MV60XX: 2775 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2776 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch); 2777 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2778 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch); 2779 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2780 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch); 2781 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1; 2782 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch); 2783 break; 2784 } 2785 2786 ch->flags |= ATA_NO_SLAVE; 2787 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */ 2788 ata_generic_hw(dev); 2789 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction; 2790 ch->hw.end_transaction = ata_marvell_edma_end_transaction; 2791 ch->hw.status = ata_marvell_edma_status; 2792 2793 /* disable the EDMA machinery */ 2794 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2795 DELAY(100000); /* SOS should poll for disabled */ 2796 2797 /* set configuration to non-queued 128b read transfers stop on error */ 2798 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13)); 2799 2800 /* request queue base high */ 2801 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32); 2802 2803 /* request queue in ptr */ 2804 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2805 2806 /* request queue out ptr */ 2807 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0); 2808 2809 /* response queue base high */ 2810 work += 1024; 2811 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32); 2812 2813 /* response queue in ptr */ 2814 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0); 2815 2816 /* response queue out ptr */ 2817 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2818 2819 /* clear SATA error register */ 2820 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 2821 2822 /* clear any outstanding error interrupts */ 2823 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2824 2825 /* unmask all error interrupts */ 2826 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 2827 2828 /* enable EDMA machinery */ 2829 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2830 return 0; 2831 } 2832 2833 static int 2834 ata_marvell_edma_status(device_t dev) 2835 { 2836 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2837 struct ata_channel *ch = device_get_softc(dev); 2838 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60); 2839 int shift = (ch->unit << 1) + (ch->unit > 3); 2840 2841 if (cause & (1 << shift)) { 2842 2843 /* clear interrupt(s) */ 2844 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2845 2846 /* do we have any PHY events ? */ 2847 ata_sata_phy_check_events(dev); 2848 } 2849 2850 /* do we have any device action ? */ 2851 return (cause & (2 << shift)); 2852 } 2853 2854 /* must be called with ATA channel locked and state_mtx held */ 2855 static int 2856 ata_marvell_edma_begin_transaction(struct ata_request *request) 2857 { 2858 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2859 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2860 u_int32_t req_in; 2861 u_int8_t *bytep; 2862 u_int16_t *wordp; 2863 u_int32_t *quadp; 2864 int i, tag = 0x07; 2865 int dummy, error, slot; 2866 2867 /* only DMA R/W goes through the EMDA machine */ 2868 if (request->u.ata.command != ATA_READ_DMA && 2869 request->u.ata.command != ATA_WRITE_DMA) { 2870 2871 /* disable the EDMA machinery */ 2872 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001) 2873 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2874 return ata_begin_transaction(request); 2875 } 2876 2877 /* check for 48 bit access and convert if needed */ 2878 ata_modify_if_48bit(request); 2879 2880 /* check sanity, setup SG list and DMA engine */ 2881 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 2882 request->flags & ATA_R_READ, ch->dma->sg, 2883 &dummy))) { 2884 device_printf(request->dev, "setting up DMA failed\n"); 2885 request->result = error; 2886 return ATA_OP_FINISHED; 2887 } 2888 2889 /* get next free request queue slot */ 2890 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch)); 2891 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f; 2892 bytep = (u_int8_t *)(ch->dma->work); 2893 bytep += (slot << 5); 2894 wordp = (u_int16_t *)bytep; 2895 quadp = (u_int32_t *)bytep; 2896 2897 /* fill in this request */ 2898 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff; 2899 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32; 2900 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1); 2901 2902 i = 10; 2903 bytep[i++] = (request->u.ata.count >> 8) & 0xff; 2904 bytep[i++] = 0x10 | ATA_COUNT; 2905 bytep[i++] = request->u.ata.count & 0xff; 2906 bytep[i++] = 0x10 | ATA_COUNT; 2907 2908 bytep[i++] = (request->u.ata.lba >> 24) & 0xff; 2909 bytep[i++] = 0x10 | ATA_SECTOR; 2910 bytep[i++] = request->u.ata.lba & 0xff; 2911 bytep[i++] = 0x10 | ATA_SECTOR; 2912 2913 bytep[i++] = (request->u.ata.lba >> 32) & 0xff; 2914 bytep[i++] = 0x10 | ATA_CYL_LSB; 2915 bytep[i++] = (request->u.ata.lba >> 8) & 0xff; 2916 bytep[i++] = 0x10 | ATA_CYL_LSB; 2917 2918 bytep[i++] = (request->u.ata.lba >> 40) & 0xff; 2919 bytep[i++] = 0x10 | ATA_CYL_MSB; 2920 bytep[i++] = (request->u.ata.lba >> 16) & 0xff; 2921 bytep[i++] = 0x10 | ATA_CYL_MSB; 2922 2923 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf); 2924 bytep[i++] = 0x10 | ATA_DRIVE; 2925 2926 bytep[i++] = request->u.ata.command; 2927 bytep[i++] = 0x90 | ATA_COMMAND; 2928 2929 /* enable EDMA machinery if needed */ 2930 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) { 2931 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2932 while (!(ATA_INL(ctlr->r_res1, 2933 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 2934 DELAY(10); 2935 } 2936 2937 /* tell EDMA it has a new request */ 2938 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f; 2939 req_in &= 0xfffffc00; 2940 req_in += (slot << 5); 2941 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in); 2942 2943 return ATA_OP_CONTINUES; 2944 } 2945 2946 /* must be called with ATA channel locked and state_mtx held */ 2947 static int 2948 ata_marvell_edma_end_transaction(struct ata_request *request) 2949 { 2950 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2951 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2952 int offset = (ch->unit > 3 ? 0x30014 : 0x20014); 2953 u_int32_t icr = ATA_INL(ctlr->r_res1, offset); 2954 int res; 2955 2956 /* EDMA interrupt */ 2957 if ((icr & (0x0001 << (ch->unit & 3)))) { 2958 struct ata_marvell_response *response; 2959 u_int32_t rsp_in, rsp_out; 2960 int slot; 2961 2962 /* stop timeout */ 2963 callout_stop(&request->callout); 2964 2965 /* get response ptr's */ 2966 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch)); 2967 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch)); 2968 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f; 2969 rsp_out &= 0xffffff00; 2970 rsp_out += (slot << 3); 2971 response = (struct ata_marvell_response *) 2972 (ch->dma->work + 1024 + (slot << 3)); 2973 2974 /* record status for this request */ 2975 request->status = response->dev_status; 2976 request->error = 0; 2977 2978 /* ack response */ 2979 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out); 2980 2981 /* update progress */ 2982 if (!(request->status & ATA_S_ERROR) && 2983 !(request->flags & ATA_R_TIMEOUT)) 2984 request->donecount = request->bytecount; 2985 2986 /* unload SG list */ 2987 ch->dma->unload(ch->dev); 2988 2989 res = ATA_OP_FINISHED; 2990 } 2991 2992 /* legacy ATA interrupt */ 2993 else { 2994 res = ata_end_transaction(request); 2995 } 2996 2997 /* ack interrupt */ 2998 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3)))); 2999 return res; 3000 } 3001 3002 static void 3003 ata_marvell_edma_reset(device_t dev) 3004 { 3005 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3006 struct ata_channel *ch = device_get_softc(dev); 3007 3008 /* disable the EDMA machinery */ 3009 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 3010 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 3011 DELAY(10); 3012 3013 /* clear SATA error register */ 3014 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 3015 3016 /* clear any outstanding error interrupts */ 3017 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 3018 3019 /* unmask all error interrupts */ 3020 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 3021 3022 /* enable channel and test for devices */ 3023 if (ata_sata_phy_reset(dev)) 3024 ata_generic_reset(dev); 3025 3026 /* enable EDMA machinery */ 3027 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 3028 } 3029 3030 static void 3031 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, 3032 int error) 3033 { 3034 struct ata_dmasetprd_args *args = xsc; 3035 struct ata_marvell_dma_prdentry *prd = args->dmatab; 3036 int i; 3037 3038 if ((args->error = error)) 3039 return; 3040 3041 for (i = 0; i < nsegs; i++) { 3042 prd[i].addrlo = htole32(segs[i].ds_addr); 3043 prd[i].count = htole32(segs[i].ds_len); 3044 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32); 3045 } 3046 prd[i - 1].count |= htole32(ATA_DMA_EOT); 3047 } 3048 3049 static void 3050 ata_marvell_edma_dmainit(device_t dev) 3051 { 3052 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3053 struct ata_channel *ch = device_get_softc(dev); 3054 3055 ata_dmainit(dev); 3056 if (ch->dma) { 3057 /* note start and stop are not used here */ 3058 ch->dma->setprd = ata_marvell_edma_dmasetprd; 3059 3060 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004) 3061 ch->dma->max_address = BUS_SPACE_MAXADDR; 3062 3063 /* chip does not reliably do 64K DMA transfers */ 3064 ch->dma->max_iosize = 126 * DEV_BSIZE; 3065 } 3066 } 3067 3068 3069 /* 3070 * National chipset support functions 3071 */ 3072 int 3073 ata_national_ident(device_t dev) 3074 { 3075 struct ata_pci_controller *ctlr = device_get_softc(dev); 3076 3077 /* this chip is a clone of the Cyrix chip, bugs and all */ 3078 if (pci_get_devid(dev) == ATA_SC1100) { 3079 device_set_desc(dev, "National Geode SC1100 ATA33 controller"); 3080 ctlr->chipinit = ata_national_chipinit; 3081 return 0; 3082 } 3083 return ENXIO; 3084 } 3085 3086 static int 3087 ata_national_chipinit(device_t dev) 3088 { 3089 struct ata_pci_controller *ctlr = device_get_softc(dev); 3090 3091 if (ata_setup_interrupt(dev)) 3092 return ENXIO; 3093 3094 ctlr->setmode = ata_national_setmode; 3095 return 0; 3096 } 3097 3098 static void 3099 ata_national_setmode(device_t dev, int mode) 3100 { 3101 device_t gparent = GRANDPARENT(dev); 3102 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3103 struct ata_device *atadev = device_get_softc(dev); 3104 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3105 u_int32_t piotiming[] = 3106 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010, 3107 0x00803020, 0x20102010, 0x00100010, 3108 0x00100010, 0x00100010, 0x00100010 }; 3109 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 }; 3110 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 }; 3111 int error; 3112 3113 ch->dma->alignment = 16; 3114 ch->dma->max_iosize = 126 * DEV_BSIZE; 3115 3116 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 3117 3118 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3119 3120 if (bootverbose) 3121 device_printf(dev, "%s setting %s on National chip\n", 3122 (error) ? "failed" : "success", ata_mode2str(mode)); 3123 if (!error) { 3124 if (mode >= ATA_UDMA0) { 3125 pci_write_config(gparent, 0x44 + (devno << 3), 3126 udmatiming[mode & ATA_MODE_MASK], 4); 3127 } 3128 else if (mode >= ATA_WDMA0) { 3129 pci_write_config(gparent, 0x44 + (devno << 3), 3130 dmatiming[mode & ATA_MODE_MASK], 4); 3131 } 3132 else { 3133 pci_write_config(gparent, 0x44 + (devno << 3), 3134 pci_read_config(gparent, 0x44 + (devno << 3), 4) | 3135 0x80000000, 4); 3136 } 3137 pci_write_config(gparent, 0x40 + (devno << 3), 3138 piotiming[ata_mode2idx(mode)], 4); 3139 atadev->mode = mode; 3140 } 3141 } 3142 3143 /* 3144 * NetCell chipset support functions 3145 */ 3146 int 3147 ata_netcell_ident(device_t dev) 3148 { 3149 struct ata_pci_controller *ctlr = device_get_softc(dev); 3150 3151 if (pci_get_devid(dev) == ATA_NETCELL_SR) { 3152 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller"); 3153 ctlr->chipinit = ata_netcell_chipinit; 3154 return 0; 3155 } 3156 return ENXIO; 3157 } 3158 3159 static int 3160 ata_netcell_chipinit(device_t dev) 3161 { 3162 struct ata_pci_controller *ctlr = device_get_softc(dev); 3163 3164 if (ata_generic_chipinit(dev)) 3165 return ENXIO; 3166 3167 ctlr->allocate = ata_netcell_allocate; 3168 return 0; 3169 } 3170 3171 static int 3172 ata_netcell_allocate(device_t dev) 3173 { 3174 struct ata_channel *ch = device_get_softc(dev); 3175 3176 /* setup the usual register normal pci style */ 3177 if (ata_pci_allocate(dev)) 3178 return ENXIO; 3179 3180 /* the NetCell only supports 16 bit PIO transfers */ 3181 ch->flags |= ATA_USE_16BIT; 3182 3183 return 0; 3184 } 3185 3186 3187 /* 3188 * nVidia chipset support functions 3189 */ 3190 int 3191 ata_nvidia_ident(device_t dev) 3192 { 3193 struct ata_pci_controller *ctlr = device_get_softc(dev); 3194 struct ata_chip_id *idx; 3195 static struct ata_chip_id ids[] = 3196 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" }, 3197 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" }, 3198 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" }, 3199 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" }, 3200 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" }, 3201 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" }, 3202 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3203 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3204 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" }, 3205 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3206 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3207 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" }, 3208 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3209 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3210 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" }, 3211 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3212 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3213 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" }, 3214 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3215 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3216 { ATA_NFORCE_MCP61, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP61" }, 3217 { ATA_NFORCE_MCP61_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" }, 3218 { ATA_NFORCE_MCP61_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" }, 3219 { ATA_NFORCE_MCP61_S3, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" }, 3220 { ATA_NFORCE_MCP65, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP65" }, 3221 { ATA_NFORCE_MCP67, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP67" }, 3222 { ATA_NFORCE_MCP67_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP67" }, 3223 { ATA_NFORCE_MCP73, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP73" }, 3224 { ATA_NFORCE_MCP77, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP77" }, 3225 { 0, 0, 0, 0, 0, 0}} ; 3226 char buffer[64] ; 3227 3228 if (!(idx = ata_match_chip(dev, ids))) 3229 return ENXIO; 3230 3231 ksprintf(buffer, "nVidia %s %s controller", 3232 idx->text, ata_mode2str(idx->max_dma)); 3233 device_set_desc_copy(dev, buffer); 3234 ctlr->chip = idx; 3235 ctlr->chipinit = ata_nvidia_chipinit; 3236 return 0; 3237 } 3238 3239 static int 3240 ata_nvidia_chipinit(device_t dev) 3241 { 3242 struct ata_pci_controller *ctlr = device_get_softc(dev); 3243 3244 if (ata_setup_interrupt(dev)) 3245 return ENXIO; 3246 3247 if (ctlr->chip->max_dma >= ATA_SA150) { 3248 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1) 3249 ctlr->r_type2 = SYS_RES_IOPORT; 3250 else 3251 ctlr->r_type2 = SYS_RES_MEMORY; 3252 ctlr->r_rid2 = PCIR_BAR(5); 3253 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3254 &ctlr->r_rid2, RF_ACTIVE))) { 3255 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3256 3257 ctlr->allocate = ata_nvidia_allocate; 3258 ctlr->reset = ata_nvidia_reset; 3259 3260 /* enable control access */ 3261 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1); 3262 3263 if (ctlr->chip->cfg2 & NVQ) { 3264 /* clear interrupt status */ 3265 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff); 3266 3267 /* enable device and PHY state change interrupts */ 3268 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d); 3269 3270 /* disable NCQ support */ 3271 ATA_OUTL(ctlr->r_res2, 0x0400, 3272 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9); 3273 } 3274 else { 3275 /* clear interrupt status */ 3276 ATA_OUTB(ctlr->r_res2, offset, 0xff); 3277 3278 /* enable device and PHY state change interrupts */ 3279 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd); 3280 } 3281 3282 /* enable PCI interrupt */ 3283 pci_write_config(dev, PCIR_COMMAND, 3284 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 3285 3286 } 3287 ctlr->setmode = ata_sata_setmode; 3288 } 3289 else { 3290 /* disable prefetch, postwrite */ 3291 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1); 3292 ctlr->setmode = ata_via_family_setmode; 3293 } 3294 return 0; 3295 } 3296 3297 static int 3298 ata_nvidia_allocate(device_t dev) 3299 { 3300 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3301 struct ata_channel *ch = device_get_softc(dev); 3302 3303 /* setup the usual register normal pci style */ 3304 if (ata_pci_allocate(dev)) 3305 return ENXIO; 3306 3307 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3308 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6); 3309 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3310 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6); 3311 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3312 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6); 3313 3314 ch->hw.status = ata_nvidia_status; 3315 ch->flags |= ATA_NO_SLAVE; 3316 3317 return 0; 3318 } 3319 3320 static int 3321 ata_nvidia_status(device_t dev) 3322 { 3323 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3324 struct ata_channel *ch = device_get_softc(dev); 3325 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3326 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2); 3327 u_int32_t istatus; 3328 3329 /* get interrupt status */ 3330 if (ctlr->chip->cfg2 & NVQ) 3331 istatus = ATA_INL(ctlr->r_res2, offset); 3332 else 3333 istatus = ATA_INB(ctlr->r_res2, offset); 3334 3335 /* do we have any PHY events ? */ 3336 if (istatus & (0x0c << shift)) 3337 ata_sata_phy_check_events(dev); 3338 3339 /* clear interrupt(s) */ 3340 if (ctlr->chip->cfg2 & NVQ) 3341 ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0); 3342 else 3343 ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift)); 3344 3345 /* do we have any device action ? */ 3346 return (istatus & (0x01 << shift)); 3347 } 3348 3349 static void 3350 ata_nvidia_reset(device_t dev) 3351 { 3352 if (ata_sata_phy_reset(dev)) 3353 ata_generic_reset(dev); 3354 } 3355 3356 3357 /* 3358 * Promise chipset support functions 3359 */ 3360 #define ATA_PDC_APKT_OFFSET 0x00000010 3361 #define ATA_PDC_HPKT_OFFSET 0x00000040 3362 #define ATA_PDC_ASG_OFFSET 0x00000080 3363 #define ATA_PDC_LSG_OFFSET 0x000000c0 3364 #define ATA_PDC_HSG_OFFSET 0x00000100 3365 #define ATA_PDC_CHN_OFFSET 0x00000400 3366 #define ATA_PDC_BUF_BASE 0x00400000 3367 #define ATA_PDC_BUF_OFFSET 0x00100000 3368 #define ATA_PDC_MAX_HPKT 8 3369 #define ATA_PDC_WRITE_REG 0x00 3370 #define ATA_PDC_WRITE_CTL 0x0e 3371 #define ATA_PDC_WRITE_END 0x08 3372 #define ATA_PDC_WAIT_NBUSY 0x10 3373 #define ATA_PDC_WAIT_READY 0x18 3374 #define ATA_PDC_1B 0x20 3375 #define ATA_PDC_2B 0x40 3376 3377 struct host_packet { 3378 u_int32_t addr; 3379 TAILQ_ENTRY(host_packet) chain; 3380 }; 3381 3382 struct ata_promise_sx4 { 3383 struct spinlock mtx; 3384 TAILQ_HEAD(, host_packet) queue; 3385 int busy; 3386 }; 3387 3388 int 3389 ata_promise_ident(device_t dev) 3390 { 3391 struct ata_pci_controller *ctlr = device_get_softc(dev); 3392 struct ata_chip_id *idx; 3393 static struct ata_chip_id ids[] = 3394 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" }, 3395 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" }, 3396 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" }, 3397 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" }, 3398 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" }, 3399 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" }, 3400 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" }, 3401 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" }, 3402 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" }, 3403 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" }, 3404 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" }, 3405 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" }, 3406 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" }, 3407 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" }, 3408 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" }, 3409 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" }, 3410 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" }, 3411 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" }, 3412 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" }, 3413 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" }, 3414 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" }, 3415 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" }, 3416 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" }, 3417 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" }, 3418 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" }, 3419 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" }, 3420 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" }, 3421 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" }, 3422 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" }, 3423 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" }, 3424 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" }, 3425 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" }, 3426 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" }, 3427 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" }, 3428 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" }, 3429 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" }, 3430 { 0, 0, 0, 0, 0, 0}}; 3431 char buffer[64]; 3432 uintptr_t devid = 0; 3433 3434 if (!(idx = ata_match_chip(dev, ids))) 3435 return ENXIO; 3436 3437 /* if we are on a SuperTrak SX6000 dont attach */ 3438 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3439 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3440 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3441 devid == ATA_I960RM) 3442 return ENXIO; 3443 3444 strcpy(buffer, "Promise "); 3445 strcat(buffer, idx->text); 3446 3447 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 3448 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3449 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3450 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3451 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 3452 static long start = 0, end = 0; 3453 3454 if (pci_get_slot(dev) == 1) { 3455 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 3456 strcat(buffer, " (channel 0+1)"); 3457 } 3458 else if (pci_get_slot(dev) == 2 && start && end) { 3459 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 3460 strcat(buffer, " (channel 2+3)"); 3461 } 3462 else { 3463 start = end = 0; 3464 } 3465 } 3466 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 3467 device_set_desc_copy(dev, buffer); 3468 ctlr->chip = idx; 3469 ctlr->chipinit = ata_promise_chipinit; 3470 return 0; 3471 } 3472 3473 static int 3474 ata_promise_chipinit(device_t dev) 3475 { 3476 struct ata_pci_controller *ctlr = device_get_softc(dev); 3477 int fake_reg, stat_reg; 3478 3479 if (ata_setup_interrupt(dev)) 3480 return ENXIO; 3481 3482 switch (ctlr->chip->cfg1) { 3483 case PRNEW: 3484 /* setup clocks */ 3485 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 3486 3487 ctlr->dmainit = ata_promise_dmainit; 3488 /* FALLTHROUGH */ 3489 3490 case PROLD: 3491 /* enable burst mode */ 3492 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 3493 ctlr->allocate = ata_promise_allocate; 3494 ctlr->setmode = ata_promise_setmode; 3495 return 0; 3496 3497 case PRTX: 3498 ctlr->allocate = ata_promise_tx2_allocate; 3499 ctlr->setmode = ata_promise_setmode; 3500 return 0; 3501 3502 case PRMIO: 3503 ctlr->r_type1 = SYS_RES_MEMORY; 3504 ctlr->r_rid1 = PCIR_BAR(4); 3505 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 3506 &ctlr->r_rid1, RF_ACTIVE))) 3507 goto failnfree; 3508 3509 ctlr->r_type2 = SYS_RES_MEMORY; 3510 ctlr->r_rid2 = PCIR_BAR(3); 3511 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3512 &ctlr->r_rid2, RF_ACTIVE))) 3513 goto failnfree; 3514 3515 if (ctlr->chip->cfg2 == PRSX4X) { 3516 struct ata_promise_sx4 *hpkt; 3517 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 3518 3519 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3520 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3521 ata_promise_sx4_intr, ctlr, &ctlr->handle, NULL)) { 3522 device_printf(dev, "unable to setup interrupt\n"); 3523 goto failnfree; 3524 } 3525 3526 /* print info about cache memory */ 3527 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 3528 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 3529 ((dimm >> 24) & 0xff), 3530 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 3531 " ECC enabled" : "" ); 3532 3533 /* adjust cache memory parameters */ 3534 ATA_OUTL(ctlr->r_res2, 0x000c000c, 3535 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 3536 3537 /* setup host packet controls */ 3538 hpkt = kmalloc(sizeof(struct ata_promise_sx4), 3539 M_TEMP, M_INTWAIT | M_ZERO); 3540 spin_init(&hpkt->mtx); 3541 TAILQ_INIT(&hpkt->queue); 3542 hpkt->busy = 0; 3543 device_set_ivars(dev, hpkt); 3544 ctlr->allocate = ata_promise_mio_allocate; 3545 ctlr->reset = ata_promise_mio_reset; 3546 ctlr->dmainit = ata_promise_mio_dmainit; 3547 ctlr->setmode = ata_promise_setmode; 3548 ctlr->channels = 4; 3549 return 0; 3550 } 3551 3552 /* mio type controllers need an interrupt intercept */ 3553 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3554 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3555 ata_promise_mio_intr, ctlr, &ctlr->handle, NULL)) { 3556 device_printf(dev, "unable to setup interrupt\n"); 3557 goto failnfree; 3558 } 3559 3560 switch (ctlr->chip->cfg2) { 3561 case PRPATA: 3562 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 3563 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 3564 goto sata150; 3565 case PRCMBO: 3566 ctlr->channels = 3; 3567 goto sata150; 3568 case PRSATA: 3569 ctlr->channels = 4; 3570 sata150: 3571 fake_reg = 0x60; 3572 stat_reg = 0x6c; 3573 break; 3574 3575 case PRCMBO2: 3576 ctlr->channels = 3; 3577 goto sataii; 3578 case PRSATA2: 3579 default: 3580 ctlr->channels = 4; 3581 sataii: 3582 fake_reg = 0x54; 3583 stat_reg = 0x60; 3584 break; 3585 } 3586 3587 /* prime fake interrupt register */ 3588 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3589 3590 /* clear SATA status */ 3591 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 3592 3593 ctlr->allocate = ata_promise_mio_allocate; 3594 ctlr->reset = ata_promise_mio_reset; 3595 ctlr->dmainit = ata_promise_mio_dmainit; 3596 ctlr->setmode = ata_promise_mio_setmode; 3597 3598 return 0; 3599 } 3600 3601 failnfree: 3602 if (ctlr->r_res2) 3603 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 3604 if (ctlr->r_res1) 3605 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 3606 return ENXIO; 3607 } 3608 3609 static int 3610 ata_promise_allocate(device_t dev) 3611 { 3612 struct ata_channel *ch = device_get_softc(dev); 3613 3614 if (ata_pci_allocate(dev)) 3615 return ENXIO; 3616 3617 ch->hw.status = ata_promise_status; 3618 return 0; 3619 } 3620 3621 static int 3622 ata_promise_status(device_t dev) 3623 { 3624 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3625 struct ata_channel *ch = device_get_softc(dev); 3626 3627 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 3628 return ata_pci_status(dev); 3629 } 3630 return 0; 3631 } 3632 3633 static int 3634 ata_promise_dmastart(device_t dev) 3635 { 3636 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3637 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3638 struct ata_device *atadev = device_get_softc(dev); 3639 3640 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3641 ATA_OUTB(ctlr->r_res1, 0x11, 3642 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 3643 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 3644 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) | 3645 (ch->dma->cur_iosize >> 1)); 3646 } 3647 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 3648 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 3649 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus); 3650 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3651 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) | 3652 ATA_BMCMD_START_STOP); 3653 ch->flags |= ATA_DMA_ACTIVE; 3654 return 0; 3655 } 3656 3657 static int 3658 ata_promise_dmastop(device_t dev) 3659 { 3660 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3661 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3662 struct ata_device *atadev = device_get_softc(dev); 3663 int error; 3664 3665 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3666 ATA_OUTB(ctlr->r_res1, 0x11, 3667 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 3668 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 3669 } 3670 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 3671 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3672 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3673 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3674 ch->flags &= ~ATA_DMA_ACTIVE; 3675 return error; 3676 } 3677 3678 static void 3679 ata_promise_dmareset(device_t dev) 3680 { 3681 struct ata_channel *ch = device_get_softc(dev); 3682 3683 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3684 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3685 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3686 ch->flags &= ~ATA_DMA_ACTIVE; 3687 } 3688 3689 static void 3690 ata_promise_dmainit(device_t dev) 3691 { 3692 struct ata_channel *ch = device_get_softc(dev); 3693 3694 ata_dmainit(dev); 3695 if (ch->dma) { 3696 ch->dma->start = ata_promise_dmastart; 3697 ch->dma->stop = ata_promise_dmastop; 3698 ch->dma->reset = ata_promise_dmareset; 3699 } 3700 } 3701 3702 static void 3703 ata_promise_setmode(device_t dev, int mode) 3704 { 3705 device_t gparent = GRANDPARENT(dev); 3706 struct ata_pci_controller *ctlr = device_get_softc(gparent); 3707 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3708 struct ata_device *atadev = device_get_softc(dev); 3709 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3710 int error; 3711 u_int32_t timings[][2] = { 3712 /* PROLD PRNEW mode */ 3713 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 3714 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 3715 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 3716 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 3717 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 3718 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 3719 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 3720 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 3721 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 3722 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 3723 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 3724 { 0, 0x00424ef6 }, /* UDMA 3 */ 3725 { 0, 0x004127f3 }, /* UDMA 4 */ 3726 { 0, 0x004127f3 } /* UDMA 5 */ 3727 }; 3728 3729 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 3730 3731 switch (ctlr->chip->cfg1) { 3732 case PROLD: 3733 case PRNEW: 3734 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) & 3735 (ch->unit ? 1 << 11 : 1 << 10))) { 3736 ata_print_cable(dev, "controller"); 3737 mode = ATA_UDMA2; 3738 } 3739 if (ata_atapi(dev) && mode > ATA_PIO_MAX) 3740 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 3741 break; 3742 3743 case PRTX: 3744 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3745 if (mode > ATA_UDMA2 && 3746 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 3747 ata_print_cable(dev, "controller"); 3748 mode = ATA_UDMA2; 3749 } 3750 break; 3751 3752 case PRMIO: 3753 if (mode > ATA_UDMA2 && 3754 (ATA_INL(ctlr->r_res2, 3755 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) + 3756 (ch->unit << 7)) & 0x01000000)) { 3757 ata_print_cable(dev, "controller"); 3758 mode = ATA_UDMA2; 3759 } 3760 break; 3761 } 3762 3763 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3764 3765 if (bootverbose) 3766 device_printf(dev, "%ssetting %s on %s chip\n", 3767 (error) ? "FAILURE " : "", 3768 ata_mode2str(mode), ctlr->chip->text); 3769 if (!error) { 3770 if (ctlr->chip->cfg1 < PRTX) 3771 pci_write_config(gparent, 0x60 + (devno << 2), 3772 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 3773 atadev->mode = mode; 3774 } 3775 return; 3776 } 3777 3778 static int 3779 ata_promise_tx2_allocate(device_t dev) 3780 { 3781 struct ata_channel *ch = device_get_softc(dev); 3782 3783 if (ata_pci_allocate(dev)) 3784 return ENXIO; 3785 3786 ch->hw.status = ata_promise_tx2_status; 3787 return 0; 3788 } 3789 3790 static int 3791 ata_promise_tx2_status(device_t dev) 3792 { 3793 struct ata_channel *ch = device_get_softc(dev); 3794 3795 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3796 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 3797 return ata_pci_status(dev); 3798 } 3799 return 0; 3800 } 3801 3802 static int 3803 ata_promise_mio_allocate(device_t dev) 3804 { 3805 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3806 struct ata_channel *ch = device_get_softc(dev); 3807 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0; 3808 int i; 3809 3810 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 3811 ch->r_io[i].res = ctlr->r_res2; 3812 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 3813 } 3814 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 3815 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 3816 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 3817 ata_default_registers(dev); 3818 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) || 3819 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) { 3820 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3821 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 3822 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3823 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 3824 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3825 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 3826 ch->flags |= ATA_NO_SLAVE; 3827 } 3828 ch->flags |= ATA_USE_16BIT; 3829 3830 ata_generic_hw(dev); 3831 if (ctlr->chip->cfg2 & PRSX4X) { 3832 ch->hw.command = ata_promise_sx4_command; 3833 } 3834 else { 3835 ch->hw.command = ata_promise_mio_command; 3836 ch->hw.status = ata_promise_mio_status; 3837 } 3838 return 0; 3839 } 3840 3841 static void 3842 ata_promise_mio_intr(void *data) 3843 { 3844 struct ata_pci_controller *ctlr = data; 3845 struct ata_channel *ch; 3846 u_int32_t vector; 3847 int unit, fake_reg; 3848 3849 switch (ctlr->chip->cfg2) { 3850 case PRPATA: 3851 case PRCMBO: 3852 case PRSATA: 3853 fake_reg = 0x60; 3854 break; 3855 case PRCMBO2: 3856 case PRSATA2: 3857 default: 3858 fake_reg = 0x54; 3859 break; 3860 } 3861 3862 /* 3863 * since reading interrupt status register on early "mio" chips 3864 * clears the status bits we cannot read it for each channel later on 3865 * in the generic interrupt routine. 3866 * store the bits in an unused register in the chip so we can read 3867 * it from there safely to get around this "feature". 3868 */ 3869 vector = ATA_INL(ctlr->r_res2, 0x040); 3870 ATA_OUTL(ctlr->r_res2, 0x040, vector); 3871 ATA_OUTL(ctlr->r_res2, fake_reg, vector); 3872 3873 for (unit = 0; unit < ctlr->channels; unit++) { 3874 if ((ch = ctlr->interrupt[unit].argument)) 3875 ctlr->interrupt[unit].function(ch); 3876 } 3877 3878 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3879 } 3880 3881 static int 3882 ata_promise_mio_status(device_t dev) 3883 { 3884 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3885 struct ata_channel *ch = device_get_softc(dev); 3886 struct ata_connect_task *tp; 3887 u_int32_t fake_reg, stat_reg, vector, status; 3888 3889 switch (ctlr->chip->cfg2) { 3890 case PRPATA: 3891 case PRCMBO: 3892 case PRSATA: 3893 fake_reg = 0x60; 3894 stat_reg = 0x6c; 3895 break; 3896 case PRCMBO2: 3897 case PRSATA2: 3898 default: 3899 fake_reg = 0x54; 3900 stat_reg = 0x60; 3901 break; 3902 } 3903 3904 /* read and acknowledge interrupt */ 3905 vector = ATA_INL(ctlr->r_res2, fake_reg); 3906 3907 /* read and clear interface status */ 3908 status = ATA_INL(ctlr->r_res2, stat_reg); 3909 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 3910 3911 /* check for and handle disconnect events */ 3912 if ((status & (0x00000001 << ch->unit)) && 3913 (tp = (struct ata_connect_task *) 3914 kmalloc(sizeof(struct ata_connect_task), 3915 M_ATA, M_INTWAIT | M_ZERO))) { 3916 3917 if (bootverbose) 3918 device_printf(ch->dev, "DISCONNECT requested\n"); 3919 tp->action = ATA_C_DETACH; 3920 tp->dev = ch->dev; 3921 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3922 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3923 } 3924 3925 /* check for and handle connect events */ 3926 if ((status & (0x00000010 << ch->unit)) && 3927 (tp = (struct ata_connect_task *) 3928 kmalloc(sizeof(struct ata_connect_task), 3929 M_ATA, M_INTWAIT | M_ZERO))) { 3930 3931 if (bootverbose) 3932 device_printf(ch->dev, "CONNECT requested\n"); 3933 tp->action = ATA_C_ATTACH; 3934 tp->dev = ch->dev; 3935 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3936 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3937 } 3938 3939 /* do we have any device action ? */ 3940 return (vector & (1 << (ch->unit + 1))); 3941 } 3942 3943 static int 3944 ata_promise_mio_command(struct ata_request *request) 3945 { 3946 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 3947 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 3948 u_int32_t *wordp = (u_int32_t *)ch->dma->work; 3949 3950 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 3951 3952 /* XXX SOS add ATAPI commands support later */ 3953 switch (request->u.ata.command) { 3954 default: 3955 return ata_generic_command(request); 3956 3957 case ATA_READ_DMA: 3958 case ATA_READ_DMA48: 3959 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3960 break; 3961 3962 case ATA_WRITE_DMA: 3963 case ATA_WRITE_DMA48: 3964 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3965 break; 3966 } 3967 wordp[1] = htole32(ch->dma->sg_bus); 3968 wordp[2] = 0; 3969 ata_promise_apkt((u_int8_t*)wordp, request); 3970 3971 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus); 3972 return 0; 3973 } 3974 3975 static void 3976 ata_promise_mio_reset(device_t dev) 3977 { 3978 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3979 struct ata_channel *ch = device_get_softc(dev); 3980 struct ata_promise_sx4 *hpktp; 3981 3982 switch (ctlr->chip->cfg2) { 3983 case PRSX4X: 3984 3985 /* softreset channel ATA module */ 3986 hpktp = device_get_ivars(ctlr->dev); 3987 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 3988 ata_udelay(1000); 3989 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 3990 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 3991 ~0x00003f9f) | (ch->unit + 1)); 3992 3993 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 3994 spin_lock_wr(&hpktp->mtx); 3995 ATA_OUTL(ctlr->r_res2, 0xc012c, 3996 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 3997 DELAY(10); 3998 ATA_OUTL(ctlr->r_res2, 0xc012c, 3999 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 4000 hpktp->busy = 0; 4001 spin_unlock_wr(&hpktp->mtx); 4002 ata_generic_reset(dev); 4003 break; 4004 4005 case PRPATA: 4006 case PRCMBO: 4007 case PRSATA: 4008 if ((ctlr->chip->cfg2 == PRSATA) || 4009 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 4010 4011 /* mask plug/unplug intr */ 4012 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 4013 } 4014 4015 /* softreset channels ATA module */ 4016 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 4017 ata_udelay(10000); 4018 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 4019 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 4020 ~0x00003f9f) | (ch->unit + 1)); 4021 4022 if ((ctlr->chip->cfg2 == PRSATA) || 4023 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 4024 4025 if (ata_sata_phy_reset(dev)) 4026 ata_generic_reset(dev); 4027 4028 /* reset and enable plug/unplug intr */ 4029 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 4030 } 4031 else 4032 ata_generic_reset(dev); 4033 break; 4034 4035 case PRCMBO2: 4036 case PRSATA2: 4037 if ((ctlr->chip->cfg2 == PRSATA2) || 4038 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 4039 /* set portmultiplier port */ 4040 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 4041 4042 /* mask plug/unplug intr */ 4043 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 4044 } 4045 4046 /* softreset channels ATA module */ 4047 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 4048 ata_udelay(10000); 4049 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 4050 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 4051 ~0x00003f9f) | (ch->unit + 1)); 4052 4053 if ((ctlr->chip->cfg2 == PRSATA2) || 4054 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 4055 4056 /* set PHY mode to "improved" */ 4057 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 4058 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 4059 ~0x00000003) | 0x00000001); 4060 4061 if (ata_sata_phy_reset(dev)) 4062 ata_generic_reset(dev); 4063 4064 /* reset and enable plug/unplug intr */ 4065 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 4066 4067 /* set portmultiplier port */ 4068 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 4069 } 4070 else 4071 ata_generic_reset(dev); 4072 break; 4073 4074 } 4075 } 4076 4077 static void 4078 ata_promise_mio_dmainit(device_t dev) 4079 { 4080 /* note start and stop are not used here */ 4081 ata_dmainit(dev); 4082 } 4083 4084 static void 4085 ata_promise_mio_setmode(device_t dev, int mode) 4086 { 4087 device_t gparent = GRANDPARENT(dev); 4088 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4089 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4090 4091 if ( (ctlr->chip->cfg2 == PRSATA) || 4092 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) || 4093 (ctlr->chip->cfg2 == PRSATA2) || 4094 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) 4095 ata_sata_setmode(dev, mode); 4096 else 4097 ata_promise_setmode(dev, mode); 4098 } 4099 4100 static void 4101 ata_promise_sx4_intr(void *data) 4102 { 4103 struct ata_pci_controller *ctlr = data; 4104 struct ata_channel *ch; 4105 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 4106 int unit; 4107 4108 for (unit = 0; unit < ctlr->channels; unit++) { 4109 if (vector & (1 << (unit + 1))) 4110 if ((ch = ctlr->interrupt[unit].argument)) 4111 ctlr->interrupt[unit].function(ch); 4112 if (vector & (1 << (unit + 5))) 4113 if ((ch = ctlr->interrupt[unit].argument)) 4114 ata_promise_queue_hpkt(ctlr, 4115 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 4116 ATA_PDC_HPKT_OFFSET)); 4117 if (vector & (1 << (unit + 9))) { 4118 ata_promise_next_hpkt(ctlr); 4119 if ((ch = ctlr->interrupt[unit].argument)) 4120 ctlr->interrupt[unit].function(ch); 4121 } 4122 if (vector & (1 << (unit + 13))) { 4123 ata_promise_next_hpkt(ctlr); 4124 if ((ch = ctlr->interrupt[unit].argument)) 4125 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4126 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 4127 ATA_PDC_APKT_OFFSET)); 4128 } 4129 } 4130 } 4131 4132 static int 4133 ata_promise_sx4_command(struct ata_request *request) 4134 { 4135 device_t gparent = GRANDPARENT(request->dev); 4136 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4137 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4138 struct ata_dma_prdentry *prd = ch->dma->sg; 4139 caddr_t window = rman_get_virtual(ctlr->r_res1); 4140 u_int32_t *wordp; 4141 int i, idx, length = 0; 4142 4143 /* XXX SOS add ATAPI commands support later */ 4144 switch (request->u.ata.command) { 4145 4146 default: 4147 return -1; 4148 4149 case ATA_ATA_IDENTIFY: 4150 case ATA_READ: 4151 case ATA_READ48: 4152 case ATA_READ_MUL: 4153 case ATA_READ_MUL48: 4154 case ATA_WRITE: 4155 case ATA_WRITE48: 4156 case ATA_WRITE_MUL: 4157 case ATA_WRITE_MUL48: 4158 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4159 return ata_generic_command(request); 4160 4161 case ATA_SETFEATURES: 4162 case ATA_FLUSHCACHE: 4163 case ATA_FLUSHCACHE48: 4164 case ATA_SLEEP: 4165 case ATA_SET_MULTI: 4166 wordp = (u_int32_t *) 4167 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4168 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 4169 wordp[1] = 0; 4170 wordp[2] = 0; 4171 ata_promise_apkt((u_int8_t *)wordp, request); 4172 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4173 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4174 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4175 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 4176 return 0; 4177 4178 case ATA_READ_DMA: 4179 case ATA_READ_DMA48: 4180 case ATA_WRITE_DMA: 4181 case ATA_WRITE_DMA48: 4182 wordp = (u_int32_t *) 4183 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 4184 i = idx = 0; 4185 do { 4186 wordp[idx++] = prd[i].addr; 4187 wordp[idx++] = prd[i].count; 4188 length += (prd[i].count & ~ATA_DMA_EOT); 4189 } while (!(prd[i++].count & ATA_DMA_EOT)); 4190 4191 wordp = (u_int32_t *) 4192 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 4193 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4194 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4195 4196 wordp = (u_int32_t *) 4197 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 4198 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4199 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4200 4201 wordp = (u_int32_t *) 4202 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 4203 if (request->flags & ATA_R_READ) 4204 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 4205 if (request->flags & ATA_R_WRITE) 4206 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 4207 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 4208 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 4209 wordp[3] = 0; 4210 4211 wordp = (u_int32_t *) 4212 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4213 if (request->flags & ATA_R_READ) 4214 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 4215 if (request->flags & ATA_R_WRITE) 4216 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 4217 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 4218 wordp[2] = 0; 4219 ata_promise_apkt((u_int8_t *)wordp, request); 4220 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4221 4222 if (request->flags & ATA_R_READ) { 4223 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 4224 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 4225 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4226 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 4227 } 4228 if (request->flags & ATA_R_WRITE) { 4229 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 4230 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 4231 ata_promise_queue_hpkt(ctlr, 4232 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 4233 } 4234 return 0; 4235 } 4236 } 4237 4238 static int 4239 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 4240 { 4241 struct ata_device *atadev = device_get_softc(request->dev); 4242 int i = 12; 4243 4244 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 4245 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit; 4246 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 4247 bytep[i++] = ATA_A_4BIT; 4248 4249 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 4250 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4251 bytep[i++] = request->u.ata.feature >> 8; 4252 bytep[i++] = request->u.ata.feature; 4253 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 4254 bytep[i++] = request->u.ata.count >> 8; 4255 bytep[i++] = request->u.ata.count; 4256 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4257 bytep[i++] = request->u.ata.lba >> 24; 4258 bytep[i++] = request->u.ata.lba; 4259 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4260 bytep[i++] = request->u.ata.lba >> 32; 4261 bytep[i++] = request->u.ata.lba >> 8; 4262 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4263 bytep[i++] = request->u.ata.lba >> 40; 4264 bytep[i++] = request->u.ata.lba >> 16; 4265 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4266 bytep[i++] = ATA_D_LBA | atadev->unit; 4267 } 4268 else { 4269 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4270 bytep[i++] = request->u.ata.feature; 4271 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 4272 bytep[i++] = request->u.ata.count; 4273 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4274 bytep[i++] = request->u.ata.lba; 4275 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4276 bytep[i++] = request->u.ata.lba >> 8; 4277 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4278 bytep[i++] = request->u.ata.lba >> 16; 4279 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4280 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) | 4281 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf); 4282 } 4283 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 4284 bytep[i++] = request->u.ata.command; 4285 return i; 4286 } 4287 4288 static void 4289 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 4290 { 4291 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4292 4293 spin_lock_wr(&hpktp->mtx); 4294 if (hpktp->busy) { 4295 struct host_packet *hp = 4296 kmalloc(sizeof(struct host_packet), M_TEMP, M_INTWAIT | M_ZERO); 4297 hp->addr = hpkt; 4298 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 4299 } 4300 else { 4301 hpktp->busy = 1; 4302 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 4303 } 4304 spin_unlock_wr(&hpktp->mtx); 4305 } 4306 4307 static void 4308 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 4309 { 4310 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4311 struct host_packet *hp; 4312 4313 spin_lock_wr(&hpktp->mtx); 4314 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 4315 TAILQ_REMOVE(&hpktp->queue, hp, chain); 4316 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 4317 kfree(hp, M_TEMP); 4318 } 4319 else 4320 hpktp->busy = 0; 4321 spin_unlock_wr(&hpktp->mtx); 4322 } 4323 4324 4325 /* 4326 * ServerWorks chipset support functions 4327 */ 4328 int 4329 ata_serverworks_ident(device_t dev) 4330 { 4331 struct ata_pci_controller *ctlr = device_get_softc(dev); 4332 struct ata_chip_id *idx; 4333 static struct ata_chip_id ids[] = 4334 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" }, 4335 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" }, 4336 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" }, 4337 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" }, 4338 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" }, 4339 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" }, 4340 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" }, 4341 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" }, 4342 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" }, 4343 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" }, 4344 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" }, 4345 { 0, 0, 0, 0, 0, 0}}; 4346 char buffer[64]; 4347 4348 if (!(idx = ata_match_chip(dev, ids))) 4349 return ENXIO; 4350 4351 ksprintf(buffer, "ServerWorks %s %s controller", 4352 idx->text, ata_mode2str(idx->max_dma)); 4353 device_set_desc_copy(dev, buffer); 4354 ctlr->chip = idx; 4355 ctlr->chipinit = ata_serverworks_chipinit; 4356 return 0; 4357 } 4358 4359 static int 4360 ata_serverworks_chipinit(device_t dev) 4361 { 4362 struct ata_pci_controller *ctlr = device_get_softc(dev); 4363 4364 if (ata_setup_interrupt(dev)) 4365 return ENXIO; 4366 4367 if (ctlr->chip->cfg1 == SWKSMIO) { 4368 ctlr->r_type2 = SYS_RES_MEMORY; 4369 ctlr->r_rid2 = PCIR_BAR(5); 4370 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4371 &ctlr->r_rid2, RF_ACTIVE))) 4372 return ENXIO; 4373 4374 ctlr->channels = ctlr->chip->cfg2; 4375 ctlr->allocate = ata_serverworks_allocate; 4376 ctlr->setmode = ata_sata_setmode; 4377 return 0; 4378 } 4379 else if (ctlr->chip->cfg1 == SWKS33) { 4380 device_t *children; 4381 int nchildren, i; 4382 4383 /* locate the ISA part in the southbridge and enable UDMA33 */ 4384 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 4385 for (i = 0; i < nchildren; i++) { 4386 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 4387 pci_write_config(children[i], 0x64, 4388 (pci_read_config(children[i], 0x64, 4) & 4389 ~0x00002000) | 0x00004000, 4); 4390 break; 4391 } 4392 } 4393 kfree(children, M_TEMP); 4394 } 4395 } 4396 else { 4397 pci_write_config(dev, 0x5a, 4398 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 4399 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1); 4400 } 4401 ctlr->setmode = ata_serverworks_setmode; 4402 return 0; 4403 } 4404 4405 static int 4406 ata_serverworks_allocate(device_t dev) 4407 { 4408 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4409 struct ata_channel *ch = device_get_softc(dev); 4410 int ch_offset; 4411 int i; 4412 4413 ch_offset = ch->unit * 0x100; 4414 4415 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 4416 ch->r_io[i].res = ctlr->r_res2; 4417 4418 /* setup ATA registers */ 4419 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 4420 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 4421 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 4422 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 4423 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 4424 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 4425 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 4426 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 4427 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 4428 ata_default_registers(dev); 4429 4430 /* setup DMA registers */ 4431 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 4432 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 4433 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 4434 4435 /* setup SATA registers */ 4436 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 4437 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 4438 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 4439 4440 ch->flags |= ATA_NO_SLAVE; 4441 ata_pci_hw(dev); 4442 4443 /* chip does not reliably do 64K DMA transfers */ 4444 if (ch->dma) 4445 ch->dma->max_iosize = 126 * DEV_BSIZE; 4446 4447 return 0; 4448 } 4449 4450 static void 4451 ata_serverworks_setmode(device_t dev, int mode) 4452 { 4453 device_t gparent = GRANDPARENT(dev); 4454 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4455 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4456 struct ata_device *atadev = device_get_softc(dev); 4457 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4458 int offset = (devno ^ 0x01) << 3; 4459 int error; 4460 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 4461 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 4462 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 4463 4464 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4465 4466 mode = ata_check_80pin(dev, mode); 4467 4468 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4469 4470 if (bootverbose) 4471 device_printf(dev, "%ssetting %s on %s chip\n", 4472 (error) ? "FAILURE " : "", 4473 ata_mode2str(mode), ctlr->chip->text); 4474 if (!error) { 4475 if (mode >= ATA_UDMA0) { 4476 pci_write_config(gparent, 0x56, 4477 (pci_read_config(gparent, 0x56, 2) & 4478 ~(0xf << (devno << 2))) | 4479 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 4480 pci_write_config(gparent, 0x54, 4481 pci_read_config(gparent, 0x54, 1) | 4482 (0x01 << devno), 1); 4483 pci_write_config(gparent, 0x44, 4484 (pci_read_config(gparent, 0x44, 4) & 4485 ~(0xff << offset)) | 4486 (dmatimings[2] << offset), 4); 4487 } 4488 else if (mode >= ATA_WDMA0) { 4489 pci_write_config(gparent, 0x54, 4490 pci_read_config(gparent, 0x54, 1) & 4491 ~(0x01 << devno), 1); 4492 pci_write_config(gparent, 0x44, 4493 (pci_read_config(gparent, 0x44, 4) & 4494 ~(0xff << offset)) | 4495 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 4496 } 4497 else 4498 pci_write_config(gparent, 0x54, 4499 pci_read_config(gparent, 0x54, 1) & 4500 ~(0x01 << devno), 1); 4501 4502 pci_write_config(gparent, 0x40, 4503 (pci_read_config(gparent, 0x40, 4) & 4504 ~(0xff << offset)) | 4505 (piotimings[ata_mode2idx(mode)] << offset), 4); 4506 atadev->mode = mode; 4507 } 4508 } 4509 4510 4511 /* 4512 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 4513 */ 4514 int 4515 ata_sii_ident(device_t dev) 4516 { 4517 struct ata_pci_controller *ctlr = device_get_softc(dev); 4518 struct ata_chip_id *idx; 4519 static struct ata_chip_id ids[] = 4520 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" }, 4521 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" }, 4522 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4523 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4524 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" }, 4525 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4526 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4527 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" }, 4528 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" }, 4529 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" }, 4530 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" }, 4531 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" }, 4532 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" }, 4533 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" }, 4534 { 0, 0, 0, 0, 0, 0}}; 4535 char buffer[64]; 4536 4537 if (!(idx = ata_match_chip(dev, ids))) 4538 return ENXIO; 4539 4540 ksprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); 4541 device_set_desc_copy(dev, buffer); 4542 ctlr->chip = idx; 4543 ctlr->chipinit = ata_sii_chipinit; 4544 return 0; 4545 } 4546 4547 static int 4548 ata_sii_chipinit(device_t dev) 4549 { 4550 struct ata_pci_controller *ctlr = device_get_softc(dev); 4551 4552 if (ata_setup_interrupt(dev)) 4553 return ENXIO; 4554 4555 switch (ctlr->chip->cfg1) { 4556 case SIIPRBIO: 4557 ctlr->r_type1 = SYS_RES_MEMORY; 4558 ctlr->r_rid1 = PCIR_BAR(0); 4559 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 4560 &ctlr->r_rid1, RF_ACTIVE))) 4561 return ENXIO; 4562 4563 ctlr->r_rid2 = PCIR_BAR(2); 4564 ctlr->r_type2 = SYS_RES_MEMORY; 4565 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4566 &ctlr->r_rid2, RF_ACTIVE))){ 4567 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 4568 return ENXIO; 4569 } 4570 ctlr->allocate = ata_siiprb_allocate; 4571 ctlr->reset = ata_siiprb_reset; 4572 ctlr->dmainit = ata_siiprb_dmainit; 4573 ctlr->setmode = ata_sata_setmode; 4574 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2; 4575 4576 /* reset controller */ 4577 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 4578 DELAY(10000); 4579 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 4580 4581 /* enable PCI interrupt */ 4582 pci_write_config(dev, PCIR_COMMAND, 4583 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 4584 break; 4585 4586 case SIIMEMIO: 4587 ctlr->r_type2 = SYS_RES_MEMORY; 4588 ctlr->r_rid2 = PCIR_BAR(5); 4589 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4590 &ctlr->r_rid2, RF_ACTIVE))) 4591 return ENXIO; 4592 4593 if (ctlr->chip->cfg2 & SIISETCLK) { 4594 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4595 pci_write_config(dev, 0x8a, 4596 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 4597 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4598 device_printf(dev, "%s could not set ATA133 clock\n", 4599 ctlr->chip->text); 4600 } 4601 4602 /* if we have 4 channels enable the second set */ 4603 if (ctlr->chip->cfg2 & SII4CH) { 4604 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 4605 ctlr->channels = 4; 4606 } 4607 4608 /* dont block interrupts from any channel */ 4609 pci_write_config(dev, 0x48, 4610 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 4611 4612 /* enable PCI interrupt as BIOS might not */ 4613 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 4614 4615 ctlr->allocate = ata_sii_allocate; 4616 if (ctlr->chip->max_dma >= ATA_SA150) { 4617 ctlr->reset = ata_sii_reset; 4618 ctlr->setmode = ata_sata_setmode; 4619 } 4620 else 4621 ctlr->setmode = ata_sii_setmode; 4622 break; 4623 4624 default: 4625 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 4626 device_printf(dev, "HW has secondary channel disabled\n"); 4627 ctlr->channels = 1; 4628 } 4629 4630 /* enable interrupt as BIOS might not */ 4631 pci_write_config(dev, 0x71, 0x01, 1); 4632 4633 ctlr->allocate = ata_cmd_allocate; 4634 ctlr->setmode = ata_cmd_setmode; 4635 break; 4636 } 4637 return 0; 4638 } 4639 4640 static int 4641 ata_cmd_allocate(device_t dev) 4642 { 4643 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4644 struct ata_channel *ch = device_get_softc(dev); 4645 4646 /* setup the usual register normal pci style */ 4647 if (ata_pci_allocate(dev)) 4648 return ENXIO; 4649 4650 if (ctlr->chip->cfg2 & SIIINTR) 4651 ch->hw.status = ata_cmd_status; 4652 4653 return 0; 4654 } 4655 4656 static int 4657 ata_cmd_status(device_t dev) 4658 { 4659 struct ata_channel *ch = device_get_softc(dev); 4660 u_int8_t reg71; 4661 4662 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) & 4663 (ch->unit ? 0x08 : 0x04))) { 4664 pci_write_config(device_get_parent(ch->dev), 0x71, 4665 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 4666 return ata_pci_status(dev); 4667 } 4668 return 0; 4669 } 4670 4671 static void 4672 ata_cmd_setmode(device_t dev, int mode) 4673 { 4674 device_t gparent = GRANDPARENT(dev); 4675 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4676 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4677 struct ata_device *atadev = device_get_softc(dev); 4678 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4679 int error; 4680 4681 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4682 4683 mode = ata_check_80pin(dev, mode); 4684 4685 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4686 4687 if (bootverbose) 4688 device_printf(dev, "%ssetting %s on %s chip\n", 4689 (error) ? "FAILURE " : "", 4690 ata_mode2str(mode), ctlr->chip->text); 4691 if (!error) { 4692 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 4693 int ureg = ch->unit ? 0x7b : 0x73; 4694 4695 if (mode >= ATA_UDMA0) { 4696 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 4697 { 0x11, 0x42 }, { 0x25, 0x8a }, 4698 { 0x15, 0x4a }, { 0x05, 0x0a } }; 4699 4700 u_int8_t umode = pci_read_config(gparent, ureg, 1); 4701 4702 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca); 4703 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)]; 4704 pci_write_config(gparent, ureg, umode, 1); 4705 } 4706 else if (mode >= ATA_WDMA0) { 4707 int dmatimings[] = { 0x87, 0x32, 0x3f }; 4708 4709 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1); 4710 pci_write_config(gparent, ureg, 4711 pci_read_config(gparent, ureg, 1) & 4712 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4713 } 4714 else { 4715 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f }; 4716 pci_write_config(gparent, treg, 4717 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1); 4718 pci_write_config(gparent, ureg, 4719 pci_read_config(gparent, ureg, 1) & 4720 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4721 } 4722 atadev->mode = mode; 4723 } 4724 } 4725 4726 static int 4727 ata_sii_allocate(device_t dev) 4728 { 4729 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4730 struct ata_channel *ch = device_get_softc(dev); 4731 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 4732 int i; 4733 4734 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 4735 ch->r_io[i].res = ctlr->r_res2; 4736 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 4737 } 4738 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 4739 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 4740 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 4741 ata_default_registers(dev); 4742 4743 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 4744 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 4745 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 4746 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 4747 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 4748 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 4749 4750 if (ctlr->chip->max_dma >= ATA_SA150) { 4751 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4752 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 4753 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4754 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 4755 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4756 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 4757 ch->flags |= ATA_NO_SLAVE; 4758 4759 /* enable PHY state change interrupt */ 4760 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 4761 } 4762 4763 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) { 4764 /* work around errata in early chips */ 4765 ch->dma->boundary = 16 * DEV_BSIZE; 4766 ch->dma->segsize = 15 * DEV_BSIZE; 4767 } 4768 4769 ata_pci_hw(dev); 4770 ch->hw.status = ata_sii_status; 4771 return 0; 4772 } 4773 4774 static int 4775 ata_sii_status(device_t dev) 4776 { 4777 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4778 struct ata_channel *ch = device_get_softc(dev); 4779 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 4780 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 4781 4782 /* do we have any PHY events ? */ 4783 if (ctlr->chip->max_dma >= ATA_SA150 && 4784 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 4785 ata_sata_phy_check_events(dev); 4786 4787 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 4788 return ata_pci_status(dev); 4789 else 4790 return 0; 4791 } 4792 4793 static void 4794 ata_sii_reset(device_t dev) 4795 { 4796 if (ata_sata_phy_reset(dev)) 4797 ata_generic_reset(dev); 4798 } 4799 4800 static void 4801 ata_sii_setmode(device_t dev, int mode) 4802 { 4803 device_t gparent = GRANDPARENT(dev); 4804 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4805 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4806 struct ata_device *atadev = device_get_softc(dev); 4807 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1); 4808 int mreg = ch->unit ? 0x84 : 0x80; 4809 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2); 4810 int mval = pci_read_config(gparent, mreg, 1) & ~mask; 4811 int error; 4812 4813 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4814 4815 if (ctlr->chip->cfg2 & SIISETCLK) { 4816 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) & 4817 (ch->unit ? 0x02 : 0x01))) { 4818 ata_print_cable(dev, "controller"); 4819 mode = ATA_UDMA2; 4820 } 4821 } 4822 else 4823 mode = ata_check_80pin(dev, mode); 4824 4825 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4826 4827 if (bootverbose) 4828 device_printf(dev, "%ssetting %s on %s chip\n", 4829 (error) ? "FAILURE " : "", 4830 ata_mode2str(mode), ctlr->chip->text); 4831 if (error) 4832 return; 4833 4834 if (mode >= ATA_UDMA0) { 4835 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 4836 u_int8_t ureg = 0xac + rego; 4837 4838 pci_write_config(gparent, mreg, 4839 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1); 4840 pci_write_config(gparent, ureg, 4841 (pci_read_config(gparent, ureg, 1) & ~0x3f) | 4842 udmatimings[mode & ATA_MODE_MASK], 1); 4843 4844 } 4845 else if (mode >= ATA_WDMA0) { 4846 u_int8_t dreg = 0xa8 + rego; 4847 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 4848 4849 pci_write_config(gparent, mreg, 4850 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1); 4851 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 4852 4853 } 4854 else { 4855 u_int8_t preg = 0xa4 + rego; 4856 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 4857 4858 pci_write_config(gparent, mreg, 4859 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1); 4860 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2); 4861 } 4862 atadev->mode = mode; 4863 } 4864 4865 struct ata_siiprb_dma_prdentry { 4866 u_int64_t addr; 4867 u_int32_t count; 4868 u_int32_t control; 4869 } __packed; 4870 4871 struct ata_siiprb_ata_command { 4872 u_int32_t reserved0; 4873 struct ata_siiprb_dma_prdentry prd[126]; 4874 } __packed; 4875 4876 struct ata_siiprb_atapi_command { 4877 u_int8_t cdb[16]; 4878 struct ata_siiprb_dma_prdentry prd[125]; 4879 } __packed; 4880 4881 struct ata_siiprb_command { 4882 u_int16_t control; 4883 u_int16_t protocol_override; 4884 u_int32_t transfer_count; 4885 u_int8_t fis[20]; 4886 union { 4887 struct ata_siiprb_ata_command ata; 4888 struct ata_siiprb_atapi_command atapi; 4889 } u; 4890 } __packed; 4891 4892 static int 4893 ata_siiprb_allocate(device_t dev) 4894 { 4895 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4896 struct ata_channel *ch = device_get_softc(dev); 4897 int offset = ch->unit * 0x2000; 4898 4899 /* set the SATA resources */ 4900 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4901 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 4902 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4903 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 4904 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4905 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 4906 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 4907 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 4908 4909 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 4910 ch->hw.end_transaction = ata_siiprb_end_transaction; 4911 ch->hw.status = ata_siiprb_status; 4912 ch->hw.command = NULL; /* not used here */ 4913 return 0; 4914 } 4915 4916 static int 4917 ata_siiprb_status(device_t dev) 4918 { 4919 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4920 struct ata_channel *ch = device_get_softc(dev); 4921 int offset = ch->unit * 0x2000; 4922 4923 if ((ATA_INL(ctlr->r_res1, 0x0044) & (1 << ch->unit))) { 4924 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 4925 4926 /* do we have any PHY events ? */ 4927 ata_sata_phy_check_events(dev); 4928 4929 /* clear interrupt(s) */ 4930 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 4931 4932 /* do we have any device action ? */ 4933 return (istatus & 0x00000001); 4934 } 4935 return 0; 4936 } 4937 4938 static int 4939 ata_siiprb_begin_transaction(struct ata_request *request) 4940 { 4941 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 4942 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4943 struct ata_siiprb_command *prb; 4944 int offset = ch->unit * 0x2000; 4945 u_int64_t prb_bus; 4946 int tag = 0, dummy; 4947 4948 /* check for 48 bit access and convert if needed */ 4949 ata_modify_if_48bit(request); 4950 4951 /* get a piece of the workspace for this request */ 4952 prb = (struct ata_siiprb_command *) 4953 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 4954 4955 /* set basic prd options ata/atapi etc etc */ 4956 bzero(prb, sizeof(struct ata_siiprb_command)); 4957 4958 /* setup the FIS for this request */ 4959 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 4960 device_printf(request->dev, "setting up SATA FIS failed\n"); 4961 request->result = EIO; 4962 return ATA_OP_FINISHED; 4963 } 4964 4965 /* if request moves data setup and load SG list */ 4966 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 4967 struct ata_siiprb_dma_prdentry *prd; 4968 4969 if (request->flags & ATA_R_ATAPI) 4970 prd = &prb->u.atapi.prd[0]; 4971 else 4972 prd = &prb->u.ata.prd[0]; 4973 if (ch->dma->load(ch->dev, request->data, request->bytecount, 4974 request->flags & ATA_R_READ, prd, &dummy)) { 4975 device_printf(request->dev, "setting up DMA failed\n"); 4976 request->result = EIO; 4977 return ATA_OP_FINISHED; 4978 } 4979 } 4980 4981 /* activate the prb */ 4982 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 4983 ATA_OUTL(ctlr->r_res2, 4984 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 4985 ATA_OUTL(ctlr->r_res2, 4986 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 4987 4988 /* start the timeout */ 4989 callout_reset(&request->callout, request->timeout * hz, 4990 (timeout_t*)ata_timeout, request); 4991 return ATA_OP_CONTINUES; 4992 } 4993 4994 static int 4995 ata_siiprb_end_transaction(struct ata_request *request) 4996 { 4997 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 4998 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4999 struct ata_siiprb_command *prb; 5000 int offset = ch->unit * 0x2000; 5001 int error, tag = 0; 5002 5003 /* kill the timeout */ 5004 callout_stop(&request->callout); 5005 5006 prb = (struct ata_siiprb_command *) 5007 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 5008 5009 /* if error status get details */ 5010 request->status = prb->fis[2]; 5011 if (request->status & ATA_S_ERROR) 5012 request->error = prb->fis[3]; 5013 5014 /* update progress */ 5015 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 5016 if (request->flags & ATA_R_READ) 5017 request->donecount = prb->transfer_count; 5018 else 5019 request->donecount = request->bytecount; 5020 } 5021 5022 /* any controller errors flagged ? */ 5023 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 5024 kprintf("ata_siiprb_end_transaction %s error=%08x\n", 5025 ata_cmd2str(request), error); 5026 } 5027 5028 /* release SG list etc */ 5029 ch->dma->unload(ch->dev); 5030 5031 return ATA_OP_FINISHED; 5032 } 5033 5034 static void 5035 ata_siiprb_reset(device_t dev) 5036 { 5037 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5038 struct ata_channel *ch = device_get_softc(dev); 5039 int offset = ch->unit * 0x2000; 5040 struct ata_siiprb_command *prb; 5041 u_int64_t prb_bus; 5042 u_int32_t status, signature; 5043 int timeout, tag = 0; 5044 5045 /* reset channel HW */ 5046 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 5047 DELAY(1000); 5048 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 5049 DELAY(10000); 5050 5051 /* poll for channel ready */ 5052 for (timeout = 0; timeout < 1000; timeout++) { 5053 if ((status = ATA_INL(ctlr->r_res2, 0x1000 + offset)) & 0x00040000) 5054 break; 5055 DELAY(1000); 5056 } 5057 if (timeout >= 1000) { 5058 device_printf(ch->dev, "channel HW reset timeout reset failure\n"); 5059 ch->devices = 0; 5060 goto finish; 5061 } 5062 if (bootverbose) 5063 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout * 1); 5064 5065 /* reset phy */ 5066 if (!ata_sata_phy_reset(dev)) { 5067 if (bootverbose) 5068 device_printf(ch->dev, "phy reset found no device\n"); 5069 ch->devices = 0; 5070 goto finish; 5071 } 5072 5073 /* get a piece of the workspace for a soft reset request */ 5074 prb = (struct ata_siiprb_command *) 5075 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 5076 bzero(prb, sizeof(struct ata_siiprb_command)); 5077 prb->control = htole16(0x0080); 5078 5079 /* activate the soft reset prb */ 5080 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 5081 ATA_OUTL(ctlr->r_res2, 5082 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 5083 ATA_OUTL(ctlr->r_res2, 5084 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 5085 5086 /* poll for channel ready */ 5087 for (timeout = 0; timeout < 1000; timeout++) { 5088 DELAY(1000); 5089 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 5090 break; 5091 } 5092 if (timeout >= 1000) { 5093 device_printf(ch->dev, "reset timeout - no device found\n"); 5094 ch->devices = 0; 5095 goto finish; 5096 } 5097 if (bootverbose) 5098 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n", 5099 timeout, status); 5100 5101 /* find out whats there */ 5102 prb = (struct ata_siiprb_command *) 5103 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 5104 signature = 5105 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 5106 if (bootverbose) 5107 device_printf(ch->dev, "signature=%08x\n", signature); 5108 switch (signature) { 5109 case 0xeb140101: 5110 ch->devices = ATA_ATAPI_MASTER; 5111 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n"); 5112 ch->devices = 0; 5113 break; 5114 case 0x96690101: 5115 ch->devices = ATA_PORTMULTIPLIER; 5116 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 5117 ch->devices = 0; 5118 break; 5119 case 0x00000101: 5120 ch->devices = ATA_ATA_MASTER; 5121 break; 5122 default: 5123 ch->devices = 0; 5124 } 5125 5126 finish: 5127 /* clear interrupt(s) */ 5128 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 5129 5130 /* require explicit interrupt ack */ 5131 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 5132 5133 /* 64bit mode */ 5134 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 5135 5136 /* enable interrupts wanted */ 5137 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 5138 } 5139 5140 static void 5141 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 5142 { 5143 struct ata_dmasetprd_args *args = xsc; 5144 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 5145 int i; 5146 5147 if ((args->error = error)) 5148 return; 5149 5150 for (i = 0; i < nsegs; i++) { 5151 prd[i].addr = htole64(segs[i].ds_addr); 5152 prd[i].count = htole32(segs[i].ds_len); 5153 } 5154 prd[i - 1].control = htole32(ATA_DMA_EOT); 5155 } 5156 5157 static void 5158 ata_siiprb_dmainit(device_t dev) 5159 { 5160 struct ata_channel *ch = device_get_softc(dev); 5161 5162 ata_dmainit(dev); 5163 if (ch->dma) { 5164 /* note start and stop are not used here */ 5165 ch->dma->setprd = ata_siiprb_dmasetprd; 5166 ch->dma->max_address = BUS_SPACE_MAXADDR; 5167 } 5168 } 5169 5170 5171 /* 5172 * Silicon Integrated Systems Corp. (SiS) chipset support functions 5173 */ 5174 int 5175 ata_sis_ident(device_t dev) 5176 { 5177 struct ata_pci_controller *ctlr = device_get_softc(dev); 5178 struct ata_chip_id *idx; 5179 static struct ata_chip_id ids[] = 5180 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */ 5181 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */ 5182 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */ 5183 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */ 5184 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */ 5185 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */ 5186 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */ 5187 5188 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */ 5189 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */ 5190 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */ 5191 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */ 5192 5193 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */ 5194 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */ 5195 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */ 5196 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */ 5197 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */ 5198 5199 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" }, 5200 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" }, 5201 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" }, 5202 5203 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" }, 5204 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" }, 5205 { 0, 0, 0, 0, 0, 0 }}; 5206 char buffer[64]; 5207 int found = 0; 5208 5209 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev)))) 5210 return ENXIO; 5211 5212 if (idx->cfg2 && !found) { 5213 u_int8_t reg57 = pci_read_config(dev, 0x57, 1); 5214 5215 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1); 5216 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) { 5217 found = 1; 5218 idx->cfg1 = SIS133NEW; 5219 idx->max_dma = ATA_UDMA6; 5220 ksprintf(buffer, "SiS 962/963 %s controller", 5221 ata_mode2str(idx->max_dma)); 5222 } 5223 pci_write_config(dev, 0x57, reg57, 1); 5224 } 5225 if (idx->cfg2 && !found) { 5226 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1); 5227 5228 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1); 5229 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) { 5230 struct ata_chip_id id[] = 5231 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }}; 5232 5233 found = 1; 5234 if (ata_find_chip(dev, id, pci_get_slot(dev))) { 5235 idx->cfg1 = SIS133OLD; 5236 idx->max_dma = ATA_UDMA6; 5237 } 5238 else { 5239 idx->cfg1 = SIS100NEW; 5240 idx->max_dma = ATA_UDMA5; 5241 } 5242 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma)); 5243 } 5244 pci_write_config(dev, 0x4a, reg4a, 1); 5245 } 5246 if (!found) 5247 ksprintf(buffer,"SiS %s %s controller", 5248 idx->text, ata_mode2str(idx->max_dma)); 5249 5250 device_set_desc_copy(dev, buffer); 5251 ctlr->chip = idx; 5252 ctlr->chipinit = ata_sis_chipinit; 5253 return 0; 5254 } 5255 5256 static int 5257 ata_sis_chipinit(device_t dev) 5258 { 5259 struct ata_pci_controller *ctlr = device_get_softc(dev); 5260 5261 if (ata_setup_interrupt(dev)) 5262 return ENXIO; 5263 5264 switch (ctlr->chip->cfg1) { 5265 case SIS33: 5266 break; 5267 case SIS66: 5268 case SIS100OLD: 5269 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1); 5270 break; 5271 case SIS100NEW: 5272 case SIS133OLD: 5273 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1); 5274 break; 5275 case SIS133NEW: 5276 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2); 5277 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2); 5278 break; 5279 case SISSATA: 5280 ctlr->r_type2 = SYS_RES_IOPORT; 5281 ctlr->r_rid2 = PCIR_BAR(5); 5282 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5283 &ctlr->r_rid2, RF_ACTIVE))) { 5284 ctlr->allocate = ata_sis_allocate; 5285 ctlr->reset = ata_sis_reset; 5286 5287 /* enable PCI interrupt */ 5288 pci_write_config(dev, PCIR_COMMAND, 5289 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5290 } 5291 ctlr->setmode = ata_sata_setmode; 5292 return 0; 5293 default: 5294 return ENXIO; 5295 } 5296 ctlr->setmode = ata_sis_setmode; 5297 return 0; 5298 } 5299 5300 static int 5301 ata_sis_allocate(device_t dev) 5302 { 5303 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5304 struct ata_channel *ch = device_get_softc(dev); 5305 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6); 5306 5307 /* setup the usual register normal pci style */ 5308 if (ata_pci_allocate(dev)) 5309 return ENXIO; 5310 5311 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5312 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; 5313 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5314 ch->r_io[ATA_SERROR].offset = 0x04 + offset; 5315 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5316 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; 5317 ch->flags |= ATA_NO_SLAVE; 5318 5319 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ 5320 /* XXX SOS unknown how to enable PHY state change interrupt */ 5321 return 0; 5322 } 5323 5324 static void 5325 ata_sis_reset(device_t dev) 5326 { 5327 if (ata_sata_phy_reset(dev)) 5328 ata_generic_reset(dev); 5329 } 5330 5331 static void 5332 ata_sis_setmode(device_t dev, int mode) 5333 { 5334 device_t gparent = GRANDPARENT(dev); 5335 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5336 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5337 struct ata_device *atadev = device_get_softc(dev); 5338 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5339 int error; 5340 5341 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5342 5343 if (ctlr->chip->cfg1 == SIS133NEW) { 5344 if (mode > ATA_UDMA2 && 5345 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) { 5346 ata_print_cable(dev, "controller"); 5347 mode = ATA_UDMA2; 5348 } 5349 } 5350 else { 5351 if (mode > ATA_UDMA2 && 5352 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) { 5353 ata_print_cable(dev, "controller"); 5354 mode = ATA_UDMA2; 5355 } 5356 } 5357 5358 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5359 5360 if (bootverbose) 5361 device_printf(dev, "%ssetting %s on %s chip\n", 5362 (error) ? "FAILURE " : "", 5363 ata_mode2str(mode), ctlr->chip->text); 5364 if (!error) { 5365 switch (ctlr->chip->cfg1) { 5366 case SIS133NEW: { 5367 u_int32_t timings[] = 5368 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 5369 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 5370 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; 5371 u_int32_t reg; 5372 5373 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); 5374 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4); 5375 break; 5376 } 5377 case SIS133OLD: { 5378 u_int16_t timings[] = 5379 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 5380 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; 5381 5382 u_int16_t reg = 0x40 + (devno << 1); 5383 5384 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5385 break; 5386 } 5387 case SIS100NEW: { 5388 u_int16_t timings[] = 5389 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 5390 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; 5391 u_int16_t reg = 0x40 + (devno << 1); 5392 5393 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5394 break; 5395 } 5396 case SIS100OLD: 5397 case SIS66: 5398 case SIS33: { 5399 u_int16_t timings[] = 5400 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 5401 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; 5402 u_int16_t reg = 0x40 + (devno << 1); 5403 5404 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5405 break; 5406 } 5407 } 5408 atadev->mode = mode; 5409 } 5410 } 5411 5412 5413 /* VIA Technologies Inc. chipset support functions */ 5414 int 5415 ata_via_ident(device_t dev) 5416 { 5417 struct ata_pci_controller *ctlr = device_get_softc(dev); 5418 struct ata_chip_id *idx; 5419 static struct ata_chip_id ids[] = 5420 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 5421 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 5422 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 5423 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 5424 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 5425 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 5426 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 5427 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 5428 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 5429 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 5430 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 5431 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 5432 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 5433 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 5434 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 5435 { 0, 0, 0, 0, 0, 0 }}; 5436 static struct ata_chip_id new_ids[] = 5437 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 5438 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 5439 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 5440 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 5441 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" }, 5442 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" }, 5443 { 0, 0, 0, 0, 0, 0 }}; 5444 char buffer[64]; 5445 5446 if (pci_get_devid(dev) == ATA_VIA82C571) { 5447 if (!(idx = ata_find_chip(dev, ids, -99))) 5448 return ENXIO; 5449 } 5450 else { 5451 if (!(idx = ata_match_chip(dev, new_ids))) 5452 return ENXIO; 5453 } 5454 5455 ksprintf(buffer, "VIA %s %s controller", 5456 idx->text, ata_mode2str(idx->max_dma)); 5457 device_set_desc_copy(dev, buffer); 5458 ctlr->chip = idx; 5459 ctlr->chipinit = ata_via_chipinit; 5460 return 0; 5461 } 5462 5463 static int 5464 ata_via_chipinit(device_t dev) 5465 { 5466 struct ata_pci_controller *ctlr = device_get_softc(dev); 5467 5468 if (ata_setup_interrupt(dev)) 5469 return ENXIO; 5470 5471 if (ctlr->chip->max_dma >= ATA_SA150) { 5472 /* do we have AHCI capability ? */ 5473 if ((ctlr->chip->cfg2 == VIAAHCI) && ata_ahci_chipinit(dev) != ENXIO) 5474 return 0; 5475 5476 ctlr->r_type2 = SYS_RES_IOPORT; 5477 ctlr->r_rid2 = PCIR_BAR(5); 5478 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5479 &ctlr->r_rid2, RF_ACTIVE))) { 5480 ctlr->allocate = ata_via_allocate; 5481 ctlr->reset = ata_via_reset; 5482 5483 /* enable PCI interrupt */ 5484 pci_write_config(dev, PCIR_COMMAND, 5485 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5486 } 5487 5488 if (ctlr->chip->cfg2 & VIABAR) { 5489 ctlr->channels = 3; 5490 ctlr->setmode = ata_via_setmode; 5491 } 5492 else 5493 ctlr->setmode = ata_sata_setmode; 5494 return 0; 5495 } 5496 5497 /* prepare for ATA-66 on the 82C686a and 82C596b */ 5498 if (ctlr->chip->cfg2 & VIACLK) 5499 pci_write_config(dev, 0x50, 0x030b030b, 4); 5500 5501 /* the southbridge might need the data corruption fix */ 5502 if (ctlr->chip->cfg2 & VIABUG) 5503 ata_via_southbridge_fixup(dev); 5504 5505 /* set fifo configuration half'n'half */ 5506 pci_write_config(dev, 0x43, 5507 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 5508 5509 /* set status register read retry */ 5510 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 5511 5512 /* set DMA read & end-of-sector fifo flush */ 5513 pci_write_config(dev, 0x46, 5514 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 5515 5516 /* set sector size */ 5517 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 5518 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 5519 5520 ctlr->setmode = ata_via_family_setmode; 5521 return 0; 5522 } 5523 5524 static int 5525 ata_via_allocate(device_t dev) 5526 { 5527 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5528 struct ata_channel *ch = device_get_softc(dev); 5529 5530 /* newer SATA chips has resources in one BAR for each channel */ 5531 if (ctlr->chip->cfg2 & VIABAR) { 5532 struct resource *r_io; 5533 int i, rid; 5534 5535 rid = PCIR_BAR(ch->unit); 5536 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 5537 SYS_RES_IOPORT, 5538 &rid, RF_ACTIVE))) 5539 return ENXIO; 5540 5541 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 5542 ch->r_io[i].res = r_io; 5543 ch->r_io[i].offset = i; 5544 } 5545 ch->r_io[ATA_CONTROL].res = r_io; 5546 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 5547 ch->r_io[ATA_IDX_ADDR].res = r_io; 5548 ata_default_registers(dev); 5549 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 5550 ch->r_io[i].res = ctlr->r_res1; 5551 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 5552 } 5553 ata_pci_hw(dev); 5554 if (ch->unit >= 2) 5555 return 0; 5556 } 5557 else { 5558 /* setup the usual register normal pci style */ 5559 if (ata_pci_allocate(dev)) 5560 return ENXIO; 5561 } 5562 5563 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5564 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 5565 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5566 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 5567 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5568 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 5569 ch->flags |= ATA_NO_SLAVE; 5570 5571 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */ 5572 /* XXX SOS unknown how to enable PHY state change interrupt */ 5573 return 0; 5574 } 5575 5576 static void 5577 ata_via_reset(device_t dev) 5578 { 5579 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5580 struct ata_channel *ch = device_get_softc(dev); 5581 5582 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 5583 ata_generic_reset(dev); 5584 else 5585 if (ata_sata_phy_reset(dev)) 5586 ata_generic_reset(dev); 5587 } 5588 5589 static void 5590 ata_via_setmode(device_t dev, int mode) 5591 { 5592 device_t gparent = GRANDPARENT(dev); 5593 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5594 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5595 struct ata_device *atadev = device_get_softc(dev); 5596 int error; 5597 5598 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 5599 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20, 5600 0x65, 0x32, 0x20, 5601 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5602 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 5603 5604 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6)); 5605 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5606 if (bootverbose) 5607 device_printf(dev, "%ssetting %s on %s chip\n", 5608 (error) ? "FAILURE " : "", ata_mode2str(mode), 5609 ctlr->chip->text); 5610 if (!error) { 5611 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1); 5612 if (mode >= ATA_UDMA0) 5613 pci_write_config(gparent, 0xb3, 5614 dma_timings[mode & ATA_MODE_MASK], 1); 5615 atadev->mode = mode; 5616 } 5617 } 5618 else 5619 ata_sata_setmode(dev, mode); 5620 } 5621 5622 static void 5623 ata_via_southbridge_fixup(device_t dev) 5624 { 5625 device_t *children; 5626 int nchildren, i; 5627 5628 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5629 return; 5630 5631 for (i = 0; i < nchildren; i++) { 5632 if (pci_get_devid(children[i]) == ATA_VIA8363 || 5633 pci_get_devid(children[i]) == ATA_VIA8371 || 5634 pci_get_devid(children[i]) == ATA_VIA8662 || 5635 pci_get_devid(children[i]) == ATA_VIA8361) { 5636 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 5637 5638 if ((reg76 & 0xf0) != 0xd0) { 5639 device_printf(dev, 5640 "Correcting VIA config for southbridge data corruption bug\n"); 5641 pci_write_config(children[i], 0x75, 0x80, 1); 5642 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 5643 } 5644 break; 5645 } 5646 } 5647 kfree(children, M_TEMP); 5648 } 5649 5650 5651 /* common code for VIA, AMD & nVidia */ 5652 static void 5653 ata_via_family_setmode(device_t dev, int mode) 5654 { 5655 device_t gparent = GRANDPARENT(dev); 5656 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5657 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5658 struct ata_device *atadev = device_get_softc(dev); 5659 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20, 5660 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5661 int modes[][7] = { 5662 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 5663 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 5664 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 5665 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */ 5666 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */ 5667 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5668 int reg = 0x53 - devno; 5669 int error; 5670 5671 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5672 5673 if (ctlr->chip->cfg2 & AMDCABLE) { 5674 if (mode > ATA_UDMA2 && 5675 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) { 5676 ata_print_cable(dev, "controller"); 5677 mode = ATA_UDMA2; 5678 } 5679 } 5680 else 5681 mode = ata_check_80pin(dev, mode); 5682 5683 if (ctlr->chip->cfg2 & NVIDIA) 5684 reg += 0x10; 5685 5686 if (ctlr->chip->cfg1 != VIA133) 5687 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1); 5688 5689 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5690 5691 if (bootverbose) 5692 device_printf(dev, "%ssetting %s on %s chip\n", 5693 (error) ? "FAILURE " : "", ata_mode2str(mode), 5694 ctlr->chip->text); 5695 if (!error) { 5696 if (mode >= ATA_UDMA0) 5697 pci_write_config(gparent, reg, 5698 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 5699 else 5700 pci_write_config(gparent, reg, 0x8b, 1); 5701 atadev->mode = mode; 5702 } 5703 } 5704 5705 5706 /* misc functions */ 5707 static struct ata_chip_id * 5708 ata_match_chip(device_t dev, struct ata_chip_id *index) 5709 { 5710 while (index->chipid != 0) { 5711 if (pci_get_devid(dev) == index->chipid && 5712 pci_get_revid(dev) >= index->chiprev) 5713 return index; 5714 index++; 5715 } 5716 return NULL; 5717 } 5718 5719 static struct ata_chip_id * 5720 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot) 5721 { 5722 device_t *children; 5723 int nchildren, i; 5724 5725 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5726 return 0; 5727 5728 while (index->chipid != 0) { 5729 for (i = 0; i < nchildren; i++) { 5730 if (((slot >= 0 && pci_get_slot(children[i]) == slot) || 5731 (slot < 0 && pci_get_slot(children[i]) <= -slot)) && 5732 pci_get_devid(children[i]) == index->chipid && 5733 pci_get_revid(children[i]) >= index->chiprev) { 5734 kfree(children, M_TEMP); 5735 return index; 5736 } 5737 } 5738 index++; 5739 } 5740 kfree(children, M_TEMP); 5741 return NULL; 5742 } 5743 5744 static int 5745 ata_setup_interrupt(device_t dev) 5746 { 5747 struct ata_pci_controller *ctlr = device_get_softc(dev); 5748 int rid = ATA_IRQ_RID; 5749 5750 if (!ctlr->legacy) { 5751 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 5752 RF_SHAREABLE | RF_ACTIVE))) { 5753 device_printf(dev, "unable to map interrupt\n"); 5754 return ENXIO; 5755 } 5756 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 5757 ata_generic_intr, ctlr, &ctlr->handle, NULL))) { 5758 device_printf(dev, "unable to setup interrupt\n"); 5759 return ENXIO; 5760 } 5761 } 5762 return 0; 5763 } 5764 5765 struct ata_serialize { 5766 struct spinlock locked_mtx; 5767 int locked_ch; 5768 int restart_ch; 5769 }; 5770 5771 static int 5772 ata_serialize(device_t dev, int flags) 5773 { 5774 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5775 struct ata_channel *ch = device_get_softc(dev); 5776 struct ata_serialize *serial; 5777 static int inited = 0; 5778 int res; 5779 5780 if (!inited) { 5781 serial = kmalloc(sizeof(struct ata_serialize), 5782 M_TEMP, M_INTWAIT | M_ZERO); 5783 spin_init(&serial->locked_mtx); 5784 serial->locked_ch = -1; 5785 serial->restart_ch = -1; 5786 device_set_ivars(ctlr->dev, serial); 5787 inited = 1; 5788 } 5789 else 5790 serial = device_get_ivars(ctlr->dev); 5791 5792 spin_lock_wr(&serial->locked_mtx); 5793 switch (flags) { 5794 case ATA_LF_LOCK: 5795 if (serial->locked_ch == -1) 5796 serial->locked_ch = ch->unit; 5797 if (serial->locked_ch != ch->unit) 5798 serial->restart_ch = ch->unit; 5799 break; 5800 5801 case ATA_LF_UNLOCK: 5802 if (serial->locked_ch == ch->unit) { 5803 serial->locked_ch = -1; 5804 if (serial->restart_ch != -1) { 5805 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) { 5806 serial->restart_ch = -1; 5807 spin_unlock_wr(&serial->locked_mtx); 5808 ata_start(ch->dev); 5809 return -1; 5810 } 5811 } 5812 } 5813 break; 5814 5815 case ATA_LF_WHICH: 5816 break; 5817 } 5818 res = serial->locked_ch; 5819 spin_unlock_wr(&serial->locked_mtx); 5820 return res; 5821 } 5822 5823 static void 5824 ata_print_cable(device_t dev, u_int8_t *who) 5825 { 5826 device_printf(dev, 5827 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who); 5828 } 5829 5830 static int 5831 ata_atapi(device_t dev) 5832 { 5833 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5834 struct ata_device *atadev = device_get_softc(dev); 5835 5836 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || 5837 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE)); 5838 } 5839 5840 static int 5841 ata_check_80pin(device_t dev, int mode) 5842 { 5843 struct ata_device *atadev = device_get_softc(dev); 5844 5845 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) { 5846 ata_print_cable(dev, "device"); 5847 mode = ATA_UDMA2; 5848 } 5849 return mode; 5850 } 5851 5852 static int 5853 ata_mode2idx(int mode) 5854 { 5855 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) 5856 return (mode & ATA_MODE_MASK) + 8; 5857 if ((mode & ATA_DMA_MASK) == ATA_WDMA0) 5858 return (mode & ATA_MODE_MASK) + 5; 5859 return (mode & ATA_MODE_MASK) - ATA_PIO0; 5860 } 5861