1 /*- 2 * Copyright (c) 1998 - 2006 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.196 2007/04/08 19:18:51 sos Exp $ 27 * $DragonFly: src/sys/dev/disk/nata/ata-chipset.c,v 1.14 2008/04/05 20:13:04 dillon Exp $ 28 */ 29 30 #include "opt_ata.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/bus_dma.h> 35 #include <sys/bus_resource.h> 36 #include <sys/callout.h> 37 #include <sys/endian.h> 38 #include <sys/libkern.h> 39 #include <sys/lock.h> /* for {get,rel}_mplock() */ 40 #include <sys/malloc.h> 41 #include <sys/nata.h> 42 #include <sys/queue.h> 43 #include <sys/rman.h> 44 #include <sys/spinlock.h> 45 #include <sys/spinlock2.h> 46 #include <sys/systm.h> 47 #include <sys/taskqueue.h> 48 49 #include <machine/bus_dma.h> 50 51 #include <bus/pci/pcireg.h> 52 #include <bus/pci/pcivar.h> 53 54 #include "ata-all.h" 55 #include "ata-pci.h" 56 #include "ata_if.h" 57 58 /* local prototypes */ 59 /* ata-chipset.c */ 60 static int ata_generic_chipinit(device_t dev); 61 static void ata_generic_intr(void *data); 62 static void ata_generic_setmode(device_t dev, int mode); 63 static void ata_sata_phy_check_events(device_t dev); 64 static void ata_sata_phy_event(void *context, int dummy); 65 static int ata_sata_phy_reset(device_t dev); 66 static int ata_sata_connect(struct ata_channel *ch); 67 static void ata_sata_setmode(device_t dev, int mode); 68 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); 69 static int ata_ahci_chipinit(device_t dev); 70 static int ata_ahci_allocate(device_t dev); 71 static int ata_ahci_status(device_t dev); 72 static int ata_ahci_begin_transaction(struct ata_request *request); 73 static int ata_ahci_end_transaction(struct ata_request *request); 74 static void ata_ahci_reset(device_t dev); 75 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 76 static void ata_ahci_dmainit(device_t dev); 77 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request); 78 static int ata_acard_chipinit(device_t dev); 79 static int ata_acard_allocate(device_t dev); 80 static int ata_acard_status(device_t dev); 81 static void ata_acard_850_setmode(device_t dev, int mode); 82 static void ata_acard_86X_setmode(device_t dev, int mode); 83 static int ata_ali_chipinit(device_t dev); 84 static int ata_ali_allocate(device_t dev); 85 static int ata_ali_sata_allocate(device_t dev); 86 static void ata_ali_reset(device_t dev); 87 static void ata_ali_setmode(device_t dev, int mode); 88 static int ata_amd_chipinit(device_t dev); 89 static int ata_ati_chipinit(device_t dev); 90 static void ata_ati_setmode(device_t dev, int mode); 91 static int ata_cyrix_chipinit(device_t dev); 92 static void ata_cyrix_setmode(device_t dev, int mode); 93 static int ata_cypress_chipinit(device_t dev); 94 static void ata_cypress_setmode(device_t dev, int mode); 95 static int ata_highpoint_chipinit(device_t dev); 96 static int ata_highpoint_allocate(device_t dev); 97 static void ata_highpoint_setmode(device_t dev, int mode); 98 static int ata_highpoint_check_80pin(device_t dev, int mode); 99 static int ata_intel_chipinit(device_t dev); 100 static int ata_intel_allocate(device_t dev); 101 static void ata_intel_reset(device_t dev); 102 static void ata_intel_old_setmode(device_t dev, int mode); 103 static void ata_intel_new_setmode(device_t dev, int mode); 104 static int ata_intel_31244_allocate(device_t dev); 105 static int ata_intel_31244_status(device_t dev); 106 static int ata_intel_31244_command(struct ata_request *request); 107 static void ata_intel_31244_reset(device_t dev); 108 static int ata_ite_chipinit(device_t dev); 109 static void ata_ite_setmode(device_t dev, int mode); 110 static int ata_jmicron_chipinit(device_t dev); 111 static int ata_jmicron_allocate(device_t dev); 112 static void ata_jmicron_reset(device_t dev); 113 static void ata_jmicron_dmainit(device_t dev); 114 static void ata_jmicron_setmode(device_t dev, int mode); 115 static int ata_marvell_pata_chipinit(device_t dev); 116 static int ata_marvell_pata_allocate(device_t dev); 117 static void ata_marvell_pata_setmode(device_t dev, int mode); 118 static int ata_marvell_edma_chipinit(device_t dev); 119 static int ata_marvell_edma_allocate(device_t dev); 120 static int ata_marvell_edma_status(device_t dev); 121 static int ata_marvell_edma_begin_transaction(struct ata_request *request); 122 static int ata_marvell_edma_end_transaction(struct ata_request *request); 123 static void ata_marvell_edma_reset(device_t dev); 124 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 125 static void ata_marvell_edma_dmainit(device_t dev); 126 static int ata_national_chipinit(device_t dev); 127 static void ata_national_setmode(device_t dev, int mode); 128 static int ata_netcell_chipinit(device_t dev); 129 static int ata_netcell_allocate(device_t dev); 130 static int ata_nvidia_chipinit(device_t dev); 131 static int ata_nvidia_allocate(device_t dev); 132 static int ata_nvidia_status(device_t dev); 133 static void ata_nvidia_reset(device_t dev); 134 static int ata_promise_chipinit(device_t dev); 135 static int ata_promise_allocate(device_t dev); 136 static int ata_promise_status(device_t dev); 137 static int ata_promise_dmastart(device_t dev); 138 static int ata_promise_dmastop(device_t dev); 139 static void ata_promise_dmareset(device_t dev); 140 static void ata_promise_dmainit(device_t dev); 141 static void ata_promise_setmode(device_t dev, int mode); 142 static int ata_promise_tx2_allocate(device_t dev); 143 static int ata_promise_tx2_status(device_t dev); 144 static int ata_promise_mio_allocate(device_t dev); 145 static void ata_promise_mio_intr(void *data); 146 static int ata_promise_mio_status(device_t dev); 147 static int ata_promise_mio_command(struct ata_request *request); 148 static void ata_promise_mio_reset(device_t dev); 149 static void ata_promise_mio_dmainit(device_t dev); 150 static void ata_promise_mio_setmode(device_t dev, int mode); 151 static void ata_promise_sx4_intr(void *data); 152 static int ata_promise_sx4_command(struct ata_request *request); 153 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 154 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 155 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 156 static int ata_serverworks_chipinit(device_t dev); 157 static int ata_serverworks_allocate(device_t dev); 158 static void ata_serverworks_setmode(device_t dev, int mode); 159 static int ata_sii_chipinit(device_t dev); 160 static int ata_cmd_allocate(device_t dev); 161 static int ata_cmd_status(device_t dev); 162 static void ata_cmd_setmode(device_t dev, int mode); 163 static int ata_sii_allocate(device_t dev); 164 static int ata_sii_status(device_t dev); 165 static void ata_sii_reset(device_t dev); 166 static void ata_sii_setmode(device_t dev, int mode); 167 static int ata_siiprb_allocate(device_t dev); 168 static int ata_siiprb_status(device_t dev); 169 static int ata_siiprb_begin_transaction(struct ata_request *request); 170 static int ata_siiprb_end_transaction(struct ata_request *request); 171 static void ata_siiprb_reset(device_t dev); 172 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 173 static void ata_siiprb_dmainit(device_t dev); 174 static int ata_sis_chipinit(device_t dev); 175 static int ata_sis_allocate(device_t dev); 176 static void ata_sis_reset(device_t dev); 177 static void ata_sis_setmode(device_t dev, int mode); 178 static int ata_via_chipinit(device_t dev); 179 static int ata_via_allocate(device_t dev); 180 static void ata_via_reset(device_t dev); 181 static void ata_via_setmode(device_t dev, int mode); 182 static void ata_via_southbridge_fixup(device_t dev); 183 static void ata_via_family_setmode(device_t dev, int mode); 184 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index); 185 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot); 186 static int ata_setup_interrupt(device_t dev); 187 static int ata_serialize(device_t dev, int flags); 188 static void ata_print_cable(device_t dev, u_int8_t *who); 189 static int ata_atapi(device_t dev); 190 static int ata_check_80pin(device_t dev, int mode); 191 static int ata_mode2idx(int mode); 192 193 194 /* 195 * generic ATA support functions 196 */ 197 int 198 ata_generic_ident(device_t dev) 199 { 200 struct ata_pci_controller *ctlr = device_get_softc(dev); 201 char buffer[64]; 202 203 ksnprintf(buffer, sizeof(buffer), 204 "%s ATA controller", ata_pcivendor2str(dev)); 205 device_set_desc_copy(dev, buffer); 206 ctlr->chipinit = ata_generic_chipinit; 207 return 0; 208 } 209 210 static int 211 ata_generic_chipinit(device_t dev) 212 { 213 struct ata_pci_controller *ctlr = device_get_softc(dev); 214 215 if (ata_setup_interrupt(dev)) 216 return ENXIO; 217 ctlr->setmode = ata_generic_setmode; 218 return 0; 219 } 220 221 static void 222 ata_generic_intr(void *data) 223 { 224 struct ata_pci_controller *ctlr = data; 225 struct ata_channel *ch; 226 int unit; 227 228 for (unit = 0; unit < ctlr->channels; unit++) { 229 if ((ch = ctlr->interrupt[unit].argument)) 230 ctlr->interrupt[unit].function(ch); 231 } 232 } 233 234 static void 235 ata_generic_setmode(device_t dev, int mode) 236 { 237 struct ata_device *atadev = device_get_softc(dev); 238 239 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 240 mode = ata_check_80pin(dev, mode); 241 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 242 atadev->mode = mode; 243 } 244 245 246 /* 247 * SATA support functions 248 */ 249 static void 250 ata_sata_phy_check_events(device_t dev) 251 { 252 struct ata_channel *ch = device_get_softc(dev); 253 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR); 254 255 /* clear error bits/interrupt */ 256 ATA_IDX_OUTL(ch, ATA_SERROR, error); 257 258 /* do we have any events flagged ? */ 259 if (error) { 260 struct ata_connect_task *tp; 261 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS); 262 263 /* if we have a connection event deal with it */ 264 if ((error & ATA_SE_PHY_CHANGED) && 265 (tp = (struct ata_connect_task *) 266 kmalloc(sizeof(struct ata_connect_task), 267 M_ATA, M_INTWAIT | M_ZERO))) { 268 269 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) || 270 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) { 271 if (bootverbose) 272 device_printf(ch->dev, "CONNECT requested\n"); 273 tp->action = ATA_C_ATTACH; 274 } 275 else { 276 if (bootverbose) 277 device_printf(ch->dev, "DISCONNECT requested\n"); 278 tp->action = ATA_C_DETACH; 279 } 280 tp->dev = ch->dev; 281 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 282 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 283 } 284 } 285 } 286 287 static void 288 ata_sata_phy_event(void *context, int dummy) 289 { 290 struct ata_connect_task *tp = (struct ata_connect_task *)context; 291 struct ata_channel *ch = device_get_softc(tp->dev); 292 device_t *children; 293 int nchildren, i; 294 295 get_mplock(); 296 if (tp->action == ATA_C_ATTACH) { 297 if (bootverbose) 298 device_printf(tp->dev, "CONNECTED\n"); 299 ATA_RESET(tp->dev); 300 ata_identify(tp->dev); 301 } 302 if (tp->action == ATA_C_DETACH) { 303 if (!device_get_children(tp->dev, &children, &nchildren)) { 304 for (i = 0; i < nchildren; i++) 305 if (children[i]) 306 device_delete_child(tp->dev, children[i]); 307 kfree(children, M_TEMP); 308 } 309 spin_lock_wr(&ch->state_mtx); 310 ch->state = ATA_IDLE; 311 spin_unlock_wr(&ch->state_mtx); 312 if (bootverbose) 313 device_printf(tp->dev, "DISCONNECTED\n"); 314 } 315 rel_mplock(); 316 kfree(tp, M_ATA); 317 } 318 319 static int 320 ata_sata_phy_reset(device_t dev) 321 { 322 struct ata_channel *ch = device_get_softc(dev); 323 int loop, retry; 324 325 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 326 return ata_sata_connect(ch); 327 328 for (retry = 0; retry < 10; retry++) { 329 for (loop = 0; loop < 10; loop++) { 330 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET); 331 ata_udelay(100); 332 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & 333 ATA_SC_DET_MASK) == ATA_SC_DET_RESET) 334 break; 335 } 336 ata_udelay(5000); 337 for (loop = 0; loop < 10; loop++) { 338 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE | 339 ATA_SC_IPM_DIS_PARTIAL | 340 ATA_SC_IPM_DIS_SLUMBER); 341 ata_udelay(100); 342 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0) 343 return ata_sata_connect(ch); 344 } 345 } 346 return 0; 347 } 348 349 static int 350 ata_sata_connect(struct ata_channel *ch) 351 { 352 u_int32_t status; 353 int timeout; 354 355 /* wait up to 1 second for "connect well" */ 356 for (timeout = 0; timeout < 100 ; timeout++) { 357 status = ATA_IDX_INL(ch, ATA_SSTATUS); 358 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 || 359 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2) 360 break; 361 ata_udelay(10000); 362 } 363 if (timeout >= 100) { 364 if (bootverbose) 365 device_printf(ch->dev, "SATA connect status=%08x\n", status); 366 return 0; 367 } 368 369 if (bootverbose) 370 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10); 371 372 /* clear SATA error register */ 373 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 374 375 return 1; 376 } 377 378 static void 379 ata_sata_setmode(device_t dev, int mode) 380 { 381 struct ata_device *atadev = device_get_softc(dev); 382 383 /* 384 * if we detect that the device isn't a real SATA device we limit 385 * the transfer mode to UDMA5/ATA100. 386 * this works around the problems some devices has with the 387 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133. 388 */ 389 if (atadev->param.satacapabilities != 0x0000 && 390 atadev->param.satacapabilities != 0xffff) { 391 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 392 393 /* on some drives we need to set the transfer mode */ 394 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 395 ata_limit_mode(dev, mode, ATA_UDMA6)); 396 397 /* query SATA STATUS for the speed */ 398 if (ch->r_io[ATA_SSTATUS].res && 399 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) == 400 ATA_SS_CONWELL_GEN2)) 401 atadev->mode = ATA_SA300; 402 else 403 atadev->mode = ATA_SA150; 404 } 405 else { 406 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 407 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 408 atadev->mode = mode; 409 } 410 } 411 412 static int 413 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis) 414 { 415 struct ata_device *atadev = device_get_softc(request->dev); 416 417 if (request->flags & ATA_R_ATAPI) { 418 fis[0] = 0x27; /* host to device */ 419 fis[1] = 0x80; /* command FIS (note PM goes here) */ 420 fis[2] = ATA_PACKET_CMD; 421 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) 422 fis[3] = ATA_F_DMA; 423 else { 424 fis[5] = request->transfersize; 425 fis[6] = request->transfersize >> 8; 426 } 427 fis[7] = ATA_D_LBA | atadev->unit; 428 fis[15] = ATA_A_4BIT; 429 return 20; 430 } 431 else { 432 ata_modify_if_48bit(request); 433 fis[0] = 0x27; /* host to device */ 434 fis[1] = 0x80; /* command FIS (note PM goes here) */ 435 fis[2] = request->u.ata.command; 436 fis[3] = request->u.ata.feature; 437 fis[4] = request->u.ata.lba; 438 fis[5] = request->u.ata.lba >> 8; 439 fis[6] = request->u.ata.lba >> 16; 440 fis[7] = ATA_D_LBA | atadev->unit; 441 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 442 fis[7] |= (request->u.ata.lba >> 24 & 0x0f); 443 fis[8] = request->u.ata.lba >> 24; 444 fis[9] = request->u.ata.lba >> 32; 445 fis[10] = request->u.ata.lba >> 40; 446 fis[11] = request->u.ata.feature >> 8; 447 fis[12] = request->u.ata.count; 448 fis[13] = request->u.ata.count >> 8; 449 fis[15] = ATA_A_4BIT; 450 return 20; 451 } 452 return 0; 453 } 454 455 /* 456 * AHCI v1.x compliant SATA chipset support functions 457 */ 458 int 459 ata_ahci_ident(device_t dev) 460 { 461 struct ata_pci_controller *ctlr = device_get_softc(dev); 462 static struct ata_chip_id id = {0, 0, 0, 0x00, ATA_SA300, "AHCI"}; 463 char buffer[64]; 464 465 if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0) 466 return ENXIO; 467 468 if (bootverbose) 469 ksnprintf(buffer, sizeof(buffer), "%s (ID=%08x) AHCI controller", 470 ata_pcivendor2str(dev), pci_get_devid(dev)); 471 else 472 ksnprintf(buffer, sizeof(buffer), "%s AHCI controller", 473 ata_pcivendor2str(dev)); 474 device_set_desc_copy(dev, buffer); 475 ctlr->chip = &id; 476 ctlr->chipinit = ata_ahci_chipinit; 477 return 0; 478 } 479 480 481 /* 482 * AHCI v1.x compliant SATA chipset support functions 483 */ 484 int 485 ata_ahci_chipinit(device_t dev) 486 { 487 struct ata_pci_controller *ctlr = device_get_softc(dev); 488 u_int32_t version; 489 int unit; 490 491 /* if we have a memory BAR(5) we are likely on an AHCI part */ 492 ctlr->r_type2 = SYS_RES_MEMORY; 493 ctlr->r_rid2 = PCIR_BAR(5); 494 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 495 &ctlr->r_rid2, RF_ACTIVE))) 496 return ENXIO; 497 498 /* setup interrupt delivery if not done allready by a vendor driver */ 499 if (!ctlr->r_irq) { 500 if (ata_setup_interrupt(dev)) 501 return ENXIO; 502 } 503 else 504 device_printf(dev, "AHCI called from vendor specific driver\n"); 505 506 /* enable AHCI mode */ 507 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 508 509 /* reset AHCI controller */ 510 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR); 511 DELAY(1000000); 512 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) { 513 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 514 device_printf(dev, "AHCI controller reset failure\n"); 515 return ENXIO; 516 } 517 518 /* reenable AHCI mode */ 519 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 520 521 /* get the number of HW channels */ 522 ctlr->channels = 523 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)), 524 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 525 526 /* disable interrupt sources and clear interrupts */ 527 for (unit = 0; unit < ctlr->channels; unit++) { 528 int offset = unit << 7; 529 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0); 530 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, -1); 531 } 532 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS)); 533 534 /* enable AHCI interrupts */ 535 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 536 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE); 537 538 ctlr->reset = ata_ahci_reset; 539 ctlr->dmainit = ata_ahci_dmainit; 540 ctlr->allocate = ata_ahci_allocate; 541 ctlr->setmode = ata_sata_setmode; 542 543 /* enable PCI interrupt */ 544 pci_write_config(dev, PCIR_COMMAND, 545 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 546 547 /* announce we support the HW */ 548 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS); 549 device_printf(dev, 550 "AHCI Version %x%x.%x%x controller with %d ports detected\n", 551 (version >> 24) & 0xff, (version >> 16) & 0xff, 552 (version >> 8) & 0xff, version & 0xff, 553 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 554 return 0; 555 } 556 557 static int 558 ata_ahci_allocate(device_t dev) 559 { 560 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 561 struct ata_channel *ch = device_get_softc(dev); 562 u_int64_t work; 563 int offset = ch->unit << 7; 564 565 /* set the SATA resources */ 566 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 567 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset; 568 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 569 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset; 570 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 571 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset; 572 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 573 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset; 574 575 ch->hw.status = ata_ahci_status; 576 ch->hw.begin_transaction = ata_ahci_begin_transaction; 577 ch->hw.end_transaction = ata_ahci_end_transaction; 578 ch->hw.command = NULL; /* not used here */ 579 580 /* setup work areas */ 581 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET; 582 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff); 583 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32); 584 585 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET; 586 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff); 587 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32); 588 589 /* enable wanted port interrupts */ 590 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 591 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF | 592 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF | 593 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP | 594 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS | 595 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR)); 596 597 /* start operations on this channel */ 598 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 599 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 600 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 601 return 0; 602 } 603 604 static int 605 ata_ahci_status(device_t dev) 606 { 607 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 608 struct ata_channel *ch = device_get_softc(dev); 609 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS); 610 int offset = ch->unit << 7; 611 int tag = 0; 612 613 if (action & (1 << ch->unit)) { 614 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset); 615 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset); 616 617 /* clear interrupt(s) */ 618 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit)); 619 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus); 620 621 /* do we have any PHY events ? */ 622 /* XXX SOS check istatus phy bits */ 623 ata_sata_phy_check_events(dev); 624 625 /* do we have a potentially hanging engine to take care of? */ 626 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) { 627 628 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 629 int timeout = 0; 630 631 /* kill off all activity on this channel */ 632 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 633 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 634 635 /* XXX SOS this is not entirely wrong */ 636 do { 637 DELAY(1000); 638 if (timeout++ > 500) { 639 device_printf(dev, "stopping AHCI engine failed\n"); 640 break; 641 } 642 } while (ATA_INL(ctlr->r_res2, 643 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 644 645 /* start operations on this channel */ 646 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 647 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 648 649 return 1; 650 } 651 else 652 return (!(cstatus & (1 << tag))); 653 } 654 return 0; 655 } 656 657 /* must be called with ATA channel locked and state_mtx held */ 658 static int 659 ata_ahci_begin_transaction(struct ata_request *request) 660 { 661 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 662 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 663 struct ata_ahci_cmd_tab *ctp; 664 struct ata_ahci_cmd_list *clp; 665 int offset = ch->unit << 7; 666 int tag = 0, entries = 0; 667 int fis_size; 668 669 /* get a piece of the workspace for this request */ 670 ctp = (struct ata_ahci_cmd_tab *) 671 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag)); 672 673 /* setup the FIS for this request */ 674 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) { 675 device_printf(request->dev, "setting up SATA FIS failed\n"); 676 request->result = EIO; 677 return ATA_OP_FINISHED; 678 } 679 680 /* if request moves data setup and load SG list */ 681 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 682 if (ch->dma->load(ch->dev, request->data, request->bytecount, 683 request->flags & ATA_R_READ, 684 ctp->prd_tab, &entries)) { 685 device_printf(request->dev, "setting up DMA failed\n"); 686 request->result = EIO; 687 return ATA_OP_FINISHED; 688 } 689 } 690 691 /* setup the command list entry */ 692 clp = (struct ata_ahci_cmd_list *) 693 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 694 695 clp->prd_length = entries; 696 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) | 697 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) | 698 (fis_size / sizeof(u_int32_t)); 699 clp->bytecount = 0; 700 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET + 701 (ATA_AHCI_CT_SIZE * tag)); 702 703 /* clear eventual ACTIVE bit */ 704 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag)); 705 706 /* set command type bit */ 707 if (request->flags & ATA_R_ATAPI) 708 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 709 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) | 710 ATA_AHCI_P_CMD_ATAPI); 711 else 712 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 713 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & 714 ~ATA_AHCI_P_CMD_ATAPI); 715 716 /* issue command to controller */ 717 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag)); 718 719 if (!(request->flags & ATA_R_ATAPI)) { 720 /* device reset doesn't interrupt */ 721 if (request->u.ata.command == ATA_DEVICE_RESET) { 722 u_int32_t tf_data; 723 int timeout = 1000000; 724 725 do { 726 DELAY(10); 727 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7)); 728 } while ((tf_data & ATA_S_BUSY) && timeout--); 729 if (bootverbose) 730 device_printf(ch->dev, "device_reset timeout=%dus\n", 731 (1000000-timeout)*10); 732 request->status = tf_data; 733 if (request->status & ATA_S_ERROR) 734 request->error = tf_data >> 8; 735 return ATA_OP_FINISHED; 736 } 737 } 738 739 /* start the timeout */ 740 callout_reset(&request->callout, request->timeout * hz, 741 (timeout_t*)ata_timeout, request); 742 return ATA_OP_CONTINUES; 743 } 744 745 /* must be called with ATA channel locked and state_mtx held */ 746 static int 747 ata_ahci_end_transaction(struct ata_request *request) 748 { 749 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 750 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 751 struct ata_ahci_cmd_list *clp; 752 u_int32_t tf_data; 753 int offset = ch->unit << 7; 754 int tag = 0; 755 756 /* kill the timeout */ 757 callout_stop(&request->callout); 758 759 /* get status */ 760 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset); 761 request->status = tf_data; 762 763 /* if error status get details */ 764 if (request->status & ATA_S_ERROR) 765 request->error = tf_data >> 8; 766 767 /* record how much data we actually moved */ 768 clp = (struct ata_ahci_cmd_list *) 769 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 770 request->donecount = clp->bytecount; 771 772 /* release SG list etc */ 773 ch->dma->unload(ch->dev); 774 775 return ATA_OP_FINISHED; 776 } 777 778 static void 779 ata_ahci_reset(device_t dev) 780 { 781 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 782 struct ata_channel *ch = device_get_softc(dev); 783 u_int32_t cmd, signature; 784 int offset = ch->unit << 7; 785 int timeout; 786 787 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) { 788 device_printf(dev, "port not implemented\n"); 789 return; 790 } 791 ch->devices = 0; 792 793 /* kill off all activity on this channel */ 794 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 795 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 796 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 797 798 /* XXX SOS this is not entirely wrong */ 799 timeout = 0; 800 do { 801 DELAY(1000); 802 if (timeout++ > 500) { 803 device_printf(dev, "stopping AHCI engine failed\n"); 804 break; 805 } 806 } 807 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 808 809 /* issue Command List Override if supported */ 810 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) { 811 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 812 cmd |= ATA_AHCI_P_CMD_CLO; 813 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd); 814 timeout = 0; 815 do { 816 DELAY(1000); 817 if (timeout++ > 500) { 818 device_printf(dev, "executing CLO failed\n"); 819 break; 820 } 821 } 822 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO); 823 } 824 825 /* reset PHY and decide what is present */ 826 if (ata_sata_phy_reset(dev)) { 827 828 /* clear any interrupts pending on this channel */ 829 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, 830 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset)); 831 832 /* clear SATA error register */ 833 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 834 835 /* start operations on this channel */ 836 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 837 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 838 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 839 840 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset); 841 switch (signature) { 842 case 0x00000101: 843 ch->devices = ATA_ATA_MASTER; 844 break; 845 case 0x96690101: 846 ch->devices = ATA_PORTMULTIPLIER; 847 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 848 ch->devices = 0; 849 break; 850 case 0xeb140101: 851 ch->devices = ATA_ATAPI_MASTER; 852 break; 853 default: /* SOS XXX */ 854 if (bootverbose) 855 device_printf(ch->dev, "No signature, assuming disk device\n"); 856 ch->devices = ATA_ATA_MASTER; 857 } 858 } 859 if (bootverbose) 860 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices, 861 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 862 } 863 864 static void 865 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 866 { 867 struct ata_dmasetprd_args *args = xsc; 868 struct ata_ahci_dma_prd *prd = args->dmatab; 869 int i; 870 871 if (!(args->error = error)) { 872 for (i = 0; i < nsegs; i++) { 873 prd[i].dba = htole64(segs[i].ds_addr); 874 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK); 875 } 876 } 877 args->nsegs = nsegs; 878 } 879 880 static void 881 ata_ahci_dmainit(device_t dev) 882 { 883 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 884 struct ata_channel *ch = device_get_softc(dev); 885 886 ata_dmainit(dev); 887 if (ch->dma) { 888 /* note start and stop are not used here */ 889 ch->dma->setprd = ata_ahci_dmasetprd; 890 ch->dma->max_iosize = 8192 * DEV_BSIZE; 891 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT) 892 ch->dma->max_address = BUS_SPACE_MAXADDR; 893 } 894 } 895 896 static int 897 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request) 898 { 899 bzero(ctp->cfis, 64); 900 if (request->flags & ATA_R_ATAPI) { 901 bzero(ctp->acmd, 32); 902 bcopy(request->u.atapi.ccb, ctp->acmd, 16); 903 } 904 return ata_request2fis_h2d(request, &ctp->cfis[0]); 905 } 906 907 /* 908 * Acard chipset support functions 909 */ 910 int 911 ata_acard_ident(device_t dev) 912 { 913 struct ata_pci_controller *ctlr = device_get_softc(dev); 914 struct ata_chip_id *idx; 915 static struct ata_chip_id ids[] = 916 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" }, 917 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" }, 918 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" }, 919 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" }, 920 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" }, 921 { 0, 0, 0, 0, 0, 0}}; 922 char buffer[64]; 923 924 if (!(idx = ata_match_chip(dev, ids))) 925 return ENXIO; 926 927 ksprintf(buffer, "Acard %s %s controller", 928 idx->text, ata_mode2str(idx->max_dma)); 929 device_set_desc_copy(dev, buffer); 930 ctlr->chip = idx; 931 ctlr->chipinit = ata_acard_chipinit; 932 return 0; 933 } 934 935 static int 936 ata_acard_chipinit(device_t dev) 937 { 938 struct ata_pci_controller *ctlr = device_get_softc(dev); 939 940 if (ata_setup_interrupt(dev)) 941 return ENXIO; 942 943 ctlr->allocate = ata_acard_allocate; 944 if (ctlr->chip->cfg1 == ATPOLD) { 945 ctlr->setmode = ata_acard_850_setmode; 946 ctlr->locking = ata_serialize; 947 } 948 else 949 ctlr->setmode = ata_acard_86X_setmode; 950 return 0; 951 } 952 953 static int 954 ata_acard_allocate(device_t dev) 955 { 956 struct ata_channel *ch = device_get_softc(dev); 957 958 /* setup the usual register normal pci style */ 959 if (ata_pci_allocate(dev)) 960 return ENXIO; 961 962 ch->hw.status = ata_acard_status; 963 return 0; 964 } 965 966 static int 967 ata_acard_status(device_t dev) 968 { 969 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 970 struct ata_channel *ch = device_get_softc(dev); 971 972 if (ctlr->chip->cfg1 == ATPOLD && 973 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit) 974 return 0; 975 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) { 976 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 977 978 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != 979 ATA_BMSTAT_INTERRUPT) 980 return 0; 981 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR); 982 DELAY(1); 983 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 984 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 985 DELAY(1); 986 } 987 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 988 DELAY(100); 989 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 990 return 0; 991 } 992 return 1; 993 } 994 995 static void 996 ata_acard_850_setmode(device_t dev, int mode) 997 { 998 device_t gparent = GRANDPARENT(dev); 999 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1000 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1001 struct ata_device *atadev = device_get_softc(dev); 1002 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1003 int error; 1004 1005 mode = ata_limit_mode(dev, mode, 1006 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 1007 1008 /* XXX SOS missing WDMA0+1 + PIO modes */ 1009 if (mode >= ATA_WDMA2) { 1010 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1011 if (bootverbose) 1012 device_printf(dev, "%ssetting %s on %s chip\n", 1013 (error) ? "FAILURE " : "", 1014 ata_mode2str(mode), ctlr->chip->text); 1015 if (!error) { 1016 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1); 1017 1018 reg54 &= ~(0x03 << (devno << 1)); 1019 if (mode >= ATA_UDMA0) 1020 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1)); 1021 pci_write_config(gparent, 0x54, reg54, 1); 1022 pci_write_config(gparent, 0x4a, 0xa6, 1); 1023 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2); 1024 atadev->mode = mode; 1025 return; 1026 } 1027 } 1028 /* we could set PIO mode timings, but we assume the BIOS did that */ 1029 } 1030 1031 static void 1032 ata_acard_86X_setmode(device_t dev, int mode) 1033 { 1034 device_t gparent = GRANDPARENT(dev); 1035 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1036 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1037 struct ata_device *atadev = device_get_softc(dev); 1038 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1039 int error; 1040 1041 1042 mode = ata_limit_mode(dev, mode, 1043 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 1044 1045 mode = ata_check_80pin(dev, mode); 1046 1047 /* XXX SOS missing WDMA0+1 + PIO modes */ 1048 if (mode >= ATA_WDMA2) { 1049 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1050 if (bootverbose) 1051 device_printf(dev, "%ssetting %s on %s chip\n", 1052 (error) ? "FAILURE " : "", 1053 ata_mode2str(mode), ctlr->chip->text); 1054 if (!error) { 1055 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2); 1056 1057 reg44 &= ~(0x000f << (devno << 2)); 1058 if (mode >= ATA_UDMA0) 1059 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2)); 1060 pci_write_config(gparent, 0x44, reg44, 2); 1061 pci_write_config(gparent, 0x4a, 0xa6, 1); 1062 pci_write_config(gparent, 0x40 + devno, 0x31, 1); 1063 atadev->mode = mode; 1064 return; 1065 } 1066 } 1067 /* we could set PIO mode timings, but we assume the BIOS did that */ 1068 } 1069 1070 1071 /* 1072 * Acer Labs Inc (ALI) chipset support functions 1073 */ 1074 int 1075 ata_ali_ident(device_t dev) 1076 { 1077 struct ata_pci_controller *ctlr = device_get_softc(dev); 1078 struct ata_chip_id *idx; 1079 static struct ata_chip_id ids[] = 1080 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" }, 1081 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" }, 1082 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" }, 1083 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" }, 1084 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" }, 1085 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" }, 1086 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" }, 1087 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" }, 1088 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" }, 1089 { 0, 0, 0, 0, 0, 0}}; 1090 char buffer[64]; 1091 1092 if (!(idx = ata_match_chip(dev, ids))) 1093 return ENXIO; 1094 1095 ksprintf(buffer, "AcerLabs %s %s controller", 1096 idx->text, ata_mode2str(idx->max_dma)); 1097 device_set_desc_copy(dev, buffer); 1098 ctlr->chip = idx; 1099 ctlr->chipinit = ata_ali_chipinit; 1100 return 0; 1101 } 1102 1103 static int 1104 ata_ali_chipinit(device_t dev) 1105 { 1106 struct ata_pci_controller *ctlr = device_get_softc(dev); 1107 1108 if (ata_setup_interrupt(dev)) 1109 return ENXIO; 1110 1111 switch (ctlr->chip->cfg2) { 1112 case ALISATA: 1113 ctlr->channels = ctlr->chip->cfg1; 1114 ctlr->allocate = ata_ali_sata_allocate; 1115 ctlr->setmode = ata_sata_setmode; 1116 1117 /* AHCI mode is correctly supported only on the ALi 5288. */ 1118 if ((ctlr->chip->chipid == ATA_ALI_5288) && 1119 (ata_ahci_chipinit(dev) != ENXIO)) 1120 return 0; 1121 1122 /* enable PCI interrupt */ 1123 pci_write_config(dev, PCIR_COMMAND, 1124 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1125 break; 1126 1127 case ALINEW: 1128 /* use device interrupt as byte count end */ 1129 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1); 1130 1131 /* enable cable detection and UDMA support on newer chips */ 1132 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1); 1133 1134 /* enable ATAPI UDMA mode */ 1135 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1); 1136 1137 /* only chips with revision > 0xc4 can do 48bit DMA */ 1138 if (ctlr->chip->chiprev <= 0xc4) 1139 device_printf(dev, 1140 "using PIO transfers above 137GB as workaround for " 1141 "48bit DMA access bug, expect reduced performance\n"); 1142 ctlr->allocate = ata_ali_allocate; 1143 ctlr->reset = ata_ali_reset; 1144 ctlr->setmode = ata_ali_setmode; 1145 break; 1146 1147 case ALIOLD: 1148 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */ 1149 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1); 1150 ctlr->setmode = ata_ali_setmode; 1151 break; 1152 } 1153 return 0; 1154 } 1155 1156 static int 1157 ata_ali_allocate(device_t dev) 1158 { 1159 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1160 struct ata_channel *ch = device_get_softc(dev); 1161 1162 /* setup the usual register normal pci style */ 1163 if (ata_pci_allocate(dev)) 1164 return ENXIO; 1165 1166 /* older chips can't do 48bit DMA transfers */ 1167 if (ctlr->chip->chiprev <= 0xc4) 1168 ch->flags |= ATA_NO_48BIT_DMA; 1169 1170 return 0; 1171 } 1172 1173 static int 1174 ata_ali_sata_allocate(device_t dev) 1175 { 1176 device_t parent = device_get_parent(dev); 1177 struct ata_pci_controller *ctlr = device_get_softc(parent); 1178 struct ata_channel *ch = device_get_softc(dev); 1179 struct resource *io = NULL, *ctlio = NULL; 1180 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 1181 int i, rid; 1182 1183 rid = PCIR_BAR(0) + (unit01 ? 8 : 0); 1184 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1185 if (!io) 1186 return ENXIO; 1187 1188 rid = PCIR_BAR(1) + (unit01 ? 8 : 0); 1189 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1190 if (!ctlio) { 1191 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io); 1192 return ENXIO; 1193 } 1194 1195 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 1196 ch->r_io[i].res = io; 1197 ch->r_io[i].offset = i + (unit10 ? 8 : 0); 1198 } 1199 ch->r_io[ATA_CONTROL].res = ctlio; 1200 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0); 1201 ch->r_io[ATA_IDX_ADDR].res = io; 1202 ata_default_registers(dev); 1203 if (ctlr->r_res1) { 1204 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 1205 ch->r_io[i].res = ctlr->r_res1; 1206 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 1207 } 1208 } 1209 ch->flags |= ATA_NO_SLAVE; 1210 1211 /* XXX SOS PHY handling awkward in ALI chip not supported yet */ 1212 ata_pci_hw(dev); 1213 return 0; 1214 } 1215 1216 static void 1217 ata_ali_reset(device_t dev) 1218 { 1219 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1220 struct ata_channel *ch = device_get_softc(dev); 1221 device_t *children; 1222 int nchildren, i; 1223 1224 ata_generic_reset(dev); 1225 1226 /* 1227 * workaround for datacorruption bug found on at least SUN Blade-100 1228 * find the ISA function on the southbridge and disable then enable 1229 * the ATA channel tristate buffer 1230 */ 1231 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) { 1232 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) { 1233 for (i = 0; i < nchildren; i++) { 1234 if (pci_get_devid(children[i]) == ATA_ALI_1533) { 1235 pci_write_config(children[i], 0x58, 1236 pci_read_config(children[i], 0x58, 1) & 1237 ~(0x04 << ch->unit), 1); 1238 pci_write_config(children[i], 0x58, 1239 pci_read_config(children[i], 0x58, 1) | 1240 (0x04 << ch->unit), 1); 1241 break; 1242 } 1243 } 1244 kfree(children, M_TEMP); 1245 } 1246 } 1247 } 1248 1249 static void 1250 ata_ali_setmode(device_t dev, int mode) 1251 { 1252 device_t gparent = GRANDPARENT(dev); 1253 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1254 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1255 struct ata_device *atadev = device_get_softc(dev); 1256 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1257 int error; 1258 1259 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1260 1261 if (ctlr->chip->cfg2 & ALINEW) { 1262 if (mode > ATA_UDMA2 && 1263 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) { 1264 ata_print_cable(dev, "controller"); 1265 mode = ATA_UDMA2; 1266 } 1267 } 1268 else 1269 mode = ata_check_80pin(dev, mode); 1270 1271 if (ctlr->chip->cfg2 & ALIOLD) { 1272 /* doesn't support ATAPI DMA on write */ 1273 ch->flags |= ATA_ATAPI_DMA_RO; 1274 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) { 1275 /* doesn't support ATAPI DMA on two ATAPI devices */ 1276 device_printf(dev, "two atapi devices on this channel, no DMA\n"); 1277 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1278 } 1279 } 1280 1281 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1282 1283 if (bootverbose) 1284 device_printf(dev, "%ssetting %s on %s chip\n", 1285 (error) ? "FAILURE " : "", 1286 ata_mode2str(mode), ctlr->chip->text); 1287 if (!error) { 1288 if (mode >= ATA_UDMA0) { 1289 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d}; 1290 u_int32_t word54 = pci_read_config(gparent, 0x54, 4); 1291 1292 word54 &= ~(0x000f000f << (devno << 2)); 1293 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2)); 1294 pci_write_config(gparent, 0x54, word54, 4); 1295 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1296 0x00310001, 4); 1297 } 1298 else { 1299 u_int32_t piotimings[] = 1300 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001, 1301 0x00310001, 0x00440001, 0x00330001, 0x00310001}; 1302 1303 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) & 1304 ~(0x0008000f << (devno << 2)), 4); 1305 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1306 piotimings[ata_mode2idx(mode)], 4); 1307 } 1308 atadev->mode = mode; 1309 } 1310 } 1311 1312 1313 /* 1314 * American Micro Devices (AMD) chipset support functions 1315 */ 1316 int 1317 ata_amd_ident(device_t dev) 1318 { 1319 struct ata_pci_controller *ctlr = device_get_softc(dev); 1320 struct ata_chip_id *idx; 1321 static struct ata_chip_id ids[] = 1322 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" }, 1323 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" }, 1324 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" }, 1325 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" }, 1326 { 0, 0, 0, 0, 0, 0}}; 1327 char buffer[64]; 1328 1329 if (!(idx = ata_match_chip(dev, ids))) 1330 return ENXIO; 1331 1332 ksprintf(buffer, "AMD %s %s controller", 1333 idx->text, ata_mode2str(idx->max_dma)); 1334 device_set_desc_copy(dev, buffer); 1335 ctlr->chip = idx; 1336 ctlr->chipinit = ata_amd_chipinit; 1337 return 0; 1338 } 1339 1340 static int 1341 ata_amd_chipinit(device_t dev) 1342 { 1343 struct ata_pci_controller *ctlr = device_get_softc(dev); 1344 1345 if (ata_setup_interrupt(dev)) 1346 return ENXIO; 1347 1348 /* disable/set prefetch, postwrite */ 1349 if (ctlr->chip->cfg2 & AMDBUG) 1350 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1); 1351 else 1352 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); 1353 1354 ctlr->setmode = ata_via_family_setmode; 1355 return 0; 1356 } 1357 1358 1359 /* 1360 * ATI chipset support functions 1361 */ 1362 int 1363 ata_ati_ident(device_t dev) 1364 { 1365 struct ata_pci_controller *ctlr = device_get_softc(dev); 1366 struct ata_chip_id *idx; 1367 static struct ata_chip_id ids[] = 1368 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" }, 1369 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" }, 1370 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" }, 1371 { ATA_ATI_SB600, 0x00, 0, 0, ATA_UDMA6, "SB600" }, 1372 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" }, 1373 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1374 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1375 { ATA_ATI_SB600_S1, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1376 { ATA_ATI_SB600_S2, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1377 { 0, 0, 0, 0, 0, 0}}; 1378 char buffer[64]; 1379 1380 if (!(idx = ata_match_chip(dev, ids))) 1381 return ENXIO; 1382 1383 ksprintf(buffer, "ATI %s %s controller", 1384 idx->text, ata_mode2str(idx->max_dma)); 1385 device_set_desc_copy(dev, buffer); 1386 ctlr->chip = idx; 1387 1388 /* 1389 * The ATI SATA controllers are actually a SiI 3112 controller, except 1390 * for the SB600. 1391 */ 1392 if (ctlr->chip->cfg1 & SIIMEMIO) 1393 ctlr->chipinit = ata_sii_chipinit; 1394 else 1395 ctlr->chipinit = ata_ati_chipinit; 1396 return 0; 1397 } 1398 1399 static int 1400 ata_ati_chipinit(device_t dev) 1401 { 1402 struct ata_pci_controller *ctlr = device_get_softc(dev); 1403 1404 if (ata_setup_interrupt(dev)) 1405 return ENXIO; 1406 1407 /* The SB600 needs special treatment. */ 1408 if (ctlr->chip->cfg1 & ATIAHCI) { 1409 /* Check if the chip is configured as an AHCI part. */ 1410 if ((pci_get_subclass(dev) == PCIS_STORAGE_SATA) && 1411 (pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI_1_0)) { 1412 if (ata_ahci_chipinit(dev) != ENXIO) 1413 return 0; 1414 } 1415 } 1416 1417 ctlr->setmode = ata_ati_setmode; 1418 return 0; 1419 } 1420 1421 static void 1422 ata_ati_setmode(device_t dev, int mode) 1423 { 1424 device_t gparent = GRANDPARENT(dev); 1425 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1426 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1427 struct ata_device *atadev = device_get_softc(dev); 1428 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1429 int offset = (devno ^ 0x01) << 3; 1430 int error; 1431 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 1432 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 1433 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 1434 1435 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1436 1437 mode = ata_check_80pin(dev, mode); 1438 1439 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1440 1441 if (bootverbose) 1442 device_printf(dev, "%ssetting %s on %s chip\n", 1443 (error) ? "FAILURE " : "", 1444 ata_mode2str(mode), ctlr->chip->text); 1445 if (!error) { 1446 if (mode >= ATA_UDMA0) { 1447 pci_write_config(gparent, 0x56, 1448 (pci_read_config(gparent, 0x56, 2) & 1449 ~(0xf << (devno << 2))) | 1450 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 1451 pci_write_config(gparent, 0x54, 1452 pci_read_config(gparent, 0x54, 1) | 1453 (0x01 << devno), 1); 1454 pci_write_config(gparent, 0x44, 1455 (pci_read_config(gparent, 0x44, 4) & 1456 ~(0xff << offset)) | 1457 (dmatimings[2] << offset), 4); 1458 } 1459 else if (mode >= ATA_WDMA0) { 1460 pci_write_config(gparent, 0x54, 1461 pci_read_config(gparent, 0x54, 1) & 1462 ~(0x01 << devno), 1); 1463 pci_write_config(gparent, 0x44, 1464 (pci_read_config(gparent, 0x44, 4) & 1465 ~(0xff << offset)) | 1466 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 1467 } 1468 else 1469 pci_write_config(gparent, 0x54, 1470 pci_read_config(gparent, 0x54, 1) & 1471 ~(0x01 << devno), 1); 1472 1473 pci_write_config(gparent, 0x4a, 1474 (pci_read_config(gparent, 0x4a, 2) & 1475 ~(0xf << (devno << 2))) | 1476 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2); 1477 pci_write_config(gparent, 0x40, 1478 (pci_read_config(gparent, 0x40, 4) & 1479 ~(0xff << offset)) | 1480 (piotimings[ata_mode2idx(mode)] << offset), 4); 1481 atadev->mode = mode; 1482 } 1483 } 1484 1485 /* 1486 * Cyrix chipset support functions 1487 */ 1488 int 1489 ata_cyrix_ident(device_t dev) 1490 { 1491 struct ata_pci_controller *ctlr = device_get_softc(dev); 1492 1493 if (pci_get_devid(dev) == ATA_CYRIX_5530) { 1494 device_set_desc(dev, "Cyrix 5530 ATA33 controller"); 1495 ctlr->chipinit = ata_cyrix_chipinit; 1496 return 0; 1497 } 1498 return ENXIO; 1499 } 1500 1501 static int 1502 ata_cyrix_chipinit(device_t dev) 1503 { 1504 struct ata_pci_controller *ctlr = device_get_softc(dev); 1505 1506 if (ata_setup_interrupt(dev)) 1507 return ENXIO; 1508 1509 if (ctlr->r_res1) 1510 ctlr->setmode = ata_cyrix_setmode; 1511 else 1512 ctlr->setmode = ata_generic_setmode; 1513 return 0; 1514 } 1515 1516 static void 1517 ata_cyrix_setmode(device_t dev, int mode) 1518 { 1519 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1520 struct ata_device *atadev = device_get_softc(dev); 1521 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1522 u_int32_t piotiming[] = 1523 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 }; 1524 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 }; 1525 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 }; 1526 int error; 1527 1528 ch->dma->alignment = 16; 1529 ch->dma->max_iosize = 126 * DEV_BSIZE; 1530 1531 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 1532 1533 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1534 1535 if (bootverbose) 1536 device_printf(dev, "%ssetting %s on Cyrix chip\n", 1537 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1538 if (!error) { 1539 if (mode >= ATA_UDMA0) { 1540 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1541 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]); 1542 } 1543 else if (mode >= ATA_WDMA0) { 1544 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1545 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]); 1546 } 1547 else { 1548 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1549 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]); 1550 } 1551 atadev->mode = mode; 1552 } 1553 } 1554 1555 1556 /* 1557 * Cypress chipset support functions 1558 */ 1559 int 1560 ata_cypress_ident(device_t dev) 1561 { 1562 struct ata_pci_controller *ctlr = device_get_softc(dev); 1563 1564 /* 1565 * the Cypress chip is a mess, it contains two ATA functions, but 1566 * both channels are visible on the first one. 1567 * simply ignore the second function for now, as the right 1568 * solution (ignoring the second channel on the first function) 1569 * doesn't work with the crappy ATA interrupt setup on the alpha. 1570 */ 1571 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 && 1572 pci_get_function(dev) == 1 && 1573 pci_get_subclass(dev) == PCIS_STORAGE_IDE) { 1574 device_set_desc(dev, "Cypress 82C693 ATA controller"); 1575 ctlr->chipinit = ata_cypress_chipinit; 1576 return 0; 1577 } 1578 return ENXIO; 1579 } 1580 1581 static int 1582 ata_cypress_chipinit(device_t dev) 1583 { 1584 struct ata_pci_controller *ctlr = device_get_softc(dev); 1585 1586 if (ata_setup_interrupt(dev)) 1587 return ENXIO; 1588 1589 ctlr->setmode = ata_cypress_setmode; 1590 return 0; 1591 } 1592 1593 static void 1594 ata_cypress_setmode(device_t dev, int mode) 1595 { 1596 device_t gparent = GRANDPARENT(dev); 1597 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1598 struct ata_device *atadev = device_get_softc(dev); 1599 int error; 1600 1601 mode = ata_limit_mode(dev, mode, ATA_WDMA2); 1602 1603 /* XXX SOS missing WDMA0+1 + PIO modes */ 1604 if (mode == ATA_WDMA2) { 1605 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1606 if (bootverbose) 1607 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n", 1608 error ? "FAILURE " : ""); 1609 if (!error) { 1610 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2); 1611 atadev->mode = mode; 1612 return; 1613 } 1614 } 1615 /* we could set PIO mode timings, but we assume the BIOS did that */ 1616 } 1617 1618 1619 /* 1620 * HighPoint chipset support functions 1621 */ 1622 int 1623 ata_highpoint_ident(device_t dev) 1624 { 1625 struct ata_pci_controller *ctlr = device_get_softc(dev); 1626 struct ata_chip_id *idx; 1627 static struct ata_chip_id ids[] = 1628 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" }, 1629 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" }, 1630 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1631 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" }, 1632 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1633 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" }, 1634 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" }, 1635 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" }, 1636 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" }, 1637 { 0, 0, 0, 0, 0, 0}}; 1638 char buffer[64]; 1639 1640 if (!(idx = ata_match_chip(dev, ids))) 1641 return ENXIO; 1642 1643 strcpy(buffer, "HighPoint "); 1644 strcat(buffer, idx->text); 1645 if (idx->cfg1 == HPT374) { 1646 if (pci_get_function(dev) == 0) 1647 strcat(buffer, " (channel 0+1)"); 1648 if (pci_get_function(dev) == 1) 1649 strcat(buffer, " (channel 2+3)"); 1650 } 1651 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 1652 device_set_desc_copy(dev, buffer); 1653 ctlr->chip = idx; 1654 ctlr->chipinit = ata_highpoint_chipinit; 1655 return 0; 1656 } 1657 1658 static int 1659 ata_highpoint_chipinit(device_t dev) 1660 { 1661 struct ata_pci_controller *ctlr = device_get_softc(dev); 1662 1663 if (ata_setup_interrupt(dev)) 1664 return ENXIO; 1665 1666 if (ctlr->chip->cfg2 == HPTOLD) { 1667 /* disable interrupt prediction */ 1668 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 1669 } 1670 else { 1671 /* disable interrupt prediction */ 1672 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 1673 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 1674 1675 /* enable interrupts */ 1676 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 1677 1678 /* set clocks etc */ 1679 if (ctlr->chip->cfg1 < HPT372) 1680 pci_write_config(dev, 0x5b, 0x22, 1); 1681 else 1682 pci_write_config(dev, 0x5b, 1683 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 1684 } 1685 ctlr->allocate = ata_highpoint_allocate; 1686 ctlr->setmode = ata_highpoint_setmode; 1687 return 0; 1688 } 1689 1690 static int 1691 ata_highpoint_allocate(device_t dev) 1692 { 1693 struct ata_channel *ch = device_get_softc(dev); 1694 1695 /* setup the usual register normal pci style */ 1696 if (ata_pci_allocate(dev)) 1697 return ENXIO; 1698 1699 ch->flags |= ATA_ALWAYS_DMASTAT; 1700 return 0; 1701 } 1702 1703 static void 1704 ata_highpoint_setmode(device_t dev, int mode) 1705 { 1706 device_t gparent = GRANDPARENT(dev); 1707 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1708 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1709 struct ata_device *atadev = device_get_softc(dev); 1710 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1711 int error; 1712 u_int32_t timings33[][4] = { 1713 /* HPT366 HPT370 HPT372 HPT374 mode */ 1714 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */ 1715 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */ 1716 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */ 1717 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */ 1718 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */ 1719 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */ 1720 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */ 1721 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */ 1722 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */ 1723 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */ 1724 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */ 1725 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */ 1726 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */ 1727 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */ 1728 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */ 1729 }; 1730 1731 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1732 1733 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev)) 1734 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1735 1736 mode = ata_highpoint_check_80pin(dev, mode); 1737 1738 /* 1739 * most if not all HPT chips cant really handle that the device is 1740 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to 1741 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance 1742 */ 1743 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 1744 ata_limit_mode(dev, mode, ATA_UDMA5)); 1745 if (bootverbose) 1746 device_printf(dev, "%ssetting %s on HighPoint chip\n", 1747 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1748 if (!error) 1749 pci_write_config(gparent, 0x40 + (devno << 2), 1750 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 1751 atadev->mode = mode; 1752 } 1753 1754 static int 1755 ata_highpoint_check_80pin(device_t dev, int mode) 1756 { 1757 device_t gparent = GRANDPARENT(dev); 1758 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1759 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1760 u_int8_t reg, val, res; 1761 1762 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) { 1763 reg = ch->unit ? 0x57 : 0x53; 1764 val = pci_read_config(gparent, reg, 1); 1765 pci_write_config(gparent, reg, val | 0x80, 1); 1766 } 1767 else { 1768 reg = 0x5b; 1769 val = pci_read_config(gparent, reg, 1); 1770 pci_write_config(gparent, reg, val & 0xfe, 1); 1771 } 1772 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2); 1773 pci_write_config(gparent, reg, val, 1); 1774 1775 if (mode > ATA_UDMA2 && res) { 1776 ata_print_cable(dev, "controller"); 1777 mode = ATA_UDMA2; 1778 } 1779 return mode; 1780 } 1781 1782 1783 /* 1784 * Intel chipset support functions 1785 */ 1786 int 1787 ata_intel_ident(device_t dev) 1788 { 1789 struct ata_pci_controller *ctlr = device_get_softc(dev); 1790 struct ata_chip_id *idx; 1791 static struct ata_chip_id ids[] = 1792 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" }, 1793 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" }, 1794 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1795 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1796 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1797 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" }, 1798 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1799 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1800 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1801 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1802 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1803 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1804 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1805 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1806 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" }, 1807 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1808 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1809 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" }, 1810 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1811 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1812 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" }, 1813 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1814 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1815 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" }, 1816 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" }, 1817 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1818 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1819 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1820 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1821 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1822 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1823 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" }, 1824 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1825 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1826 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1827 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1828 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1829 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1830 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1831 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1832 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1833 { ATA_I82801HBM_S1, 0, 0, 0x00, ATA_SA300, "ICH8M" }, 1834 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1835 { ATA_I82801HBM_S3, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1836 { ATA_I82801IB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1837 { ATA_I82801IB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1838 { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1839 { ATA_I82801IB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1840 { ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1841 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" }, 1842 { 0, 0, 0, 0, 0, 0}}; 1843 char buffer[64]; 1844 1845 if (!(idx = ata_match_chip(dev, ids))) 1846 return ENXIO; 1847 1848 ksprintf(buffer, "Intel %s %s controller", 1849 idx->text, ata_mode2str(idx->max_dma)); 1850 device_set_desc_copy(dev, buffer); 1851 ctlr->chip = idx; 1852 ctlr->chipinit = ata_intel_chipinit; 1853 return 0; 1854 } 1855 1856 static int 1857 ata_intel_chipinit(device_t dev) 1858 { 1859 struct ata_pci_controller *ctlr = device_get_softc(dev); 1860 1861 if (ata_setup_interrupt(dev)) 1862 return ENXIO; 1863 1864 /* good old PIIX needs special treatment (not implemented) */ 1865 if (ctlr->chip->chipid == ATA_I82371FB) { 1866 ctlr->setmode = ata_intel_old_setmode; 1867 } 1868 1869 /* the intel 31244 needs special care if in DPA mode */ 1870 else if (ctlr->chip->chipid == ATA_I31244) { 1871 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 1872 ctlr->r_type2 = SYS_RES_MEMORY; 1873 ctlr->r_rid2 = PCIR_BAR(0); 1874 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1875 &ctlr->r_rid2, 1876 RF_ACTIVE))) 1877 return ENXIO; 1878 ctlr->channels = 4; 1879 ctlr->allocate = ata_intel_31244_allocate; 1880 ctlr->reset = ata_intel_31244_reset; 1881 } 1882 ctlr->setmode = ata_sata_setmode; 1883 } 1884 1885 /* non SATA intel chips goes here */ 1886 else if (ctlr->chip->max_dma < ATA_SA150) { 1887 ctlr->allocate = ata_intel_allocate; 1888 ctlr->setmode = ata_intel_new_setmode; 1889 } 1890 1891 /* SATA parts can be either compat or AHCI */ 1892 else { 1893 /* force all ports active "the legacy way" */ 1894 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2); 1895 1896 ctlr->allocate = ata_intel_allocate; 1897 ctlr->reset = ata_intel_reset; 1898 1899 /* 1900 * if we have AHCI capability and BAR(5) as a memory resource 1901 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode 1902 */ 1903 if ((ctlr->chip->cfg1 == AHCI) && 1904 (pci_read_config(dev, 0x90, 1) & 0xc0) && 1905 (ata_ahci_chipinit(dev) != ENXIO)) 1906 return 0; 1907 1908 ctlr->setmode = ata_sata_setmode; 1909 1910 /* enable PCI interrupt */ 1911 pci_write_config(dev, PCIR_COMMAND, 1912 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1913 } 1914 return 0; 1915 } 1916 1917 static int 1918 ata_intel_allocate(device_t dev) 1919 { 1920 struct ata_channel *ch = device_get_softc(dev); 1921 1922 /* setup the usual register normal pci style */ 1923 if (ata_pci_allocate(dev)) 1924 return ENXIO; 1925 1926 ch->flags |= ATA_ALWAYS_DMASTAT; 1927 return 0; 1928 } 1929 1930 static void 1931 ata_intel_reset(device_t dev) 1932 { 1933 device_t parent = device_get_parent(dev); 1934 struct ata_pci_controller *ctlr = device_get_softc(parent); 1935 struct ata_channel *ch = device_get_softc(dev); 1936 int mask, timeout; 1937 1938 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */ 1939 if (ctlr->chip->cfg1) { 1940 mask = (0x0005 << ch->unit); 1941 } 1942 else { 1943 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */ 1944 if (pci_read_config(parent, 0x90, 1) & 0x04) 1945 mask = 0x0003; 1946 else { 1947 mask = (0x0001 << ch->unit); 1948 /* XXX SOS should be in intel_allocate if we grow it */ 1949 ch->flags |= ATA_NO_SLAVE; 1950 } 1951 } 1952 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2); 1953 DELAY(10); 1954 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2); 1955 1956 /* wait up to 1 sec for "connect well" */ 1957 for (timeout = 0; timeout < 100 ; timeout++) { 1958 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) && 1959 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 1960 break; 1961 ata_udelay(10000); 1962 } 1963 ata_generic_reset(dev); 1964 } 1965 1966 static void 1967 ata_intel_old_setmode(device_t dev, int mode) 1968 { 1969 /* NOT YET */ 1970 } 1971 1972 static void 1973 ata_intel_new_setmode(device_t dev, int mode) 1974 { 1975 device_t gparent = GRANDPARENT(dev); 1976 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1977 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1978 struct ata_device *atadev = device_get_softc(dev); 1979 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1980 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4); 1981 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1); 1982 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1); 1983 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2); 1984 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2); 1985 u_int32_t mask40 = 0, new40 = 0; 1986 u_int8_t mask44 = 0, new44 = 0; 1987 int error; 1988 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, 1989 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 }; 1990 /* PIO0 PIO1 PIO2 PIO3 PIO4 WDMA0 WDMA1 WDMA2 */ 1991 /* UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 UDMA5 UDMA6 */ 1992 1993 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1994 1995 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { 1996 ata_print_cable(dev, "controller"); 1997 mode = ATA_UDMA2; 1998 } 1999 2000 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2001 2002 if (bootverbose) 2003 device_printf(dev, "%ssetting %s on %s chip\n", 2004 (error) ? "FAILURE " : "", 2005 ata_mode2str(mode), ctlr->chip->text); 2006 if (error) 2007 return; 2008 2009 /* 2010 * reg48: 1 bit per (primary drive 0, primary drive 1, secondary 2011 * drive 0, secondary drive 1) 2012 * 2013 * 0 Disable Ultra DMA mode 2014 * 1 Enable Ultra DMA mode 2015 * 2016 * reg4a: 4 bits per (primary drive 0, primary drive 1, secondary 2017 * drive 0, secondary drive 1). 2018 * 0000 UDMA mode 0 2019 * 0001 UDMA mode 1, 3, 5 2020 * 0010 UDMA mode 2, 4, reserved 2021 * 0011 reserved 2022 * (top two bits for each drive reserved) 2023 */ 2024 #if 0 2025 device_printf(dev, 2026 "regs before 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 2027 reg40, reg44, reg48 ,reg4a, reg54); 2028 #endif 2029 reg48 &= ~(0x0001 << devno); 2030 reg4a &= ~(0x3 << (devno << 2)); 2031 if (mode >= ATA_UDMA0) { 2032 reg48 |= 0x0001 << devno; 2033 if (mode > ATA_UDMA0) 2034 reg4a |= (1 + !(mode & 0x01)) << (devno << 2); 2035 } 2036 pci_write_config(gparent, 0x48, reg48, 2); 2037 pci_write_config(gparent, 0x4a, reg4a, 2); 2038 2039 /* 2040 * reg54: 2041 * 2042 * 32:20 reserved 2043 * 19:18 Secondary ATA signal mode 2044 * 17:16 Primary ATA signal mode 2045 * 00 = Normal (enabled) 2046 * 01 = Tri-state (disabled) 2047 * 10 = Drive Low (disabled) 2048 * 11 = Reserved 2049 * 2050 * 15 Secondary drive 1 - Base Clock 2051 * 14 Secondary drive 0 - Base Clock 2052 * 13 Primary drive 1 - Base Clock 2053 * 12 Primary drive 0 - Base Clock 2054 * 0 = Select 33 MHz clock 2055 * 1 = Select 100 Mhz clock 2056 * 2057 * 11 Reserved 2058 * 10 Vendor specific (set by BIOS?) 2059 * 09:08 Reserved 2060 * 2061 * 07 Secondary drive 1 - Cable Type 2062 * 06 Secondary drive 0 - Cable Type 2063 * 05 Primary drive 1 - Cable Type 2064 * 04 Primary drive 0 - Cable Type 2065 * 0 = 40 Conductor 2066 * 1 = 80 Conductor (or high speed cable) 2067 * 2068 * 03 Secondary drive 1 - Select 33/66 clock 2069 * 02 Secondary drive 0 - Select 33/66 clock 2070 * 01 Primary drive 1 - Select 33/66 clock 2071 * 00 Primary drive 0 - Select 33/66 clock 2072 * 0 = Select 33 MHz 2073 * 1 = Select 66 MHz 2074 * 2075 * It is unclear what this should be set to when operating 2076 * in 100MHz mode. 2077 * 2078 * NOTE: UDMA2 = 33 MHz 2079 * UDMA3 = 40 MHz (?) - unsupported 2080 * UDMA4 = 66 MHz 2081 * UDMA5 = 100 MHz 2082 * UDMA6 = 133 Mhz 2083 */ 2084 reg54 |= 0x0400; /* set vendor specific bit */ 2085 reg54 &= ~((0x1 << devno) | (0x1000 << devno)); 2086 2087 if (mode >= ATA_UDMA5) 2088 reg54 |= (0x1000 << devno); 2089 else if (mode >= ATA_UDMA3) /* XXX should this be ATA_UDMA3 or 4? */ 2090 reg54 |= (0x1 << devno); 2091 2092 pci_write_config(gparent, 0x54, reg54, 2); 2093 2094 /* 2095 * Reg40 (32 bits... well, actually two 16 bit registers) 2096 * 2097 * Primary channel bits 15:00, Secondary channel bits 31:00. Note 2098 * that slave timings are handled in register 44. 2099 * 2100 * 15 ATA Decode Enable (R/W) 1 = enable decoding of I/O ranges 2101 * 2102 * 14 Slave ATA Timing Register Enable (R/W) 2103 * 2104 * 13:12 IORDY Sample Mode 2105 * 00 PIO-0 2106 * 01 PIO-2, SW-2 2107 * 10 PIO-3, PIO-4, MW-1, MW-2 2108 * 11 Reserved 2109 * 2110 * 11:10 Reserved 2111 * 2112 * 09:08 Recovery Mode 2113 * 00 PIO-0, PIO-2, SW-2 2114 * 01 PIO-3, MW-1 2115 * 10 Reserved 2116 * 11 PIO-4, MW-2 2117 * 2118 * 07:04 Secondary Device Control Bits 2119 * 03:00 Primary Device Control Bits 2120 * 2121 * bit 3 DMA Timing Enable 2122 * 2123 * bit 2 Indicate Presence of ATA(1) or ATAPI(0) device 2124 * 2125 * bit 1 Enable IORDY sample point capability for PIO 2126 * xfers. Always enabled for PIO4 and PIO3, enabled 2127 * for PIO2 if indicated by the device, and otherwise 2128 * probably should be 0. 2129 * 2130 * bit 0 Fast Drive Timing Enable. Enables faster then PIO-0 2131 * timing modes. 2132 */ 2133 2134 /* 2135 * Modify reg40 according to the table 2136 */ 2137 if (atadev->unit == ATA_MASTER) { 2138 mask40 = 0x3300; 2139 new40 = timings[ata_mode2idx(mode)] << 8; 2140 } 2141 else { 2142 mask44 = 0x0f; 2143 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) | 2144 (timings[ata_mode2idx(mode)] & 0x03); 2145 } 2146 2147 /* 2148 * Slave ATA timing register enable 2149 */ 2150 mask40 |= 0x4000; 2151 new40 |= 0x4000; 2152 2153 /* 2154 * Device control bits 3:0 for master, 7:4 for slave. 2155 * 2156 * bit3 DMA Timing enable. 2157 * bit2 Indicate presence of ATA(1) or ATAPI(0) device, set accordingly 2158 * bit1 Enable IORDY sample point capability for PIO xfers. Always 2159 * enabled for PIO4 and PIO3, enabled for PIO2 if indicated by 2160 * the device, and otherwise should be 0. 2161 * bit0 Fast Drive Timing Enable. Enable faster then PIO-0 timing modes. 2162 * 2163 * Set to: 0 x 1 1 2164 */ 2165 2166 if (atadev->unit == ATA_MASTER) { 2167 mask40 |= 0x0F; 2168 new40 |= 0x03; 2169 if (!ata_atapi(dev)) 2170 new40 |= 0x04; 2171 } else { 2172 mask40 |= 0xF0; 2173 new40 |= 0x30; 2174 if (!ata_atapi(dev)) 2175 new40 |= 0x40; 2176 } 2177 /* 2178 reg40 &= ~0x00ff00ff; 2179 reg40 |= 0x40774077; 2180 */ 2181 2182 /* 2183 * Primary or Secondary controller 2184 */ 2185 if (ch->unit) { 2186 mask40 <<= 16; 2187 new40 <<= 16; 2188 mask44 <<= 4; 2189 new44 <<= 4; 2190 } 2191 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4); 2192 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1); 2193 2194 #if 0 2195 reg40 = pci_read_config(gparent, 0x40, 4); 2196 reg44 = pci_read_config(gparent, 0x44, 1); 2197 reg48 = pci_read_config(gparent, 0x48, 1); 2198 reg4a = pci_read_config(gparent, 0x4a, 2); 2199 reg54 = pci_read_config(gparent, 0x54, 2); 2200 device_printf(dev, 2201 "regs after 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 2202 reg40, reg44, reg48 ,reg4a, reg54); 2203 #endif 2204 2205 atadev->mode = mode; 2206 } 2207 2208 static int 2209 ata_intel_31244_allocate(device_t dev) 2210 { 2211 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2212 struct ata_channel *ch = device_get_softc(dev); 2213 int i; 2214 int ch_offset; 2215 2216 ch_offset = 0x200 + ch->unit * 0x200; 2217 2218 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 2219 ch->r_io[i].res = ctlr->r_res2; 2220 2221 /* setup ATA registers */ 2222 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 2223 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 2224 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 2225 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 2226 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 2227 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 2228 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 2229 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 2230 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 2231 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 2232 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 2233 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 2234 2235 /* setup DMA registers */ 2236 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 2237 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 2238 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 2239 2240 /* setup SATA registers */ 2241 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 2242 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 2243 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 2244 2245 ch->flags |= ATA_NO_SLAVE; 2246 ata_pci_hw(dev); 2247 ch->hw.status = ata_intel_31244_status; 2248 ch->hw.command = ata_intel_31244_command; 2249 2250 /* enable PHY state change interrupt */ 2251 ATA_OUTL(ctlr->r_res2, 0x4, 2252 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 2253 return 0; 2254 } 2255 2256 static int 2257 ata_intel_31244_status(device_t dev) 2258 { 2259 /* do we have any PHY events ? */ 2260 ata_sata_phy_check_events(dev); 2261 2262 /* any drive action to take care of ? */ 2263 return ata_pci_status(dev); 2264 } 2265 2266 static int 2267 ata_intel_31244_command(struct ata_request *request) 2268 { 2269 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2270 struct ata_device *atadev = device_get_softc(request->dev); 2271 u_int64_t lba; 2272 2273 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 2274 return (ata_generic_command(request)); 2275 2276 lba = request->u.ata.lba; 2277 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 2278 /* enable interrupt */ 2279 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 2280 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 2281 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 2282 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff)); 2283 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) | 2284 ((lba >> 8) & 0x00ff)); 2285 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) | 2286 ((lba >> 16) & 0x00ff)); 2287 2288 /* issue command to controller */ 2289 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 2290 2291 return 0; 2292 } 2293 2294 static void 2295 ata_intel_31244_reset(device_t dev) 2296 { 2297 if (ata_sata_phy_reset(dev)) 2298 ata_generic_reset(dev); 2299 } 2300 2301 2302 /* 2303 * Integrated Technology Express Inc. (ITE) chipset support functions 2304 */ 2305 int 2306 ata_ite_ident(device_t dev) 2307 { 2308 struct ata_pci_controller *ctlr = device_get_softc(dev); 2309 struct ata_chip_id *idx; 2310 static struct ata_chip_id ids[] = 2311 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 2312 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 2313 { 0, 0, 0, 0, 0, 0}}; 2314 char buffer[64]; 2315 2316 if (!(idx = ata_match_chip(dev, ids))) 2317 return ENXIO; 2318 2319 ksprintf(buffer, "ITE %s %s controller", 2320 idx->text, ata_mode2str(idx->max_dma)); 2321 device_set_desc_copy(dev, buffer); 2322 ctlr->chip = idx; 2323 ctlr->chipinit = ata_ite_chipinit; 2324 return 0; 2325 } 2326 2327 static int 2328 ata_ite_chipinit(device_t dev) 2329 { 2330 struct ata_pci_controller *ctlr = device_get_softc(dev); 2331 2332 if (ata_setup_interrupt(dev)) 2333 return ENXIO; 2334 2335 ctlr->setmode = ata_ite_setmode; 2336 2337 /* set PCI mode and 66Mhz reference clock */ 2338 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 2339 2340 /* set default active & recover timings */ 2341 pci_write_config(dev, 0x54, 0x31, 1); 2342 pci_write_config(dev, 0x56, 0x31, 1); 2343 return 0; 2344 } 2345 2346 static void 2347 ata_ite_setmode(device_t dev, int mode) 2348 { 2349 device_t gparent = GRANDPARENT(dev); 2350 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2351 struct ata_device *atadev = device_get_softc(dev); 2352 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2353 int error; 2354 2355 /* correct the mode for what the HW supports */ 2356 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2357 2358 /* check the CBLID bits for 80 conductor cable detection */ 2359 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) & 2360 (ch->unit ? (1<<3) : (1<<2)))) { 2361 ata_print_cable(dev, "controller"); 2362 mode = ATA_UDMA2; 2363 } 2364 2365 /* set the wanted mode on the device */ 2366 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2367 2368 if (bootverbose) 2369 device_printf(dev, "%s setting %s on ITE8212F chip\n", 2370 (error) ? "failed" : "success", ata_mode2str(mode)); 2371 2372 /* if the device accepted the mode change, setup the HW accordingly */ 2373 if (!error) { 2374 if (mode >= ATA_UDMA0) { 2375 u_int8_t udmatiming[] = 2376 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 2377 2378 /* enable UDMA mode */ 2379 pci_write_config(gparent, 0x50, 2380 pci_read_config(gparent, 0x50, 1) & 2381 ~(1 << (devno + 3)), 1); 2382 2383 /* set UDMA timing */ 2384 pci_write_config(gparent, 2385 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit), 2386 udmatiming[mode & ATA_MODE_MASK], 1); 2387 } 2388 else { 2389 u_int8_t chtiming[] = 2390 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 2391 2392 /* disable UDMA mode */ 2393 pci_write_config(gparent, 0x50, 2394 pci_read_config(gparent, 0x50, 1) | 2395 (1 << (devno + 3)), 1); 2396 2397 /* set active and recover timing (shared between master & slave) */ 2398 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) < 2399 chtiming[ata_mode2idx(mode)]) 2400 pci_write_config(gparent, 0x54 + (ch->unit << 2), 2401 chtiming[ata_mode2idx(mode)], 1); 2402 } 2403 atadev->mode = mode; 2404 } 2405 } 2406 2407 2408 /* 2409 * JMicron chipset support functions 2410 */ 2411 int 2412 ata_jmicron_ident(device_t dev) 2413 { 2414 struct ata_pci_controller *ctlr = device_get_softc(dev); 2415 struct ata_chip_id *idx; 2416 static struct ata_chip_id ids[] = 2417 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" }, 2418 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" }, 2419 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" }, 2420 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" }, 2421 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" }, 2422 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" }, 2423 { 0, 0, 0, 0, 0, 0}}; 2424 char buffer[64]; 2425 2426 if (!(idx = ata_match_chip(dev, ids))) 2427 return ENXIO; 2428 2429 if ((pci_read_config(dev, 0xdf, 1) & 0x40) && 2430 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1))) 2431 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2432 idx->text, ata_mode2str(ATA_UDMA6)); 2433 else 2434 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2435 idx->text, ata_mode2str(idx->max_dma)); 2436 device_set_desc_copy(dev, buffer); 2437 ctlr->chip = idx; 2438 ctlr->chipinit = ata_jmicron_chipinit; 2439 return 0; 2440 } 2441 2442 static int 2443 ata_jmicron_chipinit(device_t dev) 2444 { 2445 struct ata_pci_controller *ctlr = device_get_softc(dev); 2446 int error; 2447 2448 if (ata_setup_interrupt(dev)) 2449 return ENXIO; 2450 2451 /* do we have multiple PCI functions ? */ 2452 if (pci_read_config(dev, 0xdf, 1) & 0x40) { 2453 /* are we on the AHCI part ? */ 2454 if (ata_ahci_chipinit(dev) != ENXIO) 2455 return 0; 2456 2457 /* otherwise we are on the PATA part */ 2458 ctlr->allocate = ata_pci_allocate; 2459 ctlr->reset = ata_generic_reset; 2460 ctlr->dmainit = ata_pci_dmainit; 2461 ctlr->setmode = ata_jmicron_setmode; 2462 ctlr->channels = ctlr->chip->cfg2; 2463 } 2464 else { 2465 /* set controller configuration to a combined setup we support */ 2466 pci_write_config(dev, 0x40, 0x80c0a131, 4); 2467 pci_write_config(dev, 0x80, 0x01200000, 4); 2468 2469 if ((error = ata_ahci_chipinit(dev))) 2470 return error; 2471 2472 ctlr->allocate = ata_jmicron_allocate; 2473 ctlr->reset = ata_jmicron_reset; 2474 ctlr->dmainit = ata_jmicron_dmainit; 2475 ctlr->setmode = ata_jmicron_setmode; 2476 2477 /* set the number of HW channels */ 2478 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2; 2479 } 2480 return 0; 2481 } 2482 2483 static int 2484 ata_jmicron_allocate(device_t dev) 2485 { 2486 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2487 struct ata_channel *ch = device_get_softc(dev); 2488 int error; 2489 2490 if (ch->unit >= ctlr->chip->cfg1) { 2491 ch->unit -= ctlr->chip->cfg1; 2492 error = ata_pci_allocate(dev); 2493 ch->unit += ctlr->chip->cfg1; 2494 } 2495 else 2496 error = ata_ahci_allocate(dev); 2497 return error; 2498 } 2499 2500 static void 2501 ata_jmicron_reset(device_t dev) 2502 { 2503 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2504 struct ata_channel *ch = device_get_softc(dev); 2505 2506 if (ch->unit >= ctlr->chip->cfg1) 2507 ata_generic_reset(dev); 2508 else 2509 ata_ahci_reset(dev); 2510 } 2511 2512 static void 2513 ata_jmicron_dmainit(device_t dev) 2514 { 2515 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2516 struct ata_channel *ch = device_get_softc(dev); 2517 2518 if (ch->unit >= ctlr->chip->cfg1) 2519 ata_pci_dmainit(dev); 2520 else 2521 ata_ahci_dmainit(dev); 2522 } 2523 2524 static void 2525 ata_jmicron_setmode(device_t dev, int mode) 2526 { 2527 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 2528 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2529 2530 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) { 2531 struct ata_device *atadev = device_get_softc(dev); 2532 2533 /* check for 80pin cable present */ 2534 if (pci_read_config(dev, 0x40, 1) & 0x08) 2535 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 2536 else 2537 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2538 2539 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2540 atadev->mode = mode; 2541 } 2542 else 2543 ata_sata_setmode(dev, mode); 2544 } 2545 2546 2547 /* 2548 * Marvell chipset support functions 2549 */ 2550 #define ATA_MV_HOST_BASE(ch) \ 2551 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000) 2552 #define ATA_MV_EDMA_BASE(ch) \ 2553 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000) 2554 2555 struct ata_marvell_response { 2556 u_int16_t tag; 2557 u_int8_t edma_status; 2558 u_int8_t dev_status; 2559 u_int32_t timestamp; 2560 }; 2561 2562 struct ata_marvell_dma_prdentry { 2563 u_int32_t addrlo; 2564 u_int32_t count; 2565 u_int32_t addrhi; 2566 u_int32_t reserved; 2567 }; 2568 2569 int 2570 ata_marvell_ident(device_t dev) 2571 { 2572 struct ata_pci_controller *ctlr = device_get_softc(dev); 2573 struct ata_chip_id *idx; 2574 static struct ata_chip_id ids[] = 2575 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" }, 2576 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" }, 2577 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" }, 2578 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" }, 2579 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" }, 2580 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" }, 2581 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" }, 2582 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" }, 2583 { 0, 0, 0, 0, 0, 0}}; 2584 char buffer[64]; 2585 2586 if (!(idx = ata_match_chip(dev, ids))) 2587 return ENXIO; 2588 2589 ksprintf(buffer, "Marvell %s %s controller", 2590 idx->text, ata_mode2str(idx->max_dma)); 2591 device_set_desc_copy(dev, buffer); 2592 ctlr->chip = idx; 2593 switch (ctlr->chip->cfg2) { 2594 case MV50XX: 2595 case MV60XX: 2596 ctlr->chipinit = ata_marvell_edma_chipinit; 2597 break; 2598 case MV61XX: 2599 ctlr->chipinit = ata_marvell_pata_chipinit; 2600 break; 2601 } 2602 return 0; 2603 } 2604 2605 static int 2606 ata_marvell_pata_chipinit(device_t dev) 2607 { 2608 struct ata_pci_controller *ctlr = device_get_softc(dev); 2609 2610 if (ata_setup_interrupt(dev)) 2611 return ENXIO; 2612 2613 ctlr->allocate = ata_marvell_pata_allocate; 2614 ctlr->setmode = ata_marvell_pata_setmode; 2615 ctlr->channels = ctlr->chip->cfg1; 2616 return 0; 2617 } 2618 2619 static int 2620 ata_marvell_pata_allocate(device_t dev) 2621 { 2622 struct ata_channel *ch = device_get_softc(dev); 2623 2624 /* setup the usual register normal pci style */ 2625 if (ata_pci_allocate(dev)) 2626 return ENXIO; 2627 2628 /* dont use 32 bit PIO transfers */ 2629 ch->flags |= ATA_USE_16BIT; 2630 2631 return 0; 2632 } 2633 2634 static void 2635 ata_marvell_pata_setmode(device_t dev, int mode) 2636 { 2637 device_t gparent = GRANDPARENT(dev); 2638 struct ata_pci_controller *ctlr = device_get_softc(gparent); 2639 struct ata_device *atadev = device_get_softc(dev); 2640 2641 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 2642 mode = ata_check_80pin(dev, mode); 2643 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2644 atadev->mode = mode; 2645 } 2646 2647 static int 2648 ata_marvell_edma_chipinit(device_t dev) 2649 { 2650 struct ata_pci_controller *ctlr = device_get_softc(dev); 2651 2652 if (ata_setup_interrupt(dev)) 2653 return ENXIO; 2654 2655 ctlr->r_type1 = SYS_RES_MEMORY; 2656 ctlr->r_rid1 = PCIR_BAR(0); 2657 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 2658 &ctlr->r_rid1, RF_ACTIVE))) 2659 return ENXIO; 2660 2661 /* mask all host controller interrupts */ 2662 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000); 2663 2664 /* mask all PCI interrupts */ 2665 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000); 2666 2667 ctlr->allocate = ata_marvell_edma_allocate; 2668 ctlr->reset = ata_marvell_edma_reset; 2669 ctlr->dmainit = ata_marvell_edma_dmainit; 2670 ctlr->setmode = ata_sata_setmode; 2671 ctlr->channels = ctlr->chip->cfg1; 2672 2673 /* clear host controller interrupts */ 2674 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000); 2675 if (ctlr->chip->cfg1 > 4) 2676 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000); 2677 2678 /* clear PCI interrupts */ 2679 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000); 2680 2681 /* unmask PCI interrupts we want */ 2682 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff); 2683 2684 /* unmask host controller interrupts we want */ 2685 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ | 2686 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25)); 2687 2688 /* enable PCI interrupt */ 2689 pci_write_config(dev, PCIR_COMMAND, 2690 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 2691 return 0; 2692 } 2693 2694 static int 2695 ata_marvell_edma_allocate(device_t dev) 2696 { 2697 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2698 struct ata_channel *ch = device_get_softc(dev); 2699 u_int64_t work = ch->dma->work_bus; 2700 int i; 2701 2702 /* clear work area */ 2703 bzero(ch->dma->work, 1024+256); 2704 2705 /* set legacy ATA resources */ 2706 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 2707 ch->r_io[i].res = ctlr->r_res1; 2708 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch); 2709 } 2710 ch->r_io[ATA_CONTROL].res = ctlr->r_res1; 2711 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch); 2712 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1; 2713 ata_default_registers(dev); 2714 2715 /* set SATA resources */ 2716 switch (ctlr->chip->cfg2) { 2717 case MV50XX: 2718 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2719 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch); 2720 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2721 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch); 2722 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2723 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch); 2724 break; 2725 case MV60XX: 2726 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2727 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch); 2728 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2729 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch); 2730 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2731 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch); 2732 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1; 2733 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch); 2734 break; 2735 } 2736 2737 ch->flags |= ATA_NO_SLAVE; 2738 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */ 2739 ata_generic_hw(dev); 2740 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction; 2741 ch->hw.end_transaction = ata_marvell_edma_end_transaction; 2742 ch->hw.status = ata_marvell_edma_status; 2743 2744 /* disable the EDMA machinery */ 2745 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2746 DELAY(100000); /* SOS should poll for disabled */ 2747 2748 /* set configuration to non-queued 128b read transfers stop on error */ 2749 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13)); 2750 2751 /* request queue base high */ 2752 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32); 2753 2754 /* request queue in ptr */ 2755 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2756 2757 /* request queue out ptr */ 2758 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0); 2759 2760 /* response queue base high */ 2761 work += 1024; 2762 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32); 2763 2764 /* response queue in ptr */ 2765 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0); 2766 2767 /* response queue out ptr */ 2768 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2769 2770 /* clear SATA error register */ 2771 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 2772 2773 /* clear any outstanding error interrupts */ 2774 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2775 2776 /* unmask all error interrupts */ 2777 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 2778 2779 /* enable EDMA machinery */ 2780 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2781 return 0; 2782 } 2783 2784 static int 2785 ata_marvell_edma_status(device_t dev) 2786 { 2787 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2788 struct ata_channel *ch = device_get_softc(dev); 2789 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60); 2790 int shift = (ch->unit << 1) + (ch->unit > 3); 2791 2792 if (cause & (1 << shift)) { 2793 2794 /* clear interrupt(s) */ 2795 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2796 2797 /* do we have any PHY events ? */ 2798 ata_sata_phy_check_events(dev); 2799 } 2800 2801 /* do we have any device action ? */ 2802 return (cause & (2 << shift)); 2803 } 2804 2805 /* must be called with ATA channel locked and state_mtx held */ 2806 static int 2807 ata_marvell_edma_begin_transaction(struct ata_request *request) 2808 { 2809 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2810 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2811 u_int32_t req_in; 2812 u_int8_t *bytep; 2813 u_int16_t *wordp; 2814 u_int32_t *quadp; 2815 int i, tag = 0x07; 2816 int dummy, error, slot; 2817 2818 /* only DMA R/W goes through the EMDA machine */ 2819 if (request->u.ata.command != ATA_READ_DMA && 2820 request->u.ata.command != ATA_WRITE_DMA) { 2821 2822 /* disable the EDMA machinery */ 2823 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001) 2824 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2825 return ata_begin_transaction(request); 2826 } 2827 2828 /* check for 48 bit access and convert if needed */ 2829 ata_modify_if_48bit(request); 2830 2831 /* check sanity, setup SG list and DMA engine */ 2832 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 2833 request->flags & ATA_R_READ, ch->dma->sg, 2834 &dummy))) { 2835 device_printf(request->dev, "setting up DMA failed\n"); 2836 request->result = error; 2837 return ATA_OP_FINISHED; 2838 } 2839 2840 /* get next free request queue slot */ 2841 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch)); 2842 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f; 2843 bytep = (u_int8_t *)(ch->dma->work); 2844 bytep += (slot << 5); 2845 wordp = (u_int16_t *)bytep; 2846 quadp = (u_int32_t *)bytep; 2847 2848 /* fill in this request */ 2849 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff; 2850 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32; 2851 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1); 2852 2853 i = 10; 2854 bytep[i++] = (request->u.ata.count >> 8) & 0xff; 2855 bytep[i++] = 0x10 | ATA_COUNT; 2856 bytep[i++] = request->u.ata.count & 0xff; 2857 bytep[i++] = 0x10 | ATA_COUNT; 2858 2859 bytep[i++] = (request->u.ata.lba >> 24) & 0xff; 2860 bytep[i++] = 0x10 | ATA_SECTOR; 2861 bytep[i++] = request->u.ata.lba & 0xff; 2862 bytep[i++] = 0x10 | ATA_SECTOR; 2863 2864 bytep[i++] = (request->u.ata.lba >> 32) & 0xff; 2865 bytep[i++] = 0x10 | ATA_CYL_LSB; 2866 bytep[i++] = (request->u.ata.lba >> 8) & 0xff; 2867 bytep[i++] = 0x10 | ATA_CYL_LSB; 2868 2869 bytep[i++] = (request->u.ata.lba >> 40) & 0xff; 2870 bytep[i++] = 0x10 | ATA_CYL_MSB; 2871 bytep[i++] = (request->u.ata.lba >> 16) & 0xff; 2872 bytep[i++] = 0x10 | ATA_CYL_MSB; 2873 2874 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf); 2875 bytep[i++] = 0x10 | ATA_DRIVE; 2876 2877 bytep[i++] = request->u.ata.command; 2878 bytep[i++] = 0x90 | ATA_COMMAND; 2879 2880 /* enable EDMA machinery if needed */ 2881 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) { 2882 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2883 while (!(ATA_INL(ctlr->r_res1, 2884 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 2885 DELAY(10); 2886 } 2887 2888 /* tell EDMA it has a new request */ 2889 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f; 2890 req_in &= 0xfffffc00; 2891 req_in += (slot << 5); 2892 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in); 2893 2894 return ATA_OP_CONTINUES; 2895 } 2896 2897 /* must be called with ATA channel locked and state_mtx held */ 2898 static int 2899 ata_marvell_edma_end_transaction(struct ata_request *request) 2900 { 2901 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2902 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2903 int offset = (ch->unit > 3 ? 0x30014 : 0x20014); 2904 u_int32_t icr = ATA_INL(ctlr->r_res1, offset); 2905 int res; 2906 2907 /* EDMA interrupt */ 2908 if ((icr & (0x0001 << (ch->unit & 3)))) { 2909 struct ata_marvell_response *response; 2910 u_int32_t rsp_in, rsp_out; 2911 int slot; 2912 2913 /* stop timeout */ 2914 callout_stop(&request->callout); 2915 2916 /* get response ptr's */ 2917 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch)); 2918 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch)); 2919 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f; 2920 rsp_out &= 0xffffff00; 2921 rsp_out += (slot << 3); 2922 response = (struct ata_marvell_response *) 2923 (ch->dma->work + 1024 + (slot << 3)); 2924 2925 /* record status for this request */ 2926 request->status = response->dev_status; 2927 request->error = 0; 2928 2929 /* ack response */ 2930 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out); 2931 2932 /* update progress */ 2933 if (!(request->status & ATA_S_ERROR) && 2934 !(request->flags & ATA_R_TIMEOUT)) 2935 request->donecount = request->bytecount; 2936 2937 /* unload SG list */ 2938 ch->dma->unload(ch->dev); 2939 2940 res = ATA_OP_FINISHED; 2941 } 2942 2943 /* legacy ATA interrupt */ 2944 else { 2945 res = ata_end_transaction(request); 2946 } 2947 2948 /* ack interrupt */ 2949 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3)))); 2950 return res; 2951 } 2952 2953 static void 2954 ata_marvell_edma_reset(device_t dev) 2955 { 2956 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2957 struct ata_channel *ch = device_get_softc(dev); 2958 2959 /* disable the EDMA machinery */ 2960 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2961 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 2962 DELAY(10); 2963 2964 /* clear SATA error register */ 2965 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 2966 2967 /* clear any outstanding error interrupts */ 2968 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2969 2970 /* unmask all error interrupts */ 2971 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 2972 2973 /* enable channel and test for devices */ 2974 if (ata_sata_phy_reset(dev)) 2975 ata_generic_reset(dev); 2976 2977 /* enable EDMA machinery */ 2978 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2979 } 2980 2981 static void 2982 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, 2983 int error) 2984 { 2985 struct ata_dmasetprd_args *args = xsc; 2986 struct ata_marvell_dma_prdentry *prd = args->dmatab; 2987 int i; 2988 2989 if ((args->error = error)) 2990 return; 2991 2992 for (i = 0; i < nsegs; i++) { 2993 prd[i].addrlo = htole32(segs[i].ds_addr); 2994 prd[i].count = htole32(segs[i].ds_len); 2995 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32); 2996 } 2997 prd[i - 1].count |= htole32(ATA_DMA_EOT); 2998 } 2999 3000 static void 3001 ata_marvell_edma_dmainit(device_t dev) 3002 { 3003 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3004 struct ata_channel *ch = device_get_softc(dev); 3005 3006 ata_dmainit(dev); 3007 if (ch->dma) { 3008 /* note start and stop are not used here */ 3009 ch->dma->setprd = ata_marvell_edma_dmasetprd; 3010 3011 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004) 3012 ch->dma->max_address = BUS_SPACE_MAXADDR; 3013 3014 /* chip does not reliably do 64K DMA transfers */ 3015 ch->dma->max_iosize = 126 * DEV_BSIZE; 3016 } 3017 } 3018 3019 3020 /* 3021 * National chipset support functions 3022 */ 3023 int 3024 ata_national_ident(device_t dev) 3025 { 3026 struct ata_pci_controller *ctlr = device_get_softc(dev); 3027 3028 /* this chip is a clone of the Cyrix chip, bugs and all */ 3029 if (pci_get_devid(dev) == ATA_SC1100) { 3030 device_set_desc(dev, "National Geode SC1100 ATA33 controller"); 3031 ctlr->chipinit = ata_national_chipinit; 3032 return 0; 3033 } 3034 return ENXIO; 3035 } 3036 3037 static int 3038 ata_national_chipinit(device_t dev) 3039 { 3040 struct ata_pci_controller *ctlr = device_get_softc(dev); 3041 3042 if (ata_setup_interrupt(dev)) 3043 return ENXIO; 3044 3045 ctlr->setmode = ata_national_setmode; 3046 return 0; 3047 } 3048 3049 static void 3050 ata_national_setmode(device_t dev, int mode) 3051 { 3052 device_t gparent = GRANDPARENT(dev); 3053 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3054 struct ata_device *atadev = device_get_softc(dev); 3055 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3056 u_int32_t piotiming[] = 3057 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010, 3058 0x00803020, 0x20102010, 0x00100010, 3059 0x00100010, 0x00100010, 0x00100010 }; 3060 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 }; 3061 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 }; 3062 int error; 3063 3064 ch->dma->alignment = 16; 3065 ch->dma->max_iosize = 126 * DEV_BSIZE; 3066 3067 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 3068 3069 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3070 3071 if (bootverbose) 3072 device_printf(dev, "%s setting %s on National chip\n", 3073 (error) ? "failed" : "success", ata_mode2str(mode)); 3074 if (!error) { 3075 if (mode >= ATA_UDMA0) { 3076 pci_write_config(gparent, 0x44 + (devno << 3), 3077 udmatiming[mode & ATA_MODE_MASK], 4); 3078 } 3079 else if (mode >= ATA_WDMA0) { 3080 pci_write_config(gparent, 0x44 + (devno << 3), 3081 dmatiming[mode & ATA_MODE_MASK], 4); 3082 } 3083 else { 3084 pci_write_config(gparent, 0x44 + (devno << 3), 3085 pci_read_config(gparent, 0x44 + (devno << 3), 4) | 3086 0x80000000, 4); 3087 } 3088 pci_write_config(gparent, 0x40 + (devno << 3), 3089 piotiming[ata_mode2idx(mode)], 4); 3090 atadev->mode = mode; 3091 } 3092 } 3093 3094 /* 3095 * NetCell chipset support functions 3096 */ 3097 int 3098 ata_netcell_ident(device_t dev) 3099 { 3100 struct ata_pci_controller *ctlr = device_get_softc(dev); 3101 3102 if (pci_get_devid(dev) == ATA_NETCELL_SR) { 3103 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller"); 3104 ctlr->chipinit = ata_netcell_chipinit; 3105 return 0; 3106 } 3107 return ENXIO; 3108 } 3109 3110 static int 3111 ata_netcell_chipinit(device_t dev) 3112 { 3113 struct ata_pci_controller *ctlr = device_get_softc(dev); 3114 3115 if (ata_generic_chipinit(dev)) 3116 return ENXIO; 3117 3118 ctlr->allocate = ata_netcell_allocate; 3119 return 0; 3120 } 3121 3122 static int 3123 ata_netcell_allocate(device_t dev) 3124 { 3125 struct ata_channel *ch = device_get_softc(dev); 3126 3127 /* setup the usual register normal pci style */ 3128 if (ata_pci_allocate(dev)) 3129 return ENXIO; 3130 3131 /* the NetCell only supports 16 bit PIO transfers */ 3132 ch->flags |= ATA_USE_16BIT; 3133 3134 return 0; 3135 } 3136 3137 3138 /* 3139 * nVidia chipset support functions 3140 */ 3141 int 3142 ata_nvidia_ident(device_t dev) 3143 { 3144 struct ata_pci_controller *ctlr = device_get_softc(dev); 3145 struct ata_chip_id *idx; 3146 static struct ata_chip_id ids[] = 3147 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" }, 3148 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" }, 3149 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" }, 3150 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" }, 3151 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" }, 3152 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" }, 3153 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3154 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3155 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" }, 3156 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3157 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3158 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" }, 3159 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3160 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3161 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" }, 3162 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3163 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3164 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" }, 3165 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3166 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3167 { 0, 0, 0, 0, 0, 0}} ; 3168 char buffer[64] ; 3169 3170 if (!(idx = ata_match_chip(dev, ids))) 3171 return ENXIO; 3172 3173 ksprintf(buffer, "nVidia %s %s controller", 3174 idx->text, ata_mode2str(idx->max_dma)); 3175 device_set_desc_copy(dev, buffer); 3176 ctlr->chip = idx; 3177 ctlr->chipinit = ata_nvidia_chipinit; 3178 return 0; 3179 } 3180 3181 static int 3182 ata_nvidia_chipinit(device_t dev) 3183 { 3184 struct ata_pci_controller *ctlr = device_get_softc(dev); 3185 3186 if (ata_setup_interrupt(dev)) 3187 return ENXIO; 3188 3189 if (ctlr->chip->max_dma >= ATA_SA150) { 3190 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1) 3191 ctlr->r_type2 = SYS_RES_IOPORT; 3192 else 3193 ctlr->r_type2 = SYS_RES_MEMORY; 3194 ctlr->r_rid2 = PCIR_BAR(5); 3195 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3196 &ctlr->r_rid2, RF_ACTIVE))) { 3197 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3198 3199 ctlr->allocate = ata_nvidia_allocate; 3200 ctlr->reset = ata_nvidia_reset; 3201 3202 /* enable control access */ 3203 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1); 3204 3205 if (ctlr->chip->cfg2 & NVQ) { 3206 /* clear interrupt status */ 3207 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff); 3208 3209 /* enable device and PHY state change interrupts */ 3210 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d); 3211 3212 /* disable NCQ support */ 3213 ATA_OUTL(ctlr->r_res2, 0x0400, 3214 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9); 3215 } 3216 else { 3217 /* clear interrupt status */ 3218 ATA_OUTB(ctlr->r_res2, offset, 0xff); 3219 3220 /* enable device and PHY state change interrupts */ 3221 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd); 3222 } 3223 3224 /* enable PCI interrupt */ 3225 pci_write_config(dev, PCIR_COMMAND, 3226 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 3227 3228 } 3229 ctlr->setmode = ata_sata_setmode; 3230 } 3231 else { 3232 /* disable prefetch, postwrite */ 3233 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1); 3234 ctlr->setmode = ata_via_family_setmode; 3235 } 3236 return 0; 3237 } 3238 3239 static int 3240 ata_nvidia_allocate(device_t dev) 3241 { 3242 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3243 struct ata_channel *ch = device_get_softc(dev); 3244 3245 /* setup the usual register normal pci style */ 3246 if (ata_pci_allocate(dev)) 3247 return ENXIO; 3248 3249 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3250 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6); 3251 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3252 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6); 3253 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3254 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6); 3255 3256 ch->hw.status = ata_nvidia_status; 3257 ch->flags |= ATA_NO_SLAVE; 3258 3259 return 0; 3260 } 3261 3262 static int 3263 ata_nvidia_status(device_t dev) 3264 { 3265 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3266 struct ata_channel *ch = device_get_softc(dev); 3267 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3268 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2); 3269 u_int32_t istatus = ATA_INL(ctlr->r_res2, offset); 3270 3271 /* do we have any PHY events ? */ 3272 if (istatus & (0x0c << shift)) 3273 ata_sata_phy_check_events(dev); 3274 3275 /* clear interrupt(s) */ 3276 ATA_OUTB(ctlr->r_res2, offset, 3277 (0x0f << shift) | (ctlr->chip->cfg2 & NVQ ? 0x00f000f0 : 0)); 3278 3279 /* do we have any device action ? */ 3280 return (istatus & (0x01 << shift)); 3281 } 3282 3283 static void 3284 ata_nvidia_reset(device_t dev) 3285 { 3286 if (ata_sata_phy_reset(dev)) 3287 ata_generic_reset(dev); 3288 } 3289 3290 3291 /* 3292 * Promise chipset support functions 3293 */ 3294 #define ATA_PDC_APKT_OFFSET 0x00000010 3295 #define ATA_PDC_HPKT_OFFSET 0x00000040 3296 #define ATA_PDC_ASG_OFFSET 0x00000080 3297 #define ATA_PDC_LSG_OFFSET 0x000000c0 3298 #define ATA_PDC_HSG_OFFSET 0x00000100 3299 #define ATA_PDC_CHN_OFFSET 0x00000400 3300 #define ATA_PDC_BUF_BASE 0x00400000 3301 #define ATA_PDC_BUF_OFFSET 0x00100000 3302 #define ATA_PDC_MAX_HPKT 8 3303 #define ATA_PDC_WRITE_REG 0x00 3304 #define ATA_PDC_WRITE_CTL 0x0e 3305 #define ATA_PDC_WRITE_END 0x08 3306 #define ATA_PDC_WAIT_NBUSY 0x10 3307 #define ATA_PDC_WAIT_READY 0x18 3308 #define ATA_PDC_1B 0x20 3309 #define ATA_PDC_2B 0x40 3310 3311 struct host_packet { 3312 u_int32_t addr; 3313 TAILQ_ENTRY(host_packet) chain; 3314 }; 3315 3316 struct ata_promise_sx4 { 3317 struct spinlock mtx; 3318 TAILQ_HEAD(, host_packet) queue; 3319 int busy; 3320 }; 3321 3322 int 3323 ata_promise_ident(device_t dev) 3324 { 3325 struct ata_pci_controller *ctlr = device_get_softc(dev); 3326 struct ata_chip_id *idx; 3327 static struct ata_chip_id ids[] = 3328 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" }, 3329 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" }, 3330 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" }, 3331 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" }, 3332 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" }, 3333 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" }, 3334 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" }, 3335 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" }, 3336 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" }, 3337 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" }, 3338 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" }, 3339 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" }, 3340 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" }, 3341 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" }, 3342 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" }, 3343 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" }, 3344 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" }, 3345 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" }, 3346 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" }, 3347 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" }, 3348 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" }, 3349 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" }, 3350 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" }, 3351 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" }, 3352 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" }, 3353 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" }, 3354 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" }, 3355 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" }, 3356 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" }, 3357 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" }, 3358 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" }, 3359 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" }, 3360 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" }, 3361 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" }, 3362 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" }, 3363 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" }, 3364 { 0, 0, 0, 0, 0, 0}}; 3365 char buffer[64]; 3366 uintptr_t devid = 0; 3367 3368 if (!(idx = ata_match_chip(dev, ids))) 3369 return ENXIO; 3370 3371 /* if we are on a SuperTrak SX6000 dont attach */ 3372 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3373 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3374 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3375 devid == ATA_I960RM) 3376 return ENXIO; 3377 3378 strcpy(buffer, "Promise "); 3379 strcat(buffer, idx->text); 3380 3381 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 3382 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3383 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3384 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3385 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 3386 static long start = 0, end = 0; 3387 3388 if (pci_get_slot(dev) == 1) { 3389 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 3390 strcat(buffer, " (channel 0+1)"); 3391 } 3392 else if (pci_get_slot(dev) == 2 && start && end) { 3393 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 3394 strcat(buffer, " (channel 2+3)"); 3395 } 3396 else { 3397 start = end = 0; 3398 } 3399 } 3400 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 3401 device_set_desc_copy(dev, buffer); 3402 ctlr->chip = idx; 3403 ctlr->chipinit = ata_promise_chipinit; 3404 return 0; 3405 } 3406 3407 static int 3408 ata_promise_chipinit(device_t dev) 3409 { 3410 struct ata_pci_controller *ctlr = device_get_softc(dev); 3411 int fake_reg, stat_reg; 3412 3413 if (ata_setup_interrupt(dev)) 3414 return ENXIO; 3415 3416 switch (ctlr->chip->cfg1) { 3417 case PRNEW: 3418 /* setup clocks */ 3419 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 3420 3421 ctlr->dmainit = ata_promise_dmainit; 3422 /* FALLTHROUGH */ 3423 3424 case PROLD: 3425 /* enable burst mode */ 3426 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 3427 ctlr->allocate = ata_promise_allocate; 3428 ctlr->setmode = ata_promise_setmode; 3429 return 0; 3430 3431 case PRTX: 3432 ctlr->allocate = ata_promise_tx2_allocate; 3433 ctlr->setmode = ata_promise_setmode; 3434 return 0; 3435 3436 case PRMIO: 3437 ctlr->r_type1 = SYS_RES_MEMORY; 3438 ctlr->r_rid1 = PCIR_BAR(4); 3439 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 3440 &ctlr->r_rid1, RF_ACTIVE))) 3441 goto failnfree; 3442 3443 ctlr->r_type2 = SYS_RES_MEMORY; 3444 ctlr->r_rid2 = PCIR_BAR(3); 3445 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3446 &ctlr->r_rid2, RF_ACTIVE))) 3447 goto failnfree; 3448 3449 if (ctlr->chip->cfg2 == PRSX4X) { 3450 struct ata_promise_sx4 *hpkt; 3451 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 3452 3453 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3454 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3455 ata_promise_sx4_intr, ctlr, &ctlr->handle, NULL)) { 3456 device_printf(dev, "unable to setup interrupt\n"); 3457 goto failnfree; 3458 } 3459 3460 /* print info about cache memory */ 3461 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 3462 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 3463 ((dimm >> 24) & 0xff), 3464 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 3465 " ECC enabled" : "" ); 3466 3467 /* adjust cache memory parameters */ 3468 ATA_OUTL(ctlr->r_res2, 0x000c000c, 3469 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 3470 3471 /* setup host packet controls */ 3472 hpkt = kmalloc(sizeof(struct ata_promise_sx4), 3473 M_TEMP, M_INTWAIT | M_ZERO); 3474 spin_init(&hpkt->mtx); 3475 TAILQ_INIT(&hpkt->queue); 3476 hpkt->busy = 0; 3477 device_set_ivars(dev, hpkt); 3478 ctlr->allocate = ata_promise_mio_allocate; 3479 ctlr->reset = ata_promise_mio_reset; 3480 ctlr->dmainit = ata_promise_mio_dmainit; 3481 ctlr->setmode = ata_promise_setmode; 3482 ctlr->channels = 4; 3483 return 0; 3484 } 3485 3486 /* mio type controllers need an interrupt intercept */ 3487 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3488 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3489 ata_promise_mio_intr, ctlr, &ctlr->handle, NULL)) { 3490 device_printf(dev, "unable to setup interrupt\n"); 3491 goto failnfree; 3492 } 3493 3494 switch (ctlr->chip->cfg2) { 3495 case PRPATA: 3496 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 3497 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 3498 goto sata150; 3499 case PRCMBO: 3500 ctlr->channels = 3; 3501 goto sata150; 3502 case PRSATA: 3503 ctlr->channels = 4; 3504 sata150: 3505 fake_reg = 0x60; 3506 stat_reg = 0x6c; 3507 break; 3508 3509 case PRCMBO2: 3510 ctlr->channels = 3; 3511 goto sataii; 3512 case PRSATA2: 3513 default: 3514 ctlr->channels = 4; 3515 sataii: 3516 fake_reg = 0x54; 3517 stat_reg = 0x60; 3518 break; 3519 } 3520 3521 /* prime fake interrupt register */ 3522 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3523 3524 /* clear SATA status */ 3525 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 3526 3527 ctlr->allocate = ata_promise_mio_allocate; 3528 ctlr->reset = ata_promise_mio_reset; 3529 ctlr->dmainit = ata_promise_mio_dmainit; 3530 ctlr->setmode = ata_promise_mio_setmode; 3531 3532 return 0; 3533 } 3534 3535 failnfree: 3536 if (ctlr->r_res2) 3537 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 3538 if (ctlr->r_res1) 3539 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 3540 return ENXIO; 3541 } 3542 3543 static int 3544 ata_promise_allocate(device_t dev) 3545 { 3546 struct ata_channel *ch = device_get_softc(dev); 3547 3548 if (ata_pci_allocate(dev)) 3549 return ENXIO; 3550 3551 ch->hw.status = ata_promise_status; 3552 return 0; 3553 } 3554 3555 static int 3556 ata_promise_status(device_t dev) 3557 { 3558 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3559 struct ata_channel *ch = device_get_softc(dev); 3560 3561 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 3562 return ata_pci_status(dev); 3563 } 3564 return 0; 3565 } 3566 3567 static int 3568 ata_promise_dmastart(device_t dev) 3569 { 3570 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3571 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3572 struct ata_device *atadev = device_get_softc(dev); 3573 3574 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3575 ATA_OUTB(ctlr->r_res1, 0x11, 3576 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 3577 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 3578 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) | 3579 (ch->dma->cur_iosize >> 1)); 3580 } 3581 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 3582 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 3583 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus); 3584 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3585 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) | 3586 ATA_BMCMD_START_STOP); 3587 ch->flags |= ATA_DMA_ACTIVE; 3588 return 0; 3589 } 3590 3591 static int 3592 ata_promise_dmastop(device_t dev) 3593 { 3594 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3595 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3596 struct ata_device *atadev = device_get_softc(dev); 3597 int error; 3598 3599 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3600 ATA_OUTB(ctlr->r_res1, 0x11, 3601 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 3602 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 3603 } 3604 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 3605 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3606 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3607 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3608 ch->flags &= ~ATA_DMA_ACTIVE; 3609 return error; 3610 } 3611 3612 static void 3613 ata_promise_dmareset(device_t dev) 3614 { 3615 struct ata_channel *ch = device_get_softc(dev); 3616 3617 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3618 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3619 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3620 ch->flags &= ~ATA_DMA_ACTIVE; 3621 } 3622 3623 static void 3624 ata_promise_dmainit(device_t dev) 3625 { 3626 struct ata_channel *ch = device_get_softc(dev); 3627 3628 ata_dmainit(dev); 3629 if (ch->dma) { 3630 ch->dma->start = ata_promise_dmastart; 3631 ch->dma->stop = ata_promise_dmastop; 3632 ch->dma->reset = ata_promise_dmareset; 3633 } 3634 } 3635 3636 static void 3637 ata_promise_setmode(device_t dev, int mode) 3638 { 3639 device_t gparent = GRANDPARENT(dev); 3640 struct ata_pci_controller *ctlr = device_get_softc(gparent); 3641 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3642 struct ata_device *atadev = device_get_softc(dev); 3643 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3644 int error; 3645 u_int32_t timings[][2] = { 3646 /* PROLD PRNEW mode */ 3647 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 3648 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 3649 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 3650 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 3651 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 3652 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 3653 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 3654 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 3655 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 3656 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 3657 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 3658 { 0, 0x00424ef6 }, /* UDMA 3 */ 3659 { 0, 0x004127f3 }, /* UDMA 4 */ 3660 { 0, 0x004127f3 } /* UDMA 5 */ 3661 }; 3662 3663 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 3664 3665 switch (ctlr->chip->cfg1) { 3666 case PROLD: 3667 case PRNEW: 3668 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) & 3669 (ch->unit ? 1 << 11 : 1 << 10))) { 3670 ata_print_cable(dev, "controller"); 3671 mode = ATA_UDMA2; 3672 } 3673 if (ata_atapi(dev) && mode > ATA_PIO_MAX) 3674 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 3675 break; 3676 3677 case PRTX: 3678 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3679 if (mode > ATA_UDMA2 && 3680 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 3681 ata_print_cable(dev, "controller"); 3682 mode = ATA_UDMA2; 3683 } 3684 break; 3685 3686 case PRMIO: 3687 if (mode > ATA_UDMA2 && 3688 (ATA_INL(ctlr->r_res2, 3689 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) + 3690 (ch->unit << 7)) & 0x01000000)) { 3691 ata_print_cable(dev, "controller"); 3692 mode = ATA_UDMA2; 3693 } 3694 break; 3695 } 3696 3697 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3698 3699 if (bootverbose) 3700 device_printf(dev, "%ssetting %s on %s chip\n", 3701 (error) ? "FAILURE " : "", 3702 ata_mode2str(mode), ctlr->chip->text); 3703 if (!error) { 3704 if (ctlr->chip->cfg1 < PRTX) 3705 pci_write_config(gparent, 0x60 + (devno << 2), 3706 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 3707 atadev->mode = mode; 3708 } 3709 return; 3710 } 3711 3712 static int 3713 ata_promise_tx2_allocate(device_t dev) 3714 { 3715 struct ata_channel *ch = device_get_softc(dev); 3716 3717 if (ata_pci_allocate(dev)) 3718 return ENXIO; 3719 3720 ch->hw.status = ata_promise_tx2_status; 3721 return 0; 3722 } 3723 3724 static int 3725 ata_promise_tx2_status(device_t dev) 3726 { 3727 struct ata_channel *ch = device_get_softc(dev); 3728 3729 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3730 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 3731 return ata_pci_status(dev); 3732 } 3733 return 0; 3734 } 3735 3736 static int 3737 ata_promise_mio_allocate(device_t dev) 3738 { 3739 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3740 struct ata_channel *ch = device_get_softc(dev); 3741 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0; 3742 int i; 3743 3744 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 3745 ch->r_io[i].res = ctlr->r_res2; 3746 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 3747 } 3748 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 3749 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 3750 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 3751 ata_default_registers(dev); 3752 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) || 3753 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) { 3754 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3755 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 3756 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3757 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 3758 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3759 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 3760 ch->flags |= ATA_NO_SLAVE; 3761 } 3762 ch->flags |= ATA_USE_16BIT; 3763 3764 ata_generic_hw(dev); 3765 if (ctlr->chip->cfg2 & PRSX4X) { 3766 ch->hw.command = ata_promise_sx4_command; 3767 } 3768 else { 3769 ch->hw.command = ata_promise_mio_command; 3770 ch->hw.status = ata_promise_mio_status; 3771 } 3772 return 0; 3773 } 3774 3775 static void 3776 ata_promise_mio_intr(void *data) 3777 { 3778 struct ata_pci_controller *ctlr = data; 3779 struct ata_channel *ch; 3780 u_int32_t vector; 3781 int unit, fake_reg; 3782 3783 switch (ctlr->chip->cfg2) { 3784 case PRPATA: 3785 case PRCMBO: 3786 case PRSATA: 3787 fake_reg = 0x60; 3788 break; 3789 case PRCMBO2: 3790 case PRSATA2: 3791 default: 3792 fake_reg = 0x54; 3793 break; 3794 } 3795 3796 /* 3797 * since reading interrupt status register on early "mio" chips 3798 * clears the status bits we cannot read it for each channel later on 3799 * in the generic interrupt routine. 3800 * store the bits in an unused register in the chip so we can read 3801 * it from there safely to get around this "feature". 3802 */ 3803 vector = ATA_INL(ctlr->r_res2, 0x040); 3804 ATA_OUTL(ctlr->r_res2, 0x040, vector); 3805 ATA_OUTL(ctlr->r_res2, fake_reg, vector); 3806 3807 for (unit = 0; unit < ctlr->channels; unit++) { 3808 if ((ch = ctlr->interrupt[unit].argument)) 3809 ctlr->interrupt[unit].function(ch); 3810 } 3811 3812 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3813 } 3814 3815 static int 3816 ata_promise_mio_status(device_t dev) 3817 { 3818 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3819 struct ata_channel *ch = device_get_softc(dev); 3820 struct ata_connect_task *tp; 3821 u_int32_t fake_reg, stat_reg, vector, status; 3822 3823 switch (ctlr->chip->cfg2) { 3824 case PRPATA: 3825 case PRCMBO: 3826 case PRSATA: 3827 fake_reg = 0x60; 3828 stat_reg = 0x6c; 3829 break; 3830 case PRCMBO2: 3831 case PRSATA2: 3832 default: 3833 fake_reg = 0x54; 3834 stat_reg = 0x60; 3835 break; 3836 } 3837 3838 /* read and acknowledge interrupt */ 3839 vector = ATA_INL(ctlr->r_res2, fake_reg); 3840 3841 /* read and clear interface status */ 3842 status = ATA_INL(ctlr->r_res2, stat_reg); 3843 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 3844 3845 /* check for and handle disconnect events */ 3846 if ((status & (0x00000001 << ch->unit)) && 3847 (tp = (struct ata_connect_task *) 3848 kmalloc(sizeof(struct ata_connect_task), 3849 M_ATA, M_INTWAIT | M_ZERO))) { 3850 3851 if (bootverbose) 3852 device_printf(ch->dev, "DISCONNECT requested\n"); 3853 tp->action = ATA_C_DETACH; 3854 tp->dev = ch->dev; 3855 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3856 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3857 } 3858 3859 /* check for and handle connect events */ 3860 if ((status & (0x00000010 << ch->unit)) && 3861 (tp = (struct ata_connect_task *) 3862 kmalloc(sizeof(struct ata_connect_task), 3863 M_ATA, M_INTWAIT | M_ZERO))) { 3864 3865 if (bootverbose) 3866 device_printf(ch->dev, "CONNECT requested\n"); 3867 tp->action = ATA_C_ATTACH; 3868 tp->dev = ch->dev; 3869 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3870 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3871 } 3872 3873 /* do we have any device action ? */ 3874 return (vector & (1 << (ch->unit + 1))); 3875 } 3876 3877 static int 3878 ata_promise_mio_command(struct ata_request *request) 3879 { 3880 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 3881 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 3882 u_int32_t *wordp = (u_int32_t *)ch->dma->work; 3883 3884 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 3885 3886 /* XXX SOS add ATAPI commands support later */ 3887 switch (request->u.ata.command) { 3888 default: 3889 return ata_generic_command(request); 3890 3891 case ATA_READ_DMA: 3892 case ATA_READ_DMA48: 3893 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3894 break; 3895 3896 case ATA_WRITE_DMA: 3897 case ATA_WRITE_DMA48: 3898 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3899 break; 3900 } 3901 wordp[1] = htole32(ch->dma->sg_bus); 3902 wordp[2] = 0; 3903 ata_promise_apkt((u_int8_t*)wordp, request); 3904 3905 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus); 3906 return 0; 3907 } 3908 3909 static void 3910 ata_promise_mio_reset(device_t dev) 3911 { 3912 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3913 struct ata_channel *ch = device_get_softc(dev); 3914 struct ata_promise_sx4 *hpktp; 3915 3916 switch (ctlr->chip->cfg2) { 3917 case PRSX4X: 3918 3919 /* softreset channel ATA module */ 3920 hpktp = device_get_ivars(ctlr->dev); 3921 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 3922 ata_udelay(1000); 3923 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 3924 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 3925 ~0x00003f9f) | (ch->unit + 1)); 3926 3927 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 3928 spin_lock_wr(&hpktp->mtx); 3929 ATA_OUTL(ctlr->r_res2, 0xc012c, 3930 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 3931 DELAY(10); 3932 ATA_OUTL(ctlr->r_res2, 0xc012c, 3933 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 3934 hpktp->busy = 0; 3935 spin_unlock_wr(&hpktp->mtx); 3936 ata_generic_reset(dev); 3937 break; 3938 3939 case PRPATA: 3940 case PRCMBO: 3941 case PRSATA: 3942 if ((ctlr->chip->cfg2 == PRSATA) || 3943 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 3944 3945 /* mask plug/unplug intr */ 3946 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 3947 } 3948 3949 /* softreset channels ATA module */ 3950 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 3951 ata_udelay(10000); 3952 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 3953 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 3954 ~0x00003f9f) | (ch->unit + 1)); 3955 3956 if ((ctlr->chip->cfg2 == PRSATA) || 3957 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 3958 3959 if (ata_sata_phy_reset(dev)) 3960 ata_generic_reset(dev); 3961 3962 /* reset and enable plug/unplug intr */ 3963 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 3964 } 3965 else 3966 ata_generic_reset(dev); 3967 break; 3968 3969 case PRCMBO2: 3970 case PRSATA2: 3971 if ((ctlr->chip->cfg2 == PRSATA2) || 3972 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 3973 /* set portmultiplier port */ 3974 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 3975 3976 /* mask plug/unplug intr */ 3977 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 3978 } 3979 3980 /* softreset channels ATA module */ 3981 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 3982 ata_udelay(10000); 3983 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 3984 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 3985 ~0x00003f9f) | (ch->unit + 1)); 3986 3987 if ((ctlr->chip->cfg2 == PRSATA2) || 3988 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 3989 3990 /* set PHY mode to "improved" */ 3991 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 3992 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 3993 ~0x00000003) | 0x00000001); 3994 3995 if (ata_sata_phy_reset(dev)) 3996 ata_generic_reset(dev); 3997 3998 /* reset and enable plug/unplug intr */ 3999 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 4000 4001 /* set portmultiplier port */ 4002 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 4003 } 4004 else 4005 ata_generic_reset(dev); 4006 break; 4007 4008 } 4009 } 4010 4011 static void 4012 ata_promise_mio_dmainit(device_t dev) 4013 { 4014 /* note start and stop are not used here */ 4015 ata_dmainit(dev); 4016 } 4017 4018 static void 4019 ata_promise_mio_setmode(device_t dev, int mode) 4020 { 4021 device_t gparent = GRANDPARENT(dev); 4022 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4023 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4024 4025 if ( (ctlr->chip->cfg2 == PRSATA) || 4026 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) || 4027 (ctlr->chip->cfg2 == PRSATA2) || 4028 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) 4029 ata_sata_setmode(dev, mode); 4030 else 4031 ata_promise_setmode(dev, mode); 4032 } 4033 4034 static void 4035 ata_promise_sx4_intr(void *data) 4036 { 4037 struct ata_pci_controller *ctlr = data; 4038 struct ata_channel *ch; 4039 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 4040 int unit; 4041 4042 for (unit = 0; unit < ctlr->channels; unit++) { 4043 if (vector & (1 << (unit + 1))) 4044 if ((ch = ctlr->interrupt[unit].argument)) 4045 ctlr->interrupt[unit].function(ch); 4046 if (vector & (1 << (unit + 5))) 4047 if ((ch = ctlr->interrupt[unit].argument)) 4048 ata_promise_queue_hpkt(ctlr, 4049 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 4050 ATA_PDC_HPKT_OFFSET)); 4051 if (vector & (1 << (unit + 9))) { 4052 ata_promise_next_hpkt(ctlr); 4053 if ((ch = ctlr->interrupt[unit].argument)) 4054 ctlr->interrupt[unit].function(ch); 4055 } 4056 if (vector & (1 << (unit + 13))) { 4057 ata_promise_next_hpkt(ctlr); 4058 if ((ch = ctlr->interrupt[unit].argument)) 4059 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4060 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 4061 ATA_PDC_APKT_OFFSET)); 4062 } 4063 } 4064 } 4065 4066 static int 4067 ata_promise_sx4_command(struct ata_request *request) 4068 { 4069 device_t gparent = GRANDPARENT(request->dev); 4070 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4071 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4072 struct ata_dma_prdentry *prd = ch->dma->sg; 4073 caddr_t window = rman_get_virtual(ctlr->r_res1); 4074 u_int32_t *wordp; 4075 int i, idx, length = 0; 4076 4077 /* XXX SOS add ATAPI commands support later */ 4078 switch (request->u.ata.command) { 4079 4080 default: 4081 return -1; 4082 4083 case ATA_ATA_IDENTIFY: 4084 case ATA_READ: 4085 case ATA_READ48: 4086 case ATA_READ_MUL: 4087 case ATA_READ_MUL48: 4088 case ATA_WRITE: 4089 case ATA_WRITE48: 4090 case ATA_WRITE_MUL: 4091 case ATA_WRITE_MUL48: 4092 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4093 return ata_generic_command(request); 4094 4095 case ATA_SETFEATURES: 4096 case ATA_FLUSHCACHE: 4097 case ATA_FLUSHCACHE48: 4098 case ATA_SLEEP: 4099 case ATA_SET_MULTI: 4100 wordp = (u_int32_t *) 4101 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4102 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 4103 wordp[1] = 0; 4104 wordp[2] = 0; 4105 ata_promise_apkt((u_int8_t *)wordp, request); 4106 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4107 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4108 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4109 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 4110 return 0; 4111 4112 case ATA_READ_DMA: 4113 case ATA_READ_DMA48: 4114 case ATA_WRITE_DMA: 4115 case ATA_WRITE_DMA48: 4116 wordp = (u_int32_t *) 4117 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 4118 i = idx = 0; 4119 do { 4120 wordp[idx++] = prd[i].addr; 4121 wordp[idx++] = prd[i].count; 4122 length += (prd[i].count & ~ATA_DMA_EOT); 4123 } while (!(prd[i++].count & ATA_DMA_EOT)); 4124 4125 wordp = (u_int32_t *) 4126 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 4127 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4128 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4129 4130 wordp = (u_int32_t *) 4131 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 4132 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4133 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4134 4135 wordp = (u_int32_t *) 4136 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 4137 if (request->flags & ATA_R_READ) 4138 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 4139 if (request->flags & ATA_R_WRITE) 4140 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 4141 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 4142 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 4143 wordp[3] = 0; 4144 4145 wordp = (u_int32_t *) 4146 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4147 if (request->flags & ATA_R_READ) 4148 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 4149 if (request->flags & ATA_R_WRITE) 4150 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 4151 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 4152 wordp[2] = 0; 4153 ata_promise_apkt((u_int8_t *)wordp, request); 4154 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4155 4156 if (request->flags & ATA_R_READ) { 4157 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 4158 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 4159 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4160 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 4161 } 4162 if (request->flags & ATA_R_WRITE) { 4163 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 4164 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 4165 ata_promise_queue_hpkt(ctlr, 4166 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 4167 } 4168 return 0; 4169 } 4170 } 4171 4172 static int 4173 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 4174 { 4175 struct ata_device *atadev = device_get_softc(request->dev); 4176 int i = 12; 4177 4178 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 4179 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit; 4180 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 4181 bytep[i++] = ATA_A_4BIT; 4182 4183 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 4184 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4185 bytep[i++] = request->u.ata.feature >> 8; 4186 bytep[i++] = request->u.ata.feature; 4187 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 4188 bytep[i++] = request->u.ata.count >> 8; 4189 bytep[i++] = request->u.ata.count; 4190 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4191 bytep[i++] = request->u.ata.lba >> 24; 4192 bytep[i++] = request->u.ata.lba; 4193 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4194 bytep[i++] = request->u.ata.lba >> 32; 4195 bytep[i++] = request->u.ata.lba >> 8; 4196 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4197 bytep[i++] = request->u.ata.lba >> 40; 4198 bytep[i++] = request->u.ata.lba >> 16; 4199 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4200 bytep[i++] = ATA_D_LBA | atadev->unit; 4201 } 4202 else { 4203 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4204 bytep[i++] = request->u.ata.feature; 4205 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 4206 bytep[i++] = request->u.ata.count; 4207 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4208 bytep[i++] = request->u.ata.lba; 4209 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4210 bytep[i++] = request->u.ata.lba >> 8; 4211 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4212 bytep[i++] = request->u.ata.lba >> 16; 4213 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4214 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) | 4215 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf); 4216 } 4217 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 4218 bytep[i++] = request->u.ata.command; 4219 return i; 4220 } 4221 4222 static void 4223 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 4224 { 4225 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4226 4227 spin_lock_wr(&hpktp->mtx); 4228 if (hpktp->busy) { 4229 struct host_packet *hp = 4230 kmalloc(sizeof(struct host_packet), M_TEMP, M_INTWAIT | M_ZERO); 4231 hp->addr = hpkt; 4232 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 4233 } 4234 else { 4235 hpktp->busy = 1; 4236 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 4237 } 4238 spin_unlock_wr(&hpktp->mtx); 4239 } 4240 4241 static void 4242 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 4243 { 4244 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4245 struct host_packet *hp; 4246 4247 spin_lock_wr(&hpktp->mtx); 4248 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 4249 TAILQ_REMOVE(&hpktp->queue, hp, chain); 4250 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 4251 kfree(hp, M_TEMP); 4252 } 4253 else 4254 hpktp->busy = 0; 4255 spin_unlock_wr(&hpktp->mtx); 4256 } 4257 4258 4259 /* 4260 * ServerWorks chipset support functions 4261 */ 4262 int 4263 ata_serverworks_ident(device_t dev) 4264 { 4265 struct ata_pci_controller *ctlr = device_get_softc(dev); 4266 struct ata_chip_id *idx; 4267 static struct ata_chip_id ids[] = 4268 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" }, 4269 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" }, 4270 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" }, 4271 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" }, 4272 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" }, 4273 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" }, 4274 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" }, 4275 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" }, 4276 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" }, 4277 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" }, 4278 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" }, 4279 { 0, 0, 0, 0, 0, 0}}; 4280 char buffer[64]; 4281 4282 if (!(idx = ata_match_chip(dev, ids))) 4283 return ENXIO; 4284 4285 ksprintf(buffer, "ServerWorks %s %s controller", 4286 idx->text, ata_mode2str(idx->max_dma)); 4287 device_set_desc_copy(dev, buffer); 4288 ctlr->chip = idx; 4289 ctlr->chipinit = ata_serverworks_chipinit; 4290 return 0; 4291 } 4292 4293 static int 4294 ata_serverworks_chipinit(device_t dev) 4295 { 4296 struct ata_pci_controller *ctlr = device_get_softc(dev); 4297 4298 if (ata_setup_interrupt(dev)) 4299 return ENXIO; 4300 4301 if (ctlr->chip->cfg1 == SWKSMIO) { 4302 ctlr->r_type2 = SYS_RES_MEMORY; 4303 ctlr->r_rid2 = PCIR_BAR(5); 4304 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4305 &ctlr->r_rid2, RF_ACTIVE))) 4306 return ENXIO; 4307 4308 ctlr->channels = ctlr->chip->cfg2; 4309 ctlr->allocate = ata_serverworks_allocate; 4310 ctlr->setmode = ata_sata_setmode; 4311 return 0; 4312 } 4313 else if (ctlr->chip->cfg1 == SWKS33) { 4314 device_t *children; 4315 int nchildren, i; 4316 4317 /* locate the ISA part in the southbridge and enable UDMA33 */ 4318 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 4319 for (i = 0; i < nchildren; i++) { 4320 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 4321 pci_write_config(children[i], 0x64, 4322 (pci_read_config(children[i], 0x64, 4) & 4323 ~0x00002000) | 0x00004000, 4); 4324 break; 4325 } 4326 } 4327 kfree(children, M_TEMP); 4328 } 4329 } 4330 else { 4331 pci_write_config(dev, 0x5a, 4332 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 4333 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1); 4334 } 4335 ctlr->setmode = ata_serverworks_setmode; 4336 return 0; 4337 } 4338 4339 static int 4340 ata_serverworks_allocate(device_t dev) 4341 { 4342 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4343 struct ata_channel *ch = device_get_softc(dev); 4344 int ch_offset; 4345 int i; 4346 4347 ch_offset = ch->unit * 0x100; 4348 4349 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 4350 ch->r_io[i].res = ctlr->r_res2; 4351 4352 /* setup ATA registers */ 4353 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 4354 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 4355 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 4356 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 4357 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 4358 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 4359 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 4360 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 4361 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 4362 ata_default_registers(dev); 4363 4364 /* setup DMA registers */ 4365 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 4366 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 4367 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 4368 4369 /* setup SATA registers */ 4370 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 4371 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 4372 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 4373 4374 ch->flags |= ATA_NO_SLAVE; 4375 ata_pci_hw(dev); 4376 4377 /* chip does not reliably do 64K DMA transfers */ 4378 if (ch->dma) 4379 ch->dma->max_iosize = 126 * DEV_BSIZE; 4380 4381 return 0; 4382 } 4383 4384 static void 4385 ata_serverworks_setmode(device_t dev, int mode) 4386 { 4387 device_t gparent = GRANDPARENT(dev); 4388 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4389 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4390 struct ata_device *atadev = device_get_softc(dev); 4391 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4392 int offset = (devno ^ 0x01) << 3; 4393 int error; 4394 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 4395 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 4396 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 4397 4398 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4399 4400 mode = ata_check_80pin(dev, mode); 4401 4402 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4403 4404 if (bootverbose) 4405 device_printf(dev, "%ssetting %s on %s chip\n", 4406 (error) ? "FAILURE " : "", 4407 ata_mode2str(mode), ctlr->chip->text); 4408 if (!error) { 4409 if (mode >= ATA_UDMA0) { 4410 pci_write_config(gparent, 0x56, 4411 (pci_read_config(gparent, 0x56, 2) & 4412 ~(0xf << (devno << 2))) | 4413 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 4414 pci_write_config(gparent, 0x54, 4415 pci_read_config(gparent, 0x54, 1) | 4416 (0x01 << devno), 1); 4417 pci_write_config(gparent, 0x44, 4418 (pci_read_config(gparent, 0x44, 4) & 4419 ~(0xff << offset)) | 4420 (dmatimings[2] << offset), 4); 4421 } 4422 else if (mode >= ATA_WDMA0) { 4423 pci_write_config(gparent, 0x54, 4424 pci_read_config(gparent, 0x54, 1) & 4425 ~(0x01 << devno), 1); 4426 pci_write_config(gparent, 0x44, 4427 (pci_read_config(gparent, 0x44, 4) & 4428 ~(0xff << offset)) | 4429 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 4430 } 4431 else 4432 pci_write_config(gparent, 0x54, 4433 pci_read_config(gparent, 0x54, 1) & 4434 ~(0x01 << devno), 1); 4435 4436 pci_write_config(gparent, 0x40, 4437 (pci_read_config(gparent, 0x40, 4) & 4438 ~(0xff << offset)) | 4439 (piotimings[ata_mode2idx(mode)] << offset), 4); 4440 atadev->mode = mode; 4441 } 4442 } 4443 4444 4445 /* 4446 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 4447 */ 4448 int 4449 ata_sii_ident(device_t dev) 4450 { 4451 struct ata_pci_controller *ctlr = device_get_softc(dev); 4452 struct ata_chip_id *idx; 4453 static struct ata_chip_id ids[] = 4454 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" }, 4455 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" }, 4456 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4457 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4458 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" }, 4459 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4460 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4461 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" }, 4462 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" }, 4463 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" }, 4464 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" }, 4465 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" }, 4466 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" }, 4467 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" }, 4468 { 0, 0, 0, 0, 0, 0}}; 4469 char buffer[64]; 4470 4471 if (!(idx = ata_match_chip(dev, ids))) 4472 return ENXIO; 4473 4474 ksprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); 4475 device_set_desc_copy(dev, buffer); 4476 ctlr->chip = idx; 4477 ctlr->chipinit = ata_sii_chipinit; 4478 return 0; 4479 } 4480 4481 static int 4482 ata_sii_chipinit(device_t dev) 4483 { 4484 struct ata_pci_controller *ctlr = device_get_softc(dev); 4485 4486 if (ata_setup_interrupt(dev)) 4487 return ENXIO; 4488 4489 switch (ctlr->chip->cfg1) { 4490 case SIIPRBIO: 4491 ctlr->r_type1 = SYS_RES_MEMORY; 4492 ctlr->r_rid1 = PCIR_BAR(0); 4493 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 4494 &ctlr->r_rid1, RF_ACTIVE))) 4495 return ENXIO; 4496 4497 ctlr->r_rid2 = PCIR_BAR(2); 4498 ctlr->r_type2 = SYS_RES_MEMORY; 4499 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4500 &ctlr->r_rid2, RF_ACTIVE))){ 4501 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 4502 return ENXIO; 4503 } 4504 ctlr->allocate = ata_siiprb_allocate; 4505 ctlr->reset = ata_siiprb_reset; 4506 ctlr->dmainit = ata_siiprb_dmainit; 4507 ctlr->setmode = ata_sata_setmode; 4508 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2; 4509 4510 /* reset controller */ 4511 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 4512 DELAY(10000); 4513 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 4514 4515 /* enable PCI interrupt */ 4516 pci_write_config(dev, PCIR_COMMAND, 4517 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 4518 break; 4519 4520 case SIIMEMIO: 4521 ctlr->r_type2 = SYS_RES_MEMORY; 4522 ctlr->r_rid2 = PCIR_BAR(5); 4523 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4524 &ctlr->r_rid2, RF_ACTIVE))) 4525 return ENXIO; 4526 4527 if (ctlr->chip->cfg2 & SIISETCLK) { 4528 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4529 pci_write_config(dev, 0x8a, 4530 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 4531 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4532 device_printf(dev, "%s could not set ATA133 clock\n", 4533 ctlr->chip->text); 4534 } 4535 4536 /* if we have 4 channels enable the second set */ 4537 if (ctlr->chip->cfg2 & SII4CH) { 4538 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 4539 ctlr->channels = 4; 4540 } 4541 4542 /* dont block interrupts from any channel */ 4543 pci_write_config(dev, 0x48, 4544 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 4545 4546 /* enable PCI interrupt as BIOS might not */ 4547 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 4548 4549 ctlr->allocate = ata_sii_allocate; 4550 if (ctlr->chip->max_dma >= ATA_SA150) { 4551 ctlr->reset = ata_sii_reset; 4552 ctlr->setmode = ata_sata_setmode; 4553 } 4554 else 4555 ctlr->setmode = ata_sii_setmode; 4556 break; 4557 4558 default: 4559 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 4560 device_printf(dev, "HW has secondary channel disabled\n"); 4561 ctlr->channels = 1; 4562 } 4563 4564 /* enable interrupt as BIOS might not */ 4565 pci_write_config(dev, 0x71, 0x01, 1); 4566 4567 ctlr->allocate = ata_cmd_allocate; 4568 ctlr->setmode = ata_cmd_setmode; 4569 break; 4570 } 4571 return 0; 4572 } 4573 4574 static int 4575 ata_cmd_allocate(device_t dev) 4576 { 4577 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4578 struct ata_channel *ch = device_get_softc(dev); 4579 4580 /* setup the usual register normal pci style */ 4581 if (ata_pci_allocate(dev)) 4582 return ENXIO; 4583 4584 if (ctlr->chip->cfg2 & SIIINTR) 4585 ch->hw.status = ata_cmd_status; 4586 4587 return 0; 4588 } 4589 4590 static int 4591 ata_cmd_status(device_t dev) 4592 { 4593 struct ata_channel *ch = device_get_softc(dev); 4594 u_int8_t reg71; 4595 4596 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) & 4597 (ch->unit ? 0x08 : 0x04))) { 4598 pci_write_config(device_get_parent(ch->dev), 0x71, 4599 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 4600 return ata_pci_status(dev); 4601 } 4602 return 0; 4603 } 4604 4605 static void 4606 ata_cmd_setmode(device_t dev, int mode) 4607 { 4608 device_t gparent = GRANDPARENT(dev); 4609 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4610 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4611 struct ata_device *atadev = device_get_softc(dev); 4612 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4613 int error; 4614 4615 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4616 4617 mode = ata_check_80pin(dev, mode); 4618 4619 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4620 4621 if (bootverbose) 4622 device_printf(dev, "%ssetting %s on %s chip\n", 4623 (error) ? "FAILURE " : "", 4624 ata_mode2str(mode), ctlr->chip->text); 4625 if (!error) { 4626 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 4627 int ureg = ch->unit ? 0x7b : 0x73; 4628 4629 if (mode >= ATA_UDMA0) { 4630 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 4631 { 0x11, 0x42 }, { 0x25, 0x8a }, 4632 { 0x15, 0x4a }, { 0x05, 0x0a } }; 4633 4634 u_int8_t umode = pci_read_config(gparent, ureg, 1); 4635 4636 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca); 4637 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)]; 4638 pci_write_config(gparent, ureg, umode, 1); 4639 } 4640 else if (mode >= ATA_WDMA0) { 4641 int dmatimings[] = { 0x87, 0x32, 0x3f }; 4642 4643 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1); 4644 pci_write_config(gparent, ureg, 4645 pci_read_config(gparent, ureg, 1) & 4646 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4647 } 4648 else { 4649 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f }; 4650 pci_write_config(gparent, treg, 4651 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1); 4652 pci_write_config(gparent, ureg, 4653 pci_read_config(gparent, ureg, 1) & 4654 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4655 } 4656 atadev->mode = mode; 4657 } 4658 } 4659 4660 static int 4661 ata_sii_allocate(device_t dev) 4662 { 4663 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4664 struct ata_channel *ch = device_get_softc(dev); 4665 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 4666 int i; 4667 4668 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 4669 ch->r_io[i].res = ctlr->r_res2; 4670 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 4671 } 4672 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 4673 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 4674 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 4675 ata_default_registers(dev); 4676 4677 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 4678 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 4679 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 4680 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 4681 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 4682 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 4683 4684 if (ctlr->chip->max_dma >= ATA_SA150) { 4685 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4686 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 4687 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4688 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 4689 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4690 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 4691 ch->flags |= ATA_NO_SLAVE; 4692 4693 /* enable PHY state change interrupt */ 4694 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 4695 } 4696 4697 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) { 4698 /* work around errata in early chips */ 4699 ch->dma->boundary = 16 * DEV_BSIZE; 4700 ch->dma->segsize = 15 * DEV_BSIZE; 4701 } 4702 4703 ata_pci_hw(dev); 4704 ch->hw.status = ata_sii_status; 4705 return 0; 4706 } 4707 4708 static int 4709 ata_sii_status(device_t dev) 4710 { 4711 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4712 struct ata_channel *ch = device_get_softc(dev); 4713 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 4714 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 4715 4716 /* do we have any PHY events ? */ 4717 if (ctlr->chip->max_dma >= ATA_SA150 && 4718 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 4719 ata_sata_phy_check_events(dev); 4720 4721 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 4722 return ata_pci_status(dev); 4723 else 4724 return 0; 4725 } 4726 4727 static void 4728 ata_sii_reset(device_t dev) 4729 { 4730 if (ata_sata_phy_reset(dev)) 4731 ata_generic_reset(dev); 4732 } 4733 4734 static void 4735 ata_sii_setmode(device_t dev, int mode) 4736 { 4737 device_t gparent = GRANDPARENT(dev); 4738 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4739 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4740 struct ata_device *atadev = device_get_softc(dev); 4741 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1); 4742 int mreg = ch->unit ? 0x84 : 0x80; 4743 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2); 4744 int mval = pci_read_config(gparent, mreg, 1) & ~mask; 4745 int error; 4746 4747 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4748 4749 if (ctlr->chip->cfg2 & SIISETCLK) { 4750 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) & 4751 (ch->unit ? 0x02 : 0x01))) { 4752 ata_print_cable(dev, "controller"); 4753 mode = ATA_UDMA2; 4754 } 4755 } 4756 else 4757 mode = ata_check_80pin(dev, mode); 4758 4759 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4760 4761 if (bootverbose) 4762 device_printf(dev, "%ssetting %s on %s chip\n", 4763 (error) ? "FAILURE " : "", 4764 ata_mode2str(mode), ctlr->chip->text); 4765 if (error) 4766 return; 4767 4768 if (mode >= ATA_UDMA0) { 4769 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 4770 u_int8_t ureg = 0xac + rego; 4771 4772 pci_write_config(gparent, mreg, 4773 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1); 4774 pci_write_config(gparent, ureg, 4775 (pci_read_config(gparent, ureg, 1) & ~0x3f) | 4776 udmatimings[mode & ATA_MODE_MASK], 1); 4777 4778 } 4779 else if (mode >= ATA_WDMA0) { 4780 u_int8_t dreg = 0xa8 + rego; 4781 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 4782 4783 pci_write_config(gparent, mreg, 4784 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1); 4785 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 4786 4787 } 4788 else { 4789 u_int8_t preg = 0xa4 + rego; 4790 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 4791 4792 pci_write_config(gparent, mreg, 4793 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1); 4794 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2); 4795 } 4796 atadev->mode = mode; 4797 } 4798 4799 struct ata_siiprb_dma_prdentry { 4800 u_int64_t addr; 4801 u_int32_t count; 4802 u_int32_t control; 4803 } __packed; 4804 4805 struct ata_siiprb_ata_command { 4806 u_int32_t reserved0; 4807 struct ata_siiprb_dma_prdentry prd[126]; 4808 } __packed; 4809 4810 struct ata_siiprb_atapi_command { 4811 u_int8_t cdb[16]; 4812 struct ata_siiprb_dma_prdentry prd[125]; 4813 } __packed; 4814 4815 struct ata_siiprb_command { 4816 u_int16_t control; 4817 u_int16_t protocol_override; 4818 u_int32_t transfer_count; 4819 u_int8_t fis[20]; 4820 union { 4821 struct ata_siiprb_ata_command ata; 4822 struct ata_siiprb_atapi_command atapi; 4823 } u; 4824 } __packed; 4825 4826 static int 4827 ata_siiprb_allocate(device_t dev) 4828 { 4829 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4830 struct ata_channel *ch = device_get_softc(dev); 4831 int offset = ch->unit * 0x2000; 4832 4833 /* set the SATA resources */ 4834 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4835 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 4836 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4837 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 4838 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4839 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 4840 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 4841 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 4842 4843 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 4844 ch->hw.end_transaction = ata_siiprb_end_transaction; 4845 ch->hw.status = ata_siiprb_status; 4846 ch->hw.command = NULL; /* not used here */ 4847 return 0; 4848 } 4849 4850 static int 4851 ata_siiprb_status(device_t dev) 4852 { 4853 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4854 struct ata_channel *ch = device_get_softc(dev); 4855 int offset = ch->unit * 0x2000; 4856 4857 if ((ATA_INL(ctlr->r_res1, 0x0044) & (1 << ch->unit))) { 4858 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 4859 4860 /* do we have any PHY events ? */ 4861 ata_sata_phy_check_events(dev); 4862 4863 /* clear interrupt(s) */ 4864 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 4865 4866 /* do we have any device action ? */ 4867 return (istatus & 0x00000001); 4868 } 4869 return 0; 4870 } 4871 4872 static int 4873 ata_siiprb_begin_transaction(struct ata_request *request) 4874 { 4875 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 4876 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4877 struct ata_siiprb_command *prb; 4878 int offset = ch->unit * 0x2000; 4879 u_int64_t prb_bus; 4880 int tag = 0, dummy; 4881 4882 /* check for 48 bit access and convert if needed */ 4883 ata_modify_if_48bit(request); 4884 4885 /* get a piece of the workspace for this request */ 4886 prb = (struct ata_siiprb_command *) 4887 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 4888 4889 /* set basic prd options ata/atapi etc etc */ 4890 bzero(prb, sizeof(struct ata_siiprb_command)); 4891 4892 /* setup the FIS for this request */ 4893 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 4894 device_printf(request->dev, "setting up SATA FIS failed\n"); 4895 request->result = EIO; 4896 return ATA_OP_FINISHED; 4897 } 4898 4899 /* if request moves data setup and load SG list */ 4900 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 4901 struct ata_siiprb_dma_prdentry *prd; 4902 4903 if (request->flags & ATA_R_ATAPI) 4904 prd = &prb->u.atapi.prd[0]; 4905 else 4906 prd = &prb->u.ata.prd[0]; 4907 if (ch->dma->load(ch->dev, request->data, request->bytecount, 4908 request->flags & ATA_R_READ, prd, &dummy)) { 4909 device_printf(request->dev, "setting up DMA failed\n"); 4910 request->result = EIO; 4911 return ATA_OP_FINISHED; 4912 } 4913 } 4914 4915 /* activate the prb */ 4916 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 4917 ATA_OUTL(ctlr->r_res2, 4918 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 4919 ATA_OUTL(ctlr->r_res2, 4920 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 4921 4922 /* start the timeout */ 4923 callout_reset(&request->callout, request->timeout * hz, 4924 (timeout_t*)ata_timeout, request); 4925 return ATA_OP_CONTINUES; 4926 } 4927 4928 static int 4929 ata_siiprb_end_transaction(struct ata_request *request) 4930 { 4931 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 4932 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4933 struct ata_siiprb_command *prb; 4934 int offset = ch->unit * 0x2000; 4935 int error, tag = 0; 4936 4937 /* kill the timeout */ 4938 callout_stop(&request->callout); 4939 4940 prb = (struct ata_siiprb_command *) 4941 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 4942 4943 /* if error status get details */ 4944 request->status = prb->fis[2]; 4945 if (request->status & ATA_S_ERROR) 4946 request->error = prb->fis[3]; 4947 4948 /* update progress */ 4949 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 4950 if (request->flags & ATA_R_READ) 4951 request->donecount = prb->transfer_count; 4952 else 4953 request->donecount = request->bytecount; 4954 } 4955 4956 /* any controller errors flagged ? */ 4957 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 4958 kprintf("ata_siiprb_end_transaction %s error=%08x\n", 4959 ata_cmd2str(request), error); 4960 } 4961 4962 /* release SG list etc */ 4963 ch->dma->unload(ch->dev); 4964 4965 return ATA_OP_FINISHED; 4966 } 4967 4968 static void 4969 ata_siiprb_reset(device_t dev) 4970 { 4971 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4972 struct ata_channel *ch = device_get_softc(dev); 4973 int offset = ch->unit * 0x2000; 4974 struct ata_siiprb_command *prb; 4975 u_int64_t prb_bus; 4976 u_int32_t status, signature; 4977 int timeout, tag = 0; 4978 4979 /* reset channel HW */ 4980 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 4981 DELAY(1000); 4982 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 4983 DELAY(10000); 4984 4985 /* poll for channel ready */ 4986 for (timeout = 0; timeout < 1000; timeout++) { 4987 if ((status = ATA_INL(ctlr->r_res2, 0x1000 + offset)) & 0x00040000) 4988 break; 4989 DELAY(1000); 4990 } 4991 if (timeout >= 1000) { 4992 device_printf(ch->dev, "channel HW reset timeout reset failure\n"); 4993 ch->devices = 0; 4994 goto finish; 4995 } 4996 if (bootverbose) 4997 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout * 1); 4998 4999 /* reset phy */ 5000 if (!ata_sata_phy_reset(dev)) { 5001 if (bootverbose) 5002 device_printf(ch->dev, "phy reset found no device\n"); 5003 ch->devices = 0; 5004 goto finish; 5005 } 5006 5007 /* get a piece of the workspace for a soft reset request */ 5008 prb = (struct ata_siiprb_command *) 5009 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 5010 bzero(prb, sizeof(struct ata_siiprb_command)); 5011 prb->control = htole16(0x0080); 5012 5013 /* activate the soft reset prb */ 5014 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 5015 ATA_OUTL(ctlr->r_res2, 5016 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 5017 ATA_OUTL(ctlr->r_res2, 5018 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 5019 5020 /* poll for channel ready */ 5021 for (timeout = 0; timeout < 1000; timeout++) { 5022 DELAY(1000); 5023 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 5024 break; 5025 } 5026 if (timeout >= 1000) { 5027 device_printf(ch->dev, "reset timeout - no device found\n"); 5028 ch->devices = 0; 5029 goto finish; 5030 } 5031 if (bootverbose) 5032 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n", 5033 timeout, status); 5034 5035 /* find out whats there */ 5036 prb = (struct ata_siiprb_command *) 5037 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 5038 signature = 5039 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 5040 if (bootverbose) 5041 device_printf(ch->dev, "signature=%08x\n", signature); 5042 switch (signature) { 5043 case 0xeb140101: 5044 ch->devices = ATA_ATAPI_MASTER; 5045 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n"); 5046 ch->devices = 0; 5047 break; 5048 case 0x96690101: 5049 ch->devices = ATA_PORTMULTIPLIER; 5050 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 5051 ch->devices = 0; 5052 break; 5053 case 0x00000101: 5054 ch->devices = ATA_ATA_MASTER; 5055 break; 5056 default: 5057 ch->devices = 0; 5058 } 5059 5060 finish: 5061 /* clear interrupt(s) */ 5062 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 5063 5064 /* require explicit interrupt ack */ 5065 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 5066 5067 /* 64bit mode */ 5068 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 5069 5070 /* enable interrupts wanted */ 5071 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 5072 } 5073 5074 static void 5075 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 5076 { 5077 struct ata_dmasetprd_args *args = xsc; 5078 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 5079 int i; 5080 5081 if ((args->error = error)) 5082 return; 5083 5084 for (i = 0; i < nsegs; i++) { 5085 prd[i].addr = htole64(segs[i].ds_addr); 5086 prd[i].count = htole32(segs[i].ds_len); 5087 } 5088 prd[i - 1].control = htole32(ATA_DMA_EOT); 5089 } 5090 5091 static void 5092 ata_siiprb_dmainit(device_t dev) 5093 { 5094 struct ata_channel *ch = device_get_softc(dev); 5095 5096 ata_dmainit(dev); 5097 if (ch->dma) { 5098 /* note start and stop are not used here */ 5099 ch->dma->setprd = ata_siiprb_dmasetprd; 5100 ch->dma->max_address = BUS_SPACE_MAXADDR; 5101 } 5102 } 5103 5104 5105 /* 5106 * Silicon Integrated Systems Corp. (SiS) chipset support functions 5107 */ 5108 int 5109 ata_sis_ident(device_t dev) 5110 { 5111 struct ata_pci_controller *ctlr = device_get_softc(dev); 5112 struct ata_chip_id *idx; 5113 static struct ata_chip_id ids[] = 5114 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */ 5115 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */ 5116 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */ 5117 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */ 5118 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */ 5119 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */ 5120 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */ 5121 5122 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */ 5123 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */ 5124 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */ 5125 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */ 5126 5127 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */ 5128 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */ 5129 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */ 5130 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */ 5131 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */ 5132 5133 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" }, 5134 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" }, 5135 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" }, 5136 5137 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" }, 5138 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" }, 5139 { 0, 0, 0, 0, 0, 0 }}; 5140 char buffer[64]; 5141 int found = 0; 5142 5143 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev)))) 5144 return ENXIO; 5145 5146 if (idx->cfg2 && !found) { 5147 u_int8_t reg57 = pci_read_config(dev, 0x57, 1); 5148 5149 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1); 5150 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) { 5151 found = 1; 5152 idx->cfg1 = SIS133NEW; 5153 idx->max_dma = ATA_UDMA6; 5154 ksprintf(buffer, "SiS 962/963 %s controller", 5155 ata_mode2str(idx->max_dma)); 5156 } 5157 pci_write_config(dev, 0x57, reg57, 1); 5158 } 5159 if (idx->cfg2 && !found) { 5160 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1); 5161 5162 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1); 5163 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) { 5164 struct ata_chip_id id[] = 5165 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }}; 5166 5167 found = 1; 5168 if (ata_find_chip(dev, id, pci_get_slot(dev))) { 5169 idx->cfg1 = SIS133OLD; 5170 idx->max_dma = ATA_UDMA6; 5171 } 5172 else { 5173 idx->cfg1 = SIS100NEW; 5174 idx->max_dma = ATA_UDMA5; 5175 } 5176 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma)); 5177 } 5178 pci_write_config(dev, 0x4a, reg4a, 1); 5179 } 5180 if (!found) 5181 ksprintf(buffer,"SiS %s %s controller", 5182 idx->text, ata_mode2str(idx->max_dma)); 5183 5184 device_set_desc_copy(dev, buffer); 5185 ctlr->chip = idx; 5186 ctlr->chipinit = ata_sis_chipinit; 5187 return 0; 5188 } 5189 5190 static int 5191 ata_sis_chipinit(device_t dev) 5192 { 5193 struct ata_pci_controller *ctlr = device_get_softc(dev); 5194 5195 if (ata_setup_interrupt(dev)) 5196 return ENXIO; 5197 5198 switch (ctlr->chip->cfg1) { 5199 case SIS33: 5200 break; 5201 case SIS66: 5202 case SIS100OLD: 5203 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1); 5204 break; 5205 case SIS100NEW: 5206 case SIS133OLD: 5207 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1); 5208 break; 5209 case SIS133NEW: 5210 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2); 5211 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2); 5212 break; 5213 case SISSATA: 5214 ctlr->r_type2 = SYS_RES_IOPORT; 5215 ctlr->r_rid2 = PCIR_BAR(5); 5216 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5217 &ctlr->r_rid2, RF_ACTIVE))) { 5218 ctlr->allocate = ata_sis_allocate; 5219 ctlr->reset = ata_sis_reset; 5220 5221 /* enable PCI interrupt */ 5222 pci_write_config(dev, PCIR_COMMAND, 5223 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5224 } 5225 ctlr->setmode = ata_sata_setmode; 5226 return 0; 5227 default: 5228 return ENXIO; 5229 } 5230 ctlr->setmode = ata_sis_setmode; 5231 return 0; 5232 } 5233 5234 static int 5235 ata_sis_allocate(device_t dev) 5236 { 5237 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5238 struct ata_channel *ch = device_get_softc(dev); 5239 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6); 5240 5241 /* setup the usual register normal pci style */ 5242 if (ata_pci_allocate(dev)) 5243 return ENXIO; 5244 5245 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5246 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; 5247 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5248 ch->r_io[ATA_SERROR].offset = 0x04 + offset; 5249 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5250 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; 5251 ch->flags |= ATA_NO_SLAVE; 5252 5253 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ 5254 /* XXX SOS unknown how to enable PHY state change interrupt */ 5255 return 0; 5256 } 5257 5258 static void 5259 ata_sis_reset(device_t dev) 5260 { 5261 if (ata_sata_phy_reset(dev)) 5262 ata_generic_reset(dev); 5263 } 5264 5265 static void 5266 ata_sis_setmode(device_t dev, int mode) 5267 { 5268 device_t gparent = GRANDPARENT(dev); 5269 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5270 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5271 struct ata_device *atadev = device_get_softc(dev); 5272 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5273 int error; 5274 5275 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5276 5277 if (ctlr->chip->cfg1 == SIS133NEW) { 5278 if (mode > ATA_UDMA2 && 5279 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) { 5280 ata_print_cable(dev, "controller"); 5281 mode = ATA_UDMA2; 5282 } 5283 } 5284 else { 5285 if (mode > ATA_UDMA2 && 5286 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) { 5287 ata_print_cable(dev, "controller"); 5288 mode = ATA_UDMA2; 5289 } 5290 } 5291 5292 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5293 5294 if (bootverbose) 5295 device_printf(dev, "%ssetting %s on %s chip\n", 5296 (error) ? "FAILURE " : "", 5297 ata_mode2str(mode), ctlr->chip->text); 5298 if (!error) { 5299 switch (ctlr->chip->cfg1) { 5300 case SIS133NEW: { 5301 u_int32_t timings[] = 5302 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 5303 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 5304 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; 5305 u_int32_t reg; 5306 5307 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); 5308 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4); 5309 break; 5310 } 5311 case SIS133OLD: { 5312 u_int16_t timings[] = 5313 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 5314 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; 5315 5316 u_int16_t reg = 0x40 + (devno << 1); 5317 5318 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5319 break; 5320 } 5321 case SIS100NEW: { 5322 u_int16_t timings[] = 5323 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 5324 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; 5325 u_int16_t reg = 0x40 + (devno << 1); 5326 5327 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5328 break; 5329 } 5330 case SIS100OLD: 5331 case SIS66: 5332 case SIS33: { 5333 u_int16_t timings[] = 5334 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 5335 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; 5336 u_int16_t reg = 0x40 + (devno << 1); 5337 5338 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5339 break; 5340 } 5341 } 5342 atadev->mode = mode; 5343 } 5344 } 5345 5346 5347 /* VIA Technologies Inc. chipset support functions */ 5348 int 5349 ata_via_ident(device_t dev) 5350 { 5351 struct ata_pci_controller *ctlr = device_get_softc(dev); 5352 struct ata_chip_id *idx; 5353 static struct ata_chip_id ids[] = 5354 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 5355 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 5356 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 5357 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 5358 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 5359 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 5360 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 5361 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 5362 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 5363 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 5364 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 5365 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 5366 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 5367 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 5368 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 5369 { 0, 0, 0, 0, 0, 0 }}; 5370 static struct ata_chip_id new_ids[] = 5371 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 5372 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 5373 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 5374 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 5375 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" }, 5376 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" }, 5377 { 0, 0, 0, 0, 0, 0 }}; 5378 char buffer[64]; 5379 5380 if (pci_get_devid(dev) == ATA_VIA82C571) { 5381 if (!(idx = ata_find_chip(dev, ids, -99))) 5382 return ENXIO; 5383 } 5384 else { 5385 if (!(idx = ata_match_chip(dev, new_ids))) 5386 return ENXIO; 5387 } 5388 5389 ksprintf(buffer, "VIA %s %s controller", 5390 idx->text, ata_mode2str(idx->max_dma)); 5391 device_set_desc_copy(dev, buffer); 5392 ctlr->chip = idx; 5393 ctlr->chipinit = ata_via_chipinit; 5394 return 0; 5395 } 5396 5397 static int 5398 ata_via_chipinit(device_t dev) 5399 { 5400 struct ata_pci_controller *ctlr = device_get_softc(dev); 5401 5402 if (ata_setup_interrupt(dev)) 5403 return ENXIO; 5404 5405 if (ctlr->chip->max_dma >= ATA_SA150) { 5406 /* do we have AHCI capability ? */ 5407 if ((ctlr->chip->cfg2 == VIAAHCI) && ata_ahci_chipinit(dev) != ENXIO) 5408 return 0; 5409 5410 ctlr->r_type2 = SYS_RES_IOPORT; 5411 ctlr->r_rid2 = PCIR_BAR(5); 5412 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5413 &ctlr->r_rid2, RF_ACTIVE))) { 5414 ctlr->allocate = ata_via_allocate; 5415 ctlr->reset = ata_via_reset; 5416 5417 /* enable PCI interrupt */ 5418 pci_write_config(dev, PCIR_COMMAND, 5419 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5420 } 5421 5422 if (ctlr->chip->cfg2 & VIABAR) { 5423 ctlr->channels = 3; 5424 ctlr->setmode = ata_via_setmode; 5425 } 5426 else 5427 ctlr->setmode = ata_sata_setmode; 5428 return 0; 5429 } 5430 5431 /* prepare for ATA-66 on the 82C686a and 82C596b */ 5432 if (ctlr->chip->cfg2 & VIACLK) 5433 pci_write_config(dev, 0x50, 0x030b030b, 4); 5434 5435 /* the southbridge might need the data corruption fix */ 5436 if (ctlr->chip->cfg2 & VIABUG) 5437 ata_via_southbridge_fixup(dev); 5438 5439 /* set fifo configuration half'n'half */ 5440 pci_write_config(dev, 0x43, 5441 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 5442 5443 /* set status register read retry */ 5444 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 5445 5446 /* set DMA read & end-of-sector fifo flush */ 5447 pci_write_config(dev, 0x46, 5448 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 5449 5450 /* set sector size */ 5451 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 5452 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 5453 5454 ctlr->setmode = ata_via_family_setmode; 5455 return 0; 5456 } 5457 5458 static int 5459 ata_via_allocate(device_t dev) 5460 { 5461 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5462 struct ata_channel *ch = device_get_softc(dev); 5463 5464 /* newer SATA chips has resources in one BAR for each channel */ 5465 if (ctlr->chip->cfg2 & VIABAR) { 5466 struct resource *r_io; 5467 int i, rid; 5468 5469 rid = PCIR_BAR(ch->unit); 5470 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 5471 SYS_RES_IOPORT, 5472 &rid, RF_ACTIVE))) 5473 return ENXIO; 5474 5475 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 5476 ch->r_io[i].res = r_io; 5477 ch->r_io[i].offset = i; 5478 } 5479 ch->r_io[ATA_CONTROL].res = r_io; 5480 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 5481 ch->r_io[ATA_IDX_ADDR].res = r_io; 5482 ata_default_registers(dev); 5483 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 5484 ch->r_io[i].res = ctlr->r_res1; 5485 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 5486 } 5487 ata_pci_hw(dev); 5488 if (ch->unit >= 2) 5489 return 0; 5490 } 5491 else { 5492 /* setup the usual register normal pci style */ 5493 if (ata_pci_allocate(dev)) 5494 return ENXIO; 5495 } 5496 5497 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5498 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 5499 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5500 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 5501 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5502 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 5503 ch->flags |= ATA_NO_SLAVE; 5504 5505 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */ 5506 /* XXX SOS unknown how to enable PHY state change interrupt */ 5507 return 0; 5508 } 5509 5510 static void 5511 ata_via_reset(device_t dev) 5512 { 5513 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5514 struct ata_channel *ch = device_get_softc(dev); 5515 5516 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 5517 ata_generic_reset(dev); 5518 else 5519 if (ata_sata_phy_reset(dev)) 5520 ata_generic_reset(dev); 5521 } 5522 5523 static void 5524 ata_via_setmode(device_t dev, int mode) 5525 { 5526 device_t gparent = GRANDPARENT(dev); 5527 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5528 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5529 struct ata_device *atadev = device_get_softc(dev); 5530 int error; 5531 5532 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 5533 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20, 5534 0x65, 0x32, 0x20, 5535 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5536 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 5537 5538 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6)); 5539 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5540 if (bootverbose) 5541 device_printf(dev, "%ssetting %s on %s chip\n", 5542 (error) ? "FAILURE " : "", ata_mode2str(mode), 5543 ctlr->chip->text); 5544 if (!error) { 5545 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1); 5546 if (mode >= ATA_UDMA0) 5547 pci_write_config(gparent, 0xb3, 5548 dma_timings[mode & ATA_MODE_MASK], 1); 5549 atadev->mode = mode; 5550 } 5551 } 5552 else 5553 ata_sata_setmode(dev, mode); 5554 } 5555 5556 static void 5557 ata_via_southbridge_fixup(device_t dev) 5558 { 5559 device_t *children; 5560 int nchildren, i; 5561 5562 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5563 return; 5564 5565 for (i = 0; i < nchildren; i++) { 5566 if (pci_get_devid(children[i]) == ATA_VIA8363 || 5567 pci_get_devid(children[i]) == ATA_VIA8371 || 5568 pci_get_devid(children[i]) == ATA_VIA8662 || 5569 pci_get_devid(children[i]) == ATA_VIA8361) { 5570 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 5571 5572 if ((reg76 & 0xf0) != 0xd0) { 5573 device_printf(dev, 5574 "Correcting VIA config for southbridge data corruption bug\n"); 5575 pci_write_config(children[i], 0x75, 0x80, 1); 5576 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 5577 } 5578 break; 5579 } 5580 } 5581 kfree(children, M_TEMP); 5582 } 5583 5584 5585 /* common code for VIA, AMD & nVidia */ 5586 static void 5587 ata_via_family_setmode(device_t dev, int mode) 5588 { 5589 device_t gparent = GRANDPARENT(dev); 5590 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5591 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5592 struct ata_device *atadev = device_get_softc(dev); 5593 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20, 5594 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5595 int modes[][7] = { 5596 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 5597 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 5598 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 5599 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */ 5600 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */ 5601 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5602 int reg = 0x53 - devno; 5603 int error; 5604 5605 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5606 5607 if (ctlr->chip->cfg2 & AMDCABLE) { 5608 if (mode > ATA_UDMA2 && 5609 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) { 5610 ata_print_cable(dev, "controller"); 5611 mode = ATA_UDMA2; 5612 } 5613 } 5614 else 5615 mode = ata_check_80pin(dev, mode); 5616 5617 if (ctlr->chip->cfg2 & NVIDIA) 5618 reg += 0x10; 5619 5620 if (ctlr->chip->cfg1 != VIA133) 5621 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1); 5622 5623 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5624 5625 if (bootverbose) 5626 device_printf(dev, "%ssetting %s on %s chip\n", 5627 (error) ? "FAILURE " : "", ata_mode2str(mode), 5628 ctlr->chip->text); 5629 if (!error) { 5630 if (mode >= ATA_UDMA0) 5631 pci_write_config(gparent, reg, 5632 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 5633 else 5634 pci_write_config(gparent, reg, 0x8b, 1); 5635 atadev->mode = mode; 5636 } 5637 } 5638 5639 5640 /* misc functions */ 5641 static struct ata_chip_id * 5642 ata_match_chip(device_t dev, struct ata_chip_id *index) 5643 { 5644 while (index->chipid != 0) { 5645 if (pci_get_devid(dev) == index->chipid && 5646 pci_get_revid(dev) >= index->chiprev) 5647 return index; 5648 index++; 5649 } 5650 return NULL; 5651 } 5652 5653 static struct ata_chip_id * 5654 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot) 5655 { 5656 device_t *children; 5657 int nchildren, i; 5658 5659 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5660 return 0; 5661 5662 while (index->chipid != 0) { 5663 for (i = 0; i < nchildren; i++) { 5664 if (((slot >= 0 && pci_get_slot(children[i]) == slot) || 5665 (slot < 0 && pci_get_slot(children[i]) <= -slot)) && 5666 pci_get_devid(children[i]) == index->chipid && 5667 pci_get_revid(children[i]) >= index->chiprev) { 5668 kfree(children, M_TEMP); 5669 return index; 5670 } 5671 } 5672 index++; 5673 } 5674 kfree(children, M_TEMP); 5675 return NULL; 5676 } 5677 5678 static int 5679 ata_setup_interrupt(device_t dev) 5680 { 5681 struct ata_pci_controller *ctlr = device_get_softc(dev); 5682 int rid = ATA_IRQ_RID; 5683 5684 if (!ata_legacy(dev)) { 5685 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 5686 RF_SHAREABLE | RF_ACTIVE))) { 5687 device_printf(dev, "unable to map interrupt\n"); 5688 return ENXIO; 5689 } 5690 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 5691 ata_generic_intr, ctlr, &ctlr->handle, NULL))) { 5692 device_printf(dev, "unable to setup interrupt\n"); 5693 return ENXIO; 5694 } 5695 } 5696 return 0; 5697 } 5698 5699 struct ata_serialize { 5700 struct spinlock locked_mtx; 5701 int locked_ch; 5702 int restart_ch; 5703 }; 5704 5705 static int 5706 ata_serialize(device_t dev, int flags) 5707 { 5708 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5709 struct ata_channel *ch = device_get_softc(dev); 5710 struct ata_serialize *serial; 5711 static int inited = 0; 5712 int res; 5713 5714 if (!inited) { 5715 serial = kmalloc(sizeof(struct ata_serialize), 5716 M_TEMP, M_INTWAIT | M_ZERO); 5717 spin_init(&serial->locked_mtx); 5718 serial->locked_ch = -1; 5719 serial->restart_ch = -1; 5720 device_set_ivars(ctlr->dev, serial); 5721 inited = 1; 5722 } 5723 else 5724 serial = device_get_ivars(ctlr->dev); 5725 5726 spin_lock_wr(&serial->locked_mtx); 5727 switch (flags) { 5728 case ATA_LF_LOCK: 5729 if (serial->locked_ch == -1) 5730 serial->locked_ch = ch->unit; 5731 if (serial->locked_ch != ch->unit) 5732 serial->restart_ch = ch->unit; 5733 break; 5734 5735 case ATA_LF_UNLOCK: 5736 if (serial->locked_ch == ch->unit) { 5737 serial->locked_ch = -1; 5738 if (serial->restart_ch != -1) { 5739 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) { 5740 serial->restart_ch = -1; 5741 spin_unlock_wr(&serial->locked_mtx); 5742 ata_start(ch->dev); 5743 return -1; 5744 } 5745 } 5746 } 5747 break; 5748 5749 case ATA_LF_WHICH: 5750 break; 5751 } 5752 res = serial->locked_ch; 5753 spin_unlock_wr(&serial->locked_mtx); 5754 return res; 5755 } 5756 5757 static void 5758 ata_print_cable(device_t dev, u_int8_t *who) 5759 { 5760 device_printf(dev, 5761 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who); 5762 } 5763 5764 static int 5765 ata_atapi(device_t dev) 5766 { 5767 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5768 struct ata_device *atadev = device_get_softc(dev); 5769 5770 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || 5771 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE)); 5772 } 5773 5774 static int 5775 ata_check_80pin(device_t dev, int mode) 5776 { 5777 struct ata_device *atadev = device_get_softc(dev); 5778 5779 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) { 5780 ata_print_cable(dev, "device"); 5781 mode = ATA_UDMA2; 5782 } 5783 return mode; 5784 } 5785 5786 static int 5787 ata_mode2idx(int mode) 5788 { 5789 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) 5790 return (mode & ATA_MODE_MASK) + 8; 5791 if ((mode & ATA_DMA_MASK) == ATA_WDMA0) 5792 return (mode & ATA_MODE_MASK) + 5; 5793 return (mode & ATA_MODE_MASK) - ATA_PIO0; 5794 } 5795