1 /*- 2 * Copyright (c) 1998 - 2006 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.166 2006/07/24 10:44:50 sos Exp $ 27 * $DragonFly: src/sys/dev/disk/nata/ata-chipset.c,v 1.3 2006/12/22 23:26:16 swildner Exp $ 28 */ 29 30 #include "opt_ata.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/bus_dma.h> 35 #include <sys/bus_resource.h> 36 #include <sys/callout.h> 37 #include <sys/endian.h> 38 #include <sys/libkern.h> 39 #include <sys/lock.h> /* for {get,rel}_mplock() */ 40 #include <sys/malloc.h> 41 #include <sys/nata.h> 42 #include <sys/queue.h> 43 #include <sys/rman.h> 44 #include <sys/spinlock.h> 45 #include <sys/spinlock2.h> 46 #include <sys/systm.h> 47 #include <sys/taskqueue.h> 48 49 #include <machine/bus_dma.h> 50 51 #include <bus/pci/pcireg.h> 52 #include <bus/pci/pcivar.h> 53 54 #include "ata-all.h" 55 #include "ata-pci.h" 56 #include "ata_if.h" 57 58 /* local prototypes */ 59 /* ata-chipset.c */ 60 static int ata_generic_chipinit(device_t dev); 61 static void ata_generic_intr(void *data); 62 static int ata_generic_nulldeallocate(device_t dev); 63 static void ata_generic_setmode(device_t dev, int mode); 64 static void ata_sata_phy_enable(struct ata_channel *ch); 65 static void ata_sata_phy_event(void *context, int dummy); 66 static int ata_sata_connect(struct ata_channel *ch); 67 static void ata_sata_setmode(device_t dev, int mode); 68 static int ata_ahci_chipinit(device_t dev); 69 static int ata_ahci_allocate(device_t dev); 70 static int ata_ahci_status(device_t dev); 71 static int ata_ahci_begin_transaction(struct ata_request *request); 72 static int ata_ahci_end_transaction(struct ata_request *request); 73 static void ata_ahci_reset(device_t dev); 74 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 75 static void ata_ahci_dmainit(device_t dev); 76 static int ata_ahci_setup_fis(u_int8_t *fis, struct ata_request *request); 77 static int ata_acard_chipinit(device_t dev); 78 static int ata_acard_allocate(device_t dev); 79 static int ata_acard_status(device_t dev); 80 static void ata_acard_850_setmode(device_t dev, int mode); 81 static void ata_acard_86X_setmode(device_t dev, int mode); 82 static int ata_ali_chipinit(device_t dev); 83 static int ata_ali_allocate(device_t dev); 84 static int ata_ali_sata_allocate(device_t dev); 85 static int ata_ali_sata_deallocate(device_t dev); 86 static void ata_ali_reset(device_t dev); 87 static void ata_ali_setmode(device_t dev, int mode); 88 static int ata_amd_chipinit(device_t dev); 89 static int ata_ati_chipinit(device_t dev); 90 static void ata_ati_setmode(device_t dev, int mode); 91 static int ata_cyrix_chipinit(device_t dev); 92 static void ata_cyrix_setmode(device_t dev, int mode); 93 static int ata_cypress_chipinit(device_t dev); 94 static void ata_cypress_setmode(device_t dev, int mode); 95 static int ata_highpoint_chipinit(device_t dev); 96 static int ata_highpoint_allocate(device_t dev); 97 static void ata_highpoint_setmode(device_t dev, int mode); 98 static int ata_highpoint_check_80pin(device_t dev, int mode); 99 static int ata_intel_chipinit(device_t dev); 100 static int ata_intel_allocate(device_t dev); 101 static void ata_intel_reset(device_t dev); 102 static void ata_intel_old_setmode(device_t dev, int mode); 103 static void ata_intel_new_setmode(device_t dev, int mode); 104 static int ata_intel_31244_allocate(device_t dev); 105 static int ata_intel_31244_status(device_t dev); 106 static int ata_intel_31244_command(struct ata_request *request); 107 static void ata_intel_31244_reset(device_t dev); 108 static int ata_ite_chipinit(device_t dev); 109 static void ata_ite_setmode(device_t dev, int mode); 110 static int ata_jmicron_chipinit(device_t dev); 111 static int ata_jmicron_allocate(device_t dev); 112 static int ata_jmicron_deallocate(device_t dev); 113 static void ata_jmicron_reset(device_t dev); 114 static void ata_jmicron_dmainit(device_t dev); 115 static void ata_jmicron_setmode(device_t dev, int mode); 116 static int ata_marvell_chipinit(device_t dev); 117 static int ata_marvell_allocate(device_t dev); 118 static int ata_marvell_status(device_t dev); 119 static int ata_marvell_begin_transaction(struct ata_request *request); 120 static int ata_marvell_end_transaction(struct ata_request *request); 121 static void ata_marvell_reset(device_t dev); 122 static void ata_marvell_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 123 static void ata_marvell_dmainit(device_t dev); 124 static int ata_national_chipinit(device_t dev); 125 static void ata_national_setmode(device_t dev, int mode); 126 static int ata_nvidia_chipinit(device_t dev); 127 static int ata_nvidia_allocate(device_t dev); 128 static int ata_nvidia_status(device_t dev); 129 static void ata_nvidia_reset(device_t dev); 130 static int ata_promise_chipinit(device_t dev); 131 static int ata_promise_allocate(device_t dev); 132 static int ata_promise_status(device_t dev); 133 static int ata_promise_dmastart(device_t dev); 134 static int ata_promise_dmastop(device_t dev); 135 static void ata_promise_dmareset(device_t dev); 136 static void ata_promise_dmainit(device_t dev); 137 static void ata_promise_setmode(device_t dev, int mode); 138 static int ata_promise_tx2_allocate(device_t dev); 139 static int ata_promise_tx2_status(device_t dev); 140 static int ata_promise_mio_allocate(device_t dev); 141 static void ata_promise_mio_intr(void *data); 142 static int ata_promise_mio_status(device_t dev); 143 static int ata_promise_mio_command(struct ata_request *request); 144 static void ata_promise_mio_reset(device_t dev); 145 static void ata_promise_mio_dmainit(device_t dev); 146 static void ata_promise_mio_setmode(device_t dev, int mode); 147 static void ata_promise_sx4_intr(void *data); 148 static int ata_promise_sx4_command(struct ata_request *request); 149 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 150 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 151 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 152 static int ata_serverworks_chipinit(device_t dev); 153 static int ata_serverworks_allocate(device_t dev); 154 static void ata_serverworks_setmode(device_t dev, int mode); 155 static int ata_sii_chipinit(device_t dev); 156 static int ata_cmd_allocate(device_t dev); 157 static int ata_cmd_status(device_t dev); 158 static void ata_cmd_setmode(device_t dev, int mode); 159 static int ata_sii_allocate(device_t dev); 160 static int ata_sii_status(device_t dev); 161 static void ata_sii_reset(device_t dev); 162 static void ata_sii_setmode(device_t dev, int mode); 163 static int ata_sis_chipinit(device_t dev); 164 static int ata_sis_allocate(device_t dev); 165 static void ata_sis_reset(device_t dev); 166 static void ata_sis_setmode(device_t dev, int mode); 167 static int ata_via_chipinit(device_t dev); 168 static int ata_via_allocate(device_t dev); 169 static int ata_via_deallocate(device_t dev); 170 static void ata_via_reset(device_t dev); 171 static void ata_via_southbridge_fixup(device_t dev); 172 static void ata_via_family_setmode(device_t dev, int mode); 173 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index); 174 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot); 175 static int ata_setup_interrupt(device_t dev); 176 static int ata_serialize(device_t dev, int flags); 177 static void ata_print_cable(device_t dev, u_int8_t *who); 178 static int ata_atapi(device_t dev); 179 static int ata_check_80pin(device_t dev, int mode); 180 static int ata_mode2idx(int mode); 181 182 183 /* 184 * generic ATA support functions 185 */ 186 int 187 ata_generic_ident(device_t dev) 188 { 189 struct ata_pci_controller *ctlr = device_get_softc(dev); 190 191 device_set_desc(dev, "GENERIC ATA controller"); 192 ctlr->chipinit = ata_generic_chipinit; 193 return 0; 194 } 195 196 static int 197 ata_generic_chipinit(device_t dev) 198 { 199 struct ata_pci_controller *ctlr = device_get_softc(dev); 200 201 if (ata_setup_interrupt(dev)) 202 return ENXIO; 203 ctlr->setmode = ata_generic_setmode; 204 return 0; 205 } 206 207 static void 208 ata_generic_intr(void *data) 209 { 210 struct ata_pci_controller *ctlr = data; 211 struct ata_channel *ch; 212 int unit; 213 214 for (unit = 0; unit < ctlr->channels; unit++) { 215 if ((ch = ctlr->interrupt[unit].argument)) 216 ctlr->interrupt[unit].function(ch); 217 } 218 } 219 220 /* 221 * Generic deallocate function which does nothing. 222 */ 223 static int 224 ata_generic_nulldeallocate(device_t dev) 225 { 226 return 0; 227 } 228 229 static void 230 ata_generic_setmode(device_t dev, int mode) 231 { 232 struct ata_device *atadev = device_get_softc(dev); 233 234 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 235 mode = ata_check_80pin(dev, mode); 236 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 237 atadev->mode = mode; 238 } 239 240 241 /* 242 * SATA support functions 243 */ 244 static void 245 ata_sata_phy_enable(struct ata_channel *ch) 246 { 247 int loop, retry; 248 249 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) { 250 ata_sata_connect(ch); 251 return; 252 } 253 254 for (retry = 0; retry < 10; retry++) { 255 for (loop = 0; loop < 10; loop++) { 256 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET); 257 ata_udelay(100); 258 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & 259 ATA_SC_DET_MASK) == ATA_SC_DET_RESET) 260 break; 261 } 262 ata_udelay(5000); 263 for (loop = 0; loop < 10; loop++) { 264 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE | 265 ATA_SC_IPM_DIS_PARTIAL | 266 ATA_SC_IPM_DIS_SLUMBER); 267 ata_udelay(100); 268 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0) { 269 ata_sata_connect(ch); 270 return; 271 } 272 } 273 } 274 } 275 276 static void 277 ata_sata_phy_event(void *context, int dummy) 278 { 279 struct ata_connect_task *tp = (struct ata_connect_task *)context; 280 struct ata_channel *ch = device_get_softc(tp->dev); 281 device_t *children; 282 int nchildren, i; 283 284 get_mplock(); 285 if (tp->action == ATA_C_ATTACH) { 286 if (bootverbose) 287 device_printf(tp->dev, "CONNECTED\n"); 288 ata_sata_connect(ch); 289 ata_identify(tp->dev); 290 } 291 if (tp->action == ATA_C_DETACH) { 292 if (!device_get_children(tp->dev, &children, &nchildren)) { 293 for (i = 0; i < nchildren; i++) 294 if (children[i]) 295 device_delete_child(tp->dev, children[i]); 296 kfree(children, M_TEMP); 297 } 298 spin_lock_wr(&ch->state_mtx); 299 ch->state = ATA_IDLE; 300 spin_unlock_wr(&ch->state_mtx); 301 if (bootverbose) 302 device_printf(tp->dev, "DISCONNECTED\n"); 303 } 304 rel_mplock(); 305 kfree(tp, M_ATA); 306 } 307 308 static int 309 ata_sata_connect(struct ata_channel *ch) 310 { 311 u_int32_t status; 312 int timeout; 313 314 /* wait up to 1 second for "connect well" */ 315 for (timeout = 0; timeout < 100 ; timeout++) { 316 status = ATA_IDX_INL(ch, ATA_SSTATUS); 317 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 || 318 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2) 319 break; 320 ata_udelay(10000); 321 } 322 if (timeout >= 100) { 323 if (bootverbose) 324 device_printf(ch->dev, "SATA connect status=%08x\n", status); 325 return 0; 326 } 327 328 /* clear SATA error register */ 329 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 330 331 /* find out what type device we got poll for spec'd 31 seconds */ 332 /* XXX SOS 10 secs for now as I have little patience */ 333 ch->devices = 0; 334 for (timeout = 0; timeout < 1000; timeout++) { 335 if (ATA_IDX_INB(ch, ATA_STATUS) & ATA_S_BUSY) 336 DELAY(10000); 337 else 338 break; 339 } 340 if (bootverbose) 341 device_printf(ch->dev, "SATA connect ready time=%dms\n", timeout * 10); 342 if (timeout < 1000) { 343 if ((ATA_IDX_INB(ch, ATA_CYL_LSB) == ATAPI_MAGIC_LSB) && 344 (ATA_IDX_INB(ch, ATA_CYL_MSB) == ATAPI_MAGIC_MSB)) 345 ch->devices = ATA_ATAPI_MASTER; 346 else 347 ch->devices = ATA_ATA_MASTER; 348 } 349 if (bootverbose) 350 device_printf(ch->dev, "sata_connect devices=0x%b\n", 351 ch->devices, "\20\3ATAPI_MASTER\1ATA_MASTER"); 352 return 1; 353 } 354 355 static void 356 ata_sata_setmode(device_t dev, int mode) 357 { 358 struct ata_device *atadev = device_get_softc(dev); 359 360 /* 361 * if we detect that the device isn't a real SATA device we limit 362 * the transfer mode to UDMA5/ATA100. 363 * this works around the problems some devices has with the 364 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133. 365 */ 366 if (atadev->param.satacapabilities != 0x0000 && 367 atadev->param.satacapabilities != 0xffff) { 368 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 369 370 /* on some drives we need to set the transfer mode */ 371 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 372 ata_limit_mode(dev, mode, ATA_UDMA6)); 373 374 /* query SATA STATUS for the speed */ 375 if (ch->r_io[ATA_SSTATUS].res && 376 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) == 377 ATA_SS_CONWELL_GEN2)) 378 atadev->mode = ATA_SA300; 379 else 380 atadev->mode = ATA_SA150; 381 } 382 else { 383 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 384 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 385 atadev->mode = mode; 386 } 387 } 388 389 390 /* 391 * AHCI v1.0 compliant SATA chipset support functions 392 */ 393 struct ata_ahci_dma_prd { 394 u_int64_t dba; 395 u_int32_t reserved; 396 u_int32_t dbc; /* 0 based */ 397 #define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */ 398 #define ATA_AHCI_PRD_IPC (1<<31) 399 } __packed; 400 401 struct ata_ahci_cmd_tab { 402 u_int8_t cfis[64]; 403 u_int8_t acmd[32]; 404 u_int8_t reserved[32]; 405 struct ata_ahci_dma_prd prd_tab[16]; 406 } __packed; 407 408 struct ata_ahci_cmd_list { 409 u_int16_t cmd_flags; 410 u_int16_t prd_length; /* PRD entries */ 411 u_int32_t bytecount; 412 u_int64_t cmd_table_phys; /* 128byte aligned */ 413 } __packed; 414 415 416 static int 417 ata_ahci_chipinit(device_t dev) 418 { 419 struct ata_pci_controller *ctlr = device_get_softc(dev); 420 u_int32_t version; 421 422 /* reset AHCI controller */ 423 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 424 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_HR); 425 DELAY(1000000); 426 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) { 427 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 428 device_printf(dev, "AHCI controller reset failure\n"); 429 return ENXIO; 430 } 431 432 /* enable AHCI mode */ 433 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 434 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_AE); 435 436 /* get the number of HW channels */ 437 ctlr->channels = (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK)+1; 438 439 /* clear interrupts */ 440 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS)); 441 442 /* enable AHCI interrupts */ 443 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 444 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE); 445 446 ctlr->reset = ata_ahci_reset; 447 ctlr->dmainit = ata_ahci_dmainit; 448 ctlr->allocate = ata_ahci_allocate; 449 ctlr->deallocate = ata_generic_nulldeallocate; 450 ctlr->setmode = ata_sata_setmode; 451 452 /* enable PCI interrupt */ 453 pci_write_config(dev, PCIR_COMMAND, 454 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 455 456 /* announce we support the HW */ 457 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS); 458 device_printf(dev, 459 "AHCI Version %x%x.%x%x controller with %d ports detected\n", 460 (version >> 24) & 0xff, (version >> 16) & 0xff, 461 (version >> 8) & 0xff, version & 0xff, ctlr->channels); 462 return 0; 463 } 464 465 static int 466 ata_ahci_allocate(device_t dev) 467 { 468 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 469 struct ata_channel *ch = device_get_softc(dev); 470 int offset = (ch->unit << 7); 471 472 /* setup legacy cruft we need */ 473 ch->r_io[ATA_CYL_LSB].res = ctlr->r_res2; 474 ch->r_io[ATA_CYL_LSB].offset = ATA_AHCI_P_SIG + 1 + offset; 475 ch->r_io[ATA_CYL_MSB].res = ctlr->r_res2; 476 ch->r_io[ATA_CYL_MSB].offset = ATA_AHCI_P_SIG + 3 + offset; 477 ch->r_io[ATA_STATUS].res = ctlr->r_res2; 478 ch->r_io[ATA_STATUS].offset = ATA_AHCI_P_TFD + offset; 479 ch->r_io[ATA_ALTSTAT].res = ctlr->r_res2; 480 ch->r_io[ATA_ALTSTAT].offset = ATA_AHCI_P_TFD + offset; 481 482 /* set the SATA resources */ 483 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 484 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset; 485 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 486 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset; 487 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 488 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset; 489 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 490 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset; 491 492 ch->hw.status = ata_ahci_status; 493 ch->hw.begin_transaction = ata_ahci_begin_transaction; 494 ch->hw.end_transaction = ata_ahci_end_transaction; 495 ch->hw.command = NULL; /* not used here */ 496 497 /* setup the work areas */ 498 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, 499 ch->dma->work_bus + ATA_AHCI_CL_OFFSET); 500 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, 0x00000000); 501 502 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, 503 ch->dma->work_bus + ATA_AHCI_FB_OFFSET); 504 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, 0x00000000); 505 506 /* enable wanted port interrupts */ 507 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 508 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF | 509 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF | 510 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP | 511 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS | 512 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR)); 513 514 /* start operations on this channel */ 515 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 516 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 517 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 518 return 0; 519 } 520 521 static int 522 ata_ahci_status(device_t dev) 523 { 524 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 525 struct ata_channel *ch = device_get_softc(dev); 526 struct ata_connect_task *tp; 527 u_int32_t action, istatus, sstatus, error, issued; 528 int offset = (ch->unit << 7); 529 int tag = 0; 530 531 action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS); 532 if (action & (1 << ch->unit)) { 533 istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset); 534 issued = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset); 535 sstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SSTS + offset); 536 error = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SERR + offset); 537 538 /* clear interrupt(s) */ 539 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action); 540 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus); 541 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_SERR + offset, error); 542 543 /* do we have cold connect surprise */ 544 if (istatus & ATA_AHCI_P_IX_CPD) { 545 kprintf("ata_ahci_status status=%08x sstatus=%08x error=%08x\n", 546 istatus, sstatus, error); 547 } 548 549 /* check for and handle connect events */ 550 if ((istatus & ATA_AHCI_P_IX_PC) && 551 (tp = (struct ata_connect_task *) 552 kmalloc(sizeof(struct ata_connect_task), 553 M_ATA, M_NOWAIT | M_ZERO))) { 554 555 if (bootverbose) 556 device_printf(ch->dev, "CONNECT requested\n"); 557 tp->action = ATA_C_ATTACH; 558 tp->dev = ch->dev; 559 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 560 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 561 } 562 563 /* check for and handle disconnect events */ 564 else if ((istatus & ATA_AHCI_P_IX_PRC) && 565 !((sstatus & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 || 566 (sstatus & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2) && 567 (tp = (struct ata_connect_task *) 568 kmalloc(sizeof(struct ata_connect_task), 569 M_ATA, M_NOWAIT | M_ZERO))) { 570 571 if (bootverbose) 572 device_printf(ch->dev, "DISCONNECT requested\n"); 573 tp->action = ATA_C_DETACH; 574 tp->dev = ch->dev; 575 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 576 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 577 } 578 579 /* do we have any device action ? */ 580 if (!(issued & (1 << tag))) 581 return 1; 582 } 583 return 0; 584 } 585 586 /* must be called with ATA channel locked and state_mtx held */ 587 static int 588 ata_ahci_begin_transaction(struct ata_request *request) 589 { 590 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 591 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 592 struct ata_ahci_cmd_tab *ctp; 593 struct ata_ahci_cmd_list *clp; 594 int tag = 0, entries = 0; 595 int fis_size; 596 597 /* get a piece of the workspace for this request */ 598 ctp = (struct ata_ahci_cmd_tab *) 599 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag)); 600 601 /* setup the FIS for this request */ /* XXX SOS ATAPI missing still */ 602 if (!(fis_size = ata_ahci_setup_fis(&ctp->cfis[0], request))) { 603 device_printf(request->dev, "setting up SATA FIS failed\n"); 604 request->result = EIO; 605 return ATA_OP_FINISHED; 606 } 607 608 /* if request moves data setup and load SG list */ 609 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 610 if (ch->dma->load(ch->dev, request->data, request->bytecount, 611 request->flags & ATA_R_READ, 612 ctp->prd_tab, &entries)) { 613 device_printf(request->dev, "setting up DMA failed\n"); 614 request->result = EIO; 615 return ATA_OP_FINISHED; 616 } 617 } 618 619 /* setup the command list entry */ 620 clp = (struct ata_ahci_cmd_list *) 621 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 622 623 clp->prd_length = entries; 624 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) | 625 (request->flags & ATA_R_ATAPI ? (1<<5) : 0) | 626 (fis_size / sizeof(u_int32_t)); 627 clp->bytecount = 0; 628 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET + 629 (ATA_AHCI_CT_SIZE * tag)); 630 631 /* clear eventual ACTIVE bit */ 632 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag)); 633 634 /* issue the command */ 635 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + (ch->unit << 7), (1 << tag)); 636 637 /* start the timeout */ 638 callout_reset(&request->callout, request->timeout * hz, 639 (timeout_t*)ata_timeout, request); 640 return ATA_OP_CONTINUES; 641 } 642 643 /* must be called with ATA channel locked and state_mtx held */ 644 static int 645 ata_ahci_end_transaction(struct ata_request *request) 646 { 647 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 648 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 649 struct ata_ahci_cmd_list *clp; 650 u_int32_t tf_data; 651 int tag = 0; 652 653 /* kill the timeout */ 654 callout_stop(&request->callout); 655 656 /* get status */ 657 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit << 7)); 658 request->status = tf_data; 659 660 /* if error status get details */ 661 if (request->status & ATA_S_ERROR) 662 request->error = tf_data >> 8; 663 664 /* record how much data we actually moved */ 665 clp = (struct ata_ahci_cmd_list *) 666 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 667 request->donecount = clp->bytecount; 668 669 /* release SG list etc */ 670 ch->dma->unload(ch->dev); 671 672 return ATA_OP_FINISHED; 673 } 674 675 static void 676 ata_ahci_reset(device_t dev) 677 { 678 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 679 struct ata_channel *ch = device_get_softc(dev); 680 u_int32_t cmd; 681 int timeout, offset = (ch->unit << 7); 682 683 /* kill off all activity on this channel */ 684 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 685 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 686 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 687 688 /* XXX SOS this is not entirely wrong */ 689 timeout = 0; 690 do { 691 DELAY(1000); 692 if (timeout++ > 500) 693 device_printf(dev, "stopping AHCI engine failed\n"); 694 break; 695 } 696 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 697 698 /* issue Command List Override if supported */ 699 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) { 700 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 701 cmd |= ATA_AHCI_P_CMD_CLO; 702 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd); 703 timeout = 0; 704 do { 705 DELAY(1000); 706 if (timeout++ > 500) 707 device_printf(dev, "executing CLO failed\n"); 708 break; 709 } 710 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO); 711 } 712 713 /* spin up device */ 714 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, ATA_AHCI_P_CMD_SUD); 715 716 ata_sata_phy_enable(ch); 717 718 /* clear any interrupts pending on this channel */ 719 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, 720 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset)); 721 722 /* start operations on this channel */ 723 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 724 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 725 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 726 } 727 728 static void 729 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 730 { 731 struct ata_dmasetprd_args *args = xsc; 732 struct ata_ahci_dma_prd *prd = args->dmatab; 733 int i; 734 735 if (!(args->error = error)) { 736 for (i = 0; i < nsegs; i++) { 737 prd[i].dba = htole64(segs[i].ds_addr); 738 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK); 739 } 740 } 741 args->nsegs = nsegs; 742 } 743 744 static void 745 ata_ahci_dmainit(device_t dev) 746 { 747 struct ata_channel *ch = device_get_softc(dev); 748 749 ata_dmainit(dev); 750 if (ch->dma) { 751 /* note start and stop are not used here */ 752 ch->dma->setprd = ata_ahci_dmasetprd; 753 ch->dma->max_iosize = 8192 * DEV_BSIZE; 754 } 755 } 756 757 static int 758 ata_ahci_setup_fis(u_int8_t *fis, struct ata_request *request) 759 { 760 struct ata_device *atadev = device_get_softc(request->dev); 761 int idx = 0; 762 763 /* XXX SOS add ATAPI commands support later */ 764 ata_modify_if_48bit(request); 765 766 fis[idx++] = 0x27; /* host to device */ 767 fis[idx++] = 0x80; /* command FIS (note PM goes here) */ 768 fis[idx++] = request->u.ata.command; 769 fis[idx++] = request->u.ata.feature; 770 771 fis[idx++] = request->u.ata.lba; 772 fis[idx++] = request->u.ata.lba >> 8; 773 fis[idx++] = request->u.ata.lba >> 16; 774 fis[idx] = ATA_D_LBA | atadev->unit; 775 if (atadev->flags & ATA_D_48BIT_ACTIVE) 776 idx++; 777 else 778 fis[idx++] |= (request->u.ata.lba >> 24 & 0x0f); 779 780 fis[idx++] = request->u.ata.lba >> 24; 781 fis[idx++] = request->u.ata.lba >> 32; 782 fis[idx++] = request->u.ata.lba >> 40; 783 fis[idx++] = request->u.ata.feature >> 8; 784 785 fis[idx++] = request->u.ata.count; 786 fis[idx++] = request->u.ata.count >> 8; 787 fis[idx++] = 0x00; 788 fis[idx++] = ATA_A_4BIT; 789 790 fis[idx++] = 0x00; 791 fis[idx++] = 0x00; 792 fis[idx++] = 0x00; 793 fis[idx++] = 0x00; 794 return idx; 795 } 796 797 798 /* 799 * Acard chipset support functions 800 */ 801 int 802 ata_acard_ident(device_t dev) 803 { 804 struct ata_pci_controller *ctlr = device_get_softc(dev); 805 struct ata_chip_id *idx; 806 static struct ata_chip_id ids[] = 807 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" }, 808 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" }, 809 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" }, 810 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" }, 811 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" }, 812 { 0, 0, 0, 0, 0, 0}}; 813 char buffer[64]; 814 815 if (!(idx = ata_match_chip(dev, ids))) 816 return ENXIO; 817 818 ksprintf(buffer, "Acard %s %s controller", 819 idx->text, ata_mode2str(idx->max_dma)); 820 device_set_desc_copy(dev, buffer); 821 ctlr->chip = idx; 822 ctlr->chipinit = ata_acard_chipinit; 823 return 0; 824 } 825 826 static int 827 ata_acard_chipinit(device_t dev) 828 { 829 struct ata_pci_controller *ctlr = device_get_softc(dev); 830 831 if (ata_setup_interrupt(dev)) 832 return ENXIO; 833 834 ctlr->allocate = ata_acard_allocate; 835 if (ctlr->chip->cfg1 == ATPOLD) { 836 ctlr->setmode = ata_acard_850_setmode; 837 ctlr->locking = ata_serialize; 838 } 839 else 840 ctlr->setmode = ata_acard_86X_setmode; 841 return 0; 842 } 843 844 static int 845 ata_acard_allocate(device_t dev) 846 { 847 struct ata_channel *ch = device_get_softc(dev); 848 849 /* setup the usual register normal pci style */ 850 if (ata_pci_allocate(dev)) 851 return ENXIO; 852 853 ch->hw.status = ata_acard_status; 854 return 0; 855 } 856 857 static int 858 ata_acard_status(device_t dev) 859 { 860 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 861 struct ata_channel *ch = device_get_softc(dev); 862 863 if (ctlr->chip->cfg1 == ATPOLD && 864 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit) 865 return 0; 866 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) { 867 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 868 869 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != 870 ATA_BMSTAT_INTERRUPT) 871 return 0; 872 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR); 873 DELAY(1); 874 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 875 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 876 DELAY(1); 877 } 878 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 879 DELAY(100); 880 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 881 return 0; 882 } 883 return 1; 884 } 885 886 static void 887 ata_acard_850_setmode(device_t dev, int mode) 888 { 889 device_t gparent = GRANDPARENT(dev); 890 struct ata_pci_controller *ctlr = device_get_softc(gparent); 891 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 892 struct ata_device *atadev = device_get_softc(dev); 893 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 894 int error; 895 896 mode = ata_limit_mode(dev, mode, 897 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 898 899 /* XXX SOS missing WDMA0+1 + PIO modes */ 900 if (mode >= ATA_WDMA2) { 901 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 902 if (bootverbose) 903 device_printf(dev, "%ssetting %s on %s chip\n", 904 (error) ? "FAILURE " : "", 905 ata_mode2str(mode), ctlr->chip->text); 906 if (!error) { 907 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1); 908 909 reg54 &= ~(0x03 << (devno << 1)); 910 if (mode >= ATA_UDMA0) 911 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1)); 912 pci_write_config(gparent, 0x54, reg54, 1); 913 pci_write_config(gparent, 0x4a, 0xa6, 1); 914 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2); 915 atadev->mode = mode; 916 return; 917 } 918 } 919 /* we could set PIO mode timings, but we assume the BIOS did that */ 920 } 921 922 static void 923 ata_acard_86X_setmode(device_t dev, int mode) 924 { 925 device_t gparent = GRANDPARENT(dev); 926 struct ata_pci_controller *ctlr = device_get_softc(gparent); 927 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 928 struct ata_device *atadev = device_get_softc(dev); 929 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 930 int error; 931 932 933 mode = ata_limit_mode(dev, mode, 934 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 935 936 mode = ata_check_80pin(dev, mode); 937 938 /* XXX SOS missing WDMA0+1 + PIO modes */ 939 if (mode >= ATA_WDMA2) { 940 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 941 if (bootverbose) 942 device_printf(dev, "%ssetting %s on %s chip\n", 943 (error) ? "FAILURE " : "", 944 ata_mode2str(mode), ctlr->chip->text); 945 if (!error) { 946 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2); 947 948 reg44 &= ~(0x000f << (devno << 2)); 949 if (mode >= ATA_UDMA0) 950 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2)); 951 pci_write_config(gparent, 0x44, reg44, 2); 952 pci_write_config(gparent, 0x4a, 0xa6, 1); 953 pci_write_config(gparent, 0x40 + devno, 0x31, 1); 954 atadev->mode = mode; 955 return; 956 } 957 } 958 /* we could set PIO mode timings, but we assume the BIOS did that */ 959 } 960 961 962 /* 963 * Acer Labs Inc (ALI) chipset support functions 964 */ 965 int 966 ata_ali_ident(device_t dev) 967 { 968 struct ata_pci_controller *ctlr = device_get_softc(dev); 969 struct ata_chip_id *idx; 970 static struct ata_chip_id ids[] = 971 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" }, 972 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" }, 973 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" }, 974 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" }, 975 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" }, 976 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" }, 977 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" }, 978 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" }, 979 { 0, 0, 0, 0, 0, 0}}; 980 char buffer[64]; 981 982 if (!(idx = ata_match_chip(dev, ids))) 983 return ENXIO; 984 985 ksprintf(buffer, "AcerLabs %s %s controller", 986 idx->text, ata_mode2str(idx->max_dma)); 987 device_set_desc_copy(dev, buffer); 988 ctlr->chip = idx; 989 ctlr->chipinit = ata_ali_chipinit; 990 return 0; 991 } 992 993 static int 994 ata_ali_chipinit(device_t dev) 995 { 996 struct ata_pci_controller *ctlr = device_get_softc(dev); 997 998 if (ata_setup_interrupt(dev)) 999 return ENXIO; 1000 1001 switch (ctlr->chip->cfg2) { 1002 case ALISATA: 1003 ctlr->channels = ctlr->chip->cfg1; 1004 ctlr->allocate = ata_ali_sata_allocate; 1005 ctlr->deallocate = ata_ali_sata_deallocate; 1006 ctlr->setmode = ata_sata_setmode; 1007 1008 /* enable PCI interrupt */ 1009 pci_write_config(dev, PCIR_COMMAND, 1010 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1011 break; 1012 1013 case ALINEW: 1014 /* use device interrupt as byte count end */ 1015 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1); 1016 1017 /* enable cable detection and UDMA support on newer chips */ 1018 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1); 1019 1020 /* enable ATAPI UDMA mode */ 1021 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1); 1022 1023 /* only chips with revision > 0xc4 can do 48bit DMA */ 1024 if (ctlr->chip->chiprev <= 0xc4) 1025 device_printf(dev, 1026 "using PIO transfers above 137GB as workaround for " 1027 "48bit DMA access bug, expect reduced performance\n"); 1028 ctlr->allocate = ata_ali_allocate; 1029 ctlr->reset = ata_ali_reset; 1030 ctlr->setmode = ata_ali_setmode; 1031 break; 1032 1033 case ALIOLD: 1034 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */ 1035 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1); 1036 ctlr->setmode = ata_ali_setmode; 1037 break; 1038 } 1039 return 0; 1040 } 1041 1042 static int 1043 ata_ali_allocate(device_t dev) 1044 { 1045 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1046 struct ata_channel *ch = device_get_softc(dev); 1047 1048 /* setup the usual register normal pci style */ 1049 if (ata_pci_allocate(dev)) 1050 return ENXIO; 1051 1052 /* older chips can't do 48bit DMA transfers */ 1053 if (ctlr->chip->chiprev <= 0xc4) 1054 ch->flags |= ATA_NO_48BIT_DMA; 1055 1056 return 0; 1057 } 1058 1059 static int 1060 ata_ali_sata_allocate(device_t dev) 1061 { 1062 device_t parent = device_get_parent(dev); 1063 struct ata_pci_controller *ctlr = device_get_softc(parent); 1064 struct ata_channel *ch = device_get_softc(dev); 1065 struct resource *io = NULL, *ctlio = NULL; 1066 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 1067 int i, rid; 1068 1069 rid = PCIR_BAR(0) + (unit01 ? 8 : 0); 1070 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1071 if (!io) 1072 return ENXIO; 1073 1074 rid = PCIR_BAR(1) + (unit01 ? 8 : 0); 1075 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1076 if (!ctlio) { 1077 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io); 1078 return ENXIO; 1079 } 1080 1081 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 1082 ch->r_io[i].res = io; 1083 ch->r_io[i].offset = i + (unit10 ? 8 : 0); 1084 } 1085 ch->r_io[ATA_CONTROL].res = ctlio; 1086 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0); 1087 ch->r_io[ATA_IDX_ADDR].res = io; 1088 ata_default_registers(dev); 1089 if (ctlr->r_res1) { 1090 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 1091 ch->r_io[i].res = ctlr->r_res1; 1092 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 1093 } 1094 } 1095 ch->flags |= ATA_NO_SLAVE; 1096 1097 /* XXX SOS PHY handling awkward in ALI chip not supported yet */ 1098 ata_pci_hw(dev); 1099 return 0; 1100 } 1101 1102 /* 1103 * Deallocate ALi SATA resources on detach. 1104 */ 1105 static int 1106 ata_ali_sata_deallocate(device_t dev) 1107 { 1108 struct ata_channel *ch = device_get_softc(dev); 1109 int unit01 = (ch->unit & 1); 1110 1111 if (ch->r_io[ATA_CONTROL].res) 1112 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(1) + 1113 (unit01 ? 8 : 0), ch->r_io[ATA_CONTROL].res); 1114 if (ch->r_io[ATA_IDX_ADDR].res) 1115 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0) + 1116 (unit01 ? 8 : 0), ch->r_io[ATA_IDX_ADDR].res); 1117 1118 return 0; 1119 } 1120 1121 static void 1122 ata_ali_reset(device_t dev) 1123 { 1124 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1125 struct ata_channel *ch = device_get_softc(dev); 1126 device_t *children; 1127 int nchildren, i; 1128 1129 ata_generic_reset(dev); 1130 1131 /* 1132 * workaround for datacorruption bug found on at least SUN Blade-100 1133 * find the ISA function on the southbridge and disable then enable 1134 * the ATA channel tristate buffer 1135 */ 1136 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) { 1137 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) { 1138 for (i = 0; i < nchildren; i++) { 1139 if (pci_get_devid(children[i]) == ATA_ALI_1533) { 1140 pci_write_config(children[i], 0x58, 1141 pci_read_config(children[i], 0x58, 1) & 1142 ~(0x04 << ch->unit), 1); 1143 pci_write_config(children[i], 0x58, 1144 pci_read_config(children[i], 0x58, 1) | 1145 (0x04 << ch->unit), 1); 1146 break; 1147 } 1148 } 1149 kfree(children, M_TEMP); 1150 } 1151 } 1152 } 1153 1154 static void 1155 ata_ali_setmode(device_t dev, int mode) 1156 { 1157 device_t gparent = GRANDPARENT(dev); 1158 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1159 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1160 struct ata_device *atadev = device_get_softc(dev); 1161 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1162 int error; 1163 1164 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1165 1166 if (ctlr->chip->cfg2 & ALINEW) { 1167 if (mode > ATA_UDMA2 && 1168 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) { 1169 ata_print_cable(dev, "controller"); 1170 mode = ATA_UDMA2; 1171 } 1172 } 1173 else 1174 mode = ata_check_80pin(dev, mode); 1175 1176 if (ctlr->chip->cfg2 & ALIOLD) { 1177 /* doesn't support ATAPI DMA on write */ 1178 ch->flags |= ATA_ATAPI_DMA_RO; 1179 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) { 1180 /* doesn't support ATAPI DMA on two ATAPI devices */ 1181 device_printf(dev, "two atapi devices on this channel, no DMA\n"); 1182 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1183 } 1184 } 1185 1186 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1187 1188 if (bootverbose) 1189 device_printf(dev, "%ssetting %s on %s chip\n", 1190 (error) ? "FAILURE " : "", 1191 ata_mode2str(mode), ctlr->chip->text); 1192 if (!error) { 1193 if (mode >= ATA_UDMA0) { 1194 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d}; 1195 u_int32_t word54 = pci_read_config(gparent, 0x54, 4); 1196 1197 word54 &= ~(0x000f000f << (devno << 2)); 1198 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2)); 1199 pci_write_config(gparent, 0x54, word54, 4); 1200 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1201 0x00310001, 4); 1202 } 1203 else { 1204 u_int32_t piotimings[] = 1205 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001, 1206 0x00310001, 0x00440001, 0x00330001, 0x00310001}; 1207 1208 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) & 1209 ~(0x0008000f << (devno << 2)), 4); 1210 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1211 piotimings[ata_mode2idx(mode)], 4); 1212 } 1213 atadev->mode = mode; 1214 } 1215 } 1216 1217 1218 /* 1219 * American Micro Devices (AMD) chipset support functions 1220 */ 1221 int 1222 ata_amd_ident(device_t dev) 1223 { 1224 struct ata_pci_controller *ctlr = device_get_softc(dev); 1225 struct ata_chip_id *idx; 1226 static struct ata_chip_id ids[] = 1227 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" }, 1228 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" }, 1229 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" }, 1230 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" }, 1231 { 0, 0, 0, 0, 0, 0}}; 1232 char buffer[64]; 1233 1234 if (!(idx = ata_match_chip(dev, ids))) 1235 return ENXIO; 1236 1237 ksprintf(buffer, "AMD %s %s controller", 1238 idx->text, ata_mode2str(idx->max_dma)); 1239 device_set_desc_copy(dev, buffer); 1240 ctlr->chip = idx; 1241 ctlr->chipinit = ata_amd_chipinit; 1242 return 0; 1243 } 1244 1245 static int 1246 ata_amd_chipinit(device_t dev) 1247 { 1248 struct ata_pci_controller *ctlr = device_get_softc(dev); 1249 1250 if (ata_setup_interrupt(dev)) 1251 return ENXIO; 1252 1253 /* disable/set prefetch, postwrite */ 1254 if (ctlr->chip->cfg2 & AMDBUG) 1255 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1); 1256 else 1257 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); 1258 1259 ctlr->setmode = ata_via_family_setmode; 1260 return 0; 1261 } 1262 1263 1264 /* 1265 * ATI chipset support functions 1266 */ 1267 int 1268 ata_ati_ident(device_t dev) 1269 { 1270 struct ata_pci_controller *ctlr = device_get_softc(dev); 1271 struct ata_chip_id *idx; 1272 static struct ata_chip_id ids[] = 1273 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" }, 1274 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" }, 1275 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" }, 1276 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" }, 1277 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1278 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1279 { 0, 0, 0, 0, 0, 0}}; 1280 char buffer[64]; 1281 1282 if (!(idx = ata_match_chip(dev, ids))) 1283 return ENXIO; 1284 1285 ksprintf(buffer, "ATI %s %s controller", 1286 idx->text, ata_mode2str(idx->max_dma)); 1287 device_set_desc_copy(dev, buffer); 1288 ctlr->chip = idx; 1289 1290 /* the ATI SATA controller is actually a SiI 3112 controller*/ 1291 if (ctlr->chip->cfg1 & SIIMEMIO) 1292 ctlr->chipinit = ata_sii_chipinit; 1293 else 1294 ctlr->chipinit = ata_ati_chipinit; 1295 return 0; 1296 } 1297 1298 static int 1299 ata_ati_chipinit(device_t dev) 1300 { 1301 struct ata_pci_controller *ctlr = device_get_softc(dev); 1302 1303 if (ata_setup_interrupt(dev)) 1304 return ENXIO; 1305 1306 ctlr->setmode = ata_ati_setmode; 1307 return 0; 1308 } 1309 1310 static void 1311 ata_ati_setmode(device_t dev, int mode) 1312 { 1313 device_t gparent = GRANDPARENT(dev); 1314 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1315 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1316 struct ata_device *atadev = device_get_softc(dev); 1317 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1318 int offset = (devno ^ 0x01) << 3; 1319 int error; 1320 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 1321 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 1322 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 1323 1324 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1325 1326 mode = ata_check_80pin(dev, mode); 1327 1328 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1329 1330 if (bootverbose) 1331 device_printf(dev, "%ssetting %s on %s chip\n", 1332 (error) ? "FAILURE " : "", 1333 ata_mode2str(mode), ctlr->chip->text); 1334 if (!error) { 1335 if (mode >= ATA_UDMA0) { 1336 pci_write_config(gparent, 0x56, 1337 (pci_read_config(gparent, 0x56, 2) & 1338 ~(0xf << (devno << 2))) | 1339 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 1340 pci_write_config(gparent, 0x54, 1341 pci_read_config(gparent, 0x54, 1) | 1342 (0x01 << devno), 1); 1343 pci_write_config(gparent, 0x44, 1344 (pci_read_config(gparent, 0x44, 4) & 1345 ~(0xff << offset)) | 1346 (dmatimings[2] << offset), 4); 1347 } 1348 else if (mode >= ATA_WDMA0) { 1349 pci_write_config(gparent, 0x54, 1350 pci_read_config(gparent, 0x54, 1) & 1351 ~(0x01 << devno), 1); 1352 pci_write_config(gparent, 0x44, 1353 (pci_read_config(gparent, 0x44, 4) & 1354 ~(0xff << offset)) | 1355 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 1356 } 1357 else 1358 pci_write_config(gparent, 0x54, 1359 pci_read_config(gparent, 0x54, 1) & 1360 ~(0x01 << devno), 1); 1361 1362 pci_write_config(gparent, 0x4a, 1363 (pci_read_config(gparent, 0x4a, 2) & 1364 ~(0xf << (devno << 2))) | 1365 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2); 1366 pci_write_config(gparent, 0x40, 1367 (pci_read_config(gparent, 0x40, 4) & 1368 ~(0xff << offset)) | 1369 (piotimings[ata_mode2idx(mode)] << offset), 4); 1370 atadev->mode = mode; 1371 } 1372 } 1373 1374 /* 1375 * Cyrix chipset support functions 1376 */ 1377 int 1378 ata_cyrix_ident(device_t dev) 1379 { 1380 struct ata_pci_controller *ctlr = device_get_softc(dev); 1381 1382 if (pci_get_devid(dev) == ATA_CYRIX_5530) { 1383 device_set_desc(dev, "Cyrix 5530 ATA33 controller"); 1384 ctlr->chipinit = ata_cyrix_chipinit; 1385 return 0; 1386 } 1387 return ENXIO; 1388 } 1389 1390 static int 1391 ata_cyrix_chipinit(device_t dev) 1392 { 1393 struct ata_pci_controller *ctlr = device_get_softc(dev); 1394 1395 if (ata_setup_interrupt(dev)) 1396 return ENXIO; 1397 1398 if (ctlr->r_res1) 1399 ctlr->setmode = ata_cyrix_setmode; 1400 else 1401 ctlr->setmode = ata_generic_setmode; 1402 return 0; 1403 } 1404 1405 static void 1406 ata_cyrix_setmode(device_t dev, int mode) 1407 { 1408 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1409 struct ata_device *atadev = device_get_softc(dev); 1410 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1411 u_int32_t piotiming[] = 1412 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 }; 1413 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 }; 1414 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 }; 1415 int error; 1416 1417 ch->dma->alignment = 16; 1418 ch->dma->max_iosize = 126 * DEV_BSIZE; 1419 1420 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 1421 1422 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1423 1424 if (bootverbose) 1425 device_printf(dev, "%ssetting %s on Cyrix chip\n", 1426 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1427 if (!error) { 1428 if (mode >= ATA_UDMA0) { 1429 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1430 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]); 1431 } 1432 else if (mode >= ATA_WDMA0) { 1433 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1434 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]); 1435 } 1436 else { 1437 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1438 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]); 1439 } 1440 atadev->mode = mode; 1441 } 1442 } 1443 1444 1445 /* 1446 * Cypress chipset support functions 1447 */ 1448 int 1449 ata_cypress_ident(device_t dev) 1450 { 1451 struct ata_pci_controller *ctlr = device_get_softc(dev); 1452 1453 /* 1454 * the Cypress chip is a mess, it contains two ATA functions, but 1455 * both channels are visible on the first one. 1456 * simply ignore the second function for now, as the right 1457 * solution (ignoring the second channel on the first function) 1458 * doesn't work with the crappy ATA interrupt setup on the alpha. 1459 */ 1460 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 && 1461 pci_get_function(dev) == 1 && 1462 pci_get_subclass(dev) == PCIS_STORAGE_IDE) { 1463 device_set_desc(dev, "Cypress 82C693 ATA controller"); 1464 ctlr->chipinit = ata_cypress_chipinit; 1465 return 0; 1466 } 1467 return ENXIO; 1468 } 1469 1470 static int 1471 ata_cypress_chipinit(device_t dev) 1472 { 1473 struct ata_pci_controller *ctlr = device_get_softc(dev); 1474 1475 if (ata_setup_interrupt(dev)) 1476 return ENXIO; 1477 1478 ctlr->setmode = ata_cypress_setmode; 1479 return 0; 1480 } 1481 1482 static void 1483 ata_cypress_setmode(device_t dev, int mode) 1484 { 1485 device_t gparent = GRANDPARENT(dev); 1486 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1487 struct ata_device *atadev = device_get_softc(dev); 1488 int error; 1489 1490 mode = ata_limit_mode(dev, mode, ATA_WDMA2); 1491 1492 /* XXX SOS missing WDMA0+1 + PIO modes */ 1493 if (mode == ATA_WDMA2) { 1494 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1495 if (bootverbose) 1496 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n", 1497 error ? "FAILURE " : ""); 1498 if (!error) { 1499 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2); 1500 atadev->mode = mode; 1501 return; 1502 } 1503 } 1504 /* we could set PIO mode timings, but we assume the BIOS did that */ 1505 } 1506 1507 1508 /* 1509 * HighPoint chipset support functions 1510 */ 1511 int 1512 ata_highpoint_ident(device_t dev) 1513 { 1514 struct ata_pci_controller *ctlr = device_get_softc(dev); 1515 struct ata_chip_id *idx; 1516 static struct ata_chip_id ids[] = 1517 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" }, 1518 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" }, 1519 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1520 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" }, 1521 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1522 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" }, 1523 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" }, 1524 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" }, 1525 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" }, 1526 { 0, 0, 0, 0, 0, 0}}; 1527 char buffer[64]; 1528 1529 if (!(idx = ata_match_chip(dev, ids))) 1530 return ENXIO; 1531 1532 strcpy(buffer, "HighPoint "); 1533 strcat(buffer, idx->text); 1534 if (idx->cfg1 == HPT374) { 1535 if (pci_get_function(dev) == 0) 1536 strcat(buffer, " (channel 0+1)"); 1537 if (pci_get_function(dev) == 1) 1538 strcat(buffer, " (channel 2+3)"); 1539 } 1540 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 1541 device_set_desc_copy(dev, buffer); 1542 ctlr->chip = idx; 1543 ctlr->chipinit = ata_highpoint_chipinit; 1544 return 0; 1545 } 1546 1547 static int 1548 ata_highpoint_chipinit(device_t dev) 1549 { 1550 struct ata_pci_controller *ctlr = device_get_softc(dev); 1551 1552 if (ata_setup_interrupt(dev)) 1553 return ENXIO; 1554 1555 if (ctlr->chip->cfg2 == HPTOLD) { 1556 /* disable interrupt prediction */ 1557 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 1558 } 1559 else { 1560 /* disable interrupt prediction */ 1561 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 1562 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 1563 1564 /* enable interrupts */ 1565 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 1566 1567 /* set clocks etc */ 1568 if (ctlr->chip->cfg1 < HPT372) 1569 pci_write_config(dev, 0x5b, 0x22, 1); 1570 else 1571 pci_write_config(dev, 0x5b, 1572 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 1573 } 1574 ctlr->allocate = ata_highpoint_allocate; 1575 ctlr->setmode = ata_highpoint_setmode; 1576 return 0; 1577 } 1578 1579 static int 1580 ata_highpoint_allocate(device_t dev) 1581 { 1582 struct ata_channel *ch = device_get_softc(dev); 1583 1584 /* setup the usual register normal pci style */ 1585 if (ata_pci_allocate(dev)) 1586 return ENXIO; 1587 1588 ch->flags |= ATA_ALWAYS_DMASTAT; 1589 return 0; 1590 } 1591 1592 static void 1593 ata_highpoint_setmode(device_t dev, int mode) 1594 { 1595 device_t gparent = GRANDPARENT(dev); 1596 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1597 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1598 struct ata_device *atadev = device_get_softc(dev); 1599 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1600 int error; 1601 u_int32_t timings33[][4] = { 1602 /* HPT366 HPT370 HPT372 HPT374 mode */ 1603 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */ 1604 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */ 1605 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */ 1606 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */ 1607 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */ 1608 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */ 1609 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */ 1610 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */ 1611 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */ 1612 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */ 1613 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */ 1614 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */ 1615 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */ 1616 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */ 1617 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */ 1618 }; 1619 1620 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1621 1622 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev)) 1623 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1624 1625 mode = ata_highpoint_check_80pin(dev, mode); 1626 1627 /* 1628 * most if not all HPT chips cant really handle that the device is 1629 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to 1630 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance 1631 */ 1632 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 1633 ata_limit_mode(dev, mode, ATA_UDMA5)); 1634 if (bootverbose) 1635 device_printf(dev, "%ssetting %s on HighPoint chip\n", 1636 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1637 if (!error) 1638 pci_write_config(gparent, 0x40 + (devno << 2), 1639 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 1640 atadev->mode = mode; 1641 } 1642 1643 static int 1644 ata_highpoint_check_80pin(device_t dev, int mode) 1645 { 1646 device_t gparent = GRANDPARENT(dev); 1647 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1648 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1649 u_int8_t reg, val, res; 1650 1651 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) { 1652 reg = ch->unit ? 0x57 : 0x53; 1653 val = pci_read_config(gparent, reg, 1); 1654 pci_write_config(gparent, reg, val | 0x80, 1); 1655 } 1656 else { 1657 reg = 0x5b; 1658 val = pci_read_config(gparent, reg, 1); 1659 pci_write_config(gparent, reg, val & 0xfe, 1); 1660 } 1661 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2); 1662 pci_write_config(gparent, reg, val, 1); 1663 1664 if (mode > ATA_UDMA2 && res) { 1665 ata_print_cable(dev, "controller"); 1666 mode = ATA_UDMA2; 1667 } 1668 return mode; 1669 } 1670 1671 1672 /* 1673 * Intel chipset support functions 1674 */ 1675 int 1676 ata_intel_ident(device_t dev) 1677 { 1678 struct ata_pci_controller *ctlr = device_get_softc(dev); 1679 struct ata_chip_id *idx; 1680 static struct ata_chip_id ids[] = 1681 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" }, 1682 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" }, 1683 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1684 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1685 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1686 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" }, 1687 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1688 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1689 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1690 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1691 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1692 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1693 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1694 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1695 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" }, 1696 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1697 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1698 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" }, 1699 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1700 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1701 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" }, 1702 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1703 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1704 { ATA_I82801FB_M, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1705 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" }, 1706 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1707 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1708 { ATA_I82801GB_M, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1709 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1710 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" }, 1711 { 0, 0, 0, 0, 0, 0}}; 1712 char buffer[64]; 1713 1714 if (!(idx = ata_match_chip(dev, ids))) 1715 return ENXIO; 1716 1717 ksprintf(buffer, "Intel %s %s controller", 1718 idx->text, ata_mode2str(idx->max_dma)); 1719 device_set_desc_copy(dev, buffer); 1720 ctlr->chip = idx; 1721 ctlr->chipinit = ata_intel_chipinit; 1722 return 0; 1723 } 1724 1725 static int 1726 ata_intel_chipinit(device_t dev) 1727 { 1728 struct ata_pci_controller *ctlr = device_get_softc(dev); 1729 1730 if (ata_setup_interrupt(dev)) 1731 return ENXIO; 1732 1733 /* good old PIIX needs special treatment (not implemented) */ 1734 if (ctlr->chip->chipid == ATA_I82371FB) { 1735 ctlr->setmode = ata_intel_old_setmode; 1736 } 1737 1738 /* the intel 31244 needs special care if in DPA mode */ 1739 else if (ctlr->chip->chipid == ATA_I31244) { 1740 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 1741 ctlr->r_type2 = SYS_RES_MEMORY; 1742 ctlr->r_rid2 = PCIR_BAR(0); 1743 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1744 &ctlr->r_rid2, 1745 RF_ACTIVE))) 1746 return ENXIO; 1747 ctlr->channels = 4; 1748 ctlr->allocate = ata_intel_31244_allocate; 1749 ctlr->deallocate = ata_generic_nulldeallocate; 1750 ctlr->reset = ata_intel_31244_reset; 1751 } 1752 ctlr->setmode = ata_sata_setmode; 1753 } 1754 1755 /* non SATA intel chips goes here */ 1756 else if (ctlr->chip->max_dma < ATA_SA150) { 1757 ctlr->allocate = ata_intel_allocate; 1758 ctlr->setmode = ata_intel_new_setmode; 1759 } 1760 1761 /* SATA parts can be either compat or AHCI */ 1762 else { 1763 /* force all ports active "the legacy way" */ 1764 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2); 1765 1766 ctlr->allocate = ata_intel_allocate; 1767 ctlr->reset = ata_intel_reset; 1768 1769 /* 1770 * if we have AHCI capability and BAR(5) as a memory resource 1771 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode 1772 */ 1773 if ((ctlr->chip->cfg1 == AHCI) && 1774 (pci_read_config(dev, 0x90, 1) & 0xc0)) { 1775 ctlr->r_type2 = SYS_RES_MEMORY; 1776 ctlr->r_rid2 = PCIR_BAR(5); 1777 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1778 &ctlr->r_rid2, 1779 RF_ACTIVE))) 1780 return ata_ahci_chipinit(dev); 1781 } 1782 ctlr->setmode = ata_sata_setmode; 1783 1784 /* enable PCI interrupt */ 1785 pci_write_config(dev, PCIR_COMMAND, 1786 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1787 } 1788 return 0; 1789 } 1790 1791 static int 1792 ata_intel_allocate(device_t dev) 1793 { 1794 struct ata_channel *ch = device_get_softc(dev); 1795 1796 /* setup the usual register normal pci style */ 1797 if (ata_pci_allocate(dev)) 1798 return ENXIO; 1799 1800 ch->flags |= ATA_ALWAYS_DMASTAT; 1801 return 0; 1802 } 1803 1804 static void 1805 ata_intel_reset(device_t dev) 1806 { 1807 device_t parent = device_get_parent(dev); 1808 struct ata_pci_controller *ctlr = device_get_softc(parent); 1809 struct ata_channel *ch = device_get_softc(dev); 1810 int mask, timeout; 1811 1812 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */ 1813 if (ctlr->chip->cfg1) { 1814 mask = (0x0005 << ch->unit); 1815 } 1816 else { 1817 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */ 1818 if (pci_read_config(parent, 0x90, 1) & 0x04) 1819 mask = 0x0003; 1820 else { 1821 mask = (0x0001 << ch->unit); 1822 /* XXX SOS should be in intel_allocate if we grow it */ 1823 ch->flags |= ATA_NO_SLAVE; 1824 } 1825 } 1826 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2); 1827 DELAY(10); 1828 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2); 1829 1830 /* wait up to 1 sec for "connect well" */ 1831 for (timeout = 0; timeout < 100 ; timeout++) { 1832 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) && 1833 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 1834 break; 1835 ata_udelay(10000); 1836 } 1837 ata_generic_reset(dev); 1838 } 1839 1840 static void 1841 ata_intel_old_setmode(device_t dev, int mode) 1842 { 1843 /* NOT YET */ 1844 } 1845 1846 static void 1847 ata_intel_new_setmode(device_t dev, int mode) 1848 { 1849 device_t gparent = GRANDPARENT(dev); 1850 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1851 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1852 struct ata_device *atadev = device_get_softc(dev); 1853 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1854 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4); 1855 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1); 1856 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1); 1857 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2); 1858 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2); 1859 u_int32_t mask40 = 0, new40 = 0; 1860 u_int8_t mask44 = 0, new44 = 0; 1861 int error; 1862 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, 1863 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 }; 1864 1865 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1866 1867 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { 1868 ata_print_cable(dev, "controller"); 1869 mode = ATA_UDMA2; 1870 } 1871 1872 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1873 1874 if (bootverbose) 1875 device_printf(dev, "%ssetting %s on %s chip\n", 1876 (error) ? "FAILURE " : "", 1877 ata_mode2str(mode), ctlr->chip->text); 1878 if (error) 1879 return; 1880 1881 if (mode >= ATA_UDMA0) { 1882 pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2); 1883 pci_write_config(gparent, 0x4a, 1884 (reg4a & ~(0x3 << (devno << 2))) | 1885 ((0x01 + !(mode & 0x01)) << (devno << 2)), 2); 1886 } 1887 else { 1888 pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2); 1889 pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2); 1890 } 1891 reg54 |= 0x0400; 1892 if (mode >= ATA_UDMA2) 1893 pci_write_config(gparent, 0x54, reg54 | (0x1 << devno), 2); 1894 else 1895 pci_write_config(gparent, 0x54, reg54 & ~(0x1 << devno), 2); 1896 1897 if (mode >= ATA_UDMA5) 1898 pci_write_config(gparent, 0x54, reg54 | (0x1000 << devno), 2); 1899 else 1900 pci_write_config(gparent, 0x54, reg54 & ~(0x1000 << devno), 2); 1901 1902 reg40 &= ~0x00ff00ff; 1903 reg40 |= 0x40774077; 1904 1905 if (atadev->unit == ATA_MASTER) { 1906 mask40 = 0x3300; 1907 new40 = timings[ata_mode2idx(mode)] << 8; 1908 } 1909 else { 1910 mask44 = 0x0f; 1911 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) | 1912 (timings[ata_mode2idx(mode)] & 0x03); 1913 } 1914 if (ch->unit) { 1915 mask40 <<= 16; 1916 new40 <<= 16; 1917 mask44 <<= 4; 1918 new44 <<= 4; 1919 } 1920 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4); 1921 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1); 1922 1923 atadev->mode = mode; 1924 } 1925 1926 static int 1927 ata_intel_31244_allocate(device_t dev) 1928 { 1929 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1930 struct ata_channel *ch = device_get_softc(dev); 1931 int i; 1932 int ch_offset; 1933 1934 ch_offset = 0x200 + ch->unit * 0x200; 1935 1936 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 1937 ch->r_io[i].res = ctlr->r_res2; 1938 1939 /* setup ATA registers */ 1940 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 1941 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 1942 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 1943 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 1944 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 1945 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 1946 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 1947 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 1948 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 1949 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 1950 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 1951 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 1952 1953 /* setup DMA registers */ 1954 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 1955 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 1956 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 1957 1958 /* setup SATA registers */ 1959 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 1960 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 1961 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 1962 1963 ch->flags |= ATA_NO_SLAVE; 1964 ata_pci_hw(dev); 1965 ch->hw.status = ata_intel_31244_status; 1966 ch->hw.command = ata_intel_31244_command; 1967 1968 /* enable PHY state change interrupt */ 1969 ATA_OUTL(ctlr->r_res2, 0x4, 1970 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 1971 return 0; 1972 } 1973 1974 static int 1975 ata_intel_31244_status(device_t dev) 1976 { 1977 struct ata_channel *ch = device_get_softc(dev); 1978 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS); 1979 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR); 1980 struct ata_connect_task *tp; 1981 1982 /* check for PHY related interrupts on SATA capable HW */ 1983 if (error) { 1984 /* clear error bits/interrupt */ 1985 ATA_IDX_OUTL(ch, ATA_SERROR, error); 1986 1987 /* if we have a connection event deal with it */ 1988 if ((error & ATA_SE_PHY_CHANGED) && 1989 (tp = (struct ata_connect_task *) 1990 kmalloc(sizeof(struct ata_connect_task), 1991 M_ATA, M_NOWAIT | M_ZERO))) { 1992 1993 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) { 1994 if (bootverbose) 1995 device_printf(ch->dev, "CONNECT requested\n"); 1996 tp->action = ATA_C_ATTACH; 1997 } 1998 else { 1999 if (bootverbose) 2000 device_printf(ch->dev, "DISCONNECT requested\n"); 2001 tp->action = ATA_C_DETACH; 2002 } 2003 tp->dev = ch->dev; 2004 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 2005 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 2006 } 2007 } 2008 2009 /* any drive action to take care of ? */ 2010 return ata_pci_status(dev); 2011 } 2012 2013 static int 2014 ata_intel_31244_command(struct ata_request *request) 2015 { 2016 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2017 struct ata_device *atadev = device_get_softc(request->dev); 2018 u_int64_t lba; 2019 2020 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 2021 return (ata_generic_command(request)); 2022 2023 lba = request->u.ata.lba; 2024 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 2025 /* enable interrupt */ 2026 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 2027 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 2028 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 2029 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff)); 2030 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) | 2031 ((lba >> 8) & 0x00ff)); 2032 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) | 2033 ((lba >> 16) & 0x00ff)); 2034 2035 /* issue command to controller */ 2036 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 2037 2038 return 0; 2039 } 2040 2041 static void 2042 ata_intel_31244_reset(device_t dev) 2043 { 2044 struct ata_channel *ch = device_get_softc(dev); 2045 2046 ata_sata_phy_enable(ch); 2047 } 2048 2049 2050 /* 2051 * Integrated Technology Express Inc. (ITE) chipset support functions 2052 */ 2053 int 2054 ata_ite_ident(device_t dev) 2055 { 2056 struct ata_pci_controller *ctlr = device_get_softc(dev); 2057 struct ata_chip_id *idx; 2058 static struct ata_chip_id ids[] = 2059 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 2060 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 2061 { 0, 0, 0, 0, 0, 0}}; 2062 char buffer[64]; 2063 2064 if (!(idx = ata_match_chip(dev, ids))) 2065 return ENXIO; 2066 2067 ksprintf(buffer, "ITE %s %s controller", 2068 idx->text, ata_mode2str(idx->max_dma)); 2069 device_set_desc_copy(dev, buffer); 2070 ctlr->chip = idx; 2071 ctlr->chipinit = ata_ite_chipinit; 2072 return 0; 2073 } 2074 2075 static int 2076 ata_ite_chipinit(device_t dev) 2077 { 2078 struct ata_pci_controller *ctlr = device_get_softc(dev); 2079 2080 if (ata_setup_interrupt(dev)) 2081 return ENXIO; 2082 2083 ctlr->setmode = ata_ite_setmode; 2084 2085 /* set PCI mode and 66Mhz reference clock */ 2086 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 2087 2088 /* set default active & recover timings */ 2089 pci_write_config(dev, 0x54, 0x31, 1); 2090 pci_write_config(dev, 0x56, 0x31, 1); 2091 return 0; 2092 } 2093 2094 static void 2095 ata_ite_setmode(device_t dev, int mode) 2096 { 2097 device_t gparent = GRANDPARENT(dev); 2098 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2099 struct ata_device *atadev = device_get_softc(dev); 2100 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2101 int error; 2102 2103 /* correct the mode for what the HW supports */ 2104 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2105 2106 /* check the CBLID bits for 80 conductor cable detection */ 2107 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) & 2108 (ch->unit ? (1<<3) : (1<<2)))) { 2109 ata_print_cable(dev, "controller"); 2110 mode = ATA_UDMA2; 2111 } 2112 2113 /* set the wanted mode on the device */ 2114 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2115 2116 if (bootverbose) 2117 device_printf(dev, "%s setting %s on ITE8212F chip\n", 2118 (error) ? "failed" : "success", ata_mode2str(mode)); 2119 2120 /* if the device accepted the mode change, setup the HW accordingly */ 2121 if (!error) { 2122 if (mode >= ATA_UDMA0) { 2123 u_int8_t udmatiming[] = 2124 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 2125 2126 /* enable UDMA mode */ 2127 pci_write_config(gparent, 0x50, 2128 pci_read_config(gparent, 0x50, 1) & 2129 ~(1 << (devno + 3)), 1); 2130 2131 /* set UDMA timing */ 2132 pci_write_config(gparent, 2133 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit), 2134 udmatiming[mode & ATA_MODE_MASK], 1); 2135 } 2136 else { 2137 u_int8_t chtiming[] = 2138 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 2139 2140 /* disable UDMA mode */ 2141 pci_write_config(gparent, 0x50, 2142 pci_read_config(gparent, 0x50, 1) | 2143 (1 << (devno + 3)), 1); 2144 2145 /* set active and recover timing (shared between master & slave) */ 2146 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) < 2147 chtiming[ata_mode2idx(mode)]) 2148 pci_write_config(gparent, 0x54 + (ch->unit << 2), 2149 chtiming[ata_mode2idx(mode)], 1); 2150 } 2151 atadev->mode = mode; 2152 } 2153 } 2154 2155 2156 /* 2157 * JMicron chipset support functions 2158 */ 2159 int 2160 ata_jmicron_ident(device_t dev) 2161 { 2162 struct ata_pci_controller *ctlr = device_get_softc(dev); 2163 struct ata_chip_id *idx; 2164 static struct ata_chip_id ids[] = 2165 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" }, 2166 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" }, 2167 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" }, 2168 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" }, 2169 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" }, 2170 { 0, 0, 0, 0, 0, 0}}; 2171 char buffer[64]; 2172 2173 if (!(idx = ata_match_chip(dev, ids))) 2174 return ENXIO; 2175 2176 ksprintf(buffer, "JMicron %s %s controller", 2177 idx->text, ata_mode2str(idx->max_dma)); 2178 device_set_desc_copy(dev, buffer); 2179 ctlr->chip = idx; 2180 ctlr->chipinit = ata_jmicron_chipinit; 2181 return 0; 2182 } 2183 2184 static int 2185 ata_jmicron_chipinit(device_t dev) 2186 { 2187 struct ata_pci_controller *ctlr = device_get_softc(dev); 2188 int error; 2189 2190 if (ata_setup_interrupt(dev)) 2191 return ENXIO; 2192 2193 /* set controller configuration to a setup we support */ 2194 pci_write_config(dev, 0x40, 0x80c0a131, 4); 2195 pci_write_config(dev, 0x80, 0x01200000, 4); 2196 2197 ctlr->allocate = ata_jmicron_allocate; 2198 ctlr->deallocate = ata_jmicron_deallocate; 2199 ctlr->reset = ata_jmicron_reset; 2200 ctlr->dmainit = ata_jmicron_dmainit; 2201 ctlr->setmode = ata_jmicron_setmode; 2202 2203 ctlr->r_type2 = SYS_RES_MEMORY; 2204 ctlr->r_rid2 = PCIR_BAR(5); 2205 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 2206 &ctlr->r_rid2, RF_ACTIVE))) { 2207 if ((error = ata_ahci_chipinit(dev))) 2208 return error; 2209 } 2210 2211 /* set the number of HW channels */ 2212 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2; 2213 return 0; 2214 } 2215 2216 static int 2217 ata_jmicron_allocate(device_t dev) 2218 { 2219 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2220 struct ata_channel *ch = device_get_softc(dev); 2221 int error; 2222 2223 if (ch->unit >= ctlr->chip->cfg1) { 2224 ch->unit -= ctlr->chip->cfg1; 2225 error = ata_pci_allocate(dev); 2226 ch->unit += ctlr->chip->cfg1; 2227 } 2228 else 2229 error = ata_ahci_allocate(dev); 2230 return error; 2231 } 2232 2233 /* 2234 * Deallocate resources that have been allocated for the ATA channel. 2235 */ 2236 static int 2237 ata_jmicron_deallocate(device_t dev) 2238 { 2239 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2240 struct ata_channel *ch = device_get_softc(dev); 2241 int error; 2242 2243 if (ch->unit >= ctlr->chip->cfg1) { 2244 ch->unit -= ctlr->chip->cfg1; 2245 error = ata_pci_deallocate(dev); 2246 ch->unit += ctlr->chip->cfg1; 2247 } else 2248 error = ata_generic_nulldeallocate(dev); 2249 2250 return error; 2251 } 2252 2253 static void 2254 ata_jmicron_reset(device_t dev) 2255 { 2256 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2257 struct ata_channel *ch = device_get_softc(dev); 2258 2259 if (ch->unit >= ctlr->chip->cfg1) 2260 ata_generic_reset(dev); 2261 else 2262 ata_ahci_reset(dev); 2263 } 2264 2265 static void 2266 ata_jmicron_dmainit(device_t dev) 2267 { 2268 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2269 struct ata_channel *ch = device_get_softc(dev); 2270 2271 if (ch->unit >= ctlr->chip->cfg1) 2272 ata_pci_dmainit(dev); 2273 else 2274 ata_ahci_dmainit(dev); 2275 } 2276 2277 static void 2278 ata_jmicron_setmode(device_t dev, int mode) 2279 { 2280 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 2281 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2282 2283 if (ch->unit >= ctlr->chip->cfg1) { 2284 struct ata_device *atadev = device_get_softc(dev); 2285 2286 /* check for 80pin cable present */ 2287 if (pci_read_config(dev, 0x40, 1) & 0x08) 2288 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 2289 else 2290 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2291 2292 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2293 atadev->mode = mode; 2294 } 2295 else 2296 ata_sata_setmode(dev, mode); 2297 } 2298 2299 2300 /* 2301 * Marvell chipset support functions 2302 */ 2303 #define ATA_MV_HOST_BASE(ch) \ 2304 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000) 2305 #define ATA_MV_EDMA_BASE(ch) \ 2306 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000) 2307 2308 struct ata_marvell_response { 2309 u_int16_t tag; 2310 u_int8_t edma_status; 2311 u_int8_t dev_status; 2312 u_int32_t timestamp; 2313 }; 2314 2315 struct ata_marvell_dma_prdentry { 2316 u_int32_t addrlo; 2317 u_int32_t count; 2318 u_int32_t addrhi; 2319 u_int32_t reserved; 2320 }; 2321 2322 int 2323 ata_marvell_ident(device_t dev) 2324 { 2325 struct ata_pci_controller *ctlr = device_get_softc(dev); 2326 struct ata_chip_id *idx; 2327 static struct ata_chip_id ids[] = 2328 {{ ATA_M88SX5040, 0, 4, MV5XXX, ATA_SA150, "88SX5040" }, 2329 { ATA_M88SX5041, 0, 4, MV5XXX, ATA_SA150, "88SX5041" }, 2330 { ATA_M88SX5080, 0, 8, MV5XXX, ATA_SA150, "88SX5080" }, 2331 { ATA_M88SX5081, 0, 8, MV5XXX, ATA_SA150, "88SX5081" }, 2332 { ATA_M88SX6041, 0, 4, MV6XXX, ATA_SA300, "88SX6041" }, 2333 { ATA_M88SX6081, 0, 8, MV6XXX, ATA_SA300, "88SX6081" }, 2334 { 0, 0, 0, 0, 0, 0}}; 2335 char buffer[64]; 2336 2337 if (!(idx = ata_match_chip(dev, ids))) 2338 return ENXIO; 2339 2340 ksprintf(buffer, "Marvell %s %s controller", 2341 idx->text, ata_mode2str(idx->max_dma)); 2342 device_set_desc_copy(dev, buffer); 2343 ctlr->chip = idx; 2344 ctlr->chipinit = ata_marvell_chipinit; 2345 return 0; 2346 } 2347 2348 static int 2349 ata_marvell_chipinit(device_t dev) 2350 { 2351 struct ata_pci_controller *ctlr = device_get_softc(dev); 2352 2353 if (ata_setup_interrupt(dev)) 2354 return ENXIO; 2355 2356 ctlr->r_type1 = SYS_RES_MEMORY; 2357 ctlr->r_rid1 = PCIR_BAR(0); 2358 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 2359 &ctlr->r_rid1, RF_ACTIVE))) 2360 return ENXIO; 2361 2362 /* mask all host controller interrupts */ 2363 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000); 2364 2365 /* mask all PCI interrupts */ 2366 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000); 2367 2368 ctlr->allocate = ata_marvell_allocate; 2369 ctlr->deallocate = ata_generic_nulldeallocate; 2370 ctlr->reset = ata_marvell_reset; 2371 ctlr->dmainit = ata_marvell_dmainit; 2372 ctlr->setmode = ata_sata_setmode; 2373 ctlr->channels = ctlr->chip->cfg1; 2374 2375 /* clear host controller interrupts */ 2376 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000); 2377 if (ctlr->chip->cfg1 > 4) 2378 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000); 2379 2380 /* clear PCI interrupts */ 2381 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000); 2382 2383 /* unmask PCI interrupts we want */ 2384 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff); 2385 2386 /* unmask host controller interrupts we want */ 2387 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ | 2388 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25)); 2389 2390 /* enable PCI interrupt */ 2391 pci_write_config(dev, PCIR_COMMAND, 2392 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 2393 return 0; 2394 } 2395 2396 static int 2397 ata_marvell_allocate(device_t dev) 2398 { 2399 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2400 struct ata_channel *ch = device_get_softc(dev); 2401 bus_addr_t work = ch->dma->work_bus; 2402 int i; 2403 2404 /* clear work area */ 2405 bzero(ch->dma->work, 1024+256); 2406 2407 /* set legacy ATA resources */ 2408 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 2409 ch->r_io[i].res = ctlr->r_res1; 2410 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch); 2411 } 2412 ch->r_io[ATA_CONTROL].res = ctlr->r_res1; 2413 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch); 2414 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1; 2415 ata_default_registers(dev); 2416 2417 /* set SATA resources */ 2418 switch (ctlr->chip->cfg2) { 2419 case MV5XXX: 2420 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2421 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch); 2422 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2423 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch); 2424 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2425 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch); 2426 break; 2427 case MV6XXX: 2428 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2429 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch); 2430 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2431 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch); 2432 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2433 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch); 2434 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1; 2435 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch); 2436 break; 2437 } 2438 2439 ch->flags |= ATA_NO_SLAVE; 2440 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */ 2441 ata_generic_hw(dev); 2442 ch->hw.begin_transaction = ata_marvell_begin_transaction; 2443 ch->hw.end_transaction = ata_marvell_end_transaction; 2444 ch->hw.status = ata_marvell_status; 2445 2446 /* disable the EDMA machinery */ 2447 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2448 DELAY(100000); /* SOS should poll for disabled */ 2449 2450 /* set configuration to non-queued 128b read transfers stop on error */ 2451 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13)); 2452 2453 /* request queue base high */ 2454 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), (work >> 16) >> 16); 2455 2456 /* request queue in ptr */ 2457 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2458 2459 /* request queue out ptr */ 2460 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0); 2461 2462 /* response queue base high */ 2463 work += 1024; 2464 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), (work >> 16) >> 16); 2465 2466 /* response queue in ptr */ 2467 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0); 2468 2469 /* response queue out ptr */ 2470 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2471 2472 /* clear SATA error register */ 2473 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 2474 2475 /* clear any outstanding error interrupts */ 2476 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2477 2478 /* unmask all error interrupts */ 2479 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 2480 2481 /* enable EDMA machinery */ 2482 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2483 return 0; 2484 } 2485 2486 static int 2487 ata_marvell_status(device_t dev) 2488 { 2489 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2490 struct ata_channel *ch = device_get_softc(dev); 2491 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60); 2492 int shift = (ch->unit << 1) + (ch->unit > 3); 2493 2494 /* do we have any errors flagged ? */ 2495 if (cause & (1 << shift)) { 2496 struct ata_connect_task *tp; 2497 u_int32_t error = 2498 ATA_INL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch)); 2499 2500 /* check for and handle disconnect events */ 2501 if ((error & 0x00000008) && 2502 (tp = (struct ata_connect_task *) 2503 kmalloc(sizeof(struct ata_connect_task), 2504 M_ATA, M_NOWAIT | M_ZERO))) { 2505 2506 if (bootverbose) 2507 device_printf(ch->dev, "DISCONNECT requested\n"); 2508 tp->action = ATA_C_DETACH; 2509 tp->dev = ch->dev; 2510 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 2511 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 2512 } 2513 2514 /* check for and handle connect events */ 2515 if ((error & 0x00000010) && 2516 (tp = (struct ata_connect_task *) 2517 kmalloc(sizeof(struct ata_connect_task), 2518 M_ATA, M_NOWAIT | M_ZERO))) { 2519 2520 if (bootverbose) 2521 device_printf(ch->dev, "CONNECT requested\n"); 2522 tp->action = ATA_C_ATTACH; 2523 tp->dev = ch->dev; 2524 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 2525 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 2526 } 2527 2528 /* clear SATA error register */ 2529 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 2530 2531 /* clear any outstanding error interrupts */ 2532 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2533 } 2534 2535 /* do we have any device action ? */ 2536 return (cause & (2 << shift)); 2537 } 2538 2539 /* must be called with ATA channel locked and state_mtx held */ 2540 static int 2541 ata_marvell_begin_transaction(struct ata_request *request) 2542 { 2543 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2544 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2545 u_int32_t req_in; 2546 u_int8_t *bytep; 2547 u_int16_t *wordp; 2548 u_int32_t *quadp; 2549 int i, tag = 0x07; 2550 int dummy, error, slot; 2551 2552 /* only DMA R/W goes through the EMDA machine */ 2553 if (request->u.ata.command != ATA_READ_DMA && 2554 request->u.ata.command != ATA_WRITE_DMA) { 2555 2556 /* disable the EDMA machinery */ 2557 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001) 2558 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2559 return ata_begin_transaction(request); 2560 } 2561 2562 /* check for 48 bit access and convert if needed */ 2563 ata_modify_if_48bit(request); 2564 2565 /* check sanity, setup SG list and DMA engine */ 2566 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 2567 request->flags & ATA_R_READ, ch->dma->sg, 2568 &dummy))) { 2569 device_printf(request->dev, "setting up DMA failed\n"); 2570 request->result = error; 2571 return ATA_OP_FINISHED; 2572 } 2573 2574 /* get next free request queue slot */ 2575 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch)); 2576 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f; 2577 bytep = (u_int8_t *)(ch->dma->work); 2578 bytep += (slot << 5); 2579 wordp = (u_int16_t *)bytep; 2580 quadp = (u_int32_t *)bytep; 2581 2582 /* fill in this request */ 2583 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff; 2584 quadp[1] = (ch->dma->sg_bus & 0xffffffff00000000) >> 32; 2585 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1); 2586 2587 i = 10; 2588 bytep[i++] = (request->u.ata.count >> 8) & 0xff; 2589 bytep[i++] = 0x10 | ATA_COUNT; 2590 bytep[i++] = request->u.ata.count & 0xff; 2591 bytep[i++] = 0x10 | ATA_COUNT; 2592 2593 bytep[i++] = (request->u.ata.lba >> 24) & 0xff; 2594 bytep[i++] = 0x10 | ATA_SECTOR; 2595 bytep[i++] = request->u.ata.lba & 0xff; 2596 bytep[i++] = 0x10 | ATA_SECTOR; 2597 2598 bytep[i++] = (request->u.ata.lba >> 32) & 0xff; 2599 bytep[i++] = 0x10 | ATA_CYL_LSB; 2600 bytep[i++] = (request->u.ata.lba >> 8) & 0xff; 2601 bytep[i++] = 0x10 | ATA_CYL_LSB; 2602 2603 bytep[i++] = (request->u.ata.lba >> 40) & 0xff; 2604 bytep[i++] = 0x10 | ATA_CYL_MSB; 2605 bytep[i++] = (request->u.ata.lba >> 16) & 0xff; 2606 bytep[i++] = 0x10 | ATA_CYL_MSB; 2607 2608 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf); 2609 bytep[i++] = 0x10 | ATA_DRIVE; 2610 2611 bytep[i++] = request->u.ata.command; 2612 bytep[i++] = 0x90 | ATA_COMMAND; 2613 2614 /* enable EDMA machinery if needed */ 2615 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) { 2616 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2617 while (!(ATA_INL(ctlr->r_res1, 2618 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 2619 DELAY(10); 2620 } 2621 2622 /* tell EDMA it has a new request */ 2623 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f; 2624 req_in &= 0xfffffc00; 2625 req_in += (slot << 5); 2626 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in); 2627 2628 return ATA_OP_CONTINUES; 2629 } 2630 2631 /* must be called with ATA channel locked and state_mtx held */ 2632 static int 2633 ata_marvell_end_transaction(struct ata_request *request) 2634 { 2635 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2636 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2637 int offset = (ch->unit > 3 ? 0x30014 : 0x20014); 2638 u_int32_t icr = ATA_INL(ctlr->r_res1, offset); 2639 int res; 2640 2641 /* EDMA interrupt */ 2642 if ((icr & (0x0001 << (ch->unit & 3)))) { 2643 struct ata_marvell_response *response; 2644 u_int32_t rsp_in, rsp_out; 2645 int slot; 2646 2647 /* unload SG list */ 2648 ch->dma->unload(ch->dev); 2649 2650 /* stop timeout */ 2651 callout_stop(&request->callout); 2652 2653 /* get response ptr's */ 2654 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch)); 2655 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch)); 2656 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f; 2657 rsp_out &= 0xffffff00; 2658 rsp_out += (slot << 3); 2659 response = (struct ata_marvell_response *) 2660 (ch->dma->work + 1024 + (slot << 3)); 2661 2662 /* record status for this request */ 2663 request->status = response->dev_status; 2664 request->error = 0; 2665 2666 /* ack response */ 2667 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out); 2668 2669 /* update progress */ 2670 if (!(request->status & ATA_S_ERROR) && 2671 !(request->flags & ATA_R_TIMEOUT)) 2672 request->donecount = request->bytecount; 2673 res = ATA_OP_FINISHED; 2674 } 2675 2676 /* legacy ATA interrupt */ 2677 else { 2678 res = ata_end_transaction(request); 2679 } 2680 2681 /* ack interrupt */ 2682 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3)))); 2683 return res; 2684 } 2685 2686 static void 2687 ata_marvell_reset(device_t dev) 2688 { 2689 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2690 struct ata_channel *ch = device_get_softc(dev); 2691 2692 /* disable the EDMA machinery */ 2693 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2694 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 2695 DELAY(10); 2696 2697 /* clear SATA error register */ 2698 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 2699 2700 /* clear any outstanding error interrupts */ 2701 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2702 2703 /* unmask all error interrupts */ 2704 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 2705 2706 /* enable channel and test for devices */ 2707 ata_sata_phy_enable(ch); 2708 2709 /* enable EDMA machinery */ 2710 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2711 } 2712 2713 static void 2714 ata_marvell_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 2715 { 2716 struct ata_dmasetprd_args *args = xsc; 2717 struct ata_marvell_dma_prdentry *prd = args->dmatab; 2718 int i; 2719 2720 if ((args->error = error)) 2721 return; 2722 2723 for (i = 0; i < nsegs; i++) { 2724 prd[i].addrlo = htole32(segs[i].ds_addr); 2725 prd[i].addrhi = 0; 2726 prd[i].count = htole32(segs[i].ds_len); 2727 } 2728 prd[i - 1].count |= htole32(ATA_DMA_EOT); 2729 } 2730 2731 static void 2732 ata_marvell_dmainit(device_t dev) 2733 { 2734 struct ata_channel *ch = device_get_softc(dev); 2735 2736 ata_dmainit(dev); 2737 if (ch->dma) { 2738 /* note start and stop are not used here */ 2739 ch->dma->setprd = ata_marvell_dmasetprd; 2740 } 2741 } 2742 2743 2744 /* 2745 * National chipset support functions 2746 */ 2747 int 2748 ata_national_ident(device_t dev) 2749 { 2750 struct ata_pci_controller *ctlr = device_get_softc(dev); 2751 2752 /* this chip is a clone of the Cyrix chip, bugs and all */ 2753 if (pci_get_devid(dev) == ATA_SC1100) { 2754 device_set_desc(dev, "National Geode SC1100 ATA33 controller"); 2755 ctlr->chipinit = ata_national_chipinit; 2756 return 0; 2757 } 2758 return ENXIO; 2759 } 2760 2761 static int 2762 ata_national_chipinit(device_t dev) 2763 { 2764 struct ata_pci_controller *ctlr = device_get_softc(dev); 2765 2766 if (ata_setup_interrupt(dev)) 2767 return ENXIO; 2768 2769 ctlr->setmode = ata_national_setmode; 2770 return 0; 2771 } 2772 2773 static void 2774 ata_national_setmode(device_t dev, int mode) 2775 { 2776 device_t gparent = GRANDPARENT(dev); 2777 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2778 struct ata_device *atadev = device_get_softc(dev); 2779 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2780 u_int32_t piotiming[] = 2781 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010, 2782 0x00803020, 0x20102010, 0x00100010, 2783 0x00100010, 0x00100010, 0x00100010 }; 2784 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 }; 2785 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 }; 2786 int error; 2787 2788 ch->dma->alignment = 16; 2789 ch->dma->max_iosize = 126 * DEV_BSIZE; 2790 2791 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 2792 2793 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2794 2795 if (bootverbose) 2796 device_printf(dev, "%s setting %s on National chip\n", 2797 (error) ? "failed" : "success", ata_mode2str(mode)); 2798 if (!error) { 2799 if (mode >= ATA_UDMA0) { 2800 pci_write_config(gparent, 0x44 + (devno << 3), 2801 udmatiming[mode & ATA_MODE_MASK], 4); 2802 } 2803 else if (mode >= ATA_WDMA0) { 2804 pci_write_config(gparent, 0x44 + (devno << 3), 2805 dmatiming[mode & ATA_MODE_MASK], 4); 2806 } 2807 else { 2808 pci_write_config(gparent, 0x44 + (devno << 3), 2809 pci_read_config(gparent, 0x44 + (devno << 3), 4) | 2810 0x80000000, 4); 2811 } 2812 pci_write_config(gparent, 0x40 + (devno << 3), 2813 piotiming[ata_mode2idx(mode)], 4); 2814 atadev->mode = mode; 2815 } 2816 } 2817 2818 2819 /* 2820 * nVidia chipset support functions 2821 */ 2822 int 2823 ata_nvidia_ident(device_t dev) 2824 { 2825 struct ata_pci_controller *ctlr = device_get_softc(dev); 2826 struct ata_chip_id *idx; 2827 static struct ata_chip_id ids[] = 2828 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" }, 2829 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" }, 2830 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" }, 2831 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" }, 2832 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" }, 2833 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" }, 2834 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 2835 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 2836 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" }, 2837 { ATA_NFORCE_MCP04_S1, 0, 0, NV4BYTE, ATA_SA150, "nForce MCP" }, 2838 { ATA_NFORCE_MCP04_S2, 0, 0, NV4BYTE, ATA_SA150, "nForce MCP" }, 2839 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" }, 2840 { ATA_NFORCE_CK804_S1, 0, 0, NV4BYTE, ATA_SA300, "nForce CK804" }, 2841 { ATA_NFORCE_CK804_S2, 0, 0, NV4BYTE, ATA_SA300, "nForce CK804" }, 2842 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" }, 2843 { ATA_NFORCE_MCP51_S1, 0, 0, NV4WORD, ATA_SA300, "nForce MCP51" }, 2844 { ATA_NFORCE_MCP51_S2, 0, 0, NV4WORD, ATA_SA300, "nForce MCP51" }, 2845 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" }, 2846 { ATA_NFORCE_MCP55_S1, 0, 0, NV4WORD, ATA_SA300, "nForce MCP55" }, 2847 { ATA_NFORCE_MCP55_S2, 0, 0, NV4WORD, ATA_SA300, "nForce MCP55" }, 2848 { 0, 0, 0, 0, 0, 0}} ; 2849 char buffer[64] ; 2850 2851 if (!(idx = ata_match_chip(dev, ids))) 2852 return ENXIO; 2853 2854 ksprintf(buffer, "nVidia %s %s controller", 2855 idx->text, ata_mode2str(idx->max_dma)); 2856 device_set_desc_copy(dev, buffer); 2857 ctlr->chip = idx; 2858 ctlr->chipinit = ata_nvidia_chipinit; 2859 return 0; 2860 } 2861 2862 static int 2863 ata_nvidia_chipinit(device_t dev) 2864 { 2865 struct ata_pci_controller *ctlr = device_get_softc(dev); 2866 2867 if (ata_setup_interrupt(dev)) 2868 return ENXIO; 2869 2870 if (ctlr->chip->max_dma >= ATA_SA150) { 2871 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1) 2872 ctlr->r_type2 = SYS_RES_IOPORT; 2873 else 2874 ctlr->r_type2 = SYS_RES_MEMORY; 2875 ctlr->r_rid2 = PCIR_BAR(5); 2876 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 2877 &ctlr->r_rid2, RF_ACTIVE))) { 2878 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 2879 2880 ctlr->allocate = ata_nvidia_allocate; 2881 ctlr->reset = ata_nvidia_reset; 2882 2883 /* enable control access */ 2884 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1); 2885 2886 if (ctlr->chip->cfg2 == NV4BYTE) { 2887 /* clear interrupt status */ 2888 ATA_OUTB(ctlr->r_res2, offset, 0xff); 2889 2890 /* enable device and PHY state change interrupts */ 2891 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd); 2892 } 2893 else { 2894 /* clear interrupt status */ 2895 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff); 2896 2897 /* enable device and PHY state change interrupts */ 2898 ATA_OUTL(ctlr->r_res2, offset + 4, 0x00dd00dd); 2899 } 2900 2901 /* enable PCI interrupt */ 2902 pci_write_config(dev, PCIR_COMMAND, 2903 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 2904 2905 } 2906 ctlr->setmode = ata_sata_setmode; 2907 } 2908 else { 2909 /* disable prefetch, postwrite */ 2910 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1); 2911 ctlr->setmode = ata_via_family_setmode; 2912 } 2913 return 0; 2914 } 2915 2916 static int 2917 ata_nvidia_allocate(device_t dev) 2918 { 2919 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2920 struct ata_channel *ch = device_get_softc(dev); 2921 2922 /* setup the usual register normal pci style */ 2923 if (ata_pci_allocate(dev)) 2924 return ENXIO; 2925 2926 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 2927 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6); 2928 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 2929 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6); 2930 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 2931 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6); 2932 2933 ch->hw.status = ata_nvidia_status; 2934 ch->flags |= ATA_NO_SLAVE; 2935 2936 return 0; 2937 } 2938 2939 static int 2940 ata_nvidia_status(device_t dev) 2941 { 2942 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2943 struct ata_channel *ch = device_get_softc(dev); 2944 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 2945 struct ata_connect_task *tp; 2946 int shift = ch->unit << (ctlr->chip->cfg2 == NV4BYTE ? 2 : 4); 2947 u_int32_t status; 2948 2949 /* get and clear interrupt status */ 2950 if (ctlr->chip->cfg2 == NV4BYTE) { 2951 status = ATA_INB(ctlr->r_res2, offset); 2952 ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift)); 2953 } 2954 else { 2955 status = ATA_INL(ctlr->r_res2, offset); 2956 ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift)); 2957 } 2958 2959 /* check for and handle connect events */ 2960 if (((status & (0x0c << shift)) == (0x04 << shift)) && 2961 (tp = (struct ata_connect_task *) 2962 kmalloc(sizeof(struct ata_connect_task), 2963 M_ATA, M_NOWAIT | M_ZERO))) { 2964 2965 if (bootverbose) 2966 device_printf(ch->dev, "CONNECT requested\n"); 2967 tp->action = ATA_C_ATTACH; 2968 tp->dev = ch->dev; 2969 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 2970 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 2971 } 2972 2973 /* check for and handle disconnect events */ 2974 if ((status & (0x08 << shift)) && 2975 (tp = (struct ata_connect_task *) 2976 kmalloc(sizeof(struct ata_connect_task), 2977 M_ATA, M_NOWAIT | M_ZERO))) { 2978 2979 if (bootverbose) 2980 device_printf(ch->dev, "DISCONNECT requested\n"); 2981 tp->action = ATA_C_DETACH; 2982 tp->dev = ch->dev; 2983 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 2984 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 2985 } 2986 2987 /* do we have any device action ? */ 2988 return (status & (0x01 << shift)); 2989 } 2990 2991 static void 2992 ata_nvidia_reset(device_t dev) 2993 { 2994 struct ata_channel *ch = device_get_softc(dev); 2995 2996 ata_sata_phy_enable(ch); 2997 } 2998 2999 3000 /* 3001 * Promise chipset support functions 3002 */ 3003 #define ATA_PDC_APKT_OFFSET 0x00000010 3004 #define ATA_PDC_HPKT_OFFSET 0x00000040 3005 #define ATA_PDC_ASG_OFFSET 0x00000080 3006 #define ATA_PDC_LSG_OFFSET 0x000000c0 3007 #define ATA_PDC_HSG_OFFSET 0x00000100 3008 #define ATA_PDC_CHN_OFFSET 0x00000400 3009 #define ATA_PDC_BUF_BASE 0x00400000 3010 #define ATA_PDC_BUF_OFFSET 0x00100000 3011 #define ATA_PDC_MAX_HPKT 8 3012 #define ATA_PDC_WRITE_REG 0x00 3013 #define ATA_PDC_WRITE_CTL 0x0e 3014 #define ATA_PDC_WRITE_END 0x08 3015 #define ATA_PDC_WAIT_NBUSY 0x10 3016 #define ATA_PDC_WAIT_READY 0x18 3017 #define ATA_PDC_1B 0x20 3018 #define ATA_PDC_2B 0x40 3019 3020 struct host_packet { 3021 u_int32_t addr; 3022 TAILQ_ENTRY(host_packet) chain; 3023 }; 3024 3025 struct ata_promise_sx4 { 3026 struct spinlock mtx; 3027 TAILQ_HEAD(, host_packet) queue; 3028 int busy; 3029 }; 3030 3031 int 3032 ata_promise_ident(device_t dev) 3033 { 3034 struct ata_pci_controller *ctlr = device_get_softc(dev); 3035 struct ata_chip_id *idx; 3036 static struct ata_chip_id ids[] = 3037 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" }, 3038 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" }, 3039 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" }, 3040 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" }, 3041 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" }, 3042 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" }, 3043 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" }, 3044 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" }, 3045 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" }, 3046 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" }, 3047 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" }, 3048 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" }, 3049 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" }, 3050 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" }, 3051 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" }, 3052 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" }, 3053 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" }, 3054 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" }, 3055 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" }, 3056 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" }, 3057 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" }, 3058 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" }, 3059 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" }, 3060 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" }, 3061 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" }, 3062 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" }, 3063 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" }, 3064 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" }, 3065 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" }, 3066 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" }, 3067 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" }, 3068 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" }, 3069 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" }, 3070 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" }, 3071 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" }, 3072 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" }, 3073 { 0, 0, 0, 0, 0, 0}}; 3074 char buffer[64]; 3075 uintptr_t devid = 0; 3076 3077 if (!(idx = ata_match_chip(dev, ids))) 3078 return ENXIO; 3079 3080 /* if we are on a SuperTrak SX6000 dont attach */ 3081 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3082 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3083 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3084 devid == ATA_I960RM) 3085 return ENXIO; 3086 3087 strcpy(buffer, "Promise "); 3088 strcat(buffer, idx->text); 3089 3090 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 3091 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3092 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3093 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3094 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 3095 static long start = 0, end = 0; 3096 3097 if (pci_get_slot(dev) == 1) { 3098 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 3099 strcat(buffer, " (channel 0+1)"); 3100 } 3101 else if (pci_get_slot(dev) == 2 && start && end) { 3102 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 3103 strcat(buffer, " (channel 2+3)"); 3104 } 3105 else { 3106 start = end = 0; 3107 } 3108 } 3109 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 3110 device_set_desc_copy(dev, buffer); 3111 ctlr->chip = idx; 3112 ctlr->chipinit = ata_promise_chipinit; 3113 return 0; 3114 } 3115 3116 static int 3117 ata_promise_chipinit(device_t dev) 3118 { 3119 struct ata_pci_controller *ctlr = device_get_softc(dev); 3120 int fake_reg, stat_reg; 3121 3122 if (ata_setup_interrupt(dev)) 3123 return ENXIO; 3124 3125 switch (ctlr->chip->cfg1) { 3126 case PRNEW: 3127 /* setup clocks */ 3128 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 3129 3130 ctlr->dmainit = ata_promise_dmainit; 3131 /* FALLTHROUGH */ 3132 3133 case PROLD: 3134 /* enable burst mode */ 3135 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 3136 ctlr->allocate = ata_promise_allocate; 3137 ctlr->setmode = ata_promise_setmode; 3138 return 0; 3139 3140 case PRTX: 3141 ctlr->allocate = ata_promise_tx2_allocate; 3142 ctlr->setmode = ata_promise_setmode; 3143 return 0; 3144 3145 case PRMIO: 3146 ctlr->r_type1 = SYS_RES_MEMORY; 3147 ctlr->r_rid1 = PCIR_BAR(4); 3148 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 3149 &ctlr->r_rid1, RF_ACTIVE))) 3150 goto failnfree; 3151 3152 ctlr->r_type2 = SYS_RES_MEMORY; 3153 ctlr->r_rid2 = PCIR_BAR(3); 3154 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3155 &ctlr->r_rid2, RF_ACTIVE))) 3156 goto failnfree; 3157 3158 if (ctlr->chip->cfg2 == PRSX4X) { 3159 struct ata_promise_sx4 *hpkt; 3160 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 3161 3162 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3163 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3164 ata_promise_sx4_intr, ctlr, &ctlr->handle, NULL)) { 3165 device_printf(dev, "unable to setup interrupt\n"); 3166 goto failnfree; 3167 } 3168 3169 /* print info about cache memory */ 3170 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 3171 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 3172 ((dimm >> 24) & 0xff), 3173 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 3174 " ECC enabled" : "" ); 3175 3176 /* adjust cache memory parameters */ 3177 ATA_OUTL(ctlr->r_res2, 0x000c000c, 3178 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 3179 3180 /* setup host packet controls */ 3181 hpkt = kmalloc(sizeof(struct ata_promise_sx4), 3182 M_TEMP, M_NOWAIT | M_ZERO); 3183 spin_init(&hpkt->mtx); 3184 TAILQ_INIT(&hpkt->queue); 3185 hpkt->busy = 0; 3186 device_set_ivars(dev, hpkt); 3187 ctlr->allocate = ata_promise_mio_allocate; 3188 ctlr->deallocate = ata_generic_nulldeallocate; 3189 ctlr->reset = ata_promise_mio_reset; 3190 ctlr->dmainit = ata_promise_mio_dmainit; 3191 ctlr->setmode = ata_promise_setmode; 3192 ctlr->channels = 4; 3193 return 0; 3194 } 3195 3196 /* mio type controllers need an interrupt intercept */ 3197 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3198 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3199 ata_promise_mio_intr, ctlr, &ctlr->handle, NULL)) { 3200 device_printf(dev, "unable to setup interrupt\n"); 3201 goto failnfree; 3202 } 3203 3204 switch (ctlr->chip->cfg2) { 3205 case PRPATA: 3206 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 3207 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 3208 goto sata150; 3209 case PRCMBO: 3210 ctlr->channels = 3; 3211 goto sata150; 3212 case PRSATA: 3213 ctlr->channels = 4; 3214 sata150: 3215 fake_reg = 0x60; 3216 stat_reg = 0x6c; 3217 break; 3218 3219 case PRCMBO2: 3220 ctlr->channels = 3; 3221 goto sataii; 3222 case PRSATA2: 3223 default: 3224 ctlr->channels = 4; 3225 sataii: 3226 fake_reg = 0x54; 3227 stat_reg = 0x60; 3228 break; 3229 } 3230 3231 /* prime fake interrupt register */ 3232 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3233 3234 /* clear SATA status */ 3235 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 3236 3237 ctlr->allocate = ata_promise_mio_allocate; 3238 ctlr->reset = ata_promise_mio_reset; 3239 ctlr->dmainit = ata_promise_mio_dmainit; 3240 ctlr->setmode = ata_promise_mio_setmode; 3241 3242 return 0; 3243 } 3244 3245 failnfree: 3246 if (ctlr->r_res2) 3247 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 3248 if (ctlr->r_res1) 3249 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 3250 return ENXIO; 3251 } 3252 3253 static int 3254 ata_promise_allocate(device_t dev) 3255 { 3256 struct ata_channel *ch = device_get_softc(dev); 3257 3258 if (ata_pci_allocate(dev)) 3259 return ENXIO; 3260 3261 ch->hw.status = ata_promise_status; 3262 return 0; 3263 } 3264 3265 static int 3266 ata_promise_status(device_t dev) 3267 { 3268 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3269 struct ata_channel *ch = device_get_softc(dev); 3270 3271 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 3272 return ata_pci_status(dev); 3273 } 3274 return 0; 3275 } 3276 3277 static int 3278 ata_promise_dmastart(device_t dev) 3279 { 3280 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3281 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3282 struct ata_device *atadev = device_get_softc(dev); 3283 3284 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3285 ATA_OUTB(ctlr->r_res1, 0x11, 3286 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 3287 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 3288 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) | 3289 (ch->dma->cur_iosize >> 1)); 3290 } 3291 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 3292 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 3293 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus); 3294 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3295 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) | 3296 ATA_BMCMD_START_STOP); 3297 ch->flags |= ATA_DMA_ACTIVE; 3298 return 0; 3299 } 3300 3301 static int 3302 ata_promise_dmastop(device_t dev) 3303 { 3304 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3305 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3306 struct ata_device *atadev = device_get_softc(dev); 3307 int error; 3308 3309 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3310 ATA_OUTB(ctlr->r_res1, 0x11, 3311 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 3312 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 3313 } 3314 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 3315 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3316 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3317 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3318 ch->flags &= ~ATA_DMA_ACTIVE; 3319 return error; 3320 } 3321 3322 static void 3323 ata_promise_dmareset(device_t dev) 3324 { 3325 struct ata_channel *ch = device_get_softc(dev); 3326 3327 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3328 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3329 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3330 ch->flags &= ~ATA_DMA_ACTIVE; 3331 } 3332 3333 static void 3334 ata_promise_dmainit(device_t dev) 3335 { 3336 struct ata_channel *ch = device_get_softc(dev); 3337 3338 ata_dmainit(dev); 3339 if (ch->dma) { 3340 ch->dma->start = ata_promise_dmastart; 3341 ch->dma->stop = ata_promise_dmastop; 3342 ch->dma->reset = ata_promise_dmareset; 3343 } 3344 } 3345 3346 static void 3347 ata_promise_setmode(device_t dev, int mode) 3348 { 3349 device_t gparent = GRANDPARENT(dev); 3350 struct ata_pci_controller *ctlr = device_get_softc(gparent); 3351 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3352 struct ata_device *atadev = device_get_softc(dev); 3353 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3354 int error; 3355 u_int32_t timings[][2] = { 3356 /* PROLD PRNEW mode */ 3357 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 3358 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 3359 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 3360 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 3361 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 3362 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 3363 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 3364 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 3365 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 3366 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 3367 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 3368 { 0, 0x00424ef6 }, /* UDMA 3 */ 3369 { 0, 0x004127f3 }, /* UDMA 4 */ 3370 { 0, 0x004127f3 } /* UDMA 5 */ 3371 }; 3372 3373 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 3374 3375 switch (ctlr->chip->cfg1) { 3376 case PROLD: 3377 case PRNEW: 3378 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) & 3379 (ch->unit ? 1 << 11 : 1 << 10))) { 3380 ata_print_cable(dev, "controller"); 3381 mode = ATA_UDMA2; 3382 } 3383 if (ata_atapi(dev) && mode > ATA_PIO_MAX) 3384 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 3385 break; 3386 3387 case PRTX: 3388 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3389 if (mode > ATA_UDMA2 && 3390 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 3391 ata_print_cable(dev, "controller"); 3392 mode = ATA_UDMA2; 3393 } 3394 break; 3395 3396 case PRMIO: 3397 if (mode > ATA_UDMA2 && 3398 (ATA_INL(ctlr->r_res2, 3399 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) + 3400 (ch->unit << 7)) & 0x01000000)) { 3401 ata_print_cable(dev, "controller"); 3402 mode = ATA_UDMA2; 3403 } 3404 break; 3405 } 3406 3407 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3408 3409 if (bootverbose) 3410 device_printf(dev, "%ssetting %s on %s chip\n", 3411 (error) ? "FAILURE " : "", 3412 ata_mode2str(mode), ctlr->chip->text); 3413 if (!error) { 3414 if (ctlr->chip->cfg1 < PRTX) 3415 pci_write_config(gparent, 0x60 + (devno << 2), 3416 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 3417 atadev->mode = mode; 3418 } 3419 return; 3420 } 3421 3422 static int 3423 ata_promise_tx2_allocate(device_t dev) 3424 { 3425 struct ata_channel *ch = device_get_softc(dev); 3426 3427 if (ata_pci_allocate(dev)) 3428 return ENXIO; 3429 3430 ch->hw.status = ata_promise_tx2_status; 3431 return 0; 3432 } 3433 3434 static int 3435 ata_promise_tx2_status(device_t dev) 3436 { 3437 struct ata_channel *ch = device_get_softc(dev); 3438 3439 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3440 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 3441 return ata_pci_status(dev); 3442 } 3443 return 0; 3444 } 3445 3446 static int 3447 ata_promise_mio_allocate(device_t dev) 3448 { 3449 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3450 struct ata_channel *ch = device_get_softc(dev); 3451 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0; 3452 int i; 3453 3454 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 3455 ch->r_io[i].res = ctlr->r_res2; 3456 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 3457 } 3458 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 3459 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 3460 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 3461 ata_default_registers(dev); 3462 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) || 3463 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) { 3464 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3465 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 3466 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3467 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 3468 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3469 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 3470 ch->flags |= ATA_NO_SLAVE; 3471 } 3472 ch->flags |= ATA_USE_16BIT; 3473 3474 ata_generic_hw(dev); 3475 if (ctlr->chip->cfg2 & PRSX4X) { 3476 ch->hw.command = ata_promise_sx4_command; 3477 } 3478 else { 3479 ch->hw.command = ata_promise_mio_command; 3480 ch->hw.status = ata_promise_mio_status; 3481 } 3482 return 0; 3483 } 3484 3485 static void 3486 ata_promise_mio_intr(void *data) 3487 { 3488 struct ata_pci_controller *ctlr = data; 3489 struct ata_channel *ch; 3490 u_int32_t vector; 3491 int unit, fake_reg; 3492 3493 switch (ctlr->chip->cfg2) { 3494 case PRPATA: 3495 case PRCMBO: 3496 case PRSATA: 3497 fake_reg = 0x60; 3498 break; 3499 case PRCMBO2: 3500 case PRSATA2: 3501 default: 3502 fake_reg = 0x54; 3503 break; 3504 } 3505 3506 /* 3507 * since reading interrupt status register on early "mio" chips 3508 * clears the status bits we cannot read it for each channel later on 3509 * in the generic interrupt routine. 3510 * store the bits in an unused register in the chip so we can read 3511 * it from there safely to get around this "feature". 3512 */ 3513 vector = ATA_INL(ctlr->r_res2, 0x040); 3514 ATA_OUTL(ctlr->r_res2, 0x040, vector); 3515 ATA_OUTL(ctlr->r_res2, fake_reg, vector); 3516 3517 for (unit = 0; unit < ctlr->channels; unit++) { 3518 if ((ch = ctlr->interrupt[unit].argument)) 3519 ctlr->interrupt[unit].function(ch); 3520 } 3521 3522 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3523 } 3524 3525 static int 3526 ata_promise_mio_status(device_t dev) 3527 { 3528 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3529 struct ata_channel *ch = device_get_softc(dev); 3530 struct ata_connect_task *tp; 3531 u_int32_t fake_reg, stat_reg, vector, status; 3532 3533 switch (ctlr->chip->cfg2) { 3534 case PRPATA: 3535 case PRCMBO: 3536 case PRSATA: 3537 fake_reg = 0x60; 3538 stat_reg = 0x6c; 3539 break; 3540 case PRCMBO2: 3541 case PRSATA2: 3542 default: 3543 fake_reg = 0x54; 3544 stat_reg = 0x60; 3545 break; 3546 } 3547 3548 /* read and acknowledge interrupt */ 3549 vector = ATA_INL(ctlr->r_res2, fake_reg); 3550 3551 /* read and clear interface status */ 3552 status = ATA_INL(ctlr->r_res2, stat_reg); 3553 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 3554 3555 /* check for and handle disconnect events */ 3556 if ((status & (0x00000001 << ch->unit)) && 3557 (tp = (struct ata_connect_task *) 3558 kmalloc(sizeof(struct ata_connect_task), 3559 M_ATA, M_NOWAIT | M_ZERO))) { 3560 3561 if (bootverbose) 3562 device_printf(ch->dev, "DISCONNECT requested\n"); 3563 tp->action = ATA_C_DETACH; 3564 tp->dev = ch->dev; 3565 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3566 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3567 } 3568 3569 /* check for and handle connect events */ 3570 if ((status & (0x00000010 << ch->unit)) && 3571 (tp = (struct ata_connect_task *) 3572 kmalloc(sizeof(struct ata_connect_task), 3573 M_ATA, M_NOWAIT | M_ZERO))) { 3574 3575 if (bootverbose) 3576 device_printf(ch->dev, "CONNECT requested\n"); 3577 tp->action = ATA_C_ATTACH; 3578 tp->dev = ch->dev; 3579 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3580 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3581 } 3582 3583 /* do we have any device action ? */ 3584 return (vector & (1 << (ch->unit + 1))); 3585 } 3586 3587 static int 3588 ata_promise_mio_command(struct ata_request *request) 3589 { 3590 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 3591 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 3592 u_int32_t *wordp = (u_int32_t *)ch->dma->work; 3593 3594 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 3595 3596 /* XXX SOS add ATAPI commands support later */ 3597 switch (request->u.ata.command) { 3598 default: 3599 return ata_generic_command(request); 3600 3601 case ATA_READ_DMA: 3602 case ATA_READ_DMA48: 3603 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3604 break; 3605 3606 case ATA_WRITE_DMA: 3607 case ATA_WRITE_DMA48: 3608 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3609 break; 3610 } 3611 wordp[1] = htole32(ch->dma->sg_bus); 3612 wordp[2] = 0; 3613 ata_promise_apkt((u_int8_t*)wordp, request); 3614 3615 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus); 3616 return 0; 3617 } 3618 3619 static void 3620 ata_promise_mio_reset(device_t dev) 3621 { 3622 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3623 struct ata_channel *ch = device_get_softc(dev); 3624 struct ata_promise_sx4 *hpktp; 3625 3626 switch (ctlr->chip->cfg2) { 3627 case PRSX4X: 3628 3629 /* softreset channel ATA module */ 3630 hpktp = device_get_ivars(ctlr->dev); 3631 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 3632 ata_udelay(1000); 3633 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 3634 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 3635 ~0x00003f9f) | (ch->unit + 1)); 3636 3637 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 3638 spin_lock_wr(&hpktp->mtx); 3639 ATA_OUTL(ctlr->r_res2, 0xc012c, 3640 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 3641 DELAY(10); 3642 ATA_OUTL(ctlr->r_res2, 0xc012c, 3643 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 3644 hpktp->busy = 0; 3645 spin_unlock_wr(&hpktp->mtx); 3646 ata_generic_reset(dev); 3647 break; 3648 3649 case PRPATA: 3650 case PRCMBO: 3651 case PRSATA: 3652 if ((ctlr->chip->cfg2 == PRSATA) || 3653 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 3654 3655 /* mask plug/unplug intr */ 3656 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 3657 } 3658 3659 /* softreset channels ATA module */ 3660 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 3661 ata_udelay(10000); 3662 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 3663 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 3664 ~0x00003f9f) | (ch->unit + 1)); 3665 3666 if ((ctlr->chip->cfg2 == PRSATA) || 3667 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 3668 3669 ata_sata_phy_enable(ch); 3670 3671 /* reset and enable plug/unplug intr */ 3672 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 3673 } 3674 else 3675 ata_generic_reset(dev); 3676 break; 3677 3678 case PRCMBO2: 3679 case PRSATA2: 3680 if ((ctlr->chip->cfg2 == PRSATA2) || 3681 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 3682 /* set portmultiplier port */ 3683 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 3684 3685 /* mask plug/unplug intr */ 3686 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 3687 } 3688 3689 /* softreset channels ATA module */ 3690 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 3691 ata_udelay(10000); 3692 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 3693 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 3694 ~0x00003f9f) | (ch->unit + 1)); 3695 3696 if ((ctlr->chip->cfg2 == PRSATA2) || 3697 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 3698 3699 /* set PHY mode to "improved" */ 3700 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 3701 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 3702 ~0x00000003) | 0x00000001); 3703 3704 ata_sata_phy_enable(ch); 3705 3706 /* reset and enable plug/unplug intr */ 3707 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 3708 3709 /* set portmultiplier port */ 3710 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 3711 } 3712 else 3713 ata_generic_reset(dev); 3714 break; 3715 3716 } 3717 } 3718 3719 static void 3720 ata_promise_mio_dmainit(device_t dev) 3721 { 3722 /* note start and stop are not used here */ 3723 ata_dmainit(dev); 3724 } 3725 3726 static void 3727 ata_promise_mio_setmode(device_t dev, int mode) 3728 { 3729 device_t gparent = GRANDPARENT(dev); 3730 struct ata_pci_controller *ctlr = device_get_softc(gparent); 3731 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3732 3733 if ( (ctlr->chip->cfg2 == PRSATA) || 3734 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) || 3735 (ctlr->chip->cfg2 == PRSATA2) || 3736 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) 3737 ata_sata_setmode(dev, mode); 3738 else 3739 ata_promise_setmode(dev, mode); 3740 } 3741 3742 static void 3743 ata_promise_sx4_intr(void *data) 3744 { 3745 struct ata_pci_controller *ctlr = data; 3746 struct ata_channel *ch; 3747 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 3748 int unit; 3749 3750 for (unit = 0; unit < ctlr->channels; unit++) { 3751 if (vector & (1 << (unit + 1))) 3752 if ((ch = ctlr->interrupt[unit].argument)) 3753 ctlr->interrupt[unit].function(ch); 3754 if (vector & (1 << (unit + 5))) 3755 if ((ch = ctlr->interrupt[unit].argument)) 3756 ata_promise_queue_hpkt(ctlr, 3757 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 3758 ATA_PDC_HPKT_OFFSET)); 3759 if (vector & (1 << (unit + 9))) { 3760 ata_promise_next_hpkt(ctlr); 3761 if ((ch = ctlr->interrupt[unit].argument)) 3762 ctlr->interrupt[unit].function(ch); 3763 } 3764 if (vector & (1 << (unit + 13))) { 3765 ata_promise_next_hpkt(ctlr); 3766 if ((ch = ctlr->interrupt[unit].argument)) 3767 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 3768 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 3769 ATA_PDC_APKT_OFFSET)); 3770 } 3771 } 3772 } 3773 3774 static int 3775 ata_promise_sx4_command(struct ata_request *request) 3776 { 3777 device_t gparent = GRANDPARENT(request->dev); 3778 struct ata_pci_controller *ctlr = device_get_softc(gparent); 3779 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 3780 struct ata_dma_prdentry *prd = ch->dma->sg; 3781 caddr_t window = rman_get_virtual(ctlr->r_res1); 3782 u_int32_t *wordp; 3783 int i, idx, length = 0; 3784 3785 /* XXX SOS add ATAPI commands support later */ 3786 switch (request->u.ata.command) { 3787 3788 default: 3789 return -1; 3790 3791 case ATA_ATA_IDENTIFY: 3792 case ATA_READ: 3793 case ATA_READ48: 3794 case ATA_READ_MUL: 3795 case ATA_READ_MUL48: 3796 case ATA_WRITE: 3797 case ATA_WRITE48: 3798 case ATA_WRITE_MUL: 3799 case ATA_WRITE_MUL48: 3800 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 3801 return ata_generic_command(request); 3802 3803 case ATA_SETFEATURES: 3804 case ATA_FLUSHCACHE: 3805 case ATA_FLUSHCACHE48: 3806 case ATA_SLEEP: 3807 case ATA_SET_MULTI: 3808 wordp = (u_int32_t *) 3809 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 3810 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 3811 wordp[1] = 0; 3812 wordp[2] = 0; 3813 ata_promise_apkt((u_int8_t *)wordp, request); 3814 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 3815 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 3816 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 3817 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 3818 return 0; 3819 3820 case ATA_READ_DMA: 3821 case ATA_READ_DMA48: 3822 case ATA_WRITE_DMA: 3823 case ATA_WRITE_DMA48: 3824 wordp = (u_int32_t *) 3825 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 3826 i = idx = 0; 3827 do { 3828 wordp[idx++] = prd[i].addr; 3829 wordp[idx++] = prd[i].count; 3830 length += (prd[i].count & ~ATA_DMA_EOT); 3831 } while (!(prd[i++].count & ATA_DMA_EOT)); 3832 3833 wordp = (u_int32_t *) 3834 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 3835 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 3836 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 3837 3838 wordp = (u_int32_t *) 3839 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 3840 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 3841 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 3842 3843 wordp = (u_int32_t *) 3844 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 3845 if (request->flags & ATA_R_READ) 3846 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 3847 if (request->flags & ATA_R_WRITE) 3848 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 3849 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 3850 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 3851 wordp[3] = 0; 3852 3853 wordp = (u_int32_t *) 3854 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 3855 if (request->flags & ATA_R_READ) 3856 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 3857 if (request->flags & ATA_R_WRITE) 3858 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 3859 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 3860 wordp[2] = 0; 3861 ata_promise_apkt((u_int8_t *)wordp, request); 3862 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 3863 3864 if (request->flags & ATA_R_READ) { 3865 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 3866 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 3867 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 3868 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 3869 } 3870 if (request->flags & ATA_R_WRITE) { 3871 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 3872 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 3873 ata_promise_queue_hpkt(ctlr, 3874 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 3875 } 3876 return 0; 3877 } 3878 } 3879 3880 static int 3881 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 3882 { 3883 struct ata_device *atadev = device_get_softc(request->dev); 3884 int i = 12; 3885 3886 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 3887 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit; 3888 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 3889 bytep[i++] = ATA_A_4BIT; 3890 3891 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3892 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 3893 bytep[i++] = request->u.ata.feature >> 8; 3894 bytep[i++] = request->u.ata.feature; 3895 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 3896 bytep[i++] = request->u.ata.count >> 8; 3897 bytep[i++] = request->u.ata.count; 3898 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 3899 bytep[i++] = request->u.ata.lba >> 24; 3900 bytep[i++] = request->u.ata.lba; 3901 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 3902 bytep[i++] = request->u.ata.lba >> 32; 3903 bytep[i++] = request->u.ata.lba >> 8; 3904 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 3905 bytep[i++] = request->u.ata.lba >> 40; 3906 bytep[i++] = request->u.ata.lba >> 16; 3907 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 3908 bytep[i++] = ATA_D_LBA | atadev->unit; 3909 } 3910 else { 3911 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 3912 bytep[i++] = request->u.ata.feature; 3913 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 3914 bytep[i++] = request->u.ata.count; 3915 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 3916 bytep[i++] = request->u.ata.lba; 3917 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 3918 bytep[i++] = request->u.ata.lba >> 8; 3919 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 3920 bytep[i++] = request->u.ata.lba >> 16; 3921 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 3922 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) | 3923 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf); 3924 } 3925 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 3926 bytep[i++] = request->u.ata.command; 3927 return i; 3928 } 3929 3930 static void 3931 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 3932 { 3933 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 3934 3935 spin_lock_wr(&hpktp->mtx); 3936 if (hpktp->busy) { 3937 struct host_packet *hp = 3938 kmalloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO); 3939 hp->addr = hpkt; 3940 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 3941 } 3942 else { 3943 hpktp->busy = 1; 3944 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 3945 } 3946 spin_unlock_wr(&hpktp->mtx); 3947 } 3948 3949 static void 3950 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 3951 { 3952 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 3953 struct host_packet *hp; 3954 3955 spin_lock_wr(&hpktp->mtx); 3956 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 3957 TAILQ_REMOVE(&hpktp->queue, hp, chain); 3958 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 3959 kfree(hp, M_TEMP); 3960 } 3961 else 3962 hpktp->busy = 0; 3963 spin_unlock_wr(&hpktp->mtx); 3964 } 3965 3966 3967 /* 3968 * ServerWorks chipset support functions 3969 */ 3970 int 3971 ata_serverworks_ident(device_t dev) 3972 { 3973 struct ata_pci_controller *ctlr = device_get_softc(dev); 3974 struct ata_chip_id *idx; 3975 static struct ata_chip_id ids[] = 3976 {{ ATA_ROSB4, 0x00, SWKS33, 0x00, ATA_UDMA2, "ROSB4" }, 3977 { ATA_CSB5, 0x92, SWKS100, 0x00, ATA_UDMA5, "CSB5" }, 3978 { ATA_CSB5, 0x00, SWKS66, 0x00, ATA_UDMA4, "CSB5" }, 3979 { ATA_CSB6, 0x00, SWKS100, 0x00, ATA_UDMA5, "CSB6" }, 3980 { ATA_CSB6_1, 0x00, SWKS66, 0x00, ATA_UDMA4, "CSB6" }, 3981 { ATA_HT1000, 0x00, SWKS100, 0x00, ATA_UDMA5, "HT1000" }, 3982 { ATA_HT1000_S1, 0x00, SWKS100, 0x00, ATA_SA150, "HT1000 SATA" }, 3983 { ATA_HT1000_S2, 0x00, SWKSMIO, 0x00, ATA_SA150, "HT1000 SATA mmio" }, 3984 { 0, 0, 0, 0, 0, 0}}; 3985 char buffer[64]; 3986 3987 if (!(idx = ata_match_chip(dev, ids))) 3988 return ENXIO; 3989 3990 ksprintf(buffer, "ServerWorks %s %s controller", 3991 idx->text, ata_mode2str(idx->max_dma)); 3992 device_set_desc_copy(dev, buffer); 3993 ctlr->chip = idx; 3994 ctlr->chipinit = ata_serverworks_chipinit; 3995 return 0; 3996 } 3997 3998 static int 3999 ata_serverworks_chipinit(device_t dev) 4000 { 4001 struct ata_pci_controller *ctlr = device_get_softc(dev); 4002 4003 if (ata_setup_interrupt(dev)) 4004 return ENXIO; 4005 4006 if (ctlr->chip->cfg1 == SWKSMIO) { 4007 ctlr->r_type2 = SYS_RES_MEMORY; 4008 ctlr->r_rid2 = PCIR_BAR(5); 4009 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4010 &ctlr->r_rid2, RF_ACTIVE))) 4011 return ENXIO; 4012 4013 ctlr->channels = 4; 4014 ctlr->allocate = ata_serverworks_allocate; 4015 ctlr->deallocate = ata_generic_nulldeallocate; 4016 ctlr->setmode = ata_sata_setmode; 4017 return 0; 4018 } 4019 else if (ctlr->chip->cfg1 == SWKS33) { 4020 device_t *children; 4021 int nchildren, i; 4022 4023 /* locate the ISA part in the southbridge and enable UDMA33 */ 4024 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 4025 for (i = 0; i < nchildren; i++) { 4026 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 4027 pci_write_config(children[i], 0x64, 4028 (pci_read_config(children[i], 0x64, 4) & 4029 ~0x00002000) | 0x00004000, 4); 4030 break; 4031 } 4032 } 4033 kfree(children, M_TEMP); 4034 } 4035 } 4036 else { 4037 pci_write_config(dev, 0x5a, 4038 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 4039 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1); 4040 } 4041 ctlr->setmode = ata_serverworks_setmode; 4042 return 0; 4043 } 4044 4045 static int 4046 ata_serverworks_allocate(device_t dev) 4047 { 4048 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4049 struct ata_channel *ch = device_get_softc(dev); 4050 int ch_offset; 4051 int i; 4052 4053 ch_offset = ch->unit * 0x100; 4054 4055 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 4056 ch->r_io[i].res = ctlr->r_res2; 4057 4058 /* setup ATA registers */ 4059 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 4060 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 4061 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 4062 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 4063 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 4064 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 4065 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 4066 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 4067 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 4068 ata_default_registers(dev); 4069 4070 /* setup DMA registers */ 4071 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 4072 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 4073 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 4074 4075 /* setup SATA registers */ 4076 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 4077 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 4078 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 4079 4080 ch->flags |= ATA_NO_SLAVE; 4081 ata_pci_hw(dev); 4082 return 0; 4083 } 4084 4085 static void 4086 ata_serverworks_setmode(device_t dev, int mode) 4087 { 4088 device_t gparent = GRANDPARENT(dev); 4089 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4090 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4091 struct ata_device *atadev = device_get_softc(dev); 4092 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4093 int offset = (devno ^ 0x01) << 3; 4094 int error; 4095 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 4096 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 4097 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 4098 4099 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4100 4101 mode = ata_check_80pin(dev, mode); 4102 4103 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4104 4105 if (bootverbose) 4106 device_printf(dev, "%ssetting %s on %s chip\n", 4107 (error) ? "FAILURE " : "", 4108 ata_mode2str(mode), ctlr->chip->text); 4109 if (!error) { 4110 if (mode >= ATA_UDMA0) { 4111 pci_write_config(gparent, 0x56, 4112 (pci_read_config(gparent, 0x56, 2) & 4113 ~(0xf << (devno << 2))) | 4114 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 4115 pci_write_config(gparent, 0x54, 4116 pci_read_config(gparent, 0x54, 1) | 4117 (0x01 << devno), 1); 4118 pci_write_config(gparent, 0x44, 4119 (pci_read_config(gparent, 0x44, 4) & 4120 ~(0xff << offset)) | 4121 (dmatimings[2] << offset), 4); 4122 } 4123 else if (mode >= ATA_WDMA0) { 4124 pci_write_config(gparent, 0x54, 4125 pci_read_config(gparent, 0x54, 1) & 4126 ~(0x01 << devno), 1); 4127 pci_write_config(gparent, 0x44, 4128 (pci_read_config(gparent, 0x44, 4) & 4129 ~(0xff << offset)) | 4130 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 4131 } 4132 else 4133 pci_write_config(gparent, 0x54, 4134 pci_read_config(gparent, 0x54, 1) & 4135 ~(0x01 << devno), 1); 4136 4137 pci_write_config(gparent, 0x40, 4138 (pci_read_config(gparent, 0x40, 4) & 4139 ~(0xff << offset)) | 4140 (piotimings[ata_mode2idx(mode)] << offset), 4); 4141 atadev->mode = mode; 4142 } 4143 } 4144 4145 4146 /* 4147 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 4148 */ 4149 int 4150 ata_sii_ident(device_t dev) 4151 { 4152 struct ata_pci_controller *ctlr = device_get_softc(dev); 4153 struct ata_chip_id *idx; 4154 static struct ata_chip_id ids[] = 4155 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" }, 4156 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" }, 4157 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4158 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4159 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" }, 4160 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4161 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4162 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" }, 4163 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" }, 4164 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" }, 4165 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" }, 4166 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" }, 4167 { 0, 0, 0, 0, 0, 0}}; 4168 char buffer[64]; 4169 4170 if (!(idx = ata_match_chip(dev, ids))) 4171 return ENXIO; 4172 4173 ksprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); 4174 device_set_desc_copy(dev, buffer); 4175 ctlr->chip = idx; 4176 ctlr->chipinit = ata_sii_chipinit; 4177 return 0; 4178 } 4179 4180 static int 4181 ata_sii_chipinit(device_t dev) 4182 { 4183 struct ata_pci_controller *ctlr = device_get_softc(dev); 4184 4185 if (ata_setup_interrupt(dev)) 4186 return ENXIO; 4187 4188 if (ctlr->chip->cfg1 == SIIMEMIO) { 4189 ctlr->r_type2 = SYS_RES_MEMORY; 4190 ctlr->r_rid2 = PCIR_BAR(5); 4191 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4192 &ctlr->r_rid2, RF_ACTIVE))) 4193 return ENXIO; 4194 4195 if (ctlr->chip->cfg2 & SIISETCLK) { 4196 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4197 pci_write_config(dev, 0x8a, 4198 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 4199 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4200 device_printf(dev, "%s could not set ATA133 clock\n", 4201 ctlr->chip->text); 4202 } 4203 4204 /* if we have 4 channels enable the second set */ 4205 if (ctlr->chip->cfg2 & SII4CH) { 4206 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 4207 ctlr->channels = 4; 4208 } 4209 4210 /* enable PCI interrupt as BIOS might not */ 4211 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 4212 4213 /* dont block interrupts from any channel */ 4214 pci_write_config(dev, 0x48, 4215 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 4216 4217 ctlr->allocate = ata_sii_allocate; 4218 ctlr->deallocate = ata_generic_nulldeallocate; 4219 if (ctlr->chip->max_dma >= ATA_SA150) { 4220 ctlr->reset = ata_sii_reset; 4221 ctlr->setmode = ata_sata_setmode; 4222 } 4223 else 4224 ctlr->setmode = ata_sii_setmode; 4225 } 4226 else { 4227 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 4228 device_printf(dev, "HW has secondary channel disabled\n"); 4229 ctlr->channels = 1; 4230 } 4231 4232 /* enable interrupt as BIOS might not */ 4233 pci_write_config(dev, 0x71, 0x01, 1); 4234 4235 ctlr->allocate = ata_cmd_allocate; 4236 ctlr->setmode = ata_cmd_setmode; 4237 } 4238 return 0; 4239 } 4240 4241 static int 4242 ata_cmd_allocate(device_t dev) 4243 { 4244 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4245 struct ata_channel *ch = device_get_softc(dev); 4246 4247 /* setup the usual register normal pci style */ 4248 if (ata_pci_allocate(dev)) 4249 return ENXIO; 4250 4251 if (ctlr->chip->cfg2 & SIIINTR) 4252 ch->hw.status = ata_cmd_status; 4253 4254 return 0; 4255 } 4256 4257 static int 4258 ata_cmd_status(device_t dev) 4259 { 4260 struct ata_channel *ch = device_get_softc(dev); 4261 u_int8_t reg71; 4262 4263 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) & 4264 (ch->unit ? 0x08 : 0x04))) { 4265 pci_write_config(device_get_parent(ch->dev), 0x71, 4266 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 4267 return ata_pci_status(dev); 4268 } 4269 return 0; 4270 } 4271 4272 static void 4273 ata_cmd_setmode(device_t dev, int mode) 4274 { 4275 device_t gparent = GRANDPARENT(dev); 4276 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4277 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4278 struct ata_device *atadev = device_get_softc(dev); 4279 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4280 int error; 4281 4282 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4283 4284 mode = ata_check_80pin(dev, mode); 4285 4286 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4287 4288 if (bootverbose) 4289 device_printf(dev, "%ssetting %s on %s chip\n", 4290 (error) ? "FAILURE " : "", 4291 ata_mode2str(mode), ctlr->chip->text); 4292 if (!error) { 4293 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 4294 int ureg = ch->unit ? 0x7b : 0x73; 4295 4296 if (mode >= ATA_UDMA0) { 4297 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 4298 { 0x11, 0x42 }, { 0x25, 0x8a }, 4299 { 0x15, 0x4a }, { 0x05, 0x0a } }; 4300 4301 u_int8_t umode = pci_read_config(gparent, ureg, 1); 4302 4303 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca); 4304 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)]; 4305 pci_write_config(gparent, ureg, umode, 1); 4306 } 4307 else if (mode >= ATA_WDMA0) { 4308 int dmatimings[] = { 0x87, 0x32, 0x3f }; 4309 4310 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1); 4311 pci_write_config(gparent, ureg, 4312 pci_read_config(gparent, ureg, 1) & 4313 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4314 } 4315 else { 4316 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f }; 4317 pci_write_config(gparent, treg, 4318 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1); 4319 pci_write_config(gparent, ureg, 4320 pci_read_config(gparent, ureg, 1) & 4321 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4322 } 4323 atadev->mode = mode; 4324 } 4325 } 4326 4327 static int 4328 ata_sii_allocate(device_t dev) 4329 { 4330 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4331 struct ata_channel *ch = device_get_softc(dev); 4332 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 4333 int i; 4334 4335 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 4336 ch->r_io[i].res = ctlr->r_res2; 4337 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 4338 } 4339 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 4340 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 4341 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 4342 ata_default_registers(dev); 4343 4344 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 4345 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 4346 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 4347 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 4348 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 4349 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 4350 ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_res2; 4351 ch->r_io[ATA_BMDEVSPEC_0].offset = 0xa1 + (unit01 << 6) + (unit10 << 8); 4352 4353 if (ctlr->chip->max_dma >= ATA_SA150) { 4354 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4355 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 4356 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4357 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 4358 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4359 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 4360 ch->flags |= ATA_NO_SLAVE; 4361 4362 /* enable PHY state change interrupt */ 4363 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 4364 } 4365 4366 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) { 4367 /* work around errata in early chips */ 4368 ch->dma->boundary = 16 * DEV_BSIZE; 4369 ch->dma->segsize = 15 * DEV_BSIZE; 4370 } 4371 4372 ata_pci_hw(dev); 4373 ch->hw.status = ata_sii_status; 4374 return 0; 4375 } 4376 4377 static int 4378 ata_sii_status(device_t dev) 4379 { 4380 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4381 struct ata_channel *ch = device_get_softc(dev); 4382 4383 /* check for PHY related interrupts on SATA capable HW */ 4384 if (ctlr->chip->max_dma >= ATA_SA150) { 4385 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS); 4386 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR); 4387 struct ata_connect_task *tp; 4388 4389 if (error) { 4390 /* clear error bits/interrupt */ 4391 ATA_IDX_OUTL(ch, ATA_SERROR, error); 4392 4393 /* if we have a connection event deal with it */ 4394 if ((error & ATA_SE_PHY_CHANGED) && 4395 (tp = (struct ata_connect_task *) 4396 kmalloc(sizeof(struct ata_connect_task), 4397 M_ATA, M_NOWAIT | M_ZERO))) { 4398 4399 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) { 4400 if (bootverbose) 4401 device_printf(ch->dev, "CONNECT requested\n"); 4402 tp->action = ATA_C_ATTACH; 4403 } 4404 else { 4405 if (bootverbose) 4406 device_printf(ch->dev, "DISCONNECT requested\n"); 4407 tp->action = ATA_C_DETACH; 4408 } 4409 tp->dev = ch->dev; 4410 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 4411 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 4412 } 4413 } 4414 } 4415 4416 /* any drive action to take care of ? */ 4417 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x08) 4418 return ata_pci_status(dev); 4419 else 4420 return 0; 4421 } 4422 4423 static void 4424 ata_sii_reset(device_t dev) 4425 { 4426 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4427 struct ata_channel *ch = device_get_softc(dev); 4428 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8); 4429 4430 /* disable PHY state change interrupt */ 4431 ATA_OUTL(ctlr->r_res2, 0x148 + offset, ~(1 << 16)); 4432 4433 /* reset controller part for this channel */ 4434 ATA_OUTL(ctlr->r_res2, 0x48, 4435 ATA_INL(ctlr->r_res2, 0x48) | (0xc0 >> ch->unit)); 4436 DELAY(1000); 4437 ATA_OUTL(ctlr->r_res2, 0x48, 4438 ATA_INL(ctlr->r_res2, 0x48) & ~(0xc0 >> ch->unit)); 4439 4440 ata_sata_phy_enable(ch); 4441 4442 /* enable PHY state change interrupt */ 4443 ATA_OUTL(ctlr->r_res2, 0x148 + offset, (1 << 16)); 4444 } 4445 4446 static void 4447 ata_sii_setmode(device_t dev, int mode) 4448 { 4449 device_t gparent = GRANDPARENT(dev); 4450 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4451 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4452 struct ata_device *atadev = device_get_softc(dev); 4453 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1); 4454 int mreg = ch->unit ? 0x84 : 0x80; 4455 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2); 4456 int mval = pci_read_config(gparent, mreg, 1) & ~mask; 4457 int error; 4458 4459 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4460 4461 if (ctlr->chip->cfg2 & SIISETCLK) { 4462 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) & 4463 (ch->unit ? 0x02 : 0x01))) { 4464 ata_print_cable(dev, "controller"); 4465 mode = ATA_UDMA2; 4466 } 4467 } 4468 else 4469 mode = ata_check_80pin(dev, mode); 4470 4471 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4472 4473 if (bootverbose) 4474 device_printf(dev, "%ssetting %s on %s chip\n", 4475 (error) ? "FAILURE " : "", 4476 ata_mode2str(mode), ctlr->chip->text); 4477 if (error) 4478 return; 4479 4480 if (mode >= ATA_UDMA0) { 4481 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 4482 u_int8_t ureg = 0xac + rego; 4483 4484 pci_write_config(gparent, mreg, 4485 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1); 4486 pci_write_config(gparent, ureg, 4487 (pci_read_config(gparent, ureg, 1) & ~0x3f) | 4488 udmatimings[mode & ATA_MODE_MASK], 1); 4489 4490 } 4491 else if (mode >= ATA_WDMA0) { 4492 u_int8_t dreg = 0xa8 + rego; 4493 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 4494 4495 pci_write_config(gparent, mreg, 4496 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1); 4497 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 4498 4499 } 4500 else { 4501 u_int8_t preg = 0xa4 + rego; 4502 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 4503 4504 pci_write_config(gparent, mreg, 4505 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1); 4506 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2); 4507 } 4508 atadev->mode = mode; 4509 } 4510 4511 4512 /* 4513 * Silicon Integrated Systems Corp. (SiS) chipset support functions 4514 */ 4515 int 4516 ata_sis_ident(device_t dev) 4517 { 4518 struct ata_pci_controller *ctlr = device_get_softc(dev); 4519 struct ata_chip_id *idx; 4520 static struct ata_chip_id ids[] = 4521 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */ 4522 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */ 4523 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */ 4524 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */ 4525 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */ 4526 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */ 4527 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */ 4528 4529 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */ 4530 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */ 4531 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */ 4532 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */ 4533 4534 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */ 4535 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */ 4536 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */ 4537 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */ 4538 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */ 4539 4540 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" }, 4541 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" }, 4542 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" }, 4543 4544 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" }, 4545 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" }, 4546 { 0, 0, 0, 0, 0, 0 }}; 4547 char buffer[64]; 4548 int found = 0; 4549 4550 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev)))) 4551 return ENXIO; 4552 4553 if (idx->cfg2 && !found) { 4554 u_int8_t reg57 = pci_read_config(dev, 0x57, 1); 4555 4556 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1); 4557 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) { 4558 found = 1; 4559 idx->cfg1 = SIS133NEW; 4560 idx->max_dma = ATA_UDMA6; 4561 ksprintf(buffer, "SiS 962/963 %s controller", 4562 ata_mode2str(idx->max_dma)); 4563 } 4564 pci_write_config(dev, 0x57, reg57, 1); 4565 } 4566 if (idx->cfg2 && !found) { 4567 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1); 4568 4569 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1); 4570 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) { 4571 struct ata_chip_id id[] = 4572 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }}; 4573 4574 found = 1; 4575 if (ata_find_chip(dev, id, pci_get_slot(dev))) { 4576 idx->cfg1 = SIS133OLD; 4577 idx->max_dma = ATA_UDMA6; 4578 } 4579 else { 4580 idx->cfg1 = SIS100NEW; 4581 idx->max_dma = ATA_UDMA5; 4582 } 4583 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma)); 4584 } 4585 pci_write_config(dev, 0x4a, reg4a, 1); 4586 } 4587 if (!found) 4588 ksprintf(buffer,"SiS %s %s controller", 4589 idx->text, ata_mode2str(idx->max_dma)); 4590 4591 device_set_desc_copy(dev, buffer); 4592 ctlr->chip = idx; 4593 ctlr->chipinit = ata_sis_chipinit; 4594 return 0; 4595 } 4596 4597 static int 4598 ata_sis_chipinit(device_t dev) 4599 { 4600 struct ata_pci_controller *ctlr = device_get_softc(dev); 4601 4602 if (ata_setup_interrupt(dev)) 4603 return ENXIO; 4604 4605 switch (ctlr->chip->cfg1) { 4606 case SIS33: 4607 break; 4608 case SIS66: 4609 case SIS100OLD: 4610 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1); 4611 break; 4612 case SIS100NEW: 4613 case SIS133OLD: 4614 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1); 4615 break; 4616 case SIS133NEW: 4617 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2); 4618 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2); 4619 break; 4620 case SISSATA: 4621 ctlr->r_type2 = SYS_RES_IOPORT; 4622 ctlr->r_rid2 = PCIR_BAR(5); 4623 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4624 &ctlr->r_rid2, RF_ACTIVE))) { 4625 ctlr->allocate = ata_sis_allocate; 4626 ctlr->reset = ata_sis_reset; 4627 4628 /* enable PCI interrupt */ 4629 pci_write_config(dev, PCIR_COMMAND, 4630 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 4631 } 4632 ctlr->setmode = ata_sata_setmode; 4633 return 0; 4634 default: 4635 return ENXIO; 4636 } 4637 ctlr->setmode = ata_sis_setmode; 4638 return 0; 4639 } 4640 4641 static int 4642 ata_sis_allocate(device_t dev) 4643 { 4644 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4645 struct ata_channel *ch = device_get_softc(dev); 4646 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6); 4647 4648 /* setup the usual register normal pci style */ 4649 if (ata_pci_allocate(dev)) 4650 return ENXIO; 4651 4652 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4653 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; 4654 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4655 ch->r_io[ATA_SERROR].offset = 0x04 + offset; 4656 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4657 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; 4658 ch->flags |= ATA_NO_SLAVE; 4659 4660 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ 4661 /* XXX SOS unknown how to enable PHY state change interrupt */ 4662 return 0; 4663 } 4664 4665 static void 4666 ata_sis_reset(device_t dev) 4667 { 4668 struct ata_channel *ch = device_get_softc(dev); 4669 4670 ata_sata_phy_enable(ch); 4671 } 4672 4673 4674 static void 4675 ata_sis_setmode(device_t dev, int mode) 4676 { 4677 device_t gparent = GRANDPARENT(dev); 4678 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4679 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4680 struct ata_device *atadev = device_get_softc(dev); 4681 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4682 int error; 4683 4684 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4685 4686 if (ctlr->chip->cfg1 == SIS133NEW) { 4687 if (mode > ATA_UDMA2 && 4688 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) { 4689 ata_print_cable(dev, "controller"); 4690 mode = ATA_UDMA2; 4691 } 4692 } 4693 else { 4694 if (mode > ATA_UDMA2 && 4695 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) { 4696 ata_print_cable(dev, "controller"); 4697 mode = ATA_UDMA2; 4698 } 4699 } 4700 4701 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4702 4703 if (bootverbose) 4704 device_printf(dev, "%ssetting %s on %s chip\n", 4705 (error) ? "FAILURE " : "", 4706 ata_mode2str(mode), ctlr->chip->text); 4707 if (!error) { 4708 switch (ctlr->chip->cfg1) { 4709 case SIS133NEW: { 4710 u_int32_t timings[] = 4711 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 4712 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 4713 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; 4714 u_int32_t reg; 4715 4716 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); 4717 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4); 4718 break; 4719 } 4720 case SIS133OLD: { 4721 u_int16_t timings[] = 4722 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 4723 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; 4724 4725 u_int16_t reg = 0x40 + (devno << 1); 4726 4727 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 4728 break; 4729 } 4730 case SIS100NEW: { 4731 u_int16_t timings[] = 4732 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 4733 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; 4734 u_int16_t reg = 0x40 + (devno << 1); 4735 4736 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 4737 break; 4738 } 4739 case SIS100OLD: 4740 case SIS66: 4741 case SIS33: { 4742 u_int16_t timings[] = 4743 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 4744 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; 4745 u_int16_t reg = 0x40 + (devno << 1); 4746 4747 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 4748 break; 4749 } 4750 } 4751 atadev->mode = mode; 4752 } 4753 } 4754 4755 4756 /* VIA Technologies Inc. chipset support functions */ 4757 int 4758 ata_via_ident(device_t dev) 4759 { 4760 struct ata_pci_controller *ctlr = device_get_softc(dev); 4761 struct ata_chip_id *idx; 4762 static struct ata_chip_id ids[] = 4763 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 4764 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 4765 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 4766 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 4767 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 4768 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 4769 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 4770 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 4771 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 4772 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 4773 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 4774 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 4775 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 4776 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 4777 { 0, 0, 0, 0, 0, 0 }}; 4778 static struct ata_chip_id new_ids[] = 4779 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 4780 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 4781 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 4782 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" }, 4783 { 0, 0, 0, 0, 0, 0 }}; 4784 char buffer[64]; 4785 4786 if (pci_get_devid(dev) == ATA_VIA82C571) { 4787 if (!(idx = ata_find_chip(dev, ids, -99))) 4788 return ENXIO; 4789 } 4790 else { 4791 if (!(idx = ata_match_chip(dev, new_ids))) 4792 return ENXIO; 4793 } 4794 4795 ksprintf(buffer, "VIA %s %s controller", 4796 idx->text, ata_mode2str(idx->max_dma)); 4797 device_set_desc_copy(dev, buffer); 4798 ctlr->chip = idx; 4799 ctlr->chipinit = ata_via_chipinit; 4800 return 0; 4801 } 4802 4803 static int 4804 ata_via_chipinit(device_t dev) 4805 { 4806 struct ata_pci_controller *ctlr = device_get_softc(dev); 4807 4808 if (ata_setup_interrupt(dev)) 4809 return ENXIO; 4810 4811 if (ctlr->chip->max_dma >= ATA_SA150) { 4812 if (ctlr->chip->cfg2 == VIAAHCI) { 4813 ctlr->r_type2 = SYS_RES_MEMORY; 4814 ctlr->r_rid2 = PCIR_BAR(5); 4815 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4816 &ctlr->r_rid2, 4817 RF_ACTIVE))) { 4818 return ata_ahci_chipinit(dev); 4819 } 4820 } 4821 ctlr->r_type2 = SYS_RES_IOPORT; 4822 ctlr->r_rid2 = PCIR_BAR(5); 4823 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4824 &ctlr->r_rid2, RF_ACTIVE))) { 4825 ctlr->allocate = ata_via_allocate; 4826 ctlr->deallocate = ata_via_deallocate; 4827 ctlr->reset = ata_via_reset; 4828 4829 /* enable PCI interrupt */ 4830 pci_write_config(dev, PCIR_COMMAND, 4831 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 4832 } 4833 ctlr->setmode = ata_sata_setmode; 4834 return 0; 4835 } 4836 4837 /* prepare for ATA-66 on the 82C686a and 82C596b */ 4838 if (ctlr->chip->cfg2 & VIACLK) 4839 pci_write_config(dev, 0x50, 0x030b030b, 4); 4840 4841 /* the southbridge might need the data corruption fix */ 4842 if (ctlr->chip->cfg2 & VIABUG) 4843 ata_via_southbridge_fixup(dev); 4844 4845 /* set fifo configuration half'n'half */ 4846 pci_write_config(dev, 0x43, 4847 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 4848 4849 /* set status register read retry */ 4850 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 4851 4852 /* set DMA read & end-of-sector fifo flush */ 4853 pci_write_config(dev, 0x46, 4854 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 4855 4856 /* set sector size */ 4857 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 4858 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 4859 4860 ctlr->setmode = ata_via_family_setmode; 4861 return 0; 4862 } 4863 4864 static int 4865 ata_via_allocate(device_t dev) 4866 { 4867 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4868 struct ata_channel *ch = device_get_softc(dev); 4869 4870 /* newer SATA chips has resources in one BAR for each channel */ 4871 if (ctlr->chip->cfg2 & VIABAR) { 4872 struct resource *r_io; 4873 int i, rid; 4874 4875 rid = PCIR_BAR(ch->unit); 4876 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 4877 SYS_RES_IOPORT, 4878 &rid, RF_ACTIVE))) 4879 return ENXIO; 4880 4881 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 4882 ch->r_io[i].res = r_io; 4883 ch->r_io[i].offset = i; 4884 } 4885 ch->r_io[ATA_CONTROL].res = r_io; 4886 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 4887 ch->r_io[ATA_IDX_ADDR].res = r_io; 4888 ata_default_registers(dev); 4889 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 4890 ch->r_io[i].res = ctlr->r_res1; 4891 ch->r_io[i].offset = i - ATA_BMCMD_PORT; 4892 } 4893 ata_pci_hw(dev); 4894 } 4895 else { 4896 /* setup the usual register normal pci style */ 4897 if (ata_pci_allocate(dev)) 4898 return ENXIO; 4899 } 4900 4901 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4902 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 4903 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4904 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 4905 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4906 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 4907 ch->flags |= ATA_NO_SLAVE; 4908 4909 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */ 4910 /* XXX SOS unknown how to enable PHY state change interrupt */ 4911 return 0; 4912 } 4913 4914 /* 4915 * Deallocate resources that have been allocated for the ATA channel. 4916 */ 4917 static int 4918 ata_via_deallocate(device_t dev) 4919 { 4920 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4921 struct ata_channel *ch = device_get_softc(dev); 4922 4923 if (ctlr->chip->cfg2 & VIABAR) { 4924 if (ch->r_io[ATA_CONTROL].res) 4925 bus_release_resource(device_get_parent(dev), SYS_RES_IOPORT, 4926 PCIR_BAR(ch->unit), 4927 ch->r_io[ATA_CONTROL].res); 4928 return 0; 4929 } else 4930 return ata_pci_deallocate(dev); 4931 } 4932 4933 static void 4934 ata_via_reset(device_t dev) 4935 { 4936 struct ata_channel *ch = device_get_softc(dev); 4937 4938 ata_sata_phy_enable(ch); 4939 } 4940 4941 static void 4942 ata_via_southbridge_fixup(device_t dev) 4943 { 4944 device_t *children; 4945 int nchildren, i; 4946 4947 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 4948 return; 4949 4950 for (i = 0; i < nchildren; i++) { 4951 if (pci_get_devid(children[i]) == ATA_VIA8363 || 4952 pci_get_devid(children[i]) == ATA_VIA8371 || 4953 pci_get_devid(children[i]) == ATA_VIA8662 || 4954 pci_get_devid(children[i]) == ATA_VIA8361) { 4955 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 4956 4957 if ((reg76 & 0xf0) != 0xd0) { 4958 device_printf(dev, 4959 "Correcting VIA config for southbridge data corruption bug\n"); 4960 pci_write_config(children[i], 0x75, 0x80, 1); 4961 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 4962 } 4963 break; 4964 } 4965 } 4966 kfree(children, M_TEMP); 4967 } 4968 4969 4970 /* common code for VIA, AMD & nVidia */ 4971 static void 4972 ata_via_family_setmode(device_t dev, int mode) 4973 { 4974 device_t gparent = GRANDPARENT(dev); 4975 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4976 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4977 struct ata_device *atadev = device_get_softc(dev); 4978 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20, 4979 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 4980 int modes[][7] = { 4981 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 4982 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 4983 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 4984 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */ 4985 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */ 4986 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4987 int reg = 0x53 - devno; 4988 int error; 4989 4990 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4991 4992 if (ctlr->chip->cfg2 & AMDCABLE) { 4993 if (mode > ATA_UDMA2 && 4994 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) { 4995 ata_print_cable(dev, "controller"); 4996 mode = ATA_UDMA2; 4997 } 4998 } 4999 else 5000 mode = ata_check_80pin(dev, mode); 5001 5002 if (ctlr->chip->cfg2 & NVIDIA) 5003 reg += 0x10; 5004 5005 if (ctlr->chip->cfg1 != VIA133) 5006 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1); 5007 5008 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5009 5010 if (bootverbose) 5011 device_printf(dev, "%ssetting %s on %s chip\n", 5012 (error) ? "FAILURE " : "", ata_mode2str(mode), 5013 ctlr->chip->text); 5014 if (!error) { 5015 if (mode >= ATA_UDMA0) 5016 pci_write_config(gparent, reg, 5017 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 5018 else 5019 pci_write_config(gparent, reg, 0x8b, 1); 5020 atadev->mode = mode; 5021 } 5022 } 5023 5024 5025 /* misc functions */ 5026 static struct ata_chip_id * 5027 ata_match_chip(device_t dev, struct ata_chip_id *index) 5028 { 5029 while (index->chipid != 0) { 5030 if (pci_get_devid(dev) == index->chipid && 5031 pci_get_revid(dev) >= index->chiprev) 5032 return index; 5033 index++; 5034 } 5035 return NULL; 5036 } 5037 5038 static struct ata_chip_id * 5039 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot) 5040 { 5041 device_t *children; 5042 int nchildren, i; 5043 5044 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5045 return 0; 5046 5047 while (index->chipid != 0) { 5048 for (i = 0; i < nchildren; i++) { 5049 if (((slot >= 0 && pci_get_slot(children[i]) == slot) || 5050 (slot < 0 && pci_get_slot(children[i]) <= -slot)) && 5051 pci_get_devid(children[i]) == index->chipid && 5052 pci_get_revid(children[i]) >= index->chiprev) { 5053 kfree(children, M_TEMP); 5054 return index; 5055 } 5056 } 5057 index++; 5058 } 5059 kfree(children, M_TEMP); 5060 return NULL; 5061 } 5062 5063 static int 5064 ata_setup_interrupt(device_t dev) 5065 { 5066 struct ata_pci_controller *ctlr = device_get_softc(dev); 5067 int rid = ATA_IRQ_RID; 5068 5069 if (!ata_legacy(dev)) { 5070 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 5071 RF_SHAREABLE | RF_ACTIVE))) { 5072 device_printf(dev, "unable to map interrupt\n"); 5073 return ENXIO; 5074 } 5075 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 5076 ata_generic_intr, ctlr, &ctlr->handle, NULL))) { 5077 device_printf(dev, "unable to setup interrupt\n"); 5078 return ENXIO; 5079 } 5080 } 5081 return 0; 5082 } 5083 5084 struct ata_serialize { 5085 struct spinlock locked_mtx; 5086 int locked_ch; 5087 int restart_ch; 5088 }; 5089 5090 static int 5091 ata_serialize(device_t dev, int flags) 5092 { 5093 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5094 struct ata_channel *ch = device_get_softc(dev); 5095 struct ata_serialize *serial; 5096 static int inited = 0; 5097 int res; 5098 5099 if (!inited) { 5100 serial = kmalloc(sizeof(struct ata_serialize), 5101 M_TEMP, M_NOWAIT | M_ZERO); 5102 spin_init(&serial->locked_mtx); 5103 serial->locked_ch = -1; 5104 serial->restart_ch = -1; 5105 device_set_ivars(ctlr->dev, serial); 5106 inited = 1; 5107 } 5108 else 5109 serial = device_get_ivars(ctlr->dev); 5110 5111 spin_lock_wr(&serial->locked_mtx); 5112 switch (flags) { 5113 case ATA_LF_LOCK: 5114 if (serial->locked_ch == -1) 5115 serial->locked_ch = ch->unit; 5116 if (serial->locked_ch != ch->unit) 5117 serial->restart_ch = ch->unit; 5118 break; 5119 5120 case ATA_LF_UNLOCK: 5121 if (serial->locked_ch == ch->unit) { 5122 serial->locked_ch = -1; 5123 if (serial->restart_ch != -1) { 5124 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) { 5125 serial->restart_ch = -1; 5126 spin_unlock_wr(&serial->locked_mtx); 5127 ata_start(ch->dev); 5128 return -1; 5129 } 5130 } 5131 } 5132 break; 5133 5134 case ATA_LF_WHICH: 5135 break; 5136 } 5137 res = serial->locked_ch; 5138 spin_unlock_wr(&serial->locked_mtx); 5139 return res; 5140 } 5141 5142 static void 5143 ata_print_cable(device_t dev, u_int8_t *who) 5144 { 5145 device_printf(dev, 5146 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who); 5147 } 5148 5149 static int 5150 ata_atapi(device_t dev) 5151 { 5152 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5153 struct ata_device *atadev = device_get_softc(dev); 5154 5155 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || 5156 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE)); 5157 } 5158 5159 static int 5160 ata_check_80pin(device_t dev, int mode) 5161 { 5162 struct ata_device *atadev = device_get_softc(dev); 5163 5164 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) { 5165 ata_print_cable(dev, "device"); 5166 mode = ATA_UDMA2; 5167 } 5168 return mode; 5169 } 5170 5171 static int 5172 ata_mode2idx(int mode) 5173 { 5174 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) 5175 return (mode & ATA_MODE_MASK) + 8; 5176 if ((mode & ATA_DMA_MASK) == ATA_WDMA0) 5177 return (mode & ATA_MODE_MASK) + 5; 5178 return (mode & ATA_MODE_MASK) - ATA_PIO0; 5179 } 5180