1 /*- 2 * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.196 2007/04/08 19:18:51 sos Exp $ 27 */ 28 29 #include "opt_ata.h" 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/bus_dma.h> 34 #include <sys/bus_resource.h> 35 #include <sys/callout.h> 36 #include <sys/endian.h> 37 #include <sys/libkern.h> 38 #include <sys/lock.h> /* for {get,rel}_mplock() */ 39 #include <sys/malloc.h> 40 #include <sys/nata.h> 41 #include <sys/queue.h> 42 #include <sys/rman.h> 43 #include <sys/systm.h> 44 #include <sys/taskqueue.h> 45 #include <sys/machintr.h> 46 47 #include <sys/mplock2.h> 48 49 #include <machine/bus_dma.h> 50 51 #include <bus/pci/pcireg.h> 52 #include <bus/pci/pcivar.h> 53 54 #include "ata-all.h" 55 #include "ata-pci.h" 56 #include "ata_if.h" 57 58 /* local prototypes */ 59 /* ata-chipset.c */ 60 static int ata_generic_chipinit(device_t dev); 61 static void ata_generic_intr(void *data); 62 static void ata_generic_setmode(device_t dev, int mode); 63 static void ata_sata_phy_check_events(device_t dev); 64 static void ata_sata_phy_event(void *context, int dummy); 65 static int ata_sata_phy_reset(device_t dev); 66 static int ata_sata_connect(struct ata_channel *ch); 67 static void ata_sata_setmode(device_t dev, int mode); 68 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); 69 static int ata_ahci_chipinit(device_t dev); 70 static int ata_ahci_allocate(device_t dev); 71 static int ata_ahci_status(device_t dev); 72 static int ata_ahci_begin_transaction(struct ata_request *request); 73 static int ata_ahci_end_transaction(struct ata_request *request); 74 static void ata_ahci_reset(device_t dev); 75 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 76 static void ata_ahci_dmainit(device_t dev); 77 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request); 78 static int ata_acard_chipinit(device_t dev); 79 static int ata_acard_allocate(device_t dev); 80 static int ata_acard_status(device_t dev); 81 static void ata_acard_850_setmode(device_t dev, int mode); 82 static void ata_acard_86X_setmode(device_t dev, int mode); 83 static int ata_ali_chipinit(device_t dev); 84 static int ata_ali_allocate(device_t dev); 85 static int ata_ali_sata_allocate(device_t dev); 86 static void ata_ali_reset(device_t dev); 87 static void ata_ali_setmode(device_t dev, int mode); 88 static int ata_amd_chipinit(device_t dev); 89 static int ata_ati_chipinit(device_t dev); 90 static void ata_ati_setmode(device_t dev, int mode); 91 static int ata_cyrix_chipinit(device_t dev); 92 static void ata_cyrix_setmode(device_t dev, int mode); 93 static int ata_cypress_chipinit(device_t dev); 94 static void ata_cypress_setmode(device_t dev, int mode); 95 static int ata_highpoint_chipinit(device_t dev); 96 static int ata_highpoint_allocate(device_t dev); 97 static void ata_highpoint_setmode(device_t dev, int mode); 98 static int ata_highpoint_check_80pin(device_t dev, int mode); 99 static int ata_intel_chipinit(device_t dev); 100 static int ata_intel_allocate(device_t dev); 101 static void ata_intel_reset(device_t dev); 102 static void ata_intel_old_setmode(device_t dev, int mode); 103 static void ata_intel_new_setmode(device_t dev, int mode); 104 static void ata_intel_sata_setmode(device_t dev, int mode); 105 static int ata_intel_31244_allocate(device_t dev); 106 static int ata_intel_31244_status(device_t dev); 107 static int ata_intel_31244_command(struct ata_request *request); 108 static void ata_intel_31244_reset(device_t dev); 109 static int ata_ite_chipinit(device_t dev); 110 static void ata_ite_setmode(device_t dev, int mode); 111 static int ata_jmicron_chipinit(device_t dev); 112 static int ata_jmicron_allocate(device_t dev); 113 static void ata_jmicron_reset(device_t dev); 114 static void ata_jmicron_dmainit(device_t dev); 115 static void ata_jmicron_setmode(device_t dev, int mode); 116 static int ata_marvell_pata_chipinit(device_t dev); 117 static int ata_marvell_pata_allocate(device_t dev); 118 static void ata_marvell_pata_setmode(device_t dev, int mode); 119 static int ata_marvell_edma_chipinit(device_t dev); 120 static int ata_marvell_edma_allocate(device_t dev); 121 static int ata_marvell_edma_status(device_t dev); 122 static int ata_marvell_edma_begin_transaction(struct ata_request *request); 123 static int ata_marvell_edma_end_transaction(struct ata_request *request); 124 static void ata_marvell_edma_reset(device_t dev); 125 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 126 static void ata_marvell_edma_dmainit(device_t dev); 127 static int ata_national_chipinit(device_t dev); 128 static void ata_national_setmode(device_t dev, int mode); 129 static int ata_netcell_chipinit(device_t dev); 130 static int ata_netcell_allocate(device_t dev); 131 static int ata_nvidia_chipinit(device_t dev); 132 static int ata_nvidia_allocate(device_t dev); 133 static int ata_nvidia_status(device_t dev); 134 static void ata_nvidia_reset(device_t dev); 135 static int ata_promise_chipinit(device_t dev); 136 static int ata_promise_allocate(device_t dev); 137 static int ata_promise_status(device_t dev); 138 static int ata_promise_dmastart(device_t dev); 139 static int ata_promise_dmastop(device_t dev); 140 static void ata_promise_dmareset(device_t dev); 141 static void ata_promise_dmainit(device_t dev); 142 static void ata_promise_setmode(device_t dev, int mode); 143 static int ata_promise_tx2_allocate(device_t dev); 144 static int ata_promise_tx2_status(device_t dev); 145 static int ata_promise_mio_allocate(device_t dev); 146 static void ata_promise_mio_intr(void *data); 147 static int ata_promise_mio_status(device_t dev); 148 static int ata_promise_mio_command(struct ata_request *request); 149 static void ata_promise_mio_reset(device_t dev); 150 static void ata_promise_mio_dmainit(device_t dev); 151 static void ata_promise_mio_setmode(device_t dev, int mode); 152 static void ata_promise_sx4_intr(void *data); 153 static int ata_promise_sx4_command(struct ata_request *request); 154 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 155 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 156 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 157 static int ata_serverworks_chipinit(device_t dev); 158 static int ata_serverworks_allocate(device_t dev); 159 static void ata_serverworks_setmode(device_t dev, int mode); 160 static int ata_sii_chipinit(device_t dev); 161 static int ata_cmd_allocate(device_t dev); 162 static int ata_cmd_status(device_t dev); 163 static void ata_cmd_setmode(device_t dev, int mode); 164 static int ata_sii_allocate(device_t dev); 165 static int ata_sii_status(device_t dev); 166 static void ata_sii_reset(device_t dev); 167 static void ata_sii_setmode(device_t dev, int mode); 168 static int ata_siiprb_allocate(device_t dev); 169 static int ata_siiprb_status(device_t dev); 170 static int ata_siiprb_begin_transaction(struct ata_request *request); 171 static int ata_siiprb_end_transaction(struct ata_request *request); 172 static void ata_siiprb_reset(device_t dev); 173 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 174 static void ata_siiprb_dmainit(device_t dev); 175 static int ata_sis_chipinit(device_t dev); 176 static int ata_sis_allocate(device_t dev); 177 static void ata_sis_reset(device_t dev); 178 static void ata_sis_setmode(device_t dev, int mode); 179 static int ata_via_chipinit(device_t dev); 180 static int ata_via_allocate(device_t dev); 181 static void ata_via_reset(device_t dev); 182 static void ata_via_setmode(device_t dev, int mode); 183 static void ata_via_southbridge_fixup(device_t dev); 184 static void ata_via_family_setmode(device_t dev, int mode); 185 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index); 186 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot); 187 static int ata_setup_interrupt(device_t dev); 188 static void ata_teardown_interrupt(device_t dev); 189 static int ata_serialize(device_t dev, int flags); 190 static void ata_print_cable(device_t dev, u_int8_t *who); 191 static int ata_atapi(device_t dev); 192 static int ata_check_80pin(device_t dev, int mode); 193 static int ata_mode2idx(int mode); 194 195 196 /* 197 * generic ATA support functions 198 */ 199 int 200 ata_generic_ident(device_t dev) 201 { 202 struct ata_pci_controller *ctlr = device_get_softc(dev); 203 char buffer[64]; 204 205 ksnprintf(buffer, sizeof(buffer), 206 "%s ATA controller", ata_pcivendor2str(dev)); 207 device_set_desc_copy(dev, buffer); 208 ctlr->chipinit = ata_generic_chipinit; 209 return 0; 210 } 211 212 static int 213 ata_generic_chipinit(device_t dev) 214 { 215 struct ata_pci_controller *ctlr = device_get_softc(dev); 216 217 if (ata_setup_interrupt(dev)) 218 return ENXIO; 219 ctlr->setmode = ata_generic_setmode; 220 return 0; 221 } 222 223 static void 224 ata_generic_intr(void *data) 225 { 226 struct ata_pci_controller *ctlr = data; 227 struct ata_channel *ch; 228 int unit; 229 230 for (unit = 0; unit < ctlr->channels; unit++) { 231 if ((ch = ctlr->interrupt[unit].argument)) 232 ctlr->interrupt[unit].function(ch); 233 } 234 } 235 236 static void 237 ata_generic_setmode(device_t dev, int mode) 238 { 239 struct ata_device *atadev = device_get_softc(dev); 240 241 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 242 mode = ata_check_80pin(dev, mode); 243 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 244 atadev->mode = mode; 245 } 246 247 248 /* 249 * SATA support functions 250 */ 251 static void 252 ata_sata_phy_check_events(device_t dev) 253 { 254 struct ata_channel *ch = device_get_softc(dev); 255 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR); 256 257 /* clear error bits/interrupt */ 258 ATA_IDX_OUTL(ch, ATA_SERROR, error); 259 260 /* do we have any events flagged ? */ 261 if (error) { 262 struct ata_connect_task *tp; 263 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS); 264 265 /* if we have a connection event deal with it */ 266 if ((error & ATA_SE_PHY_CHANGED) && 267 (tp = (struct ata_connect_task *) 268 kmalloc(sizeof(struct ata_connect_task), 269 M_ATA, M_INTWAIT | M_ZERO))) { 270 271 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) || 272 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) { 273 if (bootverbose) 274 device_printf(ch->dev, "CONNECT requested\n"); 275 tp->action = ATA_C_ATTACH; 276 } 277 else { 278 if (bootverbose) 279 device_printf(ch->dev, "DISCONNECT requested\n"); 280 tp->action = ATA_C_DETACH; 281 } 282 tp->dev = ch->dev; 283 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 284 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 285 } 286 } 287 } 288 289 static void 290 ata_sata_phy_event(void *context, int dummy) 291 { 292 struct ata_connect_task *tp = (struct ata_connect_task *)context; 293 struct ata_channel *ch = device_get_softc(tp->dev); 294 device_t *children; 295 int nchildren, i; 296 297 get_mplock(); 298 if (tp->action == ATA_C_ATTACH) { 299 if (bootverbose) 300 device_printf(tp->dev, "CONNECTED\n"); 301 ATA_RESET(tp->dev); 302 ata_identify(tp->dev); 303 } 304 if (tp->action == ATA_C_DETACH) { 305 if (!device_get_children(tp->dev, &children, &nchildren)) { 306 for (i = 0; i < nchildren; i++) 307 if (children[i]) 308 device_delete_child(tp->dev, children[i]); 309 kfree(children, M_TEMP); 310 } 311 lockmgr(&ch->state_mtx, LK_EXCLUSIVE); 312 ch->state = ATA_IDLE; 313 lockmgr(&ch->state_mtx, LK_RELEASE); 314 if (bootverbose) 315 device_printf(tp->dev, "DISCONNECTED\n"); 316 } 317 rel_mplock(); 318 kfree(tp, M_ATA); 319 } 320 321 static int 322 ata_sata_phy_reset(device_t dev) 323 { 324 struct ata_channel *ch = device_get_softc(dev); 325 int loop, retry; 326 327 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 328 return ata_sata_connect(ch); 329 330 for (retry = 0; retry < 10; retry++) { 331 for (loop = 0; loop < 10; loop++) { 332 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET); 333 ata_udelay(100); 334 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & 335 ATA_SC_DET_MASK) == ATA_SC_DET_RESET) 336 break; 337 } 338 ata_udelay(5000); 339 for (loop = 0; loop < 10; loop++) { 340 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE | 341 ATA_SC_IPM_DIS_PARTIAL | 342 ATA_SC_IPM_DIS_SLUMBER); 343 ata_udelay(100); 344 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0) 345 return ata_sata_connect(ch); 346 } 347 } 348 return 0; 349 } 350 351 static int 352 ata_sata_connect(struct ata_channel *ch) 353 { 354 u_int32_t status; 355 int timeout; 356 357 /* wait up to 1 second for "connect well" */ 358 for (timeout = 0; timeout < 100 ; timeout++) { 359 status = ATA_IDX_INL(ch, ATA_SSTATUS); 360 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 || 361 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2) 362 break; 363 ata_udelay(10000); 364 } 365 if (timeout >= 100) { 366 if (bootverbose) 367 device_printf(ch->dev, "SATA connect status=%08x\n", status); 368 return 0; 369 } 370 371 if (bootverbose) 372 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10); 373 374 /* clear SATA error register */ 375 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 376 377 return 1; 378 } 379 380 static void 381 ata_sata_setmode(device_t dev, int mode) 382 { 383 struct ata_device *atadev = device_get_softc(dev); 384 385 /* 386 * if we detect that the device isn't a real SATA device we limit 387 * the transfer mode to UDMA5/ATA100. 388 * this works around the problems some devices has with the 389 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133. 390 */ 391 if (atadev->param.satacapabilities != 0x0000 && 392 atadev->param.satacapabilities != 0xffff) { 393 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 394 395 /* on some drives we need to set the transfer mode */ 396 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 397 ata_limit_mode(dev, mode, ATA_UDMA6)); 398 399 /* query SATA STATUS for the speed */ 400 if (ch->r_io[ATA_SSTATUS].res && 401 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) == 402 ATA_SS_CONWELL_GEN2)) 403 atadev->mode = ATA_SA300; 404 else 405 atadev->mode = ATA_SA150; 406 } 407 else { 408 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 409 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 410 atadev->mode = mode; 411 } 412 } 413 414 static int 415 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis) 416 { 417 struct ata_device *atadev = device_get_softc(request->dev); 418 419 if (request->flags & ATA_R_ATAPI) { 420 fis[0] = 0x27; /* host to device */ 421 fis[1] = 0x80; /* command FIS (note PM goes here) */ 422 fis[2] = ATA_PACKET_CMD; 423 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) 424 fis[3] = ATA_F_DMA; 425 else { 426 fis[5] = request->transfersize; 427 fis[6] = request->transfersize >> 8; 428 } 429 fis[7] = ATA_D_LBA | atadev->unit; 430 fis[15] = ATA_A_4BIT; 431 return 20; 432 } 433 else { 434 ata_modify_if_48bit(request); 435 fis[0] = 0x27; /* host to device */ 436 fis[1] = 0x80; /* command FIS (note PM goes here) */ 437 fis[2] = request->u.ata.command; 438 fis[3] = request->u.ata.feature; 439 fis[4] = request->u.ata.lba; 440 fis[5] = request->u.ata.lba >> 8; 441 fis[6] = request->u.ata.lba >> 16; 442 fis[7] = ATA_D_LBA | atadev->unit; 443 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 444 fis[7] |= (request->u.ata.lba >> 24 & 0x0f); 445 fis[8] = request->u.ata.lba >> 24; 446 fis[9] = request->u.ata.lba >> 32; 447 fis[10] = request->u.ata.lba >> 40; 448 fis[11] = request->u.ata.feature >> 8; 449 fis[12] = request->u.ata.count; 450 fis[13] = request->u.ata.count >> 8; 451 fis[15] = ATA_A_4BIT; 452 return 20; 453 } 454 return 0; 455 } 456 457 /* 458 * AHCI v1.x compliant SATA chipset support functions 459 */ 460 int 461 ata_ahci_ident(device_t dev) 462 { 463 struct ata_pci_controller *ctlr = device_get_softc(dev); 464 static struct ata_chip_id id = {0, 0, 0, 0x00, ATA_SA300, "AHCI"}; 465 char buffer[64]; 466 467 if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0) 468 return ENXIO; 469 470 if (bootverbose) 471 ksnprintf(buffer, sizeof(buffer), "%s (ID=%08x) AHCI controller", 472 ata_pcivendor2str(dev), pci_get_devid(dev)); 473 else 474 ksnprintf(buffer, sizeof(buffer), "%s AHCI controller", 475 ata_pcivendor2str(dev)); 476 device_set_desc_copy(dev, buffer); 477 ctlr->chip = &id; 478 ctlr->chipinit = ata_ahci_chipinit; 479 return 0; 480 } 481 482 483 /* 484 * AHCI v1.x compliant SATA chipset support functions 485 */ 486 int 487 ata_ahci_chipinit(device_t dev) 488 { 489 struct ata_pci_controller *ctlr = device_get_softc(dev); 490 u_int32_t version; 491 int unit; 492 493 /* if we have a memory BAR(5) we are likely on an AHCI part */ 494 ctlr->r_type2 = SYS_RES_MEMORY; 495 ctlr->r_rid2 = PCIR_BAR(5); 496 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 497 &ctlr->r_rid2, RF_ACTIVE))) 498 return ENXIO; 499 500 /* setup interrupt delivery if not done allready by a vendor driver */ 501 if (!ctlr->r_irq) { 502 if (ata_setup_interrupt(dev)) 503 return ENXIO; 504 } 505 else 506 device_printf(dev, "AHCI called from vendor specific driver\n"); 507 508 /* enable AHCI mode */ 509 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 510 511 /* reset AHCI controller */ 512 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR); 513 DELAY(1000000); 514 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) { 515 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 516 device_printf(dev, "AHCI controller reset failure\n"); 517 return ENXIO; 518 } 519 520 /* reenable AHCI mode */ 521 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 522 523 /* get the number of HW channels */ 524 ctlr->channels = 525 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)), 526 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 527 528 /* disable interrupt sources and clear interrupts */ 529 for (unit = 0; unit < ctlr->channels; unit++) { 530 int offset = unit << 7; 531 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0); 532 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, -1); 533 } 534 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS)); 535 536 /* enable AHCI interrupts */ 537 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 538 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE); 539 540 ctlr->reset = ata_ahci_reset; 541 ctlr->dmainit = ata_ahci_dmainit; 542 ctlr->allocate = ata_ahci_allocate; 543 ctlr->setmode = ata_sata_setmode; 544 545 /* enable PCI interrupt */ 546 pci_write_config(dev, PCIR_COMMAND, 547 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 548 549 /* announce we support the HW */ 550 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS); 551 device_printf(dev, 552 "AHCI Version %x%x.%x%x controller with %d ports detected\n", 553 (version >> 24) & 0xff, (version >> 16) & 0xff, 554 (version >> 8) & 0xff, version & 0xff, 555 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 556 return 0; 557 } 558 559 static int 560 ata_ahci_allocate(device_t dev) 561 { 562 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 563 struct ata_channel *ch = device_get_softc(dev); 564 u_int64_t work; 565 int offset = ch->unit << 7; 566 567 /* set the SATA resources */ 568 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 569 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset; 570 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 571 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset; 572 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 573 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset; 574 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 575 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset; 576 577 ch->hw.status = ata_ahci_status; 578 ch->hw.begin_transaction = ata_ahci_begin_transaction; 579 ch->hw.end_transaction = ata_ahci_end_transaction; 580 ch->hw.command = NULL; /* not used here */ 581 582 /* setup work areas */ 583 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET; 584 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff); 585 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32); 586 587 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET; 588 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff); 589 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32); 590 591 /* enable wanted port interrupts */ 592 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 593 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF | 594 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF | 595 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP | 596 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS | 597 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR)); 598 599 /* start operations on this channel */ 600 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 601 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 602 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 603 return 0; 604 } 605 606 static int 607 ata_ahci_status(device_t dev) 608 { 609 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 610 struct ata_channel *ch = device_get_softc(dev); 611 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS); 612 int offset = ch->unit << 7; 613 int tag = 0; 614 615 if (action & (1 << ch->unit)) { 616 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset); 617 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset); 618 619 /* clear interrupt(s) */ 620 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit)); 621 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus); 622 623 /* do we have any PHY events ? */ 624 /* XXX SOS check istatus phy bits */ 625 ata_sata_phy_check_events(dev); 626 627 /* do we have a potentially hanging engine to take care of? */ 628 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) { 629 630 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 631 int timeout = 0; 632 633 /* kill off all activity on this channel */ 634 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 635 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 636 637 /* XXX SOS this is not entirely wrong */ 638 do { 639 DELAY(1000); 640 if (timeout++ > 500) { 641 device_printf(dev, "stopping AHCI engine failed\n"); 642 break; 643 } 644 } while (ATA_INL(ctlr->r_res2, 645 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 646 647 /* start operations on this channel */ 648 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 649 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 650 651 return 1; 652 } 653 else 654 return (!(cstatus & (1 << tag))); 655 } 656 return 0; 657 } 658 659 /* must be called with ATA channel locked and state_mtx held */ 660 static int 661 ata_ahci_begin_transaction(struct ata_request *request) 662 { 663 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 664 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 665 struct ata_ahci_cmd_tab *ctp; 666 struct ata_ahci_cmd_list *clp; 667 int offset = ch->unit << 7; 668 int tag = 0, entries = 0; 669 int fis_size; 670 671 /* get a piece of the workspace for this request */ 672 ctp = (struct ata_ahci_cmd_tab *) 673 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag)); 674 675 /* setup the FIS for this request */ 676 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) { 677 device_printf(request->dev, "setting up SATA FIS failed\n"); 678 request->result = EIO; 679 return ATA_OP_FINISHED; 680 } 681 682 /* if request moves data setup and load SG list */ 683 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 684 if (ch->dma->load(ch->dev, request->data, request->bytecount, 685 request->flags & ATA_R_READ, 686 ctp->prd_tab, &entries)) { 687 device_printf(request->dev, "setting up DMA failed\n"); 688 request->result = EIO; 689 return ATA_OP_FINISHED; 690 } 691 } 692 693 /* setup the command list entry */ 694 clp = (struct ata_ahci_cmd_list *) 695 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 696 697 clp->prd_length = entries; 698 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) | 699 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) | 700 (fis_size / sizeof(u_int32_t)); 701 clp->bytecount = 0; 702 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET + 703 (ATA_AHCI_CT_SIZE * tag)); 704 705 /* clear eventual ACTIVE bit */ 706 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag)); 707 708 /* set command type bit */ 709 if (request->flags & ATA_R_ATAPI) 710 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 711 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) | 712 ATA_AHCI_P_CMD_ATAPI); 713 else 714 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 715 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & 716 ~ATA_AHCI_P_CMD_ATAPI); 717 718 /* issue command to controller */ 719 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag)); 720 721 if (!(request->flags & ATA_R_ATAPI)) { 722 /* device reset doesn't interrupt */ 723 if (request->u.ata.command == ATA_DEVICE_RESET) { 724 u_int32_t tf_data; 725 int timeout = 1000000; 726 727 do { 728 DELAY(10); 729 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7)); 730 } while ((tf_data & ATA_S_BUSY) && timeout--); 731 if (bootverbose) 732 device_printf(ch->dev, "device_reset timeout=%dus\n", 733 (1000000-timeout)*10); 734 request->status = tf_data; 735 if (request->status & ATA_S_ERROR) 736 request->error = tf_data >> 8; 737 return ATA_OP_FINISHED; 738 } 739 } 740 741 /* start the timeout */ 742 callout_reset(&request->callout, request->timeout * hz, 743 (timeout_t*)ata_timeout, request); 744 return ATA_OP_CONTINUES; 745 } 746 747 /* must be called with ATA channel locked and state_mtx held */ 748 static int 749 ata_ahci_end_transaction(struct ata_request *request) 750 { 751 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 752 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 753 struct ata_ahci_cmd_list *clp; 754 u_int32_t tf_data; 755 int offset = ch->unit << 7; 756 int tag = 0; 757 758 /* kill the timeout */ 759 callout_stop_sync(&request->callout); 760 761 /* get status */ 762 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset); 763 request->status = tf_data; 764 765 /* if error status get details */ 766 if (request->status & ATA_S_ERROR) 767 request->error = tf_data >> 8; 768 769 /* record how much data we actually moved */ 770 clp = (struct ata_ahci_cmd_list *) 771 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 772 request->donecount = clp->bytecount; 773 774 /* release SG list etc */ 775 ch->dma->unload(ch->dev); 776 777 return ATA_OP_FINISHED; 778 } 779 780 static void 781 ata_ahci_reset(device_t dev) 782 { 783 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 784 struct ata_channel *ch = device_get_softc(dev); 785 u_int32_t cmd, signature; 786 int offset = ch->unit << 7; 787 int timeout; 788 789 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) { 790 device_printf(dev, "port not implemented\n"); 791 return; 792 } 793 ch->devices = 0; 794 795 /* kill off all activity on this channel */ 796 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 797 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 798 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 799 800 /* XXX SOS this is not entirely wrong */ 801 timeout = 0; 802 do { 803 DELAY(1000); 804 if (timeout++ > 500) { 805 device_printf(dev, "stopping AHCI engine failed\n"); 806 break; 807 } 808 } 809 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 810 811 /* issue Command List Override if supported */ 812 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) { 813 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 814 cmd |= ATA_AHCI_P_CMD_CLO; 815 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd); 816 timeout = 0; 817 do { 818 DELAY(1000); 819 if (timeout++ > 500) { 820 device_printf(dev, "executing CLO failed\n"); 821 break; 822 } 823 } 824 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO); 825 } 826 827 /* reset PHY and decide what is present */ 828 if (ata_sata_phy_reset(dev)) { 829 830 /* clear any interrupts pending on this channel */ 831 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, 832 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset)); 833 834 /* clear SATA error register */ 835 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 836 837 /* start operations on this channel */ 838 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 839 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 840 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 841 842 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset); 843 switch (signature) { 844 case 0x00000101: 845 ch->devices = ATA_ATA_MASTER; 846 break; 847 case 0x96690101: 848 ch->devices = ATA_PORTMULTIPLIER; 849 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 850 ch->devices = 0; 851 break; 852 case 0xeb140101: 853 ch->devices = ATA_ATAPI_MASTER; 854 break; 855 default: /* SOS XXX */ 856 if (bootverbose) 857 device_printf(ch->dev, "No signature, assuming disk device\n"); 858 ch->devices = ATA_ATA_MASTER; 859 } 860 } 861 if (bootverbose) 862 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices, 863 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 864 } 865 866 static void 867 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 868 { 869 struct ata_dmasetprd_args *args = xsc; 870 struct ata_ahci_dma_prd *prd = args->dmatab; 871 int i; 872 873 if (!(args->error = error)) { 874 for (i = 0; i < nsegs; i++) { 875 prd[i].dba = htole64(segs[i].ds_addr); 876 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK); 877 } 878 } 879 args->nsegs = nsegs; 880 } 881 882 static void 883 ata_ahci_dmainit(device_t dev) 884 { 885 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 886 struct ata_channel *ch = device_get_softc(dev); 887 888 ata_dmainit(dev); 889 if (ch->dma) { 890 /* note start and stop are not used here */ 891 ch->dma->setprd = ata_ahci_dmasetprd; 892 ch->dma->max_iosize = 8192 * DEV_BSIZE; 893 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT) 894 ch->dma->max_address = BUS_SPACE_MAXADDR; 895 } 896 } 897 898 static int 899 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request) 900 { 901 bzero(ctp->cfis, 64); 902 if (request->flags & ATA_R_ATAPI) { 903 bzero(ctp->acmd, 32); 904 bcopy(request->u.atapi.ccb, ctp->acmd, 16); 905 } 906 return ata_request2fis_h2d(request, &ctp->cfis[0]); 907 } 908 909 /* 910 * Acard chipset support functions 911 */ 912 int 913 ata_acard_ident(device_t dev) 914 { 915 struct ata_pci_controller *ctlr = device_get_softc(dev); 916 struct ata_chip_id *idx; 917 static struct ata_chip_id ids[] = 918 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" }, 919 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" }, 920 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" }, 921 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" }, 922 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" }, 923 { 0, 0, 0, 0, 0, 0}}; 924 char buffer[64]; 925 926 if (!(idx = ata_match_chip(dev, ids))) 927 return ENXIO; 928 929 ksprintf(buffer, "Acard %s %s controller", 930 idx->text, ata_mode2str(idx->max_dma)); 931 device_set_desc_copy(dev, buffer); 932 ctlr->chip = idx; 933 ctlr->chipinit = ata_acard_chipinit; 934 return 0; 935 } 936 937 static int 938 ata_acard_chipinit(device_t dev) 939 { 940 struct ata_pci_controller *ctlr = device_get_softc(dev); 941 942 if (ata_setup_interrupt(dev)) 943 return ENXIO; 944 945 ctlr->allocate = ata_acard_allocate; 946 if (ctlr->chip->cfg1 == ATPOLD) { 947 ctlr->setmode = ata_acard_850_setmode; 948 ctlr->locking = ata_serialize; 949 } 950 else 951 ctlr->setmode = ata_acard_86X_setmode; 952 return 0; 953 } 954 955 static int 956 ata_acard_allocate(device_t dev) 957 { 958 struct ata_channel *ch = device_get_softc(dev); 959 960 /* setup the usual register normal pci style */ 961 if (ata_pci_allocate(dev)) 962 return ENXIO; 963 964 ch->hw.status = ata_acard_status; 965 return 0; 966 } 967 968 static int 969 ata_acard_status(device_t dev) 970 { 971 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 972 struct ata_channel *ch = device_get_softc(dev); 973 974 if (ctlr->chip->cfg1 == ATPOLD && 975 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit) 976 return 0; 977 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) { 978 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 979 980 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != 981 ATA_BMSTAT_INTERRUPT) 982 return 0; 983 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR); 984 DELAY(1); 985 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 986 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 987 DELAY(1); 988 } 989 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 990 DELAY(100); 991 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 992 return 0; 993 } 994 return 1; 995 } 996 997 static void 998 ata_acard_850_setmode(device_t dev, int mode) 999 { 1000 device_t gparent = GRANDPARENT(dev); 1001 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1002 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1003 struct ata_device *atadev = device_get_softc(dev); 1004 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1005 int error; 1006 1007 mode = ata_limit_mode(dev, mode, 1008 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 1009 1010 /* XXX SOS missing WDMA0+1 + PIO modes */ 1011 if (mode >= ATA_WDMA2) { 1012 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1013 if (bootverbose) 1014 device_printf(dev, "%ssetting %s on %s chip\n", 1015 (error) ? "FAILURE " : "", 1016 ata_mode2str(mode), ctlr->chip->text); 1017 if (!error) { 1018 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1); 1019 1020 reg54 &= ~(0x03 << (devno << 1)); 1021 if (mode >= ATA_UDMA0) 1022 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1)); 1023 pci_write_config(gparent, 0x54, reg54, 1); 1024 pci_write_config(gparent, 0x4a, 0xa6, 1); 1025 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2); 1026 atadev->mode = mode; 1027 return; 1028 } 1029 } 1030 /* we could set PIO mode timings, but we assume the BIOS did that */ 1031 } 1032 1033 static void 1034 ata_acard_86X_setmode(device_t dev, int mode) 1035 { 1036 device_t gparent = GRANDPARENT(dev); 1037 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1038 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1039 struct ata_device *atadev = device_get_softc(dev); 1040 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1041 int error; 1042 1043 1044 mode = ata_limit_mode(dev, mode, 1045 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 1046 1047 mode = ata_check_80pin(dev, mode); 1048 1049 /* XXX SOS missing WDMA0+1 + PIO modes */ 1050 if (mode >= ATA_WDMA2) { 1051 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1052 if (bootverbose) 1053 device_printf(dev, "%ssetting %s on %s chip\n", 1054 (error) ? "FAILURE " : "", 1055 ata_mode2str(mode), ctlr->chip->text); 1056 if (!error) { 1057 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2); 1058 1059 reg44 &= ~(0x000f << (devno << 2)); 1060 if (mode >= ATA_UDMA0) 1061 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2)); 1062 pci_write_config(gparent, 0x44, reg44, 2); 1063 pci_write_config(gparent, 0x4a, 0xa6, 1); 1064 pci_write_config(gparent, 0x40 + devno, 0x31, 1); 1065 atadev->mode = mode; 1066 return; 1067 } 1068 } 1069 /* we could set PIO mode timings, but we assume the BIOS did that */ 1070 } 1071 1072 1073 /* 1074 * Acer Labs Inc (ALI) chipset support functions 1075 */ 1076 int 1077 ata_ali_ident(device_t dev) 1078 { 1079 struct ata_pci_controller *ctlr = device_get_softc(dev); 1080 struct ata_chip_id *idx; 1081 static struct ata_chip_id ids[] = 1082 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" }, 1083 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" }, 1084 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" }, 1085 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" }, 1086 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" }, 1087 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" }, 1088 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" }, 1089 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" }, 1090 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" }, 1091 { 0, 0, 0, 0, 0, 0}}; 1092 char buffer[64]; 1093 1094 if (!(idx = ata_match_chip(dev, ids))) 1095 return ENXIO; 1096 1097 ksprintf(buffer, "AcerLabs %s %s controller", 1098 idx->text, ata_mode2str(idx->max_dma)); 1099 device_set_desc_copy(dev, buffer); 1100 ctlr->chip = idx; 1101 ctlr->chipinit = ata_ali_chipinit; 1102 return 0; 1103 } 1104 1105 static int 1106 ata_ali_chipinit(device_t dev) 1107 { 1108 struct ata_pci_controller *ctlr = device_get_softc(dev); 1109 1110 if (ata_setup_interrupt(dev)) 1111 return ENXIO; 1112 1113 switch (ctlr->chip->cfg2) { 1114 case ALISATA: 1115 ctlr->channels = ctlr->chip->cfg1; 1116 ctlr->allocate = ata_ali_sata_allocate; 1117 ctlr->setmode = ata_sata_setmode; 1118 1119 /* AHCI mode is correctly supported only on the ALi 5288. */ 1120 if ((ctlr->chip->chipid == ATA_ALI_5288) && 1121 (ata_ahci_chipinit(dev) != ENXIO)) 1122 return 0; 1123 1124 /* enable PCI interrupt */ 1125 pci_write_config(dev, PCIR_COMMAND, 1126 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1127 break; 1128 1129 case ALINEW: 1130 /* use device interrupt as byte count end */ 1131 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1); 1132 1133 /* enable cable detection and UDMA support on newer chips */ 1134 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1); 1135 1136 /* enable ATAPI UDMA mode */ 1137 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1); 1138 1139 /* only chips with revision > 0xc4 can do 48bit DMA */ 1140 if (ctlr->chip->chiprev <= 0xc4) 1141 device_printf(dev, 1142 "using PIO transfers above 137GB as workaround for " 1143 "48bit DMA access bug, expect reduced performance\n"); 1144 ctlr->allocate = ata_ali_allocate; 1145 ctlr->reset = ata_ali_reset; 1146 ctlr->setmode = ata_ali_setmode; 1147 break; 1148 1149 case ALIOLD: 1150 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */ 1151 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1); 1152 ctlr->setmode = ata_ali_setmode; 1153 break; 1154 } 1155 return 0; 1156 } 1157 1158 static int 1159 ata_ali_allocate(device_t dev) 1160 { 1161 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1162 struct ata_channel *ch = device_get_softc(dev); 1163 1164 /* setup the usual register normal pci style */ 1165 if (ata_pci_allocate(dev)) 1166 return ENXIO; 1167 1168 /* older chips can't do 48bit DMA transfers */ 1169 if (ctlr->chip->chiprev <= 0xc4) 1170 ch->flags |= ATA_NO_48BIT_DMA; 1171 1172 return 0; 1173 } 1174 1175 static int 1176 ata_ali_sata_allocate(device_t dev) 1177 { 1178 device_t parent = device_get_parent(dev); 1179 struct ata_pci_controller *ctlr = device_get_softc(parent); 1180 struct ata_channel *ch = device_get_softc(dev); 1181 struct resource *io = NULL, *ctlio = NULL; 1182 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 1183 int i, rid; 1184 1185 rid = PCIR_BAR(0) + (unit01 ? 8 : 0); 1186 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1187 if (!io) 1188 return ENXIO; 1189 1190 rid = PCIR_BAR(1) + (unit01 ? 8 : 0); 1191 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1192 if (!ctlio) { 1193 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io); 1194 return ENXIO; 1195 } 1196 1197 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 1198 ch->r_io[i].res = io; 1199 ch->r_io[i].offset = i + (unit10 ? 8 : 0); 1200 } 1201 ch->r_io[ATA_CONTROL].res = ctlio; 1202 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0); 1203 ch->r_io[ATA_IDX_ADDR].res = io; 1204 ata_default_registers(dev); 1205 if (ctlr->r_res1) { 1206 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 1207 ch->r_io[i].res = ctlr->r_res1; 1208 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 1209 } 1210 } 1211 ch->flags |= ATA_NO_SLAVE; 1212 1213 /* XXX SOS PHY handling awkward in ALI chip not supported yet */ 1214 ata_pci_hw(dev); 1215 return 0; 1216 } 1217 1218 static void 1219 ata_ali_reset(device_t dev) 1220 { 1221 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1222 struct ata_channel *ch = device_get_softc(dev); 1223 device_t *children; 1224 int nchildren, i; 1225 1226 ata_generic_reset(dev); 1227 1228 /* 1229 * workaround for datacorruption bug found on at least SUN Blade-100 1230 * find the ISA function on the southbridge and disable then enable 1231 * the ATA channel tristate buffer 1232 */ 1233 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) { 1234 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) { 1235 for (i = 0; i < nchildren; i++) { 1236 if (pci_get_devid(children[i]) == ATA_ALI_1533) { 1237 pci_write_config(children[i], 0x58, 1238 pci_read_config(children[i], 0x58, 1) & 1239 ~(0x04 << ch->unit), 1); 1240 pci_write_config(children[i], 0x58, 1241 pci_read_config(children[i], 0x58, 1) | 1242 (0x04 << ch->unit), 1); 1243 break; 1244 } 1245 } 1246 kfree(children, M_TEMP); 1247 } 1248 } 1249 } 1250 1251 static void 1252 ata_ali_setmode(device_t dev, int mode) 1253 { 1254 device_t gparent = GRANDPARENT(dev); 1255 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1256 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1257 struct ata_device *atadev = device_get_softc(dev); 1258 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1259 int error; 1260 1261 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1262 1263 if (ctlr->chip->cfg2 & ALINEW) { 1264 if (mode > ATA_UDMA2 && 1265 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) { 1266 ata_print_cable(dev, "controller"); 1267 mode = ATA_UDMA2; 1268 } 1269 } 1270 else 1271 mode = ata_check_80pin(dev, mode); 1272 1273 if (ctlr->chip->cfg2 & ALIOLD) { 1274 /* doesn't support ATAPI DMA on write */ 1275 ch->flags |= ATA_ATAPI_DMA_RO; 1276 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) { 1277 /* doesn't support ATAPI DMA on two ATAPI devices */ 1278 device_printf(dev, "two atapi devices on this channel, no DMA\n"); 1279 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1280 } 1281 } 1282 1283 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1284 1285 if (bootverbose) 1286 device_printf(dev, "%ssetting %s on %s chip\n", 1287 (error) ? "FAILURE " : "", 1288 ata_mode2str(mode), ctlr->chip->text); 1289 if (!error) { 1290 if (mode >= ATA_UDMA0) { 1291 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d}; 1292 u_int32_t word54 = pci_read_config(gparent, 0x54, 4); 1293 1294 word54 &= ~(0x000f000f << (devno << 2)); 1295 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2)); 1296 pci_write_config(gparent, 0x54, word54, 4); 1297 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1298 0x00310001, 4); 1299 } 1300 else { 1301 u_int32_t piotimings[] = 1302 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001, 1303 0x00310001, 0x00440001, 0x00330001, 0x00310001}; 1304 1305 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) & 1306 ~(0x0008000f << (devno << 2)), 4); 1307 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1308 piotimings[ata_mode2idx(mode)], 4); 1309 } 1310 atadev->mode = mode; 1311 } 1312 } 1313 1314 1315 /* 1316 * American Micro Devices (AMD) chipset support functions 1317 */ 1318 int 1319 ata_amd_ident(device_t dev) 1320 { 1321 struct ata_pci_controller *ctlr = device_get_softc(dev); 1322 struct ata_chip_id *idx; 1323 static struct ata_chip_id ids[] = 1324 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" }, 1325 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" }, 1326 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" }, 1327 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" }, 1328 { 0, 0, 0, 0, 0, 0}}; 1329 char buffer[64]; 1330 1331 if (!(idx = ata_match_chip(dev, ids))) 1332 return ENXIO; 1333 1334 ksprintf(buffer, "AMD %s %s controller", 1335 idx->text, ata_mode2str(idx->max_dma)); 1336 device_set_desc_copy(dev, buffer); 1337 ctlr->chip = idx; 1338 ctlr->chipinit = ata_amd_chipinit; 1339 return 0; 1340 } 1341 1342 static int 1343 ata_amd_chipinit(device_t dev) 1344 { 1345 struct ata_pci_controller *ctlr = device_get_softc(dev); 1346 1347 if (ata_setup_interrupt(dev)) 1348 return ENXIO; 1349 1350 /* disable/set prefetch, postwrite */ 1351 if (ctlr->chip->cfg2 & AMDBUG) 1352 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1); 1353 else 1354 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); 1355 1356 ctlr->setmode = ata_via_family_setmode; 1357 return 0; 1358 } 1359 1360 1361 /* 1362 * ATI chipset support functions 1363 */ 1364 int 1365 ata_ati_ident(device_t dev) 1366 { 1367 struct ata_pci_controller *ctlr = device_get_softc(dev); 1368 struct ata_chip_id *idx; 1369 static struct ata_chip_id ids[] = 1370 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" }, 1371 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" }, 1372 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" }, 1373 { ATA_ATI_SB600, 0x00, 0, 0, ATA_UDMA6, "SB600" }, 1374 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" }, 1375 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1376 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1377 { ATA_ATI_SB600_S1, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1378 { ATA_ATI_SB600_S2, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1379 { 0, 0, 0, 0, 0, 0}}; 1380 char buffer[64]; 1381 1382 if (!(idx = ata_match_chip(dev, ids))) 1383 return ENXIO; 1384 1385 ksprintf(buffer, "ATI %s %s controller", 1386 idx->text, ata_mode2str(idx->max_dma)); 1387 device_set_desc_copy(dev, buffer); 1388 ctlr->chip = idx; 1389 1390 /* 1391 * The ATI SATA controllers are actually a SiI 3112 controller, except 1392 * for the SB600. 1393 */ 1394 if (ctlr->chip->cfg1 & SIIMEMIO) 1395 ctlr->chipinit = ata_sii_chipinit; 1396 else 1397 ctlr->chipinit = ata_ati_chipinit; 1398 return 0; 1399 } 1400 1401 static int 1402 ata_ati_chipinit(device_t dev) 1403 { 1404 struct ata_pci_controller *ctlr = device_get_softc(dev); 1405 1406 if (ata_setup_interrupt(dev)) 1407 return ENXIO; 1408 1409 /* The SB600 needs special treatment. */ 1410 if (ctlr->chip->cfg1 & ATIAHCI) { 1411 /* Check if the chip is configured as an AHCI part. */ 1412 if ((pci_get_subclass(dev) == PCIS_STORAGE_SATA) && 1413 (pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI_1_0)) { 1414 if (ata_ahci_chipinit(dev) != ENXIO) 1415 return 0; 1416 } 1417 } 1418 1419 ctlr->setmode = ata_ati_setmode; 1420 return 0; 1421 } 1422 1423 static void 1424 ata_ati_setmode(device_t dev, int mode) 1425 { 1426 device_t gparent = GRANDPARENT(dev); 1427 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1428 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1429 struct ata_device *atadev = device_get_softc(dev); 1430 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1431 int offset = (devno ^ 0x01) << 3; 1432 int error; 1433 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 1434 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 1435 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 1436 1437 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1438 1439 mode = ata_check_80pin(dev, mode); 1440 1441 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1442 1443 if (bootverbose) 1444 device_printf(dev, "%ssetting %s on %s chip\n", 1445 (error) ? "FAILURE " : "", 1446 ata_mode2str(mode), ctlr->chip->text); 1447 if (!error) { 1448 if (mode >= ATA_UDMA0) { 1449 pci_write_config(gparent, 0x56, 1450 (pci_read_config(gparent, 0x56, 2) & 1451 ~(0xf << (devno << 2))) | 1452 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 1453 pci_write_config(gparent, 0x54, 1454 pci_read_config(gparent, 0x54, 1) | 1455 (0x01 << devno), 1); 1456 pci_write_config(gparent, 0x44, 1457 (pci_read_config(gparent, 0x44, 4) & 1458 ~(0xff << offset)) | 1459 (dmatimings[2] << offset), 4); 1460 } 1461 else if (mode >= ATA_WDMA0) { 1462 pci_write_config(gparent, 0x54, 1463 pci_read_config(gparent, 0x54, 1) & 1464 ~(0x01 << devno), 1); 1465 pci_write_config(gparent, 0x44, 1466 (pci_read_config(gparent, 0x44, 4) & 1467 ~(0xff << offset)) | 1468 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 1469 } 1470 else 1471 pci_write_config(gparent, 0x54, 1472 pci_read_config(gparent, 0x54, 1) & 1473 ~(0x01 << devno), 1); 1474 1475 pci_write_config(gparent, 0x4a, 1476 (pci_read_config(gparent, 0x4a, 2) & 1477 ~(0xf << (devno << 2))) | 1478 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2); 1479 pci_write_config(gparent, 0x40, 1480 (pci_read_config(gparent, 0x40, 4) & 1481 ~(0xff << offset)) | 1482 (piotimings[ata_mode2idx(mode)] << offset), 4); 1483 atadev->mode = mode; 1484 } 1485 } 1486 1487 /* 1488 * Cyrix chipset support functions 1489 */ 1490 int 1491 ata_cyrix_ident(device_t dev) 1492 { 1493 struct ata_pci_controller *ctlr = device_get_softc(dev); 1494 1495 if (pci_get_devid(dev) == ATA_CYRIX_5530) { 1496 device_set_desc(dev, "Cyrix 5530 ATA33 controller"); 1497 ctlr->chipinit = ata_cyrix_chipinit; 1498 return 0; 1499 } 1500 return ENXIO; 1501 } 1502 1503 static int 1504 ata_cyrix_chipinit(device_t dev) 1505 { 1506 struct ata_pci_controller *ctlr = device_get_softc(dev); 1507 1508 if (ata_setup_interrupt(dev)) 1509 return ENXIO; 1510 1511 if (ctlr->r_res1) 1512 ctlr->setmode = ata_cyrix_setmode; 1513 else 1514 ctlr->setmode = ata_generic_setmode; 1515 return 0; 1516 } 1517 1518 static void 1519 ata_cyrix_setmode(device_t dev, int mode) 1520 { 1521 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1522 struct ata_device *atadev = device_get_softc(dev); 1523 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1524 u_int32_t piotiming[] = 1525 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 }; 1526 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 }; 1527 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 }; 1528 int error; 1529 1530 ch->dma->alignment = 16; 1531 ch->dma->max_iosize = 126 * DEV_BSIZE; 1532 1533 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 1534 1535 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1536 1537 if (bootverbose) 1538 device_printf(dev, "%ssetting %s on Cyrix chip\n", 1539 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1540 if (!error) { 1541 if (mode >= ATA_UDMA0) { 1542 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1543 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]); 1544 } 1545 else if (mode >= ATA_WDMA0) { 1546 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1547 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]); 1548 } 1549 else { 1550 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1551 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]); 1552 } 1553 atadev->mode = mode; 1554 } 1555 } 1556 1557 1558 /* 1559 * Cypress chipset support functions 1560 */ 1561 int 1562 ata_cypress_ident(device_t dev) 1563 { 1564 struct ata_pci_controller *ctlr = device_get_softc(dev); 1565 1566 /* 1567 * the Cypress chip is a mess, it contains two ATA functions, but 1568 * both channels are visible on the first one. 1569 * simply ignore the second function for now, as the right 1570 * solution (ignoring the second channel on the first function) 1571 * doesn't work with the crappy ATA interrupt setup on the alpha. 1572 */ 1573 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 && 1574 pci_get_function(dev) == 1 && 1575 pci_get_subclass(dev) == PCIS_STORAGE_IDE) { 1576 device_set_desc(dev, "Cypress 82C693 ATA controller"); 1577 ctlr->chipinit = ata_cypress_chipinit; 1578 return 0; 1579 } 1580 return ENXIO; 1581 } 1582 1583 static int 1584 ata_cypress_chipinit(device_t dev) 1585 { 1586 struct ata_pci_controller *ctlr = device_get_softc(dev); 1587 1588 if (ata_setup_interrupt(dev)) 1589 return ENXIO; 1590 1591 ctlr->setmode = ata_cypress_setmode; 1592 return 0; 1593 } 1594 1595 static void 1596 ata_cypress_setmode(device_t dev, int mode) 1597 { 1598 device_t gparent = GRANDPARENT(dev); 1599 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1600 struct ata_device *atadev = device_get_softc(dev); 1601 int error; 1602 1603 mode = ata_limit_mode(dev, mode, ATA_WDMA2); 1604 1605 /* XXX SOS missing WDMA0+1 + PIO modes */ 1606 if (mode == ATA_WDMA2) { 1607 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1608 if (bootverbose) 1609 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n", 1610 error ? "FAILURE " : ""); 1611 if (!error) { 1612 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2); 1613 atadev->mode = mode; 1614 return; 1615 } 1616 } 1617 /* we could set PIO mode timings, but we assume the BIOS did that */ 1618 } 1619 1620 1621 /* 1622 * HighPoint chipset support functions 1623 */ 1624 int 1625 ata_highpoint_ident(device_t dev) 1626 { 1627 struct ata_pci_controller *ctlr = device_get_softc(dev); 1628 struct ata_chip_id *idx; 1629 static struct ata_chip_id ids[] = 1630 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" }, 1631 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" }, 1632 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1633 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" }, 1634 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1635 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" }, 1636 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" }, 1637 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" }, 1638 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" }, 1639 { 0, 0, 0, 0, 0, 0}}; 1640 char buffer[64]; 1641 1642 if (!(idx = ata_match_chip(dev, ids))) 1643 return ENXIO; 1644 1645 strcpy(buffer, "HighPoint "); 1646 strcat(buffer, idx->text); 1647 if (idx->cfg1 == HPT374) { 1648 if (pci_get_function(dev) == 0) 1649 strcat(buffer, " (channel 0+1)"); 1650 if (pci_get_function(dev) == 1) 1651 strcat(buffer, " (channel 2+3)"); 1652 } 1653 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 1654 device_set_desc_copy(dev, buffer); 1655 ctlr->chip = idx; 1656 ctlr->chipinit = ata_highpoint_chipinit; 1657 return 0; 1658 } 1659 1660 static int 1661 ata_highpoint_chipinit(device_t dev) 1662 { 1663 struct ata_pci_controller *ctlr = device_get_softc(dev); 1664 1665 if (ata_setup_interrupt(dev)) 1666 return ENXIO; 1667 1668 if (ctlr->chip->cfg2 == HPTOLD) { 1669 /* disable interrupt prediction */ 1670 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 1671 } 1672 else { 1673 /* disable interrupt prediction */ 1674 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 1675 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 1676 1677 /* enable interrupts */ 1678 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 1679 1680 /* set clocks etc */ 1681 if (ctlr->chip->cfg1 < HPT372) 1682 pci_write_config(dev, 0x5b, 0x22, 1); 1683 else 1684 pci_write_config(dev, 0x5b, 1685 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 1686 } 1687 ctlr->allocate = ata_highpoint_allocate; 1688 ctlr->setmode = ata_highpoint_setmode; 1689 return 0; 1690 } 1691 1692 static int 1693 ata_highpoint_allocate(device_t dev) 1694 { 1695 struct ata_channel *ch = device_get_softc(dev); 1696 1697 /* setup the usual register normal pci style */ 1698 if (ata_pci_allocate(dev)) 1699 return ENXIO; 1700 1701 ch->flags |= ATA_ALWAYS_DMASTAT; 1702 return 0; 1703 } 1704 1705 static void 1706 ata_highpoint_setmode(device_t dev, int mode) 1707 { 1708 device_t gparent = GRANDPARENT(dev); 1709 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1710 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1711 struct ata_device *atadev = device_get_softc(dev); 1712 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1713 int error; 1714 u_int32_t timings33[][4] = { 1715 /* HPT366 HPT370 HPT372 HPT374 mode */ 1716 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */ 1717 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */ 1718 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */ 1719 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */ 1720 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */ 1721 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */ 1722 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */ 1723 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */ 1724 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */ 1725 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */ 1726 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */ 1727 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */ 1728 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */ 1729 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */ 1730 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */ 1731 }; 1732 1733 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1734 1735 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev)) 1736 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1737 1738 mode = ata_highpoint_check_80pin(dev, mode); 1739 1740 /* 1741 * most if not all HPT chips cant really handle that the device is 1742 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to 1743 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance 1744 */ 1745 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 1746 ata_limit_mode(dev, mode, ATA_UDMA5)); 1747 if (bootverbose) 1748 device_printf(dev, "%ssetting %s on HighPoint chip\n", 1749 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1750 if (!error) 1751 pci_write_config(gparent, 0x40 + (devno << 2), 1752 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 1753 atadev->mode = mode; 1754 } 1755 1756 static int 1757 ata_highpoint_check_80pin(device_t dev, int mode) 1758 { 1759 device_t gparent = GRANDPARENT(dev); 1760 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1761 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1762 u_int8_t reg, val, res; 1763 1764 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) { 1765 reg = ch->unit ? 0x57 : 0x53; 1766 val = pci_read_config(gparent, reg, 1); 1767 pci_write_config(gparent, reg, val | 0x80, 1); 1768 } 1769 else { 1770 reg = 0x5b; 1771 val = pci_read_config(gparent, reg, 1); 1772 pci_write_config(gparent, reg, val & 0xfe, 1); 1773 } 1774 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2); 1775 pci_write_config(gparent, reg, val, 1); 1776 1777 if (mode > ATA_UDMA2 && res) { 1778 ata_print_cable(dev, "controller"); 1779 mode = ATA_UDMA2; 1780 } 1781 return mode; 1782 } 1783 1784 1785 /* 1786 * Intel chipset support functions 1787 */ 1788 int 1789 ata_intel_ident(device_t dev) 1790 { 1791 struct ata_pci_controller *ctlr = device_get_softc(dev); 1792 struct ata_chip_id *idx; 1793 static struct ata_chip_id ids[] = 1794 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" }, 1795 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" }, 1796 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1797 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1798 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1799 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" }, 1800 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1801 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1802 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1803 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1804 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1805 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1806 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1807 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1808 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" }, 1809 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1810 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1811 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" }, 1812 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1813 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1814 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" }, 1815 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1816 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1817 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" }, 1818 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" }, 1819 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1820 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1821 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1822 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1823 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1824 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1825 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" }, 1826 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1827 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1828 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1829 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1830 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1831 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1832 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1833 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1834 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1835 { ATA_I82801HBM_S1, 0, 0, 0x00, ATA_SA300, "ICH8M" }, 1836 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1837 { ATA_I82801HBM_S3, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1838 { ATA_I82801IB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1839 { ATA_I82801IB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1840 { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1841 { ATA_I82801IB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1842 { ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1843 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" }, 1844 { 0, 0, 0, 0, 0, 0}}; 1845 char buffer[64]; 1846 1847 if (!(idx = ata_match_chip(dev, ids))) 1848 return ENXIO; 1849 1850 ksprintf(buffer, "Intel %s %s controller", 1851 idx->text, ata_mode2str(idx->max_dma)); 1852 device_set_desc_copy(dev, buffer); 1853 ctlr->chip = idx; 1854 ctlr->chipinit = ata_intel_chipinit; 1855 return 0; 1856 } 1857 1858 static int 1859 ata_intel_chipinit(device_t dev) 1860 { 1861 struct ata_pci_controller *ctlr = device_get_softc(dev); 1862 1863 if (ata_setup_interrupt(dev)) 1864 return ENXIO; 1865 1866 /* good old PIIX needs special treatment (not implemented) */ 1867 if (ctlr->chip->chipid == ATA_I82371FB) { 1868 ctlr->setmode = ata_intel_old_setmode; 1869 } 1870 1871 /* the intel 31244 needs special care if in DPA mode */ 1872 else if (ctlr->chip->chipid == ATA_I31244) { 1873 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 1874 ctlr->r_type2 = SYS_RES_MEMORY; 1875 ctlr->r_rid2 = PCIR_BAR(0); 1876 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1877 &ctlr->r_rid2, 1878 RF_ACTIVE))) { 1879 ata_teardown_interrupt(dev); 1880 return ENXIO; 1881 } 1882 ctlr->channels = 4; 1883 ctlr->allocate = ata_intel_31244_allocate; 1884 ctlr->reset = ata_intel_31244_reset; 1885 } 1886 ctlr->setmode = ata_sata_setmode; 1887 } 1888 1889 /* non SATA intel chips goes here */ 1890 else if (ctlr->chip->max_dma < ATA_SA150) { 1891 ctlr->allocate = ata_intel_allocate; 1892 ctlr->setmode = ata_intel_new_setmode; 1893 } 1894 1895 /* SATA parts can be either compat or AHCI */ 1896 else { 1897 /* force all ports active "the legacy way" */ 1898 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2); 1899 1900 ctlr->allocate = ata_intel_allocate; 1901 ctlr->reset = ata_intel_reset; 1902 1903 /* 1904 * if we have AHCI capability and BAR(5) as a memory resource 1905 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode 1906 */ 1907 if ((ctlr->chip->cfg1 == AHCI) && 1908 (pci_read_config(dev, 0x90, 1) & 0xc0) && 1909 (ata_ahci_chipinit(dev) != ENXIO)) 1910 return 0; 1911 1912 /* if BAR(5) is IO it should point to SATA interface registers */ 1913 ctlr->r_type2 = SYS_RES_IOPORT; 1914 ctlr->r_rid2 = PCIR_BAR(5); 1915 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1916 &ctlr->r_rid2, RF_ACTIVE))) 1917 ctlr->setmode = ata_intel_sata_setmode; 1918 else 1919 ctlr->setmode = ata_sata_setmode; 1920 1921 /* enable PCI interrupt */ 1922 pci_write_config(dev, PCIR_COMMAND, 1923 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1924 } 1925 return 0; 1926 } 1927 1928 static int 1929 ata_intel_allocate(device_t dev) 1930 { 1931 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1932 struct ata_channel *ch = device_get_softc(dev); 1933 1934 /* setup the usual register normal pci style */ 1935 if (ata_pci_allocate(dev)) 1936 return ENXIO; 1937 1938 /* if r_res2 is valid it points to SATA interface registers */ 1939 if (ctlr->r_res2) { 1940 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 1941 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 1942 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 1943 ch->r_io[ATA_IDX_DATA].offset = 0x04; 1944 } 1945 1946 ch->flags |= ATA_ALWAYS_DMASTAT; 1947 return 0; 1948 } 1949 1950 static void 1951 ata_intel_reset(device_t dev) 1952 { 1953 device_t parent = device_get_parent(dev); 1954 struct ata_pci_controller *ctlr = device_get_softc(parent); 1955 struct ata_channel *ch = device_get_softc(dev); 1956 int mask, timeout; 1957 1958 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */ 1959 if (ctlr->chip->cfg1) { 1960 mask = (0x0005 << ch->unit); 1961 } 1962 else { 1963 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */ 1964 if (pci_read_config(parent, 0x90, 1) & 0x04) 1965 mask = 0x0003; 1966 else { 1967 mask = (0x0001 << ch->unit); 1968 /* XXX SOS should be in intel_allocate if we grow it */ 1969 ch->flags |= ATA_NO_SLAVE; 1970 } 1971 } 1972 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2); 1973 DELAY(10); 1974 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2); 1975 1976 /* wait up to 1 sec for "connect well" */ 1977 for (timeout = 0; timeout < 100 ; timeout++) { 1978 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) && 1979 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 1980 break; 1981 ata_udelay(10000); 1982 } 1983 ata_generic_reset(dev); 1984 } 1985 1986 static void 1987 ata_intel_old_setmode(device_t dev, int mode) 1988 { 1989 /* NOT YET */ 1990 } 1991 1992 static void 1993 ata_intel_new_setmode(device_t dev, int mode) 1994 { 1995 device_t gparent = GRANDPARENT(dev); 1996 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1997 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1998 struct ata_device *atadev = device_get_softc(dev); 1999 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2000 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4); 2001 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1); 2002 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1); 2003 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2); 2004 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2); 2005 u_int32_t mask40 = 0, new40 = 0; 2006 u_int8_t mask44 = 0, new44 = 0; 2007 int error; 2008 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, 2009 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 }; 2010 /* PIO0 PIO1 PIO2 PIO3 PIO4 WDMA0 WDMA1 WDMA2 */ 2011 /* UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 UDMA5 UDMA6 */ 2012 2013 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 2014 2015 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { 2016 ata_print_cable(dev, "controller"); 2017 mode = ATA_UDMA2; 2018 } 2019 2020 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2021 2022 if (bootverbose) 2023 device_printf(dev, "%ssetting %s on %s chip\n", 2024 (error) ? "FAILURE " : "", 2025 ata_mode2str(mode), ctlr->chip->text); 2026 if (error) 2027 return; 2028 2029 /* 2030 * reg48: 1 bit per (primary drive 0, primary drive 1, secondary 2031 * drive 0, secondary drive 1) 2032 * 2033 * 0 Disable Ultra DMA mode 2034 * 1 Enable Ultra DMA mode 2035 * 2036 * reg4a: 4 bits per (primary drive 0, primary drive 1, secondary 2037 * drive 0, secondary drive 1). 2038 * 0000 UDMA mode 0 2039 * 0001 UDMA mode 1, 3, 5 2040 * 0010 UDMA mode 2, 4, reserved 2041 * 0011 reserved 2042 * (top two bits for each drive reserved) 2043 */ 2044 #if 0 2045 device_printf(dev, 2046 "regs before 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 2047 reg40, reg44, reg48 ,reg4a, reg54); 2048 #endif 2049 reg48 &= ~(0x0001 << devno); 2050 reg4a &= ~(0x3 << (devno << 2)); 2051 if (mode >= ATA_UDMA0) { 2052 reg48 |= 0x0001 << devno; 2053 if (mode > ATA_UDMA0) 2054 reg4a |= (1 + !(mode & 0x01)) << (devno << 2); 2055 } 2056 pci_write_config(gparent, 0x48, reg48, 2); 2057 pci_write_config(gparent, 0x4a, reg4a, 2); 2058 2059 /* 2060 * reg54: 2061 * 2062 * 32:20 reserved 2063 * 19:18 Secondary ATA signal mode 2064 * 17:16 Primary ATA signal mode 2065 * 00 = Normal (enabled) 2066 * 01 = Tri-state (disabled) 2067 * 10 = Drive Low (disabled) 2068 * 11 = Reserved 2069 * 2070 * 15 Secondary drive 1 - Base Clock 2071 * 14 Secondary drive 0 - Base Clock 2072 * 13 Primary drive 1 - Base Clock 2073 * 12 Primary drive 0 - Base Clock 2074 * 0 = Select 33 MHz clock 2075 * 1 = Select 100 Mhz clock 2076 * 2077 * 11 Reserved 2078 * 10 Vendor specific (set by BIOS?) 2079 * 09:08 Reserved 2080 * 2081 * 07 Secondary drive 1 - Cable Type 2082 * 06 Secondary drive 0 - Cable Type 2083 * 05 Primary drive 1 - Cable Type 2084 * 04 Primary drive 0 - Cable Type 2085 * 0 = 40 Conductor 2086 * 1 = 80 Conductor (or high speed cable) 2087 * 2088 * 03 Secondary drive 1 - Select 33/66 clock 2089 * 02 Secondary drive 0 - Select 33/66 clock 2090 * 01 Primary drive 1 - Select 33/66 clock 2091 * 00 Primary drive 0 - Select 33/66 clock 2092 * 0 = Select 33 MHz 2093 * 1 = Select 66 MHz 2094 * 2095 * It is unclear what this should be set to when operating 2096 * in 100MHz mode. 2097 * 2098 * NOTE: UDMA2 = 33 MHz 2099 * UDMA3 = 40 MHz (?) - unsupported 2100 * UDMA4 = 66 MHz 2101 * UDMA5 = 100 MHz 2102 * UDMA6 = 133 Mhz 2103 */ 2104 reg54 |= 0x0400; /* set vendor specific bit */ 2105 reg54 &= ~((0x1 << devno) | (0x1000 << devno)); 2106 2107 if (mode >= ATA_UDMA5) 2108 reg54 |= (0x1000 << devno); 2109 else if (mode >= ATA_UDMA3) /* XXX should this be ATA_UDMA3 or 4? */ 2110 reg54 |= (0x1 << devno); 2111 2112 pci_write_config(gparent, 0x54, reg54, 2); 2113 2114 /* 2115 * Reg40 (32 bits... well, actually two 16 bit registers) 2116 * 2117 * Primary channel bits 15:00, Secondary channel bits 31:00. Note 2118 * that slave timings are handled in register 44. 2119 * 2120 * 15 ATA Decode Enable (R/W) 1 = enable decoding of I/O ranges 2121 * 2122 * 14 Slave ATA Timing Register Enable (R/W) 2123 * 2124 * 13:12 IORDY Sample Mode 2125 * 00 PIO-0 2126 * 01 PIO-2, SW-2 2127 * 10 PIO-3, PIO-4, MW-1, MW-2 2128 * 11 Reserved 2129 * 2130 * 11:10 Reserved 2131 * 2132 * 09:08 Recovery Mode 2133 * 00 PIO-0, PIO-2, SW-2 2134 * 01 PIO-3, MW-1 2135 * 10 Reserved 2136 * 11 PIO-4, MW-2 2137 * 2138 * 07:04 Secondary Device Control Bits 2139 * 03:00 Primary Device Control Bits 2140 * 2141 * bit 3 DMA Timing Enable 2142 * 2143 * bit 2 Indicate Presence of ATA(1) or ATAPI(0) device 2144 * 2145 * bit 1 Enable IORDY sample point capability for PIO 2146 * xfers. Always enabled for PIO4 and PIO3, enabled 2147 * for PIO2 if indicated by the device, and otherwise 2148 * probably should be 0. 2149 * 2150 * bit 0 Fast Drive Timing Enable. Enables faster then PIO-0 2151 * timing modes. 2152 */ 2153 2154 /* 2155 * Modify reg40 according to the table 2156 */ 2157 if (atadev->unit == ATA_MASTER) { 2158 mask40 = 0x3300; 2159 new40 = timings[ata_mode2idx(mode)] << 8; 2160 } 2161 else { 2162 mask44 = 0x0f; 2163 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) | 2164 (timings[ata_mode2idx(mode)] & 0x03); 2165 } 2166 2167 /* 2168 * Slave ATA timing register enable 2169 */ 2170 mask40 |= 0x4000; 2171 new40 |= 0x4000; 2172 2173 /* 2174 * Device control bits 3:0 for master, 7:4 for slave. 2175 * 2176 * bit3 DMA Timing enable. 2177 * bit2 Indicate presence of ATA(1) or ATAPI(0) device, set accordingly 2178 * bit1 Enable IORDY sample point capability for PIO xfers. Always 2179 * enabled for PIO4 and PIO3, enabled for PIO2 if indicated by 2180 * the device, and otherwise should be 0. 2181 * bit0 Fast Drive Timing Enable. Enable faster then PIO-0 timing modes. 2182 * 2183 * Set to: 0 x 1 1 2184 */ 2185 2186 if (atadev->unit == ATA_MASTER) { 2187 mask40 |= 0x0F; 2188 new40 |= 0x03; 2189 if (!ata_atapi(dev)) 2190 new40 |= 0x04; 2191 } else { 2192 mask40 |= 0xF0; 2193 new40 |= 0x30; 2194 if (!ata_atapi(dev)) 2195 new40 |= 0x40; 2196 } 2197 /* 2198 reg40 &= ~0x00ff00ff; 2199 reg40 |= 0x40774077; 2200 */ 2201 2202 /* 2203 * Primary or Secondary controller 2204 */ 2205 if (ch->unit) { 2206 mask40 <<= 16; 2207 new40 <<= 16; 2208 mask44 <<= 4; 2209 new44 <<= 4; 2210 } 2211 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4); 2212 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1); 2213 2214 #if 0 2215 reg40 = pci_read_config(gparent, 0x40, 4); 2216 reg44 = pci_read_config(gparent, 0x44, 1); 2217 reg48 = pci_read_config(gparent, 0x48, 1); 2218 reg4a = pci_read_config(gparent, 0x4a, 2); 2219 reg54 = pci_read_config(gparent, 0x54, 2); 2220 device_printf(dev, 2221 "regs after 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 2222 reg40, reg44, reg48 ,reg4a, reg54); 2223 #endif 2224 2225 atadev->mode = mode; 2226 } 2227 2228 static void 2229 ata_intel_sata_setmode(device_t dev, int mode) 2230 { 2231 struct ata_device *atadev = device_get_softc(dev); 2232 2233 if (atadev->param.satacapabilities != 0x0000 && 2234 atadev->param.satacapabilities != 0xffff) { 2235 2236 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2237 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2238 2239 /* on some drives we need to set the transfer mode */ 2240 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 2241 ata_limit_mode(dev, mode, ATA_UDMA6)); 2242 2243 /* set ATA_SSTATUS register offset */ 2244 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100); 2245 2246 /* query SATA STATUS for the speed */ 2247 if ((ATA_IDX_INL(ch, ATA_IDX_DATA) & ATA_SS_CONWELL_MASK) == 2248 ATA_SS_CONWELL_GEN2) 2249 atadev->mode = ATA_SA300; 2250 else 2251 atadev->mode = ATA_SA150; 2252 } 2253 else { 2254 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 2255 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2256 atadev->mode = mode; 2257 } 2258 } 2259 2260 static int 2261 ata_intel_31244_allocate(device_t dev) 2262 { 2263 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2264 struct ata_channel *ch = device_get_softc(dev); 2265 int i; 2266 int ch_offset; 2267 2268 ch_offset = 0x200 + ch->unit * 0x200; 2269 2270 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 2271 ch->r_io[i].res = ctlr->r_res2; 2272 2273 /* setup ATA registers */ 2274 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 2275 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 2276 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 2277 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 2278 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 2279 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 2280 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 2281 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 2282 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 2283 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 2284 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 2285 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 2286 2287 /* setup DMA registers */ 2288 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 2289 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 2290 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 2291 2292 /* setup SATA registers */ 2293 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 2294 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 2295 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 2296 2297 ch->flags |= ATA_NO_SLAVE; 2298 ata_pci_hw(dev); 2299 ch->hw.status = ata_intel_31244_status; 2300 ch->hw.command = ata_intel_31244_command; 2301 2302 /* enable PHY state change interrupt */ 2303 ATA_OUTL(ctlr->r_res2, 0x4, 2304 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 2305 return 0; 2306 } 2307 2308 static int 2309 ata_intel_31244_status(device_t dev) 2310 { 2311 /* do we have any PHY events ? */ 2312 ata_sata_phy_check_events(dev); 2313 2314 /* any drive action to take care of ? */ 2315 return ata_pci_status(dev); 2316 } 2317 2318 static int 2319 ata_intel_31244_command(struct ata_request *request) 2320 { 2321 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2322 struct ata_device *atadev = device_get_softc(request->dev); 2323 u_int64_t lba; 2324 2325 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 2326 return (ata_generic_command(request)); 2327 2328 lba = request->u.ata.lba; 2329 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 2330 /* enable interrupt */ 2331 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 2332 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 2333 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 2334 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff)); 2335 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) | 2336 ((lba >> 8) & 0x00ff)); 2337 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) | 2338 ((lba >> 16) & 0x00ff)); 2339 2340 /* issue command to controller */ 2341 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 2342 2343 return 0; 2344 } 2345 2346 static void 2347 ata_intel_31244_reset(device_t dev) 2348 { 2349 if (ata_sata_phy_reset(dev)) 2350 ata_generic_reset(dev); 2351 } 2352 2353 2354 /* 2355 * Integrated Technology Express Inc. (ITE) chipset support functions 2356 */ 2357 int 2358 ata_ite_ident(device_t dev) 2359 { 2360 struct ata_pci_controller *ctlr = device_get_softc(dev); 2361 struct ata_chip_id *idx; 2362 static struct ata_chip_id ids[] = 2363 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 2364 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 2365 { 0, 0, 0, 0, 0, 0}}; 2366 char buffer[64]; 2367 2368 if (!(idx = ata_match_chip(dev, ids))) 2369 return ENXIO; 2370 2371 ksprintf(buffer, "ITE %s %s controller", 2372 idx->text, ata_mode2str(idx->max_dma)); 2373 device_set_desc_copy(dev, buffer); 2374 ctlr->chip = idx; 2375 ctlr->chipinit = ata_ite_chipinit; 2376 return 0; 2377 } 2378 2379 static int 2380 ata_ite_chipinit(device_t dev) 2381 { 2382 struct ata_pci_controller *ctlr = device_get_softc(dev); 2383 2384 if (ata_setup_interrupt(dev)) 2385 return ENXIO; 2386 2387 ctlr->setmode = ata_ite_setmode; 2388 2389 /* set PCI mode and 66Mhz reference clock */ 2390 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 2391 2392 /* set default active & recover timings */ 2393 pci_write_config(dev, 0x54, 0x31, 1); 2394 pci_write_config(dev, 0x56, 0x31, 1); 2395 return 0; 2396 } 2397 2398 static void 2399 ata_ite_setmode(device_t dev, int mode) 2400 { 2401 device_t gparent = GRANDPARENT(dev); 2402 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2403 struct ata_device *atadev = device_get_softc(dev); 2404 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2405 int error; 2406 2407 /* correct the mode for what the HW supports */ 2408 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2409 2410 /* check the CBLID bits for 80 conductor cable detection */ 2411 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) & 2412 (ch->unit ? (1<<3) : (1<<2)))) { 2413 ata_print_cable(dev, "controller"); 2414 mode = ATA_UDMA2; 2415 } 2416 2417 /* set the wanted mode on the device */ 2418 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2419 2420 if (bootverbose) 2421 device_printf(dev, "%s setting %s on ITE8212F chip\n", 2422 (error) ? "failed" : "success", ata_mode2str(mode)); 2423 2424 /* if the device accepted the mode change, setup the HW accordingly */ 2425 if (!error) { 2426 if (mode >= ATA_UDMA0) { 2427 u_int8_t udmatiming[] = 2428 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 2429 2430 /* enable UDMA mode */ 2431 pci_write_config(gparent, 0x50, 2432 pci_read_config(gparent, 0x50, 1) & 2433 ~(1 << (devno + 3)), 1); 2434 2435 /* set UDMA timing */ 2436 pci_write_config(gparent, 2437 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit), 2438 udmatiming[mode & ATA_MODE_MASK], 1); 2439 } 2440 else { 2441 u_int8_t chtiming[] = 2442 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 2443 2444 /* disable UDMA mode */ 2445 pci_write_config(gparent, 0x50, 2446 pci_read_config(gparent, 0x50, 1) | 2447 (1 << (devno + 3)), 1); 2448 2449 /* set active and recover timing (shared between master & slave) */ 2450 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) < 2451 chtiming[ata_mode2idx(mode)]) 2452 pci_write_config(gparent, 0x54 + (ch->unit << 2), 2453 chtiming[ata_mode2idx(mode)], 1); 2454 } 2455 atadev->mode = mode; 2456 } 2457 } 2458 2459 2460 /* 2461 * JMicron chipset support functions 2462 */ 2463 int 2464 ata_jmicron_ident(device_t dev) 2465 { 2466 struct ata_pci_controller *ctlr = device_get_softc(dev); 2467 struct ata_chip_id *idx; 2468 static struct ata_chip_id ids[] = 2469 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" }, 2470 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" }, 2471 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" }, 2472 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" }, 2473 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" }, 2474 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" }, 2475 { 0, 0, 0, 0, 0, 0}}; 2476 char buffer[64]; 2477 2478 if (!(idx = ata_match_chip(dev, ids))) 2479 return ENXIO; 2480 2481 if ((pci_read_config(dev, 0xdf, 1) & 0x40) && 2482 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1))) 2483 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2484 idx->text, ata_mode2str(ATA_UDMA6)); 2485 else 2486 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2487 idx->text, ata_mode2str(idx->max_dma)); 2488 device_set_desc_copy(dev, buffer); 2489 ctlr->chip = idx; 2490 ctlr->chipinit = ata_jmicron_chipinit; 2491 return 0; 2492 } 2493 2494 static int 2495 ata_jmicron_chipinit(device_t dev) 2496 { 2497 struct ata_pci_controller *ctlr = device_get_softc(dev); 2498 int error; 2499 2500 if (ata_setup_interrupt(dev)) 2501 return ENXIO; 2502 2503 /* do we have multiple PCI functions ? */ 2504 if (pci_read_config(dev, 0xdf, 1) & 0x40) { 2505 /* are we on the AHCI part ? */ 2506 if (ata_ahci_chipinit(dev) != ENXIO) 2507 return 0; 2508 2509 /* otherwise we are on the PATA part */ 2510 ctlr->allocate = ata_pci_allocate; 2511 ctlr->reset = ata_generic_reset; 2512 ctlr->dmainit = ata_pci_dmainit; 2513 ctlr->setmode = ata_jmicron_setmode; 2514 ctlr->channels = ctlr->chip->cfg2; 2515 } 2516 else { 2517 /* set controller configuration to a combined setup we support */ 2518 pci_write_config(dev, 0x40, 0x80c0a131, 4); 2519 pci_write_config(dev, 0x80, 0x01200000, 4); 2520 2521 if ((error = ata_ahci_chipinit(dev))) { 2522 ata_teardown_interrupt(dev); 2523 return error; 2524 } 2525 2526 ctlr->allocate = ata_jmicron_allocate; 2527 ctlr->reset = ata_jmicron_reset; 2528 ctlr->dmainit = ata_jmicron_dmainit; 2529 ctlr->setmode = ata_jmicron_setmode; 2530 2531 /* set the number of HW channels */ 2532 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2; 2533 } 2534 return 0; 2535 } 2536 2537 static int 2538 ata_jmicron_allocate(device_t dev) 2539 { 2540 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2541 struct ata_channel *ch = device_get_softc(dev); 2542 int error; 2543 2544 if (ch->unit >= ctlr->chip->cfg1) { 2545 ch->unit -= ctlr->chip->cfg1; 2546 error = ata_pci_allocate(dev); 2547 ch->unit += ctlr->chip->cfg1; 2548 } 2549 else 2550 error = ata_ahci_allocate(dev); 2551 return error; 2552 } 2553 2554 static void 2555 ata_jmicron_reset(device_t dev) 2556 { 2557 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2558 struct ata_channel *ch = device_get_softc(dev); 2559 2560 if (ch->unit >= ctlr->chip->cfg1) 2561 ata_generic_reset(dev); 2562 else 2563 ata_ahci_reset(dev); 2564 } 2565 2566 static void 2567 ata_jmicron_dmainit(device_t dev) 2568 { 2569 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2570 struct ata_channel *ch = device_get_softc(dev); 2571 2572 if (ch->unit >= ctlr->chip->cfg1) 2573 ata_pci_dmainit(dev); 2574 else 2575 ata_ahci_dmainit(dev); 2576 } 2577 2578 static void 2579 ata_jmicron_setmode(device_t dev, int mode) 2580 { 2581 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 2582 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2583 2584 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) { 2585 struct ata_device *atadev = device_get_softc(dev); 2586 2587 /* check for 80pin cable present */ 2588 if (pci_read_config(dev, 0x40, 1) & 0x08) 2589 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 2590 else 2591 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2592 2593 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2594 atadev->mode = mode; 2595 } 2596 else 2597 ata_sata_setmode(dev, mode); 2598 } 2599 2600 2601 /* 2602 * Marvell chipset support functions 2603 */ 2604 #define ATA_MV_HOST_BASE(ch) \ 2605 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000) 2606 #define ATA_MV_EDMA_BASE(ch) \ 2607 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000) 2608 2609 struct ata_marvell_response { 2610 u_int16_t tag; 2611 u_int8_t edma_status; 2612 u_int8_t dev_status; 2613 u_int32_t timestamp; 2614 }; 2615 2616 struct ata_marvell_dma_prdentry { 2617 u_int32_t addrlo; 2618 u_int32_t count; 2619 u_int32_t addrhi; 2620 u_int32_t reserved; 2621 }; 2622 2623 int 2624 ata_marvell_ident(device_t dev) 2625 { 2626 struct ata_pci_controller *ctlr = device_get_softc(dev); 2627 struct ata_chip_id *idx; 2628 static struct ata_chip_id ids[] = 2629 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" }, 2630 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" }, 2631 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" }, 2632 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" }, 2633 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" }, 2634 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" }, 2635 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" }, 2636 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" }, 2637 { 0, 0, 0, 0, 0, 0}}; 2638 char buffer[64]; 2639 2640 if (!(idx = ata_match_chip(dev, ids))) 2641 return ENXIO; 2642 2643 ksprintf(buffer, "Marvell %s %s controller", 2644 idx->text, ata_mode2str(idx->max_dma)); 2645 device_set_desc_copy(dev, buffer); 2646 ctlr->chip = idx; 2647 switch (ctlr->chip->cfg2) { 2648 case MV50XX: 2649 case MV60XX: 2650 ctlr->chipinit = ata_marvell_edma_chipinit; 2651 break; 2652 case MV61XX: 2653 ctlr->chipinit = ata_marvell_pata_chipinit; 2654 break; 2655 } 2656 return 0; 2657 } 2658 2659 static int 2660 ata_marvell_pata_chipinit(device_t dev) 2661 { 2662 struct ata_pci_controller *ctlr = device_get_softc(dev); 2663 2664 if (ata_setup_interrupt(dev)) 2665 return ENXIO; 2666 2667 ctlr->allocate = ata_marvell_pata_allocate; 2668 ctlr->setmode = ata_marvell_pata_setmode; 2669 ctlr->channels = ctlr->chip->cfg1; 2670 return 0; 2671 } 2672 2673 static int 2674 ata_marvell_pata_allocate(device_t dev) 2675 { 2676 struct ata_channel *ch = device_get_softc(dev); 2677 2678 /* setup the usual register normal pci style */ 2679 if (ata_pci_allocate(dev)) 2680 return ENXIO; 2681 2682 /* dont use 32 bit PIO transfers */ 2683 ch->flags |= ATA_USE_16BIT; 2684 2685 return 0; 2686 } 2687 2688 static void 2689 ata_marvell_pata_setmode(device_t dev, int mode) 2690 { 2691 device_t gparent = GRANDPARENT(dev); 2692 struct ata_pci_controller *ctlr = device_get_softc(gparent); 2693 struct ata_device *atadev = device_get_softc(dev); 2694 2695 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 2696 mode = ata_check_80pin(dev, mode); 2697 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2698 atadev->mode = mode; 2699 } 2700 2701 static int 2702 ata_marvell_edma_chipinit(device_t dev) 2703 { 2704 struct ata_pci_controller *ctlr = device_get_softc(dev); 2705 2706 if (ata_setup_interrupt(dev)) 2707 return ENXIO; 2708 2709 ctlr->r_type1 = SYS_RES_MEMORY; 2710 ctlr->r_rid1 = PCIR_BAR(0); 2711 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 2712 &ctlr->r_rid1, RF_ACTIVE))) { 2713 ata_teardown_interrupt(dev); 2714 return ENXIO; 2715 } 2716 2717 /* mask all host controller interrupts */ 2718 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000); 2719 2720 /* mask all PCI interrupts */ 2721 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000); 2722 2723 ctlr->allocate = ata_marvell_edma_allocate; 2724 ctlr->reset = ata_marvell_edma_reset; 2725 ctlr->dmainit = ata_marvell_edma_dmainit; 2726 ctlr->setmode = ata_sata_setmode; 2727 ctlr->channels = ctlr->chip->cfg1; 2728 2729 /* clear host controller interrupts */ 2730 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000); 2731 if (ctlr->chip->cfg1 > 4) 2732 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000); 2733 2734 /* clear PCI interrupts */ 2735 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000); 2736 2737 /* unmask PCI interrupts we want */ 2738 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff); 2739 2740 /* unmask host controller interrupts we want */ 2741 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ | 2742 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25)); 2743 2744 /* enable PCI interrupt */ 2745 pci_write_config(dev, PCIR_COMMAND, 2746 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 2747 return 0; 2748 } 2749 2750 static int 2751 ata_marvell_edma_allocate(device_t dev) 2752 { 2753 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2754 struct ata_channel *ch = device_get_softc(dev); 2755 u_int64_t work = ch->dma->work_bus; 2756 int i; 2757 2758 /* clear work area */ 2759 bzero(ch->dma->work, 1024+256); 2760 2761 /* set legacy ATA resources */ 2762 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 2763 ch->r_io[i].res = ctlr->r_res1; 2764 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch); 2765 } 2766 ch->r_io[ATA_CONTROL].res = ctlr->r_res1; 2767 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch); 2768 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1; 2769 ata_default_registers(dev); 2770 2771 /* set SATA resources */ 2772 switch (ctlr->chip->cfg2) { 2773 case MV50XX: 2774 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2775 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch); 2776 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2777 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch); 2778 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2779 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch); 2780 break; 2781 case MV60XX: 2782 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2783 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch); 2784 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2785 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch); 2786 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2787 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch); 2788 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1; 2789 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch); 2790 break; 2791 } 2792 2793 ch->flags |= ATA_NO_SLAVE; 2794 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */ 2795 ata_generic_hw(dev); 2796 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction; 2797 ch->hw.end_transaction = ata_marvell_edma_end_transaction; 2798 ch->hw.status = ata_marvell_edma_status; 2799 2800 /* disable the EDMA machinery */ 2801 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2802 DELAY(100000); /* SOS should poll for disabled */ 2803 2804 /* set configuration to non-queued 128b read transfers stop on error */ 2805 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13)); 2806 2807 /* request queue base high */ 2808 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32); 2809 2810 /* request queue in ptr */ 2811 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2812 2813 /* request queue out ptr */ 2814 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0); 2815 2816 /* response queue base high */ 2817 work += 1024; 2818 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32); 2819 2820 /* response queue in ptr */ 2821 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0); 2822 2823 /* response queue out ptr */ 2824 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2825 2826 /* clear SATA error register */ 2827 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 2828 2829 /* clear any outstanding error interrupts */ 2830 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2831 2832 /* unmask all error interrupts */ 2833 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 2834 2835 /* enable EDMA machinery */ 2836 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2837 return 0; 2838 } 2839 2840 static int 2841 ata_marvell_edma_status(device_t dev) 2842 { 2843 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2844 struct ata_channel *ch = device_get_softc(dev); 2845 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60); 2846 int shift = (ch->unit << 1) + (ch->unit > 3); 2847 2848 if (cause & (1 << shift)) { 2849 2850 /* clear interrupt(s) */ 2851 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2852 2853 /* do we have any PHY events ? */ 2854 ata_sata_phy_check_events(dev); 2855 } 2856 2857 /* do we have any device action ? */ 2858 return (cause & (2 << shift)); 2859 } 2860 2861 /* must be called with ATA channel locked and state_mtx held */ 2862 static int 2863 ata_marvell_edma_begin_transaction(struct ata_request *request) 2864 { 2865 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2866 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2867 u_int32_t req_in; 2868 u_int8_t *bytep; 2869 u_int16_t *wordp; 2870 u_int32_t *quadp; 2871 int i, tag = 0x07; 2872 int dummy, error, slot; 2873 2874 /* only DMA R/W goes through the EMDA machine */ 2875 if (request->u.ata.command != ATA_READ_DMA && 2876 request->u.ata.command != ATA_WRITE_DMA) { 2877 2878 /* disable the EDMA machinery */ 2879 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001) 2880 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2881 return ata_begin_transaction(request); 2882 } 2883 2884 /* check for 48 bit access and convert if needed */ 2885 ata_modify_if_48bit(request); 2886 2887 /* check sanity, setup SG list and DMA engine */ 2888 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 2889 request->flags & ATA_R_READ, ch->dma->sg, 2890 &dummy))) { 2891 device_printf(request->dev, "setting up DMA failed\n"); 2892 request->result = error; 2893 return ATA_OP_FINISHED; 2894 } 2895 2896 /* get next free request queue slot */ 2897 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch)); 2898 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f; 2899 bytep = (u_int8_t *)(ch->dma->work); 2900 bytep += (slot << 5); 2901 wordp = (u_int16_t *)bytep; 2902 quadp = (u_int32_t *)bytep; 2903 2904 /* fill in this request */ 2905 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff; 2906 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32; 2907 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1); 2908 2909 i = 10; 2910 bytep[i++] = (request->u.ata.count >> 8) & 0xff; 2911 bytep[i++] = 0x10 | ATA_COUNT; 2912 bytep[i++] = request->u.ata.count & 0xff; 2913 bytep[i++] = 0x10 | ATA_COUNT; 2914 2915 bytep[i++] = (request->u.ata.lba >> 24) & 0xff; 2916 bytep[i++] = 0x10 | ATA_SECTOR; 2917 bytep[i++] = request->u.ata.lba & 0xff; 2918 bytep[i++] = 0x10 | ATA_SECTOR; 2919 2920 bytep[i++] = (request->u.ata.lba >> 32) & 0xff; 2921 bytep[i++] = 0x10 | ATA_CYL_LSB; 2922 bytep[i++] = (request->u.ata.lba >> 8) & 0xff; 2923 bytep[i++] = 0x10 | ATA_CYL_LSB; 2924 2925 bytep[i++] = (request->u.ata.lba >> 40) & 0xff; 2926 bytep[i++] = 0x10 | ATA_CYL_MSB; 2927 bytep[i++] = (request->u.ata.lba >> 16) & 0xff; 2928 bytep[i++] = 0x10 | ATA_CYL_MSB; 2929 2930 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf); 2931 bytep[i++] = 0x10 | ATA_DRIVE; 2932 2933 bytep[i++] = request->u.ata.command; 2934 bytep[i++] = 0x90 | ATA_COMMAND; 2935 2936 /* enable EDMA machinery if needed */ 2937 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) { 2938 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2939 while (!(ATA_INL(ctlr->r_res1, 2940 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 2941 DELAY(10); 2942 } 2943 2944 /* tell EDMA it has a new request */ 2945 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f; 2946 req_in &= 0xfffffc00; 2947 req_in += (slot << 5); 2948 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in); 2949 2950 return ATA_OP_CONTINUES; 2951 } 2952 2953 /* must be called with ATA channel locked and state_mtx held */ 2954 static int 2955 ata_marvell_edma_end_transaction(struct ata_request *request) 2956 { 2957 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2958 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2959 int offset = (ch->unit > 3 ? 0x30014 : 0x20014); 2960 u_int32_t icr = ATA_INL(ctlr->r_res1, offset); 2961 int res; 2962 2963 /* EDMA interrupt */ 2964 if ((icr & (0x0001 << (ch->unit & 3)))) { 2965 struct ata_marvell_response *response; 2966 u_int32_t rsp_in, rsp_out; 2967 int slot; 2968 2969 /* stop timeout */ 2970 callout_stop_sync(&request->callout); 2971 2972 /* get response ptr's */ 2973 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch)); 2974 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch)); 2975 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f; 2976 rsp_out &= 0xffffff00; 2977 rsp_out += (slot << 3); 2978 response = (struct ata_marvell_response *) 2979 (ch->dma->work + 1024 + (slot << 3)); 2980 2981 /* record status for this request */ 2982 request->status = response->dev_status; 2983 request->error = 0; 2984 2985 /* ack response */ 2986 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out); 2987 2988 /* update progress */ 2989 if (!(request->status & ATA_S_ERROR) && 2990 !(request->flags & ATA_R_TIMEOUT)) 2991 request->donecount = request->bytecount; 2992 2993 /* unload SG list */ 2994 ch->dma->unload(ch->dev); 2995 2996 res = ATA_OP_FINISHED; 2997 } 2998 2999 /* legacy ATA interrupt */ 3000 else { 3001 res = ata_end_transaction(request); 3002 } 3003 3004 /* ack interrupt */ 3005 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3)))); 3006 return res; 3007 } 3008 3009 static void 3010 ata_marvell_edma_reset(device_t dev) 3011 { 3012 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3013 struct ata_channel *ch = device_get_softc(dev); 3014 3015 /* disable the EDMA machinery */ 3016 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 3017 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 3018 DELAY(10); 3019 3020 /* clear SATA error register */ 3021 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 3022 3023 /* clear any outstanding error interrupts */ 3024 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 3025 3026 /* unmask all error interrupts */ 3027 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 3028 3029 /* enable channel and test for devices */ 3030 if (ata_sata_phy_reset(dev)) 3031 ata_generic_reset(dev); 3032 3033 /* enable EDMA machinery */ 3034 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 3035 } 3036 3037 static void 3038 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, 3039 int error) 3040 { 3041 struct ata_dmasetprd_args *args = xsc; 3042 struct ata_marvell_dma_prdentry *prd = args->dmatab; 3043 int i; 3044 3045 if ((args->error = error)) 3046 return; 3047 3048 for (i = 0; i < nsegs; i++) { 3049 prd[i].addrlo = htole32(segs[i].ds_addr); 3050 prd[i].count = htole32(segs[i].ds_len); 3051 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32); 3052 } 3053 prd[i - 1].count |= htole32(ATA_DMA_EOT); 3054 } 3055 3056 static void 3057 ata_marvell_edma_dmainit(device_t dev) 3058 { 3059 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3060 struct ata_channel *ch = device_get_softc(dev); 3061 3062 ata_dmainit(dev); 3063 if (ch->dma) { 3064 /* note start and stop are not used here */ 3065 ch->dma->setprd = ata_marvell_edma_dmasetprd; 3066 3067 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004) 3068 ch->dma->max_address = BUS_SPACE_MAXADDR; 3069 3070 /* chip does not reliably do 64K DMA transfers */ 3071 ch->dma->max_iosize = 126 * DEV_BSIZE; 3072 } 3073 } 3074 3075 3076 /* 3077 * National chipset support functions 3078 */ 3079 int 3080 ata_national_ident(device_t dev) 3081 { 3082 struct ata_pci_controller *ctlr = device_get_softc(dev); 3083 3084 /* this chip is a clone of the Cyrix chip, bugs and all */ 3085 if (pci_get_devid(dev) == ATA_SC1100) { 3086 device_set_desc(dev, "National Geode SC1100 ATA33 controller"); 3087 ctlr->chipinit = ata_national_chipinit; 3088 return 0; 3089 } 3090 return ENXIO; 3091 } 3092 3093 static int 3094 ata_national_chipinit(device_t dev) 3095 { 3096 struct ata_pci_controller *ctlr = device_get_softc(dev); 3097 3098 if (ata_setup_interrupt(dev)) 3099 return ENXIO; 3100 3101 ctlr->setmode = ata_national_setmode; 3102 return 0; 3103 } 3104 3105 static void 3106 ata_national_setmode(device_t dev, int mode) 3107 { 3108 device_t gparent = GRANDPARENT(dev); 3109 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3110 struct ata_device *atadev = device_get_softc(dev); 3111 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3112 u_int32_t piotiming[] = 3113 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010, 3114 0x00803020, 0x20102010, 0x00100010, 3115 0x00100010, 0x00100010, 0x00100010 }; 3116 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 }; 3117 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 }; 3118 int error; 3119 3120 ch->dma->alignment = 16; 3121 ch->dma->max_iosize = 126 * DEV_BSIZE; 3122 3123 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 3124 3125 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3126 3127 if (bootverbose) 3128 device_printf(dev, "%s setting %s on National chip\n", 3129 (error) ? "failed" : "success", ata_mode2str(mode)); 3130 if (!error) { 3131 if (mode >= ATA_UDMA0) { 3132 pci_write_config(gparent, 0x44 + (devno << 3), 3133 udmatiming[mode & ATA_MODE_MASK], 4); 3134 } 3135 else if (mode >= ATA_WDMA0) { 3136 pci_write_config(gparent, 0x44 + (devno << 3), 3137 dmatiming[mode & ATA_MODE_MASK], 4); 3138 } 3139 else { 3140 pci_write_config(gparent, 0x44 + (devno << 3), 3141 pci_read_config(gparent, 0x44 + (devno << 3), 4) | 3142 0x80000000, 4); 3143 } 3144 pci_write_config(gparent, 0x40 + (devno << 3), 3145 piotiming[ata_mode2idx(mode)], 4); 3146 atadev->mode = mode; 3147 } 3148 } 3149 3150 /* 3151 * NetCell chipset support functions 3152 */ 3153 int 3154 ata_netcell_ident(device_t dev) 3155 { 3156 struct ata_pci_controller *ctlr = device_get_softc(dev); 3157 3158 if (pci_get_devid(dev) == ATA_NETCELL_SR) { 3159 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller"); 3160 ctlr->chipinit = ata_netcell_chipinit; 3161 return 0; 3162 } 3163 return ENXIO; 3164 } 3165 3166 static int 3167 ata_netcell_chipinit(device_t dev) 3168 { 3169 struct ata_pci_controller *ctlr = device_get_softc(dev); 3170 3171 if (ata_generic_chipinit(dev)) 3172 return ENXIO; 3173 3174 ctlr->allocate = ata_netcell_allocate; 3175 return 0; 3176 } 3177 3178 static int 3179 ata_netcell_allocate(device_t dev) 3180 { 3181 struct ata_channel *ch = device_get_softc(dev); 3182 3183 /* setup the usual register normal pci style */ 3184 if (ata_pci_allocate(dev)) 3185 return ENXIO; 3186 3187 /* the NetCell only supports 16 bit PIO transfers */ 3188 ch->flags |= ATA_USE_16BIT; 3189 3190 return 0; 3191 } 3192 3193 3194 /* 3195 * nVidia chipset support functions 3196 */ 3197 int 3198 ata_nvidia_ident(device_t dev) 3199 { 3200 struct ata_pci_controller *ctlr = device_get_softc(dev); 3201 struct ata_chip_id *idx; 3202 static struct ata_chip_id ids[] = 3203 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" }, 3204 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" }, 3205 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" }, 3206 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" }, 3207 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" }, 3208 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" }, 3209 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3210 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3211 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" }, 3212 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3213 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3214 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" }, 3215 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3216 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3217 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" }, 3218 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3219 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3220 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" }, 3221 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3222 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3223 { ATA_NFORCE_MCP61, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP61" }, 3224 { ATA_NFORCE_MCP61_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" }, 3225 { ATA_NFORCE_MCP61_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" }, 3226 { ATA_NFORCE_MCP61_S3, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" }, 3227 { ATA_NFORCE_MCP65, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP65" }, 3228 { ATA_NFORCE_MCP67, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP67" }, 3229 { ATA_NFORCE_MCP67_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP67" }, 3230 { ATA_NFORCE_MCP73, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP73" }, 3231 { ATA_NFORCE_MCP77, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP77" }, 3232 { 0, 0, 0, 0, 0, 0}} ; 3233 char buffer[64] ; 3234 3235 if (!(idx = ata_match_chip(dev, ids))) 3236 return ENXIO; 3237 3238 ksprintf(buffer, "nVidia %s %s controller", 3239 idx->text, ata_mode2str(idx->max_dma)); 3240 device_set_desc_copy(dev, buffer); 3241 ctlr->chip = idx; 3242 ctlr->chipinit = ata_nvidia_chipinit; 3243 return 0; 3244 } 3245 3246 static int 3247 ata_nvidia_chipinit(device_t dev) 3248 { 3249 struct ata_pci_controller *ctlr = device_get_softc(dev); 3250 3251 if (ata_setup_interrupt(dev)) 3252 return ENXIO; 3253 3254 if (ctlr->chip->max_dma >= ATA_SA150) { 3255 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1) 3256 ctlr->r_type2 = SYS_RES_IOPORT; 3257 else 3258 ctlr->r_type2 = SYS_RES_MEMORY; 3259 ctlr->r_rid2 = PCIR_BAR(5); 3260 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3261 &ctlr->r_rid2, RF_ACTIVE))) { 3262 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3263 3264 ctlr->allocate = ata_nvidia_allocate; 3265 ctlr->reset = ata_nvidia_reset; 3266 3267 /* enable control access */ 3268 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1); 3269 3270 if (ctlr->chip->cfg2 & NVQ) { 3271 /* clear interrupt status */ 3272 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff); 3273 3274 /* enable device and PHY state change interrupts */ 3275 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d); 3276 3277 /* disable NCQ support */ 3278 ATA_OUTL(ctlr->r_res2, 0x0400, 3279 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9); 3280 } 3281 else { 3282 /* clear interrupt status */ 3283 ATA_OUTB(ctlr->r_res2, offset, 0xff); 3284 3285 /* enable device and PHY state change interrupts */ 3286 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd); 3287 } 3288 3289 /* enable PCI interrupt */ 3290 pci_write_config(dev, PCIR_COMMAND, 3291 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 3292 3293 } 3294 ctlr->setmode = ata_sata_setmode; 3295 } 3296 else { 3297 /* disable prefetch, postwrite */ 3298 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1); 3299 ctlr->setmode = ata_via_family_setmode; 3300 } 3301 return 0; 3302 } 3303 3304 static int 3305 ata_nvidia_allocate(device_t dev) 3306 { 3307 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3308 struct ata_channel *ch = device_get_softc(dev); 3309 3310 /* setup the usual register normal pci style */ 3311 if (ata_pci_allocate(dev)) 3312 return ENXIO; 3313 3314 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3315 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6); 3316 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3317 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6); 3318 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3319 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6); 3320 3321 ch->hw.status = ata_nvidia_status; 3322 ch->flags |= ATA_NO_SLAVE; 3323 3324 return 0; 3325 } 3326 3327 static int 3328 ata_nvidia_status(device_t dev) 3329 { 3330 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3331 struct ata_channel *ch = device_get_softc(dev); 3332 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3333 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2); 3334 u_int32_t istatus; 3335 3336 /* get interrupt status */ 3337 if (ctlr->chip->cfg2 & NVQ) 3338 istatus = ATA_INL(ctlr->r_res2, offset); 3339 else 3340 istatus = ATA_INB(ctlr->r_res2, offset); 3341 3342 /* do we have any PHY events ? */ 3343 if (istatus & (0x0c << shift)) 3344 ata_sata_phy_check_events(dev); 3345 3346 /* clear interrupt(s) */ 3347 if (ctlr->chip->cfg2 & NVQ) 3348 ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0); 3349 else 3350 ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift)); 3351 3352 /* do we have any device action ? */ 3353 return (istatus & (0x01 << shift)); 3354 } 3355 3356 static void 3357 ata_nvidia_reset(device_t dev) 3358 { 3359 if (ata_sata_phy_reset(dev)) 3360 ata_generic_reset(dev); 3361 } 3362 3363 3364 /* 3365 * Promise chipset support functions 3366 */ 3367 #define ATA_PDC_APKT_OFFSET 0x00000010 3368 #define ATA_PDC_HPKT_OFFSET 0x00000040 3369 #define ATA_PDC_ASG_OFFSET 0x00000080 3370 #define ATA_PDC_LSG_OFFSET 0x000000c0 3371 #define ATA_PDC_HSG_OFFSET 0x00000100 3372 #define ATA_PDC_CHN_OFFSET 0x00000400 3373 #define ATA_PDC_BUF_BASE 0x00400000 3374 #define ATA_PDC_BUF_OFFSET 0x00100000 3375 #define ATA_PDC_MAX_HPKT 8 3376 #define ATA_PDC_WRITE_REG 0x00 3377 #define ATA_PDC_WRITE_CTL 0x0e 3378 #define ATA_PDC_WRITE_END 0x08 3379 #define ATA_PDC_WAIT_NBUSY 0x10 3380 #define ATA_PDC_WAIT_READY 0x18 3381 #define ATA_PDC_1B 0x20 3382 #define ATA_PDC_2B 0x40 3383 3384 struct host_packet { 3385 u_int32_t addr; 3386 TAILQ_ENTRY(host_packet) chain; 3387 }; 3388 3389 struct ata_promise_sx4 { 3390 struct lock mtx; 3391 TAILQ_HEAD(, host_packet) queue; 3392 int busy; 3393 }; 3394 3395 int 3396 ata_promise_ident(device_t dev) 3397 { 3398 struct ata_pci_controller *ctlr = device_get_softc(dev); 3399 struct ata_chip_id *idx; 3400 static struct ata_chip_id ids[] = 3401 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" }, 3402 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" }, 3403 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" }, 3404 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" }, 3405 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" }, 3406 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" }, 3407 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" }, 3408 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" }, 3409 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" }, 3410 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" }, 3411 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" }, 3412 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" }, 3413 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" }, 3414 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" }, 3415 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" }, 3416 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" }, 3417 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" }, 3418 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" }, 3419 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" }, 3420 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" }, 3421 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" }, 3422 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" }, 3423 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" }, 3424 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" }, 3425 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" }, 3426 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" }, 3427 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" }, 3428 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" }, 3429 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" }, 3430 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" }, 3431 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" }, 3432 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" }, 3433 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" }, 3434 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" }, 3435 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" }, 3436 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" }, 3437 { 0, 0, 0, 0, 0, 0}}; 3438 char buffer[64]; 3439 uintptr_t devid = 0; 3440 3441 if (!(idx = ata_match_chip(dev, ids))) 3442 return ENXIO; 3443 3444 /* if we are on a SuperTrak SX6000 dont attach */ 3445 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3446 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3447 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3448 devid == ATA_I960RM) 3449 return ENXIO; 3450 3451 strcpy(buffer, "Promise "); 3452 strcat(buffer, idx->text); 3453 3454 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 3455 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3456 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3457 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3458 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 3459 static long start = 0, end = 0; 3460 3461 if (pci_get_slot(dev) == 1) { 3462 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 3463 strcat(buffer, " (channel 0+1)"); 3464 } 3465 else if (pci_get_slot(dev) == 2 && start && end) { 3466 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end, 3467 machintr_legacy_intr_cpuid(start)); 3468 strcat(buffer, " (channel 2+3)"); 3469 } 3470 else { 3471 start = end = 0; 3472 } 3473 } 3474 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 3475 device_set_desc_copy(dev, buffer); 3476 ctlr->chip = idx; 3477 ctlr->chipinit = ata_promise_chipinit; 3478 return 0; 3479 } 3480 3481 static int 3482 ata_promise_chipinit(device_t dev) 3483 { 3484 struct ata_pci_controller *ctlr = device_get_softc(dev); 3485 int fake_reg, stat_reg; 3486 3487 if (ata_setup_interrupt(dev)) 3488 return ENXIO; 3489 3490 switch (ctlr->chip->cfg1) { 3491 case PRNEW: 3492 /* setup clocks */ 3493 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 3494 3495 ctlr->dmainit = ata_promise_dmainit; 3496 /* FALLTHROUGH */ 3497 3498 case PROLD: 3499 /* enable burst mode */ 3500 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 3501 ctlr->allocate = ata_promise_allocate; 3502 ctlr->setmode = ata_promise_setmode; 3503 return 0; 3504 3505 case PRTX: 3506 ctlr->allocate = ata_promise_tx2_allocate; 3507 ctlr->setmode = ata_promise_setmode; 3508 return 0; 3509 3510 case PRMIO: 3511 ctlr->r_type1 = SYS_RES_MEMORY; 3512 ctlr->r_rid1 = PCIR_BAR(4); 3513 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 3514 &ctlr->r_rid1, RF_ACTIVE))) 3515 goto failnfree; 3516 3517 ctlr->r_type2 = SYS_RES_MEMORY; 3518 ctlr->r_rid2 = PCIR_BAR(3); 3519 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3520 &ctlr->r_rid2, RF_ACTIVE))) 3521 goto failnfree; 3522 3523 if (ctlr->chip->cfg2 == PRSX4X) { 3524 struct ata_promise_sx4 *hpkt; 3525 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 3526 3527 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3528 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3529 ata_promise_sx4_intr, ctlr, &ctlr->handle, NULL)) { 3530 device_printf(dev, "unable to setup interrupt\n"); 3531 goto failnfree; 3532 } 3533 3534 /* print info about cache memory */ 3535 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 3536 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 3537 ((dimm >> 24) & 0xff), 3538 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 3539 " ECC enabled" : "" ); 3540 3541 /* adjust cache memory parameters */ 3542 ATA_OUTL(ctlr->r_res2, 0x000c000c, 3543 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 3544 3545 /* setup host packet controls */ 3546 hpkt = kmalloc(sizeof(struct ata_promise_sx4), 3547 M_TEMP, M_INTWAIT | M_ZERO); 3548 lockinit(&hpkt->mtx, "chipinit", 0, 0); 3549 TAILQ_INIT(&hpkt->queue); 3550 hpkt->busy = 0; 3551 device_set_ivars(dev, hpkt); 3552 ctlr->allocate = ata_promise_mio_allocate; 3553 ctlr->reset = ata_promise_mio_reset; 3554 ctlr->dmainit = ata_promise_mio_dmainit; 3555 ctlr->setmode = ata_promise_setmode; 3556 ctlr->channels = 4; 3557 return 0; 3558 } 3559 3560 /* mio type controllers need an interrupt intercept */ 3561 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3562 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3563 ata_promise_mio_intr, ctlr, &ctlr->handle, NULL)) { 3564 device_printf(dev, "unable to setup interrupt\n"); 3565 goto failnfree; 3566 } 3567 3568 switch (ctlr->chip->cfg2) { 3569 case PRPATA: 3570 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 3571 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 3572 goto sata150; 3573 case PRCMBO: 3574 ctlr->channels = 3; 3575 goto sata150; 3576 case PRSATA: 3577 ctlr->channels = 4; 3578 sata150: 3579 fake_reg = 0x60; 3580 stat_reg = 0x6c; 3581 break; 3582 3583 case PRCMBO2: 3584 ctlr->channels = 3; 3585 goto sataii; 3586 case PRSATA2: 3587 default: 3588 ctlr->channels = 4; 3589 sataii: 3590 fake_reg = 0x54; 3591 stat_reg = 0x60; 3592 break; 3593 } 3594 3595 /* prime fake interrupt register */ 3596 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3597 3598 /* clear SATA status */ 3599 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 3600 3601 ctlr->allocate = ata_promise_mio_allocate; 3602 ctlr->reset = ata_promise_mio_reset; 3603 ctlr->dmainit = ata_promise_mio_dmainit; 3604 ctlr->setmode = ata_promise_mio_setmode; 3605 3606 return 0; 3607 } 3608 3609 failnfree: 3610 if (ctlr->r_res2) 3611 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 3612 if (ctlr->r_res1) 3613 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 3614 return ENXIO; 3615 } 3616 3617 static int 3618 ata_promise_allocate(device_t dev) 3619 { 3620 struct ata_channel *ch = device_get_softc(dev); 3621 3622 if (ata_pci_allocate(dev)) 3623 return ENXIO; 3624 3625 ch->hw.status = ata_promise_status; 3626 return 0; 3627 } 3628 3629 static int 3630 ata_promise_status(device_t dev) 3631 { 3632 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3633 struct ata_channel *ch = device_get_softc(dev); 3634 3635 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 3636 return ata_pci_status(dev); 3637 } 3638 return 0; 3639 } 3640 3641 static int 3642 ata_promise_dmastart(device_t dev) 3643 { 3644 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3645 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3646 struct ata_device *atadev = device_get_softc(dev); 3647 3648 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3649 ATA_OUTB(ctlr->r_res1, 0x11, 3650 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 3651 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 3652 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) | 3653 (ch->dma->cur_iosize >> 1)); 3654 } 3655 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 3656 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 3657 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus); 3658 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3659 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) | 3660 ATA_BMCMD_START_STOP); 3661 ch->flags |= ATA_DMA_ACTIVE; 3662 return 0; 3663 } 3664 3665 static int 3666 ata_promise_dmastop(device_t dev) 3667 { 3668 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3669 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3670 struct ata_device *atadev = device_get_softc(dev); 3671 int error; 3672 3673 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3674 ATA_OUTB(ctlr->r_res1, 0x11, 3675 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 3676 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 3677 } 3678 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 3679 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3680 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3681 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3682 ch->flags &= ~ATA_DMA_ACTIVE; 3683 return error; 3684 } 3685 3686 static void 3687 ata_promise_dmareset(device_t dev) 3688 { 3689 struct ata_channel *ch = device_get_softc(dev); 3690 3691 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3692 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3693 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3694 ch->flags &= ~ATA_DMA_ACTIVE; 3695 } 3696 3697 static void 3698 ata_promise_dmainit(device_t dev) 3699 { 3700 struct ata_channel *ch = device_get_softc(dev); 3701 3702 ata_dmainit(dev); 3703 if (ch->dma) { 3704 ch->dma->start = ata_promise_dmastart; 3705 ch->dma->stop = ata_promise_dmastop; 3706 ch->dma->reset = ata_promise_dmareset; 3707 } 3708 } 3709 3710 static void 3711 ata_promise_setmode(device_t dev, int mode) 3712 { 3713 device_t gparent = GRANDPARENT(dev); 3714 struct ata_pci_controller *ctlr = device_get_softc(gparent); 3715 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3716 struct ata_device *atadev = device_get_softc(dev); 3717 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3718 int error; 3719 u_int32_t timings[][2] = { 3720 /* PROLD PRNEW mode */ 3721 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 3722 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 3723 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 3724 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 3725 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 3726 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 3727 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 3728 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 3729 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 3730 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 3731 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 3732 { 0, 0x00424ef6 }, /* UDMA 3 */ 3733 { 0, 0x004127f3 }, /* UDMA 4 */ 3734 { 0, 0x004127f3 } /* UDMA 5 */ 3735 }; 3736 3737 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 3738 3739 switch (ctlr->chip->cfg1) { 3740 case PROLD: 3741 case PRNEW: 3742 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) & 3743 (ch->unit ? 1 << 11 : 1 << 10))) { 3744 ata_print_cable(dev, "controller"); 3745 mode = ATA_UDMA2; 3746 } 3747 if (ata_atapi(dev) && mode > ATA_PIO_MAX) 3748 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 3749 break; 3750 3751 case PRTX: 3752 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3753 if (mode > ATA_UDMA2 && 3754 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 3755 ata_print_cable(dev, "controller"); 3756 mode = ATA_UDMA2; 3757 } 3758 break; 3759 3760 case PRMIO: 3761 if (mode > ATA_UDMA2 && 3762 (ATA_INL(ctlr->r_res2, 3763 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) + 3764 (ch->unit << 7)) & 0x01000000)) { 3765 ata_print_cable(dev, "controller"); 3766 mode = ATA_UDMA2; 3767 } 3768 break; 3769 } 3770 3771 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3772 3773 if (bootverbose) 3774 device_printf(dev, "%ssetting %s on %s chip\n", 3775 (error) ? "FAILURE " : "", 3776 ata_mode2str(mode), ctlr->chip->text); 3777 if (!error) { 3778 if (ctlr->chip->cfg1 < PRTX) 3779 pci_write_config(gparent, 0x60 + (devno << 2), 3780 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 3781 atadev->mode = mode; 3782 } 3783 return; 3784 } 3785 3786 static int 3787 ata_promise_tx2_allocate(device_t dev) 3788 { 3789 struct ata_channel *ch = device_get_softc(dev); 3790 3791 if (ata_pci_allocate(dev)) 3792 return ENXIO; 3793 3794 ch->hw.status = ata_promise_tx2_status; 3795 return 0; 3796 } 3797 3798 static int 3799 ata_promise_tx2_status(device_t dev) 3800 { 3801 struct ata_channel *ch = device_get_softc(dev); 3802 3803 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3804 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 3805 return ata_pci_status(dev); 3806 } 3807 return 0; 3808 } 3809 3810 static int 3811 ata_promise_mio_allocate(device_t dev) 3812 { 3813 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3814 struct ata_channel *ch = device_get_softc(dev); 3815 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0; 3816 int i; 3817 3818 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 3819 ch->r_io[i].res = ctlr->r_res2; 3820 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 3821 } 3822 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 3823 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 3824 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 3825 ata_default_registers(dev); 3826 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) || 3827 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) { 3828 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3829 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 3830 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3831 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 3832 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3833 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 3834 ch->flags |= ATA_NO_SLAVE; 3835 } 3836 ch->flags |= ATA_USE_16BIT; 3837 3838 ata_generic_hw(dev); 3839 if (ctlr->chip->cfg2 & PRSX4X) { 3840 ch->hw.command = ata_promise_sx4_command; 3841 } 3842 else { 3843 ch->hw.command = ata_promise_mio_command; 3844 ch->hw.status = ata_promise_mio_status; 3845 } 3846 return 0; 3847 } 3848 3849 static void 3850 ata_promise_mio_intr(void *data) 3851 { 3852 struct ata_pci_controller *ctlr = data; 3853 struct ata_channel *ch; 3854 u_int32_t vector; 3855 int unit, fake_reg; 3856 3857 switch (ctlr->chip->cfg2) { 3858 case PRPATA: 3859 case PRCMBO: 3860 case PRSATA: 3861 fake_reg = 0x60; 3862 break; 3863 case PRCMBO2: 3864 case PRSATA2: 3865 default: 3866 fake_reg = 0x54; 3867 break; 3868 } 3869 3870 /* 3871 * since reading interrupt status register on early "mio" chips 3872 * clears the status bits we cannot read it for each channel later on 3873 * in the generic interrupt routine. 3874 * store the bits in an unused register in the chip so we can read 3875 * it from there safely to get around this "feature". 3876 */ 3877 vector = ATA_INL(ctlr->r_res2, 0x040); 3878 ATA_OUTL(ctlr->r_res2, 0x040, vector); 3879 ATA_OUTL(ctlr->r_res2, fake_reg, vector); 3880 3881 for (unit = 0; unit < ctlr->channels; unit++) { 3882 if ((ch = ctlr->interrupt[unit].argument)) 3883 ctlr->interrupt[unit].function(ch); 3884 } 3885 3886 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3887 } 3888 3889 static int 3890 ata_promise_mio_status(device_t dev) 3891 { 3892 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3893 struct ata_channel *ch = device_get_softc(dev); 3894 struct ata_connect_task *tp; 3895 u_int32_t fake_reg, stat_reg, vector, status; 3896 3897 switch (ctlr->chip->cfg2) { 3898 case PRPATA: 3899 case PRCMBO: 3900 case PRSATA: 3901 fake_reg = 0x60; 3902 stat_reg = 0x6c; 3903 break; 3904 case PRCMBO2: 3905 case PRSATA2: 3906 default: 3907 fake_reg = 0x54; 3908 stat_reg = 0x60; 3909 break; 3910 } 3911 3912 /* read and acknowledge interrupt */ 3913 vector = ATA_INL(ctlr->r_res2, fake_reg); 3914 3915 /* read and clear interface status */ 3916 status = ATA_INL(ctlr->r_res2, stat_reg); 3917 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 3918 3919 /* check for and handle disconnect events */ 3920 if ((status & (0x00000001 << ch->unit)) && 3921 (tp = (struct ata_connect_task *) 3922 kmalloc(sizeof(struct ata_connect_task), 3923 M_ATA, M_INTWAIT | M_ZERO))) { 3924 3925 if (bootverbose) 3926 device_printf(ch->dev, "DISCONNECT requested\n"); 3927 tp->action = ATA_C_DETACH; 3928 tp->dev = ch->dev; 3929 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3930 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3931 } 3932 3933 /* check for and handle connect events */ 3934 if ((status & (0x00000010 << ch->unit)) && 3935 (tp = (struct ata_connect_task *) 3936 kmalloc(sizeof(struct ata_connect_task), 3937 M_ATA, M_INTWAIT | M_ZERO))) { 3938 3939 if (bootverbose) 3940 device_printf(ch->dev, "CONNECT requested\n"); 3941 tp->action = ATA_C_ATTACH; 3942 tp->dev = ch->dev; 3943 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3944 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3945 } 3946 3947 /* do we have any device action ? */ 3948 return (vector & (1 << (ch->unit + 1))); 3949 } 3950 3951 static int 3952 ata_promise_mio_command(struct ata_request *request) 3953 { 3954 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 3955 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 3956 u_int32_t *wordp = (u_int32_t *)ch->dma->work; 3957 3958 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 3959 3960 /* XXX SOS add ATAPI commands support later */ 3961 switch (request->u.ata.command) { 3962 default: 3963 return ata_generic_command(request); 3964 3965 case ATA_READ_DMA: 3966 case ATA_READ_DMA48: 3967 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3968 break; 3969 3970 case ATA_WRITE_DMA: 3971 case ATA_WRITE_DMA48: 3972 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3973 break; 3974 } 3975 wordp[1] = htole32(ch->dma->sg_bus); 3976 wordp[2] = 0; 3977 ata_promise_apkt((u_int8_t*)wordp, request); 3978 3979 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus); 3980 return 0; 3981 } 3982 3983 static void 3984 ata_promise_mio_reset(device_t dev) 3985 { 3986 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3987 struct ata_channel *ch = device_get_softc(dev); 3988 struct ata_promise_sx4 *hpktp; 3989 3990 switch (ctlr->chip->cfg2) { 3991 case PRSX4X: 3992 3993 /* softreset channel ATA module */ 3994 hpktp = device_get_ivars(ctlr->dev); 3995 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 3996 ata_udelay(1000); 3997 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 3998 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 3999 ~0x00003f9f) | (ch->unit + 1)); 4000 4001 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 4002 lockmgr(&hpktp->mtx, LK_EXCLUSIVE); 4003 ATA_OUTL(ctlr->r_res2, 0xc012c, 4004 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 4005 DELAY(10); 4006 ATA_OUTL(ctlr->r_res2, 0xc012c, 4007 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 4008 hpktp->busy = 0; 4009 lockmgr(&hpktp->mtx, LK_RELEASE); 4010 ata_generic_reset(dev); 4011 break; 4012 4013 case PRPATA: 4014 case PRCMBO: 4015 case PRSATA: 4016 if ((ctlr->chip->cfg2 == PRSATA) || 4017 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 4018 4019 /* mask plug/unplug intr */ 4020 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 4021 } 4022 4023 /* softreset channels ATA module */ 4024 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 4025 ata_udelay(10000); 4026 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 4027 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 4028 ~0x00003f9f) | (ch->unit + 1)); 4029 4030 if ((ctlr->chip->cfg2 == PRSATA) || 4031 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 4032 4033 if (ata_sata_phy_reset(dev)) 4034 ata_generic_reset(dev); 4035 4036 /* reset and enable plug/unplug intr */ 4037 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 4038 } 4039 else 4040 ata_generic_reset(dev); 4041 break; 4042 4043 case PRCMBO2: 4044 case PRSATA2: 4045 if ((ctlr->chip->cfg2 == PRSATA2) || 4046 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 4047 /* set portmultiplier port */ 4048 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 4049 4050 /* mask plug/unplug intr */ 4051 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 4052 } 4053 4054 /* softreset channels ATA module */ 4055 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 4056 ata_udelay(10000); 4057 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 4058 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 4059 ~0x00003f9f) | (ch->unit + 1)); 4060 4061 if ((ctlr->chip->cfg2 == PRSATA2) || 4062 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 4063 4064 /* set PHY mode to "improved" */ 4065 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 4066 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 4067 ~0x00000003) | 0x00000001); 4068 4069 if (ata_sata_phy_reset(dev)) 4070 ata_generic_reset(dev); 4071 4072 /* reset and enable plug/unplug intr */ 4073 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 4074 4075 /* set portmultiplier port */ 4076 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 4077 } 4078 else 4079 ata_generic_reset(dev); 4080 break; 4081 4082 } 4083 } 4084 4085 static void 4086 ata_promise_mio_dmainit(device_t dev) 4087 { 4088 /* note start and stop are not used here */ 4089 ata_dmainit(dev); 4090 } 4091 4092 static void 4093 ata_promise_mio_setmode(device_t dev, int mode) 4094 { 4095 device_t gparent = GRANDPARENT(dev); 4096 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4097 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4098 4099 if ( (ctlr->chip->cfg2 == PRSATA) || 4100 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) || 4101 (ctlr->chip->cfg2 == PRSATA2) || 4102 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) 4103 ata_sata_setmode(dev, mode); 4104 else 4105 ata_promise_setmode(dev, mode); 4106 } 4107 4108 static void 4109 ata_promise_sx4_intr(void *data) 4110 { 4111 struct ata_pci_controller *ctlr = data; 4112 struct ata_channel *ch; 4113 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 4114 int unit; 4115 4116 for (unit = 0; unit < ctlr->channels; unit++) { 4117 if (vector & (1 << (unit + 1))) 4118 if ((ch = ctlr->interrupt[unit].argument)) 4119 ctlr->interrupt[unit].function(ch); 4120 if (vector & (1 << (unit + 5))) 4121 if ((ch = ctlr->interrupt[unit].argument)) 4122 ata_promise_queue_hpkt(ctlr, 4123 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 4124 ATA_PDC_HPKT_OFFSET)); 4125 if (vector & (1 << (unit + 9))) { 4126 ata_promise_next_hpkt(ctlr); 4127 if ((ch = ctlr->interrupt[unit].argument)) 4128 ctlr->interrupt[unit].function(ch); 4129 } 4130 if (vector & (1 << (unit + 13))) { 4131 ata_promise_next_hpkt(ctlr); 4132 if ((ch = ctlr->interrupt[unit].argument)) 4133 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4134 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 4135 ATA_PDC_APKT_OFFSET)); 4136 } 4137 } 4138 } 4139 4140 static int 4141 ata_promise_sx4_command(struct ata_request *request) 4142 { 4143 device_t gparent = GRANDPARENT(request->dev); 4144 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4145 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4146 struct ata_dma_prdentry *prd = ch->dma->sg; 4147 caddr_t window = rman_get_virtual(ctlr->r_res1); 4148 u_int32_t *wordp; 4149 int i, idx, length = 0; 4150 4151 /* XXX SOS add ATAPI commands support later */ 4152 switch (request->u.ata.command) { 4153 4154 default: 4155 return -1; 4156 4157 case ATA_ATA_IDENTIFY: 4158 case ATA_READ: 4159 case ATA_READ48: 4160 case ATA_READ_MUL: 4161 case ATA_READ_MUL48: 4162 case ATA_WRITE: 4163 case ATA_WRITE48: 4164 case ATA_WRITE_MUL: 4165 case ATA_WRITE_MUL48: 4166 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4167 return ata_generic_command(request); 4168 4169 case ATA_SETFEATURES: 4170 case ATA_FLUSHCACHE: 4171 case ATA_FLUSHCACHE48: 4172 case ATA_SLEEP: 4173 case ATA_SET_MULTI: 4174 wordp = (u_int32_t *) 4175 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4176 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 4177 wordp[1] = 0; 4178 wordp[2] = 0; 4179 ata_promise_apkt((u_int8_t *)wordp, request); 4180 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4181 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4182 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4183 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 4184 return 0; 4185 4186 case ATA_READ_DMA: 4187 case ATA_READ_DMA48: 4188 case ATA_WRITE_DMA: 4189 case ATA_WRITE_DMA48: 4190 wordp = (u_int32_t *) 4191 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 4192 i = idx = 0; 4193 do { 4194 wordp[idx++] = prd[i].addr; 4195 wordp[idx++] = prd[i].count; 4196 length += (prd[i].count & ~ATA_DMA_EOT); 4197 } while (!(prd[i++].count & ATA_DMA_EOT)); 4198 4199 wordp = (u_int32_t *) 4200 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 4201 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4202 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4203 4204 wordp = (u_int32_t *) 4205 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 4206 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4207 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4208 4209 wordp = (u_int32_t *) 4210 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 4211 if (request->flags & ATA_R_READ) 4212 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 4213 if (request->flags & ATA_R_WRITE) 4214 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 4215 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 4216 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 4217 wordp[3] = 0; 4218 4219 wordp = (u_int32_t *) 4220 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4221 if (request->flags & ATA_R_READ) 4222 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 4223 if (request->flags & ATA_R_WRITE) 4224 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 4225 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 4226 wordp[2] = 0; 4227 ata_promise_apkt((u_int8_t *)wordp, request); 4228 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4229 4230 if (request->flags & ATA_R_READ) { 4231 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 4232 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 4233 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4234 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 4235 } 4236 if (request->flags & ATA_R_WRITE) { 4237 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 4238 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 4239 ata_promise_queue_hpkt(ctlr, 4240 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 4241 } 4242 return 0; 4243 } 4244 } 4245 4246 static int 4247 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 4248 { 4249 struct ata_device *atadev = device_get_softc(request->dev); 4250 int i = 12; 4251 4252 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 4253 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit; 4254 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 4255 bytep[i++] = ATA_A_4BIT; 4256 4257 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 4258 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4259 bytep[i++] = request->u.ata.feature >> 8; 4260 bytep[i++] = request->u.ata.feature; 4261 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 4262 bytep[i++] = request->u.ata.count >> 8; 4263 bytep[i++] = request->u.ata.count; 4264 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4265 bytep[i++] = request->u.ata.lba >> 24; 4266 bytep[i++] = request->u.ata.lba; 4267 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4268 bytep[i++] = request->u.ata.lba >> 32; 4269 bytep[i++] = request->u.ata.lba >> 8; 4270 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4271 bytep[i++] = request->u.ata.lba >> 40; 4272 bytep[i++] = request->u.ata.lba >> 16; 4273 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4274 bytep[i++] = ATA_D_LBA | atadev->unit; 4275 } 4276 else { 4277 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4278 bytep[i++] = request->u.ata.feature; 4279 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 4280 bytep[i++] = request->u.ata.count; 4281 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4282 bytep[i++] = request->u.ata.lba; 4283 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4284 bytep[i++] = request->u.ata.lba >> 8; 4285 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4286 bytep[i++] = request->u.ata.lba >> 16; 4287 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4288 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) | 4289 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf); 4290 } 4291 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 4292 bytep[i++] = request->u.ata.command; 4293 return i; 4294 } 4295 4296 static void 4297 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 4298 { 4299 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4300 4301 lockmgr(&hpktp->mtx, LK_EXCLUSIVE); 4302 if (hpktp->busy) { 4303 struct host_packet *hp = 4304 kmalloc(sizeof(struct host_packet), M_TEMP, M_INTWAIT | M_ZERO); 4305 hp->addr = hpkt; 4306 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 4307 } 4308 else { 4309 hpktp->busy = 1; 4310 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 4311 } 4312 lockmgr(&hpktp->mtx, LK_RELEASE); 4313 } 4314 4315 static void 4316 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 4317 { 4318 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4319 struct host_packet *hp; 4320 4321 lockmgr(&hpktp->mtx, LK_EXCLUSIVE); 4322 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 4323 TAILQ_REMOVE(&hpktp->queue, hp, chain); 4324 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 4325 kfree(hp, M_TEMP); 4326 } 4327 else 4328 hpktp->busy = 0; 4329 lockmgr(&hpktp->mtx, LK_RELEASE); 4330 } 4331 4332 4333 /* 4334 * ServerWorks chipset support functions 4335 */ 4336 int 4337 ata_serverworks_ident(device_t dev) 4338 { 4339 struct ata_pci_controller *ctlr = device_get_softc(dev); 4340 struct ata_chip_id *idx; 4341 static struct ata_chip_id ids[] = 4342 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" }, 4343 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" }, 4344 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" }, 4345 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" }, 4346 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" }, 4347 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" }, 4348 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" }, 4349 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" }, 4350 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" }, 4351 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" }, 4352 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" }, 4353 { 0, 0, 0, 0, 0, 0}}; 4354 char buffer[64]; 4355 4356 if (!(idx = ata_match_chip(dev, ids))) 4357 return ENXIO; 4358 4359 ksprintf(buffer, "ServerWorks %s %s controller", 4360 idx->text, ata_mode2str(idx->max_dma)); 4361 device_set_desc_copy(dev, buffer); 4362 ctlr->chip = idx; 4363 ctlr->chipinit = ata_serverworks_chipinit; 4364 return 0; 4365 } 4366 4367 static int 4368 ata_serverworks_chipinit(device_t dev) 4369 { 4370 struct ata_pci_controller *ctlr = device_get_softc(dev); 4371 4372 if (ata_setup_interrupt(dev)) 4373 return ENXIO; 4374 4375 if (ctlr->chip->cfg1 == SWKSMIO) { 4376 ctlr->r_type2 = SYS_RES_MEMORY; 4377 ctlr->r_rid2 = PCIR_BAR(5); 4378 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4379 &ctlr->r_rid2, RF_ACTIVE))){ 4380 ata_teardown_interrupt(dev); 4381 return ENXIO; 4382 } 4383 4384 ctlr->channels = ctlr->chip->cfg2; 4385 ctlr->allocate = ata_serverworks_allocate; 4386 ctlr->setmode = ata_sata_setmode; 4387 return 0; 4388 } 4389 else if (ctlr->chip->cfg1 == SWKS33) { 4390 device_t *children; 4391 int nchildren, i; 4392 4393 /* locate the ISA part in the southbridge and enable UDMA33 */ 4394 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 4395 for (i = 0; i < nchildren; i++) { 4396 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 4397 pci_write_config(children[i], 0x64, 4398 (pci_read_config(children[i], 0x64, 4) & 4399 ~0x00002000) | 0x00004000, 4); 4400 break; 4401 } 4402 } 4403 kfree(children, M_TEMP); 4404 } 4405 } 4406 else { 4407 pci_write_config(dev, 0x5a, 4408 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 4409 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1); 4410 } 4411 ctlr->setmode = ata_serverworks_setmode; 4412 return 0; 4413 } 4414 4415 static int 4416 ata_serverworks_allocate(device_t dev) 4417 { 4418 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4419 struct ata_channel *ch = device_get_softc(dev); 4420 int ch_offset; 4421 int i; 4422 4423 ch_offset = ch->unit * 0x100; 4424 4425 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 4426 ch->r_io[i].res = ctlr->r_res2; 4427 4428 /* setup ATA registers */ 4429 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 4430 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 4431 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 4432 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 4433 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 4434 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 4435 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 4436 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 4437 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 4438 ata_default_registers(dev); 4439 4440 /* setup DMA registers */ 4441 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 4442 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 4443 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 4444 4445 /* setup SATA registers */ 4446 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 4447 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 4448 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 4449 4450 ch->flags |= ATA_NO_SLAVE; 4451 ata_pci_hw(dev); 4452 4453 /* chip does not reliably do 64K DMA transfers */ 4454 if (ch->dma) 4455 ch->dma->max_iosize = 126 * DEV_BSIZE; 4456 4457 return 0; 4458 } 4459 4460 static void 4461 ata_serverworks_setmode(device_t dev, int mode) 4462 { 4463 device_t gparent = GRANDPARENT(dev); 4464 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4465 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4466 struct ata_device *atadev = device_get_softc(dev); 4467 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4468 int offset = (devno ^ 0x01) << 3; 4469 int error; 4470 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 4471 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 4472 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 4473 4474 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4475 4476 mode = ata_check_80pin(dev, mode); 4477 4478 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4479 4480 if (bootverbose) 4481 device_printf(dev, "%ssetting %s on %s chip\n", 4482 (error) ? "FAILURE " : "", 4483 ata_mode2str(mode), ctlr->chip->text); 4484 if (!error) { 4485 if (mode >= ATA_UDMA0) { 4486 pci_write_config(gparent, 0x56, 4487 (pci_read_config(gparent, 0x56, 2) & 4488 ~(0xf << (devno << 2))) | 4489 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 4490 pci_write_config(gparent, 0x54, 4491 pci_read_config(gparent, 0x54, 1) | 4492 (0x01 << devno), 1); 4493 pci_write_config(gparent, 0x44, 4494 (pci_read_config(gparent, 0x44, 4) & 4495 ~(0xff << offset)) | 4496 (dmatimings[2] << offset), 4); 4497 } 4498 else if (mode >= ATA_WDMA0) { 4499 pci_write_config(gparent, 0x54, 4500 pci_read_config(gparent, 0x54, 1) & 4501 ~(0x01 << devno), 1); 4502 pci_write_config(gparent, 0x44, 4503 (pci_read_config(gparent, 0x44, 4) & 4504 ~(0xff << offset)) | 4505 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 4506 } 4507 else 4508 pci_write_config(gparent, 0x54, 4509 pci_read_config(gparent, 0x54, 1) & 4510 ~(0x01 << devno), 1); 4511 4512 pci_write_config(gparent, 0x40, 4513 (pci_read_config(gparent, 0x40, 4) & 4514 ~(0xff << offset)) | 4515 (piotimings[ata_mode2idx(mode)] << offset), 4); 4516 atadev->mode = mode; 4517 } 4518 } 4519 4520 4521 /* 4522 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 4523 */ 4524 int 4525 ata_sii_ident(device_t dev) 4526 { 4527 struct ata_pci_controller *ctlr = device_get_softc(dev); 4528 struct ata_chip_id *idx; 4529 static struct ata_chip_id ids[] = 4530 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" }, 4531 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" }, 4532 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4533 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4534 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" }, 4535 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4536 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4537 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" }, 4538 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" }, 4539 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" }, 4540 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" }, 4541 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" }, 4542 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" }, 4543 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" }, 4544 { 0, 0, 0, 0, 0, 0}}; 4545 char buffer[64]; 4546 4547 if (!(idx = ata_match_chip(dev, ids))) 4548 return ENXIO; 4549 4550 ksprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); 4551 device_set_desc_copy(dev, buffer); 4552 ctlr->chip = idx; 4553 ctlr->chipinit = ata_sii_chipinit; 4554 return 0; 4555 } 4556 4557 static int 4558 ata_sii_chipinit(device_t dev) 4559 { 4560 struct ata_pci_controller *ctlr = device_get_softc(dev); 4561 4562 if (ata_setup_interrupt(dev)) 4563 return ENXIO; 4564 4565 switch (ctlr->chip->cfg1) { 4566 case SIIPRBIO: 4567 ctlr->r_type1 = SYS_RES_MEMORY; 4568 ctlr->r_rid1 = PCIR_BAR(0); 4569 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 4570 &ctlr->r_rid1, RF_ACTIVE))){ 4571 ata_teardown_interrupt(dev); 4572 return ENXIO; 4573 } 4574 4575 ctlr->r_rid2 = PCIR_BAR(2); 4576 ctlr->r_type2 = SYS_RES_MEMORY; 4577 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4578 &ctlr->r_rid2, RF_ACTIVE))){ 4579 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 4580 ata_teardown_interrupt(dev); 4581 return ENXIO; 4582 } 4583 ctlr->allocate = ata_siiprb_allocate; 4584 ctlr->reset = ata_siiprb_reset; 4585 ctlr->dmainit = ata_siiprb_dmainit; 4586 ctlr->setmode = ata_sata_setmode; 4587 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2; 4588 4589 /* reset controller */ 4590 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 4591 DELAY(10000); 4592 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 4593 4594 /* enable PCI interrupt */ 4595 pci_write_config(dev, PCIR_COMMAND, 4596 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 4597 break; 4598 4599 case SIIMEMIO: 4600 ctlr->r_type2 = SYS_RES_MEMORY; 4601 ctlr->r_rid2 = PCIR_BAR(5); 4602 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4603 &ctlr->r_rid2, RF_ACTIVE))){ 4604 ata_teardown_interrupt(dev); 4605 return ENXIO; 4606 } 4607 4608 if (ctlr->chip->cfg2 & SIISETCLK) { 4609 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4610 pci_write_config(dev, 0x8a, 4611 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 4612 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4613 device_printf(dev, "%s could not set ATA133 clock\n", 4614 ctlr->chip->text); 4615 } 4616 4617 /* if we have 4 channels enable the second set */ 4618 if (ctlr->chip->cfg2 & SII4CH) { 4619 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 4620 ctlr->channels = 4; 4621 } 4622 4623 /* dont block interrupts from any channel */ 4624 pci_write_config(dev, 0x48, 4625 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 4626 4627 /* enable PCI interrupt as BIOS might not */ 4628 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 4629 4630 ctlr->allocate = ata_sii_allocate; 4631 if (ctlr->chip->max_dma >= ATA_SA150) { 4632 ctlr->reset = ata_sii_reset; 4633 ctlr->setmode = ata_sata_setmode; 4634 } 4635 else 4636 ctlr->setmode = ata_sii_setmode; 4637 break; 4638 4639 default: 4640 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 4641 device_printf(dev, "HW has secondary channel disabled\n"); 4642 ctlr->channels = 1; 4643 } 4644 4645 /* enable interrupt as BIOS might not */ 4646 pci_write_config(dev, 0x71, 0x01, 1); 4647 4648 ctlr->allocate = ata_cmd_allocate; 4649 ctlr->setmode = ata_cmd_setmode; 4650 break; 4651 } 4652 return 0; 4653 } 4654 4655 static int 4656 ata_cmd_allocate(device_t dev) 4657 { 4658 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4659 struct ata_channel *ch = device_get_softc(dev); 4660 4661 /* setup the usual register normal pci style */ 4662 if (ata_pci_allocate(dev)) 4663 return ENXIO; 4664 4665 if (ctlr->chip->cfg2 & SIIINTR) 4666 ch->hw.status = ata_cmd_status; 4667 4668 return 0; 4669 } 4670 4671 static int 4672 ata_cmd_status(device_t dev) 4673 { 4674 struct ata_channel *ch = device_get_softc(dev); 4675 u_int8_t reg71; 4676 4677 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) & 4678 (ch->unit ? 0x08 : 0x04))) { 4679 pci_write_config(device_get_parent(ch->dev), 0x71, 4680 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 4681 return ata_pci_status(dev); 4682 } 4683 return 0; 4684 } 4685 4686 static void 4687 ata_cmd_setmode(device_t dev, int mode) 4688 { 4689 device_t gparent = GRANDPARENT(dev); 4690 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4691 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4692 struct ata_device *atadev = device_get_softc(dev); 4693 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4694 int error; 4695 4696 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4697 4698 mode = ata_check_80pin(dev, mode); 4699 4700 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4701 4702 if (bootverbose) 4703 device_printf(dev, "%ssetting %s on %s chip\n", 4704 (error) ? "FAILURE " : "", 4705 ata_mode2str(mode), ctlr->chip->text); 4706 if (!error) { 4707 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 4708 int ureg = ch->unit ? 0x7b : 0x73; 4709 4710 if (mode >= ATA_UDMA0) { 4711 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 4712 { 0x11, 0x42 }, { 0x25, 0x8a }, 4713 { 0x15, 0x4a }, { 0x05, 0x0a } }; 4714 4715 u_int8_t umode = pci_read_config(gparent, ureg, 1); 4716 4717 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca); 4718 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)]; 4719 pci_write_config(gparent, ureg, umode, 1); 4720 } 4721 else if (mode >= ATA_WDMA0) { 4722 int dmatimings[] = { 0x87, 0x32, 0x3f }; 4723 4724 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1); 4725 pci_write_config(gparent, ureg, 4726 pci_read_config(gparent, ureg, 1) & 4727 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4728 } 4729 else { 4730 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f }; 4731 pci_write_config(gparent, treg, 4732 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1); 4733 pci_write_config(gparent, ureg, 4734 pci_read_config(gparent, ureg, 1) & 4735 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4736 } 4737 atadev->mode = mode; 4738 } 4739 } 4740 4741 static int 4742 ata_sii_allocate(device_t dev) 4743 { 4744 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4745 struct ata_channel *ch = device_get_softc(dev); 4746 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 4747 int i; 4748 4749 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 4750 ch->r_io[i].res = ctlr->r_res2; 4751 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 4752 } 4753 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 4754 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 4755 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 4756 ata_default_registers(dev); 4757 4758 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 4759 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 4760 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 4761 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 4762 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 4763 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 4764 4765 if (ctlr->chip->max_dma >= ATA_SA150) { 4766 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4767 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 4768 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4769 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 4770 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4771 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 4772 ch->flags |= ATA_NO_SLAVE; 4773 4774 /* enable PHY state change interrupt */ 4775 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 4776 } 4777 4778 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) { 4779 /* work around errata in early chips */ 4780 ch->dma->boundary = 16 * DEV_BSIZE; 4781 ch->dma->segsize = 15 * DEV_BSIZE; 4782 } 4783 4784 ata_pci_hw(dev); 4785 ch->hw.status = ata_sii_status; 4786 return 0; 4787 } 4788 4789 static int 4790 ata_sii_status(device_t dev) 4791 { 4792 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4793 struct ata_channel *ch = device_get_softc(dev); 4794 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 4795 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 4796 4797 /* do we have any PHY events ? */ 4798 if (ctlr->chip->max_dma >= ATA_SA150 && 4799 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 4800 ata_sata_phy_check_events(dev); 4801 4802 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 4803 return ata_pci_status(dev); 4804 else 4805 return 0; 4806 } 4807 4808 static void 4809 ata_sii_reset(device_t dev) 4810 { 4811 if (ata_sata_phy_reset(dev)) 4812 ata_generic_reset(dev); 4813 } 4814 4815 static void 4816 ata_sii_setmode(device_t dev, int mode) 4817 { 4818 device_t gparent = GRANDPARENT(dev); 4819 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4820 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4821 struct ata_device *atadev = device_get_softc(dev); 4822 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1); 4823 int mreg = ch->unit ? 0x84 : 0x80; 4824 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2); 4825 int mval = pci_read_config(gparent, mreg, 1) & ~mask; 4826 int error; 4827 4828 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4829 4830 if (ctlr->chip->cfg2 & SIISETCLK) { 4831 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) & 4832 (ch->unit ? 0x02 : 0x01))) { 4833 ata_print_cable(dev, "controller"); 4834 mode = ATA_UDMA2; 4835 } 4836 } 4837 else 4838 mode = ata_check_80pin(dev, mode); 4839 4840 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4841 4842 if (bootverbose) 4843 device_printf(dev, "%ssetting %s on %s chip\n", 4844 (error) ? "FAILURE " : "", 4845 ata_mode2str(mode), ctlr->chip->text); 4846 if (error) 4847 return; 4848 4849 if (mode >= ATA_UDMA0) { 4850 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 4851 u_int8_t ureg = 0xac + rego; 4852 4853 pci_write_config(gparent, mreg, 4854 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1); 4855 pci_write_config(gparent, ureg, 4856 (pci_read_config(gparent, ureg, 1) & ~0x3f) | 4857 udmatimings[mode & ATA_MODE_MASK], 1); 4858 4859 } 4860 else if (mode >= ATA_WDMA0) { 4861 u_int8_t dreg = 0xa8 + rego; 4862 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 4863 4864 pci_write_config(gparent, mreg, 4865 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1); 4866 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 4867 4868 } 4869 else { 4870 u_int8_t preg = 0xa4 + rego; 4871 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 4872 4873 pci_write_config(gparent, mreg, 4874 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1); 4875 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2); 4876 } 4877 atadev->mode = mode; 4878 } 4879 4880 struct ata_siiprb_dma_prdentry { 4881 u_int64_t addr; 4882 u_int32_t count; 4883 u_int32_t control; 4884 } __packed; 4885 4886 struct ata_siiprb_ata_command { 4887 u_int32_t reserved0; 4888 struct ata_siiprb_dma_prdentry prd[126]; 4889 } __packed; 4890 4891 struct ata_siiprb_atapi_command { 4892 u_int8_t cdb[16]; 4893 struct ata_siiprb_dma_prdentry prd[125]; 4894 } __packed; 4895 4896 struct ata_siiprb_command { 4897 u_int16_t control; 4898 u_int16_t protocol_override; 4899 u_int32_t transfer_count; 4900 u_int8_t fis[20]; 4901 union { 4902 struct ata_siiprb_ata_command ata; 4903 struct ata_siiprb_atapi_command atapi; 4904 } u; 4905 } __packed; 4906 4907 static int 4908 ata_siiprb_allocate(device_t dev) 4909 { 4910 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4911 struct ata_channel *ch = device_get_softc(dev); 4912 int offset = ch->unit * 0x2000; 4913 4914 /* set the SATA resources */ 4915 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4916 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 4917 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4918 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 4919 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4920 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 4921 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 4922 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 4923 4924 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 4925 ch->hw.end_transaction = ata_siiprb_end_transaction; 4926 ch->hw.status = ata_siiprb_status; 4927 ch->hw.command = NULL; /* not used here */ 4928 return 0; 4929 } 4930 4931 static int 4932 ata_siiprb_status(device_t dev) 4933 { 4934 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4935 struct ata_channel *ch = device_get_softc(dev); 4936 int offset = ch->unit * 0x2000; 4937 4938 if ((ATA_INL(ctlr->r_res1, 0x0044) & (1 << ch->unit))) { 4939 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 4940 4941 /* do we have any PHY events ? */ 4942 ata_sata_phy_check_events(dev); 4943 4944 /* clear interrupt(s) */ 4945 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 4946 4947 /* do we have any device action ? */ 4948 return (istatus & 0x00000001); 4949 } 4950 return 0; 4951 } 4952 4953 static int 4954 ata_siiprb_begin_transaction(struct ata_request *request) 4955 { 4956 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 4957 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4958 struct ata_siiprb_command *prb; 4959 int offset = ch->unit * 0x2000; 4960 u_int64_t prb_bus; 4961 int tag = 0, dummy; 4962 4963 /* check for 48 bit access and convert if needed */ 4964 ata_modify_if_48bit(request); 4965 4966 /* get a piece of the workspace for this request */ 4967 prb = (struct ata_siiprb_command *) 4968 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 4969 4970 /* set basic prd options ata/atapi etc etc */ 4971 bzero(prb, sizeof(struct ata_siiprb_command)); 4972 4973 /* setup the FIS for this request */ 4974 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 4975 device_printf(request->dev, "setting up SATA FIS failed\n"); 4976 request->result = EIO; 4977 return ATA_OP_FINISHED; 4978 } 4979 4980 /* if request moves data setup and load SG list */ 4981 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 4982 struct ata_siiprb_dma_prdentry *prd; 4983 4984 if (request->flags & ATA_R_ATAPI) 4985 prd = &prb->u.atapi.prd[0]; 4986 else 4987 prd = &prb->u.ata.prd[0]; 4988 if (ch->dma->load(ch->dev, request->data, request->bytecount, 4989 request->flags & ATA_R_READ, prd, &dummy)) { 4990 device_printf(request->dev, "setting up DMA failed\n"); 4991 request->result = EIO; 4992 return ATA_OP_FINISHED; 4993 } 4994 } 4995 4996 /* activate the prb */ 4997 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 4998 ATA_OUTL(ctlr->r_res2, 4999 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 5000 ATA_OUTL(ctlr->r_res2, 5001 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 5002 5003 /* start the timeout */ 5004 callout_reset(&request->callout, request->timeout * hz, 5005 (timeout_t*)ata_timeout, request); 5006 return ATA_OP_CONTINUES; 5007 } 5008 5009 static int 5010 ata_siiprb_end_transaction(struct ata_request *request) 5011 { 5012 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 5013 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 5014 struct ata_siiprb_command *prb; 5015 int offset = ch->unit * 0x2000; 5016 int error, tag = 0; 5017 5018 /* kill the timeout */ 5019 callout_stop_sync(&request->callout); 5020 5021 prb = (struct ata_siiprb_command *) 5022 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 5023 5024 /* if error status get details */ 5025 request->status = prb->fis[2]; 5026 if (request->status & ATA_S_ERROR) 5027 request->error = prb->fis[3]; 5028 5029 /* update progress */ 5030 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 5031 if (request->flags & ATA_R_READ) 5032 request->donecount = prb->transfer_count; 5033 else 5034 request->donecount = request->bytecount; 5035 } 5036 5037 /* any controller errors flagged ? */ 5038 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 5039 kprintf("ata_siiprb_end_transaction %s error=%08x\n", 5040 ata_cmd2str(request), error); 5041 } 5042 5043 /* release SG list etc */ 5044 ch->dma->unload(ch->dev); 5045 5046 return ATA_OP_FINISHED; 5047 } 5048 5049 static void 5050 ata_siiprb_reset(device_t dev) 5051 { 5052 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5053 struct ata_channel *ch = device_get_softc(dev); 5054 int offset = ch->unit * 0x2000; 5055 struct ata_siiprb_command *prb; 5056 u_int64_t prb_bus; 5057 u_int32_t status, signature; 5058 int timeout, tag = 0; 5059 5060 /* reset channel HW */ 5061 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 5062 DELAY(1000); 5063 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 5064 DELAY(10000); 5065 5066 /* poll for channel ready */ 5067 for (timeout = 0; timeout < 1000; timeout++) { 5068 if ((status = ATA_INL(ctlr->r_res2, 0x1000 + offset)) & 0x00040000) 5069 break; 5070 DELAY(1000); 5071 } 5072 if (timeout >= 1000) { 5073 device_printf(ch->dev, "channel HW reset timeout reset failure\n"); 5074 ch->devices = 0; 5075 goto finish; 5076 } 5077 if (bootverbose) 5078 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout * 1); 5079 5080 /* reset phy */ 5081 if (!ata_sata_phy_reset(dev)) { 5082 if (bootverbose) 5083 device_printf(ch->dev, "phy reset found no device\n"); 5084 ch->devices = 0; 5085 goto finish; 5086 } 5087 5088 /* get a piece of the workspace for a soft reset request */ 5089 prb = (struct ata_siiprb_command *) 5090 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 5091 bzero(prb, sizeof(struct ata_siiprb_command)); 5092 prb->control = htole16(0x0080); 5093 5094 /* activate the soft reset prb */ 5095 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 5096 ATA_OUTL(ctlr->r_res2, 5097 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 5098 ATA_OUTL(ctlr->r_res2, 5099 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 5100 5101 /* poll for channel ready */ 5102 for (timeout = 0; timeout < 1000; timeout++) { 5103 DELAY(1000); 5104 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 5105 break; 5106 } 5107 if (timeout >= 1000) { 5108 device_printf(ch->dev, "reset timeout - no device found\n"); 5109 ch->devices = 0; 5110 goto finish; 5111 } 5112 if (bootverbose) 5113 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n", 5114 timeout, status); 5115 5116 /* find out whats there */ 5117 prb = (struct ata_siiprb_command *) 5118 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 5119 signature = 5120 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 5121 if (bootverbose) 5122 device_printf(ch->dev, "signature=%08x\n", signature); 5123 switch (signature) { 5124 case 0xeb140101: 5125 ch->devices = ATA_ATAPI_MASTER; 5126 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n"); 5127 ch->devices = 0; 5128 break; 5129 case 0x96690101: 5130 ch->devices = ATA_PORTMULTIPLIER; 5131 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 5132 ch->devices = 0; 5133 break; 5134 case 0x00000101: 5135 ch->devices = ATA_ATA_MASTER; 5136 break; 5137 default: 5138 ch->devices = 0; 5139 } 5140 5141 finish: 5142 /* clear interrupt(s) */ 5143 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 5144 5145 /* require explicit interrupt ack */ 5146 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 5147 5148 /* 64bit mode */ 5149 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 5150 5151 /* enable interrupts wanted */ 5152 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 5153 } 5154 5155 static void 5156 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 5157 { 5158 struct ata_dmasetprd_args *args = xsc; 5159 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 5160 int i; 5161 5162 if ((args->error = error)) 5163 return; 5164 5165 for (i = 0; i < nsegs; i++) { 5166 prd[i].addr = htole64(segs[i].ds_addr); 5167 prd[i].count = htole32(segs[i].ds_len); 5168 } 5169 prd[i - 1].control = htole32(ATA_DMA_EOT); 5170 } 5171 5172 static void 5173 ata_siiprb_dmainit(device_t dev) 5174 { 5175 struct ata_channel *ch = device_get_softc(dev); 5176 5177 ata_dmainit(dev); 5178 if (ch->dma) { 5179 /* note start and stop are not used here */ 5180 ch->dma->setprd = ata_siiprb_dmasetprd; 5181 ch->dma->max_address = BUS_SPACE_MAXADDR; 5182 } 5183 } 5184 5185 5186 /* 5187 * Silicon Integrated Systems Corp. (SiS) chipset support functions 5188 */ 5189 int 5190 ata_sis_ident(device_t dev) 5191 { 5192 struct ata_pci_controller *ctlr = device_get_softc(dev); 5193 struct ata_chip_id *idx; 5194 static struct ata_chip_id ids[] = 5195 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */ 5196 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */ 5197 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */ 5198 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */ 5199 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */ 5200 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */ 5201 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */ 5202 5203 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */ 5204 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */ 5205 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */ 5206 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */ 5207 5208 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */ 5209 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */ 5210 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */ 5211 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */ 5212 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */ 5213 5214 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" }, 5215 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" }, 5216 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" }, 5217 5218 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" }, 5219 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" }, 5220 { 0, 0, 0, 0, 0, 0 }}; 5221 char buffer[64]; 5222 int found = 0; 5223 5224 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev)))) 5225 return ENXIO; 5226 5227 if (idx->cfg2 && !found) { 5228 u_int8_t reg57 = pci_read_config(dev, 0x57, 1); 5229 5230 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1); 5231 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) { 5232 found = 1; 5233 idx->cfg1 = SIS133NEW; 5234 idx->max_dma = ATA_UDMA6; 5235 ksprintf(buffer, "SiS 962/963 %s controller", 5236 ata_mode2str(idx->max_dma)); 5237 } 5238 pci_write_config(dev, 0x57, reg57, 1); 5239 } 5240 if (idx->cfg2 && !found) { 5241 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1); 5242 5243 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1); 5244 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) { 5245 struct ata_chip_id id[] = 5246 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }}; 5247 5248 found = 1; 5249 if (ata_find_chip(dev, id, pci_get_slot(dev))) { 5250 idx->cfg1 = SIS133OLD; 5251 idx->max_dma = ATA_UDMA6; 5252 } 5253 else { 5254 idx->cfg1 = SIS100NEW; 5255 idx->max_dma = ATA_UDMA5; 5256 } 5257 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma)); 5258 } 5259 pci_write_config(dev, 0x4a, reg4a, 1); 5260 } 5261 if (!found) 5262 ksprintf(buffer,"SiS %s %s controller", 5263 idx->text, ata_mode2str(idx->max_dma)); 5264 5265 device_set_desc_copy(dev, buffer); 5266 ctlr->chip = idx; 5267 ctlr->chipinit = ata_sis_chipinit; 5268 return 0; 5269 } 5270 5271 static int 5272 ata_sis_chipinit(device_t dev) 5273 { 5274 struct ata_pci_controller *ctlr = device_get_softc(dev); 5275 5276 if (ata_setup_interrupt(dev)) 5277 return ENXIO; 5278 5279 switch (ctlr->chip->cfg1) { 5280 case SIS33: 5281 break; 5282 case SIS66: 5283 case SIS100OLD: 5284 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1); 5285 break; 5286 case SIS100NEW: 5287 case SIS133OLD: 5288 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1); 5289 break; 5290 case SIS133NEW: 5291 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2); 5292 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2); 5293 break; 5294 case SISSATA: 5295 ctlr->r_type2 = SYS_RES_IOPORT; 5296 ctlr->r_rid2 = PCIR_BAR(5); 5297 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5298 &ctlr->r_rid2, RF_ACTIVE))) { 5299 ctlr->allocate = ata_sis_allocate; 5300 ctlr->reset = ata_sis_reset; 5301 5302 /* enable PCI interrupt */ 5303 pci_write_config(dev, PCIR_COMMAND, 5304 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5305 } 5306 ctlr->setmode = ata_sata_setmode; 5307 return 0; 5308 default: 5309 ata_teardown_interrupt(dev); 5310 return ENXIO; 5311 } 5312 ctlr->setmode = ata_sis_setmode; 5313 return 0; 5314 } 5315 5316 static int 5317 ata_sis_allocate(device_t dev) 5318 { 5319 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5320 struct ata_channel *ch = device_get_softc(dev); 5321 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6); 5322 5323 /* setup the usual register normal pci style */ 5324 if (ata_pci_allocate(dev)) 5325 return ENXIO; 5326 5327 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5328 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; 5329 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5330 ch->r_io[ATA_SERROR].offset = 0x04 + offset; 5331 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5332 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; 5333 ch->flags |= ATA_NO_SLAVE; 5334 5335 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ 5336 /* XXX SOS unknown how to enable PHY state change interrupt */ 5337 return 0; 5338 } 5339 5340 static void 5341 ata_sis_reset(device_t dev) 5342 { 5343 if (ata_sata_phy_reset(dev)) 5344 ata_generic_reset(dev); 5345 } 5346 5347 static void 5348 ata_sis_setmode(device_t dev, int mode) 5349 { 5350 device_t gparent = GRANDPARENT(dev); 5351 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5352 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5353 struct ata_device *atadev = device_get_softc(dev); 5354 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5355 int error; 5356 5357 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5358 5359 if (ctlr->chip->cfg1 == SIS133NEW) { 5360 if (mode > ATA_UDMA2 && 5361 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) { 5362 ata_print_cable(dev, "controller"); 5363 mode = ATA_UDMA2; 5364 } 5365 } 5366 else { 5367 if (mode > ATA_UDMA2 && 5368 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) { 5369 ata_print_cable(dev, "controller"); 5370 mode = ATA_UDMA2; 5371 } 5372 } 5373 5374 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5375 5376 if (bootverbose) 5377 device_printf(dev, "%ssetting %s on %s chip\n", 5378 (error) ? "FAILURE " : "", 5379 ata_mode2str(mode), ctlr->chip->text); 5380 if (!error) { 5381 switch (ctlr->chip->cfg1) { 5382 case SIS133NEW: { 5383 u_int32_t timings[] = 5384 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 5385 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 5386 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; 5387 u_int32_t reg; 5388 5389 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); 5390 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4); 5391 break; 5392 } 5393 case SIS133OLD: { 5394 u_int16_t timings[] = 5395 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 5396 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; 5397 5398 u_int16_t reg = 0x40 + (devno << 1); 5399 5400 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5401 break; 5402 } 5403 case SIS100NEW: { 5404 u_int16_t timings[] = 5405 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 5406 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; 5407 u_int16_t reg = 0x40 + (devno << 1); 5408 5409 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5410 break; 5411 } 5412 case SIS100OLD: 5413 case SIS66: 5414 case SIS33: { 5415 u_int16_t timings[] = 5416 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 5417 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; 5418 u_int16_t reg = 0x40 + (devno << 1); 5419 5420 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5421 break; 5422 } 5423 } 5424 atadev->mode = mode; 5425 } 5426 } 5427 5428 5429 /* VIA Technologies Inc. chipset support functions */ 5430 int 5431 ata_via_ident(device_t dev) 5432 { 5433 struct ata_pci_controller *ctlr = device_get_softc(dev); 5434 struct ata_chip_id *idx; 5435 static struct ata_chip_id ids[] = 5436 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 5437 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 5438 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 5439 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 5440 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 5441 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 5442 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 5443 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 5444 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 5445 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 5446 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 5447 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 5448 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 5449 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 5450 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 5451 { 0, 0, 0, 0, 0, 0 }}; 5452 static struct ata_chip_id new_ids[] = 5453 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 5454 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 5455 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 5456 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 5457 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" }, 5458 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" }, 5459 { 0, 0, 0, 0, 0, 0 }}; 5460 char buffer[64]; 5461 5462 if (pci_get_devid(dev) == ATA_VIA82C571) { 5463 if (!(idx = ata_find_chip(dev, ids, -99))) 5464 return ENXIO; 5465 } 5466 else { 5467 if (!(idx = ata_match_chip(dev, new_ids))) 5468 return ENXIO; 5469 } 5470 5471 ksprintf(buffer, "VIA %s %s controller", 5472 idx->text, ata_mode2str(idx->max_dma)); 5473 device_set_desc_copy(dev, buffer); 5474 ctlr->chip = idx; 5475 ctlr->chipinit = ata_via_chipinit; 5476 return 0; 5477 } 5478 5479 static int 5480 ata_via_chipinit(device_t dev) 5481 { 5482 struct ata_pci_controller *ctlr = device_get_softc(dev); 5483 5484 if (ata_setup_interrupt(dev)) 5485 return ENXIO; 5486 5487 if (ctlr->chip->max_dma >= ATA_SA150) { 5488 /* do we have AHCI capability ? */ 5489 if ((ctlr->chip->cfg2 == VIAAHCI) && ata_ahci_chipinit(dev) != ENXIO) 5490 return 0; 5491 5492 ctlr->r_type2 = SYS_RES_IOPORT; 5493 ctlr->r_rid2 = PCIR_BAR(5); 5494 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5495 &ctlr->r_rid2, RF_ACTIVE))) { 5496 ctlr->allocate = ata_via_allocate; 5497 ctlr->reset = ata_via_reset; 5498 5499 /* enable PCI interrupt */ 5500 pci_write_config(dev, PCIR_COMMAND, 5501 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5502 } 5503 5504 if (ctlr->chip->cfg2 & VIABAR) { 5505 ctlr->channels = 3; 5506 ctlr->setmode = ata_via_setmode; 5507 } 5508 else 5509 ctlr->setmode = ata_sata_setmode; 5510 return 0; 5511 } 5512 5513 /* prepare for ATA-66 on the 82C686a and 82C596b */ 5514 if (ctlr->chip->cfg2 & VIACLK) 5515 pci_write_config(dev, 0x50, 0x030b030b, 4); 5516 5517 /* the southbridge might need the data corruption fix */ 5518 if (ctlr->chip->cfg2 & VIABUG) 5519 ata_via_southbridge_fixup(dev); 5520 5521 /* set fifo configuration half'n'half */ 5522 pci_write_config(dev, 0x43, 5523 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 5524 5525 /* set status register read retry */ 5526 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 5527 5528 /* set DMA read & end-of-sector fifo flush */ 5529 pci_write_config(dev, 0x46, 5530 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 5531 5532 /* set sector size */ 5533 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 5534 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 5535 5536 ctlr->setmode = ata_via_family_setmode; 5537 return 0; 5538 } 5539 5540 static int 5541 ata_via_allocate(device_t dev) 5542 { 5543 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5544 struct ata_channel *ch = device_get_softc(dev); 5545 5546 /* newer SATA chips has resources in one BAR for each channel */ 5547 if (ctlr->chip->cfg2 & VIABAR) { 5548 struct resource *r_io; 5549 int i, rid; 5550 5551 rid = PCIR_BAR(ch->unit); 5552 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 5553 SYS_RES_IOPORT, 5554 &rid, RF_ACTIVE))) 5555 return ENXIO; 5556 5557 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 5558 ch->r_io[i].res = r_io; 5559 ch->r_io[i].offset = i; 5560 } 5561 ch->r_io[ATA_CONTROL].res = r_io; 5562 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 5563 ch->r_io[ATA_IDX_ADDR].res = r_io; 5564 ata_default_registers(dev); 5565 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 5566 ch->r_io[i].res = ctlr->r_res1; 5567 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 5568 } 5569 ata_pci_hw(dev); 5570 if (ch->unit >= 2) 5571 return 0; 5572 } 5573 else { 5574 /* setup the usual register normal pci style */ 5575 if (ata_pci_allocate(dev)) 5576 return ENXIO; 5577 } 5578 5579 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5580 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 5581 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5582 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 5583 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5584 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 5585 ch->flags |= ATA_NO_SLAVE; 5586 5587 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */ 5588 /* XXX SOS unknown how to enable PHY state change interrupt */ 5589 return 0; 5590 } 5591 5592 static void 5593 ata_via_reset(device_t dev) 5594 { 5595 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5596 struct ata_channel *ch = device_get_softc(dev); 5597 5598 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 5599 ata_generic_reset(dev); 5600 else 5601 if (ata_sata_phy_reset(dev)) 5602 ata_generic_reset(dev); 5603 } 5604 5605 static void 5606 ata_via_setmode(device_t dev, int mode) 5607 { 5608 device_t gparent = GRANDPARENT(dev); 5609 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5610 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5611 struct ata_device *atadev = device_get_softc(dev); 5612 int error; 5613 5614 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 5615 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20, 5616 0x65, 0x32, 0x20, 5617 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5618 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 5619 5620 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6)); 5621 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5622 if (bootverbose) 5623 device_printf(dev, "%ssetting %s on %s chip\n", 5624 (error) ? "FAILURE " : "", ata_mode2str(mode), 5625 ctlr->chip->text); 5626 if (!error) { 5627 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1); 5628 if (mode >= ATA_UDMA0) 5629 pci_write_config(gparent, 0xb3, 5630 dma_timings[mode & ATA_MODE_MASK], 1); 5631 atadev->mode = mode; 5632 } 5633 } 5634 else 5635 ata_sata_setmode(dev, mode); 5636 } 5637 5638 static void 5639 ata_via_southbridge_fixup(device_t dev) 5640 { 5641 device_t *children; 5642 int nchildren, i; 5643 5644 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5645 return; 5646 5647 for (i = 0; i < nchildren; i++) { 5648 if (pci_get_devid(children[i]) == ATA_VIA8363 || 5649 pci_get_devid(children[i]) == ATA_VIA8371 || 5650 pci_get_devid(children[i]) == ATA_VIA8662 || 5651 pci_get_devid(children[i]) == ATA_VIA8361) { 5652 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 5653 5654 if ((reg76 & 0xf0) != 0xd0) { 5655 device_printf(dev, 5656 "Correcting VIA config for southbridge data corruption bug\n"); 5657 pci_write_config(children[i], 0x75, 0x80, 1); 5658 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 5659 } 5660 break; 5661 } 5662 } 5663 kfree(children, M_TEMP); 5664 } 5665 5666 5667 /* common code for VIA, AMD & nVidia */ 5668 static void 5669 ata_via_family_setmode(device_t dev, int mode) 5670 { 5671 device_t gparent = GRANDPARENT(dev); 5672 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5673 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5674 struct ata_device *atadev = device_get_softc(dev); 5675 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20, 5676 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5677 int modes[][7] = { 5678 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 5679 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 5680 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 5681 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */ 5682 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */ 5683 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5684 int reg = 0x53 - devno; 5685 int error; 5686 5687 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5688 5689 if (ctlr->chip->cfg2 & AMDCABLE) { 5690 if (mode > ATA_UDMA2 && 5691 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) { 5692 ata_print_cable(dev, "controller"); 5693 mode = ATA_UDMA2; 5694 } 5695 } 5696 else 5697 mode = ata_check_80pin(dev, mode); 5698 5699 if (ctlr->chip->cfg2 & NVIDIA) 5700 reg += 0x10; 5701 5702 if (ctlr->chip->cfg1 != VIA133) 5703 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1); 5704 5705 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5706 5707 if (bootverbose) 5708 device_printf(dev, "%ssetting %s on %s chip\n", 5709 (error) ? "FAILURE " : "", ata_mode2str(mode), 5710 ctlr->chip->text); 5711 if (!error) { 5712 if (mode >= ATA_UDMA0) 5713 pci_write_config(gparent, reg, 5714 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 5715 else 5716 pci_write_config(gparent, reg, 0x8b, 1); 5717 atadev->mode = mode; 5718 } 5719 } 5720 5721 5722 /* misc functions */ 5723 static struct ata_chip_id * 5724 ata_match_chip(device_t dev, struct ata_chip_id *index) 5725 { 5726 while (index->chipid != 0) { 5727 if (pci_get_devid(dev) == index->chipid && 5728 pci_get_revid(dev) >= index->chiprev) 5729 return index; 5730 index++; 5731 } 5732 return NULL; 5733 } 5734 5735 static struct ata_chip_id * 5736 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot) 5737 { 5738 device_t *children; 5739 int nchildren, i; 5740 5741 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5742 return 0; 5743 5744 while (index->chipid != 0) { 5745 for (i = 0; i < nchildren; i++) { 5746 if (((slot >= 0 && pci_get_slot(children[i]) == slot) || 5747 (slot < 0 && pci_get_slot(children[i]) <= -slot)) && 5748 pci_get_devid(children[i]) == index->chipid && 5749 pci_get_revid(children[i]) >= index->chiprev) { 5750 kfree(children, M_TEMP); 5751 return index; 5752 } 5753 } 5754 index++; 5755 } 5756 kfree(children, M_TEMP); 5757 return NULL; 5758 } 5759 5760 static int 5761 ata_setup_interrupt(device_t dev) 5762 { 5763 struct ata_pci_controller *ctlr = device_get_softc(dev); 5764 int rid = ATA_IRQ_RID; 5765 5766 if (!ctlr->legacy) { 5767 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 5768 RF_SHAREABLE | RF_ACTIVE))) { 5769 device_printf(dev, "unable to map interrupt\n"); 5770 return ENXIO; 5771 } 5772 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 5773 ata_generic_intr, ctlr, &ctlr->handle, NULL))) { 5774 device_printf(dev, "unable to setup interrupt\n"); 5775 bus_release_resource(dev, SYS_RES_IRQ, rid, ctlr->r_irq); 5776 ctlr->r_irq = 0; 5777 return ENXIO; 5778 } 5779 } 5780 return 0; 5781 } 5782 5783 static void 5784 ata_teardown_interrupt(device_t dev) 5785 { 5786 struct ata_pci_controller *ctlr = device_get_softc(dev); 5787 5788 if (!ctlr->legacy) { 5789 if (ctlr->r_irq) { 5790 bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle); 5791 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ctlr->r_irq); 5792 ctlr->r_irq = 0; 5793 } 5794 } 5795 } 5796 5797 struct ata_serialize { 5798 struct lock locked_mtx; 5799 int locked_ch; 5800 int restart_ch; 5801 }; 5802 5803 static int 5804 ata_serialize(device_t dev, int flags) 5805 { 5806 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5807 struct ata_channel *ch = device_get_softc(dev); 5808 struct ata_serialize *serial; 5809 static int inited = 0; 5810 int res; 5811 5812 if (!inited) { 5813 serial = kmalloc(sizeof(struct ata_serialize), 5814 M_TEMP, M_INTWAIT | M_ZERO); 5815 lockinit(&serial->locked_mtx, "ataserialize", 0, 0); 5816 serial->locked_ch = -1; 5817 serial->restart_ch = -1; 5818 device_set_ivars(ctlr->dev, serial); 5819 inited = 1; 5820 } 5821 else 5822 serial = device_get_ivars(ctlr->dev); 5823 5824 lockmgr(&serial->locked_mtx, LK_EXCLUSIVE); 5825 switch (flags) { 5826 case ATA_LF_LOCK: 5827 if (serial->locked_ch == -1) 5828 serial->locked_ch = ch->unit; 5829 if (serial->locked_ch != ch->unit) 5830 serial->restart_ch = ch->unit; 5831 break; 5832 5833 case ATA_LF_UNLOCK: 5834 if (serial->locked_ch == ch->unit) { 5835 serial->locked_ch = -1; 5836 if (serial->restart_ch != -1) { 5837 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) { 5838 serial->restart_ch = -1; 5839 lockmgr(&serial->locked_mtx, LK_RELEASE); 5840 ata_start(ch->dev); 5841 return -1; 5842 } 5843 } 5844 } 5845 break; 5846 5847 case ATA_LF_WHICH: 5848 break; 5849 } 5850 res = serial->locked_ch; 5851 lockmgr(&serial->locked_mtx, LK_RELEASE); 5852 return res; 5853 } 5854 5855 static void 5856 ata_print_cable(device_t dev, u_int8_t *who) 5857 { 5858 device_printf(dev, 5859 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who); 5860 } 5861 5862 static int 5863 ata_atapi(device_t dev) 5864 { 5865 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5866 struct ata_device *atadev = device_get_softc(dev); 5867 5868 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || 5869 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE)); 5870 } 5871 5872 static int 5873 ata_check_80pin(device_t dev, int mode) 5874 { 5875 struct ata_device *atadev = device_get_softc(dev); 5876 5877 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) { 5878 ata_print_cable(dev, "device"); 5879 mode = ATA_UDMA2; 5880 } 5881 return mode; 5882 } 5883 5884 static int 5885 ata_mode2idx(int mode) 5886 { 5887 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) 5888 return (mode & ATA_MODE_MASK) + 8; 5889 if ((mode & ATA_DMA_MASK) == ATA_WDMA0) 5890 return (mode & ATA_MODE_MASK) + 5; 5891 return (mode & ATA_MODE_MASK) - ATA_PIO0; 5892 } 5893