1 /*- 2 * Copyright (c) 1998 - 2006 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.196 2007/04/08 19:18:51 sos Exp $ 27 * $DragonFly: src/sys/dev/disk/nata/ata-chipset.c,v 1.9 2007/10/19 11:53:14 tgen Exp $ 28 */ 29 30 #include "opt_ata.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/bus_dma.h> 35 #include <sys/bus_resource.h> 36 #include <sys/callout.h> 37 #include <sys/endian.h> 38 #include <sys/libkern.h> 39 #include <sys/lock.h> /* for {get,rel}_mplock() */ 40 #include <sys/malloc.h> 41 #include <sys/nata.h> 42 #include <sys/queue.h> 43 #include <sys/rman.h> 44 #include <sys/spinlock.h> 45 #include <sys/spinlock2.h> 46 #include <sys/systm.h> 47 #include <sys/taskqueue.h> 48 49 #include <machine/bus_dma.h> 50 51 #include <bus/pci/pcireg.h> 52 #include <bus/pci/pcivar.h> 53 54 #include "ata-all.h" 55 #include "ata-pci.h" 56 #include "ata_if.h" 57 58 /* local prototypes */ 59 /* ata-chipset.c */ 60 static int ata_generic_chipinit(device_t dev); 61 static void ata_generic_intr(void *data); 62 static void ata_generic_setmode(device_t dev, int mode); 63 static void ata_sata_phy_check_events(device_t dev); 64 static void ata_sata_phy_event(void *context, int dummy); 65 static int ata_sata_phy_reset(device_t dev); 66 static int ata_sata_connect(struct ata_channel *ch); 67 static void ata_sata_setmode(device_t dev, int mode); 68 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); 69 static int ata_ahci_chipinit(device_t dev); 70 static int ata_ahci_allocate(device_t dev); 71 static int ata_ahci_status(device_t dev); 72 static int ata_ahci_begin_transaction(struct ata_request *request); 73 static int ata_ahci_end_transaction(struct ata_request *request); 74 static void ata_ahci_reset(device_t dev); 75 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 76 static void ata_ahci_dmainit(device_t dev); 77 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request); 78 static int ata_genahci_chipinit(device_t dev); 79 static int ata_acard_chipinit(device_t dev); 80 static int ata_acard_allocate(device_t dev); 81 static int ata_acard_status(device_t dev); 82 static void ata_acard_850_setmode(device_t dev, int mode); 83 static void ata_acard_86X_setmode(device_t dev, int mode); 84 static int ata_ali_chipinit(device_t dev); 85 static int ata_ali_allocate(device_t dev); 86 static int ata_ali_sata_allocate(device_t dev); 87 static void ata_ali_reset(device_t dev); 88 static void ata_ali_setmode(device_t dev, int mode); 89 static int ata_amd_chipinit(device_t dev); 90 static int ata_ati_chipinit(device_t dev); 91 static void ata_ati_setmode(device_t dev, int mode); 92 static int ata_cyrix_chipinit(device_t dev); 93 static void ata_cyrix_setmode(device_t dev, int mode); 94 static int ata_cypress_chipinit(device_t dev); 95 static void ata_cypress_setmode(device_t dev, int mode); 96 static int ata_highpoint_chipinit(device_t dev); 97 static int ata_highpoint_allocate(device_t dev); 98 static void ata_highpoint_setmode(device_t dev, int mode); 99 static int ata_highpoint_check_80pin(device_t dev, int mode); 100 static int ata_intel_chipinit(device_t dev); 101 static int ata_intel_allocate(device_t dev); 102 static void ata_intel_reset(device_t dev); 103 static void ata_intel_old_setmode(device_t dev, int mode); 104 static void ata_intel_new_setmode(device_t dev, int mode); 105 static int ata_intel_31244_allocate(device_t dev); 106 static int ata_intel_31244_status(device_t dev); 107 static int ata_intel_31244_command(struct ata_request *request); 108 static void ata_intel_31244_reset(device_t dev); 109 static int ata_ite_chipinit(device_t dev); 110 static void ata_ite_setmode(device_t dev, int mode); 111 static int ata_jmicron_chipinit(device_t dev); 112 static int ata_jmicron_allocate(device_t dev); 113 static void ata_jmicron_reset(device_t dev); 114 static void ata_jmicron_dmainit(device_t dev); 115 static void ata_jmicron_setmode(device_t dev, int mode); 116 static int ata_marvell_pata_chipinit(device_t dev); 117 static int ata_marvell_pata_allocate(device_t dev); 118 static void ata_marvell_pata_setmode(device_t dev, int mode); 119 static int ata_marvell_edma_chipinit(device_t dev); 120 static int ata_marvell_edma_allocate(device_t dev); 121 static int ata_marvell_edma_status(device_t dev); 122 static int ata_marvell_edma_begin_transaction(struct ata_request *request); 123 static int ata_marvell_edma_end_transaction(struct ata_request *request); 124 static void ata_marvell_edma_reset(device_t dev); 125 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 126 static void ata_marvell_edma_dmainit(device_t dev); 127 static int ata_national_chipinit(device_t dev); 128 static void ata_national_setmode(device_t dev, int mode); 129 static int ata_netcell_chipinit(device_t dev); 130 static int ata_netcell_allocate(device_t dev); 131 static int ata_nvidia_chipinit(device_t dev); 132 static int ata_nvidia_allocate(device_t dev); 133 static int ata_nvidia_status(device_t dev); 134 static void ata_nvidia_reset(device_t dev); 135 static int ata_promise_chipinit(device_t dev); 136 static int ata_promise_allocate(device_t dev); 137 static int ata_promise_status(device_t dev); 138 static int ata_promise_dmastart(device_t dev); 139 static int ata_promise_dmastop(device_t dev); 140 static void ata_promise_dmareset(device_t dev); 141 static void ata_promise_dmainit(device_t dev); 142 static void ata_promise_setmode(device_t dev, int mode); 143 static int ata_promise_tx2_allocate(device_t dev); 144 static int ata_promise_tx2_status(device_t dev); 145 static int ata_promise_mio_allocate(device_t dev); 146 static void ata_promise_mio_intr(void *data); 147 static int ata_promise_mio_status(device_t dev); 148 static int ata_promise_mio_command(struct ata_request *request); 149 static void ata_promise_mio_reset(device_t dev); 150 static void ata_promise_mio_dmainit(device_t dev); 151 static void ata_promise_mio_setmode(device_t dev, int mode); 152 static void ata_promise_sx4_intr(void *data); 153 static int ata_promise_sx4_command(struct ata_request *request); 154 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 155 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 156 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 157 static int ata_serverworks_chipinit(device_t dev); 158 static int ata_serverworks_allocate(device_t dev); 159 static void ata_serverworks_setmode(device_t dev, int mode); 160 static int ata_sii_chipinit(device_t dev); 161 static int ata_cmd_allocate(device_t dev); 162 static int ata_cmd_status(device_t dev); 163 static void ata_cmd_setmode(device_t dev, int mode); 164 static int ata_sii_allocate(device_t dev); 165 static int ata_sii_status(device_t dev); 166 static void ata_sii_reset(device_t dev); 167 static void ata_sii_setmode(device_t dev, int mode); 168 static int ata_siiprb_allocate(device_t dev); 169 static int ata_siiprb_status(device_t dev); 170 static int ata_siiprb_begin_transaction(struct ata_request *request); 171 static int ata_siiprb_end_transaction(struct ata_request *request); 172 static void ata_siiprb_reset(device_t dev); 173 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 174 static void ata_siiprb_dmainit(device_t dev); 175 static int ata_sis_chipinit(device_t dev); 176 static int ata_sis_allocate(device_t dev); 177 static void ata_sis_reset(device_t dev); 178 static void ata_sis_setmode(device_t dev, int mode); 179 static int ata_via_chipinit(device_t dev); 180 static int ata_via_allocate(device_t dev); 181 static void ata_via_reset(device_t dev); 182 static void ata_via_setmode(device_t dev, int mode); 183 static void ata_via_southbridge_fixup(device_t dev); 184 static void ata_via_family_setmode(device_t dev, int mode); 185 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index); 186 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot); 187 static int ata_setup_interrupt(device_t dev); 188 static int ata_serialize(device_t dev, int flags); 189 static void ata_print_cable(device_t dev, u_int8_t *who); 190 static int ata_atapi(device_t dev); 191 static int ata_check_80pin(device_t dev, int mode); 192 static int ata_mode2idx(int mode); 193 194 195 /* 196 * generic ATA support functions 197 */ 198 int 199 ata_generic_ident(device_t dev) 200 { 201 struct ata_pci_controller *ctlr = device_get_softc(dev); 202 203 device_set_desc(dev, "GENERIC ATA controller"); 204 ctlr->chipinit = ata_generic_chipinit; 205 return 0; 206 } 207 208 static int 209 ata_generic_chipinit(device_t dev) 210 { 211 struct ata_pci_controller *ctlr = device_get_softc(dev); 212 213 if (ata_setup_interrupt(dev)) 214 return ENXIO; 215 ctlr->setmode = ata_generic_setmode; 216 return 0; 217 } 218 219 static void 220 ata_generic_intr(void *data) 221 { 222 struct ata_pci_controller *ctlr = data; 223 struct ata_channel *ch; 224 int unit; 225 226 for (unit = 0; unit < ctlr->channels; unit++) { 227 if ((ch = ctlr->interrupt[unit].argument)) 228 ctlr->interrupt[unit].function(ch); 229 } 230 } 231 232 static void 233 ata_generic_setmode(device_t dev, int mode) 234 { 235 struct ata_device *atadev = device_get_softc(dev); 236 237 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 238 mode = ata_check_80pin(dev, mode); 239 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 240 atadev->mode = mode; 241 } 242 243 244 /* 245 * SATA support functions 246 */ 247 static void 248 ata_sata_phy_check_events(device_t dev) 249 { 250 struct ata_channel *ch = device_get_softc(dev); 251 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR); 252 253 /* clear error bits/interrupt */ 254 ATA_IDX_OUTL(ch, ATA_SERROR, error); 255 256 /* do we have any events flagged ? */ 257 if (error) { 258 struct ata_connect_task *tp; 259 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS); 260 261 /* if we have a connection event deal with it */ 262 if ((error & ATA_SE_PHY_CHANGED) && 263 (tp = (struct ata_connect_task *) 264 kmalloc(sizeof(struct ata_connect_task), 265 M_ATA, M_INTWAIT | M_ZERO))) { 266 267 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) || 268 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) { 269 if (bootverbose) 270 device_printf(ch->dev, "CONNECT requested\n"); 271 tp->action = ATA_C_ATTACH; 272 } 273 else { 274 if (bootverbose) 275 device_printf(ch->dev, "DISCONNECT requested\n"); 276 tp->action = ATA_C_DETACH; 277 } 278 tp->dev = ch->dev; 279 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 280 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 281 } 282 } 283 } 284 285 static void 286 ata_sata_phy_event(void *context, int dummy) 287 { 288 struct ata_connect_task *tp = (struct ata_connect_task *)context; 289 struct ata_channel *ch = device_get_softc(tp->dev); 290 device_t *children; 291 int nchildren, i; 292 293 get_mplock(); 294 if (tp->action == ATA_C_ATTACH) { 295 if (bootverbose) 296 device_printf(tp->dev, "CONNECTED\n"); 297 ATA_RESET(tp->dev); 298 ata_identify(tp->dev); 299 } 300 if (tp->action == ATA_C_DETACH) { 301 if (!device_get_children(tp->dev, &children, &nchildren)) { 302 for (i = 0; i < nchildren; i++) 303 if (children[i]) 304 device_delete_child(tp->dev, children[i]); 305 kfree(children, M_TEMP); 306 } 307 spin_lock_wr(&ch->state_mtx); 308 ch->state = ATA_IDLE; 309 spin_unlock_wr(&ch->state_mtx); 310 if (bootverbose) 311 device_printf(tp->dev, "DISCONNECTED\n"); 312 } 313 rel_mplock(); 314 kfree(tp, M_ATA); 315 } 316 317 static int 318 ata_sata_phy_reset(device_t dev) 319 { 320 struct ata_channel *ch = device_get_softc(dev); 321 int loop, retry; 322 323 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 324 return ata_sata_connect(ch); 325 326 for (retry = 0; retry < 10; retry++) { 327 for (loop = 0; loop < 10; loop++) { 328 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET); 329 ata_udelay(100); 330 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & 331 ATA_SC_DET_MASK) == ATA_SC_DET_RESET) 332 break; 333 } 334 ata_udelay(5000); 335 for (loop = 0; loop < 10; loop++) { 336 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE | 337 ATA_SC_IPM_DIS_PARTIAL | 338 ATA_SC_IPM_DIS_SLUMBER); 339 ata_udelay(100); 340 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0) 341 return ata_sata_connect(ch); 342 } 343 } 344 return 0; 345 } 346 347 static int 348 ata_sata_connect(struct ata_channel *ch) 349 { 350 u_int32_t status; 351 int timeout; 352 353 /* wait up to 1 second for "connect well" */ 354 for (timeout = 0; timeout < 100 ; timeout++) { 355 status = ATA_IDX_INL(ch, ATA_SSTATUS); 356 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 || 357 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2) 358 break; 359 ata_udelay(10000); 360 } 361 if (timeout >= 100) { 362 if (bootverbose) 363 device_printf(ch->dev, "SATA connect status=%08x\n", status); 364 return 0; 365 } 366 367 if (bootverbose) 368 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10); 369 370 /* clear SATA error register */ 371 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 372 373 return 1; 374 } 375 376 static void 377 ata_sata_setmode(device_t dev, int mode) 378 { 379 struct ata_device *atadev = device_get_softc(dev); 380 381 /* 382 * if we detect that the device isn't a real SATA device we limit 383 * the transfer mode to UDMA5/ATA100. 384 * this works around the problems some devices has with the 385 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133. 386 */ 387 if (atadev->param.satacapabilities != 0x0000 && 388 atadev->param.satacapabilities != 0xffff) { 389 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 390 391 /* on some drives we need to set the transfer mode */ 392 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 393 ata_limit_mode(dev, mode, ATA_UDMA6)); 394 395 /* query SATA STATUS for the speed */ 396 if (ch->r_io[ATA_SSTATUS].res && 397 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) == 398 ATA_SS_CONWELL_GEN2)) 399 atadev->mode = ATA_SA300; 400 else 401 atadev->mode = ATA_SA150; 402 } 403 else { 404 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 405 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 406 atadev->mode = mode; 407 } 408 } 409 410 static int 411 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis) 412 { 413 struct ata_device *atadev = device_get_softc(request->dev); 414 415 if (request->flags & ATA_R_ATAPI) { 416 fis[0] = 0x27; /* host to device */ 417 fis[1] = 0x80; /* command FIS (note PM goes here) */ 418 fis[2] = ATA_PACKET_CMD; 419 if (request->flags & ATA_R_DMA) 420 fis[3] = ATA_F_DMA; 421 else { 422 fis[5] = request->transfersize; 423 fis[6] = request->transfersize >> 8; 424 } 425 fis[7] = ATA_D_LBA | atadev->unit; 426 fis[15] = ATA_A_4BIT; 427 return 20; 428 } 429 else { 430 ata_modify_if_48bit(request); 431 fis[0] = 0x27; /* host to device */ 432 fis[1] = 0x80; /* command FIS (note PM goes here) */ 433 fis[2] = request->u.ata.command; 434 fis[3] = request->u.ata.feature; 435 fis[4] = request->u.ata.lba; 436 fis[5] = request->u.ata.lba >> 8; 437 fis[6] = request->u.ata.lba >> 16; 438 fis[7] = ATA_D_LBA | atadev->unit; 439 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 440 fis[7] |= (request->u.ata.lba >> 24 & 0x0f); 441 fis[8] = request->u.ata.lba >> 24; 442 fis[9] = request->u.ata.lba >> 32; 443 fis[10] = request->u.ata.lba >> 40; 444 fis[11] = request->u.ata.feature >> 8; 445 fis[12] = request->u.ata.count; 446 fis[13] = request->u.ata.count >> 8; 447 fis[15] = ATA_A_4BIT; 448 return 20; 449 } 450 return 0; 451 } 452 453 /* 454 * AHCI v1.x compliant SATA chipset support functions 455 */ 456 static int 457 ata_ahci_chipinit(device_t dev) 458 { 459 struct ata_pci_controller *ctlr = device_get_softc(dev); 460 u_int32_t version; 461 int unit; 462 463 /* reset AHCI controller */ 464 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 465 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_HR); 466 DELAY(1000000); 467 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) { 468 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 469 device_printf(dev, "AHCI controller reset failure\n"); 470 return ENXIO; 471 } 472 473 /* enable AHCI mode */ 474 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 475 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_AE); 476 477 /* get the number of HW channels */ 478 ctlr->channels = 479 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)), 480 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 481 482 /* disable interrupt sources and clear interrupts */ 483 for (unit = 0; unit < ctlr->channels; unit++) { 484 int offset = unit << 7; 485 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0); 486 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, -1); 487 } 488 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS)); 489 490 /* enable AHCI interrupts */ 491 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 492 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE); 493 494 ctlr->reset = ata_ahci_reset; 495 ctlr->dmainit = ata_ahci_dmainit; 496 ctlr->allocate = ata_ahci_allocate; 497 ctlr->setmode = ata_sata_setmode; 498 499 /* enable PCI interrupt */ 500 pci_write_config(dev, PCIR_COMMAND, 501 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 502 503 /* announce we support the HW */ 504 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS); 505 device_printf(dev, 506 "AHCI Version %x%x.%x%x controller with %d ports detected\n", 507 (version >> 24) & 0xff, (version >> 16) & 0xff, 508 (version >> 8) & 0xff, version & 0xff, 509 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 510 return 0; 511 } 512 513 static int 514 ata_ahci_allocate(device_t dev) 515 { 516 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 517 struct ata_channel *ch = device_get_softc(dev); 518 u_int64_t work; 519 int offset = ch->unit << 7; 520 521 /* set the SATA resources */ 522 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 523 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset; 524 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 525 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset; 526 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 527 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset; 528 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 529 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset; 530 531 ch->hw.status = ata_ahci_status; 532 ch->hw.begin_transaction = ata_ahci_begin_transaction; 533 ch->hw.end_transaction = ata_ahci_end_transaction; 534 ch->hw.command = NULL; /* not used here */ 535 536 /* setup work areas */ 537 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET; 538 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff); 539 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32); 540 541 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET; 542 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff); 543 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32); 544 545 /* enable wanted port interrupts */ 546 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 547 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF | 548 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF | 549 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP | 550 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS | 551 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR)); 552 553 /* start operations on this channel */ 554 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 555 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 556 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 557 return 0; 558 } 559 560 static int 561 ata_ahci_status(device_t dev) 562 { 563 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 564 struct ata_channel *ch = device_get_softc(dev); 565 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS); 566 int offset = ch->unit << 7; 567 int tag = 0; 568 569 if (action & (1 << ch->unit)) { 570 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset); 571 572 /* clear interrupt(s) */ 573 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit)); 574 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus); 575 576 /* do we have any PHY events ? */ 577 ata_sata_phy_check_events(dev); 578 579 /* do we have any device action ? */ 580 return (!(ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset) & (1 << tag))); 581 } 582 return 0; 583 } 584 585 /* must be called with ATA channel locked and state_mtx held */ 586 static int 587 ata_ahci_begin_transaction(struct ata_request *request) 588 { 589 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 590 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 591 struct ata_ahci_cmd_tab *ctp; 592 struct ata_ahci_cmd_list *clp; 593 int offset = ch->unit << 7; 594 int tag = 0, entries = 0; 595 int fis_size; 596 597 /* get a piece of the workspace for this request */ 598 ctp = (struct ata_ahci_cmd_tab *) 599 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag)); 600 601 /* setup the FIS for this request */ 602 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) { 603 device_printf(request->dev, "setting up SATA FIS failed\n"); 604 request->result = EIO; 605 return ATA_OP_FINISHED; 606 } 607 608 /* if request moves data setup and load SG list */ 609 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 610 if (ch->dma->load(ch->dev, request->data, request->bytecount, 611 request->flags & ATA_R_READ, 612 ctp->prd_tab, &entries)) { 613 device_printf(request->dev, "setting up DMA failed\n"); 614 request->result = EIO; 615 return ATA_OP_FINISHED; 616 } 617 } 618 619 /* setup the command list entry */ 620 clp = (struct ata_ahci_cmd_list *) 621 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 622 623 clp->prd_length = entries; 624 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) | 625 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) | 626 (fis_size / sizeof(u_int32_t)); 627 clp->bytecount = 0; 628 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET + 629 (ATA_AHCI_CT_SIZE * tag)); 630 631 /* clear eventual ACTIVE bit */ 632 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag)); 633 634 /* set command type bit */ 635 if (request->flags & ATA_R_ATAPI) 636 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 637 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) | 638 ATA_AHCI_P_CMD_ATAPI); 639 else 640 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 641 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & 642 ~ATA_AHCI_P_CMD_ATAPI); 643 644 /* issue the command */ 645 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag)); 646 647 /* start the timeout */ 648 callout_reset(&request->callout, request->timeout * hz, 649 (timeout_t*)ata_timeout, request); 650 return ATA_OP_CONTINUES; 651 } 652 653 /* must be called with ATA channel locked and state_mtx held */ 654 static int 655 ata_ahci_end_transaction(struct ata_request *request) 656 { 657 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 658 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 659 struct ata_ahci_cmd_list *clp; 660 u_int32_t tf_data; 661 int offset = ch->unit << 7; 662 int tag = 0; 663 664 /* kill the timeout */ 665 callout_stop(&request->callout); 666 667 /* get status */ 668 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset); 669 request->status = tf_data; 670 671 /* if error status get details */ 672 if (request->status & ATA_S_ERROR) 673 request->error = tf_data >> 8; 674 675 /* record how much data we actually moved */ 676 clp = (struct ata_ahci_cmd_list *) 677 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 678 request->donecount = clp->bytecount; 679 680 /* release SG list etc */ 681 ch->dma->unload(ch->dev); 682 683 return ATA_OP_FINISHED; 684 } 685 686 static void 687 ata_ahci_reset(device_t dev) 688 { 689 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 690 struct ata_channel *ch = device_get_softc(dev); 691 u_int32_t cmd; 692 int offset = ch->unit << 7; 693 int timeout; 694 695 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) { 696 device_printf(dev, "port not implemented\n"); 697 return; 698 } 699 ch->devices = 0; 700 701 /* kill off all activity on this channel */ 702 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 703 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 704 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 705 706 /* XXX SOS this is not entirely wrong */ 707 timeout = 0; 708 do { 709 DELAY(1000); 710 if (timeout++ > 500) 711 device_printf(dev, "stopping AHCI engine failed\n"); 712 break; 713 } 714 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 715 716 /* issue Command List Override if supported */ 717 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) { 718 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 719 cmd |= ATA_AHCI_P_CMD_CLO; 720 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd); 721 timeout = 0; 722 do { 723 DELAY(1000); 724 if (timeout++ > 500) 725 device_printf(dev, "executing CLO failed\n"); 726 break; 727 } 728 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO); 729 } 730 731 /* spin up device */ 732 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, ATA_AHCI_P_CMD_SUD); 733 734 /* enable interface */ 735 if (ata_sata_phy_reset(dev)) { 736 switch (ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset)) { 737 case 0xeb140101: 738 ch->devices = ATA_ATAPI_MASTER; 739 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n"); 740 ch->devices = 0; 741 break; 742 case 0x96690101: 743 ch->devices = ATA_PORTMULTIPLIER; 744 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 745 ch->devices = 0; 746 break; 747 case 0x00000101: 748 ch->devices = ATA_ATA_MASTER; 749 break; 750 } 751 } 752 753 /* clear any interrupts pending on this channel */ 754 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, 755 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset)); 756 757 /* start operations on this channel */ 758 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 759 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 760 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 761 } 762 763 static void 764 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 765 { 766 struct ata_dmasetprd_args *args = xsc; 767 struct ata_ahci_dma_prd *prd = args->dmatab; 768 int i; 769 770 if (!(args->error = error)) { 771 for (i = 0; i < nsegs; i++) { 772 prd[i].dba = htole64(segs[i].ds_addr); 773 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK); 774 } 775 } 776 args->nsegs = nsegs; 777 } 778 779 static void 780 ata_ahci_dmainit(device_t dev) 781 { 782 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 783 struct ata_channel *ch = device_get_softc(dev); 784 785 ata_dmainit(dev); 786 if (ch->dma) { 787 /* note start and stop are not used here */ 788 ch->dma->setprd = ata_ahci_dmasetprd; 789 ch->dma->max_iosize = 8192 * DEV_BSIZE; 790 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT) 791 ch->dma->max_address = BUS_SPACE_MAXADDR; 792 } 793 } 794 795 static int 796 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request) 797 { 798 bzero(ctp->cfis, 64); 799 if (request->flags & ATA_R_ATAPI) { 800 bzero(ctp->acmd, 32); 801 bcopy(request->u.atapi.ccb, ctp->acmd, 12); 802 } 803 return ata_request2fis_h2d(request, &ctp->cfis[0]); 804 } 805 806 /* 807 * Generic AHCI part support functions. 808 */ 809 int 810 ata_genahci_ident(device_t dev) 811 { 812 struct ata_pci_controller *ctlr = device_get_softc(dev); 813 static struct ata_chip_id id = {0, 0, 0, 0x00, ATA_SA300, "AHCI"}; 814 char buffer[64]; 815 816 if(!(pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI)) { 817 return ENXIO; 818 } 819 820 ksprintf(buffer, "GENERIC %s %s controller", id.text, ata_mode2str(id.max_dma)); 821 device_set_desc_copy(dev, buffer); 822 ctlr->chip = &id; 823 ctlr->chipinit = ata_genahci_chipinit; 824 return 0; 825 } 826 827 static int 828 ata_genahci_chipinit(device_t dev) 829 { 830 struct ata_pci_controller *ctlr = device_get_softc(dev); 831 832 if (ata_setup_interrupt(dev)) 833 return ENXIO; 834 835 /* Check if the chip has PCI BAR 5 as memory resource. */ 836 ctlr->r_type2 = SYS_RES_MEMORY; 837 ctlr->r_rid2 = PCIR_BAR(5); /* 0x24 */ 838 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 839 &ctlr->r_rid2, RF_ACTIVE))) { 840 return ata_ahci_chipinit(dev); 841 } else 842 return ENXIO; 843 } 844 845 /* 846 * Acard chipset support functions 847 */ 848 int 849 ata_acard_ident(device_t dev) 850 { 851 struct ata_pci_controller *ctlr = device_get_softc(dev); 852 struct ata_chip_id *idx; 853 static struct ata_chip_id ids[] = 854 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" }, 855 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" }, 856 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" }, 857 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" }, 858 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" }, 859 { 0, 0, 0, 0, 0, 0}}; 860 char buffer[64]; 861 862 if (!(idx = ata_match_chip(dev, ids))) 863 return ENXIO; 864 865 ksprintf(buffer, "Acard %s %s controller", 866 idx->text, ata_mode2str(idx->max_dma)); 867 device_set_desc_copy(dev, buffer); 868 ctlr->chip = idx; 869 ctlr->chipinit = ata_acard_chipinit; 870 return 0; 871 } 872 873 static int 874 ata_acard_chipinit(device_t dev) 875 { 876 struct ata_pci_controller *ctlr = device_get_softc(dev); 877 878 if (ata_setup_interrupt(dev)) 879 return ENXIO; 880 881 ctlr->allocate = ata_acard_allocate; 882 if (ctlr->chip->cfg1 == ATPOLD) { 883 ctlr->setmode = ata_acard_850_setmode; 884 ctlr->locking = ata_serialize; 885 } 886 else 887 ctlr->setmode = ata_acard_86X_setmode; 888 return 0; 889 } 890 891 static int 892 ata_acard_allocate(device_t dev) 893 { 894 struct ata_channel *ch = device_get_softc(dev); 895 896 /* setup the usual register normal pci style */ 897 if (ata_pci_allocate(dev)) 898 return ENXIO; 899 900 ch->hw.status = ata_acard_status; 901 return 0; 902 } 903 904 static int 905 ata_acard_status(device_t dev) 906 { 907 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 908 struct ata_channel *ch = device_get_softc(dev); 909 910 if (ctlr->chip->cfg1 == ATPOLD && 911 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit) 912 return 0; 913 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) { 914 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 915 916 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != 917 ATA_BMSTAT_INTERRUPT) 918 return 0; 919 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR); 920 DELAY(1); 921 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 922 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 923 DELAY(1); 924 } 925 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 926 DELAY(100); 927 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 928 return 0; 929 } 930 return 1; 931 } 932 933 static void 934 ata_acard_850_setmode(device_t dev, int mode) 935 { 936 device_t gparent = GRANDPARENT(dev); 937 struct ata_pci_controller *ctlr = device_get_softc(gparent); 938 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 939 struct ata_device *atadev = device_get_softc(dev); 940 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 941 int error; 942 943 mode = ata_limit_mode(dev, mode, 944 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 945 946 /* XXX SOS missing WDMA0+1 + PIO modes */ 947 if (mode >= ATA_WDMA2) { 948 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 949 if (bootverbose) 950 device_printf(dev, "%ssetting %s on %s chip\n", 951 (error) ? "FAILURE " : "", 952 ata_mode2str(mode), ctlr->chip->text); 953 if (!error) { 954 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1); 955 956 reg54 &= ~(0x03 << (devno << 1)); 957 if (mode >= ATA_UDMA0) 958 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1)); 959 pci_write_config(gparent, 0x54, reg54, 1); 960 pci_write_config(gparent, 0x4a, 0xa6, 1); 961 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2); 962 atadev->mode = mode; 963 return; 964 } 965 } 966 /* we could set PIO mode timings, but we assume the BIOS did that */ 967 } 968 969 static void 970 ata_acard_86X_setmode(device_t dev, int mode) 971 { 972 device_t gparent = GRANDPARENT(dev); 973 struct ata_pci_controller *ctlr = device_get_softc(gparent); 974 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 975 struct ata_device *atadev = device_get_softc(dev); 976 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 977 int error; 978 979 980 mode = ata_limit_mode(dev, mode, 981 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 982 983 mode = ata_check_80pin(dev, mode); 984 985 /* XXX SOS missing WDMA0+1 + PIO modes */ 986 if (mode >= ATA_WDMA2) { 987 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 988 if (bootverbose) 989 device_printf(dev, "%ssetting %s on %s chip\n", 990 (error) ? "FAILURE " : "", 991 ata_mode2str(mode), ctlr->chip->text); 992 if (!error) { 993 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2); 994 995 reg44 &= ~(0x000f << (devno << 2)); 996 if (mode >= ATA_UDMA0) 997 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2)); 998 pci_write_config(gparent, 0x44, reg44, 2); 999 pci_write_config(gparent, 0x4a, 0xa6, 1); 1000 pci_write_config(gparent, 0x40 + devno, 0x31, 1); 1001 atadev->mode = mode; 1002 return; 1003 } 1004 } 1005 /* we could set PIO mode timings, but we assume the BIOS did that */ 1006 } 1007 1008 1009 /* 1010 * Acer Labs Inc (ALI) chipset support functions 1011 */ 1012 int 1013 ata_ali_ident(device_t dev) 1014 { 1015 struct ata_pci_controller *ctlr = device_get_softc(dev); 1016 struct ata_chip_id *idx; 1017 static struct ata_chip_id ids[] = 1018 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" }, 1019 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" }, 1020 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" }, 1021 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" }, 1022 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" }, 1023 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" }, 1024 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" }, 1025 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" }, 1026 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" }, 1027 { 0, 0, 0, 0, 0, 0}}; 1028 char buffer[64]; 1029 1030 if (!(idx = ata_match_chip(dev, ids))) 1031 return ENXIO; 1032 1033 ksprintf(buffer, "AcerLabs %s %s controller", 1034 idx->text, ata_mode2str(idx->max_dma)); 1035 device_set_desc_copy(dev, buffer); 1036 ctlr->chip = idx; 1037 ctlr->chipinit = ata_ali_chipinit; 1038 return 0; 1039 } 1040 1041 static int 1042 ata_ali_chipinit(device_t dev) 1043 { 1044 struct ata_pci_controller *ctlr = device_get_softc(dev); 1045 1046 if (ata_setup_interrupt(dev)) 1047 return ENXIO; 1048 1049 switch (ctlr->chip->cfg2) { 1050 case ALISATA: 1051 ctlr->channels = ctlr->chip->cfg1; 1052 ctlr->allocate = ata_ali_sata_allocate; 1053 ctlr->setmode = ata_sata_setmode; 1054 1055 /* if we have a memory resource we can likely do AHCI */ 1056 ctlr->r_type2 = SYS_RES_MEMORY; 1057 ctlr->r_rid2 = PCIR_BAR(5); 1058 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1059 &ctlr->r_rid2, RF_ACTIVE))) 1060 return ata_ahci_chipinit(dev); 1061 1062 /* enable PCI interrupt */ 1063 pci_write_config(dev, PCIR_COMMAND, 1064 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1065 break; 1066 1067 case ALINEW: 1068 /* use device interrupt as byte count end */ 1069 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1); 1070 1071 /* enable cable detection and UDMA support on newer chips */ 1072 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1); 1073 1074 /* enable ATAPI UDMA mode */ 1075 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1); 1076 1077 /* only chips with revision > 0xc4 can do 48bit DMA */ 1078 if (ctlr->chip->chiprev <= 0xc4) 1079 device_printf(dev, 1080 "using PIO transfers above 137GB as workaround for " 1081 "48bit DMA access bug, expect reduced performance\n"); 1082 ctlr->allocate = ata_ali_allocate; 1083 ctlr->reset = ata_ali_reset; 1084 ctlr->setmode = ata_ali_setmode; 1085 break; 1086 1087 case ALIOLD: 1088 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */ 1089 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1); 1090 ctlr->setmode = ata_ali_setmode; 1091 break; 1092 } 1093 return 0; 1094 } 1095 1096 static int 1097 ata_ali_allocate(device_t dev) 1098 { 1099 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1100 struct ata_channel *ch = device_get_softc(dev); 1101 1102 /* setup the usual register normal pci style */ 1103 if (ata_pci_allocate(dev)) 1104 return ENXIO; 1105 1106 /* older chips can't do 48bit DMA transfers */ 1107 if (ctlr->chip->chiprev <= 0xc4) 1108 ch->flags |= ATA_NO_48BIT_DMA; 1109 1110 return 0; 1111 } 1112 1113 static int 1114 ata_ali_sata_allocate(device_t dev) 1115 { 1116 device_t parent = device_get_parent(dev); 1117 struct ata_pci_controller *ctlr = device_get_softc(parent); 1118 struct ata_channel *ch = device_get_softc(dev); 1119 struct resource *io = NULL, *ctlio = NULL; 1120 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 1121 int i, rid; 1122 1123 rid = PCIR_BAR(0) + (unit01 ? 8 : 0); 1124 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1125 if (!io) 1126 return ENXIO; 1127 1128 rid = PCIR_BAR(1) + (unit01 ? 8 : 0); 1129 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1130 if (!ctlio) { 1131 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io); 1132 return ENXIO; 1133 } 1134 1135 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 1136 ch->r_io[i].res = io; 1137 ch->r_io[i].offset = i + (unit10 ? 8 : 0); 1138 } 1139 ch->r_io[ATA_CONTROL].res = ctlio; 1140 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0); 1141 ch->r_io[ATA_IDX_ADDR].res = io; 1142 ata_default_registers(dev); 1143 if (ctlr->r_res1) { 1144 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 1145 ch->r_io[i].res = ctlr->r_res1; 1146 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 1147 } 1148 } 1149 ch->flags |= ATA_NO_SLAVE; 1150 1151 /* XXX SOS PHY handling awkward in ALI chip not supported yet */ 1152 ata_pci_hw(dev); 1153 return 0; 1154 } 1155 1156 static void 1157 ata_ali_reset(device_t dev) 1158 { 1159 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1160 struct ata_channel *ch = device_get_softc(dev); 1161 device_t *children; 1162 int nchildren, i; 1163 1164 ata_generic_reset(dev); 1165 1166 /* 1167 * workaround for datacorruption bug found on at least SUN Blade-100 1168 * find the ISA function on the southbridge and disable then enable 1169 * the ATA channel tristate buffer 1170 */ 1171 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) { 1172 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) { 1173 for (i = 0; i < nchildren; i++) { 1174 if (pci_get_devid(children[i]) == ATA_ALI_1533) { 1175 pci_write_config(children[i], 0x58, 1176 pci_read_config(children[i], 0x58, 1) & 1177 ~(0x04 << ch->unit), 1); 1178 pci_write_config(children[i], 0x58, 1179 pci_read_config(children[i], 0x58, 1) | 1180 (0x04 << ch->unit), 1); 1181 break; 1182 } 1183 } 1184 kfree(children, M_TEMP); 1185 } 1186 } 1187 } 1188 1189 static void 1190 ata_ali_setmode(device_t dev, int mode) 1191 { 1192 device_t gparent = GRANDPARENT(dev); 1193 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1194 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1195 struct ata_device *atadev = device_get_softc(dev); 1196 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1197 int error; 1198 1199 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1200 1201 if (ctlr->chip->cfg2 & ALINEW) { 1202 if (mode > ATA_UDMA2 && 1203 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) { 1204 ata_print_cable(dev, "controller"); 1205 mode = ATA_UDMA2; 1206 } 1207 } 1208 else 1209 mode = ata_check_80pin(dev, mode); 1210 1211 if (ctlr->chip->cfg2 & ALIOLD) { 1212 /* doesn't support ATAPI DMA on write */ 1213 ch->flags |= ATA_ATAPI_DMA_RO; 1214 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) { 1215 /* doesn't support ATAPI DMA on two ATAPI devices */ 1216 device_printf(dev, "two atapi devices on this channel, no DMA\n"); 1217 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1218 } 1219 } 1220 1221 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1222 1223 if (bootverbose) 1224 device_printf(dev, "%ssetting %s on %s chip\n", 1225 (error) ? "FAILURE " : "", 1226 ata_mode2str(mode), ctlr->chip->text); 1227 if (!error) { 1228 if (mode >= ATA_UDMA0) { 1229 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d}; 1230 u_int32_t word54 = pci_read_config(gparent, 0x54, 4); 1231 1232 word54 &= ~(0x000f000f << (devno << 2)); 1233 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2)); 1234 pci_write_config(gparent, 0x54, word54, 4); 1235 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1236 0x00310001, 4); 1237 } 1238 else { 1239 u_int32_t piotimings[] = 1240 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001, 1241 0x00310001, 0x00440001, 0x00330001, 0x00310001}; 1242 1243 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) & 1244 ~(0x0008000f << (devno << 2)), 4); 1245 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1246 piotimings[ata_mode2idx(mode)], 4); 1247 } 1248 atadev->mode = mode; 1249 } 1250 } 1251 1252 1253 /* 1254 * American Micro Devices (AMD) chipset support functions 1255 */ 1256 int 1257 ata_amd_ident(device_t dev) 1258 { 1259 struct ata_pci_controller *ctlr = device_get_softc(dev); 1260 struct ata_chip_id *idx; 1261 static struct ata_chip_id ids[] = 1262 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" }, 1263 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" }, 1264 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" }, 1265 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" }, 1266 { 0, 0, 0, 0, 0, 0}}; 1267 char buffer[64]; 1268 1269 if (!(idx = ata_match_chip(dev, ids))) 1270 return ENXIO; 1271 1272 ksprintf(buffer, "AMD %s %s controller", 1273 idx->text, ata_mode2str(idx->max_dma)); 1274 device_set_desc_copy(dev, buffer); 1275 ctlr->chip = idx; 1276 ctlr->chipinit = ata_amd_chipinit; 1277 return 0; 1278 } 1279 1280 static int 1281 ata_amd_chipinit(device_t dev) 1282 { 1283 struct ata_pci_controller *ctlr = device_get_softc(dev); 1284 1285 if (ata_setup_interrupt(dev)) 1286 return ENXIO; 1287 1288 /* disable/set prefetch, postwrite */ 1289 if (ctlr->chip->cfg2 & AMDBUG) 1290 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1); 1291 else 1292 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); 1293 1294 ctlr->setmode = ata_via_family_setmode; 1295 return 0; 1296 } 1297 1298 1299 /* 1300 * ATI chipset support functions 1301 */ 1302 int 1303 ata_ati_ident(device_t dev) 1304 { 1305 struct ata_pci_controller *ctlr = device_get_softc(dev); 1306 struct ata_chip_id *idx; 1307 static struct ata_chip_id ids[] = 1308 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" }, 1309 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" }, 1310 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" }, 1311 { ATA_ATI_SB600, 0x00, 0, 0, ATA_UDMA6, "SB600" }, 1312 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" }, 1313 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1314 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1315 { ATA_ATI_SB600_S1, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1316 { ATA_ATI_SB600_S2, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1317 { 0, 0, 0, 0, 0, 0}}; 1318 char buffer[64]; 1319 1320 if (!(idx = ata_match_chip(dev, ids))) 1321 return ENXIO; 1322 1323 ksprintf(buffer, "ATI %s %s controller", 1324 idx->text, ata_mode2str(idx->max_dma)); 1325 device_set_desc_copy(dev, buffer); 1326 ctlr->chip = idx; 1327 1328 /* 1329 * The ATI SATA controllers are actually a SiI 3112 controller, except 1330 * for the SB600. 1331 */ 1332 if (ctlr->chip->cfg1 & SIIMEMIO) 1333 ctlr->chipinit = ata_sii_chipinit; 1334 else 1335 ctlr->chipinit = ata_ati_chipinit; 1336 return 0; 1337 } 1338 1339 static int 1340 ata_ati_chipinit(device_t dev) 1341 { 1342 struct ata_pci_controller *ctlr = device_get_softc(dev); 1343 1344 if (ata_setup_interrupt(dev)) 1345 return ENXIO; 1346 1347 /* The SB600 needs special treatment. */ 1348 if (ctlr->chip->cfg1 & ATIAHCI) { 1349 /* Check if the chip is configured as an AHCI part. */ 1350 if ((pci_get_subclass(dev) == PCIS_STORAGE_SATA) && 1351 (pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI)) { 1352 /* Check if the chip has PCI BAR 5 as memory resource. */ 1353 ctlr->r_type2 = SYS_RES_MEMORY; 1354 ctlr->r_rid2 = PCIR_BAR(5); /* 0x24 */ 1355 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1356 &ctlr->r_rid2, 1357 RF_ACTIVE))) { 1358 return ata_ahci_chipinit(dev); 1359 } 1360 } 1361 } 1362 1363 ctlr->setmode = ata_ati_setmode; 1364 return 0; 1365 } 1366 1367 static void 1368 ata_ati_setmode(device_t dev, int mode) 1369 { 1370 device_t gparent = GRANDPARENT(dev); 1371 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1372 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1373 struct ata_device *atadev = device_get_softc(dev); 1374 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1375 int offset = (devno ^ 0x01) << 3; 1376 int error; 1377 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 1378 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 1379 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 1380 1381 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1382 1383 mode = ata_check_80pin(dev, mode); 1384 1385 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1386 1387 if (bootverbose) 1388 device_printf(dev, "%ssetting %s on %s chip\n", 1389 (error) ? "FAILURE " : "", 1390 ata_mode2str(mode), ctlr->chip->text); 1391 if (!error) { 1392 if (mode >= ATA_UDMA0) { 1393 pci_write_config(gparent, 0x56, 1394 (pci_read_config(gparent, 0x56, 2) & 1395 ~(0xf << (devno << 2))) | 1396 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 1397 pci_write_config(gparent, 0x54, 1398 pci_read_config(gparent, 0x54, 1) | 1399 (0x01 << devno), 1); 1400 pci_write_config(gparent, 0x44, 1401 (pci_read_config(gparent, 0x44, 4) & 1402 ~(0xff << offset)) | 1403 (dmatimings[2] << offset), 4); 1404 } 1405 else if (mode >= ATA_WDMA0) { 1406 pci_write_config(gparent, 0x54, 1407 pci_read_config(gparent, 0x54, 1) & 1408 ~(0x01 << devno), 1); 1409 pci_write_config(gparent, 0x44, 1410 (pci_read_config(gparent, 0x44, 4) & 1411 ~(0xff << offset)) | 1412 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 1413 } 1414 else 1415 pci_write_config(gparent, 0x54, 1416 pci_read_config(gparent, 0x54, 1) & 1417 ~(0x01 << devno), 1); 1418 1419 pci_write_config(gparent, 0x4a, 1420 (pci_read_config(gparent, 0x4a, 2) & 1421 ~(0xf << (devno << 2))) | 1422 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2); 1423 pci_write_config(gparent, 0x40, 1424 (pci_read_config(gparent, 0x40, 4) & 1425 ~(0xff << offset)) | 1426 (piotimings[ata_mode2idx(mode)] << offset), 4); 1427 atadev->mode = mode; 1428 } 1429 } 1430 1431 /* 1432 * Cyrix chipset support functions 1433 */ 1434 int 1435 ata_cyrix_ident(device_t dev) 1436 { 1437 struct ata_pci_controller *ctlr = device_get_softc(dev); 1438 1439 if (pci_get_devid(dev) == ATA_CYRIX_5530) { 1440 device_set_desc(dev, "Cyrix 5530 ATA33 controller"); 1441 ctlr->chipinit = ata_cyrix_chipinit; 1442 return 0; 1443 } 1444 return ENXIO; 1445 } 1446 1447 static int 1448 ata_cyrix_chipinit(device_t dev) 1449 { 1450 struct ata_pci_controller *ctlr = device_get_softc(dev); 1451 1452 if (ata_setup_interrupt(dev)) 1453 return ENXIO; 1454 1455 if (ctlr->r_res1) 1456 ctlr->setmode = ata_cyrix_setmode; 1457 else 1458 ctlr->setmode = ata_generic_setmode; 1459 return 0; 1460 } 1461 1462 static void 1463 ata_cyrix_setmode(device_t dev, int mode) 1464 { 1465 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1466 struct ata_device *atadev = device_get_softc(dev); 1467 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1468 u_int32_t piotiming[] = 1469 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 }; 1470 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 }; 1471 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 }; 1472 int error; 1473 1474 ch->dma->alignment = 16; 1475 ch->dma->max_iosize = 126 * DEV_BSIZE; 1476 1477 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 1478 1479 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1480 1481 if (bootverbose) 1482 device_printf(dev, "%ssetting %s on Cyrix chip\n", 1483 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1484 if (!error) { 1485 if (mode >= ATA_UDMA0) { 1486 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1487 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]); 1488 } 1489 else if (mode >= ATA_WDMA0) { 1490 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1491 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]); 1492 } 1493 else { 1494 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1495 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]); 1496 } 1497 atadev->mode = mode; 1498 } 1499 } 1500 1501 1502 /* 1503 * Cypress chipset support functions 1504 */ 1505 int 1506 ata_cypress_ident(device_t dev) 1507 { 1508 struct ata_pci_controller *ctlr = device_get_softc(dev); 1509 1510 /* 1511 * the Cypress chip is a mess, it contains two ATA functions, but 1512 * both channels are visible on the first one. 1513 * simply ignore the second function for now, as the right 1514 * solution (ignoring the second channel on the first function) 1515 * doesn't work with the crappy ATA interrupt setup on the alpha. 1516 */ 1517 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 && 1518 pci_get_function(dev) == 1 && 1519 pci_get_subclass(dev) == PCIS_STORAGE_IDE) { 1520 device_set_desc(dev, "Cypress 82C693 ATA controller"); 1521 ctlr->chipinit = ata_cypress_chipinit; 1522 return 0; 1523 } 1524 return ENXIO; 1525 } 1526 1527 static int 1528 ata_cypress_chipinit(device_t dev) 1529 { 1530 struct ata_pci_controller *ctlr = device_get_softc(dev); 1531 1532 if (ata_setup_interrupt(dev)) 1533 return ENXIO; 1534 1535 ctlr->setmode = ata_cypress_setmode; 1536 return 0; 1537 } 1538 1539 static void 1540 ata_cypress_setmode(device_t dev, int mode) 1541 { 1542 device_t gparent = GRANDPARENT(dev); 1543 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1544 struct ata_device *atadev = device_get_softc(dev); 1545 int error; 1546 1547 mode = ata_limit_mode(dev, mode, ATA_WDMA2); 1548 1549 /* XXX SOS missing WDMA0+1 + PIO modes */ 1550 if (mode == ATA_WDMA2) { 1551 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1552 if (bootverbose) 1553 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n", 1554 error ? "FAILURE " : ""); 1555 if (!error) { 1556 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2); 1557 atadev->mode = mode; 1558 return; 1559 } 1560 } 1561 /* we could set PIO mode timings, but we assume the BIOS did that */ 1562 } 1563 1564 1565 /* 1566 * HighPoint chipset support functions 1567 */ 1568 int 1569 ata_highpoint_ident(device_t dev) 1570 { 1571 struct ata_pci_controller *ctlr = device_get_softc(dev); 1572 struct ata_chip_id *idx; 1573 static struct ata_chip_id ids[] = 1574 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" }, 1575 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" }, 1576 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1577 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" }, 1578 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1579 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" }, 1580 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" }, 1581 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" }, 1582 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" }, 1583 { 0, 0, 0, 0, 0, 0}}; 1584 char buffer[64]; 1585 1586 if (!(idx = ata_match_chip(dev, ids))) 1587 return ENXIO; 1588 1589 strcpy(buffer, "HighPoint "); 1590 strcat(buffer, idx->text); 1591 if (idx->cfg1 == HPT374) { 1592 if (pci_get_function(dev) == 0) 1593 strcat(buffer, " (channel 0+1)"); 1594 if (pci_get_function(dev) == 1) 1595 strcat(buffer, " (channel 2+3)"); 1596 } 1597 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 1598 device_set_desc_copy(dev, buffer); 1599 ctlr->chip = idx; 1600 ctlr->chipinit = ata_highpoint_chipinit; 1601 return 0; 1602 } 1603 1604 static int 1605 ata_highpoint_chipinit(device_t dev) 1606 { 1607 struct ata_pci_controller *ctlr = device_get_softc(dev); 1608 1609 if (ata_setup_interrupt(dev)) 1610 return ENXIO; 1611 1612 if (ctlr->chip->cfg2 == HPTOLD) { 1613 /* disable interrupt prediction */ 1614 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 1615 } 1616 else { 1617 /* disable interrupt prediction */ 1618 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 1619 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 1620 1621 /* enable interrupts */ 1622 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 1623 1624 /* set clocks etc */ 1625 if (ctlr->chip->cfg1 < HPT372) 1626 pci_write_config(dev, 0x5b, 0x22, 1); 1627 else 1628 pci_write_config(dev, 0x5b, 1629 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 1630 } 1631 ctlr->allocate = ata_highpoint_allocate; 1632 ctlr->setmode = ata_highpoint_setmode; 1633 return 0; 1634 } 1635 1636 static int 1637 ata_highpoint_allocate(device_t dev) 1638 { 1639 struct ata_channel *ch = device_get_softc(dev); 1640 1641 /* setup the usual register normal pci style */ 1642 if (ata_pci_allocate(dev)) 1643 return ENXIO; 1644 1645 ch->flags |= ATA_ALWAYS_DMASTAT; 1646 return 0; 1647 } 1648 1649 static void 1650 ata_highpoint_setmode(device_t dev, int mode) 1651 { 1652 device_t gparent = GRANDPARENT(dev); 1653 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1654 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1655 struct ata_device *atadev = device_get_softc(dev); 1656 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1657 int error; 1658 u_int32_t timings33[][4] = { 1659 /* HPT366 HPT370 HPT372 HPT374 mode */ 1660 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */ 1661 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */ 1662 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */ 1663 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */ 1664 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */ 1665 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */ 1666 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */ 1667 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */ 1668 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */ 1669 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */ 1670 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */ 1671 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */ 1672 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */ 1673 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */ 1674 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */ 1675 }; 1676 1677 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1678 1679 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev)) 1680 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1681 1682 mode = ata_highpoint_check_80pin(dev, mode); 1683 1684 /* 1685 * most if not all HPT chips cant really handle that the device is 1686 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to 1687 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance 1688 */ 1689 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 1690 ata_limit_mode(dev, mode, ATA_UDMA5)); 1691 if (bootverbose) 1692 device_printf(dev, "%ssetting %s on HighPoint chip\n", 1693 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1694 if (!error) 1695 pci_write_config(gparent, 0x40 + (devno << 2), 1696 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 1697 atadev->mode = mode; 1698 } 1699 1700 static int 1701 ata_highpoint_check_80pin(device_t dev, int mode) 1702 { 1703 device_t gparent = GRANDPARENT(dev); 1704 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1705 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1706 u_int8_t reg, val, res; 1707 1708 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) { 1709 reg = ch->unit ? 0x57 : 0x53; 1710 val = pci_read_config(gparent, reg, 1); 1711 pci_write_config(gparent, reg, val | 0x80, 1); 1712 } 1713 else { 1714 reg = 0x5b; 1715 val = pci_read_config(gparent, reg, 1); 1716 pci_write_config(gparent, reg, val & 0xfe, 1); 1717 } 1718 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2); 1719 pci_write_config(gparent, reg, val, 1); 1720 1721 if (mode > ATA_UDMA2 && res) { 1722 ata_print_cable(dev, "controller"); 1723 mode = ATA_UDMA2; 1724 } 1725 return mode; 1726 } 1727 1728 1729 /* 1730 * Intel chipset support functions 1731 */ 1732 int 1733 ata_intel_ident(device_t dev) 1734 { 1735 struct ata_pci_controller *ctlr = device_get_softc(dev); 1736 struct ata_chip_id *idx; 1737 static struct ata_chip_id ids[] = 1738 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" }, 1739 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" }, 1740 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1741 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1742 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1743 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" }, 1744 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1745 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1746 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1747 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1748 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1749 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1750 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1751 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1752 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" }, 1753 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1754 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1755 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" }, 1756 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1757 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1758 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" }, 1759 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1760 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1761 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" }, 1762 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" }, 1763 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1764 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1765 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1766 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1767 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1768 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1769 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" }, 1770 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1771 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1772 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1773 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1774 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1775 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1776 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1777 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1778 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1779 { ATA_I82801HBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1780 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1781 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" }, 1782 { 0, 0, 0, 0, 0, 0}}; 1783 char buffer[64]; 1784 1785 if (!(idx = ata_match_chip(dev, ids))) 1786 return ENXIO; 1787 1788 ksprintf(buffer, "Intel %s %s controller", 1789 idx->text, ata_mode2str(idx->max_dma)); 1790 device_set_desc_copy(dev, buffer); 1791 ctlr->chip = idx; 1792 ctlr->chipinit = ata_intel_chipinit; 1793 return 0; 1794 } 1795 1796 static int 1797 ata_intel_chipinit(device_t dev) 1798 { 1799 struct ata_pci_controller *ctlr = device_get_softc(dev); 1800 1801 if (ata_setup_interrupt(dev)) 1802 return ENXIO; 1803 1804 /* good old PIIX needs special treatment (not implemented) */ 1805 if (ctlr->chip->chipid == ATA_I82371FB) { 1806 ctlr->setmode = ata_intel_old_setmode; 1807 } 1808 1809 /* the intel 31244 needs special care if in DPA mode */ 1810 else if (ctlr->chip->chipid == ATA_I31244) { 1811 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 1812 ctlr->r_type2 = SYS_RES_MEMORY; 1813 ctlr->r_rid2 = PCIR_BAR(0); 1814 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1815 &ctlr->r_rid2, 1816 RF_ACTIVE))) 1817 return ENXIO; 1818 ctlr->channels = 4; 1819 ctlr->allocate = ata_intel_31244_allocate; 1820 ctlr->reset = ata_intel_31244_reset; 1821 } 1822 ctlr->setmode = ata_sata_setmode; 1823 } 1824 1825 /* non SATA intel chips goes here */ 1826 else if (ctlr->chip->max_dma < ATA_SA150) { 1827 ctlr->allocate = ata_intel_allocate; 1828 ctlr->setmode = ata_intel_new_setmode; 1829 } 1830 1831 /* SATA parts can be either compat or AHCI */ 1832 else { 1833 /* force all ports active "the legacy way" */ 1834 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2); 1835 1836 ctlr->allocate = ata_intel_allocate; 1837 ctlr->reset = ata_intel_reset; 1838 1839 /* 1840 * if we have AHCI capability and BAR(5) as a memory resource 1841 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode 1842 */ 1843 if ((ctlr->chip->cfg1 == AHCI) && 1844 (pci_read_config(dev, 0x90, 1) & 0xc0)) { 1845 ctlr->r_type2 = SYS_RES_MEMORY; 1846 ctlr->r_rid2 = PCIR_BAR(5); 1847 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1848 &ctlr->r_rid2, 1849 RF_ACTIVE))) 1850 return ata_ahci_chipinit(dev); 1851 } 1852 ctlr->setmode = ata_sata_setmode; 1853 1854 /* enable PCI interrupt */ 1855 pci_write_config(dev, PCIR_COMMAND, 1856 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1857 } 1858 return 0; 1859 } 1860 1861 static int 1862 ata_intel_allocate(device_t dev) 1863 { 1864 struct ata_channel *ch = device_get_softc(dev); 1865 1866 /* setup the usual register normal pci style */ 1867 if (ata_pci_allocate(dev)) 1868 return ENXIO; 1869 1870 ch->flags |= ATA_ALWAYS_DMASTAT; 1871 return 0; 1872 } 1873 1874 static void 1875 ata_intel_reset(device_t dev) 1876 { 1877 device_t parent = device_get_parent(dev); 1878 struct ata_pci_controller *ctlr = device_get_softc(parent); 1879 struct ata_channel *ch = device_get_softc(dev); 1880 int mask, timeout; 1881 1882 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */ 1883 if (ctlr->chip->cfg1) { 1884 mask = (0x0005 << ch->unit); 1885 } 1886 else { 1887 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */ 1888 if (pci_read_config(parent, 0x90, 1) & 0x04) 1889 mask = 0x0003; 1890 else { 1891 mask = (0x0001 << ch->unit); 1892 /* XXX SOS should be in intel_allocate if we grow it */ 1893 ch->flags |= ATA_NO_SLAVE; 1894 } 1895 } 1896 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2); 1897 DELAY(10); 1898 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2); 1899 1900 /* wait up to 1 sec for "connect well" */ 1901 for (timeout = 0; timeout < 100 ; timeout++) { 1902 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) && 1903 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 1904 break; 1905 ata_udelay(10000); 1906 } 1907 ata_generic_reset(dev); 1908 } 1909 1910 static void 1911 ata_intel_old_setmode(device_t dev, int mode) 1912 { 1913 /* NOT YET */ 1914 } 1915 1916 static void 1917 ata_intel_new_setmode(device_t dev, int mode) 1918 { 1919 device_t gparent = GRANDPARENT(dev); 1920 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1921 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1922 struct ata_device *atadev = device_get_softc(dev); 1923 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1924 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4); 1925 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1); 1926 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1); 1927 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2); 1928 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2); 1929 u_int32_t mask40 = 0, new40 = 0; 1930 u_int8_t mask44 = 0, new44 = 0; 1931 int error; 1932 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, 1933 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 }; 1934 /* PIO0 PIO1 PIO2 PIO3 PIO4 WDMA0 WDMA1 WDMA2 */ 1935 /* UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 UDMA5 UDMA6 */ 1936 1937 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1938 1939 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { 1940 ata_print_cable(dev, "controller"); 1941 mode = ATA_UDMA2; 1942 } 1943 1944 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1945 1946 if (bootverbose) 1947 device_printf(dev, "%ssetting %s on %s chip\n", 1948 (error) ? "FAILURE " : "", 1949 ata_mode2str(mode), ctlr->chip->text); 1950 if (error) 1951 return; 1952 1953 /* 1954 * reg48: 1 bit per (primary drive 0, primary drive 1, secondary 1955 * drive 0, secondary drive 1) 1956 * 1957 * 0 Disable Ultra DMA mode 1958 * 1 Enable Ultra DMA mode 1959 * 1960 * reg4a: 4 bits per (primary drive 0, primary drive 1, secondary 1961 * drive 0, secondary drive 1). 1962 * 0000 UDMA mode 0 1963 * 0001 UDMA mode 1, 3, 5 1964 * 0010 UDMA mode 2, 4, reserved 1965 * 0011 reserved 1966 * (top two bits for each drive reserved) 1967 */ 1968 #if 0 1969 device_printf(dev, 1970 "regs before 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 1971 reg40, reg44, reg48 ,reg4a, reg54); 1972 #endif 1973 reg48 &= ~(0x0001 << devno); 1974 reg4a &= ~(0x3 << (devno << 2)); 1975 if (mode >= ATA_UDMA0) { 1976 reg48 |= 0x0001 << devno; 1977 if (mode > ATA_UDMA0) 1978 reg4a |= (1 + !(mode & 0x01)) << (devno << 2); 1979 } 1980 pci_write_config(gparent, 0x48, reg48, 2); 1981 pci_write_config(gparent, 0x4a, reg4a, 2); 1982 1983 /* 1984 * reg54: 1985 * 1986 * 32:20 reserved 1987 * 19:18 Secondary ATA signal mode 1988 * 17:16 Primary ATA signal mode 1989 * 00 = Normal (enabled) 1990 * 01 = Tri-state (disabled) 1991 * 10 = Drive Low (disabled) 1992 * 11 = Reserved 1993 * 1994 * 15 Secondary drive 1 - Base Clock 1995 * 14 Secondary drive 0 - Base Clock 1996 * 13 Primary drive 1 - Base Clock 1997 * 12 Primary drive 0 - Base Clock 1998 * 0 = Select 33 MHz clock 1999 * 1 = Select 100 Mhz clock 2000 * 2001 * 11 Reserved 2002 * 10 Vendor specific (set by BIOS?) 2003 * 09:08 Reserved 2004 * 2005 * 07 Secondary drive 1 - Cable Type 2006 * 06 Secondary drive 0 - Cable Type 2007 * 05 Primary drive 1 - Cable Type 2008 * 04 Primary drive 0 - Cable Type 2009 * 0 = 40 Conductor 2010 * 1 = 80 Conductor (or high speed cable) 2011 * 2012 * 03 Secondary drive 1 - Select 33/66 clock 2013 * 02 Secondary drive 0 - Select 33/66 clock 2014 * 01 Primary drive 1 - Select 33/66 clock 2015 * 00 Primary drive 0 - Select 33/66 clock 2016 * 0 = Select 33 MHz 2017 * 1 = Select 66 MHz 2018 * 2019 * It is unclear what this should be set to when operating 2020 * in 100MHz mode. 2021 * 2022 * NOTE: UDMA2 = 33 MHz 2023 * UDMA3 = 40 MHz (?) - unsupported 2024 * UDMA4 = 66 MHz 2025 * UDMA5 = 100 MHz 2026 * UDMA6 = 133 Mhz 2027 */ 2028 reg54 |= 0x0400; /* set vendor specific bit */ 2029 reg54 &= ~((0x1 << devno) | (0x1000 << devno)); 2030 2031 if (mode >= ATA_UDMA5) 2032 reg54 |= (0x1000 << devno); 2033 else if (mode >= ATA_UDMA3) /* XXX should this be ATA_UDMA3 or 4? */ 2034 reg54 |= (0x1 << devno); 2035 2036 pci_write_config(gparent, 0x54, reg54, 2); 2037 2038 /* 2039 * Reg40 (32 bits... well, actually two 16 bit registers) 2040 * 2041 * Primary channel bits 15:00, Secondary channel bits 31:00. Note 2042 * that slave timings are handled in register 44. 2043 * 2044 * 15 ATA Decode Enable (R/W) 1 = enable decoding of I/O ranges 2045 * 2046 * 14 Slave ATA Timing Register Enable (R/W) 2047 * 2048 * 13:12 IORDY Sample Mode 2049 * 00 PIO-0 2050 * 01 PIO-2, SW-2 2051 * 10 PIO-3, PIO-4, MW-1, MW-2 2052 * 11 Reserved 2053 * 2054 * 11:10 Reserved 2055 * 2056 * 09:08 Recovery Mode 2057 * 00 PIO-0, PIO-2, SW-2 2058 * 01 PIO-3, MW-1 2059 * 10 Reserved 2060 * 11 PIO-4, MW-2 2061 * 2062 * 07:04 Secondary Device Control Bits 2063 * 03:00 Primary Device Control Bits 2064 * 2065 * bit 3 DMA Timing Enable 2066 * 2067 * bit 2 Indicate Presence of ATA(1) or ATAPI(0) device 2068 * 2069 * bit 1 Enable IORDY sample point capability for PIO 2070 * xfers. Always enabled for PIO4 and PIO3, enabled 2071 * for PIO2 if indicated by the device, and otherwise 2072 * probably should be 0. 2073 * 2074 * bit 0 Fast Drive Timing Enable. Enables faster then PIO-0 2075 * timing modes. 2076 */ 2077 2078 /* 2079 * Modify reg40 according to the table 2080 */ 2081 if (atadev->unit == ATA_MASTER) { 2082 mask40 = 0x3300; 2083 new40 = timings[ata_mode2idx(mode)] << 8; 2084 } 2085 else { 2086 mask44 = 0x0f; 2087 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) | 2088 (timings[ata_mode2idx(mode)] & 0x03); 2089 } 2090 2091 /* 2092 * Slave ATA timing register enable 2093 */ 2094 mask40 |= 0x4000; 2095 new40 |= 0x4000; 2096 2097 /* 2098 * Device control bits 3:0 for master, 7:4 for slave. 2099 * 2100 * bit3 DMA Timing enable. 2101 * bit2 Indicate presence of ATA(1) or ATAPI(0) device, set accordingly 2102 * bit1 Enable IORDY sample point capability for PIO xfers. Always 2103 * enabled for PIO4 and PIO3, enabled for PIO2 if indicated by 2104 * the device, and otherwise should be 0. 2105 * bit0 Fast Drive Timing Enable. Enable faster then PIO-0 timing modes. 2106 * 2107 * Set to: 0 x 1 1 2108 */ 2109 2110 if (atadev->unit == ATA_MASTER) { 2111 mask40 |= 0x0F; 2112 new40 |= 0x03; 2113 if (!ata_atapi(dev)) 2114 new40 |= 0x04; 2115 } else { 2116 mask40 |= 0xF0; 2117 new40 |= 0x30; 2118 if (!ata_atapi(dev)) 2119 new40 |= 0x40; 2120 } 2121 /* 2122 reg40 &= ~0x00ff00ff; 2123 reg40 |= 0x40774077; 2124 */ 2125 2126 /* 2127 * Primary or Secondary controller 2128 */ 2129 if (ch->unit) { 2130 mask40 <<= 16; 2131 new40 <<= 16; 2132 mask44 <<= 4; 2133 new44 <<= 4; 2134 } 2135 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4); 2136 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1); 2137 2138 #if 0 2139 reg40 = pci_read_config(gparent, 0x40, 4); 2140 reg44 = pci_read_config(gparent, 0x44, 1); 2141 reg48 = pci_read_config(gparent, 0x48, 1); 2142 reg4a = pci_read_config(gparent, 0x4a, 2); 2143 reg54 = pci_read_config(gparent, 0x54, 2); 2144 device_printf(dev, 2145 "regs after 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 2146 reg40, reg44, reg48 ,reg4a, reg54); 2147 #endif 2148 2149 atadev->mode = mode; 2150 } 2151 2152 static int 2153 ata_intel_31244_allocate(device_t dev) 2154 { 2155 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2156 struct ata_channel *ch = device_get_softc(dev); 2157 int i; 2158 int ch_offset; 2159 2160 ch_offset = 0x200 + ch->unit * 0x200; 2161 2162 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 2163 ch->r_io[i].res = ctlr->r_res2; 2164 2165 /* setup ATA registers */ 2166 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 2167 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 2168 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 2169 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 2170 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 2171 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 2172 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 2173 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 2174 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 2175 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 2176 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 2177 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 2178 2179 /* setup DMA registers */ 2180 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 2181 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 2182 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 2183 2184 /* setup SATA registers */ 2185 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 2186 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 2187 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 2188 2189 ch->flags |= ATA_NO_SLAVE; 2190 ata_pci_hw(dev); 2191 ch->hw.status = ata_intel_31244_status; 2192 ch->hw.command = ata_intel_31244_command; 2193 2194 /* enable PHY state change interrupt */ 2195 ATA_OUTL(ctlr->r_res2, 0x4, 2196 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 2197 return 0; 2198 } 2199 2200 static int 2201 ata_intel_31244_status(device_t dev) 2202 { 2203 /* do we have any PHY events ? */ 2204 ata_sata_phy_check_events(dev); 2205 2206 /* any drive action to take care of ? */ 2207 return ata_pci_status(dev); 2208 } 2209 2210 static int 2211 ata_intel_31244_command(struct ata_request *request) 2212 { 2213 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2214 struct ata_device *atadev = device_get_softc(request->dev); 2215 u_int64_t lba; 2216 2217 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 2218 return (ata_generic_command(request)); 2219 2220 lba = request->u.ata.lba; 2221 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 2222 /* enable interrupt */ 2223 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 2224 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 2225 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 2226 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff)); 2227 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) | 2228 ((lba >> 8) & 0x00ff)); 2229 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) | 2230 ((lba >> 16) & 0x00ff)); 2231 2232 /* issue command to controller */ 2233 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 2234 2235 return 0; 2236 } 2237 2238 static void 2239 ata_intel_31244_reset(device_t dev) 2240 { 2241 if (ata_sata_phy_reset(dev)) 2242 ata_generic_reset(dev); 2243 } 2244 2245 2246 /* 2247 * Integrated Technology Express Inc. (ITE) chipset support functions 2248 */ 2249 int 2250 ata_ite_ident(device_t dev) 2251 { 2252 struct ata_pci_controller *ctlr = device_get_softc(dev); 2253 struct ata_chip_id *idx; 2254 static struct ata_chip_id ids[] = 2255 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 2256 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 2257 { 0, 0, 0, 0, 0, 0}}; 2258 char buffer[64]; 2259 2260 if (!(idx = ata_match_chip(dev, ids))) 2261 return ENXIO; 2262 2263 ksprintf(buffer, "ITE %s %s controller", 2264 idx->text, ata_mode2str(idx->max_dma)); 2265 device_set_desc_copy(dev, buffer); 2266 ctlr->chip = idx; 2267 ctlr->chipinit = ata_ite_chipinit; 2268 return 0; 2269 } 2270 2271 static int 2272 ata_ite_chipinit(device_t dev) 2273 { 2274 struct ata_pci_controller *ctlr = device_get_softc(dev); 2275 2276 if (ata_setup_interrupt(dev)) 2277 return ENXIO; 2278 2279 ctlr->setmode = ata_ite_setmode; 2280 2281 /* set PCI mode and 66Mhz reference clock */ 2282 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 2283 2284 /* set default active & recover timings */ 2285 pci_write_config(dev, 0x54, 0x31, 1); 2286 pci_write_config(dev, 0x56, 0x31, 1); 2287 return 0; 2288 } 2289 2290 static void 2291 ata_ite_setmode(device_t dev, int mode) 2292 { 2293 device_t gparent = GRANDPARENT(dev); 2294 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2295 struct ata_device *atadev = device_get_softc(dev); 2296 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2297 int error; 2298 2299 /* correct the mode for what the HW supports */ 2300 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2301 2302 /* check the CBLID bits for 80 conductor cable detection */ 2303 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) & 2304 (ch->unit ? (1<<3) : (1<<2)))) { 2305 ata_print_cable(dev, "controller"); 2306 mode = ATA_UDMA2; 2307 } 2308 2309 /* set the wanted mode on the device */ 2310 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2311 2312 if (bootverbose) 2313 device_printf(dev, "%s setting %s on ITE8212F chip\n", 2314 (error) ? "failed" : "success", ata_mode2str(mode)); 2315 2316 /* if the device accepted the mode change, setup the HW accordingly */ 2317 if (!error) { 2318 if (mode >= ATA_UDMA0) { 2319 u_int8_t udmatiming[] = 2320 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 2321 2322 /* enable UDMA mode */ 2323 pci_write_config(gparent, 0x50, 2324 pci_read_config(gparent, 0x50, 1) & 2325 ~(1 << (devno + 3)), 1); 2326 2327 /* set UDMA timing */ 2328 pci_write_config(gparent, 2329 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit), 2330 udmatiming[mode & ATA_MODE_MASK], 1); 2331 } 2332 else { 2333 u_int8_t chtiming[] = 2334 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 2335 2336 /* disable UDMA mode */ 2337 pci_write_config(gparent, 0x50, 2338 pci_read_config(gparent, 0x50, 1) | 2339 (1 << (devno + 3)), 1); 2340 2341 /* set active and recover timing (shared between master & slave) */ 2342 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) < 2343 chtiming[ata_mode2idx(mode)]) 2344 pci_write_config(gparent, 0x54 + (ch->unit << 2), 2345 chtiming[ata_mode2idx(mode)], 1); 2346 } 2347 atadev->mode = mode; 2348 } 2349 } 2350 2351 2352 /* 2353 * JMicron chipset support functions 2354 */ 2355 int 2356 ata_jmicron_ident(device_t dev) 2357 { 2358 struct ata_pci_controller *ctlr = device_get_softc(dev); 2359 struct ata_chip_id *idx; 2360 static struct ata_chip_id ids[] = 2361 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" }, 2362 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" }, 2363 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" }, 2364 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" }, 2365 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" }, 2366 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" }, 2367 { 0, 0, 0, 0, 0, 0}}; 2368 char buffer[64]; 2369 2370 if (!(idx = ata_match_chip(dev, ids))) 2371 return ENXIO; 2372 2373 if ((pci_read_config(dev, 0xdf, 1) & 0x40) && 2374 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1))) 2375 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2376 idx->text, ata_mode2str(ATA_UDMA6)); 2377 else 2378 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2379 idx->text, ata_mode2str(idx->max_dma)); 2380 device_set_desc_copy(dev, buffer); 2381 ctlr->chip = idx; 2382 ctlr->chipinit = ata_jmicron_chipinit; 2383 return 0; 2384 } 2385 2386 static int 2387 ata_jmicron_chipinit(device_t dev) 2388 { 2389 struct ata_pci_controller *ctlr = device_get_softc(dev); 2390 int error; 2391 2392 if (ata_setup_interrupt(dev)) 2393 return ENXIO; 2394 2395 /* do we have multiple PCI functions ? */ 2396 if (pci_read_config(dev, 0xdf, 1) & 0x40) { 2397 /* if we have a memory BAR(5) we are on the AHCI part */ 2398 ctlr->r_type2 = SYS_RES_MEMORY; 2399 ctlr->r_rid2 = PCIR_BAR(5); 2400 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 2401 &ctlr->r_rid2, RF_ACTIVE))) 2402 return ata_ahci_chipinit(dev); 2403 2404 /* otherwise we are on the PATA part */ 2405 ctlr->allocate = ata_pci_allocate; 2406 ctlr->reset = ata_generic_reset; 2407 ctlr->dmainit = ata_pci_dmainit; 2408 ctlr->setmode = ata_jmicron_setmode; 2409 ctlr->channels = ctlr->chip->cfg2; 2410 } 2411 else { 2412 /* set controller configuration to a combined setup we support */ 2413 pci_write_config(dev, 0x40, 0x80c0a131, 4); 2414 pci_write_config(dev, 0x80, 0x01200000, 4); 2415 2416 ctlr->r_type2 = SYS_RES_MEMORY; 2417 ctlr->r_rid2 = PCIR_BAR(5); 2418 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 2419 &ctlr->r_rid2, RF_ACTIVE))) { 2420 if ((error = ata_ahci_chipinit(dev))) 2421 return error; 2422 } 2423 2424 ctlr->allocate = ata_jmicron_allocate; 2425 ctlr->reset = ata_jmicron_reset; 2426 ctlr->dmainit = ata_jmicron_dmainit; 2427 ctlr->setmode = ata_jmicron_setmode; 2428 2429 /* set the number of HW channels */ 2430 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2; 2431 } 2432 return 0; 2433 } 2434 2435 static int 2436 ata_jmicron_allocate(device_t dev) 2437 { 2438 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2439 struct ata_channel *ch = device_get_softc(dev); 2440 int error; 2441 2442 if (ch->unit >= ctlr->chip->cfg1) { 2443 ch->unit -= ctlr->chip->cfg1; 2444 error = ata_pci_allocate(dev); 2445 ch->unit += ctlr->chip->cfg1; 2446 } 2447 else 2448 error = ata_ahci_allocate(dev); 2449 return error; 2450 } 2451 2452 static void 2453 ata_jmicron_reset(device_t dev) 2454 { 2455 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2456 struct ata_channel *ch = device_get_softc(dev); 2457 2458 if (ch->unit >= ctlr->chip->cfg1) 2459 ata_generic_reset(dev); 2460 else 2461 ata_ahci_reset(dev); 2462 } 2463 2464 static void 2465 ata_jmicron_dmainit(device_t dev) 2466 { 2467 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2468 struct ata_channel *ch = device_get_softc(dev); 2469 2470 if (ch->unit >= ctlr->chip->cfg1) 2471 ata_pci_dmainit(dev); 2472 else 2473 ata_ahci_dmainit(dev); 2474 } 2475 2476 static void 2477 ata_jmicron_setmode(device_t dev, int mode) 2478 { 2479 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 2480 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2481 2482 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) { 2483 struct ata_device *atadev = device_get_softc(dev); 2484 2485 /* check for 80pin cable present */ 2486 if (pci_read_config(dev, 0x40, 1) & 0x08) 2487 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 2488 else 2489 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2490 2491 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2492 atadev->mode = mode; 2493 } 2494 else 2495 ata_sata_setmode(dev, mode); 2496 } 2497 2498 2499 /* 2500 * Marvell chipset support functions 2501 */ 2502 #define ATA_MV_HOST_BASE(ch) \ 2503 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000) 2504 #define ATA_MV_EDMA_BASE(ch) \ 2505 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000) 2506 2507 struct ata_marvell_response { 2508 u_int16_t tag; 2509 u_int8_t edma_status; 2510 u_int8_t dev_status; 2511 u_int32_t timestamp; 2512 }; 2513 2514 struct ata_marvell_dma_prdentry { 2515 u_int32_t addrlo; 2516 u_int32_t count; 2517 u_int32_t addrhi; 2518 u_int32_t reserved; 2519 }; 2520 2521 int 2522 ata_marvell_ident(device_t dev) 2523 { 2524 struct ata_pci_controller *ctlr = device_get_softc(dev); 2525 struct ata_chip_id *idx; 2526 static struct ata_chip_id ids[] = 2527 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" }, 2528 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" }, 2529 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" }, 2530 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" }, 2531 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" }, 2532 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" }, 2533 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" }, 2534 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" }, 2535 { 0, 0, 0, 0, 0, 0}}; 2536 char buffer[64]; 2537 2538 if (!(idx = ata_match_chip(dev, ids))) 2539 return ENXIO; 2540 2541 ksprintf(buffer, "Marvell %s %s controller", 2542 idx->text, ata_mode2str(idx->max_dma)); 2543 device_set_desc_copy(dev, buffer); 2544 ctlr->chip = idx; 2545 switch (ctlr->chip->cfg2) { 2546 case MV50XX: 2547 case MV60XX: 2548 ctlr->chipinit = ata_marvell_edma_chipinit; 2549 break; 2550 case MV61XX: 2551 ctlr->chipinit = ata_marvell_pata_chipinit; 2552 break; 2553 } 2554 return 0; 2555 } 2556 2557 static int 2558 ata_marvell_pata_chipinit(device_t dev) 2559 { 2560 struct ata_pci_controller *ctlr = device_get_softc(dev); 2561 2562 if (ata_setup_interrupt(dev)) 2563 return ENXIO; 2564 2565 ctlr->allocate = ata_marvell_pata_allocate; 2566 ctlr->setmode = ata_marvell_pata_setmode; 2567 ctlr->channels = ctlr->chip->cfg1; 2568 return 0; 2569 } 2570 2571 static int 2572 ata_marvell_pata_allocate(device_t dev) 2573 { 2574 struct ata_channel *ch = device_get_softc(dev); 2575 2576 /* setup the usual register normal pci style */ 2577 if (ata_pci_allocate(dev)) 2578 return ENXIO; 2579 2580 /* dont use 32 bit PIO transfers */ 2581 ch->flags |= ATA_USE_16BIT; 2582 2583 return 0; 2584 } 2585 2586 static void 2587 ata_marvell_pata_setmode(device_t dev, int mode) 2588 { 2589 device_t gparent = GRANDPARENT(dev); 2590 struct ata_pci_controller *ctlr = device_get_softc(gparent); 2591 struct ata_device *atadev = device_get_softc(dev); 2592 2593 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 2594 mode = ata_check_80pin(dev, mode); 2595 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2596 atadev->mode = mode; 2597 } 2598 2599 static int 2600 ata_marvell_edma_chipinit(device_t dev) 2601 { 2602 struct ata_pci_controller *ctlr = device_get_softc(dev); 2603 2604 if (ata_setup_interrupt(dev)) 2605 return ENXIO; 2606 2607 ctlr->r_type1 = SYS_RES_MEMORY; 2608 ctlr->r_rid1 = PCIR_BAR(0); 2609 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 2610 &ctlr->r_rid1, RF_ACTIVE))) 2611 return ENXIO; 2612 2613 /* mask all host controller interrupts */ 2614 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000); 2615 2616 /* mask all PCI interrupts */ 2617 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000); 2618 2619 ctlr->allocate = ata_marvell_edma_allocate; 2620 ctlr->reset = ata_marvell_edma_reset; 2621 ctlr->dmainit = ata_marvell_edma_dmainit; 2622 ctlr->setmode = ata_sata_setmode; 2623 ctlr->channels = ctlr->chip->cfg1; 2624 2625 /* clear host controller interrupts */ 2626 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000); 2627 if (ctlr->chip->cfg1 > 4) 2628 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000); 2629 2630 /* clear PCI interrupts */ 2631 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000); 2632 2633 /* unmask PCI interrupts we want */ 2634 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff); 2635 2636 /* unmask host controller interrupts we want */ 2637 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ | 2638 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25)); 2639 2640 /* enable PCI interrupt */ 2641 pci_write_config(dev, PCIR_COMMAND, 2642 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 2643 return 0; 2644 } 2645 2646 static int 2647 ata_marvell_edma_allocate(device_t dev) 2648 { 2649 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2650 struct ata_channel *ch = device_get_softc(dev); 2651 u_int64_t work = ch->dma->work_bus; 2652 int i; 2653 2654 /* clear work area */ 2655 bzero(ch->dma->work, 1024+256); 2656 2657 /* set legacy ATA resources */ 2658 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 2659 ch->r_io[i].res = ctlr->r_res1; 2660 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch); 2661 } 2662 ch->r_io[ATA_CONTROL].res = ctlr->r_res1; 2663 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch); 2664 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1; 2665 ata_default_registers(dev); 2666 2667 /* set SATA resources */ 2668 switch (ctlr->chip->cfg2) { 2669 case MV50XX: 2670 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2671 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch); 2672 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2673 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch); 2674 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2675 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch); 2676 break; 2677 case MV60XX: 2678 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2679 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch); 2680 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2681 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch); 2682 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2683 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch); 2684 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1; 2685 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch); 2686 break; 2687 } 2688 2689 ch->flags |= ATA_NO_SLAVE; 2690 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */ 2691 ata_generic_hw(dev); 2692 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction; 2693 ch->hw.end_transaction = ata_marvell_edma_end_transaction; 2694 ch->hw.status = ata_marvell_edma_status; 2695 2696 /* disable the EDMA machinery */ 2697 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2698 DELAY(100000); /* SOS should poll for disabled */ 2699 2700 /* set configuration to non-queued 128b read transfers stop on error */ 2701 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13)); 2702 2703 /* request queue base high */ 2704 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32); 2705 2706 /* request queue in ptr */ 2707 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2708 2709 /* request queue out ptr */ 2710 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0); 2711 2712 /* response queue base high */ 2713 work += 1024; 2714 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32); 2715 2716 /* response queue in ptr */ 2717 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0); 2718 2719 /* response queue out ptr */ 2720 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2721 2722 /* clear SATA error register */ 2723 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 2724 2725 /* clear any outstanding error interrupts */ 2726 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2727 2728 /* unmask all error interrupts */ 2729 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 2730 2731 /* enable EDMA machinery */ 2732 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2733 return 0; 2734 } 2735 2736 static int 2737 ata_marvell_edma_status(device_t dev) 2738 { 2739 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2740 struct ata_channel *ch = device_get_softc(dev); 2741 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60); 2742 int shift = (ch->unit << 1) + (ch->unit > 3); 2743 2744 if (cause & (1 << shift)) { 2745 2746 /* clear interrupt(s) */ 2747 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2748 2749 /* do we have any PHY events ? */ 2750 ata_sata_phy_check_events(dev); 2751 } 2752 2753 /* do we have any device action ? */ 2754 return (cause & (2 << shift)); 2755 } 2756 2757 /* must be called with ATA channel locked and state_mtx held */ 2758 static int 2759 ata_marvell_edma_begin_transaction(struct ata_request *request) 2760 { 2761 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2762 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2763 u_int32_t req_in; 2764 u_int8_t *bytep; 2765 u_int16_t *wordp; 2766 u_int32_t *quadp; 2767 int i, tag = 0x07; 2768 int dummy, error, slot; 2769 2770 /* only DMA R/W goes through the EMDA machine */ 2771 if (request->u.ata.command != ATA_READ_DMA && 2772 request->u.ata.command != ATA_WRITE_DMA) { 2773 2774 /* disable the EDMA machinery */ 2775 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001) 2776 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2777 return ata_begin_transaction(request); 2778 } 2779 2780 /* check for 48 bit access and convert if needed */ 2781 ata_modify_if_48bit(request); 2782 2783 /* check sanity, setup SG list and DMA engine */ 2784 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 2785 request->flags & ATA_R_READ, ch->dma->sg, 2786 &dummy))) { 2787 device_printf(request->dev, "setting up DMA failed\n"); 2788 request->result = error; 2789 return ATA_OP_FINISHED; 2790 } 2791 2792 /* get next free request queue slot */ 2793 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch)); 2794 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f; 2795 bytep = (u_int8_t *)(ch->dma->work); 2796 bytep += (slot << 5); 2797 wordp = (u_int16_t *)bytep; 2798 quadp = (u_int32_t *)bytep; 2799 2800 /* fill in this request */ 2801 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff; 2802 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32; 2803 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1); 2804 2805 i = 10; 2806 bytep[i++] = (request->u.ata.count >> 8) & 0xff; 2807 bytep[i++] = 0x10 | ATA_COUNT; 2808 bytep[i++] = request->u.ata.count & 0xff; 2809 bytep[i++] = 0x10 | ATA_COUNT; 2810 2811 bytep[i++] = (request->u.ata.lba >> 24) & 0xff; 2812 bytep[i++] = 0x10 | ATA_SECTOR; 2813 bytep[i++] = request->u.ata.lba & 0xff; 2814 bytep[i++] = 0x10 | ATA_SECTOR; 2815 2816 bytep[i++] = (request->u.ata.lba >> 32) & 0xff; 2817 bytep[i++] = 0x10 | ATA_CYL_LSB; 2818 bytep[i++] = (request->u.ata.lba >> 8) & 0xff; 2819 bytep[i++] = 0x10 | ATA_CYL_LSB; 2820 2821 bytep[i++] = (request->u.ata.lba >> 40) & 0xff; 2822 bytep[i++] = 0x10 | ATA_CYL_MSB; 2823 bytep[i++] = (request->u.ata.lba >> 16) & 0xff; 2824 bytep[i++] = 0x10 | ATA_CYL_MSB; 2825 2826 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf); 2827 bytep[i++] = 0x10 | ATA_DRIVE; 2828 2829 bytep[i++] = request->u.ata.command; 2830 bytep[i++] = 0x90 | ATA_COMMAND; 2831 2832 /* enable EDMA machinery if needed */ 2833 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) { 2834 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2835 while (!(ATA_INL(ctlr->r_res1, 2836 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 2837 DELAY(10); 2838 } 2839 2840 /* tell EDMA it has a new request */ 2841 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f; 2842 req_in &= 0xfffffc00; 2843 req_in += (slot << 5); 2844 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in); 2845 2846 return ATA_OP_CONTINUES; 2847 } 2848 2849 /* must be called with ATA channel locked and state_mtx held */ 2850 static int 2851 ata_marvell_edma_end_transaction(struct ata_request *request) 2852 { 2853 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2854 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2855 int offset = (ch->unit > 3 ? 0x30014 : 0x20014); 2856 u_int32_t icr = ATA_INL(ctlr->r_res1, offset); 2857 int res; 2858 2859 /* EDMA interrupt */ 2860 if ((icr & (0x0001 << (ch->unit & 3)))) { 2861 struct ata_marvell_response *response; 2862 u_int32_t rsp_in, rsp_out; 2863 int slot; 2864 2865 /* stop timeout */ 2866 callout_stop(&request->callout); 2867 2868 /* get response ptr's */ 2869 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch)); 2870 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch)); 2871 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f; 2872 rsp_out &= 0xffffff00; 2873 rsp_out += (slot << 3); 2874 response = (struct ata_marvell_response *) 2875 (ch->dma->work + 1024 + (slot << 3)); 2876 2877 /* record status for this request */ 2878 request->status = response->dev_status; 2879 request->error = 0; 2880 2881 /* ack response */ 2882 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out); 2883 2884 /* update progress */ 2885 if (!(request->status & ATA_S_ERROR) && 2886 !(request->flags & ATA_R_TIMEOUT)) 2887 request->donecount = request->bytecount; 2888 2889 /* unload SG list */ 2890 ch->dma->unload(ch->dev); 2891 2892 res = ATA_OP_FINISHED; 2893 } 2894 2895 /* legacy ATA interrupt */ 2896 else { 2897 res = ata_end_transaction(request); 2898 } 2899 2900 /* ack interrupt */ 2901 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3)))); 2902 return res; 2903 } 2904 2905 static void 2906 ata_marvell_edma_reset(device_t dev) 2907 { 2908 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2909 struct ata_channel *ch = device_get_softc(dev); 2910 2911 /* disable the EDMA machinery */ 2912 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2913 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 2914 DELAY(10); 2915 2916 /* clear SATA error register */ 2917 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 2918 2919 /* clear any outstanding error interrupts */ 2920 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2921 2922 /* unmask all error interrupts */ 2923 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 2924 2925 /* enable channel and test for devices */ 2926 if (ata_sata_phy_reset(dev)) 2927 ata_generic_reset(dev); 2928 2929 /* enable EDMA machinery */ 2930 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2931 } 2932 2933 static void 2934 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, 2935 int error) 2936 { 2937 struct ata_dmasetprd_args *args = xsc; 2938 struct ata_marvell_dma_prdentry *prd = args->dmatab; 2939 int i; 2940 2941 if ((args->error = error)) 2942 return; 2943 2944 for (i = 0; i < nsegs; i++) { 2945 prd[i].addrlo = htole32(segs[i].ds_addr); 2946 prd[i].count = htole32(segs[i].ds_len); 2947 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32); 2948 } 2949 prd[i - 1].count |= htole32(ATA_DMA_EOT); 2950 } 2951 2952 static void 2953 ata_marvell_edma_dmainit(device_t dev) 2954 { 2955 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2956 struct ata_channel *ch = device_get_softc(dev); 2957 2958 ata_dmainit(dev); 2959 if (ch->dma) { 2960 /* note start and stop are not used here */ 2961 ch->dma->setprd = ata_marvell_edma_dmasetprd; 2962 2963 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004) 2964 ch->dma->max_address = BUS_SPACE_MAXADDR; 2965 } 2966 } 2967 2968 2969 /* 2970 * National chipset support functions 2971 */ 2972 int 2973 ata_national_ident(device_t dev) 2974 { 2975 struct ata_pci_controller *ctlr = device_get_softc(dev); 2976 2977 /* this chip is a clone of the Cyrix chip, bugs and all */ 2978 if (pci_get_devid(dev) == ATA_SC1100) { 2979 device_set_desc(dev, "National Geode SC1100 ATA33 controller"); 2980 ctlr->chipinit = ata_national_chipinit; 2981 return 0; 2982 } 2983 return ENXIO; 2984 } 2985 2986 static int 2987 ata_national_chipinit(device_t dev) 2988 { 2989 struct ata_pci_controller *ctlr = device_get_softc(dev); 2990 2991 if (ata_setup_interrupt(dev)) 2992 return ENXIO; 2993 2994 ctlr->setmode = ata_national_setmode; 2995 return 0; 2996 } 2997 2998 static void 2999 ata_national_setmode(device_t dev, int mode) 3000 { 3001 device_t gparent = GRANDPARENT(dev); 3002 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3003 struct ata_device *atadev = device_get_softc(dev); 3004 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3005 u_int32_t piotiming[] = 3006 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010, 3007 0x00803020, 0x20102010, 0x00100010, 3008 0x00100010, 0x00100010, 0x00100010 }; 3009 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 }; 3010 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 }; 3011 int error; 3012 3013 ch->dma->alignment = 16; 3014 ch->dma->max_iosize = 126 * DEV_BSIZE; 3015 3016 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 3017 3018 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3019 3020 if (bootverbose) 3021 device_printf(dev, "%s setting %s on National chip\n", 3022 (error) ? "failed" : "success", ata_mode2str(mode)); 3023 if (!error) { 3024 if (mode >= ATA_UDMA0) { 3025 pci_write_config(gparent, 0x44 + (devno << 3), 3026 udmatiming[mode & ATA_MODE_MASK], 4); 3027 } 3028 else if (mode >= ATA_WDMA0) { 3029 pci_write_config(gparent, 0x44 + (devno << 3), 3030 dmatiming[mode & ATA_MODE_MASK], 4); 3031 } 3032 else { 3033 pci_write_config(gparent, 0x44 + (devno << 3), 3034 pci_read_config(gparent, 0x44 + (devno << 3), 4) | 3035 0x80000000, 4); 3036 } 3037 pci_write_config(gparent, 0x40 + (devno << 3), 3038 piotiming[ata_mode2idx(mode)], 4); 3039 atadev->mode = mode; 3040 } 3041 } 3042 3043 /* 3044 * NetCell chipset support functions 3045 */ 3046 int 3047 ata_netcell_ident(device_t dev) 3048 { 3049 struct ata_pci_controller *ctlr = device_get_softc(dev); 3050 3051 if (pci_get_devid(dev) == ATA_NETCELL_SR) { 3052 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller"); 3053 ctlr->chipinit = ata_netcell_chipinit; 3054 return 0; 3055 } 3056 return ENXIO; 3057 } 3058 3059 static int 3060 ata_netcell_chipinit(device_t dev) 3061 { 3062 struct ata_pci_controller *ctlr = device_get_softc(dev); 3063 3064 if (ata_generic_chipinit(dev)) 3065 return ENXIO; 3066 3067 ctlr->allocate = ata_netcell_allocate; 3068 return 0; 3069 } 3070 3071 static int 3072 ata_netcell_allocate(device_t dev) 3073 { 3074 struct ata_channel *ch = device_get_softc(dev); 3075 3076 /* setup the usual register normal pci style */ 3077 if (ata_pci_allocate(dev)) 3078 return ENXIO; 3079 3080 /* the NetCell only supports 16 bit PIO transfers */ 3081 ch->flags |= ATA_USE_16BIT; 3082 3083 return 0; 3084 } 3085 3086 3087 /* 3088 * nVidia chipset support functions 3089 */ 3090 int 3091 ata_nvidia_ident(device_t dev) 3092 { 3093 struct ata_pci_controller *ctlr = device_get_softc(dev); 3094 struct ata_chip_id *idx; 3095 static struct ata_chip_id ids[] = 3096 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" }, 3097 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" }, 3098 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" }, 3099 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" }, 3100 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" }, 3101 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" }, 3102 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3103 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3104 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" }, 3105 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3106 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3107 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" }, 3108 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3109 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3110 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" }, 3111 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3112 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3113 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" }, 3114 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3115 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3116 { 0, 0, 0, 0, 0, 0}} ; 3117 char buffer[64] ; 3118 3119 if (!(idx = ata_match_chip(dev, ids))) 3120 return ENXIO; 3121 3122 ksprintf(buffer, "nVidia %s %s controller", 3123 idx->text, ata_mode2str(idx->max_dma)); 3124 device_set_desc_copy(dev, buffer); 3125 ctlr->chip = idx; 3126 ctlr->chipinit = ata_nvidia_chipinit; 3127 return 0; 3128 } 3129 3130 static int 3131 ata_nvidia_chipinit(device_t dev) 3132 { 3133 struct ata_pci_controller *ctlr = device_get_softc(dev); 3134 3135 if (ata_setup_interrupt(dev)) 3136 return ENXIO; 3137 3138 if (ctlr->chip->max_dma >= ATA_SA150) { 3139 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1) 3140 ctlr->r_type2 = SYS_RES_IOPORT; 3141 else 3142 ctlr->r_type2 = SYS_RES_MEMORY; 3143 ctlr->r_rid2 = PCIR_BAR(5); 3144 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3145 &ctlr->r_rid2, RF_ACTIVE))) { 3146 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3147 3148 ctlr->allocate = ata_nvidia_allocate; 3149 ctlr->reset = ata_nvidia_reset; 3150 3151 /* enable control access */ 3152 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1); 3153 3154 if (ctlr->chip->cfg2 & NVQ) { 3155 /* clear interrupt status */ 3156 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff); 3157 3158 /* enable device and PHY state change interrupts */ 3159 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d); 3160 3161 /* disable NCQ support */ 3162 ATA_OUTL(ctlr->r_res2, 0x0400, 3163 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9); 3164 } 3165 else { 3166 /* clear interrupt status */ 3167 ATA_OUTB(ctlr->r_res2, offset, 0xff); 3168 3169 /* enable device and PHY state change interrupts */ 3170 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd); 3171 } 3172 3173 /* enable PCI interrupt */ 3174 pci_write_config(dev, PCIR_COMMAND, 3175 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 3176 3177 } 3178 ctlr->setmode = ata_sata_setmode; 3179 } 3180 else { 3181 /* disable prefetch, postwrite */ 3182 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1); 3183 ctlr->setmode = ata_via_family_setmode; 3184 } 3185 return 0; 3186 } 3187 3188 static int 3189 ata_nvidia_allocate(device_t dev) 3190 { 3191 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3192 struct ata_channel *ch = device_get_softc(dev); 3193 3194 /* setup the usual register normal pci style */ 3195 if (ata_pci_allocate(dev)) 3196 return ENXIO; 3197 3198 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3199 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6); 3200 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3201 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6); 3202 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3203 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6); 3204 3205 ch->hw.status = ata_nvidia_status; 3206 ch->flags |= ATA_NO_SLAVE; 3207 3208 return 0; 3209 } 3210 3211 static int 3212 ata_nvidia_status(device_t dev) 3213 { 3214 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3215 struct ata_channel *ch = device_get_softc(dev); 3216 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3217 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2); 3218 u_int32_t istatus = ATA_INL(ctlr->r_res2, offset); 3219 3220 /* do we have any PHY events ? */ 3221 if (istatus & (0x0c << shift)) 3222 ata_sata_phy_check_events(dev); 3223 3224 /* clear interrupt(s) */ 3225 ATA_OUTB(ctlr->r_res2, offset, 3226 (0x0f << shift) | (ctlr->chip->cfg2 & NVQ ? 0x00f000f0 : 0)); 3227 3228 /* do we have any device action ? */ 3229 return (istatus & (0x01 << shift)); 3230 } 3231 3232 static void 3233 ata_nvidia_reset(device_t dev) 3234 { 3235 if (ata_sata_phy_reset(dev)) 3236 ata_generic_reset(dev); 3237 } 3238 3239 3240 /* 3241 * Promise chipset support functions 3242 */ 3243 #define ATA_PDC_APKT_OFFSET 0x00000010 3244 #define ATA_PDC_HPKT_OFFSET 0x00000040 3245 #define ATA_PDC_ASG_OFFSET 0x00000080 3246 #define ATA_PDC_LSG_OFFSET 0x000000c0 3247 #define ATA_PDC_HSG_OFFSET 0x00000100 3248 #define ATA_PDC_CHN_OFFSET 0x00000400 3249 #define ATA_PDC_BUF_BASE 0x00400000 3250 #define ATA_PDC_BUF_OFFSET 0x00100000 3251 #define ATA_PDC_MAX_HPKT 8 3252 #define ATA_PDC_WRITE_REG 0x00 3253 #define ATA_PDC_WRITE_CTL 0x0e 3254 #define ATA_PDC_WRITE_END 0x08 3255 #define ATA_PDC_WAIT_NBUSY 0x10 3256 #define ATA_PDC_WAIT_READY 0x18 3257 #define ATA_PDC_1B 0x20 3258 #define ATA_PDC_2B 0x40 3259 3260 struct host_packet { 3261 u_int32_t addr; 3262 TAILQ_ENTRY(host_packet) chain; 3263 }; 3264 3265 struct ata_promise_sx4 { 3266 struct spinlock mtx; 3267 TAILQ_HEAD(, host_packet) queue; 3268 int busy; 3269 }; 3270 3271 int 3272 ata_promise_ident(device_t dev) 3273 { 3274 struct ata_pci_controller *ctlr = device_get_softc(dev); 3275 struct ata_chip_id *idx; 3276 static struct ata_chip_id ids[] = 3277 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" }, 3278 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" }, 3279 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" }, 3280 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" }, 3281 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" }, 3282 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" }, 3283 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" }, 3284 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" }, 3285 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" }, 3286 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" }, 3287 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" }, 3288 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" }, 3289 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" }, 3290 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" }, 3291 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" }, 3292 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" }, 3293 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" }, 3294 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" }, 3295 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" }, 3296 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" }, 3297 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" }, 3298 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" }, 3299 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" }, 3300 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" }, 3301 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" }, 3302 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" }, 3303 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" }, 3304 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" }, 3305 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" }, 3306 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" }, 3307 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" }, 3308 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" }, 3309 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" }, 3310 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" }, 3311 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" }, 3312 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" }, 3313 { 0, 0, 0, 0, 0, 0}}; 3314 char buffer[64]; 3315 uintptr_t devid = 0; 3316 3317 if (!(idx = ata_match_chip(dev, ids))) 3318 return ENXIO; 3319 3320 /* if we are on a SuperTrak SX6000 dont attach */ 3321 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3322 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3323 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3324 devid == ATA_I960RM) 3325 return ENXIO; 3326 3327 strcpy(buffer, "Promise "); 3328 strcat(buffer, idx->text); 3329 3330 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 3331 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3332 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3333 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3334 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 3335 static long start = 0, end = 0; 3336 3337 if (pci_get_slot(dev) == 1) { 3338 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 3339 strcat(buffer, " (channel 0+1)"); 3340 } 3341 else if (pci_get_slot(dev) == 2 && start && end) { 3342 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 3343 strcat(buffer, " (channel 2+3)"); 3344 } 3345 else { 3346 start = end = 0; 3347 } 3348 } 3349 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 3350 device_set_desc_copy(dev, buffer); 3351 ctlr->chip = idx; 3352 ctlr->chipinit = ata_promise_chipinit; 3353 return 0; 3354 } 3355 3356 static int 3357 ata_promise_chipinit(device_t dev) 3358 { 3359 struct ata_pci_controller *ctlr = device_get_softc(dev); 3360 int fake_reg, stat_reg; 3361 3362 if (ata_setup_interrupt(dev)) 3363 return ENXIO; 3364 3365 switch (ctlr->chip->cfg1) { 3366 case PRNEW: 3367 /* setup clocks */ 3368 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 3369 3370 ctlr->dmainit = ata_promise_dmainit; 3371 /* FALLTHROUGH */ 3372 3373 case PROLD: 3374 /* enable burst mode */ 3375 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 3376 ctlr->allocate = ata_promise_allocate; 3377 ctlr->setmode = ata_promise_setmode; 3378 return 0; 3379 3380 case PRTX: 3381 ctlr->allocate = ata_promise_tx2_allocate; 3382 ctlr->setmode = ata_promise_setmode; 3383 return 0; 3384 3385 case PRMIO: 3386 ctlr->r_type1 = SYS_RES_MEMORY; 3387 ctlr->r_rid1 = PCIR_BAR(4); 3388 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 3389 &ctlr->r_rid1, RF_ACTIVE))) 3390 goto failnfree; 3391 3392 ctlr->r_type2 = SYS_RES_MEMORY; 3393 ctlr->r_rid2 = PCIR_BAR(3); 3394 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3395 &ctlr->r_rid2, RF_ACTIVE))) 3396 goto failnfree; 3397 3398 if (ctlr->chip->cfg2 == PRSX4X) { 3399 struct ata_promise_sx4 *hpkt; 3400 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 3401 3402 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3403 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3404 ata_promise_sx4_intr, ctlr, &ctlr->handle, NULL)) { 3405 device_printf(dev, "unable to setup interrupt\n"); 3406 goto failnfree; 3407 } 3408 3409 /* print info about cache memory */ 3410 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 3411 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 3412 ((dimm >> 24) & 0xff), 3413 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 3414 " ECC enabled" : "" ); 3415 3416 /* adjust cache memory parameters */ 3417 ATA_OUTL(ctlr->r_res2, 0x000c000c, 3418 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 3419 3420 /* setup host packet controls */ 3421 hpkt = kmalloc(sizeof(struct ata_promise_sx4), 3422 M_TEMP, M_INTWAIT | M_ZERO); 3423 spin_init(&hpkt->mtx); 3424 TAILQ_INIT(&hpkt->queue); 3425 hpkt->busy = 0; 3426 device_set_ivars(dev, hpkt); 3427 ctlr->allocate = ata_promise_mio_allocate; 3428 ctlr->reset = ata_promise_mio_reset; 3429 ctlr->dmainit = ata_promise_mio_dmainit; 3430 ctlr->setmode = ata_promise_setmode; 3431 ctlr->channels = 4; 3432 return 0; 3433 } 3434 3435 /* mio type controllers need an interrupt intercept */ 3436 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3437 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3438 ata_promise_mio_intr, ctlr, &ctlr->handle, NULL)) { 3439 device_printf(dev, "unable to setup interrupt\n"); 3440 goto failnfree; 3441 } 3442 3443 switch (ctlr->chip->cfg2) { 3444 case PRPATA: 3445 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 3446 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 3447 goto sata150; 3448 case PRCMBO: 3449 ctlr->channels = 3; 3450 goto sata150; 3451 case PRSATA: 3452 ctlr->channels = 4; 3453 sata150: 3454 fake_reg = 0x60; 3455 stat_reg = 0x6c; 3456 break; 3457 3458 case PRCMBO2: 3459 ctlr->channels = 3; 3460 goto sataii; 3461 case PRSATA2: 3462 default: 3463 ctlr->channels = 4; 3464 sataii: 3465 fake_reg = 0x54; 3466 stat_reg = 0x60; 3467 break; 3468 } 3469 3470 /* prime fake interrupt register */ 3471 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3472 3473 /* clear SATA status */ 3474 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 3475 3476 ctlr->allocate = ata_promise_mio_allocate; 3477 ctlr->reset = ata_promise_mio_reset; 3478 ctlr->dmainit = ata_promise_mio_dmainit; 3479 ctlr->setmode = ata_promise_mio_setmode; 3480 3481 return 0; 3482 } 3483 3484 failnfree: 3485 if (ctlr->r_res2) 3486 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 3487 if (ctlr->r_res1) 3488 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 3489 return ENXIO; 3490 } 3491 3492 static int 3493 ata_promise_allocate(device_t dev) 3494 { 3495 struct ata_channel *ch = device_get_softc(dev); 3496 3497 if (ata_pci_allocate(dev)) 3498 return ENXIO; 3499 3500 ch->hw.status = ata_promise_status; 3501 return 0; 3502 } 3503 3504 static int 3505 ata_promise_status(device_t dev) 3506 { 3507 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3508 struct ata_channel *ch = device_get_softc(dev); 3509 3510 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 3511 return ata_pci_status(dev); 3512 } 3513 return 0; 3514 } 3515 3516 static int 3517 ata_promise_dmastart(device_t dev) 3518 { 3519 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3520 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3521 struct ata_device *atadev = device_get_softc(dev); 3522 3523 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3524 ATA_OUTB(ctlr->r_res1, 0x11, 3525 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 3526 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 3527 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) | 3528 (ch->dma->cur_iosize >> 1)); 3529 } 3530 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 3531 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 3532 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus); 3533 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3534 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) | 3535 ATA_BMCMD_START_STOP); 3536 ch->flags |= ATA_DMA_ACTIVE; 3537 return 0; 3538 } 3539 3540 static int 3541 ata_promise_dmastop(device_t dev) 3542 { 3543 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3544 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3545 struct ata_device *atadev = device_get_softc(dev); 3546 int error; 3547 3548 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3549 ATA_OUTB(ctlr->r_res1, 0x11, 3550 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 3551 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 3552 } 3553 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 3554 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3555 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3556 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3557 ch->flags &= ~ATA_DMA_ACTIVE; 3558 return error; 3559 } 3560 3561 static void 3562 ata_promise_dmareset(device_t dev) 3563 { 3564 struct ata_channel *ch = device_get_softc(dev); 3565 3566 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3567 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3568 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3569 ch->flags &= ~ATA_DMA_ACTIVE; 3570 } 3571 3572 static void 3573 ata_promise_dmainit(device_t dev) 3574 { 3575 struct ata_channel *ch = device_get_softc(dev); 3576 3577 ata_dmainit(dev); 3578 if (ch->dma) { 3579 ch->dma->start = ata_promise_dmastart; 3580 ch->dma->stop = ata_promise_dmastop; 3581 ch->dma->reset = ata_promise_dmareset; 3582 } 3583 } 3584 3585 static void 3586 ata_promise_setmode(device_t dev, int mode) 3587 { 3588 device_t gparent = GRANDPARENT(dev); 3589 struct ata_pci_controller *ctlr = device_get_softc(gparent); 3590 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3591 struct ata_device *atadev = device_get_softc(dev); 3592 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3593 int error; 3594 u_int32_t timings[][2] = { 3595 /* PROLD PRNEW mode */ 3596 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 3597 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 3598 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 3599 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 3600 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 3601 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 3602 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 3603 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 3604 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 3605 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 3606 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 3607 { 0, 0x00424ef6 }, /* UDMA 3 */ 3608 { 0, 0x004127f3 }, /* UDMA 4 */ 3609 { 0, 0x004127f3 } /* UDMA 5 */ 3610 }; 3611 3612 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 3613 3614 switch (ctlr->chip->cfg1) { 3615 case PROLD: 3616 case PRNEW: 3617 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) & 3618 (ch->unit ? 1 << 11 : 1 << 10))) { 3619 ata_print_cable(dev, "controller"); 3620 mode = ATA_UDMA2; 3621 } 3622 if (ata_atapi(dev) && mode > ATA_PIO_MAX) 3623 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 3624 break; 3625 3626 case PRTX: 3627 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3628 if (mode > ATA_UDMA2 && 3629 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 3630 ata_print_cable(dev, "controller"); 3631 mode = ATA_UDMA2; 3632 } 3633 break; 3634 3635 case PRMIO: 3636 if (mode > ATA_UDMA2 && 3637 (ATA_INL(ctlr->r_res2, 3638 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) + 3639 (ch->unit << 7)) & 0x01000000)) { 3640 ata_print_cable(dev, "controller"); 3641 mode = ATA_UDMA2; 3642 } 3643 break; 3644 } 3645 3646 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3647 3648 if (bootverbose) 3649 device_printf(dev, "%ssetting %s on %s chip\n", 3650 (error) ? "FAILURE " : "", 3651 ata_mode2str(mode), ctlr->chip->text); 3652 if (!error) { 3653 if (ctlr->chip->cfg1 < PRTX) 3654 pci_write_config(gparent, 0x60 + (devno << 2), 3655 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 3656 atadev->mode = mode; 3657 } 3658 return; 3659 } 3660 3661 static int 3662 ata_promise_tx2_allocate(device_t dev) 3663 { 3664 struct ata_channel *ch = device_get_softc(dev); 3665 3666 if (ata_pci_allocate(dev)) 3667 return ENXIO; 3668 3669 ch->hw.status = ata_promise_tx2_status; 3670 return 0; 3671 } 3672 3673 static int 3674 ata_promise_tx2_status(device_t dev) 3675 { 3676 struct ata_channel *ch = device_get_softc(dev); 3677 3678 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3679 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 3680 return ata_pci_status(dev); 3681 } 3682 return 0; 3683 } 3684 3685 static int 3686 ata_promise_mio_allocate(device_t dev) 3687 { 3688 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3689 struct ata_channel *ch = device_get_softc(dev); 3690 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0; 3691 int i; 3692 3693 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 3694 ch->r_io[i].res = ctlr->r_res2; 3695 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 3696 } 3697 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 3698 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 3699 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 3700 ata_default_registers(dev); 3701 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) || 3702 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) { 3703 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3704 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 3705 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3706 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 3707 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3708 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 3709 ch->flags |= ATA_NO_SLAVE; 3710 } 3711 ch->flags |= ATA_USE_16BIT; 3712 3713 ata_generic_hw(dev); 3714 if (ctlr->chip->cfg2 & PRSX4X) { 3715 ch->hw.command = ata_promise_sx4_command; 3716 } 3717 else { 3718 ch->hw.command = ata_promise_mio_command; 3719 ch->hw.status = ata_promise_mio_status; 3720 } 3721 return 0; 3722 } 3723 3724 static void 3725 ata_promise_mio_intr(void *data) 3726 { 3727 struct ata_pci_controller *ctlr = data; 3728 struct ata_channel *ch; 3729 u_int32_t vector; 3730 int unit, fake_reg; 3731 3732 switch (ctlr->chip->cfg2) { 3733 case PRPATA: 3734 case PRCMBO: 3735 case PRSATA: 3736 fake_reg = 0x60; 3737 break; 3738 case PRCMBO2: 3739 case PRSATA2: 3740 default: 3741 fake_reg = 0x54; 3742 break; 3743 } 3744 3745 /* 3746 * since reading interrupt status register on early "mio" chips 3747 * clears the status bits we cannot read it for each channel later on 3748 * in the generic interrupt routine. 3749 * store the bits in an unused register in the chip so we can read 3750 * it from there safely to get around this "feature". 3751 */ 3752 vector = ATA_INL(ctlr->r_res2, 0x040); 3753 ATA_OUTL(ctlr->r_res2, 0x040, vector); 3754 ATA_OUTL(ctlr->r_res2, fake_reg, vector); 3755 3756 for (unit = 0; unit < ctlr->channels; unit++) { 3757 if ((ch = ctlr->interrupt[unit].argument)) 3758 ctlr->interrupt[unit].function(ch); 3759 } 3760 3761 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3762 } 3763 3764 static int 3765 ata_promise_mio_status(device_t dev) 3766 { 3767 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3768 struct ata_channel *ch = device_get_softc(dev); 3769 struct ata_connect_task *tp; 3770 u_int32_t fake_reg, stat_reg, vector, status; 3771 3772 switch (ctlr->chip->cfg2) { 3773 case PRPATA: 3774 case PRCMBO: 3775 case PRSATA: 3776 fake_reg = 0x60; 3777 stat_reg = 0x6c; 3778 break; 3779 case PRCMBO2: 3780 case PRSATA2: 3781 default: 3782 fake_reg = 0x54; 3783 stat_reg = 0x60; 3784 break; 3785 } 3786 3787 /* read and acknowledge interrupt */ 3788 vector = ATA_INL(ctlr->r_res2, fake_reg); 3789 3790 /* read and clear interface status */ 3791 status = ATA_INL(ctlr->r_res2, stat_reg); 3792 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 3793 3794 /* check for and handle disconnect events */ 3795 if ((status & (0x00000001 << ch->unit)) && 3796 (tp = (struct ata_connect_task *) 3797 kmalloc(sizeof(struct ata_connect_task), 3798 M_ATA, M_INTWAIT | M_ZERO))) { 3799 3800 if (bootverbose) 3801 device_printf(ch->dev, "DISCONNECT requested\n"); 3802 tp->action = ATA_C_DETACH; 3803 tp->dev = ch->dev; 3804 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3805 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3806 } 3807 3808 /* check for and handle connect events */ 3809 if ((status & (0x00000010 << ch->unit)) && 3810 (tp = (struct ata_connect_task *) 3811 kmalloc(sizeof(struct ata_connect_task), 3812 M_ATA, M_INTWAIT | M_ZERO))) { 3813 3814 if (bootverbose) 3815 device_printf(ch->dev, "CONNECT requested\n"); 3816 tp->action = ATA_C_ATTACH; 3817 tp->dev = ch->dev; 3818 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3819 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3820 } 3821 3822 /* do we have any device action ? */ 3823 return (vector & (1 << (ch->unit + 1))); 3824 } 3825 3826 static int 3827 ata_promise_mio_command(struct ata_request *request) 3828 { 3829 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 3830 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 3831 u_int32_t *wordp = (u_int32_t *)ch->dma->work; 3832 3833 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 3834 3835 /* XXX SOS add ATAPI commands support later */ 3836 switch (request->u.ata.command) { 3837 default: 3838 return ata_generic_command(request); 3839 3840 case ATA_READ_DMA: 3841 case ATA_READ_DMA48: 3842 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3843 break; 3844 3845 case ATA_WRITE_DMA: 3846 case ATA_WRITE_DMA48: 3847 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3848 break; 3849 } 3850 wordp[1] = htole32(ch->dma->sg_bus); 3851 wordp[2] = 0; 3852 ata_promise_apkt((u_int8_t*)wordp, request); 3853 3854 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus); 3855 return 0; 3856 } 3857 3858 static void 3859 ata_promise_mio_reset(device_t dev) 3860 { 3861 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3862 struct ata_channel *ch = device_get_softc(dev); 3863 struct ata_promise_sx4 *hpktp; 3864 3865 switch (ctlr->chip->cfg2) { 3866 case PRSX4X: 3867 3868 /* softreset channel ATA module */ 3869 hpktp = device_get_ivars(ctlr->dev); 3870 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 3871 ata_udelay(1000); 3872 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 3873 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 3874 ~0x00003f9f) | (ch->unit + 1)); 3875 3876 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 3877 spin_lock_wr(&hpktp->mtx); 3878 ATA_OUTL(ctlr->r_res2, 0xc012c, 3879 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 3880 DELAY(10); 3881 ATA_OUTL(ctlr->r_res2, 0xc012c, 3882 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 3883 hpktp->busy = 0; 3884 spin_unlock_wr(&hpktp->mtx); 3885 ata_generic_reset(dev); 3886 break; 3887 3888 case PRPATA: 3889 case PRCMBO: 3890 case PRSATA: 3891 if ((ctlr->chip->cfg2 == PRSATA) || 3892 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 3893 3894 /* mask plug/unplug intr */ 3895 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 3896 } 3897 3898 /* softreset channels ATA module */ 3899 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 3900 ata_udelay(10000); 3901 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 3902 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 3903 ~0x00003f9f) | (ch->unit + 1)); 3904 3905 if ((ctlr->chip->cfg2 == PRSATA) || 3906 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 3907 3908 if (ata_sata_phy_reset(dev)) 3909 ata_generic_reset(dev); 3910 3911 /* reset and enable plug/unplug intr */ 3912 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 3913 } 3914 else 3915 ata_generic_reset(dev); 3916 break; 3917 3918 case PRCMBO2: 3919 case PRSATA2: 3920 if ((ctlr->chip->cfg2 == PRSATA2) || 3921 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 3922 /* set portmultiplier port */ 3923 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 3924 3925 /* mask plug/unplug intr */ 3926 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 3927 } 3928 3929 /* softreset channels ATA module */ 3930 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 3931 ata_udelay(10000); 3932 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 3933 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 3934 ~0x00003f9f) | (ch->unit + 1)); 3935 3936 if ((ctlr->chip->cfg2 == PRSATA2) || 3937 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 3938 3939 /* set PHY mode to "improved" */ 3940 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 3941 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 3942 ~0x00000003) | 0x00000001); 3943 3944 if (ata_sata_phy_reset(dev)) 3945 ata_generic_reset(dev); 3946 3947 /* reset and enable plug/unplug intr */ 3948 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 3949 3950 /* set portmultiplier port */ 3951 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 3952 } 3953 else 3954 ata_generic_reset(dev); 3955 break; 3956 3957 } 3958 } 3959 3960 static void 3961 ata_promise_mio_dmainit(device_t dev) 3962 { 3963 /* note start and stop are not used here */ 3964 ata_dmainit(dev); 3965 } 3966 3967 static void 3968 ata_promise_mio_setmode(device_t dev, int mode) 3969 { 3970 device_t gparent = GRANDPARENT(dev); 3971 struct ata_pci_controller *ctlr = device_get_softc(gparent); 3972 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3973 3974 if ( (ctlr->chip->cfg2 == PRSATA) || 3975 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) || 3976 (ctlr->chip->cfg2 == PRSATA2) || 3977 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) 3978 ata_sata_setmode(dev, mode); 3979 else 3980 ata_promise_setmode(dev, mode); 3981 } 3982 3983 static void 3984 ata_promise_sx4_intr(void *data) 3985 { 3986 struct ata_pci_controller *ctlr = data; 3987 struct ata_channel *ch; 3988 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 3989 int unit; 3990 3991 for (unit = 0; unit < ctlr->channels; unit++) { 3992 if (vector & (1 << (unit + 1))) 3993 if ((ch = ctlr->interrupt[unit].argument)) 3994 ctlr->interrupt[unit].function(ch); 3995 if (vector & (1 << (unit + 5))) 3996 if ((ch = ctlr->interrupt[unit].argument)) 3997 ata_promise_queue_hpkt(ctlr, 3998 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 3999 ATA_PDC_HPKT_OFFSET)); 4000 if (vector & (1 << (unit + 9))) { 4001 ata_promise_next_hpkt(ctlr); 4002 if ((ch = ctlr->interrupt[unit].argument)) 4003 ctlr->interrupt[unit].function(ch); 4004 } 4005 if (vector & (1 << (unit + 13))) { 4006 ata_promise_next_hpkt(ctlr); 4007 if ((ch = ctlr->interrupt[unit].argument)) 4008 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4009 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 4010 ATA_PDC_APKT_OFFSET)); 4011 } 4012 } 4013 } 4014 4015 static int 4016 ata_promise_sx4_command(struct ata_request *request) 4017 { 4018 device_t gparent = GRANDPARENT(request->dev); 4019 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4020 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4021 struct ata_dma_prdentry *prd = ch->dma->sg; 4022 caddr_t window = rman_get_virtual(ctlr->r_res1); 4023 u_int32_t *wordp; 4024 int i, idx, length = 0; 4025 4026 /* XXX SOS add ATAPI commands support later */ 4027 switch (request->u.ata.command) { 4028 4029 default: 4030 return -1; 4031 4032 case ATA_ATA_IDENTIFY: 4033 case ATA_READ: 4034 case ATA_READ48: 4035 case ATA_READ_MUL: 4036 case ATA_READ_MUL48: 4037 case ATA_WRITE: 4038 case ATA_WRITE48: 4039 case ATA_WRITE_MUL: 4040 case ATA_WRITE_MUL48: 4041 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4042 return ata_generic_command(request); 4043 4044 case ATA_SETFEATURES: 4045 case ATA_FLUSHCACHE: 4046 case ATA_FLUSHCACHE48: 4047 case ATA_SLEEP: 4048 case ATA_SET_MULTI: 4049 wordp = (u_int32_t *) 4050 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4051 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 4052 wordp[1] = 0; 4053 wordp[2] = 0; 4054 ata_promise_apkt((u_int8_t *)wordp, request); 4055 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4056 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4057 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4058 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 4059 return 0; 4060 4061 case ATA_READ_DMA: 4062 case ATA_READ_DMA48: 4063 case ATA_WRITE_DMA: 4064 case ATA_WRITE_DMA48: 4065 wordp = (u_int32_t *) 4066 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 4067 i = idx = 0; 4068 do { 4069 wordp[idx++] = prd[i].addr; 4070 wordp[idx++] = prd[i].count; 4071 length += (prd[i].count & ~ATA_DMA_EOT); 4072 } while (!(prd[i++].count & ATA_DMA_EOT)); 4073 4074 wordp = (u_int32_t *) 4075 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 4076 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4077 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4078 4079 wordp = (u_int32_t *) 4080 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 4081 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4082 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4083 4084 wordp = (u_int32_t *) 4085 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 4086 if (request->flags & ATA_R_READ) 4087 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 4088 if (request->flags & ATA_R_WRITE) 4089 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 4090 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 4091 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 4092 wordp[3] = 0; 4093 4094 wordp = (u_int32_t *) 4095 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4096 if (request->flags & ATA_R_READ) 4097 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 4098 if (request->flags & ATA_R_WRITE) 4099 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 4100 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 4101 wordp[2] = 0; 4102 ata_promise_apkt((u_int8_t *)wordp, request); 4103 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4104 4105 if (request->flags & ATA_R_READ) { 4106 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 4107 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 4108 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4109 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 4110 } 4111 if (request->flags & ATA_R_WRITE) { 4112 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 4113 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 4114 ata_promise_queue_hpkt(ctlr, 4115 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 4116 } 4117 return 0; 4118 } 4119 } 4120 4121 static int 4122 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 4123 { 4124 struct ata_device *atadev = device_get_softc(request->dev); 4125 int i = 12; 4126 4127 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 4128 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit; 4129 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 4130 bytep[i++] = ATA_A_4BIT; 4131 4132 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 4133 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4134 bytep[i++] = request->u.ata.feature >> 8; 4135 bytep[i++] = request->u.ata.feature; 4136 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 4137 bytep[i++] = request->u.ata.count >> 8; 4138 bytep[i++] = request->u.ata.count; 4139 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4140 bytep[i++] = request->u.ata.lba >> 24; 4141 bytep[i++] = request->u.ata.lba; 4142 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4143 bytep[i++] = request->u.ata.lba >> 32; 4144 bytep[i++] = request->u.ata.lba >> 8; 4145 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4146 bytep[i++] = request->u.ata.lba >> 40; 4147 bytep[i++] = request->u.ata.lba >> 16; 4148 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4149 bytep[i++] = ATA_D_LBA | atadev->unit; 4150 } 4151 else { 4152 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4153 bytep[i++] = request->u.ata.feature; 4154 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 4155 bytep[i++] = request->u.ata.count; 4156 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4157 bytep[i++] = request->u.ata.lba; 4158 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4159 bytep[i++] = request->u.ata.lba >> 8; 4160 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4161 bytep[i++] = request->u.ata.lba >> 16; 4162 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4163 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) | 4164 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf); 4165 } 4166 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 4167 bytep[i++] = request->u.ata.command; 4168 return i; 4169 } 4170 4171 static void 4172 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 4173 { 4174 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4175 4176 spin_lock_wr(&hpktp->mtx); 4177 if (hpktp->busy) { 4178 struct host_packet *hp = 4179 kmalloc(sizeof(struct host_packet), M_TEMP, M_INTWAIT | M_ZERO); 4180 hp->addr = hpkt; 4181 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 4182 } 4183 else { 4184 hpktp->busy = 1; 4185 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 4186 } 4187 spin_unlock_wr(&hpktp->mtx); 4188 } 4189 4190 static void 4191 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 4192 { 4193 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4194 struct host_packet *hp; 4195 4196 spin_lock_wr(&hpktp->mtx); 4197 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 4198 TAILQ_REMOVE(&hpktp->queue, hp, chain); 4199 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 4200 kfree(hp, M_TEMP); 4201 } 4202 else 4203 hpktp->busy = 0; 4204 spin_unlock_wr(&hpktp->mtx); 4205 } 4206 4207 4208 /* 4209 * ServerWorks chipset support functions 4210 */ 4211 int 4212 ata_serverworks_ident(device_t dev) 4213 { 4214 struct ata_pci_controller *ctlr = device_get_softc(dev); 4215 struct ata_chip_id *idx; 4216 static struct ata_chip_id ids[] = 4217 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" }, 4218 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" }, 4219 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" }, 4220 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" }, 4221 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" }, 4222 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" }, 4223 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" }, 4224 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" }, 4225 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" }, 4226 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" }, 4227 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" }, 4228 { 0, 0, 0, 0, 0, 0}}; 4229 char buffer[64]; 4230 4231 if (!(idx = ata_match_chip(dev, ids))) 4232 return ENXIO; 4233 4234 ksprintf(buffer, "ServerWorks %s %s controller", 4235 idx->text, ata_mode2str(idx->max_dma)); 4236 device_set_desc_copy(dev, buffer); 4237 ctlr->chip = idx; 4238 ctlr->chipinit = ata_serverworks_chipinit; 4239 return 0; 4240 } 4241 4242 static int 4243 ata_serverworks_chipinit(device_t dev) 4244 { 4245 struct ata_pci_controller *ctlr = device_get_softc(dev); 4246 4247 if (ata_setup_interrupt(dev)) 4248 return ENXIO; 4249 4250 if (ctlr->chip->cfg1 == SWKSMIO) { 4251 ctlr->r_type2 = SYS_RES_MEMORY; 4252 ctlr->r_rid2 = PCIR_BAR(5); 4253 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4254 &ctlr->r_rid2, RF_ACTIVE))) 4255 return ENXIO; 4256 4257 ctlr->channels = ctlr->chip->cfg2; 4258 ctlr->allocate = ata_serverworks_allocate; 4259 ctlr->setmode = ata_sata_setmode; 4260 return 0; 4261 } 4262 else if (ctlr->chip->cfg1 == SWKS33) { 4263 device_t *children; 4264 int nchildren, i; 4265 4266 /* locate the ISA part in the southbridge and enable UDMA33 */ 4267 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 4268 for (i = 0; i < nchildren; i++) { 4269 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 4270 pci_write_config(children[i], 0x64, 4271 (pci_read_config(children[i], 0x64, 4) & 4272 ~0x00002000) | 0x00004000, 4); 4273 break; 4274 } 4275 } 4276 kfree(children, M_TEMP); 4277 } 4278 } 4279 else { 4280 pci_write_config(dev, 0x5a, 4281 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 4282 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1); 4283 } 4284 ctlr->setmode = ata_serverworks_setmode; 4285 return 0; 4286 } 4287 4288 static int 4289 ata_serverworks_allocate(device_t dev) 4290 { 4291 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4292 struct ata_channel *ch = device_get_softc(dev); 4293 int ch_offset; 4294 int i; 4295 4296 ch_offset = ch->unit * 0x100; 4297 4298 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 4299 ch->r_io[i].res = ctlr->r_res2; 4300 4301 /* setup ATA registers */ 4302 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 4303 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 4304 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 4305 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 4306 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 4307 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 4308 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 4309 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 4310 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 4311 ata_default_registers(dev); 4312 4313 /* setup DMA registers */ 4314 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 4315 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 4316 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 4317 4318 /* setup SATA registers */ 4319 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 4320 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 4321 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 4322 4323 ch->flags |= ATA_NO_SLAVE; 4324 ata_pci_hw(dev); 4325 return 0; 4326 } 4327 4328 static void 4329 ata_serverworks_setmode(device_t dev, int mode) 4330 { 4331 device_t gparent = GRANDPARENT(dev); 4332 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4333 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4334 struct ata_device *atadev = device_get_softc(dev); 4335 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4336 int offset = (devno ^ 0x01) << 3; 4337 int error; 4338 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 4339 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 4340 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 4341 4342 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4343 4344 mode = ata_check_80pin(dev, mode); 4345 4346 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4347 4348 if (bootverbose) 4349 device_printf(dev, "%ssetting %s on %s chip\n", 4350 (error) ? "FAILURE " : "", 4351 ata_mode2str(mode), ctlr->chip->text); 4352 if (!error) { 4353 if (mode >= ATA_UDMA0) { 4354 pci_write_config(gparent, 0x56, 4355 (pci_read_config(gparent, 0x56, 2) & 4356 ~(0xf << (devno << 2))) | 4357 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 4358 pci_write_config(gparent, 0x54, 4359 pci_read_config(gparent, 0x54, 1) | 4360 (0x01 << devno), 1); 4361 pci_write_config(gparent, 0x44, 4362 (pci_read_config(gparent, 0x44, 4) & 4363 ~(0xff << offset)) | 4364 (dmatimings[2] << offset), 4); 4365 } 4366 else if (mode >= ATA_WDMA0) { 4367 pci_write_config(gparent, 0x54, 4368 pci_read_config(gparent, 0x54, 1) & 4369 ~(0x01 << devno), 1); 4370 pci_write_config(gparent, 0x44, 4371 (pci_read_config(gparent, 0x44, 4) & 4372 ~(0xff << offset)) | 4373 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 4374 } 4375 else 4376 pci_write_config(gparent, 0x54, 4377 pci_read_config(gparent, 0x54, 1) & 4378 ~(0x01 << devno), 1); 4379 4380 pci_write_config(gparent, 0x40, 4381 (pci_read_config(gparent, 0x40, 4) & 4382 ~(0xff << offset)) | 4383 (piotimings[ata_mode2idx(mode)] << offset), 4); 4384 atadev->mode = mode; 4385 } 4386 } 4387 4388 4389 /* 4390 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 4391 */ 4392 int 4393 ata_sii_ident(device_t dev) 4394 { 4395 struct ata_pci_controller *ctlr = device_get_softc(dev); 4396 struct ata_chip_id *idx; 4397 static struct ata_chip_id ids[] = 4398 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" }, 4399 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" }, 4400 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4401 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4402 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" }, 4403 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4404 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4405 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" }, 4406 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" }, 4407 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" }, 4408 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" }, 4409 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" }, 4410 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" }, 4411 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" }, 4412 { 0, 0, 0, 0, 0, 0}}; 4413 char buffer[64]; 4414 4415 if (!(idx = ata_match_chip(dev, ids))) 4416 return ENXIO; 4417 4418 ksprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); 4419 device_set_desc_copy(dev, buffer); 4420 ctlr->chip = idx; 4421 ctlr->chipinit = ata_sii_chipinit; 4422 return 0; 4423 } 4424 4425 static int 4426 ata_sii_chipinit(device_t dev) 4427 { 4428 struct ata_pci_controller *ctlr = device_get_softc(dev); 4429 4430 if (ata_setup_interrupt(dev)) 4431 return ENXIO; 4432 4433 switch (ctlr->chip->cfg1) { 4434 case SIIPRBIO: 4435 ctlr->r_type1 = SYS_RES_MEMORY; 4436 ctlr->r_rid1 = PCIR_BAR(0); 4437 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 4438 &ctlr->r_rid1, RF_ACTIVE))) 4439 return ENXIO; 4440 4441 ctlr->r_rid2 = PCIR_BAR(2); 4442 ctlr->r_type2 = SYS_RES_MEMORY; 4443 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4444 &ctlr->r_rid2, RF_ACTIVE))){ 4445 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 4446 return ENXIO; 4447 } 4448 ctlr->allocate = ata_siiprb_allocate; 4449 ctlr->reset = ata_siiprb_reset; 4450 ctlr->dmainit = ata_siiprb_dmainit; 4451 ctlr->setmode = ata_sata_setmode; 4452 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2; 4453 4454 /* reset controller */ 4455 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 4456 DELAY(10000); 4457 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 4458 4459 /* enable PCI interrupt */ 4460 pci_write_config(dev, PCIR_COMMAND, 4461 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 4462 break; 4463 4464 case SIIMEMIO: 4465 ctlr->r_type2 = SYS_RES_MEMORY; 4466 ctlr->r_rid2 = PCIR_BAR(5); 4467 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4468 &ctlr->r_rid2, RF_ACTIVE))) 4469 return ENXIO; 4470 4471 if (ctlr->chip->cfg2 & SIISETCLK) { 4472 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4473 pci_write_config(dev, 0x8a, 4474 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 4475 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4476 device_printf(dev, "%s could not set ATA133 clock\n", 4477 ctlr->chip->text); 4478 } 4479 4480 /* if we have 4 channels enable the second set */ 4481 if (ctlr->chip->cfg2 & SII4CH) { 4482 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 4483 ctlr->channels = 4; 4484 } 4485 4486 /* dont block interrupts from any channel */ 4487 pci_write_config(dev, 0x48, 4488 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 4489 4490 /* enable PCI interrupt as BIOS might not */ 4491 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 4492 4493 ctlr->allocate = ata_sii_allocate; 4494 if (ctlr->chip->max_dma >= ATA_SA150) { 4495 ctlr->reset = ata_sii_reset; 4496 ctlr->setmode = ata_sata_setmode; 4497 } 4498 else 4499 ctlr->setmode = ata_sii_setmode; 4500 break; 4501 4502 default: 4503 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 4504 device_printf(dev, "HW has secondary channel disabled\n"); 4505 ctlr->channels = 1; 4506 } 4507 4508 /* enable interrupt as BIOS might not */ 4509 pci_write_config(dev, 0x71, 0x01, 1); 4510 4511 ctlr->allocate = ata_cmd_allocate; 4512 ctlr->setmode = ata_cmd_setmode; 4513 break; 4514 } 4515 return 0; 4516 } 4517 4518 static int 4519 ata_cmd_allocate(device_t dev) 4520 { 4521 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4522 struct ata_channel *ch = device_get_softc(dev); 4523 4524 /* setup the usual register normal pci style */ 4525 if (ata_pci_allocate(dev)) 4526 return ENXIO; 4527 4528 if (ctlr->chip->cfg2 & SIIINTR) 4529 ch->hw.status = ata_cmd_status; 4530 4531 return 0; 4532 } 4533 4534 static int 4535 ata_cmd_status(device_t dev) 4536 { 4537 struct ata_channel *ch = device_get_softc(dev); 4538 u_int8_t reg71; 4539 4540 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) & 4541 (ch->unit ? 0x08 : 0x04))) { 4542 pci_write_config(device_get_parent(ch->dev), 0x71, 4543 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 4544 return ata_pci_status(dev); 4545 } 4546 return 0; 4547 } 4548 4549 static void 4550 ata_cmd_setmode(device_t dev, int mode) 4551 { 4552 device_t gparent = GRANDPARENT(dev); 4553 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4554 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4555 struct ata_device *atadev = device_get_softc(dev); 4556 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4557 int error; 4558 4559 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4560 4561 mode = ata_check_80pin(dev, mode); 4562 4563 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4564 4565 if (bootverbose) 4566 device_printf(dev, "%ssetting %s on %s chip\n", 4567 (error) ? "FAILURE " : "", 4568 ata_mode2str(mode), ctlr->chip->text); 4569 if (!error) { 4570 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 4571 int ureg = ch->unit ? 0x7b : 0x73; 4572 4573 if (mode >= ATA_UDMA0) { 4574 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 4575 { 0x11, 0x42 }, { 0x25, 0x8a }, 4576 { 0x15, 0x4a }, { 0x05, 0x0a } }; 4577 4578 u_int8_t umode = pci_read_config(gparent, ureg, 1); 4579 4580 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca); 4581 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)]; 4582 pci_write_config(gparent, ureg, umode, 1); 4583 } 4584 else if (mode >= ATA_WDMA0) { 4585 int dmatimings[] = { 0x87, 0x32, 0x3f }; 4586 4587 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1); 4588 pci_write_config(gparent, ureg, 4589 pci_read_config(gparent, ureg, 1) & 4590 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4591 } 4592 else { 4593 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f }; 4594 pci_write_config(gparent, treg, 4595 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1); 4596 pci_write_config(gparent, ureg, 4597 pci_read_config(gparent, ureg, 1) & 4598 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4599 } 4600 atadev->mode = mode; 4601 } 4602 } 4603 4604 static int 4605 ata_sii_allocate(device_t dev) 4606 { 4607 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4608 struct ata_channel *ch = device_get_softc(dev); 4609 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 4610 int i; 4611 4612 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 4613 ch->r_io[i].res = ctlr->r_res2; 4614 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 4615 } 4616 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 4617 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 4618 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 4619 ata_default_registers(dev); 4620 4621 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 4622 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 4623 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 4624 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 4625 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 4626 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 4627 4628 if (ctlr->chip->max_dma >= ATA_SA150) { 4629 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4630 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 4631 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4632 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 4633 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4634 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 4635 ch->flags |= ATA_NO_SLAVE; 4636 4637 /* enable PHY state change interrupt */ 4638 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 4639 } 4640 4641 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) { 4642 /* work around errata in early chips */ 4643 ch->dma->boundary = 16 * DEV_BSIZE; 4644 ch->dma->segsize = 15 * DEV_BSIZE; 4645 } 4646 4647 ata_pci_hw(dev); 4648 ch->hw.status = ata_sii_status; 4649 return 0; 4650 } 4651 4652 static int 4653 ata_sii_status(device_t dev) 4654 { 4655 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4656 struct ata_channel *ch = device_get_softc(dev); 4657 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 4658 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 4659 4660 /* do we have any PHY events ? */ 4661 if (ctlr->chip->max_dma >= ATA_SA150 && 4662 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 4663 ata_sata_phy_check_events(dev); 4664 4665 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 4666 return ata_pci_status(dev); 4667 else 4668 return 0; 4669 } 4670 4671 static void 4672 ata_sii_reset(device_t dev) 4673 { 4674 if (ata_sata_phy_reset(dev)) 4675 ata_generic_reset(dev); 4676 } 4677 4678 static void 4679 ata_sii_setmode(device_t dev, int mode) 4680 { 4681 device_t gparent = GRANDPARENT(dev); 4682 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4683 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4684 struct ata_device *atadev = device_get_softc(dev); 4685 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1); 4686 int mreg = ch->unit ? 0x84 : 0x80; 4687 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2); 4688 int mval = pci_read_config(gparent, mreg, 1) & ~mask; 4689 int error; 4690 4691 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4692 4693 if (ctlr->chip->cfg2 & SIISETCLK) { 4694 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) & 4695 (ch->unit ? 0x02 : 0x01))) { 4696 ata_print_cable(dev, "controller"); 4697 mode = ATA_UDMA2; 4698 } 4699 } 4700 else 4701 mode = ata_check_80pin(dev, mode); 4702 4703 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4704 4705 if (bootverbose) 4706 device_printf(dev, "%ssetting %s on %s chip\n", 4707 (error) ? "FAILURE " : "", 4708 ata_mode2str(mode), ctlr->chip->text); 4709 if (error) 4710 return; 4711 4712 if (mode >= ATA_UDMA0) { 4713 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 4714 u_int8_t ureg = 0xac + rego; 4715 4716 pci_write_config(gparent, mreg, 4717 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1); 4718 pci_write_config(gparent, ureg, 4719 (pci_read_config(gparent, ureg, 1) & ~0x3f) | 4720 udmatimings[mode & ATA_MODE_MASK], 1); 4721 4722 } 4723 else if (mode >= ATA_WDMA0) { 4724 u_int8_t dreg = 0xa8 + rego; 4725 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 4726 4727 pci_write_config(gparent, mreg, 4728 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1); 4729 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 4730 4731 } 4732 else { 4733 u_int8_t preg = 0xa4 + rego; 4734 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 4735 4736 pci_write_config(gparent, mreg, 4737 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1); 4738 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2); 4739 } 4740 atadev->mode = mode; 4741 } 4742 4743 struct ata_siiprb_dma_prdentry { 4744 u_int64_t addr; 4745 u_int32_t count; 4746 u_int32_t control; 4747 } __packed; 4748 4749 struct ata_siiprb_ata_command { 4750 u_int32_t reserved0; 4751 struct ata_siiprb_dma_prdentry prd[126]; 4752 } __packed; 4753 4754 struct ata_siiprb_atapi_command { 4755 u_int8_t cdb[16]; 4756 struct ata_siiprb_dma_prdentry prd[125]; 4757 } __packed; 4758 4759 struct ata_siiprb_command { 4760 u_int16_t control; 4761 u_int16_t protocol_override; 4762 u_int32_t transfer_count; 4763 u_int8_t fis[20]; 4764 union { 4765 struct ata_siiprb_ata_command ata; 4766 struct ata_siiprb_atapi_command atapi; 4767 } u; 4768 } __packed; 4769 4770 static int 4771 ata_siiprb_allocate(device_t dev) 4772 { 4773 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4774 struct ata_channel *ch = device_get_softc(dev); 4775 int offset = ch->unit * 0x2000; 4776 4777 /* set the SATA resources */ 4778 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4779 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 4780 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4781 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 4782 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4783 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 4784 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 4785 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 4786 4787 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 4788 ch->hw.end_transaction = ata_siiprb_end_transaction; 4789 ch->hw.status = ata_siiprb_status; 4790 ch->hw.command = NULL; /* not used here */ 4791 return 0; 4792 } 4793 4794 static int 4795 ata_siiprb_status(device_t dev) 4796 { 4797 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4798 struct ata_channel *ch = device_get_softc(dev); 4799 int offset = ch->unit * 0x2000; 4800 4801 if ((ATA_INL(ctlr->r_res1, 0x0044) & (1 << ch->unit))) { 4802 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 4803 4804 /* do we have any PHY events ? */ 4805 ata_sata_phy_check_events(dev); 4806 4807 /* clear interrupt(s) */ 4808 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 4809 4810 /* do we have any device action ? */ 4811 return (istatus & 0x00000001); 4812 } 4813 return 0; 4814 } 4815 4816 static int 4817 ata_siiprb_begin_transaction(struct ata_request *request) 4818 { 4819 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 4820 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4821 struct ata_siiprb_command *prb; 4822 int offset = ch->unit * 0x2000; 4823 u_int64_t prb_bus; 4824 int tag = 0, dummy; 4825 4826 /* check for 48 bit access and convert if needed */ 4827 ata_modify_if_48bit(request); 4828 4829 /* get a piece of the workspace for this request */ 4830 prb = (struct ata_siiprb_command *) 4831 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 4832 4833 /* set basic prd options ata/atapi etc etc */ 4834 bzero(prb, sizeof(struct ata_siiprb_command)); 4835 4836 /* setup the FIS for this request */ 4837 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 4838 device_printf(request->dev, "setting up SATA FIS failed\n"); 4839 request->result = EIO; 4840 return ATA_OP_FINISHED; 4841 } 4842 4843 /* if request moves data setup and load SG list */ 4844 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 4845 struct ata_siiprb_dma_prdentry *prd; 4846 4847 if (request->flags & ATA_R_ATAPI) 4848 prd = &prb->u.atapi.prd[0]; 4849 else 4850 prd = &prb->u.ata.prd[0]; 4851 if (ch->dma->load(ch->dev, request->data, request->bytecount, 4852 request->flags & ATA_R_READ, prd, &dummy)) { 4853 device_printf(request->dev, "setting up DMA failed\n"); 4854 request->result = EIO; 4855 return ATA_OP_FINISHED; 4856 } 4857 } 4858 4859 /* activate the prb */ 4860 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 4861 ATA_OUTL(ctlr->r_res2, 4862 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 4863 ATA_OUTL(ctlr->r_res2, 4864 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 4865 4866 /* start the timeout */ 4867 callout_reset(&request->callout, request->timeout * hz, 4868 (timeout_t*)ata_timeout, request); 4869 return ATA_OP_CONTINUES; 4870 } 4871 4872 static int 4873 ata_siiprb_end_transaction(struct ata_request *request) 4874 { 4875 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 4876 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4877 struct ata_siiprb_command *prb; 4878 int offset = ch->unit * 0x2000; 4879 int error, tag = 0; 4880 4881 /* kill the timeout */ 4882 callout_stop(&request->callout); 4883 4884 prb = (struct ata_siiprb_command *) 4885 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 4886 4887 /* if error status get details */ 4888 request->status = prb->fis[2]; 4889 if (request->status & ATA_S_ERROR) 4890 request->error = prb->fis[3]; 4891 4892 /* update progress */ 4893 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 4894 if (request->flags & ATA_R_READ) 4895 request->donecount = prb->transfer_count; 4896 else 4897 request->donecount = request->bytecount; 4898 } 4899 4900 /* any controller errors flagged ? */ 4901 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 4902 kprintf("ata_siiprb_end_transaction %s error=%08x\n", 4903 ata_cmd2str(request), error); 4904 } 4905 4906 /* release SG list etc */ 4907 ch->dma->unload(ch->dev); 4908 4909 return ATA_OP_FINISHED; 4910 } 4911 4912 static void 4913 ata_siiprb_reset(device_t dev) 4914 { 4915 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4916 struct ata_channel *ch = device_get_softc(dev); 4917 int offset = ch->unit * 0x2000; 4918 struct ata_siiprb_command *prb; 4919 u_int64_t prb_bus; 4920 u_int32_t status, signature; 4921 int timeout, tag = 0; 4922 4923 /* reset channel HW */ 4924 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 4925 DELAY(1000); 4926 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 4927 DELAY(10000); 4928 4929 /* poll for channel ready */ 4930 for (timeout = 0; timeout < 1000; timeout++) { 4931 if ((status = ATA_INL(ctlr->r_res2, 0x1000 + offset)) & 0x00040000) 4932 break; 4933 DELAY(1000); 4934 } 4935 if (timeout >= 1000) { 4936 device_printf(ch->dev, "channel HW reset timeout reset failure\n"); 4937 ch->devices = 0; 4938 goto finish; 4939 } 4940 if (bootverbose) 4941 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout * 1); 4942 4943 /* reset phy */ 4944 if (!ata_sata_phy_reset(dev)) { 4945 if (bootverbose) 4946 device_printf(ch->dev, "phy reset found no device\n"); 4947 ch->devices = 0; 4948 goto finish; 4949 } 4950 4951 /* get a piece of the workspace for a soft reset request */ 4952 prb = (struct ata_siiprb_command *) 4953 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 4954 bzero(prb, sizeof(struct ata_siiprb_command)); 4955 prb->control = htole16(0x0080); 4956 4957 /* activate the soft reset prb */ 4958 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 4959 ATA_OUTL(ctlr->r_res2, 4960 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 4961 ATA_OUTL(ctlr->r_res2, 4962 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 4963 4964 /* poll for channel ready */ 4965 for (timeout = 0; timeout < 1000; timeout++) { 4966 DELAY(1000); 4967 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 4968 break; 4969 } 4970 if (timeout >= 1000) { 4971 device_printf(ch->dev, "reset timeout - no device found\n"); 4972 ch->devices = 0; 4973 goto finish; 4974 } 4975 if (bootverbose) 4976 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n", 4977 timeout, status); 4978 4979 /* find out whats there */ 4980 prb = (struct ata_siiprb_command *) 4981 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 4982 signature = 4983 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 4984 if (bootverbose) 4985 device_printf(ch->dev, "signature=%08x\n", signature); 4986 switch (signature) { 4987 case 0xeb140101: 4988 ch->devices = ATA_ATAPI_MASTER; 4989 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n"); 4990 ch->devices = 0; 4991 break; 4992 case 0x96690101: 4993 ch->devices = ATA_PORTMULTIPLIER; 4994 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 4995 ch->devices = 0; 4996 break; 4997 case 0x00000101: 4998 ch->devices = ATA_ATA_MASTER; 4999 break; 5000 default: 5001 ch->devices = 0; 5002 } 5003 5004 finish: 5005 /* clear interrupt(s) */ 5006 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 5007 5008 /* require explicit interrupt ack */ 5009 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 5010 5011 /* 64bit mode */ 5012 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 5013 5014 /* enable interrupts wanted */ 5015 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 5016 } 5017 5018 static void 5019 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 5020 { 5021 struct ata_dmasetprd_args *args = xsc; 5022 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 5023 int i; 5024 5025 if ((args->error = error)) 5026 return; 5027 5028 for (i = 0; i < nsegs; i++) { 5029 prd[i].addr = htole64(segs[i].ds_addr); 5030 prd[i].count = htole32(segs[i].ds_len); 5031 } 5032 prd[i - 1].control = htole32(ATA_DMA_EOT); 5033 } 5034 5035 static void 5036 ata_siiprb_dmainit(device_t dev) 5037 { 5038 struct ata_channel *ch = device_get_softc(dev); 5039 5040 ata_dmainit(dev); 5041 if (ch->dma) { 5042 /* note start and stop are not used here */ 5043 ch->dma->setprd = ata_siiprb_dmasetprd; 5044 ch->dma->max_address = BUS_SPACE_MAXADDR; 5045 } 5046 } 5047 5048 5049 /* 5050 * Silicon Integrated Systems Corp. (SiS) chipset support functions 5051 */ 5052 int 5053 ata_sis_ident(device_t dev) 5054 { 5055 struct ata_pci_controller *ctlr = device_get_softc(dev); 5056 struct ata_chip_id *idx; 5057 static struct ata_chip_id ids[] = 5058 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */ 5059 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */ 5060 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */ 5061 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */ 5062 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */ 5063 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */ 5064 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */ 5065 5066 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */ 5067 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */ 5068 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */ 5069 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */ 5070 5071 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */ 5072 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */ 5073 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */ 5074 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */ 5075 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */ 5076 5077 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" }, 5078 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" }, 5079 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" }, 5080 5081 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" }, 5082 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" }, 5083 { 0, 0, 0, 0, 0, 0 }}; 5084 char buffer[64]; 5085 int found = 0; 5086 5087 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev)))) 5088 return ENXIO; 5089 5090 if (idx->cfg2 && !found) { 5091 u_int8_t reg57 = pci_read_config(dev, 0x57, 1); 5092 5093 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1); 5094 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) { 5095 found = 1; 5096 idx->cfg1 = SIS133NEW; 5097 idx->max_dma = ATA_UDMA6; 5098 ksprintf(buffer, "SiS 962/963 %s controller", 5099 ata_mode2str(idx->max_dma)); 5100 } 5101 pci_write_config(dev, 0x57, reg57, 1); 5102 } 5103 if (idx->cfg2 && !found) { 5104 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1); 5105 5106 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1); 5107 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) { 5108 struct ata_chip_id id[] = 5109 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }}; 5110 5111 found = 1; 5112 if (ata_find_chip(dev, id, pci_get_slot(dev))) { 5113 idx->cfg1 = SIS133OLD; 5114 idx->max_dma = ATA_UDMA6; 5115 } 5116 else { 5117 idx->cfg1 = SIS100NEW; 5118 idx->max_dma = ATA_UDMA5; 5119 } 5120 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma)); 5121 } 5122 pci_write_config(dev, 0x4a, reg4a, 1); 5123 } 5124 if (!found) 5125 ksprintf(buffer,"SiS %s %s controller", 5126 idx->text, ata_mode2str(idx->max_dma)); 5127 5128 device_set_desc_copy(dev, buffer); 5129 ctlr->chip = idx; 5130 ctlr->chipinit = ata_sis_chipinit; 5131 return 0; 5132 } 5133 5134 static int 5135 ata_sis_chipinit(device_t dev) 5136 { 5137 struct ata_pci_controller *ctlr = device_get_softc(dev); 5138 5139 if (ata_setup_interrupt(dev)) 5140 return ENXIO; 5141 5142 switch (ctlr->chip->cfg1) { 5143 case SIS33: 5144 break; 5145 case SIS66: 5146 case SIS100OLD: 5147 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1); 5148 break; 5149 case SIS100NEW: 5150 case SIS133OLD: 5151 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1); 5152 break; 5153 case SIS133NEW: 5154 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2); 5155 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2); 5156 break; 5157 case SISSATA: 5158 ctlr->r_type2 = SYS_RES_IOPORT; 5159 ctlr->r_rid2 = PCIR_BAR(5); 5160 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5161 &ctlr->r_rid2, RF_ACTIVE))) { 5162 ctlr->allocate = ata_sis_allocate; 5163 ctlr->reset = ata_sis_reset; 5164 5165 /* enable PCI interrupt */ 5166 pci_write_config(dev, PCIR_COMMAND, 5167 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5168 } 5169 ctlr->setmode = ata_sata_setmode; 5170 return 0; 5171 default: 5172 return ENXIO; 5173 } 5174 ctlr->setmode = ata_sis_setmode; 5175 return 0; 5176 } 5177 5178 static int 5179 ata_sis_allocate(device_t dev) 5180 { 5181 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5182 struct ata_channel *ch = device_get_softc(dev); 5183 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6); 5184 5185 /* setup the usual register normal pci style */ 5186 if (ata_pci_allocate(dev)) 5187 return ENXIO; 5188 5189 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5190 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; 5191 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5192 ch->r_io[ATA_SERROR].offset = 0x04 + offset; 5193 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5194 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; 5195 ch->flags |= ATA_NO_SLAVE; 5196 5197 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ 5198 /* XXX SOS unknown how to enable PHY state change interrupt */ 5199 return 0; 5200 } 5201 5202 static void 5203 ata_sis_reset(device_t dev) 5204 { 5205 if (ata_sata_phy_reset(dev)) 5206 ata_generic_reset(dev); 5207 } 5208 5209 static void 5210 ata_sis_setmode(device_t dev, int mode) 5211 { 5212 device_t gparent = GRANDPARENT(dev); 5213 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5214 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5215 struct ata_device *atadev = device_get_softc(dev); 5216 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5217 int error; 5218 5219 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5220 5221 if (ctlr->chip->cfg1 == SIS133NEW) { 5222 if (mode > ATA_UDMA2 && 5223 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) { 5224 ata_print_cable(dev, "controller"); 5225 mode = ATA_UDMA2; 5226 } 5227 } 5228 else { 5229 if (mode > ATA_UDMA2 && 5230 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) { 5231 ata_print_cable(dev, "controller"); 5232 mode = ATA_UDMA2; 5233 } 5234 } 5235 5236 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5237 5238 if (bootverbose) 5239 device_printf(dev, "%ssetting %s on %s chip\n", 5240 (error) ? "FAILURE " : "", 5241 ata_mode2str(mode), ctlr->chip->text); 5242 if (!error) { 5243 switch (ctlr->chip->cfg1) { 5244 case SIS133NEW: { 5245 u_int32_t timings[] = 5246 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 5247 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 5248 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; 5249 u_int32_t reg; 5250 5251 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); 5252 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4); 5253 break; 5254 } 5255 case SIS133OLD: { 5256 u_int16_t timings[] = 5257 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 5258 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; 5259 5260 u_int16_t reg = 0x40 + (devno << 1); 5261 5262 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5263 break; 5264 } 5265 case SIS100NEW: { 5266 u_int16_t timings[] = 5267 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 5268 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; 5269 u_int16_t reg = 0x40 + (devno << 1); 5270 5271 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5272 break; 5273 } 5274 case SIS100OLD: 5275 case SIS66: 5276 case SIS33: { 5277 u_int16_t timings[] = 5278 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 5279 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; 5280 u_int16_t reg = 0x40 + (devno << 1); 5281 5282 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5283 break; 5284 } 5285 } 5286 atadev->mode = mode; 5287 } 5288 } 5289 5290 5291 /* VIA Technologies Inc. chipset support functions */ 5292 int 5293 ata_via_ident(device_t dev) 5294 { 5295 struct ata_pci_controller *ctlr = device_get_softc(dev); 5296 struct ata_chip_id *idx; 5297 static struct ata_chip_id ids[] = 5298 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 5299 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 5300 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 5301 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 5302 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 5303 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 5304 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 5305 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 5306 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 5307 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 5308 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 5309 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 5310 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 5311 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 5312 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 5313 { 0, 0, 0, 0, 0, 0 }}; 5314 static struct ata_chip_id new_ids[] = 5315 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 5316 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 5317 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 5318 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 5319 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" }, 5320 { 0, 0, 0, 0, 0, 0 }}; 5321 char buffer[64]; 5322 5323 if (pci_get_devid(dev) == ATA_VIA82C571) { 5324 if (!(idx = ata_find_chip(dev, ids, -99))) 5325 return ENXIO; 5326 } 5327 else { 5328 if (!(idx = ata_match_chip(dev, new_ids))) 5329 return ENXIO; 5330 } 5331 5332 ksprintf(buffer, "VIA %s %s controller", 5333 idx->text, ata_mode2str(idx->max_dma)); 5334 device_set_desc_copy(dev, buffer); 5335 ctlr->chip = idx; 5336 ctlr->chipinit = ata_via_chipinit; 5337 return 0; 5338 } 5339 5340 static int 5341 ata_via_chipinit(device_t dev) 5342 { 5343 struct ata_pci_controller *ctlr = device_get_softc(dev); 5344 5345 if (ata_setup_interrupt(dev)) 5346 return ENXIO; 5347 5348 if (ctlr->chip->max_dma >= ATA_SA150) { 5349 if (ctlr->chip->cfg2 == VIAAHCI) { 5350 ctlr->r_type2 = SYS_RES_MEMORY; 5351 ctlr->r_rid2 = PCIR_BAR(5); 5352 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5353 &ctlr->r_rid2, 5354 RF_ACTIVE))) { 5355 return ata_ahci_chipinit(dev); 5356 } 5357 } 5358 ctlr->r_type2 = SYS_RES_IOPORT; 5359 ctlr->r_rid2 = PCIR_BAR(5); 5360 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5361 &ctlr->r_rid2, RF_ACTIVE))) { 5362 ctlr->allocate = ata_via_allocate; 5363 ctlr->reset = ata_via_reset; 5364 5365 /* enable PCI interrupt */ 5366 pci_write_config(dev, PCIR_COMMAND, 5367 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5368 } 5369 5370 if (ctlr->chip->cfg2 & VIABAR) { 5371 ctlr->channels = 3; 5372 ctlr->setmode = ata_via_setmode; 5373 } 5374 else 5375 ctlr->setmode = ata_sata_setmode; 5376 return 0; 5377 } 5378 5379 /* prepare for ATA-66 on the 82C686a and 82C596b */ 5380 if (ctlr->chip->cfg2 & VIACLK) 5381 pci_write_config(dev, 0x50, 0x030b030b, 4); 5382 5383 /* the southbridge might need the data corruption fix */ 5384 if (ctlr->chip->cfg2 & VIABUG) 5385 ata_via_southbridge_fixup(dev); 5386 5387 /* set fifo configuration half'n'half */ 5388 pci_write_config(dev, 0x43, 5389 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 5390 5391 /* set status register read retry */ 5392 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 5393 5394 /* set DMA read & end-of-sector fifo flush */ 5395 pci_write_config(dev, 0x46, 5396 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 5397 5398 /* set sector size */ 5399 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 5400 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 5401 5402 ctlr->setmode = ata_via_family_setmode; 5403 return 0; 5404 } 5405 5406 static int 5407 ata_via_allocate(device_t dev) 5408 { 5409 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5410 struct ata_channel *ch = device_get_softc(dev); 5411 5412 /* newer SATA chips has resources in one BAR for each channel */ 5413 if (ctlr->chip->cfg2 & VIABAR) { 5414 struct resource *r_io; 5415 int i, rid; 5416 5417 rid = PCIR_BAR(ch->unit); 5418 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 5419 SYS_RES_IOPORT, 5420 &rid, RF_ACTIVE))) 5421 return ENXIO; 5422 5423 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 5424 ch->r_io[i].res = r_io; 5425 ch->r_io[i].offset = i; 5426 } 5427 ch->r_io[ATA_CONTROL].res = r_io; 5428 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 5429 ch->r_io[ATA_IDX_ADDR].res = r_io; 5430 ata_default_registers(dev); 5431 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 5432 ch->r_io[i].res = ctlr->r_res1; 5433 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 5434 } 5435 ata_pci_hw(dev); 5436 if (ch->unit > 1) 5437 return 0; 5438 } 5439 else { 5440 /* setup the usual register normal pci style */ 5441 if (ata_pci_allocate(dev)) 5442 return ENXIO; 5443 } 5444 5445 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5446 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 5447 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5448 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 5449 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5450 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 5451 ch->flags |= ATA_NO_SLAVE; 5452 5453 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */ 5454 /* XXX SOS unknown how to enable PHY state change interrupt */ 5455 return 0; 5456 } 5457 5458 static void 5459 ata_via_reset(device_t dev) 5460 { 5461 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5462 struct ata_channel *ch = device_get_softc(dev); 5463 5464 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 5465 ata_generic_reset(dev); 5466 else 5467 if (ata_sata_phy_reset(dev)) 5468 ata_generic_reset(dev); 5469 } 5470 5471 static void 5472 ata_via_setmode(device_t dev, int mode) 5473 { 5474 device_t gparent = GRANDPARENT(dev); 5475 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5476 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5477 struct ata_device *atadev = device_get_softc(dev); 5478 int error; 5479 5480 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 5481 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20, 5482 0x65, 0x32, 0x20, 5483 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5484 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 5485 5486 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6)); 5487 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5488 if (bootverbose) 5489 device_printf(dev, "%ssetting %s on %s chip\n", 5490 (error) ? "FAILURE " : "", ata_mode2str(mode), 5491 ctlr->chip->text); 5492 if (!error) { 5493 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1); 5494 if (mode >= ATA_UDMA0) 5495 pci_write_config(gparent, 0xb3, 5496 dma_timings[mode & ATA_MODE_MASK], 1); 5497 atadev->mode = mode; 5498 } 5499 } 5500 else 5501 ata_sata_setmode(dev, mode); 5502 } 5503 5504 static void 5505 ata_via_southbridge_fixup(device_t dev) 5506 { 5507 device_t *children; 5508 int nchildren, i; 5509 5510 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5511 return; 5512 5513 for (i = 0; i < nchildren; i++) { 5514 if (pci_get_devid(children[i]) == ATA_VIA8363 || 5515 pci_get_devid(children[i]) == ATA_VIA8371 || 5516 pci_get_devid(children[i]) == ATA_VIA8662 || 5517 pci_get_devid(children[i]) == ATA_VIA8361) { 5518 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 5519 5520 if ((reg76 & 0xf0) != 0xd0) { 5521 device_printf(dev, 5522 "Correcting VIA config for southbridge data corruption bug\n"); 5523 pci_write_config(children[i], 0x75, 0x80, 1); 5524 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 5525 } 5526 break; 5527 } 5528 } 5529 kfree(children, M_TEMP); 5530 } 5531 5532 5533 /* common code for VIA, AMD & nVidia */ 5534 static void 5535 ata_via_family_setmode(device_t dev, int mode) 5536 { 5537 device_t gparent = GRANDPARENT(dev); 5538 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5539 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5540 struct ata_device *atadev = device_get_softc(dev); 5541 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20, 5542 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5543 int modes[][7] = { 5544 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 5545 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 5546 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 5547 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */ 5548 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */ 5549 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5550 int reg = 0x53 - devno; 5551 int error; 5552 5553 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5554 5555 if (ctlr->chip->cfg2 & AMDCABLE) { 5556 if (mode > ATA_UDMA2 && 5557 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) { 5558 ata_print_cable(dev, "controller"); 5559 mode = ATA_UDMA2; 5560 } 5561 } 5562 else 5563 mode = ata_check_80pin(dev, mode); 5564 5565 if (ctlr->chip->cfg2 & NVIDIA) 5566 reg += 0x10; 5567 5568 if (ctlr->chip->cfg1 != VIA133) 5569 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1); 5570 5571 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5572 5573 if (bootverbose) 5574 device_printf(dev, "%ssetting %s on %s chip\n", 5575 (error) ? "FAILURE " : "", ata_mode2str(mode), 5576 ctlr->chip->text); 5577 if (!error) { 5578 if (mode >= ATA_UDMA0) 5579 pci_write_config(gparent, reg, 5580 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 5581 else 5582 pci_write_config(gparent, reg, 0x8b, 1); 5583 atadev->mode = mode; 5584 } 5585 } 5586 5587 5588 /* misc functions */ 5589 static struct ata_chip_id * 5590 ata_match_chip(device_t dev, struct ata_chip_id *index) 5591 { 5592 while (index->chipid != 0) { 5593 if (pci_get_devid(dev) == index->chipid && 5594 pci_get_revid(dev) >= index->chiprev) 5595 return index; 5596 index++; 5597 } 5598 return NULL; 5599 } 5600 5601 static struct ata_chip_id * 5602 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot) 5603 { 5604 device_t *children; 5605 int nchildren, i; 5606 5607 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5608 return 0; 5609 5610 while (index->chipid != 0) { 5611 for (i = 0; i < nchildren; i++) { 5612 if (((slot >= 0 && pci_get_slot(children[i]) == slot) || 5613 (slot < 0 && pci_get_slot(children[i]) <= -slot)) && 5614 pci_get_devid(children[i]) == index->chipid && 5615 pci_get_revid(children[i]) >= index->chiprev) { 5616 kfree(children, M_TEMP); 5617 return index; 5618 } 5619 } 5620 index++; 5621 } 5622 kfree(children, M_TEMP); 5623 return NULL; 5624 } 5625 5626 static int 5627 ata_setup_interrupt(device_t dev) 5628 { 5629 struct ata_pci_controller *ctlr = device_get_softc(dev); 5630 int rid = ATA_IRQ_RID; 5631 5632 if (!ata_legacy(dev)) { 5633 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 5634 RF_SHAREABLE | RF_ACTIVE))) { 5635 device_printf(dev, "unable to map interrupt\n"); 5636 return ENXIO; 5637 } 5638 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 5639 ata_generic_intr, ctlr, &ctlr->handle, NULL))) { 5640 device_printf(dev, "unable to setup interrupt\n"); 5641 return ENXIO; 5642 } 5643 } 5644 return 0; 5645 } 5646 5647 struct ata_serialize { 5648 struct spinlock locked_mtx; 5649 int locked_ch; 5650 int restart_ch; 5651 }; 5652 5653 static int 5654 ata_serialize(device_t dev, int flags) 5655 { 5656 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5657 struct ata_channel *ch = device_get_softc(dev); 5658 struct ata_serialize *serial; 5659 static int inited = 0; 5660 int res; 5661 5662 if (!inited) { 5663 serial = kmalloc(sizeof(struct ata_serialize), 5664 M_TEMP, M_INTWAIT | M_ZERO); 5665 spin_init(&serial->locked_mtx); 5666 serial->locked_ch = -1; 5667 serial->restart_ch = -1; 5668 device_set_ivars(ctlr->dev, serial); 5669 inited = 1; 5670 } 5671 else 5672 serial = device_get_ivars(ctlr->dev); 5673 5674 spin_lock_wr(&serial->locked_mtx); 5675 switch (flags) { 5676 case ATA_LF_LOCK: 5677 if (serial->locked_ch == -1) 5678 serial->locked_ch = ch->unit; 5679 if (serial->locked_ch != ch->unit) 5680 serial->restart_ch = ch->unit; 5681 break; 5682 5683 case ATA_LF_UNLOCK: 5684 if (serial->locked_ch == ch->unit) { 5685 serial->locked_ch = -1; 5686 if (serial->restart_ch != -1) { 5687 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) { 5688 serial->restart_ch = -1; 5689 spin_unlock_wr(&serial->locked_mtx); 5690 ata_start(ch->dev); 5691 return -1; 5692 } 5693 } 5694 } 5695 break; 5696 5697 case ATA_LF_WHICH: 5698 break; 5699 } 5700 res = serial->locked_ch; 5701 spin_unlock_wr(&serial->locked_mtx); 5702 return res; 5703 } 5704 5705 static void 5706 ata_print_cable(device_t dev, u_int8_t *who) 5707 { 5708 device_printf(dev, 5709 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who); 5710 } 5711 5712 static int 5713 ata_atapi(device_t dev) 5714 { 5715 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5716 struct ata_device *atadev = device_get_softc(dev); 5717 5718 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || 5719 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE)); 5720 } 5721 5722 static int 5723 ata_check_80pin(device_t dev, int mode) 5724 { 5725 struct ata_device *atadev = device_get_softc(dev); 5726 5727 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) { 5728 ata_print_cable(dev, "device"); 5729 mode = ATA_UDMA2; 5730 } 5731 return mode; 5732 } 5733 5734 static int 5735 ata_mode2idx(int mode) 5736 { 5737 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) 5738 return (mode & ATA_MODE_MASK) + 8; 5739 if ((mode & ATA_DMA_MASK) == ATA_WDMA0) 5740 return (mode & ATA_MODE_MASK) + 5; 5741 return (mode & ATA_MODE_MASK) - ATA_PIO0; 5742 } 5743