1 /*- 2 * Copyright (c) 1998 - 2006 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.196 2007/04/08 19:18:51 sos Exp $ 27 * $DragonFly: src/sys/dev/disk/nata/ata-chipset.c,v 1.15 2008/07/12 16:38:10 mneumann Exp $ 28 */ 29 30 #include "opt_ata.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/bus_dma.h> 35 #include <sys/bus_resource.h> 36 #include <sys/callout.h> 37 #include <sys/endian.h> 38 #include <sys/libkern.h> 39 #include <sys/lock.h> /* for {get,rel}_mplock() */ 40 #include <sys/malloc.h> 41 #include <sys/nata.h> 42 #include <sys/queue.h> 43 #include <sys/rman.h> 44 #include <sys/spinlock.h> 45 #include <sys/systm.h> 46 #include <sys/taskqueue.h> 47 #include <sys/machintr.h> 48 49 #include <sys/spinlock2.h> 50 #include <sys/mplock2.h> 51 52 #include <machine/bus_dma.h> 53 54 #include <bus/pci/pcireg.h> 55 #include <bus/pci/pcivar.h> 56 57 #include "ata-all.h" 58 #include "ata-pci.h" 59 #include "ata_if.h" 60 61 /* local prototypes */ 62 /* ata-chipset.c */ 63 static int ata_generic_chipinit(device_t dev); 64 static void ata_generic_intr(void *data); 65 static void ata_generic_setmode(device_t dev, int mode); 66 static void ata_sata_phy_check_events(device_t dev); 67 static void ata_sata_phy_event(void *context, int dummy); 68 static int ata_sata_phy_reset(device_t dev); 69 static int ata_sata_connect(struct ata_channel *ch); 70 static void ata_sata_setmode(device_t dev, int mode); 71 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); 72 static int ata_ahci_chipinit(device_t dev); 73 static int ata_ahci_allocate(device_t dev); 74 static int ata_ahci_status(device_t dev); 75 static int ata_ahci_begin_transaction(struct ata_request *request); 76 static int ata_ahci_end_transaction(struct ata_request *request); 77 static void ata_ahci_reset(device_t dev); 78 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 79 static void ata_ahci_dmainit(device_t dev); 80 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request); 81 static int ata_acard_chipinit(device_t dev); 82 static int ata_acard_allocate(device_t dev); 83 static int ata_acard_status(device_t dev); 84 static void ata_acard_850_setmode(device_t dev, int mode); 85 static void ata_acard_86X_setmode(device_t dev, int mode); 86 static int ata_ali_chipinit(device_t dev); 87 static int ata_ali_allocate(device_t dev); 88 static int ata_ali_sata_allocate(device_t dev); 89 static void ata_ali_reset(device_t dev); 90 static void ata_ali_setmode(device_t dev, int mode); 91 static int ata_amd_chipinit(device_t dev); 92 static int ata_ati_chipinit(device_t dev); 93 static void ata_ati_setmode(device_t dev, int mode); 94 static int ata_cyrix_chipinit(device_t dev); 95 static void ata_cyrix_setmode(device_t dev, int mode); 96 static int ata_cypress_chipinit(device_t dev); 97 static void ata_cypress_setmode(device_t dev, int mode); 98 static int ata_highpoint_chipinit(device_t dev); 99 static int ata_highpoint_allocate(device_t dev); 100 static void ata_highpoint_setmode(device_t dev, int mode); 101 static int ata_highpoint_check_80pin(device_t dev, int mode); 102 static int ata_intel_chipinit(device_t dev); 103 static int ata_intel_allocate(device_t dev); 104 static void ata_intel_reset(device_t dev); 105 static void ata_intel_old_setmode(device_t dev, int mode); 106 static void ata_intel_new_setmode(device_t dev, int mode); 107 static void ata_intel_sata_setmode(device_t dev, int mode); 108 static int ata_intel_31244_allocate(device_t dev); 109 static int ata_intel_31244_status(device_t dev); 110 static int ata_intel_31244_command(struct ata_request *request); 111 static void ata_intel_31244_reset(device_t dev); 112 static int ata_ite_chipinit(device_t dev); 113 static void ata_ite_setmode(device_t dev, int mode); 114 static int ata_jmicron_chipinit(device_t dev); 115 static int ata_jmicron_allocate(device_t dev); 116 static void ata_jmicron_reset(device_t dev); 117 static void ata_jmicron_dmainit(device_t dev); 118 static void ata_jmicron_setmode(device_t dev, int mode); 119 static int ata_marvell_pata_chipinit(device_t dev); 120 static int ata_marvell_pata_allocate(device_t dev); 121 static void ata_marvell_pata_setmode(device_t dev, int mode); 122 static int ata_marvell_edma_chipinit(device_t dev); 123 static int ata_marvell_edma_allocate(device_t dev); 124 static int ata_marvell_edma_status(device_t dev); 125 static int ata_marvell_edma_begin_transaction(struct ata_request *request); 126 static int ata_marvell_edma_end_transaction(struct ata_request *request); 127 static void ata_marvell_edma_reset(device_t dev); 128 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 129 static void ata_marvell_edma_dmainit(device_t dev); 130 static int ata_national_chipinit(device_t dev); 131 static void ata_national_setmode(device_t dev, int mode); 132 static int ata_netcell_chipinit(device_t dev); 133 static int ata_netcell_allocate(device_t dev); 134 static int ata_nvidia_chipinit(device_t dev); 135 static int ata_nvidia_allocate(device_t dev); 136 static int ata_nvidia_status(device_t dev); 137 static void ata_nvidia_reset(device_t dev); 138 static int ata_promise_chipinit(device_t dev); 139 static int ata_promise_allocate(device_t dev); 140 static int ata_promise_status(device_t dev); 141 static int ata_promise_dmastart(device_t dev); 142 static int ata_promise_dmastop(device_t dev); 143 static void ata_promise_dmareset(device_t dev); 144 static void ata_promise_dmainit(device_t dev); 145 static void ata_promise_setmode(device_t dev, int mode); 146 static int ata_promise_tx2_allocate(device_t dev); 147 static int ata_promise_tx2_status(device_t dev); 148 static int ata_promise_mio_allocate(device_t dev); 149 static void ata_promise_mio_intr(void *data); 150 static int ata_promise_mio_status(device_t dev); 151 static int ata_promise_mio_command(struct ata_request *request); 152 static void ata_promise_mio_reset(device_t dev); 153 static void ata_promise_mio_dmainit(device_t dev); 154 static void ata_promise_mio_setmode(device_t dev, int mode); 155 static void ata_promise_sx4_intr(void *data); 156 static int ata_promise_sx4_command(struct ata_request *request); 157 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 158 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 159 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 160 static int ata_serverworks_chipinit(device_t dev); 161 static int ata_serverworks_allocate(device_t dev); 162 static void ata_serverworks_setmode(device_t dev, int mode); 163 static int ata_sii_chipinit(device_t dev); 164 static int ata_cmd_allocate(device_t dev); 165 static int ata_cmd_status(device_t dev); 166 static void ata_cmd_setmode(device_t dev, int mode); 167 static int ata_sii_allocate(device_t dev); 168 static int ata_sii_status(device_t dev); 169 static void ata_sii_reset(device_t dev); 170 static void ata_sii_setmode(device_t dev, int mode); 171 static int ata_siiprb_allocate(device_t dev); 172 static int ata_siiprb_status(device_t dev); 173 static int ata_siiprb_begin_transaction(struct ata_request *request); 174 static int ata_siiprb_end_transaction(struct ata_request *request); 175 static void ata_siiprb_reset(device_t dev); 176 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 177 static void ata_siiprb_dmainit(device_t dev); 178 static int ata_sis_chipinit(device_t dev); 179 static int ata_sis_allocate(device_t dev); 180 static void ata_sis_reset(device_t dev); 181 static void ata_sis_setmode(device_t dev, int mode); 182 static int ata_via_chipinit(device_t dev); 183 static int ata_via_allocate(device_t dev); 184 static void ata_via_reset(device_t dev); 185 static void ata_via_setmode(device_t dev, int mode); 186 static void ata_via_southbridge_fixup(device_t dev); 187 static void ata_via_family_setmode(device_t dev, int mode); 188 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index); 189 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot); 190 static int ata_setup_interrupt(device_t dev); 191 static void ata_teardown_interrupt(device_t dev); 192 static int ata_serialize(device_t dev, int flags); 193 static void ata_print_cable(device_t dev, u_int8_t *who); 194 static int ata_atapi(device_t dev); 195 static int ata_check_80pin(device_t dev, int mode); 196 static int ata_mode2idx(int mode); 197 198 199 /* 200 * generic ATA support functions 201 */ 202 int 203 ata_generic_ident(device_t dev) 204 { 205 struct ata_pci_controller *ctlr = device_get_softc(dev); 206 char buffer[64]; 207 208 ksnprintf(buffer, sizeof(buffer), 209 "%s ATA controller", ata_pcivendor2str(dev)); 210 device_set_desc_copy(dev, buffer); 211 ctlr->chipinit = ata_generic_chipinit; 212 return 0; 213 } 214 215 static int 216 ata_generic_chipinit(device_t dev) 217 { 218 struct ata_pci_controller *ctlr = device_get_softc(dev); 219 220 if (ata_setup_interrupt(dev)) 221 return ENXIO; 222 ctlr->setmode = ata_generic_setmode; 223 return 0; 224 } 225 226 static void 227 ata_generic_intr(void *data) 228 { 229 struct ata_pci_controller *ctlr = data; 230 struct ata_channel *ch; 231 int unit; 232 233 for (unit = 0; unit < ctlr->channels; unit++) { 234 if ((ch = ctlr->interrupt[unit].argument)) 235 ctlr->interrupt[unit].function(ch); 236 } 237 } 238 239 static void 240 ata_generic_setmode(device_t dev, int mode) 241 { 242 struct ata_device *atadev = device_get_softc(dev); 243 244 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 245 mode = ata_check_80pin(dev, mode); 246 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 247 atadev->mode = mode; 248 } 249 250 251 /* 252 * SATA support functions 253 */ 254 static void 255 ata_sata_phy_check_events(device_t dev) 256 { 257 struct ata_channel *ch = device_get_softc(dev); 258 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR); 259 260 /* clear error bits/interrupt */ 261 ATA_IDX_OUTL(ch, ATA_SERROR, error); 262 263 /* do we have any events flagged ? */ 264 if (error) { 265 struct ata_connect_task *tp; 266 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS); 267 268 /* if we have a connection event deal with it */ 269 if ((error & ATA_SE_PHY_CHANGED) && 270 (tp = (struct ata_connect_task *) 271 kmalloc(sizeof(struct ata_connect_task), 272 M_ATA, M_INTWAIT | M_ZERO))) { 273 274 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) || 275 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) { 276 if (bootverbose) 277 device_printf(ch->dev, "CONNECT requested\n"); 278 tp->action = ATA_C_ATTACH; 279 } 280 else { 281 if (bootverbose) 282 device_printf(ch->dev, "DISCONNECT requested\n"); 283 tp->action = ATA_C_DETACH; 284 } 285 tp->dev = ch->dev; 286 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 287 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 288 } 289 } 290 } 291 292 static void 293 ata_sata_phy_event(void *context, int dummy) 294 { 295 struct ata_connect_task *tp = (struct ata_connect_task *)context; 296 struct ata_channel *ch = device_get_softc(tp->dev); 297 device_t *children; 298 int nchildren, i; 299 300 get_mplock(); 301 if (tp->action == ATA_C_ATTACH) { 302 if (bootverbose) 303 device_printf(tp->dev, "CONNECTED\n"); 304 ATA_RESET(tp->dev); 305 ata_identify(tp->dev); 306 } 307 if (tp->action == ATA_C_DETACH) { 308 if (!device_get_children(tp->dev, &children, &nchildren)) { 309 for (i = 0; i < nchildren; i++) 310 if (children[i]) 311 device_delete_child(tp->dev, children[i]); 312 kfree(children, M_TEMP); 313 } 314 spin_lock(&ch->state_mtx); 315 ch->state = ATA_IDLE; 316 spin_unlock(&ch->state_mtx); 317 if (bootverbose) 318 device_printf(tp->dev, "DISCONNECTED\n"); 319 } 320 rel_mplock(); 321 kfree(tp, M_ATA); 322 } 323 324 static int 325 ata_sata_phy_reset(device_t dev) 326 { 327 struct ata_channel *ch = device_get_softc(dev); 328 int loop, retry; 329 330 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 331 return ata_sata_connect(ch); 332 333 for (retry = 0; retry < 10; retry++) { 334 for (loop = 0; loop < 10; loop++) { 335 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET); 336 ata_udelay(100); 337 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & 338 ATA_SC_DET_MASK) == ATA_SC_DET_RESET) 339 break; 340 } 341 ata_udelay(5000); 342 for (loop = 0; loop < 10; loop++) { 343 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE | 344 ATA_SC_IPM_DIS_PARTIAL | 345 ATA_SC_IPM_DIS_SLUMBER); 346 ata_udelay(100); 347 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0) 348 return ata_sata_connect(ch); 349 } 350 } 351 return 0; 352 } 353 354 static int 355 ata_sata_connect(struct ata_channel *ch) 356 { 357 u_int32_t status; 358 int timeout; 359 360 /* wait up to 1 second for "connect well" */ 361 for (timeout = 0; timeout < 100 ; timeout++) { 362 status = ATA_IDX_INL(ch, ATA_SSTATUS); 363 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 || 364 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2) 365 break; 366 ata_udelay(10000); 367 } 368 if (timeout >= 100) { 369 if (bootverbose) 370 device_printf(ch->dev, "SATA connect status=%08x\n", status); 371 return 0; 372 } 373 374 if (bootverbose) 375 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10); 376 377 /* clear SATA error register */ 378 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 379 380 return 1; 381 } 382 383 static void 384 ata_sata_setmode(device_t dev, int mode) 385 { 386 struct ata_device *atadev = device_get_softc(dev); 387 388 /* 389 * if we detect that the device isn't a real SATA device we limit 390 * the transfer mode to UDMA5/ATA100. 391 * this works around the problems some devices has with the 392 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133. 393 */ 394 if (atadev->param.satacapabilities != 0x0000 && 395 atadev->param.satacapabilities != 0xffff) { 396 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 397 398 /* on some drives we need to set the transfer mode */ 399 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 400 ata_limit_mode(dev, mode, ATA_UDMA6)); 401 402 /* query SATA STATUS for the speed */ 403 if (ch->r_io[ATA_SSTATUS].res && 404 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) == 405 ATA_SS_CONWELL_GEN2)) 406 atadev->mode = ATA_SA300; 407 else 408 atadev->mode = ATA_SA150; 409 } 410 else { 411 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 412 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 413 atadev->mode = mode; 414 } 415 } 416 417 static int 418 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis) 419 { 420 struct ata_device *atadev = device_get_softc(request->dev); 421 422 if (request->flags & ATA_R_ATAPI) { 423 fis[0] = 0x27; /* host to device */ 424 fis[1] = 0x80; /* command FIS (note PM goes here) */ 425 fis[2] = ATA_PACKET_CMD; 426 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) 427 fis[3] = ATA_F_DMA; 428 else { 429 fis[5] = request->transfersize; 430 fis[6] = request->transfersize >> 8; 431 } 432 fis[7] = ATA_D_LBA | atadev->unit; 433 fis[15] = ATA_A_4BIT; 434 return 20; 435 } 436 else { 437 ata_modify_if_48bit(request); 438 fis[0] = 0x27; /* host to device */ 439 fis[1] = 0x80; /* command FIS (note PM goes here) */ 440 fis[2] = request->u.ata.command; 441 fis[3] = request->u.ata.feature; 442 fis[4] = request->u.ata.lba; 443 fis[5] = request->u.ata.lba >> 8; 444 fis[6] = request->u.ata.lba >> 16; 445 fis[7] = ATA_D_LBA | atadev->unit; 446 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 447 fis[7] |= (request->u.ata.lba >> 24 & 0x0f); 448 fis[8] = request->u.ata.lba >> 24; 449 fis[9] = request->u.ata.lba >> 32; 450 fis[10] = request->u.ata.lba >> 40; 451 fis[11] = request->u.ata.feature >> 8; 452 fis[12] = request->u.ata.count; 453 fis[13] = request->u.ata.count >> 8; 454 fis[15] = ATA_A_4BIT; 455 return 20; 456 } 457 return 0; 458 } 459 460 /* 461 * AHCI v1.x compliant SATA chipset support functions 462 */ 463 int 464 ata_ahci_ident(device_t dev) 465 { 466 struct ata_pci_controller *ctlr = device_get_softc(dev); 467 static struct ata_chip_id id = {0, 0, 0, 0x00, ATA_SA300, "AHCI"}; 468 char buffer[64]; 469 470 if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0) 471 return ENXIO; 472 473 if (bootverbose) 474 ksnprintf(buffer, sizeof(buffer), "%s (ID=%08x) AHCI controller", 475 ata_pcivendor2str(dev), pci_get_devid(dev)); 476 else 477 ksnprintf(buffer, sizeof(buffer), "%s AHCI controller", 478 ata_pcivendor2str(dev)); 479 device_set_desc_copy(dev, buffer); 480 ctlr->chip = &id; 481 ctlr->chipinit = ata_ahci_chipinit; 482 return 0; 483 } 484 485 486 /* 487 * AHCI v1.x compliant SATA chipset support functions 488 */ 489 int 490 ata_ahci_chipinit(device_t dev) 491 { 492 struct ata_pci_controller *ctlr = device_get_softc(dev); 493 u_int32_t version; 494 int unit; 495 496 /* if we have a memory BAR(5) we are likely on an AHCI part */ 497 ctlr->r_type2 = SYS_RES_MEMORY; 498 ctlr->r_rid2 = PCIR_BAR(5); 499 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 500 &ctlr->r_rid2, RF_ACTIVE))) 501 return ENXIO; 502 503 /* setup interrupt delivery if not done allready by a vendor driver */ 504 if (!ctlr->r_irq) { 505 if (ata_setup_interrupt(dev)) 506 return ENXIO; 507 } 508 else 509 device_printf(dev, "AHCI called from vendor specific driver\n"); 510 511 /* enable AHCI mode */ 512 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 513 514 /* reset AHCI controller */ 515 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR); 516 DELAY(1000000); 517 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) { 518 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 519 device_printf(dev, "AHCI controller reset failure\n"); 520 return ENXIO; 521 } 522 523 /* reenable AHCI mode */ 524 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 525 526 /* get the number of HW channels */ 527 ctlr->channels = 528 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)), 529 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 530 531 /* disable interrupt sources and clear interrupts */ 532 for (unit = 0; unit < ctlr->channels; unit++) { 533 int offset = unit << 7; 534 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0); 535 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, -1); 536 } 537 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS)); 538 539 /* enable AHCI interrupts */ 540 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 541 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE); 542 543 ctlr->reset = ata_ahci_reset; 544 ctlr->dmainit = ata_ahci_dmainit; 545 ctlr->allocate = ata_ahci_allocate; 546 ctlr->setmode = ata_sata_setmode; 547 548 /* enable PCI interrupt */ 549 pci_write_config(dev, PCIR_COMMAND, 550 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 551 552 /* announce we support the HW */ 553 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS); 554 device_printf(dev, 555 "AHCI Version %x%x.%x%x controller with %d ports detected\n", 556 (version >> 24) & 0xff, (version >> 16) & 0xff, 557 (version >> 8) & 0xff, version & 0xff, 558 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 559 return 0; 560 } 561 562 static int 563 ata_ahci_allocate(device_t dev) 564 { 565 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 566 struct ata_channel *ch = device_get_softc(dev); 567 u_int64_t work; 568 int offset = ch->unit << 7; 569 570 /* set the SATA resources */ 571 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 572 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset; 573 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 574 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset; 575 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 576 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset; 577 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 578 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset; 579 580 ch->hw.status = ata_ahci_status; 581 ch->hw.begin_transaction = ata_ahci_begin_transaction; 582 ch->hw.end_transaction = ata_ahci_end_transaction; 583 ch->hw.command = NULL; /* not used here */ 584 585 /* setup work areas */ 586 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET; 587 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff); 588 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32); 589 590 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET; 591 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff); 592 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32); 593 594 /* enable wanted port interrupts */ 595 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 596 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF | 597 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF | 598 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP | 599 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS | 600 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR)); 601 602 /* start operations on this channel */ 603 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 604 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 605 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 606 return 0; 607 } 608 609 static int 610 ata_ahci_status(device_t dev) 611 { 612 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 613 struct ata_channel *ch = device_get_softc(dev); 614 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS); 615 int offset = ch->unit << 7; 616 int tag = 0; 617 618 if (action & (1 << ch->unit)) { 619 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset); 620 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset); 621 622 /* clear interrupt(s) */ 623 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit)); 624 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus); 625 626 /* do we have any PHY events ? */ 627 /* XXX SOS check istatus phy bits */ 628 ata_sata_phy_check_events(dev); 629 630 /* do we have a potentially hanging engine to take care of? */ 631 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) { 632 633 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 634 int timeout = 0; 635 636 /* kill off all activity on this channel */ 637 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 638 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 639 640 /* XXX SOS this is not entirely wrong */ 641 do { 642 DELAY(1000); 643 if (timeout++ > 500) { 644 device_printf(dev, "stopping AHCI engine failed\n"); 645 break; 646 } 647 } while (ATA_INL(ctlr->r_res2, 648 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 649 650 /* start operations on this channel */ 651 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 652 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 653 654 return 1; 655 } 656 else 657 return (!(cstatus & (1 << tag))); 658 } 659 return 0; 660 } 661 662 /* must be called with ATA channel locked and state_mtx held */ 663 static int 664 ata_ahci_begin_transaction(struct ata_request *request) 665 { 666 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 667 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 668 struct ata_ahci_cmd_tab *ctp; 669 struct ata_ahci_cmd_list *clp; 670 int offset = ch->unit << 7; 671 int tag = 0, entries = 0; 672 int fis_size; 673 674 /* get a piece of the workspace for this request */ 675 ctp = (struct ata_ahci_cmd_tab *) 676 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag)); 677 678 /* setup the FIS for this request */ 679 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) { 680 device_printf(request->dev, "setting up SATA FIS failed\n"); 681 request->result = EIO; 682 return ATA_OP_FINISHED; 683 } 684 685 /* if request moves data setup and load SG list */ 686 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 687 if (ch->dma->load(ch->dev, request->data, request->bytecount, 688 request->flags & ATA_R_READ, 689 ctp->prd_tab, &entries)) { 690 device_printf(request->dev, "setting up DMA failed\n"); 691 request->result = EIO; 692 return ATA_OP_FINISHED; 693 } 694 } 695 696 /* setup the command list entry */ 697 clp = (struct ata_ahci_cmd_list *) 698 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 699 700 clp->prd_length = entries; 701 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) | 702 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) | 703 (fis_size / sizeof(u_int32_t)); 704 clp->bytecount = 0; 705 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET + 706 (ATA_AHCI_CT_SIZE * tag)); 707 708 /* clear eventual ACTIVE bit */ 709 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag)); 710 711 /* set command type bit */ 712 if (request->flags & ATA_R_ATAPI) 713 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 714 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) | 715 ATA_AHCI_P_CMD_ATAPI); 716 else 717 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 718 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & 719 ~ATA_AHCI_P_CMD_ATAPI); 720 721 /* issue command to controller */ 722 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag)); 723 724 if (!(request->flags & ATA_R_ATAPI)) { 725 /* device reset doesn't interrupt */ 726 if (request->u.ata.command == ATA_DEVICE_RESET) { 727 u_int32_t tf_data; 728 int timeout = 1000000; 729 730 do { 731 DELAY(10); 732 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7)); 733 } while ((tf_data & ATA_S_BUSY) && timeout--); 734 if (bootverbose) 735 device_printf(ch->dev, "device_reset timeout=%dus\n", 736 (1000000-timeout)*10); 737 request->status = tf_data; 738 if (request->status & ATA_S_ERROR) 739 request->error = tf_data >> 8; 740 return ATA_OP_FINISHED; 741 } 742 } 743 744 /* start the timeout */ 745 callout_reset(&request->callout, request->timeout * hz, 746 (timeout_t*)ata_timeout, request); 747 return ATA_OP_CONTINUES; 748 } 749 750 /* must be called with ATA channel locked and state_mtx held */ 751 static int 752 ata_ahci_end_transaction(struct ata_request *request) 753 { 754 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 755 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 756 struct ata_ahci_cmd_list *clp; 757 u_int32_t tf_data; 758 int offset = ch->unit << 7; 759 int tag = 0; 760 761 /* kill the timeout */ 762 callout_stop(&request->callout); 763 764 /* get status */ 765 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset); 766 request->status = tf_data; 767 768 /* if error status get details */ 769 if (request->status & ATA_S_ERROR) 770 request->error = tf_data >> 8; 771 772 /* record how much data we actually moved */ 773 clp = (struct ata_ahci_cmd_list *) 774 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 775 request->donecount = clp->bytecount; 776 777 /* release SG list etc */ 778 ch->dma->unload(ch->dev); 779 780 return ATA_OP_FINISHED; 781 } 782 783 static void 784 ata_ahci_reset(device_t dev) 785 { 786 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 787 struct ata_channel *ch = device_get_softc(dev); 788 u_int32_t cmd, signature; 789 int offset = ch->unit << 7; 790 int timeout; 791 792 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) { 793 device_printf(dev, "port not implemented\n"); 794 return; 795 } 796 ch->devices = 0; 797 798 /* kill off all activity on this channel */ 799 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 800 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 801 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 802 803 /* XXX SOS this is not entirely wrong */ 804 timeout = 0; 805 do { 806 DELAY(1000); 807 if (timeout++ > 500) { 808 device_printf(dev, "stopping AHCI engine failed\n"); 809 break; 810 } 811 } 812 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 813 814 /* issue Command List Override if supported */ 815 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) { 816 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 817 cmd |= ATA_AHCI_P_CMD_CLO; 818 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd); 819 timeout = 0; 820 do { 821 DELAY(1000); 822 if (timeout++ > 500) { 823 device_printf(dev, "executing CLO failed\n"); 824 break; 825 } 826 } 827 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO); 828 } 829 830 /* reset PHY and decide what is present */ 831 if (ata_sata_phy_reset(dev)) { 832 833 /* clear any interrupts pending on this channel */ 834 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, 835 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset)); 836 837 /* clear SATA error register */ 838 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 839 840 /* start operations on this channel */ 841 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 842 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 843 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 844 845 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset); 846 switch (signature) { 847 case 0x00000101: 848 ch->devices = ATA_ATA_MASTER; 849 break; 850 case 0x96690101: 851 ch->devices = ATA_PORTMULTIPLIER; 852 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 853 ch->devices = 0; 854 break; 855 case 0xeb140101: 856 ch->devices = ATA_ATAPI_MASTER; 857 break; 858 default: /* SOS XXX */ 859 if (bootverbose) 860 device_printf(ch->dev, "No signature, assuming disk device\n"); 861 ch->devices = ATA_ATA_MASTER; 862 } 863 } 864 if (bootverbose) 865 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices, 866 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 867 } 868 869 static void 870 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 871 { 872 struct ata_dmasetprd_args *args = xsc; 873 struct ata_ahci_dma_prd *prd = args->dmatab; 874 int i; 875 876 if (!(args->error = error)) { 877 for (i = 0; i < nsegs; i++) { 878 prd[i].dba = htole64(segs[i].ds_addr); 879 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK); 880 } 881 } 882 args->nsegs = nsegs; 883 } 884 885 static void 886 ata_ahci_dmainit(device_t dev) 887 { 888 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 889 struct ata_channel *ch = device_get_softc(dev); 890 891 ata_dmainit(dev); 892 if (ch->dma) { 893 /* note start and stop are not used here */ 894 ch->dma->setprd = ata_ahci_dmasetprd; 895 ch->dma->max_iosize = 8192 * DEV_BSIZE; 896 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT) 897 ch->dma->max_address = BUS_SPACE_MAXADDR; 898 } 899 } 900 901 static int 902 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request) 903 { 904 bzero(ctp->cfis, 64); 905 if (request->flags & ATA_R_ATAPI) { 906 bzero(ctp->acmd, 32); 907 bcopy(request->u.atapi.ccb, ctp->acmd, 16); 908 } 909 return ata_request2fis_h2d(request, &ctp->cfis[0]); 910 } 911 912 /* 913 * Acard chipset support functions 914 */ 915 int 916 ata_acard_ident(device_t dev) 917 { 918 struct ata_pci_controller *ctlr = device_get_softc(dev); 919 struct ata_chip_id *idx; 920 static struct ata_chip_id ids[] = 921 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" }, 922 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" }, 923 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" }, 924 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" }, 925 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" }, 926 { 0, 0, 0, 0, 0, 0}}; 927 char buffer[64]; 928 929 if (!(idx = ata_match_chip(dev, ids))) 930 return ENXIO; 931 932 ksprintf(buffer, "Acard %s %s controller", 933 idx->text, ata_mode2str(idx->max_dma)); 934 device_set_desc_copy(dev, buffer); 935 ctlr->chip = idx; 936 ctlr->chipinit = ata_acard_chipinit; 937 return 0; 938 } 939 940 static int 941 ata_acard_chipinit(device_t dev) 942 { 943 struct ata_pci_controller *ctlr = device_get_softc(dev); 944 945 if (ata_setup_interrupt(dev)) 946 return ENXIO; 947 948 ctlr->allocate = ata_acard_allocate; 949 if (ctlr->chip->cfg1 == ATPOLD) { 950 ctlr->setmode = ata_acard_850_setmode; 951 ctlr->locking = ata_serialize; 952 } 953 else 954 ctlr->setmode = ata_acard_86X_setmode; 955 return 0; 956 } 957 958 static int 959 ata_acard_allocate(device_t dev) 960 { 961 struct ata_channel *ch = device_get_softc(dev); 962 963 /* setup the usual register normal pci style */ 964 if (ata_pci_allocate(dev)) 965 return ENXIO; 966 967 ch->hw.status = ata_acard_status; 968 return 0; 969 } 970 971 static int 972 ata_acard_status(device_t dev) 973 { 974 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 975 struct ata_channel *ch = device_get_softc(dev); 976 977 if (ctlr->chip->cfg1 == ATPOLD && 978 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit) 979 return 0; 980 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) { 981 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 982 983 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != 984 ATA_BMSTAT_INTERRUPT) 985 return 0; 986 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR); 987 DELAY(1); 988 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 989 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 990 DELAY(1); 991 } 992 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 993 DELAY(100); 994 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 995 return 0; 996 } 997 return 1; 998 } 999 1000 static void 1001 ata_acard_850_setmode(device_t dev, int mode) 1002 { 1003 device_t gparent = GRANDPARENT(dev); 1004 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1005 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1006 struct ata_device *atadev = device_get_softc(dev); 1007 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1008 int error; 1009 1010 mode = ata_limit_mode(dev, mode, 1011 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 1012 1013 /* XXX SOS missing WDMA0+1 + PIO modes */ 1014 if (mode >= ATA_WDMA2) { 1015 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1016 if (bootverbose) 1017 device_printf(dev, "%ssetting %s on %s chip\n", 1018 (error) ? "FAILURE " : "", 1019 ata_mode2str(mode), ctlr->chip->text); 1020 if (!error) { 1021 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1); 1022 1023 reg54 &= ~(0x03 << (devno << 1)); 1024 if (mode >= ATA_UDMA0) 1025 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1)); 1026 pci_write_config(gparent, 0x54, reg54, 1); 1027 pci_write_config(gparent, 0x4a, 0xa6, 1); 1028 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2); 1029 atadev->mode = mode; 1030 return; 1031 } 1032 } 1033 /* we could set PIO mode timings, but we assume the BIOS did that */ 1034 } 1035 1036 static void 1037 ata_acard_86X_setmode(device_t dev, int mode) 1038 { 1039 device_t gparent = GRANDPARENT(dev); 1040 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1041 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1042 struct ata_device *atadev = device_get_softc(dev); 1043 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1044 int error; 1045 1046 1047 mode = ata_limit_mode(dev, mode, 1048 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 1049 1050 mode = ata_check_80pin(dev, mode); 1051 1052 /* XXX SOS missing WDMA0+1 + PIO modes */ 1053 if (mode >= ATA_WDMA2) { 1054 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1055 if (bootverbose) 1056 device_printf(dev, "%ssetting %s on %s chip\n", 1057 (error) ? "FAILURE " : "", 1058 ata_mode2str(mode), ctlr->chip->text); 1059 if (!error) { 1060 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2); 1061 1062 reg44 &= ~(0x000f << (devno << 2)); 1063 if (mode >= ATA_UDMA0) 1064 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2)); 1065 pci_write_config(gparent, 0x44, reg44, 2); 1066 pci_write_config(gparent, 0x4a, 0xa6, 1); 1067 pci_write_config(gparent, 0x40 + devno, 0x31, 1); 1068 atadev->mode = mode; 1069 return; 1070 } 1071 } 1072 /* we could set PIO mode timings, but we assume the BIOS did that */ 1073 } 1074 1075 1076 /* 1077 * Acer Labs Inc (ALI) chipset support functions 1078 */ 1079 int 1080 ata_ali_ident(device_t dev) 1081 { 1082 struct ata_pci_controller *ctlr = device_get_softc(dev); 1083 struct ata_chip_id *idx; 1084 static struct ata_chip_id ids[] = 1085 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" }, 1086 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" }, 1087 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" }, 1088 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" }, 1089 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" }, 1090 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" }, 1091 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" }, 1092 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" }, 1093 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" }, 1094 { 0, 0, 0, 0, 0, 0}}; 1095 char buffer[64]; 1096 1097 if (!(idx = ata_match_chip(dev, ids))) 1098 return ENXIO; 1099 1100 ksprintf(buffer, "AcerLabs %s %s controller", 1101 idx->text, ata_mode2str(idx->max_dma)); 1102 device_set_desc_copy(dev, buffer); 1103 ctlr->chip = idx; 1104 ctlr->chipinit = ata_ali_chipinit; 1105 return 0; 1106 } 1107 1108 static int 1109 ata_ali_chipinit(device_t dev) 1110 { 1111 struct ata_pci_controller *ctlr = device_get_softc(dev); 1112 1113 if (ata_setup_interrupt(dev)) 1114 return ENXIO; 1115 1116 switch (ctlr->chip->cfg2) { 1117 case ALISATA: 1118 ctlr->channels = ctlr->chip->cfg1; 1119 ctlr->allocate = ata_ali_sata_allocate; 1120 ctlr->setmode = ata_sata_setmode; 1121 1122 /* AHCI mode is correctly supported only on the ALi 5288. */ 1123 if ((ctlr->chip->chipid == ATA_ALI_5288) && 1124 (ata_ahci_chipinit(dev) != ENXIO)) 1125 return 0; 1126 1127 /* enable PCI interrupt */ 1128 pci_write_config(dev, PCIR_COMMAND, 1129 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1130 break; 1131 1132 case ALINEW: 1133 /* use device interrupt as byte count end */ 1134 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1); 1135 1136 /* enable cable detection and UDMA support on newer chips */ 1137 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1); 1138 1139 /* enable ATAPI UDMA mode */ 1140 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1); 1141 1142 /* only chips with revision > 0xc4 can do 48bit DMA */ 1143 if (ctlr->chip->chiprev <= 0xc4) 1144 device_printf(dev, 1145 "using PIO transfers above 137GB as workaround for " 1146 "48bit DMA access bug, expect reduced performance\n"); 1147 ctlr->allocate = ata_ali_allocate; 1148 ctlr->reset = ata_ali_reset; 1149 ctlr->setmode = ata_ali_setmode; 1150 break; 1151 1152 case ALIOLD: 1153 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */ 1154 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1); 1155 ctlr->setmode = ata_ali_setmode; 1156 break; 1157 } 1158 return 0; 1159 } 1160 1161 static int 1162 ata_ali_allocate(device_t dev) 1163 { 1164 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1165 struct ata_channel *ch = device_get_softc(dev); 1166 1167 /* setup the usual register normal pci style */ 1168 if (ata_pci_allocate(dev)) 1169 return ENXIO; 1170 1171 /* older chips can't do 48bit DMA transfers */ 1172 if (ctlr->chip->chiprev <= 0xc4) 1173 ch->flags |= ATA_NO_48BIT_DMA; 1174 1175 return 0; 1176 } 1177 1178 static int 1179 ata_ali_sata_allocate(device_t dev) 1180 { 1181 device_t parent = device_get_parent(dev); 1182 struct ata_pci_controller *ctlr = device_get_softc(parent); 1183 struct ata_channel *ch = device_get_softc(dev); 1184 struct resource *io = NULL, *ctlio = NULL; 1185 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 1186 int i, rid; 1187 1188 rid = PCIR_BAR(0) + (unit01 ? 8 : 0); 1189 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1190 if (!io) 1191 return ENXIO; 1192 1193 rid = PCIR_BAR(1) + (unit01 ? 8 : 0); 1194 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1195 if (!ctlio) { 1196 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io); 1197 return ENXIO; 1198 } 1199 1200 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 1201 ch->r_io[i].res = io; 1202 ch->r_io[i].offset = i + (unit10 ? 8 : 0); 1203 } 1204 ch->r_io[ATA_CONTROL].res = ctlio; 1205 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0); 1206 ch->r_io[ATA_IDX_ADDR].res = io; 1207 ata_default_registers(dev); 1208 if (ctlr->r_res1) { 1209 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 1210 ch->r_io[i].res = ctlr->r_res1; 1211 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 1212 } 1213 } 1214 ch->flags |= ATA_NO_SLAVE; 1215 1216 /* XXX SOS PHY handling awkward in ALI chip not supported yet */ 1217 ata_pci_hw(dev); 1218 return 0; 1219 } 1220 1221 static void 1222 ata_ali_reset(device_t dev) 1223 { 1224 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1225 struct ata_channel *ch = device_get_softc(dev); 1226 device_t *children; 1227 int nchildren, i; 1228 1229 ata_generic_reset(dev); 1230 1231 /* 1232 * workaround for datacorruption bug found on at least SUN Blade-100 1233 * find the ISA function on the southbridge and disable then enable 1234 * the ATA channel tristate buffer 1235 */ 1236 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) { 1237 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) { 1238 for (i = 0; i < nchildren; i++) { 1239 if (pci_get_devid(children[i]) == ATA_ALI_1533) { 1240 pci_write_config(children[i], 0x58, 1241 pci_read_config(children[i], 0x58, 1) & 1242 ~(0x04 << ch->unit), 1); 1243 pci_write_config(children[i], 0x58, 1244 pci_read_config(children[i], 0x58, 1) | 1245 (0x04 << ch->unit), 1); 1246 break; 1247 } 1248 } 1249 kfree(children, M_TEMP); 1250 } 1251 } 1252 } 1253 1254 static void 1255 ata_ali_setmode(device_t dev, int mode) 1256 { 1257 device_t gparent = GRANDPARENT(dev); 1258 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1259 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1260 struct ata_device *atadev = device_get_softc(dev); 1261 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1262 int error; 1263 1264 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1265 1266 if (ctlr->chip->cfg2 & ALINEW) { 1267 if (mode > ATA_UDMA2 && 1268 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) { 1269 ata_print_cable(dev, "controller"); 1270 mode = ATA_UDMA2; 1271 } 1272 } 1273 else 1274 mode = ata_check_80pin(dev, mode); 1275 1276 if (ctlr->chip->cfg2 & ALIOLD) { 1277 /* doesn't support ATAPI DMA on write */ 1278 ch->flags |= ATA_ATAPI_DMA_RO; 1279 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) { 1280 /* doesn't support ATAPI DMA on two ATAPI devices */ 1281 device_printf(dev, "two atapi devices on this channel, no DMA\n"); 1282 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1283 } 1284 } 1285 1286 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1287 1288 if (bootverbose) 1289 device_printf(dev, "%ssetting %s on %s chip\n", 1290 (error) ? "FAILURE " : "", 1291 ata_mode2str(mode), ctlr->chip->text); 1292 if (!error) { 1293 if (mode >= ATA_UDMA0) { 1294 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d}; 1295 u_int32_t word54 = pci_read_config(gparent, 0x54, 4); 1296 1297 word54 &= ~(0x000f000f << (devno << 2)); 1298 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2)); 1299 pci_write_config(gparent, 0x54, word54, 4); 1300 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1301 0x00310001, 4); 1302 } 1303 else { 1304 u_int32_t piotimings[] = 1305 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001, 1306 0x00310001, 0x00440001, 0x00330001, 0x00310001}; 1307 1308 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) & 1309 ~(0x0008000f << (devno << 2)), 4); 1310 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1311 piotimings[ata_mode2idx(mode)], 4); 1312 } 1313 atadev->mode = mode; 1314 } 1315 } 1316 1317 1318 /* 1319 * American Micro Devices (AMD) chipset support functions 1320 */ 1321 int 1322 ata_amd_ident(device_t dev) 1323 { 1324 struct ata_pci_controller *ctlr = device_get_softc(dev); 1325 struct ata_chip_id *idx; 1326 static struct ata_chip_id ids[] = 1327 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" }, 1328 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" }, 1329 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" }, 1330 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" }, 1331 { 0, 0, 0, 0, 0, 0}}; 1332 char buffer[64]; 1333 1334 if (!(idx = ata_match_chip(dev, ids))) 1335 return ENXIO; 1336 1337 ksprintf(buffer, "AMD %s %s controller", 1338 idx->text, ata_mode2str(idx->max_dma)); 1339 device_set_desc_copy(dev, buffer); 1340 ctlr->chip = idx; 1341 ctlr->chipinit = ata_amd_chipinit; 1342 return 0; 1343 } 1344 1345 static int 1346 ata_amd_chipinit(device_t dev) 1347 { 1348 struct ata_pci_controller *ctlr = device_get_softc(dev); 1349 1350 if (ata_setup_interrupt(dev)) 1351 return ENXIO; 1352 1353 /* disable/set prefetch, postwrite */ 1354 if (ctlr->chip->cfg2 & AMDBUG) 1355 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1); 1356 else 1357 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); 1358 1359 ctlr->setmode = ata_via_family_setmode; 1360 return 0; 1361 } 1362 1363 1364 /* 1365 * ATI chipset support functions 1366 */ 1367 int 1368 ata_ati_ident(device_t dev) 1369 { 1370 struct ata_pci_controller *ctlr = device_get_softc(dev); 1371 struct ata_chip_id *idx; 1372 static struct ata_chip_id ids[] = 1373 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" }, 1374 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" }, 1375 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" }, 1376 { ATA_ATI_SB600, 0x00, 0, 0, ATA_UDMA6, "SB600" }, 1377 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" }, 1378 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1379 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1380 { ATA_ATI_SB600_S1, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1381 { ATA_ATI_SB600_S2, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1382 { 0, 0, 0, 0, 0, 0}}; 1383 char buffer[64]; 1384 1385 if (!(idx = ata_match_chip(dev, ids))) 1386 return ENXIO; 1387 1388 ksprintf(buffer, "ATI %s %s controller", 1389 idx->text, ata_mode2str(idx->max_dma)); 1390 device_set_desc_copy(dev, buffer); 1391 ctlr->chip = idx; 1392 1393 /* 1394 * The ATI SATA controllers are actually a SiI 3112 controller, except 1395 * for the SB600. 1396 */ 1397 if (ctlr->chip->cfg1 & SIIMEMIO) 1398 ctlr->chipinit = ata_sii_chipinit; 1399 else 1400 ctlr->chipinit = ata_ati_chipinit; 1401 return 0; 1402 } 1403 1404 static int 1405 ata_ati_chipinit(device_t dev) 1406 { 1407 struct ata_pci_controller *ctlr = device_get_softc(dev); 1408 1409 if (ata_setup_interrupt(dev)) 1410 return ENXIO; 1411 1412 /* The SB600 needs special treatment. */ 1413 if (ctlr->chip->cfg1 & ATIAHCI) { 1414 /* Check if the chip is configured as an AHCI part. */ 1415 if ((pci_get_subclass(dev) == PCIS_STORAGE_SATA) && 1416 (pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI_1_0)) { 1417 if (ata_ahci_chipinit(dev) != ENXIO) 1418 return 0; 1419 } 1420 } 1421 1422 ctlr->setmode = ata_ati_setmode; 1423 return 0; 1424 } 1425 1426 static void 1427 ata_ati_setmode(device_t dev, int mode) 1428 { 1429 device_t gparent = GRANDPARENT(dev); 1430 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1431 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1432 struct ata_device *atadev = device_get_softc(dev); 1433 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1434 int offset = (devno ^ 0x01) << 3; 1435 int error; 1436 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 1437 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 1438 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 1439 1440 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1441 1442 mode = ata_check_80pin(dev, mode); 1443 1444 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1445 1446 if (bootverbose) 1447 device_printf(dev, "%ssetting %s on %s chip\n", 1448 (error) ? "FAILURE " : "", 1449 ata_mode2str(mode), ctlr->chip->text); 1450 if (!error) { 1451 if (mode >= ATA_UDMA0) { 1452 pci_write_config(gparent, 0x56, 1453 (pci_read_config(gparent, 0x56, 2) & 1454 ~(0xf << (devno << 2))) | 1455 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 1456 pci_write_config(gparent, 0x54, 1457 pci_read_config(gparent, 0x54, 1) | 1458 (0x01 << devno), 1); 1459 pci_write_config(gparent, 0x44, 1460 (pci_read_config(gparent, 0x44, 4) & 1461 ~(0xff << offset)) | 1462 (dmatimings[2] << offset), 4); 1463 } 1464 else if (mode >= ATA_WDMA0) { 1465 pci_write_config(gparent, 0x54, 1466 pci_read_config(gparent, 0x54, 1) & 1467 ~(0x01 << devno), 1); 1468 pci_write_config(gparent, 0x44, 1469 (pci_read_config(gparent, 0x44, 4) & 1470 ~(0xff << offset)) | 1471 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 1472 } 1473 else 1474 pci_write_config(gparent, 0x54, 1475 pci_read_config(gparent, 0x54, 1) & 1476 ~(0x01 << devno), 1); 1477 1478 pci_write_config(gparent, 0x4a, 1479 (pci_read_config(gparent, 0x4a, 2) & 1480 ~(0xf << (devno << 2))) | 1481 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2); 1482 pci_write_config(gparent, 0x40, 1483 (pci_read_config(gparent, 0x40, 4) & 1484 ~(0xff << offset)) | 1485 (piotimings[ata_mode2idx(mode)] << offset), 4); 1486 atadev->mode = mode; 1487 } 1488 } 1489 1490 /* 1491 * Cyrix chipset support functions 1492 */ 1493 int 1494 ata_cyrix_ident(device_t dev) 1495 { 1496 struct ata_pci_controller *ctlr = device_get_softc(dev); 1497 1498 if (pci_get_devid(dev) == ATA_CYRIX_5530) { 1499 device_set_desc(dev, "Cyrix 5530 ATA33 controller"); 1500 ctlr->chipinit = ata_cyrix_chipinit; 1501 return 0; 1502 } 1503 return ENXIO; 1504 } 1505 1506 static int 1507 ata_cyrix_chipinit(device_t dev) 1508 { 1509 struct ata_pci_controller *ctlr = device_get_softc(dev); 1510 1511 if (ata_setup_interrupt(dev)) 1512 return ENXIO; 1513 1514 if (ctlr->r_res1) 1515 ctlr->setmode = ata_cyrix_setmode; 1516 else 1517 ctlr->setmode = ata_generic_setmode; 1518 return 0; 1519 } 1520 1521 static void 1522 ata_cyrix_setmode(device_t dev, int mode) 1523 { 1524 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1525 struct ata_device *atadev = device_get_softc(dev); 1526 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1527 u_int32_t piotiming[] = 1528 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 }; 1529 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 }; 1530 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 }; 1531 int error; 1532 1533 ch->dma->alignment = 16; 1534 ch->dma->max_iosize = 126 * DEV_BSIZE; 1535 1536 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 1537 1538 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1539 1540 if (bootverbose) 1541 device_printf(dev, "%ssetting %s on Cyrix chip\n", 1542 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1543 if (!error) { 1544 if (mode >= ATA_UDMA0) { 1545 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1546 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]); 1547 } 1548 else if (mode >= ATA_WDMA0) { 1549 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1550 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]); 1551 } 1552 else { 1553 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1554 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]); 1555 } 1556 atadev->mode = mode; 1557 } 1558 } 1559 1560 1561 /* 1562 * Cypress chipset support functions 1563 */ 1564 int 1565 ata_cypress_ident(device_t dev) 1566 { 1567 struct ata_pci_controller *ctlr = device_get_softc(dev); 1568 1569 /* 1570 * the Cypress chip is a mess, it contains two ATA functions, but 1571 * both channels are visible on the first one. 1572 * simply ignore the second function for now, as the right 1573 * solution (ignoring the second channel on the first function) 1574 * doesn't work with the crappy ATA interrupt setup on the alpha. 1575 */ 1576 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 && 1577 pci_get_function(dev) == 1 && 1578 pci_get_subclass(dev) == PCIS_STORAGE_IDE) { 1579 device_set_desc(dev, "Cypress 82C693 ATA controller"); 1580 ctlr->chipinit = ata_cypress_chipinit; 1581 return 0; 1582 } 1583 return ENXIO; 1584 } 1585 1586 static int 1587 ata_cypress_chipinit(device_t dev) 1588 { 1589 struct ata_pci_controller *ctlr = device_get_softc(dev); 1590 1591 if (ata_setup_interrupt(dev)) 1592 return ENXIO; 1593 1594 ctlr->setmode = ata_cypress_setmode; 1595 return 0; 1596 } 1597 1598 static void 1599 ata_cypress_setmode(device_t dev, int mode) 1600 { 1601 device_t gparent = GRANDPARENT(dev); 1602 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1603 struct ata_device *atadev = device_get_softc(dev); 1604 int error; 1605 1606 mode = ata_limit_mode(dev, mode, ATA_WDMA2); 1607 1608 /* XXX SOS missing WDMA0+1 + PIO modes */ 1609 if (mode == ATA_WDMA2) { 1610 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1611 if (bootverbose) 1612 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n", 1613 error ? "FAILURE " : ""); 1614 if (!error) { 1615 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2); 1616 atadev->mode = mode; 1617 return; 1618 } 1619 } 1620 /* we could set PIO mode timings, but we assume the BIOS did that */ 1621 } 1622 1623 1624 /* 1625 * HighPoint chipset support functions 1626 */ 1627 int 1628 ata_highpoint_ident(device_t dev) 1629 { 1630 struct ata_pci_controller *ctlr = device_get_softc(dev); 1631 struct ata_chip_id *idx; 1632 static struct ata_chip_id ids[] = 1633 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" }, 1634 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" }, 1635 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1636 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" }, 1637 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1638 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" }, 1639 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" }, 1640 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" }, 1641 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" }, 1642 { 0, 0, 0, 0, 0, 0}}; 1643 char buffer[64]; 1644 1645 if (!(idx = ata_match_chip(dev, ids))) 1646 return ENXIO; 1647 1648 strcpy(buffer, "HighPoint "); 1649 strcat(buffer, idx->text); 1650 if (idx->cfg1 == HPT374) { 1651 if (pci_get_function(dev) == 0) 1652 strcat(buffer, " (channel 0+1)"); 1653 if (pci_get_function(dev) == 1) 1654 strcat(buffer, " (channel 2+3)"); 1655 } 1656 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 1657 device_set_desc_copy(dev, buffer); 1658 ctlr->chip = idx; 1659 ctlr->chipinit = ata_highpoint_chipinit; 1660 return 0; 1661 } 1662 1663 static int 1664 ata_highpoint_chipinit(device_t dev) 1665 { 1666 struct ata_pci_controller *ctlr = device_get_softc(dev); 1667 1668 if (ata_setup_interrupt(dev)) 1669 return ENXIO; 1670 1671 if (ctlr->chip->cfg2 == HPTOLD) { 1672 /* disable interrupt prediction */ 1673 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 1674 } 1675 else { 1676 /* disable interrupt prediction */ 1677 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 1678 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 1679 1680 /* enable interrupts */ 1681 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 1682 1683 /* set clocks etc */ 1684 if (ctlr->chip->cfg1 < HPT372) 1685 pci_write_config(dev, 0x5b, 0x22, 1); 1686 else 1687 pci_write_config(dev, 0x5b, 1688 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 1689 } 1690 ctlr->allocate = ata_highpoint_allocate; 1691 ctlr->setmode = ata_highpoint_setmode; 1692 return 0; 1693 } 1694 1695 static int 1696 ata_highpoint_allocate(device_t dev) 1697 { 1698 struct ata_channel *ch = device_get_softc(dev); 1699 1700 /* setup the usual register normal pci style */ 1701 if (ata_pci_allocate(dev)) 1702 return ENXIO; 1703 1704 ch->flags |= ATA_ALWAYS_DMASTAT; 1705 return 0; 1706 } 1707 1708 static void 1709 ata_highpoint_setmode(device_t dev, int mode) 1710 { 1711 device_t gparent = GRANDPARENT(dev); 1712 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1713 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1714 struct ata_device *atadev = device_get_softc(dev); 1715 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1716 int error; 1717 u_int32_t timings33[][4] = { 1718 /* HPT366 HPT370 HPT372 HPT374 mode */ 1719 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */ 1720 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */ 1721 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */ 1722 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */ 1723 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */ 1724 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */ 1725 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */ 1726 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */ 1727 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */ 1728 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */ 1729 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */ 1730 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */ 1731 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */ 1732 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */ 1733 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */ 1734 }; 1735 1736 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1737 1738 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev)) 1739 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1740 1741 mode = ata_highpoint_check_80pin(dev, mode); 1742 1743 /* 1744 * most if not all HPT chips cant really handle that the device is 1745 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to 1746 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance 1747 */ 1748 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 1749 ata_limit_mode(dev, mode, ATA_UDMA5)); 1750 if (bootverbose) 1751 device_printf(dev, "%ssetting %s on HighPoint chip\n", 1752 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1753 if (!error) 1754 pci_write_config(gparent, 0x40 + (devno << 2), 1755 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 1756 atadev->mode = mode; 1757 } 1758 1759 static int 1760 ata_highpoint_check_80pin(device_t dev, int mode) 1761 { 1762 device_t gparent = GRANDPARENT(dev); 1763 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1764 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1765 u_int8_t reg, val, res; 1766 1767 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) { 1768 reg = ch->unit ? 0x57 : 0x53; 1769 val = pci_read_config(gparent, reg, 1); 1770 pci_write_config(gparent, reg, val | 0x80, 1); 1771 } 1772 else { 1773 reg = 0x5b; 1774 val = pci_read_config(gparent, reg, 1); 1775 pci_write_config(gparent, reg, val & 0xfe, 1); 1776 } 1777 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2); 1778 pci_write_config(gparent, reg, val, 1); 1779 1780 if (mode > ATA_UDMA2 && res) { 1781 ata_print_cable(dev, "controller"); 1782 mode = ATA_UDMA2; 1783 } 1784 return mode; 1785 } 1786 1787 1788 /* 1789 * Intel chipset support functions 1790 */ 1791 int 1792 ata_intel_ident(device_t dev) 1793 { 1794 struct ata_pci_controller *ctlr = device_get_softc(dev); 1795 struct ata_chip_id *idx; 1796 static struct ata_chip_id ids[] = 1797 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" }, 1798 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" }, 1799 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1800 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1801 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1802 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" }, 1803 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1804 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1805 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1806 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1807 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1808 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1809 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1810 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1811 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" }, 1812 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1813 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1814 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" }, 1815 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1816 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1817 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" }, 1818 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1819 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1820 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" }, 1821 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" }, 1822 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1823 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1824 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1825 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1826 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1827 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1828 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" }, 1829 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1830 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1831 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1832 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1833 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1834 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1835 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1836 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1837 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1838 { ATA_I82801HBM_S1, 0, 0, 0x00, ATA_SA300, "ICH8M" }, 1839 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1840 { ATA_I82801HBM_S3, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1841 { ATA_I82801IB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1842 { ATA_I82801IB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1843 { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1844 { ATA_I82801IB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1845 { ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1846 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" }, 1847 { 0, 0, 0, 0, 0, 0}}; 1848 char buffer[64]; 1849 1850 if (!(idx = ata_match_chip(dev, ids))) 1851 return ENXIO; 1852 1853 ksprintf(buffer, "Intel %s %s controller", 1854 idx->text, ata_mode2str(idx->max_dma)); 1855 device_set_desc_copy(dev, buffer); 1856 ctlr->chip = idx; 1857 ctlr->chipinit = ata_intel_chipinit; 1858 return 0; 1859 } 1860 1861 static int 1862 ata_intel_chipinit(device_t dev) 1863 { 1864 struct ata_pci_controller *ctlr = device_get_softc(dev); 1865 1866 if (ata_setup_interrupt(dev)) 1867 return ENXIO; 1868 1869 /* good old PIIX needs special treatment (not implemented) */ 1870 if (ctlr->chip->chipid == ATA_I82371FB) { 1871 ctlr->setmode = ata_intel_old_setmode; 1872 } 1873 1874 /* the intel 31244 needs special care if in DPA mode */ 1875 else if (ctlr->chip->chipid == ATA_I31244) { 1876 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 1877 ctlr->r_type2 = SYS_RES_MEMORY; 1878 ctlr->r_rid2 = PCIR_BAR(0); 1879 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1880 &ctlr->r_rid2, 1881 RF_ACTIVE))) { 1882 ata_teardown_interrupt(dev); 1883 return ENXIO; 1884 } 1885 ctlr->channels = 4; 1886 ctlr->allocate = ata_intel_31244_allocate; 1887 ctlr->reset = ata_intel_31244_reset; 1888 } 1889 ctlr->setmode = ata_sata_setmode; 1890 } 1891 1892 /* non SATA intel chips goes here */ 1893 else if (ctlr->chip->max_dma < ATA_SA150) { 1894 ctlr->allocate = ata_intel_allocate; 1895 ctlr->setmode = ata_intel_new_setmode; 1896 } 1897 1898 /* SATA parts can be either compat or AHCI */ 1899 else { 1900 /* force all ports active "the legacy way" */ 1901 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2); 1902 1903 ctlr->allocate = ata_intel_allocate; 1904 ctlr->reset = ata_intel_reset; 1905 1906 /* 1907 * if we have AHCI capability and BAR(5) as a memory resource 1908 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode 1909 */ 1910 if ((ctlr->chip->cfg1 == AHCI) && 1911 (pci_read_config(dev, 0x90, 1) & 0xc0) && 1912 (ata_ahci_chipinit(dev) != ENXIO)) 1913 return 0; 1914 1915 /* if BAR(5) is IO it should point to SATA interface registers */ 1916 ctlr->r_type2 = SYS_RES_IOPORT; 1917 ctlr->r_rid2 = PCIR_BAR(5); 1918 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1919 &ctlr->r_rid2, RF_ACTIVE))) 1920 ctlr->setmode = ata_intel_sata_setmode; 1921 else 1922 ctlr->setmode = ata_sata_setmode; 1923 1924 /* enable PCI interrupt */ 1925 pci_write_config(dev, PCIR_COMMAND, 1926 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1927 } 1928 return 0; 1929 } 1930 1931 static int 1932 ata_intel_allocate(device_t dev) 1933 { 1934 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1935 struct ata_channel *ch = device_get_softc(dev); 1936 1937 /* setup the usual register normal pci style */ 1938 if (ata_pci_allocate(dev)) 1939 return ENXIO; 1940 1941 /* if r_res2 is valid it points to SATA interface registers */ 1942 if (ctlr->r_res2) { 1943 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 1944 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 1945 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 1946 ch->r_io[ATA_IDX_DATA].offset = 0x04; 1947 } 1948 1949 ch->flags |= ATA_ALWAYS_DMASTAT; 1950 return 0; 1951 } 1952 1953 static void 1954 ata_intel_reset(device_t dev) 1955 { 1956 device_t parent = device_get_parent(dev); 1957 struct ata_pci_controller *ctlr = device_get_softc(parent); 1958 struct ata_channel *ch = device_get_softc(dev); 1959 int mask, timeout; 1960 1961 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */ 1962 if (ctlr->chip->cfg1) { 1963 mask = (0x0005 << ch->unit); 1964 } 1965 else { 1966 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */ 1967 if (pci_read_config(parent, 0x90, 1) & 0x04) 1968 mask = 0x0003; 1969 else { 1970 mask = (0x0001 << ch->unit); 1971 /* XXX SOS should be in intel_allocate if we grow it */ 1972 ch->flags |= ATA_NO_SLAVE; 1973 } 1974 } 1975 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2); 1976 DELAY(10); 1977 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2); 1978 1979 /* wait up to 1 sec for "connect well" */ 1980 for (timeout = 0; timeout < 100 ; timeout++) { 1981 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) && 1982 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 1983 break; 1984 ata_udelay(10000); 1985 } 1986 ata_generic_reset(dev); 1987 } 1988 1989 static void 1990 ata_intel_old_setmode(device_t dev, int mode) 1991 { 1992 /* NOT YET */ 1993 } 1994 1995 static void 1996 ata_intel_new_setmode(device_t dev, int mode) 1997 { 1998 device_t gparent = GRANDPARENT(dev); 1999 struct ata_pci_controller *ctlr = device_get_softc(gparent); 2000 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2001 struct ata_device *atadev = device_get_softc(dev); 2002 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2003 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4); 2004 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1); 2005 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1); 2006 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2); 2007 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2); 2008 u_int32_t mask40 = 0, new40 = 0; 2009 u_int8_t mask44 = 0, new44 = 0; 2010 int error; 2011 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, 2012 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 }; 2013 /* PIO0 PIO1 PIO2 PIO3 PIO4 WDMA0 WDMA1 WDMA2 */ 2014 /* UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 UDMA5 UDMA6 */ 2015 2016 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 2017 2018 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { 2019 ata_print_cable(dev, "controller"); 2020 mode = ATA_UDMA2; 2021 } 2022 2023 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2024 2025 if (bootverbose) 2026 device_printf(dev, "%ssetting %s on %s chip\n", 2027 (error) ? "FAILURE " : "", 2028 ata_mode2str(mode), ctlr->chip->text); 2029 if (error) 2030 return; 2031 2032 /* 2033 * reg48: 1 bit per (primary drive 0, primary drive 1, secondary 2034 * drive 0, secondary drive 1) 2035 * 2036 * 0 Disable Ultra DMA mode 2037 * 1 Enable Ultra DMA mode 2038 * 2039 * reg4a: 4 bits per (primary drive 0, primary drive 1, secondary 2040 * drive 0, secondary drive 1). 2041 * 0000 UDMA mode 0 2042 * 0001 UDMA mode 1, 3, 5 2043 * 0010 UDMA mode 2, 4, reserved 2044 * 0011 reserved 2045 * (top two bits for each drive reserved) 2046 */ 2047 #if 0 2048 device_printf(dev, 2049 "regs before 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 2050 reg40, reg44, reg48 ,reg4a, reg54); 2051 #endif 2052 reg48 &= ~(0x0001 << devno); 2053 reg4a &= ~(0x3 << (devno << 2)); 2054 if (mode >= ATA_UDMA0) { 2055 reg48 |= 0x0001 << devno; 2056 if (mode > ATA_UDMA0) 2057 reg4a |= (1 + !(mode & 0x01)) << (devno << 2); 2058 } 2059 pci_write_config(gparent, 0x48, reg48, 2); 2060 pci_write_config(gparent, 0x4a, reg4a, 2); 2061 2062 /* 2063 * reg54: 2064 * 2065 * 32:20 reserved 2066 * 19:18 Secondary ATA signal mode 2067 * 17:16 Primary ATA signal mode 2068 * 00 = Normal (enabled) 2069 * 01 = Tri-state (disabled) 2070 * 10 = Drive Low (disabled) 2071 * 11 = Reserved 2072 * 2073 * 15 Secondary drive 1 - Base Clock 2074 * 14 Secondary drive 0 - Base Clock 2075 * 13 Primary drive 1 - Base Clock 2076 * 12 Primary drive 0 - Base Clock 2077 * 0 = Select 33 MHz clock 2078 * 1 = Select 100 Mhz clock 2079 * 2080 * 11 Reserved 2081 * 10 Vendor specific (set by BIOS?) 2082 * 09:08 Reserved 2083 * 2084 * 07 Secondary drive 1 - Cable Type 2085 * 06 Secondary drive 0 - Cable Type 2086 * 05 Primary drive 1 - Cable Type 2087 * 04 Primary drive 0 - Cable Type 2088 * 0 = 40 Conductor 2089 * 1 = 80 Conductor (or high speed cable) 2090 * 2091 * 03 Secondary drive 1 - Select 33/66 clock 2092 * 02 Secondary drive 0 - Select 33/66 clock 2093 * 01 Primary drive 1 - Select 33/66 clock 2094 * 00 Primary drive 0 - Select 33/66 clock 2095 * 0 = Select 33 MHz 2096 * 1 = Select 66 MHz 2097 * 2098 * It is unclear what this should be set to when operating 2099 * in 100MHz mode. 2100 * 2101 * NOTE: UDMA2 = 33 MHz 2102 * UDMA3 = 40 MHz (?) - unsupported 2103 * UDMA4 = 66 MHz 2104 * UDMA5 = 100 MHz 2105 * UDMA6 = 133 Mhz 2106 */ 2107 reg54 |= 0x0400; /* set vendor specific bit */ 2108 reg54 &= ~((0x1 << devno) | (0x1000 << devno)); 2109 2110 if (mode >= ATA_UDMA5) 2111 reg54 |= (0x1000 << devno); 2112 else if (mode >= ATA_UDMA3) /* XXX should this be ATA_UDMA3 or 4? */ 2113 reg54 |= (0x1 << devno); 2114 2115 pci_write_config(gparent, 0x54, reg54, 2); 2116 2117 /* 2118 * Reg40 (32 bits... well, actually two 16 bit registers) 2119 * 2120 * Primary channel bits 15:00, Secondary channel bits 31:00. Note 2121 * that slave timings are handled in register 44. 2122 * 2123 * 15 ATA Decode Enable (R/W) 1 = enable decoding of I/O ranges 2124 * 2125 * 14 Slave ATA Timing Register Enable (R/W) 2126 * 2127 * 13:12 IORDY Sample Mode 2128 * 00 PIO-0 2129 * 01 PIO-2, SW-2 2130 * 10 PIO-3, PIO-4, MW-1, MW-2 2131 * 11 Reserved 2132 * 2133 * 11:10 Reserved 2134 * 2135 * 09:08 Recovery Mode 2136 * 00 PIO-0, PIO-2, SW-2 2137 * 01 PIO-3, MW-1 2138 * 10 Reserved 2139 * 11 PIO-4, MW-2 2140 * 2141 * 07:04 Secondary Device Control Bits 2142 * 03:00 Primary Device Control Bits 2143 * 2144 * bit 3 DMA Timing Enable 2145 * 2146 * bit 2 Indicate Presence of ATA(1) or ATAPI(0) device 2147 * 2148 * bit 1 Enable IORDY sample point capability for PIO 2149 * xfers. Always enabled for PIO4 and PIO3, enabled 2150 * for PIO2 if indicated by the device, and otherwise 2151 * probably should be 0. 2152 * 2153 * bit 0 Fast Drive Timing Enable. Enables faster then PIO-0 2154 * timing modes. 2155 */ 2156 2157 /* 2158 * Modify reg40 according to the table 2159 */ 2160 if (atadev->unit == ATA_MASTER) { 2161 mask40 = 0x3300; 2162 new40 = timings[ata_mode2idx(mode)] << 8; 2163 } 2164 else { 2165 mask44 = 0x0f; 2166 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) | 2167 (timings[ata_mode2idx(mode)] & 0x03); 2168 } 2169 2170 /* 2171 * Slave ATA timing register enable 2172 */ 2173 mask40 |= 0x4000; 2174 new40 |= 0x4000; 2175 2176 /* 2177 * Device control bits 3:0 for master, 7:4 for slave. 2178 * 2179 * bit3 DMA Timing enable. 2180 * bit2 Indicate presence of ATA(1) or ATAPI(0) device, set accordingly 2181 * bit1 Enable IORDY sample point capability for PIO xfers. Always 2182 * enabled for PIO4 and PIO3, enabled for PIO2 if indicated by 2183 * the device, and otherwise should be 0. 2184 * bit0 Fast Drive Timing Enable. Enable faster then PIO-0 timing modes. 2185 * 2186 * Set to: 0 x 1 1 2187 */ 2188 2189 if (atadev->unit == ATA_MASTER) { 2190 mask40 |= 0x0F; 2191 new40 |= 0x03; 2192 if (!ata_atapi(dev)) 2193 new40 |= 0x04; 2194 } else { 2195 mask40 |= 0xF0; 2196 new40 |= 0x30; 2197 if (!ata_atapi(dev)) 2198 new40 |= 0x40; 2199 } 2200 /* 2201 reg40 &= ~0x00ff00ff; 2202 reg40 |= 0x40774077; 2203 */ 2204 2205 /* 2206 * Primary or Secondary controller 2207 */ 2208 if (ch->unit) { 2209 mask40 <<= 16; 2210 new40 <<= 16; 2211 mask44 <<= 4; 2212 new44 <<= 4; 2213 } 2214 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4); 2215 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1); 2216 2217 #if 0 2218 reg40 = pci_read_config(gparent, 0x40, 4); 2219 reg44 = pci_read_config(gparent, 0x44, 1); 2220 reg48 = pci_read_config(gparent, 0x48, 1); 2221 reg4a = pci_read_config(gparent, 0x4a, 2); 2222 reg54 = pci_read_config(gparent, 0x54, 2); 2223 device_printf(dev, 2224 "regs after 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 2225 reg40, reg44, reg48 ,reg4a, reg54); 2226 #endif 2227 2228 atadev->mode = mode; 2229 } 2230 2231 static void 2232 ata_intel_sata_setmode(device_t dev, int mode) 2233 { 2234 struct ata_device *atadev = device_get_softc(dev); 2235 2236 if (atadev->param.satacapabilities != 0x0000 && 2237 atadev->param.satacapabilities != 0xffff) { 2238 2239 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2240 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2241 2242 /* on some drives we need to set the transfer mode */ 2243 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 2244 ata_limit_mode(dev, mode, ATA_UDMA6)); 2245 2246 /* set ATA_SSTATUS register offset */ 2247 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100); 2248 2249 /* query SATA STATUS for the speed */ 2250 if ((ATA_IDX_INL(ch, ATA_IDX_DATA) & ATA_SS_CONWELL_MASK) == 2251 ATA_SS_CONWELL_GEN2) 2252 atadev->mode = ATA_SA300; 2253 else 2254 atadev->mode = ATA_SA150; 2255 } 2256 else { 2257 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 2258 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2259 atadev->mode = mode; 2260 } 2261 } 2262 2263 static int 2264 ata_intel_31244_allocate(device_t dev) 2265 { 2266 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2267 struct ata_channel *ch = device_get_softc(dev); 2268 int i; 2269 int ch_offset; 2270 2271 ch_offset = 0x200 + ch->unit * 0x200; 2272 2273 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 2274 ch->r_io[i].res = ctlr->r_res2; 2275 2276 /* setup ATA registers */ 2277 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 2278 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 2279 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 2280 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 2281 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 2282 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 2283 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 2284 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 2285 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 2286 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 2287 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 2288 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 2289 2290 /* setup DMA registers */ 2291 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 2292 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 2293 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 2294 2295 /* setup SATA registers */ 2296 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 2297 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 2298 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 2299 2300 ch->flags |= ATA_NO_SLAVE; 2301 ata_pci_hw(dev); 2302 ch->hw.status = ata_intel_31244_status; 2303 ch->hw.command = ata_intel_31244_command; 2304 2305 /* enable PHY state change interrupt */ 2306 ATA_OUTL(ctlr->r_res2, 0x4, 2307 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 2308 return 0; 2309 } 2310 2311 static int 2312 ata_intel_31244_status(device_t dev) 2313 { 2314 /* do we have any PHY events ? */ 2315 ata_sata_phy_check_events(dev); 2316 2317 /* any drive action to take care of ? */ 2318 return ata_pci_status(dev); 2319 } 2320 2321 static int 2322 ata_intel_31244_command(struct ata_request *request) 2323 { 2324 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2325 struct ata_device *atadev = device_get_softc(request->dev); 2326 u_int64_t lba; 2327 2328 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 2329 return (ata_generic_command(request)); 2330 2331 lba = request->u.ata.lba; 2332 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 2333 /* enable interrupt */ 2334 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 2335 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 2336 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 2337 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff)); 2338 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) | 2339 ((lba >> 8) & 0x00ff)); 2340 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) | 2341 ((lba >> 16) & 0x00ff)); 2342 2343 /* issue command to controller */ 2344 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 2345 2346 return 0; 2347 } 2348 2349 static void 2350 ata_intel_31244_reset(device_t dev) 2351 { 2352 if (ata_sata_phy_reset(dev)) 2353 ata_generic_reset(dev); 2354 } 2355 2356 2357 /* 2358 * Integrated Technology Express Inc. (ITE) chipset support functions 2359 */ 2360 int 2361 ata_ite_ident(device_t dev) 2362 { 2363 struct ata_pci_controller *ctlr = device_get_softc(dev); 2364 struct ata_chip_id *idx; 2365 static struct ata_chip_id ids[] = 2366 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 2367 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 2368 { 0, 0, 0, 0, 0, 0}}; 2369 char buffer[64]; 2370 2371 if (!(idx = ata_match_chip(dev, ids))) 2372 return ENXIO; 2373 2374 ksprintf(buffer, "ITE %s %s controller", 2375 idx->text, ata_mode2str(idx->max_dma)); 2376 device_set_desc_copy(dev, buffer); 2377 ctlr->chip = idx; 2378 ctlr->chipinit = ata_ite_chipinit; 2379 return 0; 2380 } 2381 2382 static int 2383 ata_ite_chipinit(device_t dev) 2384 { 2385 struct ata_pci_controller *ctlr = device_get_softc(dev); 2386 2387 if (ata_setup_interrupt(dev)) 2388 return ENXIO; 2389 2390 ctlr->setmode = ata_ite_setmode; 2391 2392 /* set PCI mode and 66Mhz reference clock */ 2393 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 2394 2395 /* set default active & recover timings */ 2396 pci_write_config(dev, 0x54, 0x31, 1); 2397 pci_write_config(dev, 0x56, 0x31, 1); 2398 return 0; 2399 } 2400 2401 static void 2402 ata_ite_setmode(device_t dev, int mode) 2403 { 2404 device_t gparent = GRANDPARENT(dev); 2405 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2406 struct ata_device *atadev = device_get_softc(dev); 2407 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2408 int error; 2409 2410 /* correct the mode for what the HW supports */ 2411 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2412 2413 /* check the CBLID bits for 80 conductor cable detection */ 2414 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) & 2415 (ch->unit ? (1<<3) : (1<<2)))) { 2416 ata_print_cable(dev, "controller"); 2417 mode = ATA_UDMA2; 2418 } 2419 2420 /* set the wanted mode on the device */ 2421 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2422 2423 if (bootverbose) 2424 device_printf(dev, "%s setting %s on ITE8212F chip\n", 2425 (error) ? "failed" : "success", ata_mode2str(mode)); 2426 2427 /* if the device accepted the mode change, setup the HW accordingly */ 2428 if (!error) { 2429 if (mode >= ATA_UDMA0) { 2430 u_int8_t udmatiming[] = 2431 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 2432 2433 /* enable UDMA mode */ 2434 pci_write_config(gparent, 0x50, 2435 pci_read_config(gparent, 0x50, 1) & 2436 ~(1 << (devno + 3)), 1); 2437 2438 /* set UDMA timing */ 2439 pci_write_config(gparent, 2440 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit), 2441 udmatiming[mode & ATA_MODE_MASK], 1); 2442 } 2443 else { 2444 u_int8_t chtiming[] = 2445 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 2446 2447 /* disable UDMA mode */ 2448 pci_write_config(gparent, 0x50, 2449 pci_read_config(gparent, 0x50, 1) | 2450 (1 << (devno + 3)), 1); 2451 2452 /* set active and recover timing (shared between master & slave) */ 2453 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) < 2454 chtiming[ata_mode2idx(mode)]) 2455 pci_write_config(gparent, 0x54 + (ch->unit << 2), 2456 chtiming[ata_mode2idx(mode)], 1); 2457 } 2458 atadev->mode = mode; 2459 } 2460 } 2461 2462 2463 /* 2464 * JMicron chipset support functions 2465 */ 2466 int 2467 ata_jmicron_ident(device_t dev) 2468 { 2469 struct ata_pci_controller *ctlr = device_get_softc(dev); 2470 struct ata_chip_id *idx; 2471 static struct ata_chip_id ids[] = 2472 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" }, 2473 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" }, 2474 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" }, 2475 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" }, 2476 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" }, 2477 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" }, 2478 { 0, 0, 0, 0, 0, 0}}; 2479 char buffer[64]; 2480 2481 if (!(idx = ata_match_chip(dev, ids))) 2482 return ENXIO; 2483 2484 if ((pci_read_config(dev, 0xdf, 1) & 0x40) && 2485 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1))) 2486 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2487 idx->text, ata_mode2str(ATA_UDMA6)); 2488 else 2489 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2490 idx->text, ata_mode2str(idx->max_dma)); 2491 device_set_desc_copy(dev, buffer); 2492 ctlr->chip = idx; 2493 ctlr->chipinit = ata_jmicron_chipinit; 2494 return 0; 2495 } 2496 2497 static int 2498 ata_jmicron_chipinit(device_t dev) 2499 { 2500 struct ata_pci_controller *ctlr = device_get_softc(dev); 2501 int error; 2502 2503 if (ata_setup_interrupt(dev)) 2504 return ENXIO; 2505 2506 /* do we have multiple PCI functions ? */ 2507 if (pci_read_config(dev, 0xdf, 1) & 0x40) { 2508 /* are we on the AHCI part ? */ 2509 if (ata_ahci_chipinit(dev) != ENXIO) 2510 return 0; 2511 2512 /* otherwise we are on the PATA part */ 2513 ctlr->allocate = ata_pci_allocate; 2514 ctlr->reset = ata_generic_reset; 2515 ctlr->dmainit = ata_pci_dmainit; 2516 ctlr->setmode = ata_jmicron_setmode; 2517 ctlr->channels = ctlr->chip->cfg2; 2518 } 2519 else { 2520 /* set controller configuration to a combined setup we support */ 2521 pci_write_config(dev, 0x40, 0x80c0a131, 4); 2522 pci_write_config(dev, 0x80, 0x01200000, 4); 2523 2524 if ((error = ata_ahci_chipinit(dev))) { 2525 ata_teardown_interrupt(dev); 2526 return error; 2527 } 2528 2529 ctlr->allocate = ata_jmicron_allocate; 2530 ctlr->reset = ata_jmicron_reset; 2531 ctlr->dmainit = ata_jmicron_dmainit; 2532 ctlr->setmode = ata_jmicron_setmode; 2533 2534 /* set the number of HW channels */ 2535 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2; 2536 } 2537 return 0; 2538 } 2539 2540 static int 2541 ata_jmicron_allocate(device_t dev) 2542 { 2543 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2544 struct ata_channel *ch = device_get_softc(dev); 2545 int error; 2546 2547 if (ch->unit >= ctlr->chip->cfg1) { 2548 ch->unit -= ctlr->chip->cfg1; 2549 error = ata_pci_allocate(dev); 2550 ch->unit += ctlr->chip->cfg1; 2551 } 2552 else 2553 error = ata_ahci_allocate(dev); 2554 return error; 2555 } 2556 2557 static void 2558 ata_jmicron_reset(device_t dev) 2559 { 2560 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2561 struct ata_channel *ch = device_get_softc(dev); 2562 2563 if (ch->unit >= ctlr->chip->cfg1) 2564 ata_generic_reset(dev); 2565 else 2566 ata_ahci_reset(dev); 2567 } 2568 2569 static void 2570 ata_jmicron_dmainit(device_t dev) 2571 { 2572 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2573 struct ata_channel *ch = device_get_softc(dev); 2574 2575 if (ch->unit >= ctlr->chip->cfg1) 2576 ata_pci_dmainit(dev); 2577 else 2578 ata_ahci_dmainit(dev); 2579 } 2580 2581 static void 2582 ata_jmicron_setmode(device_t dev, int mode) 2583 { 2584 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 2585 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2586 2587 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) { 2588 struct ata_device *atadev = device_get_softc(dev); 2589 2590 /* check for 80pin cable present */ 2591 if (pci_read_config(dev, 0x40, 1) & 0x08) 2592 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 2593 else 2594 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2595 2596 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2597 atadev->mode = mode; 2598 } 2599 else 2600 ata_sata_setmode(dev, mode); 2601 } 2602 2603 2604 /* 2605 * Marvell chipset support functions 2606 */ 2607 #define ATA_MV_HOST_BASE(ch) \ 2608 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000) 2609 #define ATA_MV_EDMA_BASE(ch) \ 2610 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000) 2611 2612 struct ata_marvell_response { 2613 u_int16_t tag; 2614 u_int8_t edma_status; 2615 u_int8_t dev_status; 2616 u_int32_t timestamp; 2617 }; 2618 2619 struct ata_marvell_dma_prdentry { 2620 u_int32_t addrlo; 2621 u_int32_t count; 2622 u_int32_t addrhi; 2623 u_int32_t reserved; 2624 }; 2625 2626 int 2627 ata_marvell_ident(device_t dev) 2628 { 2629 struct ata_pci_controller *ctlr = device_get_softc(dev); 2630 struct ata_chip_id *idx; 2631 static struct ata_chip_id ids[] = 2632 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" }, 2633 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" }, 2634 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" }, 2635 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" }, 2636 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" }, 2637 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" }, 2638 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" }, 2639 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" }, 2640 { 0, 0, 0, 0, 0, 0}}; 2641 char buffer[64]; 2642 2643 if (!(idx = ata_match_chip(dev, ids))) 2644 return ENXIO; 2645 2646 ksprintf(buffer, "Marvell %s %s controller", 2647 idx->text, ata_mode2str(idx->max_dma)); 2648 device_set_desc_copy(dev, buffer); 2649 ctlr->chip = idx; 2650 switch (ctlr->chip->cfg2) { 2651 case MV50XX: 2652 case MV60XX: 2653 ctlr->chipinit = ata_marvell_edma_chipinit; 2654 break; 2655 case MV61XX: 2656 ctlr->chipinit = ata_marvell_pata_chipinit; 2657 break; 2658 } 2659 return 0; 2660 } 2661 2662 static int 2663 ata_marvell_pata_chipinit(device_t dev) 2664 { 2665 struct ata_pci_controller *ctlr = device_get_softc(dev); 2666 2667 if (ata_setup_interrupt(dev)) 2668 return ENXIO; 2669 2670 ctlr->allocate = ata_marvell_pata_allocate; 2671 ctlr->setmode = ata_marvell_pata_setmode; 2672 ctlr->channels = ctlr->chip->cfg1; 2673 return 0; 2674 } 2675 2676 static int 2677 ata_marvell_pata_allocate(device_t dev) 2678 { 2679 struct ata_channel *ch = device_get_softc(dev); 2680 2681 /* setup the usual register normal pci style */ 2682 if (ata_pci_allocate(dev)) 2683 return ENXIO; 2684 2685 /* dont use 32 bit PIO transfers */ 2686 ch->flags |= ATA_USE_16BIT; 2687 2688 return 0; 2689 } 2690 2691 static void 2692 ata_marvell_pata_setmode(device_t dev, int mode) 2693 { 2694 device_t gparent = GRANDPARENT(dev); 2695 struct ata_pci_controller *ctlr = device_get_softc(gparent); 2696 struct ata_device *atadev = device_get_softc(dev); 2697 2698 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 2699 mode = ata_check_80pin(dev, mode); 2700 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2701 atadev->mode = mode; 2702 } 2703 2704 static int 2705 ata_marvell_edma_chipinit(device_t dev) 2706 { 2707 struct ata_pci_controller *ctlr = device_get_softc(dev); 2708 2709 if (ata_setup_interrupt(dev)) 2710 return ENXIO; 2711 2712 ctlr->r_type1 = SYS_RES_MEMORY; 2713 ctlr->r_rid1 = PCIR_BAR(0); 2714 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 2715 &ctlr->r_rid1, RF_ACTIVE))) { 2716 ata_teardown_interrupt(dev); 2717 return ENXIO; 2718 } 2719 2720 /* mask all host controller interrupts */ 2721 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000); 2722 2723 /* mask all PCI interrupts */ 2724 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000); 2725 2726 ctlr->allocate = ata_marvell_edma_allocate; 2727 ctlr->reset = ata_marvell_edma_reset; 2728 ctlr->dmainit = ata_marvell_edma_dmainit; 2729 ctlr->setmode = ata_sata_setmode; 2730 ctlr->channels = ctlr->chip->cfg1; 2731 2732 /* clear host controller interrupts */ 2733 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000); 2734 if (ctlr->chip->cfg1 > 4) 2735 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000); 2736 2737 /* clear PCI interrupts */ 2738 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000); 2739 2740 /* unmask PCI interrupts we want */ 2741 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff); 2742 2743 /* unmask host controller interrupts we want */ 2744 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ | 2745 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25)); 2746 2747 /* enable PCI interrupt */ 2748 pci_write_config(dev, PCIR_COMMAND, 2749 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 2750 return 0; 2751 } 2752 2753 static int 2754 ata_marvell_edma_allocate(device_t dev) 2755 { 2756 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2757 struct ata_channel *ch = device_get_softc(dev); 2758 u_int64_t work = ch->dma->work_bus; 2759 int i; 2760 2761 /* clear work area */ 2762 bzero(ch->dma->work, 1024+256); 2763 2764 /* set legacy ATA resources */ 2765 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 2766 ch->r_io[i].res = ctlr->r_res1; 2767 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch); 2768 } 2769 ch->r_io[ATA_CONTROL].res = ctlr->r_res1; 2770 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch); 2771 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1; 2772 ata_default_registers(dev); 2773 2774 /* set SATA resources */ 2775 switch (ctlr->chip->cfg2) { 2776 case MV50XX: 2777 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2778 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch); 2779 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2780 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch); 2781 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2782 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch); 2783 break; 2784 case MV60XX: 2785 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2786 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch); 2787 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2788 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch); 2789 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2790 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch); 2791 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1; 2792 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch); 2793 break; 2794 } 2795 2796 ch->flags |= ATA_NO_SLAVE; 2797 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */ 2798 ata_generic_hw(dev); 2799 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction; 2800 ch->hw.end_transaction = ata_marvell_edma_end_transaction; 2801 ch->hw.status = ata_marvell_edma_status; 2802 2803 /* disable the EDMA machinery */ 2804 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2805 DELAY(100000); /* SOS should poll for disabled */ 2806 2807 /* set configuration to non-queued 128b read transfers stop on error */ 2808 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13)); 2809 2810 /* request queue base high */ 2811 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32); 2812 2813 /* request queue in ptr */ 2814 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2815 2816 /* request queue out ptr */ 2817 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0); 2818 2819 /* response queue base high */ 2820 work += 1024; 2821 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32); 2822 2823 /* response queue in ptr */ 2824 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0); 2825 2826 /* response queue out ptr */ 2827 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2828 2829 /* clear SATA error register */ 2830 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 2831 2832 /* clear any outstanding error interrupts */ 2833 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2834 2835 /* unmask all error interrupts */ 2836 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 2837 2838 /* enable EDMA machinery */ 2839 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2840 return 0; 2841 } 2842 2843 static int 2844 ata_marvell_edma_status(device_t dev) 2845 { 2846 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2847 struct ata_channel *ch = device_get_softc(dev); 2848 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60); 2849 int shift = (ch->unit << 1) + (ch->unit > 3); 2850 2851 if (cause & (1 << shift)) { 2852 2853 /* clear interrupt(s) */ 2854 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2855 2856 /* do we have any PHY events ? */ 2857 ata_sata_phy_check_events(dev); 2858 } 2859 2860 /* do we have any device action ? */ 2861 return (cause & (2 << shift)); 2862 } 2863 2864 /* must be called with ATA channel locked and state_mtx held */ 2865 static int 2866 ata_marvell_edma_begin_transaction(struct ata_request *request) 2867 { 2868 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2869 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2870 u_int32_t req_in; 2871 u_int8_t *bytep; 2872 u_int16_t *wordp; 2873 u_int32_t *quadp; 2874 int i, tag = 0x07; 2875 int dummy, error, slot; 2876 2877 /* only DMA R/W goes through the EMDA machine */ 2878 if (request->u.ata.command != ATA_READ_DMA && 2879 request->u.ata.command != ATA_WRITE_DMA) { 2880 2881 /* disable the EDMA machinery */ 2882 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001) 2883 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2884 return ata_begin_transaction(request); 2885 } 2886 2887 /* check for 48 bit access and convert if needed */ 2888 ata_modify_if_48bit(request); 2889 2890 /* check sanity, setup SG list and DMA engine */ 2891 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 2892 request->flags & ATA_R_READ, ch->dma->sg, 2893 &dummy))) { 2894 device_printf(request->dev, "setting up DMA failed\n"); 2895 request->result = error; 2896 return ATA_OP_FINISHED; 2897 } 2898 2899 /* get next free request queue slot */ 2900 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch)); 2901 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f; 2902 bytep = (u_int8_t *)(ch->dma->work); 2903 bytep += (slot << 5); 2904 wordp = (u_int16_t *)bytep; 2905 quadp = (u_int32_t *)bytep; 2906 2907 /* fill in this request */ 2908 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff; 2909 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32; 2910 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1); 2911 2912 i = 10; 2913 bytep[i++] = (request->u.ata.count >> 8) & 0xff; 2914 bytep[i++] = 0x10 | ATA_COUNT; 2915 bytep[i++] = request->u.ata.count & 0xff; 2916 bytep[i++] = 0x10 | ATA_COUNT; 2917 2918 bytep[i++] = (request->u.ata.lba >> 24) & 0xff; 2919 bytep[i++] = 0x10 | ATA_SECTOR; 2920 bytep[i++] = request->u.ata.lba & 0xff; 2921 bytep[i++] = 0x10 | ATA_SECTOR; 2922 2923 bytep[i++] = (request->u.ata.lba >> 32) & 0xff; 2924 bytep[i++] = 0x10 | ATA_CYL_LSB; 2925 bytep[i++] = (request->u.ata.lba >> 8) & 0xff; 2926 bytep[i++] = 0x10 | ATA_CYL_LSB; 2927 2928 bytep[i++] = (request->u.ata.lba >> 40) & 0xff; 2929 bytep[i++] = 0x10 | ATA_CYL_MSB; 2930 bytep[i++] = (request->u.ata.lba >> 16) & 0xff; 2931 bytep[i++] = 0x10 | ATA_CYL_MSB; 2932 2933 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf); 2934 bytep[i++] = 0x10 | ATA_DRIVE; 2935 2936 bytep[i++] = request->u.ata.command; 2937 bytep[i++] = 0x90 | ATA_COMMAND; 2938 2939 /* enable EDMA machinery if needed */ 2940 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) { 2941 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2942 while (!(ATA_INL(ctlr->r_res1, 2943 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 2944 DELAY(10); 2945 } 2946 2947 /* tell EDMA it has a new request */ 2948 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f; 2949 req_in &= 0xfffffc00; 2950 req_in += (slot << 5); 2951 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in); 2952 2953 return ATA_OP_CONTINUES; 2954 } 2955 2956 /* must be called with ATA channel locked and state_mtx held */ 2957 static int 2958 ata_marvell_edma_end_transaction(struct ata_request *request) 2959 { 2960 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2961 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2962 int offset = (ch->unit > 3 ? 0x30014 : 0x20014); 2963 u_int32_t icr = ATA_INL(ctlr->r_res1, offset); 2964 int res; 2965 2966 /* EDMA interrupt */ 2967 if ((icr & (0x0001 << (ch->unit & 3)))) { 2968 struct ata_marvell_response *response; 2969 u_int32_t rsp_in, rsp_out; 2970 int slot; 2971 2972 /* stop timeout */ 2973 callout_stop(&request->callout); 2974 2975 /* get response ptr's */ 2976 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch)); 2977 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch)); 2978 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f; 2979 rsp_out &= 0xffffff00; 2980 rsp_out += (slot << 3); 2981 response = (struct ata_marvell_response *) 2982 (ch->dma->work + 1024 + (slot << 3)); 2983 2984 /* record status for this request */ 2985 request->status = response->dev_status; 2986 request->error = 0; 2987 2988 /* ack response */ 2989 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out); 2990 2991 /* update progress */ 2992 if (!(request->status & ATA_S_ERROR) && 2993 !(request->flags & ATA_R_TIMEOUT)) 2994 request->donecount = request->bytecount; 2995 2996 /* unload SG list */ 2997 ch->dma->unload(ch->dev); 2998 2999 res = ATA_OP_FINISHED; 3000 } 3001 3002 /* legacy ATA interrupt */ 3003 else { 3004 res = ata_end_transaction(request); 3005 } 3006 3007 /* ack interrupt */ 3008 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3)))); 3009 return res; 3010 } 3011 3012 static void 3013 ata_marvell_edma_reset(device_t dev) 3014 { 3015 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3016 struct ata_channel *ch = device_get_softc(dev); 3017 3018 /* disable the EDMA machinery */ 3019 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 3020 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 3021 DELAY(10); 3022 3023 /* clear SATA error register */ 3024 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 3025 3026 /* clear any outstanding error interrupts */ 3027 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 3028 3029 /* unmask all error interrupts */ 3030 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 3031 3032 /* enable channel and test for devices */ 3033 if (ata_sata_phy_reset(dev)) 3034 ata_generic_reset(dev); 3035 3036 /* enable EDMA machinery */ 3037 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 3038 } 3039 3040 static void 3041 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, 3042 int error) 3043 { 3044 struct ata_dmasetprd_args *args = xsc; 3045 struct ata_marvell_dma_prdentry *prd = args->dmatab; 3046 int i; 3047 3048 if ((args->error = error)) 3049 return; 3050 3051 for (i = 0; i < nsegs; i++) { 3052 prd[i].addrlo = htole32(segs[i].ds_addr); 3053 prd[i].count = htole32(segs[i].ds_len); 3054 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32); 3055 } 3056 prd[i - 1].count |= htole32(ATA_DMA_EOT); 3057 } 3058 3059 static void 3060 ata_marvell_edma_dmainit(device_t dev) 3061 { 3062 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3063 struct ata_channel *ch = device_get_softc(dev); 3064 3065 ata_dmainit(dev); 3066 if (ch->dma) { 3067 /* note start and stop are not used here */ 3068 ch->dma->setprd = ata_marvell_edma_dmasetprd; 3069 3070 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004) 3071 ch->dma->max_address = BUS_SPACE_MAXADDR; 3072 3073 /* chip does not reliably do 64K DMA transfers */ 3074 ch->dma->max_iosize = 126 * DEV_BSIZE; 3075 } 3076 } 3077 3078 3079 /* 3080 * National chipset support functions 3081 */ 3082 int 3083 ata_national_ident(device_t dev) 3084 { 3085 struct ata_pci_controller *ctlr = device_get_softc(dev); 3086 3087 /* this chip is a clone of the Cyrix chip, bugs and all */ 3088 if (pci_get_devid(dev) == ATA_SC1100) { 3089 device_set_desc(dev, "National Geode SC1100 ATA33 controller"); 3090 ctlr->chipinit = ata_national_chipinit; 3091 return 0; 3092 } 3093 return ENXIO; 3094 } 3095 3096 static int 3097 ata_national_chipinit(device_t dev) 3098 { 3099 struct ata_pci_controller *ctlr = device_get_softc(dev); 3100 3101 if (ata_setup_interrupt(dev)) 3102 return ENXIO; 3103 3104 ctlr->setmode = ata_national_setmode; 3105 return 0; 3106 } 3107 3108 static void 3109 ata_national_setmode(device_t dev, int mode) 3110 { 3111 device_t gparent = GRANDPARENT(dev); 3112 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3113 struct ata_device *atadev = device_get_softc(dev); 3114 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3115 u_int32_t piotiming[] = 3116 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010, 3117 0x00803020, 0x20102010, 0x00100010, 3118 0x00100010, 0x00100010, 0x00100010 }; 3119 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 }; 3120 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 }; 3121 int error; 3122 3123 ch->dma->alignment = 16; 3124 ch->dma->max_iosize = 126 * DEV_BSIZE; 3125 3126 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 3127 3128 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3129 3130 if (bootverbose) 3131 device_printf(dev, "%s setting %s on National chip\n", 3132 (error) ? "failed" : "success", ata_mode2str(mode)); 3133 if (!error) { 3134 if (mode >= ATA_UDMA0) { 3135 pci_write_config(gparent, 0x44 + (devno << 3), 3136 udmatiming[mode & ATA_MODE_MASK], 4); 3137 } 3138 else if (mode >= ATA_WDMA0) { 3139 pci_write_config(gparent, 0x44 + (devno << 3), 3140 dmatiming[mode & ATA_MODE_MASK], 4); 3141 } 3142 else { 3143 pci_write_config(gparent, 0x44 + (devno << 3), 3144 pci_read_config(gparent, 0x44 + (devno << 3), 4) | 3145 0x80000000, 4); 3146 } 3147 pci_write_config(gparent, 0x40 + (devno << 3), 3148 piotiming[ata_mode2idx(mode)], 4); 3149 atadev->mode = mode; 3150 } 3151 } 3152 3153 /* 3154 * NetCell chipset support functions 3155 */ 3156 int 3157 ata_netcell_ident(device_t dev) 3158 { 3159 struct ata_pci_controller *ctlr = device_get_softc(dev); 3160 3161 if (pci_get_devid(dev) == ATA_NETCELL_SR) { 3162 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller"); 3163 ctlr->chipinit = ata_netcell_chipinit; 3164 return 0; 3165 } 3166 return ENXIO; 3167 } 3168 3169 static int 3170 ata_netcell_chipinit(device_t dev) 3171 { 3172 struct ata_pci_controller *ctlr = device_get_softc(dev); 3173 3174 if (ata_generic_chipinit(dev)) 3175 return ENXIO; 3176 3177 ctlr->allocate = ata_netcell_allocate; 3178 return 0; 3179 } 3180 3181 static int 3182 ata_netcell_allocate(device_t dev) 3183 { 3184 struct ata_channel *ch = device_get_softc(dev); 3185 3186 /* setup the usual register normal pci style */ 3187 if (ata_pci_allocate(dev)) 3188 return ENXIO; 3189 3190 /* the NetCell only supports 16 bit PIO transfers */ 3191 ch->flags |= ATA_USE_16BIT; 3192 3193 return 0; 3194 } 3195 3196 3197 /* 3198 * nVidia chipset support functions 3199 */ 3200 int 3201 ata_nvidia_ident(device_t dev) 3202 { 3203 struct ata_pci_controller *ctlr = device_get_softc(dev); 3204 struct ata_chip_id *idx; 3205 static struct ata_chip_id ids[] = 3206 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" }, 3207 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" }, 3208 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" }, 3209 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" }, 3210 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" }, 3211 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" }, 3212 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3213 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3214 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" }, 3215 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3216 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3217 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" }, 3218 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3219 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3220 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" }, 3221 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3222 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3223 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" }, 3224 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3225 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3226 { ATA_NFORCE_MCP61, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP61" }, 3227 { ATA_NFORCE_MCP61_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" }, 3228 { ATA_NFORCE_MCP61_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" }, 3229 { ATA_NFORCE_MCP61_S3, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" }, 3230 { ATA_NFORCE_MCP65, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP65" }, 3231 { ATA_NFORCE_MCP67, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP67" }, 3232 { ATA_NFORCE_MCP67_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP67" }, 3233 { ATA_NFORCE_MCP73, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP73" }, 3234 { ATA_NFORCE_MCP77, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP77" }, 3235 { 0, 0, 0, 0, 0, 0}} ; 3236 char buffer[64] ; 3237 3238 if (!(idx = ata_match_chip(dev, ids))) 3239 return ENXIO; 3240 3241 ksprintf(buffer, "nVidia %s %s controller", 3242 idx->text, ata_mode2str(idx->max_dma)); 3243 device_set_desc_copy(dev, buffer); 3244 ctlr->chip = idx; 3245 ctlr->chipinit = ata_nvidia_chipinit; 3246 return 0; 3247 } 3248 3249 static int 3250 ata_nvidia_chipinit(device_t dev) 3251 { 3252 struct ata_pci_controller *ctlr = device_get_softc(dev); 3253 3254 if (ata_setup_interrupt(dev)) 3255 return ENXIO; 3256 3257 if (ctlr->chip->max_dma >= ATA_SA150) { 3258 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1) 3259 ctlr->r_type2 = SYS_RES_IOPORT; 3260 else 3261 ctlr->r_type2 = SYS_RES_MEMORY; 3262 ctlr->r_rid2 = PCIR_BAR(5); 3263 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3264 &ctlr->r_rid2, RF_ACTIVE))) { 3265 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3266 3267 ctlr->allocate = ata_nvidia_allocate; 3268 ctlr->reset = ata_nvidia_reset; 3269 3270 /* enable control access */ 3271 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1); 3272 3273 if (ctlr->chip->cfg2 & NVQ) { 3274 /* clear interrupt status */ 3275 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff); 3276 3277 /* enable device and PHY state change interrupts */ 3278 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d); 3279 3280 /* disable NCQ support */ 3281 ATA_OUTL(ctlr->r_res2, 0x0400, 3282 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9); 3283 } 3284 else { 3285 /* clear interrupt status */ 3286 ATA_OUTB(ctlr->r_res2, offset, 0xff); 3287 3288 /* enable device and PHY state change interrupts */ 3289 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd); 3290 } 3291 3292 /* enable PCI interrupt */ 3293 pci_write_config(dev, PCIR_COMMAND, 3294 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 3295 3296 } 3297 ctlr->setmode = ata_sata_setmode; 3298 } 3299 else { 3300 /* disable prefetch, postwrite */ 3301 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1); 3302 ctlr->setmode = ata_via_family_setmode; 3303 } 3304 return 0; 3305 } 3306 3307 static int 3308 ata_nvidia_allocate(device_t dev) 3309 { 3310 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3311 struct ata_channel *ch = device_get_softc(dev); 3312 3313 /* setup the usual register normal pci style */ 3314 if (ata_pci_allocate(dev)) 3315 return ENXIO; 3316 3317 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3318 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6); 3319 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3320 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6); 3321 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3322 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6); 3323 3324 ch->hw.status = ata_nvidia_status; 3325 ch->flags |= ATA_NO_SLAVE; 3326 3327 return 0; 3328 } 3329 3330 static int 3331 ata_nvidia_status(device_t dev) 3332 { 3333 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3334 struct ata_channel *ch = device_get_softc(dev); 3335 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3336 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2); 3337 u_int32_t istatus; 3338 3339 /* get interrupt status */ 3340 if (ctlr->chip->cfg2 & NVQ) 3341 istatus = ATA_INL(ctlr->r_res2, offset); 3342 else 3343 istatus = ATA_INB(ctlr->r_res2, offset); 3344 3345 /* do we have any PHY events ? */ 3346 if (istatus & (0x0c << shift)) 3347 ata_sata_phy_check_events(dev); 3348 3349 /* clear interrupt(s) */ 3350 if (ctlr->chip->cfg2 & NVQ) 3351 ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0); 3352 else 3353 ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift)); 3354 3355 /* do we have any device action ? */ 3356 return (istatus & (0x01 << shift)); 3357 } 3358 3359 static void 3360 ata_nvidia_reset(device_t dev) 3361 { 3362 if (ata_sata_phy_reset(dev)) 3363 ata_generic_reset(dev); 3364 } 3365 3366 3367 /* 3368 * Promise chipset support functions 3369 */ 3370 #define ATA_PDC_APKT_OFFSET 0x00000010 3371 #define ATA_PDC_HPKT_OFFSET 0x00000040 3372 #define ATA_PDC_ASG_OFFSET 0x00000080 3373 #define ATA_PDC_LSG_OFFSET 0x000000c0 3374 #define ATA_PDC_HSG_OFFSET 0x00000100 3375 #define ATA_PDC_CHN_OFFSET 0x00000400 3376 #define ATA_PDC_BUF_BASE 0x00400000 3377 #define ATA_PDC_BUF_OFFSET 0x00100000 3378 #define ATA_PDC_MAX_HPKT 8 3379 #define ATA_PDC_WRITE_REG 0x00 3380 #define ATA_PDC_WRITE_CTL 0x0e 3381 #define ATA_PDC_WRITE_END 0x08 3382 #define ATA_PDC_WAIT_NBUSY 0x10 3383 #define ATA_PDC_WAIT_READY 0x18 3384 #define ATA_PDC_1B 0x20 3385 #define ATA_PDC_2B 0x40 3386 3387 struct host_packet { 3388 u_int32_t addr; 3389 TAILQ_ENTRY(host_packet) chain; 3390 }; 3391 3392 struct ata_promise_sx4 { 3393 struct spinlock mtx; 3394 TAILQ_HEAD(, host_packet) queue; 3395 int busy; 3396 }; 3397 3398 int 3399 ata_promise_ident(device_t dev) 3400 { 3401 struct ata_pci_controller *ctlr = device_get_softc(dev); 3402 struct ata_chip_id *idx; 3403 static struct ata_chip_id ids[] = 3404 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" }, 3405 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" }, 3406 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" }, 3407 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" }, 3408 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" }, 3409 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" }, 3410 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" }, 3411 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" }, 3412 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" }, 3413 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" }, 3414 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" }, 3415 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" }, 3416 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" }, 3417 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" }, 3418 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" }, 3419 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" }, 3420 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" }, 3421 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" }, 3422 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" }, 3423 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" }, 3424 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" }, 3425 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" }, 3426 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" }, 3427 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" }, 3428 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" }, 3429 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" }, 3430 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" }, 3431 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" }, 3432 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" }, 3433 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" }, 3434 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" }, 3435 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" }, 3436 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" }, 3437 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" }, 3438 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" }, 3439 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" }, 3440 { 0, 0, 0, 0, 0, 0}}; 3441 char buffer[64]; 3442 uintptr_t devid = 0; 3443 3444 if (!(idx = ata_match_chip(dev, ids))) 3445 return ENXIO; 3446 3447 /* if we are on a SuperTrak SX6000 dont attach */ 3448 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3449 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3450 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3451 devid == ATA_I960RM) 3452 return ENXIO; 3453 3454 strcpy(buffer, "Promise "); 3455 strcat(buffer, idx->text); 3456 3457 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 3458 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3459 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3460 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3461 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 3462 static long start = 0, end = 0; 3463 3464 if (pci_get_slot(dev) == 1) { 3465 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 3466 strcat(buffer, " (channel 0+1)"); 3467 } 3468 else if (pci_get_slot(dev) == 2 && start && end) { 3469 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end, 3470 machintr_intr_cpuid(start)); 3471 strcat(buffer, " (channel 2+3)"); 3472 } 3473 else { 3474 start = end = 0; 3475 } 3476 } 3477 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 3478 device_set_desc_copy(dev, buffer); 3479 ctlr->chip = idx; 3480 ctlr->chipinit = ata_promise_chipinit; 3481 return 0; 3482 } 3483 3484 static int 3485 ata_promise_chipinit(device_t dev) 3486 { 3487 struct ata_pci_controller *ctlr = device_get_softc(dev); 3488 int fake_reg, stat_reg; 3489 3490 if (ata_setup_interrupt(dev)) 3491 return ENXIO; 3492 3493 switch (ctlr->chip->cfg1) { 3494 case PRNEW: 3495 /* setup clocks */ 3496 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 3497 3498 ctlr->dmainit = ata_promise_dmainit; 3499 /* FALLTHROUGH */ 3500 3501 case PROLD: 3502 /* enable burst mode */ 3503 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 3504 ctlr->allocate = ata_promise_allocate; 3505 ctlr->setmode = ata_promise_setmode; 3506 return 0; 3507 3508 case PRTX: 3509 ctlr->allocate = ata_promise_tx2_allocate; 3510 ctlr->setmode = ata_promise_setmode; 3511 return 0; 3512 3513 case PRMIO: 3514 ctlr->r_type1 = SYS_RES_MEMORY; 3515 ctlr->r_rid1 = PCIR_BAR(4); 3516 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 3517 &ctlr->r_rid1, RF_ACTIVE))) 3518 goto failnfree; 3519 3520 ctlr->r_type2 = SYS_RES_MEMORY; 3521 ctlr->r_rid2 = PCIR_BAR(3); 3522 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3523 &ctlr->r_rid2, RF_ACTIVE))) 3524 goto failnfree; 3525 3526 if (ctlr->chip->cfg2 == PRSX4X) { 3527 struct ata_promise_sx4 *hpkt; 3528 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 3529 3530 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3531 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3532 ata_promise_sx4_intr, ctlr, &ctlr->handle, NULL)) { 3533 device_printf(dev, "unable to setup interrupt\n"); 3534 goto failnfree; 3535 } 3536 3537 /* print info about cache memory */ 3538 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 3539 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 3540 ((dimm >> 24) & 0xff), 3541 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 3542 " ECC enabled" : "" ); 3543 3544 /* adjust cache memory parameters */ 3545 ATA_OUTL(ctlr->r_res2, 0x000c000c, 3546 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 3547 3548 /* setup host packet controls */ 3549 hpkt = kmalloc(sizeof(struct ata_promise_sx4), 3550 M_TEMP, M_INTWAIT | M_ZERO); 3551 spin_init(&hpkt->mtx); 3552 TAILQ_INIT(&hpkt->queue); 3553 hpkt->busy = 0; 3554 device_set_ivars(dev, hpkt); 3555 ctlr->allocate = ata_promise_mio_allocate; 3556 ctlr->reset = ata_promise_mio_reset; 3557 ctlr->dmainit = ata_promise_mio_dmainit; 3558 ctlr->setmode = ata_promise_setmode; 3559 ctlr->channels = 4; 3560 return 0; 3561 } 3562 3563 /* mio type controllers need an interrupt intercept */ 3564 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3565 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3566 ata_promise_mio_intr, ctlr, &ctlr->handle, NULL)) { 3567 device_printf(dev, "unable to setup interrupt\n"); 3568 goto failnfree; 3569 } 3570 3571 switch (ctlr->chip->cfg2) { 3572 case PRPATA: 3573 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 3574 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 3575 goto sata150; 3576 case PRCMBO: 3577 ctlr->channels = 3; 3578 goto sata150; 3579 case PRSATA: 3580 ctlr->channels = 4; 3581 sata150: 3582 fake_reg = 0x60; 3583 stat_reg = 0x6c; 3584 break; 3585 3586 case PRCMBO2: 3587 ctlr->channels = 3; 3588 goto sataii; 3589 case PRSATA2: 3590 default: 3591 ctlr->channels = 4; 3592 sataii: 3593 fake_reg = 0x54; 3594 stat_reg = 0x60; 3595 break; 3596 } 3597 3598 /* prime fake interrupt register */ 3599 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3600 3601 /* clear SATA status */ 3602 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 3603 3604 ctlr->allocate = ata_promise_mio_allocate; 3605 ctlr->reset = ata_promise_mio_reset; 3606 ctlr->dmainit = ata_promise_mio_dmainit; 3607 ctlr->setmode = ata_promise_mio_setmode; 3608 3609 return 0; 3610 } 3611 3612 failnfree: 3613 if (ctlr->r_res2) 3614 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 3615 if (ctlr->r_res1) 3616 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 3617 return ENXIO; 3618 } 3619 3620 static int 3621 ata_promise_allocate(device_t dev) 3622 { 3623 struct ata_channel *ch = device_get_softc(dev); 3624 3625 if (ata_pci_allocate(dev)) 3626 return ENXIO; 3627 3628 ch->hw.status = ata_promise_status; 3629 return 0; 3630 } 3631 3632 static int 3633 ata_promise_status(device_t dev) 3634 { 3635 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3636 struct ata_channel *ch = device_get_softc(dev); 3637 3638 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 3639 return ata_pci_status(dev); 3640 } 3641 return 0; 3642 } 3643 3644 static int 3645 ata_promise_dmastart(device_t dev) 3646 { 3647 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3648 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3649 struct ata_device *atadev = device_get_softc(dev); 3650 3651 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3652 ATA_OUTB(ctlr->r_res1, 0x11, 3653 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 3654 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 3655 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) | 3656 (ch->dma->cur_iosize >> 1)); 3657 } 3658 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 3659 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 3660 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus); 3661 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3662 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) | 3663 ATA_BMCMD_START_STOP); 3664 ch->flags |= ATA_DMA_ACTIVE; 3665 return 0; 3666 } 3667 3668 static int 3669 ata_promise_dmastop(device_t dev) 3670 { 3671 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3672 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3673 struct ata_device *atadev = device_get_softc(dev); 3674 int error; 3675 3676 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3677 ATA_OUTB(ctlr->r_res1, 0x11, 3678 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 3679 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 3680 } 3681 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 3682 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3683 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3684 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3685 ch->flags &= ~ATA_DMA_ACTIVE; 3686 return error; 3687 } 3688 3689 static void 3690 ata_promise_dmareset(device_t dev) 3691 { 3692 struct ata_channel *ch = device_get_softc(dev); 3693 3694 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3695 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3696 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3697 ch->flags &= ~ATA_DMA_ACTIVE; 3698 } 3699 3700 static void 3701 ata_promise_dmainit(device_t dev) 3702 { 3703 struct ata_channel *ch = device_get_softc(dev); 3704 3705 ata_dmainit(dev); 3706 if (ch->dma) { 3707 ch->dma->start = ata_promise_dmastart; 3708 ch->dma->stop = ata_promise_dmastop; 3709 ch->dma->reset = ata_promise_dmareset; 3710 } 3711 } 3712 3713 static void 3714 ata_promise_setmode(device_t dev, int mode) 3715 { 3716 device_t gparent = GRANDPARENT(dev); 3717 struct ata_pci_controller *ctlr = device_get_softc(gparent); 3718 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3719 struct ata_device *atadev = device_get_softc(dev); 3720 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3721 int error; 3722 u_int32_t timings[][2] = { 3723 /* PROLD PRNEW mode */ 3724 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 3725 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 3726 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 3727 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 3728 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 3729 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 3730 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 3731 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 3732 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 3733 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 3734 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 3735 { 0, 0x00424ef6 }, /* UDMA 3 */ 3736 { 0, 0x004127f3 }, /* UDMA 4 */ 3737 { 0, 0x004127f3 } /* UDMA 5 */ 3738 }; 3739 3740 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 3741 3742 switch (ctlr->chip->cfg1) { 3743 case PROLD: 3744 case PRNEW: 3745 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) & 3746 (ch->unit ? 1 << 11 : 1 << 10))) { 3747 ata_print_cable(dev, "controller"); 3748 mode = ATA_UDMA2; 3749 } 3750 if (ata_atapi(dev) && mode > ATA_PIO_MAX) 3751 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 3752 break; 3753 3754 case PRTX: 3755 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3756 if (mode > ATA_UDMA2 && 3757 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 3758 ata_print_cable(dev, "controller"); 3759 mode = ATA_UDMA2; 3760 } 3761 break; 3762 3763 case PRMIO: 3764 if (mode > ATA_UDMA2 && 3765 (ATA_INL(ctlr->r_res2, 3766 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) + 3767 (ch->unit << 7)) & 0x01000000)) { 3768 ata_print_cable(dev, "controller"); 3769 mode = ATA_UDMA2; 3770 } 3771 break; 3772 } 3773 3774 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3775 3776 if (bootverbose) 3777 device_printf(dev, "%ssetting %s on %s chip\n", 3778 (error) ? "FAILURE " : "", 3779 ata_mode2str(mode), ctlr->chip->text); 3780 if (!error) { 3781 if (ctlr->chip->cfg1 < PRTX) 3782 pci_write_config(gparent, 0x60 + (devno << 2), 3783 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 3784 atadev->mode = mode; 3785 } 3786 return; 3787 } 3788 3789 static int 3790 ata_promise_tx2_allocate(device_t dev) 3791 { 3792 struct ata_channel *ch = device_get_softc(dev); 3793 3794 if (ata_pci_allocate(dev)) 3795 return ENXIO; 3796 3797 ch->hw.status = ata_promise_tx2_status; 3798 return 0; 3799 } 3800 3801 static int 3802 ata_promise_tx2_status(device_t dev) 3803 { 3804 struct ata_channel *ch = device_get_softc(dev); 3805 3806 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3807 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 3808 return ata_pci_status(dev); 3809 } 3810 return 0; 3811 } 3812 3813 static int 3814 ata_promise_mio_allocate(device_t dev) 3815 { 3816 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3817 struct ata_channel *ch = device_get_softc(dev); 3818 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0; 3819 int i; 3820 3821 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 3822 ch->r_io[i].res = ctlr->r_res2; 3823 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 3824 } 3825 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 3826 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 3827 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 3828 ata_default_registers(dev); 3829 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) || 3830 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) { 3831 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3832 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 3833 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3834 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 3835 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3836 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 3837 ch->flags |= ATA_NO_SLAVE; 3838 } 3839 ch->flags |= ATA_USE_16BIT; 3840 3841 ata_generic_hw(dev); 3842 if (ctlr->chip->cfg2 & PRSX4X) { 3843 ch->hw.command = ata_promise_sx4_command; 3844 } 3845 else { 3846 ch->hw.command = ata_promise_mio_command; 3847 ch->hw.status = ata_promise_mio_status; 3848 } 3849 return 0; 3850 } 3851 3852 static void 3853 ata_promise_mio_intr(void *data) 3854 { 3855 struct ata_pci_controller *ctlr = data; 3856 struct ata_channel *ch; 3857 u_int32_t vector; 3858 int unit, fake_reg; 3859 3860 switch (ctlr->chip->cfg2) { 3861 case PRPATA: 3862 case PRCMBO: 3863 case PRSATA: 3864 fake_reg = 0x60; 3865 break; 3866 case PRCMBO2: 3867 case PRSATA2: 3868 default: 3869 fake_reg = 0x54; 3870 break; 3871 } 3872 3873 /* 3874 * since reading interrupt status register on early "mio" chips 3875 * clears the status bits we cannot read it for each channel later on 3876 * in the generic interrupt routine. 3877 * store the bits in an unused register in the chip so we can read 3878 * it from there safely to get around this "feature". 3879 */ 3880 vector = ATA_INL(ctlr->r_res2, 0x040); 3881 ATA_OUTL(ctlr->r_res2, 0x040, vector); 3882 ATA_OUTL(ctlr->r_res2, fake_reg, vector); 3883 3884 for (unit = 0; unit < ctlr->channels; unit++) { 3885 if ((ch = ctlr->interrupt[unit].argument)) 3886 ctlr->interrupt[unit].function(ch); 3887 } 3888 3889 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3890 } 3891 3892 static int 3893 ata_promise_mio_status(device_t dev) 3894 { 3895 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3896 struct ata_channel *ch = device_get_softc(dev); 3897 struct ata_connect_task *tp; 3898 u_int32_t fake_reg, stat_reg, vector, status; 3899 3900 switch (ctlr->chip->cfg2) { 3901 case PRPATA: 3902 case PRCMBO: 3903 case PRSATA: 3904 fake_reg = 0x60; 3905 stat_reg = 0x6c; 3906 break; 3907 case PRCMBO2: 3908 case PRSATA2: 3909 default: 3910 fake_reg = 0x54; 3911 stat_reg = 0x60; 3912 break; 3913 } 3914 3915 /* read and acknowledge interrupt */ 3916 vector = ATA_INL(ctlr->r_res2, fake_reg); 3917 3918 /* read and clear interface status */ 3919 status = ATA_INL(ctlr->r_res2, stat_reg); 3920 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 3921 3922 /* check for and handle disconnect events */ 3923 if ((status & (0x00000001 << ch->unit)) && 3924 (tp = (struct ata_connect_task *) 3925 kmalloc(sizeof(struct ata_connect_task), 3926 M_ATA, M_INTWAIT | M_ZERO))) { 3927 3928 if (bootverbose) 3929 device_printf(ch->dev, "DISCONNECT requested\n"); 3930 tp->action = ATA_C_DETACH; 3931 tp->dev = ch->dev; 3932 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3933 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3934 } 3935 3936 /* check for and handle connect events */ 3937 if ((status & (0x00000010 << ch->unit)) && 3938 (tp = (struct ata_connect_task *) 3939 kmalloc(sizeof(struct ata_connect_task), 3940 M_ATA, M_INTWAIT | M_ZERO))) { 3941 3942 if (bootverbose) 3943 device_printf(ch->dev, "CONNECT requested\n"); 3944 tp->action = ATA_C_ATTACH; 3945 tp->dev = ch->dev; 3946 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3947 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3948 } 3949 3950 /* do we have any device action ? */ 3951 return (vector & (1 << (ch->unit + 1))); 3952 } 3953 3954 static int 3955 ata_promise_mio_command(struct ata_request *request) 3956 { 3957 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 3958 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 3959 u_int32_t *wordp = (u_int32_t *)ch->dma->work; 3960 3961 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 3962 3963 /* XXX SOS add ATAPI commands support later */ 3964 switch (request->u.ata.command) { 3965 default: 3966 return ata_generic_command(request); 3967 3968 case ATA_READ_DMA: 3969 case ATA_READ_DMA48: 3970 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3971 break; 3972 3973 case ATA_WRITE_DMA: 3974 case ATA_WRITE_DMA48: 3975 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3976 break; 3977 } 3978 wordp[1] = htole32(ch->dma->sg_bus); 3979 wordp[2] = 0; 3980 ata_promise_apkt((u_int8_t*)wordp, request); 3981 3982 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus); 3983 return 0; 3984 } 3985 3986 static void 3987 ata_promise_mio_reset(device_t dev) 3988 { 3989 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3990 struct ata_channel *ch = device_get_softc(dev); 3991 struct ata_promise_sx4 *hpktp; 3992 3993 switch (ctlr->chip->cfg2) { 3994 case PRSX4X: 3995 3996 /* softreset channel ATA module */ 3997 hpktp = device_get_ivars(ctlr->dev); 3998 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 3999 ata_udelay(1000); 4000 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 4001 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 4002 ~0x00003f9f) | (ch->unit + 1)); 4003 4004 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 4005 spin_lock(&hpktp->mtx); 4006 ATA_OUTL(ctlr->r_res2, 0xc012c, 4007 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 4008 DELAY(10); 4009 ATA_OUTL(ctlr->r_res2, 0xc012c, 4010 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 4011 hpktp->busy = 0; 4012 spin_unlock(&hpktp->mtx); 4013 ata_generic_reset(dev); 4014 break; 4015 4016 case PRPATA: 4017 case PRCMBO: 4018 case PRSATA: 4019 if ((ctlr->chip->cfg2 == PRSATA) || 4020 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 4021 4022 /* mask plug/unplug intr */ 4023 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 4024 } 4025 4026 /* softreset channels ATA module */ 4027 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 4028 ata_udelay(10000); 4029 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 4030 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 4031 ~0x00003f9f) | (ch->unit + 1)); 4032 4033 if ((ctlr->chip->cfg2 == PRSATA) || 4034 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 4035 4036 if (ata_sata_phy_reset(dev)) 4037 ata_generic_reset(dev); 4038 4039 /* reset and enable plug/unplug intr */ 4040 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 4041 } 4042 else 4043 ata_generic_reset(dev); 4044 break; 4045 4046 case PRCMBO2: 4047 case PRSATA2: 4048 if ((ctlr->chip->cfg2 == PRSATA2) || 4049 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 4050 /* set portmultiplier port */ 4051 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 4052 4053 /* mask plug/unplug intr */ 4054 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 4055 } 4056 4057 /* softreset channels ATA module */ 4058 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 4059 ata_udelay(10000); 4060 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 4061 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 4062 ~0x00003f9f) | (ch->unit + 1)); 4063 4064 if ((ctlr->chip->cfg2 == PRSATA2) || 4065 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 4066 4067 /* set PHY mode to "improved" */ 4068 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 4069 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 4070 ~0x00000003) | 0x00000001); 4071 4072 if (ata_sata_phy_reset(dev)) 4073 ata_generic_reset(dev); 4074 4075 /* reset and enable plug/unplug intr */ 4076 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 4077 4078 /* set portmultiplier port */ 4079 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 4080 } 4081 else 4082 ata_generic_reset(dev); 4083 break; 4084 4085 } 4086 } 4087 4088 static void 4089 ata_promise_mio_dmainit(device_t dev) 4090 { 4091 /* note start and stop are not used here */ 4092 ata_dmainit(dev); 4093 } 4094 4095 static void 4096 ata_promise_mio_setmode(device_t dev, int mode) 4097 { 4098 device_t gparent = GRANDPARENT(dev); 4099 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4100 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4101 4102 if ( (ctlr->chip->cfg2 == PRSATA) || 4103 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) || 4104 (ctlr->chip->cfg2 == PRSATA2) || 4105 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) 4106 ata_sata_setmode(dev, mode); 4107 else 4108 ata_promise_setmode(dev, mode); 4109 } 4110 4111 static void 4112 ata_promise_sx4_intr(void *data) 4113 { 4114 struct ata_pci_controller *ctlr = data; 4115 struct ata_channel *ch; 4116 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 4117 int unit; 4118 4119 for (unit = 0; unit < ctlr->channels; unit++) { 4120 if (vector & (1 << (unit + 1))) 4121 if ((ch = ctlr->interrupt[unit].argument)) 4122 ctlr->interrupt[unit].function(ch); 4123 if (vector & (1 << (unit + 5))) 4124 if ((ch = ctlr->interrupt[unit].argument)) 4125 ata_promise_queue_hpkt(ctlr, 4126 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 4127 ATA_PDC_HPKT_OFFSET)); 4128 if (vector & (1 << (unit + 9))) { 4129 ata_promise_next_hpkt(ctlr); 4130 if ((ch = ctlr->interrupt[unit].argument)) 4131 ctlr->interrupt[unit].function(ch); 4132 } 4133 if (vector & (1 << (unit + 13))) { 4134 ata_promise_next_hpkt(ctlr); 4135 if ((ch = ctlr->interrupt[unit].argument)) 4136 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4137 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 4138 ATA_PDC_APKT_OFFSET)); 4139 } 4140 } 4141 } 4142 4143 static int 4144 ata_promise_sx4_command(struct ata_request *request) 4145 { 4146 device_t gparent = GRANDPARENT(request->dev); 4147 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4148 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4149 struct ata_dma_prdentry *prd = ch->dma->sg; 4150 caddr_t window = rman_get_virtual(ctlr->r_res1); 4151 u_int32_t *wordp; 4152 int i, idx, length = 0; 4153 4154 /* XXX SOS add ATAPI commands support later */ 4155 switch (request->u.ata.command) { 4156 4157 default: 4158 return -1; 4159 4160 case ATA_ATA_IDENTIFY: 4161 case ATA_READ: 4162 case ATA_READ48: 4163 case ATA_READ_MUL: 4164 case ATA_READ_MUL48: 4165 case ATA_WRITE: 4166 case ATA_WRITE48: 4167 case ATA_WRITE_MUL: 4168 case ATA_WRITE_MUL48: 4169 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4170 return ata_generic_command(request); 4171 4172 case ATA_SETFEATURES: 4173 case ATA_FLUSHCACHE: 4174 case ATA_FLUSHCACHE48: 4175 case ATA_SLEEP: 4176 case ATA_SET_MULTI: 4177 wordp = (u_int32_t *) 4178 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4179 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 4180 wordp[1] = 0; 4181 wordp[2] = 0; 4182 ata_promise_apkt((u_int8_t *)wordp, request); 4183 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4184 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4185 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4186 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 4187 return 0; 4188 4189 case ATA_READ_DMA: 4190 case ATA_READ_DMA48: 4191 case ATA_WRITE_DMA: 4192 case ATA_WRITE_DMA48: 4193 wordp = (u_int32_t *) 4194 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 4195 i = idx = 0; 4196 do { 4197 wordp[idx++] = prd[i].addr; 4198 wordp[idx++] = prd[i].count; 4199 length += (prd[i].count & ~ATA_DMA_EOT); 4200 } while (!(prd[i++].count & ATA_DMA_EOT)); 4201 4202 wordp = (u_int32_t *) 4203 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 4204 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4205 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4206 4207 wordp = (u_int32_t *) 4208 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 4209 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4210 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4211 4212 wordp = (u_int32_t *) 4213 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 4214 if (request->flags & ATA_R_READ) 4215 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 4216 if (request->flags & ATA_R_WRITE) 4217 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 4218 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 4219 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 4220 wordp[3] = 0; 4221 4222 wordp = (u_int32_t *) 4223 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4224 if (request->flags & ATA_R_READ) 4225 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 4226 if (request->flags & ATA_R_WRITE) 4227 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 4228 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 4229 wordp[2] = 0; 4230 ata_promise_apkt((u_int8_t *)wordp, request); 4231 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4232 4233 if (request->flags & ATA_R_READ) { 4234 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 4235 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 4236 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4237 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 4238 } 4239 if (request->flags & ATA_R_WRITE) { 4240 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 4241 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 4242 ata_promise_queue_hpkt(ctlr, 4243 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 4244 } 4245 return 0; 4246 } 4247 } 4248 4249 static int 4250 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 4251 { 4252 struct ata_device *atadev = device_get_softc(request->dev); 4253 int i = 12; 4254 4255 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 4256 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit; 4257 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 4258 bytep[i++] = ATA_A_4BIT; 4259 4260 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 4261 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4262 bytep[i++] = request->u.ata.feature >> 8; 4263 bytep[i++] = request->u.ata.feature; 4264 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 4265 bytep[i++] = request->u.ata.count >> 8; 4266 bytep[i++] = request->u.ata.count; 4267 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4268 bytep[i++] = request->u.ata.lba >> 24; 4269 bytep[i++] = request->u.ata.lba; 4270 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4271 bytep[i++] = request->u.ata.lba >> 32; 4272 bytep[i++] = request->u.ata.lba >> 8; 4273 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4274 bytep[i++] = request->u.ata.lba >> 40; 4275 bytep[i++] = request->u.ata.lba >> 16; 4276 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4277 bytep[i++] = ATA_D_LBA | atadev->unit; 4278 } 4279 else { 4280 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4281 bytep[i++] = request->u.ata.feature; 4282 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 4283 bytep[i++] = request->u.ata.count; 4284 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4285 bytep[i++] = request->u.ata.lba; 4286 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4287 bytep[i++] = request->u.ata.lba >> 8; 4288 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4289 bytep[i++] = request->u.ata.lba >> 16; 4290 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4291 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) | 4292 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf); 4293 } 4294 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 4295 bytep[i++] = request->u.ata.command; 4296 return i; 4297 } 4298 4299 static void 4300 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 4301 { 4302 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4303 4304 spin_lock(&hpktp->mtx); 4305 if (hpktp->busy) { 4306 struct host_packet *hp = 4307 kmalloc(sizeof(struct host_packet), M_TEMP, M_INTWAIT | M_ZERO); 4308 hp->addr = hpkt; 4309 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 4310 } 4311 else { 4312 hpktp->busy = 1; 4313 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 4314 } 4315 spin_unlock(&hpktp->mtx); 4316 } 4317 4318 static void 4319 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 4320 { 4321 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4322 struct host_packet *hp; 4323 4324 spin_lock(&hpktp->mtx); 4325 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 4326 TAILQ_REMOVE(&hpktp->queue, hp, chain); 4327 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 4328 kfree(hp, M_TEMP); 4329 } 4330 else 4331 hpktp->busy = 0; 4332 spin_unlock(&hpktp->mtx); 4333 } 4334 4335 4336 /* 4337 * ServerWorks chipset support functions 4338 */ 4339 int 4340 ata_serverworks_ident(device_t dev) 4341 { 4342 struct ata_pci_controller *ctlr = device_get_softc(dev); 4343 struct ata_chip_id *idx; 4344 static struct ata_chip_id ids[] = 4345 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" }, 4346 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" }, 4347 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" }, 4348 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" }, 4349 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" }, 4350 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" }, 4351 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" }, 4352 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" }, 4353 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" }, 4354 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" }, 4355 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" }, 4356 { 0, 0, 0, 0, 0, 0}}; 4357 char buffer[64]; 4358 4359 if (!(idx = ata_match_chip(dev, ids))) 4360 return ENXIO; 4361 4362 ksprintf(buffer, "ServerWorks %s %s controller", 4363 idx->text, ata_mode2str(idx->max_dma)); 4364 device_set_desc_copy(dev, buffer); 4365 ctlr->chip = idx; 4366 ctlr->chipinit = ata_serverworks_chipinit; 4367 return 0; 4368 } 4369 4370 static int 4371 ata_serverworks_chipinit(device_t dev) 4372 { 4373 struct ata_pci_controller *ctlr = device_get_softc(dev); 4374 4375 if (ata_setup_interrupt(dev)) 4376 return ENXIO; 4377 4378 if (ctlr->chip->cfg1 == SWKSMIO) { 4379 ctlr->r_type2 = SYS_RES_MEMORY; 4380 ctlr->r_rid2 = PCIR_BAR(5); 4381 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4382 &ctlr->r_rid2, RF_ACTIVE))){ 4383 ata_teardown_interrupt(dev); 4384 return ENXIO; 4385 } 4386 4387 ctlr->channels = ctlr->chip->cfg2; 4388 ctlr->allocate = ata_serverworks_allocate; 4389 ctlr->setmode = ata_sata_setmode; 4390 return 0; 4391 } 4392 else if (ctlr->chip->cfg1 == SWKS33) { 4393 device_t *children; 4394 int nchildren, i; 4395 4396 /* locate the ISA part in the southbridge and enable UDMA33 */ 4397 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 4398 for (i = 0; i < nchildren; i++) { 4399 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 4400 pci_write_config(children[i], 0x64, 4401 (pci_read_config(children[i], 0x64, 4) & 4402 ~0x00002000) | 0x00004000, 4); 4403 break; 4404 } 4405 } 4406 kfree(children, M_TEMP); 4407 } 4408 } 4409 else { 4410 pci_write_config(dev, 0x5a, 4411 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 4412 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1); 4413 } 4414 ctlr->setmode = ata_serverworks_setmode; 4415 return 0; 4416 } 4417 4418 static int 4419 ata_serverworks_allocate(device_t dev) 4420 { 4421 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4422 struct ata_channel *ch = device_get_softc(dev); 4423 int ch_offset; 4424 int i; 4425 4426 ch_offset = ch->unit * 0x100; 4427 4428 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 4429 ch->r_io[i].res = ctlr->r_res2; 4430 4431 /* setup ATA registers */ 4432 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 4433 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 4434 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 4435 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 4436 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 4437 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 4438 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 4439 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 4440 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 4441 ata_default_registers(dev); 4442 4443 /* setup DMA registers */ 4444 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 4445 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 4446 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 4447 4448 /* setup SATA registers */ 4449 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 4450 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 4451 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 4452 4453 ch->flags |= ATA_NO_SLAVE; 4454 ata_pci_hw(dev); 4455 4456 /* chip does not reliably do 64K DMA transfers */ 4457 if (ch->dma) 4458 ch->dma->max_iosize = 126 * DEV_BSIZE; 4459 4460 return 0; 4461 } 4462 4463 static void 4464 ata_serverworks_setmode(device_t dev, int mode) 4465 { 4466 device_t gparent = GRANDPARENT(dev); 4467 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4468 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4469 struct ata_device *atadev = device_get_softc(dev); 4470 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4471 int offset = (devno ^ 0x01) << 3; 4472 int error; 4473 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 4474 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 4475 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 4476 4477 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4478 4479 mode = ata_check_80pin(dev, mode); 4480 4481 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4482 4483 if (bootverbose) 4484 device_printf(dev, "%ssetting %s on %s chip\n", 4485 (error) ? "FAILURE " : "", 4486 ata_mode2str(mode), ctlr->chip->text); 4487 if (!error) { 4488 if (mode >= ATA_UDMA0) { 4489 pci_write_config(gparent, 0x56, 4490 (pci_read_config(gparent, 0x56, 2) & 4491 ~(0xf << (devno << 2))) | 4492 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 4493 pci_write_config(gparent, 0x54, 4494 pci_read_config(gparent, 0x54, 1) | 4495 (0x01 << devno), 1); 4496 pci_write_config(gparent, 0x44, 4497 (pci_read_config(gparent, 0x44, 4) & 4498 ~(0xff << offset)) | 4499 (dmatimings[2] << offset), 4); 4500 } 4501 else if (mode >= ATA_WDMA0) { 4502 pci_write_config(gparent, 0x54, 4503 pci_read_config(gparent, 0x54, 1) & 4504 ~(0x01 << devno), 1); 4505 pci_write_config(gparent, 0x44, 4506 (pci_read_config(gparent, 0x44, 4) & 4507 ~(0xff << offset)) | 4508 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 4509 } 4510 else 4511 pci_write_config(gparent, 0x54, 4512 pci_read_config(gparent, 0x54, 1) & 4513 ~(0x01 << devno), 1); 4514 4515 pci_write_config(gparent, 0x40, 4516 (pci_read_config(gparent, 0x40, 4) & 4517 ~(0xff << offset)) | 4518 (piotimings[ata_mode2idx(mode)] << offset), 4); 4519 atadev->mode = mode; 4520 } 4521 } 4522 4523 4524 /* 4525 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 4526 */ 4527 int 4528 ata_sii_ident(device_t dev) 4529 { 4530 struct ata_pci_controller *ctlr = device_get_softc(dev); 4531 struct ata_chip_id *idx; 4532 static struct ata_chip_id ids[] = 4533 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" }, 4534 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" }, 4535 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4536 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4537 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" }, 4538 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4539 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4540 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" }, 4541 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" }, 4542 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" }, 4543 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" }, 4544 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" }, 4545 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" }, 4546 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" }, 4547 { 0, 0, 0, 0, 0, 0}}; 4548 char buffer[64]; 4549 4550 if (!(idx = ata_match_chip(dev, ids))) 4551 return ENXIO; 4552 4553 ksprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); 4554 device_set_desc_copy(dev, buffer); 4555 ctlr->chip = idx; 4556 ctlr->chipinit = ata_sii_chipinit; 4557 return 0; 4558 } 4559 4560 static int 4561 ata_sii_chipinit(device_t dev) 4562 { 4563 struct ata_pci_controller *ctlr = device_get_softc(dev); 4564 4565 if (ata_setup_interrupt(dev)) 4566 return ENXIO; 4567 4568 switch (ctlr->chip->cfg1) { 4569 case SIIPRBIO: 4570 ctlr->r_type1 = SYS_RES_MEMORY; 4571 ctlr->r_rid1 = PCIR_BAR(0); 4572 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 4573 &ctlr->r_rid1, RF_ACTIVE))){ 4574 ata_teardown_interrupt(dev); 4575 return ENXIO; 4576 } 4577 4578 ctlr->r_rid2 = PCIR_BAR(2); 4579 ctlr->r_type2 = SYS_RES_MEMORY; 4580 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4581 &ctlr->r_rid2, RF_ACTIVE))){ 4582 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 4583 ata_teardown_interrupt(dev); 4584 return ENXIO; 4585 } 4586 ctlr->allocate = ata_siiprb_allocate; 4587 ctlr->reset = ata_siiprb_reset; 4588 ctlr->dmainit = ata_siiprb_dmainit; 4589 ctlr->setmode = ata_sata_setmode; 4590 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2; 4591 4592 /* reset controller */ 4593 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 4594 DELAY(10000); 4595 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 4596 4597 /* enable PCI interrupt */ 4598 pci_write_config(dev, PCIR_COMMAND, 4599 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 4600 break; 4601 4602 case SIIMEMIO: 4603 ctlr->r_type2 = SYS_RES_MEMORY; 4604 ctlr->r_rid2 = PCIR_BAR(5); 4605 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4606 &ctlr->r_rid2, RF_ACTIVE))){ 4607 ata_teardown_interrupt(dev); 4608 return ENXIO; 4609 } 4610 4611 if (ctlr->chip->cfg2 & SIISETCLK) { 4612 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4613 pci_write_config(dev, 0x8a, 4614 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 4615 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4616 device_printf(dev, "%s could not set ATA133 clock\n", 4617 ctlr->chip->text); 4618 } 4619 4620 /* if we have 4 channels enable the second set */ 4621 if (ctlr->chip->cfg2 & SII4CH) { 4622 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 4623 ctlr->channels = 4; 4624 } 4625 4626 /* dont block interrupts from any channel */ 4627 pci_write_config(dev, 0x48, 4628 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 4629 4630 /* enable PCI interrupt as BIOS might not */ 4631 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 4632 4633 ctlr->allocate = ata_sii_allocate; 4634 if (ctlr->chip->max_dma >= ATA_SA150) { 4635 ctlr->reset = ata_sii_reset; 4636 ctlr->setmode = ata_sata_setmode; 4637 } 4638 else 4639 ctlr->setmode = ata_sii_setmode; 4640 break; 4641 4642 default: 4643 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 4644 device_printf(dev, "HW has secondary channel disabled\n"); 4645 ctlr->channels = 1; 4646 } 4647 4648 /* enable interrupt as BIOS might not */ 4649 pci_write_config(dev, 0x71, 0x01, 1); 4650 4651 ctlr->allocate = ata_cmd_allocate; 4652 ctlr->setmode = ata_cmd_setmode; 4653 break; 4654 } 4655 return 0; 4656 } 4657 4658 static int 4659 ata_cmd_allocate(device_t dev) 4660 { 4661 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4662 struct ata_channel *ch = device_get_softc(dev); 4663 4664 /* setup the usual register normal pci style */ 4665 if (ata_pci_allocate(dev)) 4666 return ENXIO; 4667 4668 if (ctlr->chip->cfg2 & SIIINTR) 4669 ch->hw.status = ata_cmd_status; 4670 4671 return 0; 4672 } 4673 4674 static int 4675 ata_cmd_status(device_t dev) 4676 { 4677 struct ata_channel *ch = device_get_softc(dev); 4678 u_int8_t reg71; 4679 4680 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) & 4681 (ch->unit ? 0x08 : 0x04))) { 4682 pci_write_config(device_get_parent(ch->dev), 0x71, 4683 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 4684 return ata_pci_status(dev); 4685 } 4686 return 0; 4687 } 4688 4689 static void 4690 ata_cmd_setmode(device_t dev, int mode) 4691 { 4692 device_t gparent = GRANDPARENT(dev); 4693 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4694 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4695 struct ata_device *atadev = device_get_softc(dev); 4696 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4697 int error; 4698 4699 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4700 4701 mode = ata_check_80pin(dev, mode); 4702 4703 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4704 4705 if (bootverbose) 4706 device_printf(dev, "%ssetting %s on %s chip\n", 4707 (error) ? "FAILURE " : "", 4708 ata_mode2str(mode), ctlr->chip->text); 4709 if (!error) { 4710 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 4711 int ureg = ch->unit ? 0x7b : 0x73; 4712 4713 if (mode >= ATA_UDMA0) { 4714 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 4715 { 0x11, 0x42 }, { 0x25, 0x8a }, 4716 { 0x15, 0x4a }, { 0x05, 0x0a } }; 4717 4718 u_int8_t umode = pci_read_config(gparent, ureg, 1); 4719 4720 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca); 4721 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)]; 4722 pci_write_config(gparent, ureg, umode, 1); 4723 } 4724 else if (mode >= ATA_WDMA0) { 4725 int dmatimings[] = { 0x87, 0x32, 0x3f }; 4726 4727 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1); 4728 pci_write_config(gparent, ureg, 4729 pci_read_config(gparent, ureg, 1) & 4730 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4731 } 4732 else { 4733 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f }; 4734 pci_write_config(gparent, treg, 4735 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1); 4736 pci_write_config(gparent, ureg, 4737 pci_read_config(gparent, ureg, 1) & 4738 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4739 } 4740 atadev->mode = mode; 4741 } 4742 } 4743 4744 static int 4745 ata_sii_allocate(device_t dev) 4746 { 4747 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4748 struct ata_channel *ch = device_get_softc(dev); 4749 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 4750 int i; 4751 4752 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 4753 ch->r_io[i].res = ctlr->r_res2; 4754 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 4755 } 4756 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 4757 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 4758 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 4759 ata_default_registers(dev); 4760 4761 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 4762 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 4763 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 4764 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 4765 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 4766 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 4767 4768 if (ctlr->chip->max_dma >= ATA_SA150) { 4769 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4770 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 4771 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4772 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 4773 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4774 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 4775 ch->flags |= ATA_NO_SLAVE; 4776 4777 /* enable PHY state change interrupt */ 4778 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 4779 } 4780 4781 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) { 4782 /* work around errata in early chips */ 4783 ch->dma->boundary = 16 * DEV_BSIZE; 4784 ch->dma->segsize = 15 * DEV_BSIZE; 4785 } 4786 4787 ata_pci_hw(dev); 4788 ch->hw.status = ata_sii_status; 4789 return 0; 4790 } 4791 4792 static int 4793 ata_sii_status(device_t dev) 4794 { 4795 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4796 struct ata_channel *ch = device_get_softc(dev); 4797 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 4798 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 4799 4800 /* do we have any PHY events ? */ 4801 if (ctlr->chip->max_dma >= ATA_SA150 && 4802 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 4803 ata_sata_phy_check_events(dev); 4804 4805 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 4806 return ata_pci_status(dev); 4807 else 4808 return 0; 4809 } 4810 4811 static void 4812 ata_sii_reset(device_t dev) 4813 { 4814 if (ata_sata_phy_reset(dev)) 4815 ata_generic_reset(dev); 4816 } 4817 4818 static void 4819 ata_sii_setmode(device_t dev, int mode) 4820 { 4821 device_t gparent = GRANDPARENT(dev); 4822 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4823 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4824 struct ata_device *atadev = device_get_softc(dev); 4825 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1); 4826 int mreg = ch->unit ? 0x84 : 0x80; 4827 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2); 4828 int mval = pci_read_config(gparent, mreg, 1) & ~mask; 4829 int error; 4830 4831 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4832 4833 if (ctlr->chip->cfg2 & SIISETCLK) { 4834 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) & 4835 (ch->unit ? 0x02 : 0x01))) { 4836 ata_print_cable(dev, "controller"); 4837 mode = ATA_UDMA2; 4838 } 4839 } 4840 else 4841 mode = ata_check_80pin(dev, mode); 4842 4843 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4844 4845 if (bootverbose) 4846 device_printf(dev, "%ssetting %s on %s chip\n", 4847 (error) ? "FAILURE " : "", 4848 ata_mode2str(mode), ctlr->chip->text); 4849 if (error) 4850 return; 4851 4852 if (mode >= ATA_UDMA0) { 4853 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 4854 u_int8_t ureg = 0xac + rego; 4855 4856 pci_write_config(gparent, mreg, 4857 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1); 4858 pci_write_config(gparent, ureg, 4859 (pci_read_config(gparent, ureg, 1) & ~0x3f) | 4860 udmatimings[mode & ATA_MODE_MASK], 1); 4861 4862 } 4863 else if (mode >= ATA_WDMA0) { 4864 u_int8_t dreg = 0xa8 + rego; 4865 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 4866 4867 pci_write_config(gparent, mreg, 4868 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1); 4869 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 4870 4871 } 4872 else { 4873 u_int8_t preg = 0xa4 + rego; 4874 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 4875 4876 pci_write_config(gparent, mreg, 4877 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1); 4878 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2); 4879 } 4880 atadev->mode = mode; 4881 } 4882 4883 struct ata_siiprb_dma_prdentry { 4884 u_int64_t addr; 4885 u_int32_t count; 4886 u_int32_t control; 4887 } __packed; 4888 4889 struct ata_siiprb_ata_command { 4890 u_int32_t reserved0; 4891 struct ata_siiprb_dma_prdentry prd[126]; 4892 } __packed; 4893 4894 struct ata_siiprb_atapi_command { 4895 u_int8_t cdb[16]; 4896 struct ata_siiprb_dma_prdentry prd[125]; 4897 } __packed; 4898 4899 struct ata_siiprb_command { 4900 u_int16_t control; 4901 u_int16_t protocol_override; 4902 u_int32_t transfer_count; 4903 u_int8_t fis[20]; 4904 union { 4905 struct ata_siiprb_ata_command ata; 4906 struct ata_siiprb_atapi_command atapi; 4907 } u; 4908 } __packed; 4909 4910 static int 4911 ata_siiprb_allocate(device_t dev) 4912 { 4913 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4914 struct ata_channel *ch = device_get_softc(dev); 4915 int offset = ch->unit * 0x2000; 4916 4917 /* set the SATA resources */ 4918 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4919 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 4920 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4921 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 4922 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4923 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 4924 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 4925 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 4926 4927 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 4928 ch->hw.end_transaction = ata_siiprb_end_transaction; 4929 ch->hw.status = ata_siiprb_status; 4930 ch->hw.command = NULL; /* not used here */ 4931 return 0; 4932 } 4933 4934 static int 4935 ata_siiprb_status(device_t dev) 4936 { 4937 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4938 struct ata_channel *ch = device_get_softc(dev); 4939 int offset = ch->unit * 0x2000; 4940 4941 if ((ATA_INL(ctlr->r_res1, 0x0044) & (1 << ch->unit))) { 4942 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 4943 4944 /* do we have any PHY events ? */ 4945 ata_sata_phy_check_events(dev); 4946 4947 /* clear interrupt(s) */ 4948 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 4949 4950 /* do we have any device action ? */ 4951 return (istatus & 0x00000001); 4952 } 4953 return 0; 4954 } 4955 4956 static int 4957 ata_siiprb_begin_transaction(struct ata_request *request) 4958 { 4959 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 4960 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4961 struct ata_siiprb_command *prb; 4962 int offset = ch->unit * 0x2000; 4963 u_int64_t prb_bus; 4964 int tag = 0, dummy; 4965 4966 /* check for 48 bit access and convert if needed */ 4967 ata_modify_if_48bit(request); 4968 4969 /* get a piece of the workspace for this request */ 4970 prb = (struct ata_siiprb_command *) 4971 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 4972 4973 /* set basic prd options ata/atapi etc etc */ 4974 bzero(prb, sizeof(struct ata_siiprb_command)); 4975 4976 /* setup the FIS for this request */ 4977 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 4978 device_printf(request->dev, "setting up SATA FIS failed\n"); 4979 request->result = EIO; 4980 return ATA_OP_FINISHED; 4981 } 4982 4983 /* if request moves data setup and load SG list */ 4984 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 4985 struct ata_siiprb_dma_prdentry *prd; 4986 4987 if (request->flags & ATA_R_ATAPI) 4988 prd = &prb->u.atapi.prd[0]; 4989 else 4990 prd = &prb->u.ata.prd[0]; 4991 if (ch->dma->load(ch->dev, request->data, request->bytecount, 4992 request->flags & ATA_R_READ, prd, &dummy)) { 4993 device_printf(request->dev, "setting up DMA failed\n"); 4994 request->result = EIO; 4995 return ATA_OP_FINISHED; 4996 } 4997 } 4998 4999 /* activate the prb */ 5000 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 5001 ATA_OUTL(ctlr->r_res2, 5002 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 5003 ATA_OUTL(ctlr->r_res2, 5004 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 5005 5006 /* start the timeout */ 5007 callout_reset(&request->callout, request->timeout * hz, 5008 (timeout_t*)ata_timeout, request); 5009 return ATA_OP_CONTINUES; 5010 } 5011 5012 static int 5013 ata_siiprb_end_transaction(struct ata_request *request) 5014 { 5015 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 5016 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 5017 struct ata_siiprb_command *prb; 5018 int offset = ch->unit * 0x2000; 5019 int error, tag = 0; 5020 5021 /* kill the timeout */ 5022 callout_stop(&request->callout); 5023 5024 prb = (struct ata_siiprb_command *) 5025 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 5026 5027 /* if error status get details */ 5028 request->status = prb->fis[2]; 5029 if (request->status & ATA_S_ERROR) 5030 request->error = prb->fis[3]; 5031 5032 /* update progress */ 5033 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 5034 if (request->flags & ATA_R_READ) 5035 request->donecount = prb->transfer_count; 5036 else 5037 request->donecount = request->bytecount; 5038 } 5039 5040 /* any controller errors flagged ? */ 5041 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 5042 kprintf("ata_siiprb_end_transaction %s error=%08x\n", 5043 ata_cmd2str(request), error); 5044 } 5045 5046 /* release SG list etc */ 5047 ch->dma->unload(ch->dev); 5048 5049 return ATA_OP_FINISHED; 5050 } 5051 5052 static void 5053 ata_siiprb_reset(device_t dev) 5054 { 5055 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5056 struct ata_channel *ch = device_get_softc(dev); 5057 int offset = ch->unit * 0x2000; 5058 struct ata_siiprb_command *prb; 5059 u_int64_t prb_bus; 5060 u_int32_t status, signature; 5061 int timeout, tag = 0; 5062 5063 /* reset channel HW */ 5064 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 5065 DELAY(1000); 5066 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 5067 DELAY(10000); 5068 5069 /* poll for channel ready */ 5070 for (timeout = 0; timeout < 1000; timeout++) { 5071 if ((status = ATA_INL(ctlr->r_res2, 0x1000 + offset)) & 0x00040000) 5072 break; 5073 DELAY(1000); 5074 } 5075 if (timeout >= 1000) { 5076 device_printf(ch->dev, "channel HW reset timeout reset failure\n"); 5077 ch->devices = 0; 5078 goto finish; 5079 } 5080 if (bootverbose) 5081 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout * 1); 5082 5083 /* reset phy */ 5084 if (!ata_sata_phy_reset(dev)) { 5085 if (bootverbose) 5086 device_printf(ch->dev, "phy reset found no device\n"); 5087 ch->devices = 0; 5088 goto finish; 5089 } 5090 5091 /* get a piece of the workspace for a soft reset request */ 5092 prb = (struct ata_siiprb_command *) 5093 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 5094 bzero(prb, sizeof(struct ata_siiprb_command)); 5095 prb->control = htole16(0x0080); 5096 5097 /* activate the soft reset prb */ 5098 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 5099 ATA_OUTL(ctlr->r_res2, 5100 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 5101 ATA_OUTL(ctlr->r_res2, 5102 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 5103 5104 /* poll for channel ready */ 5105 for (timeout = 0; timeout < 1000; timeout++) { 5106 DELAY(1000); 5107 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 5108 break; 5109 } 5110 if (timeout >= 1000) { 5111 device_printf(ch->dev, "reset timeout - no device found\n"); 5112 ch->devices = 0; 5113 goto finish; 5114 } 5115 if (bootverbose) 5116 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n", 5117 timeout, status); 5118 5119 /* find out whats there */ 5120 prb = (struct ata_siiprb_command *) 5121 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 5122 signature = 5123 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 5124 if (bootverbose) 5125 device_printf(ch->dev, "signature=%08x\n", signature); 5126 switch (signature) { 5127 case 0xeb140101: 5128 ch->devices = ATA_ATAPI_MASTER; 5129 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n"); 5130 ch->devices = 0; 5131 break; 5132 case 0x96690101: 5133 ch->devices = ATA_PORTMULTIPLIER; 5134 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 5135 ch->devices = 0; 5136 break; 5137 case 0x00000101: 5138 ch->devices = ATA_ATA_MASTER; 5139 break; 5140 default: 5141 ch->devices = 0; 5142 } 5143 5144 finish: 5145 /* clear interrupt(s) */ 5146 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 5147 5148 /* require explicit interrupt ack */ 5149 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 5150 5151 /* 64bit mode */ 5152 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 5153 5154 /* enable interrupts wanted */ 5155 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 5156 } 5157 5158 static void 5159 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 5160 { 5161 struct ata_dmasetprd_args *args = xsc; 5162 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 5163 int i; 5164 5165 if ((args->error = error)) 5166 return; 5167 5168 for (i = 0; i < nsegs; i++) { 5169 prd[i].addr = htole64(segs[i].ds_addr); 5170 prd[i].count = htole32(segs[i].ds_len); 5171 } 5172 prd[i - 1].control = htole32(ATA_DMA_EOT); 5173 } 5174 5175 static void 5176 ata_siiprb_dmainit(device_t dev) 5177 { 5178 struct ata_channel *ch = device_get_softc(dev); 5179 5180 ata_dmainit(dev); 5181 if (ch->dma) { 5182 /* note start and stop are not used here */ 5183 ch->dma->setprd = ata_siiprb_dmasetprd; 5184 ch->dma->max_address = BUS_SPACE_MAXADDR; 5185 } 5186 } 5187 5188 5189 /* 5190 * Silicon Integrated Systems Corp. (SiS) chipset support functions 5191 */ 5192 int 5193 ata_sis_ident(device_t dev) 5194 { 5195 struct ata_pci_controller *ctlr = device_get_softc(dev); 5196 struct ata_chip_id *idx; 5197 static struct ata_chip_id ids[] = 5198 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */ 5199 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */ 5200 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */ 5201 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */ 5202 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */ 5203 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */ 5204 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */ 5205 5206 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */ 5207 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */ 5208 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */ 5209 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */ 5210 5211 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */ 5212 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */ 5213 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */ 5214 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */ 5215 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */ 5216 5217 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" }, 5218 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" }, 5219 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" }, 5220 5221 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" }, 5222 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" }, 5223 { 0, 0, 0, 0, 0, 0 }}; 5224 char buffer[64]; 5225 int found = 0; 5226 5227 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev)))) 5228 return ENXIO; 5229 5230 if (idx->cfg2 && !found) { 5231 u_int8_t reg57 = pci_read_config(dev, 0x57, 1); 5232 5233 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1); 5234 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) { 5235 found = 1; 5236 idx->cfg1 = SIS133NEW; 5237 idx->max_dma = ATA_UDMA6; 5238 ksprintf(buffer, "SiS 962/963 %s controller", 5239 ata_mode2str(idx->max_dma)); 5240 } 5241 pci_write_config(dev, 0x57, reg57, 1); 5242 } 5243 if (idx->cfg2 && !found) { 5244 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1); 5245 5246 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1); 5247 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) { 5248 struct ata_chip_id id[] = 5249 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }}; 5250 5251 found = 1; 5252 if (ata_find_chip(dev, id, pci_get_slot(dev))) { 5253 idx->cfg1 = SIS133OLD; 5254 idx->max_dma = ATA_UDMA6; 5255 } 5256 else { 5257 idx->cfg1 = SIS100NEW; 5258 idx->max_dma = ATA_UDMA5; 5259 } 5260 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma)); 5261 } 5262 pci_write_config(dev, 0x4a, reg4a, 1); 5263 } 5264 if (!found) 5265 ksprintf(buffer,"SiS %s %s controller", 5266 idx->text, ata_mode2str(idx->max_dma)); 5267 5268 device_set_desc_copy(dev, buffer); 5269 ctlr->chip = idx; 5270 ctlr->chipinit = ata_sis_chipinit; 5271 return 0; 5272 } 5273 5274 static int 5275 ata_sis_chipinit(device_t dev) 5276 { 5277 struct ata_pci_controller *ctlr = device_get_softc(dev); 5278 5279 if (ata_setup_interrupt(dev)) 5280 return ENXIO; 5281 5282 switch (ctlr->chip->cfg1) { 5283 case SIS33: 5284 break; 5285 case SIS66: 5286 case SIS100OLD: 5287 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1); 5288 break; 5289 case SIS100NEW: 5290 case SIS133OLD: 5291 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1); 5292 break; 5293 case SIS133NEW: 5294 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2); 5295 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2); 5296 break; 5297 case SISSATA: 5298 ctlr->r_type2 = SYS_RES_IOPORT; 5299 ctlr->r_rid2 = PCIR_BAR(5); 5300 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5301 &ctlr->r_rid2, RF_ACTIVE))) { 5302 ctlr->allocate = ata_sis_allocate; 5303 ctlr->reset = ata_sis_reset; 5304 5305 /* enable PCI interrupt */ 5306 pci_write_config(dev, PCIR_COMMAND, 5307 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5308 } 5309 ctlr->setmode = ata_sata_setmode; 5310 return 0; 5311 default: 5312 ata_teardown_interrupt(dev); 5313 return ENXIO; 5314 } 5315 ctlr->setmode = ata_sis_setmode; 5316 return 0; 5317 } 5318 5319 static int 5320 ata_sis_allocate(device_t dev) 5321 { 5322 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5323 struct ata_channel *ch = device_get_softc(dev); 5324 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6); 5325 5326 /* setup the usual register normal pci style */ 5327 if (ata_pci_allocate(dev)) 5328 return ENXIO; 5329 5330 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5331 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; 5332 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5333 ch->r_io[ATA_SERROR].offset = 0x04 + offset; 5334 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5335 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; 5336 ch->flags |= ATA_NO_SLAVE; 5337 5338 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ 5339 /* XXX SOS unknown how to enable PHY state change interrupt */ 5340 return 0; 5341 } 5342 5343 static void 5344 ata_sis_reset(device_t dev) 5345 { 5346 if (ata_sata_phy_reset(dev)) 5347 ata_generic_reset(dev); 5348 } 5349 5350 static void 5351 ata_sis_setmode(device_t dev, int mode) 5352 { 5353 device_t gparent = GRANDPARENT(dev); 5354 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5355 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5356 struct ata_device *atadev = device_get_softc(dev); 5357 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5358 int error; 5359 5360 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5361 5362 if (ctlr->chip->cfg1 == SIS133NEW) { 5363 if (mode > ATA_UDMA2 && 5364 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) { 5365 ata_print_cable(dev, "controller"); 5366 mode = ATA_UDMA2; 5367 } 5368 } 5369 else { 5370 if (mode > ATA_UDMA2 && 5371 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) { 5372 ata_print_cable(dev, "controller"); 5373 mode = ATA_UDMA2; 5374 } 5375 } 5376 5377 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5378 5379 if (bootverbose) 5380 device_printf(dev, "%ssetting %s on %s chip\n", 5381 (error) ? "FAILURE " : "", 5382 ata_mode2str(mode), ctlr->chip->text); 5383 if (!error) { 5384 switch (ctlr->chip->cfg1) { 5385 case SIS133NEW: { 5386 u_int32_t timings[] = 5387 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 5388 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 5389 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; 5390 u_int32_t reg; 5391 5392 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); 5393 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4); 5394 break; 5395 } 5396 case SIS133OLD: { 5397 u_int16_t timings[] = 5398 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 5399 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; 5400 5401 u_int16_t reg = 0x40 + (devno << 1); 5402 5403 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5404 break; 5405 } 5406 case SIS100NEW: { 5407 u_int16_t timings[] = 5408 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 5409 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; 5410 u_int16_t reg = 0x40 + (devno << 1); 5411 5412 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5413 break; 5414 } 5415 case SIS100OLD: 5416 case SIS66: 5417 case SIS33: { 5418 u_int16_t timings[] = 5419 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 5420 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; 5421 u_int16_t reg = 0x40 + (devno << 1); 5422 5423 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5424 break; 5425 } 5426 } 5427 atadev->mode = mode; 5428 } 5429 } 5430 5431 5432 /* VIA Technologies Inc. chipset support functions */ 5433 int 5434 ata_via_ident(device_t dev) 5435 { 5436 struct ata_pci_controller *ctlr = device_get_softc(dev); 5437 struct ata_chip_id *idx; 5438 static struct ata_chip_id ids[] = 5439 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 5440 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 5441 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 5442 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 5443 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 5444 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 5445 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 5446 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 5447 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 5448 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 5449 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 5450 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 5451 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 5452 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 5453 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 5454 { 0, 0, 0, 0, 0, 0 }}; 5455 static struct ata_chip_id new_ids[] = 5456 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 5457 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 5458 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 5459 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 5460 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" }, 5461 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" }, 5462 { 0, 0, 0, 0, 0, 0 }}; 5463 char buffer[64]; 5464 5465 if (pci_get_devid(dev) == ATA_VIA82C571) { 5466 if (!(idx = ata_find_chip(dev, ids, -99))) 5467 return ENXIO; 5468 } 5469 else { 5470 if (!(idx = ata_match_chip(dev, new_ids))) 5471 return ENXIO; 5472 } 5473 5474 ksprintf(buffer, "VIA %s %s controller", 5475 idx->text, ata_mode2str(idx->max_dma)); 5476 device_set_desc_copy(dev, buffer); 5477 ctlr->chip = idx; 5478 ctlr->chipinit = ata_via_chipinit; 5479 return 0; 5480 } 5481 5482 static int 5483 ata_via_chipinit(device_t dev) 5484 { 5485 struct ata_pci_controller *ctlr = device_get_softc(dev); 5486 5487 if (ata_setup_interrupt(dev)) 5488 return ENXIO; 5489 5490 if (ctlr->chip->max_dma >= ATA_SA150) { 5491 /* do we have AHCI capability ? */ 5492 if ((ctlr->chip->cfg2 == VIAAHCI) && ata_ahci_chipinit(dev) != ENXIO) 5493 return 0; 5494 5495 ctlr->r_type2 = SYS_RES_IOPORT; 5496 ctlr->r_rid2 = PCIR_BAR(5); 5497 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5498 &ctlr->r_rid2, RF_ACTIVE))) { 5499 ctlr->allocate = ata_via_allocate; 5500 ctlr->reset = ata_via_reset; 5501 5502 /* enable PCI interrupt */ 5503 pci_write_config(dev, PCIR_COMMAND, 5504 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5505 } 5506 5507 if (ctlr->chip->cfg2 & VIABAR) { 5508 ctlr->channels = 3; 5509 ctlr->setmode = ata_via_setmode; 5510 } 5511 else 5512 ctlr->setmode = ata_sata_setmode; 5513 return 0; 5514 } 5515 5516 /* prepare for ATA-66 on the 82C686a and 82C596b */ 5517 if (ctlr->chip->cfg2 & VIACLK) 5518 pci_write_config(dev, 0x50, 0x030b030b, 4); 5519 5520 /* the southbridge might need the data corruption fix */ 5521 if (ctlr->chip->cfg2 & VIABUG) 5522 ata_via_southbridge_fixup(dev); 5523 5524 /* set fifo configuration half'n'half */ 5525 pci_write_config(dev, 0x43, 5526 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 5527 5528 /* set status register read retry */ 5529 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 5530 5531 /* set DMA read & end-of-sector fifo flush */ 5532 pci_write_config(dev, 0x46, 5533 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 5534 5535 /* set sector size */ 5536 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 5537 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 5538 5539 ctlr->setmode = ata_via_family_setmode; 5540 return 0; 5541 } 5542 5543 static int 5544 ata_via_allocate(device_t dev) 5545 { 5546 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5547 struct ata_channel *ch = device_get_softc(dev); 5548 5549 /* newer SATA chips has resources in one BAR for each channel */ 5550 if (ctlr->chip->cfg2 & VIABAR) { 5551 struct resource *r_io; 5552 int i, rid; 5553 5554 rid = PCIR_BAR(ch->unit); 5555 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 5556 SYS_RES_IOPORT, 5557 &rid, RF_ACTIVE))) 5558 return ENXIO; 5559 5560 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 5561 ch->r_io[i].res = r_io; 5562 ch->r_io[i].offset = i; 5563 } 5564 ch->r_io[ATA_CONTROL].res = r_io; 5565 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 5566 ch->r_io[ATA_IDX_ADDR].res = r_io; 5567 ata_default_registers(dev); 5568 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 5569 ch->r_io[i].res = ctlr->r_res1; 5570 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 5571 } 5572 ata_pci_hw(dev); 5573 if (ch->unit >= 2) 5574 return 0; 5575 } 5576 else { 5577 /* setup the usual register normal pci style */ 5578 if (ata_pci_allocate(dev)) 5579 return ENXIO; 5580 } 5581 5582 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5583 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 5584 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5585 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 5586 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5587 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 5588 ch->flags |= ATA_NO_SLAVE; 5589 5590 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */ 5591 /* XXX SOS unknown how to enable PHY state change interrupt */ 5592 return 0; 5593 } 5594 5595 static void 5596 ata_via_reset(device_t dev) 5597 { 5598 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5599 struct ata_channel *ch = device_get_softc(dev); 5600 5601 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 5602 ata_generic_reset(dev); 5603 else 5604 if (ata_sata_phy_reset(dev)) 5605 ata_generic_reset(dev); 5606 } 5607 5608 static void 5609 ata_via_setmode(device_t dev, int mode) 5610 { 5611 device_t gparent = GRANDPARENT(dev); 5612 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5613 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5614 struct ata_device *atadev = device_get_softc(dev); 5615 int error; 5616 5617 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 5618 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20, 5619 0x65, 0x32, 0x20, 5620 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5621 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 5622 5623 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6)); 5624 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5625 if (bootverbose) 5626 device_printf(dev, "%ssetting %s on %s chip\n", 5627 (error) ? "FAILURE " : "", ata_mode2str(mode), 5628 ctlr->chip->text); 5629 if (!error) { 5630 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1); 5631 if (mode >= ATA_UDMA0) 5632 pci_write_config(gparent, 0xb3, 5633 dma_timings[mode & ATA_MODE_MASK], 1); 5634 atadev->mode = mode; 5635 } 5636 } 5637 else 5638 ata_sata_setmode(dev, mode); 5639 } 5640 5641 static void 5642 ata_via_southbridge_fixup(device_t dev) 5643 { 5644 device_t *children; 5645 int nchildren, i; 5646 5647 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5648 return; 5649 5650 for (i = 0; i < nchildren; i++) { 5651 if (pci_get_devid(children[i]) == ATA_VIA8363 || 5652 pci_get_devid(children[i]) == ATA_VIA8371 || 5653 pci_get_devid(children[i]) == ATA_VIA8662 || 5654 pci_get_devid(children[i]) == ATA_VIA8361) { 5655 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 5656 5657 if ((reg76 & 0xf0) != 0xd0) { 5658 device_printf(dev, 5659 "Correcting VIA config for southbridge data corruption bug\n"); 5660 pci_write_config(children[i], 0x75, 0x80, 1); 5661 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 5662 } 5663 break; 5664 } 5665 } 5666 kfree(children, M_TEMP); 5667 } 5668 5669 5670 /* common code for VIA, AMD & nVidia */ 5671 static void 5672 ata_via_family_setmode(device_t dev, int mode) 5673 { 5674 device_t gparent = GRANDPARENT(dev); 5675 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5676 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5677 struct ata_device *atadev = device_get_softc(dev); 5678 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20, 5679 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5680 int modes[][7] = { 5681 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 5682 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 5683 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 5684 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */ 5685 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */ 5686 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5687 int reg = 0x53 - devno; 5688 int error; 5689 5690 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5691 5692 if (ctlr->chip->cfg2 & AMDCABLE) { 5693 if (mode > ATA_UDMA2 && 5694 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) { 5695 ata_print_cable(dev, "controller"); 5696 mode = ATA_UDMA2; 5697 } 5698 } 5699 else 5700 mode = ata_check_80pin(dev, mode); 5701 5702 if (ctlr->chip->cfg2 & NVIDIA) 5703 reg += 0x10; 5704 5705 if (ctlr->chip->cfg1 != VIA133) 5706 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1); 5707 5708 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5709 5710 if (bootverbose) 5711 device_printf(dev, "%ssetting %s on %s chip\n", 5712 (error) ? "FAILURE " : "", ata_mode2str(mode), 5713 ctlr->chip->text); 5714 if (!error) { 5715 if (mode >= ATA_UDMA0) 5716 pci_write_config(gparent, reg, 5717 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 5718 else 5719 pci_write_config(gparent, reg, 0x8b, 1); 5720 atadev->mode = mode; 5721 } 5722 } 5723 5724 5725 /* misc functions */ 5726 static struct ata_chip_id * 5727 ata_match_chip(device_t dev, struct ata_chip_id *index) 5728 { 5729 while (index->chipid != 0) { 5730 if (pci_get_devid(dev) == index->chipid && 5731 pci_get_revid(dev) >= index->chiprev) 5732 return index; 5733 index++; 5734 } 5735 return NULL; 5736 } 5737 5738 static struct ata_chip_id * 5739 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot) 5740 { 5741 device_t *children; 5742 int nchildren, i; 5743 5744 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5745 return 0; 5746 5747 while (index->chipid != 0) { 5748 for (i = 0; i < nchildren; i++) { 5749 if (((slot >= 0 && pci_get_slot(children[i]) == slot) || 5750 (slot < 0 && pci_get_slot(children[i]) <= -slot)) && 5751 pci_get_devid(children[i]) == index->chipid && 5752 pci_get_revid(children[i]) >= index->chiprev) { 5753 kfree(children, M_TEMP); 5754 return index; 5755 } 5756 } 5757 index++; 5758 } 5759 kfree(children, M_TEMP); 5760 return NULL; 5761 } 5762 5763 static int 5764 ata_setup_interrupt(device_t dev) 5765 { 5766 struct ata_pci_controller *ctlr = device_get_softc(dev); 5767 int rid = ATA_IRQ_RID; 5768 5769 if (!ctlr->legacy) { 5770 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 5771 RF_SHAREABLE | RF_ACTIVE))) { 5772 device_printf(dev, "unable to map interrupt\n"); 5773 return ENXIO; 5774 } 5775 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 5776 ata_generic_intr, ctlr, &ctlr->handle, NULL))) { 5777 device_printf(dev, "unable to setup interrupt\n"); 5778 bus_release_resource(dev, SYS_RES_IRQ, rid, ctlr->r_irq); 5779 ctlr->r_irq = 0; 5780 return ENXIO; 5781 } 5782 } 5783 return 0; 5784 } 5785 5786 static void 5787 ata_teardown_interrupt(device_t dev) 5788 { 5789 struct ata_pci_controller *ctlr = device_get_softc(dev); 5790 5791 if (!ctlr->legacy) { 5792 if (ctlr->r_irq) { 5793 bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle); 5794 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ctlr->r_irq); 5795 ctlr->r_irq = 0; 5796 } 5797 } 5798 } 5799 5800 struct ata_serialize { 5801 struct spinlock locked_mtx; 5802 int locked_ch; 5803 int restart_ch; 5804 }; 5805 5806 static int 5807 ata_serialize(device_t dev, int flags) 5808 { 5809 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5810 struct ata_channel *ch = device_get_softc(dev); 5811 struct ata_serialize *serial; 5812 static int inited = 0; 5813 int res; 5814 5815 if (!inited) { 5816 serial = kmalloc(sizeof(struct ata_serialize), 5817 M_TEMP, M_INTWAIT | M_ZERO); 5818 spin_init(&serial->locked_mtx); 5819 serial->locked_ch = -1; 5820 serial->restart_ch = -1; 5821 device_set_ivars(ctlr->dev, serial); 5822 inited = 1; 5823 } 5824 else 5825 serial = device_get_ivars(ctlr->dev); 5826 5827 spin_lock(&serial->locked_mtx); 5828 switch (flags) { 5829 case ATA_LF_LOCK: 5830 if (serial->locked_ch == -1) 5831 serial->locked_ch = ch->unit; 5832 if (serial->locked_ch != ch->unit) 5833 serial->restart_ch = ch->unit; 5834 break; 5835 5836 case ATA_LF_UNLOCK: 5837 if (serial->locked_ch == ch->unit) { 5838 serial->locked_ch = -1; 5839 if (serial->restart_ch != -1) { 5840 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) { 5841 serial->restart_ch = -1; 5842 spin_unlock(&serial->locked_mtx); 5843 ata_start(ch->dev); 5844 return -1; 5845 } 5846 } 5847 } 5848 break; 5849 5850 case ATA_LF_WHICH: 5851 break; 5852 } 5853 res = serial->locked_ch; 5854 spin_unlock(&serial->locked_mtx); 5855 return res; 5856 } 5857 5858 static void 5859 ata_print_cable(device_t dev, u_int8_t *who) 5860 { 5861 device_printf(dev, 5862 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who); 5863 } 5864 5865 static int 5866 ata_atapi(device_t dev) 5867 { 5868 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5869 struct ata_device *atadev = device_get_softc(dev); 5870 5871 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || 5872 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE)); 5873 } 5874 5875 static int 5876 ata_check_80pin(device_t dev, int mode) 5877 { 5878 struct ata_device *atadev = device_get_softc(dev); 5879 5880 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) { 5881 ata_print_cable(dev, "device"); 5882 mode = ATA_UDMA2; 5883 } 5884 return mode; 5885 } 5886 5887 static int 5888 ata_mode2idx(int mode) 5889 { 5890 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) 5891 return (mode & ATA_MODE_MASK) + 8; 5892 if ((mode & ATA_DMA_MASK) == ATA_WDMA0) 5893 return (mode & ATA_MODE_MASK) + 5; 5894 return (mode & ATA_MODE_MASK) - ATA_PIO0; 5895 } 5896