1 /*- 2 * Copyright (c) 1998 - 2006 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.196 2007/04/08 19:18:51 sos Exp $ 27 * $DragonFly: src/sys/dev/disk/nata/ata-chipset.c,v 1.13 2008/03/24 06:41:56 dillon Exp $ 28 */ 29 30 #include "opt_ata.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/bus_dma.h> 35 #include <sys/bus_resource.h> 36 #include <sys/callout.h> 37 #include <sys/endian.h> 38 #include <sys/libkern.h> 39 #include <sys/lock.h> /* for {get,rel}_mplock() */ 40 #include <sys/malloc.h> 41 #include <sys/nata.h> 42 #include <sys/queue.h> 43 #include <sys/rman.h> 44 #include <sys/spinlock.h> 45 #include <sys/spinlock2.h> 46 #include <sys/systm.h> 47 #include <sys/taskqueue.h> 48 49 #include <machine/bus_dma.h> 50 51 #include <bus/pci/pcireg.h> 52 #include <bus/pci/pcivar.h> 53 54 #include "ata-all.h" 55 #include "ata-pci.h" 56 #include "ata_if.h" 57 58 /* local prototypes */ 59 /* ata-chipset.c */ 60 static int ata_generic_chipinit(device_t dev); 61 static void ata_generic_intr(void *data); 62 static void ata_generic_setmode(device_t dev, int mode); 63 static void ata_sata_phy_check_events(device_t dev); 64 static void ata_sata_phy_event(void *context, int dummy); 65 static int ata_sata_phy_reset(device_t dev); 66 static int ata_sata_connect(struct ata_channel *ch); 67 static void ata_sata_setmode(device_t dev, int mode); 68 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); 69 static int ata_ahci_chipinit(device_t dev); 70 static int ata_ahci_allocate(device_t dev); 71 static int ata_ahci_status(device_t dev); 72 static int ata_ahci_begin_transaction(struct ata_request *request); 73 static int ata_ahci_end_transaction(struct ata_request *request); 74 static void ata_ahci_reset(device_t dev); 75 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 76 static void ata_ahci_dmainit(device_t dev); 77 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request); 78 static int ata_acard_chipinit(device_t dev); 79 static int ata_acard_allocate(device_t dev); 80 static int ata_acard_status(device_t dev); 81 static void ata_acard_850_setmode(device_t dev, int mode); 82 static void ata_acard_86X_setmode(device_t dev, int mode); 83 static int ata_ali_chipinit(device_t dev); 84 static int ata_ali_allocate(device_t dev); 85 static int ata_ali_sata_allocate(device_t dev); 86 static void ata_ali_reset(device_t dev); 87 static void ata_ali_setmode(device_t dev, int mode); 88 static int ata_amd_chipinit(device_t dev); 89 static int ata_ati_chipinit(device_t dev); 90 static void ata_ati_setmode(device_t dev, int mode); 91 static int ata_cyrix_chipinit(device_t dev); 92 static void ata_cyrix_setmode(device_t dev, int mode); 93 static int ata_cypress_chipinit(device_t dev); 94 static void ata_cypress_setmode(device_t dev, int mode); 95 static int ata_highpoint_chipinit(device_t dev); 96 static int ata_highpoint_allocate(device_t dev); 97 static void ata_highpoint_setmode(device_t dev, int mode); 98 static int ata_highpoint_check_80pin(device_t dev, int mode); 99 static int ata_intel_chipinit(device_t dev); 100 static int ata_intel_allocate(device_t dev); 101 static void ata_intel_reset(device_t dev); 102 static void ata_intel_old_setmode(device_t dev, int mode); 103 static void ata_intel_new_setmode(device_t dev, int mode); 104 static int ata_intel_31244_allocate(device_t dev); 105 static int ata_intel_31244_status(device_t dev); 106 static int ata_intel_31244_command(struct ata_request *request); 107 static void ata_intel_31244_reset(device_t dev); 108 static int ata_ite_chipinit(device_t dev); 109 static void ata_ite_setmode(device_t dev, int mode); 110 static int ata_jmicron_chipinit(device_t dev); 111 static int ata_jmicron_allocate(device_t dev); 112 static void ata_jmicron_reset(device_t dev); 113 static void ata_jmicron_dmainit(device_t dev); 114 static void ata_jmicron_setmode(device_t dev, int mode); 115 static int ata_marvell_pata_chipinit(device_t dev); 116 static int ata_marvell_pata_allocate(device_t dev); 117 static void ata_marvell_pata_setmode(device_t dev, int mode); 118 static int ata_marvell_edma_chipinit(device_t dev); 119 static int ata_marvell_edma_allocate(device_t dev); 120 static int ata_marvell_edma_status(device_t dev); 121 static int ata_marvell_edma_begin_transaction(struct ata_request *request); 122 static int ata_marvell_edma_end_transaction(struct ata_request *request); 123 static void ata_marvell_edma_reset(device_t dev); 124 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 125 static void ata_marvell_edma_dmainit(device_t dev); 126 static int ata_national_chipinit(device_t dev); 127 static void ata_national_setmode(device_t dev, int mode); 128 static int ata_netcell_chipinit(device_t dev); 129 static int ata_netcell_allocate(device_t dev); 130 static int ata_nvidia_chipinit(device_t dev); 131 static int ata_nvidia_allocate(device_t dev); 132 static int ata_nvidia_status(device_t dev); 133 static void ata_nvidia_reset(device_t dev); 134 static int ata_promise_chipinit(device_t dev); 135 static int ata_promise_allocate(device_t dev); 136 static int ata_promise_status(device_t dev); 137 static int ata_promise_dmastart(device_t dev); 138 static int ata_promise_dmastop(device_t dev); 139 static void ata_promise_dmareset(device_t dev); 140 static void ata_promise_dmainit(device_t dev); 141 static void ata_promise_setmode(device_t dev, int mode); 142 static int ata_promise_tx2_allocate(device_t dev); 143 static int ata_promise_tx2_status(device_t dev); 144 static int ata_promise_mio_allocate(device_t dev); 145 static void ata_promise_mio_intr(void *data); 146 static int ata_promise_mio_status(device_t dev); 147 static int ata_promise_mio_command(struct ata_request *request); 148 static void ata_promise_mio_reset(device_t dev); 149 static void ata_promise_mio_dmainit(device_t dev); 150 static void ata_promise_mio_setmode(device_t dev, int mode); 151 static void ata_promise_sx4_intr(void *data); 152 static int ata_promise_sx4_command(struct ata_request *request); 153 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 154 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 155 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 156 static int ata_serverworks_chipinit(device_t dev); 157 static int ata_serverworks_allocate(device_t dev); 158 static void ata_serverworks_setmode(device_t dev, int mode); 159 static int ata_sii_chipinit(device_t dev); 160 static int ata_cmd_allocate(device_t dev); 161 static int ata_cmd_status(device_t dev); 162 static void ata_cmd_setmode(device_t dev, int mode); 163 static int ata_sii_allocate(device_t dev); 164 static int ata_sii_status(device_t dev); 165 static void ata_sii_reset(device_t dev); 166 static void ata_sii_setmode(device_t dev, int mode); 167 static int ata_siiprb_allocate(device_t dev); 168 static int ata_siiprb_status(device_t dev); 169 static int ata_siiprb_begin_transaction(struct ata_request *request); 170 static int ata_siiprb_end_transaction(struct ata_request *request); 171 static void ata_siiprb_reset(device_t dev); 172 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 173 static void ata_siiprb_dmainit(device_t dev); 174 static int ata_sis_chipinit(device_t dev); 175 static int ata_sis_allocate(device_t dev); 176 static void ata_sis_reset(device_t dev); 177 static void ata_sis_setmode(device_t dev, int mode); 178 static int ata_via_chipinit(device_t dev); 179 static int ata_via_allocate(device_t dev); 180 static void ata_via_reset(device_t dev); 181 static void ata_via_setmode(device_t dev, int mode); 182 static void ata_via_southbridge_fixup(device_t dev); 183 static void ata_via_family_setmode(device_t dev, int mode); 184 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index); 185 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot); 186 static int ata_setup_interrupt(device_t dev); 187 static int ata_serialize(device_t dev, int flags); 188 static void ata_print_cable(device_t dev, u_int8_t *who); 189 static int ata_atapi(device_t dev); 190 static int ata_check_80pin(device_t dev, int mode); 191 static int ata_mode2idx(int mode); 192 193 194 /* 195 * generic ATA support functions 196 */ 197 int 198 ata_generic_ident(device_t dev) 199 { 200 struct ata_pci_controller *ctlr = device_get_softc(dev); 201 char buffer[64]; 202 203 ksnprintf(buffer, sizeof(buffer), 204 "%s ATA controller", ata_pcivendor2str(dev)); 205 device_set_desc_copy(dev, buffer); 206 ctlr->chipinit = ata_generic_chipinit; 207 return 0; 208 } 209 210 static int 211 ata_generic_chipinit(device_t dev) 212 { 213 struct ata_pci_controller *ctlr = device_get_softc(dev); 214 215 if (ata_setup_interrupt(dev)) 216 return ENXIO; 217 ctlr->setmode = ata_generic_setmode; 218 return 0; 219 } 220 221 static void 222 ata_generic_intr(void *data) 223 { 224 struct ata_pci_controller *ctlr = data; 225 struct ata_channel *ch; 226 int unit; 227 228 for (unit = 0; unit < ctlr->channels; unit++) { 229 if ((ch = ctlr->interrupt[unit].argument)) 230 ctlr->interrupt[unit].function(ch); 231 } 232 } 233 234 static void 235 ata_generic_setmode(device_t dev, int mode) 236 { 237 struct ata_device *atadev = device_get_softc(dev); 238 239 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 240 mode = ata_check_80pin(dev, mode); 241 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 242 atadev->mode = mode; 243 } 244 245 246 /* 247 * SATA support functions 248 */ 249 static void 250 ata_sata_phy_check_events(device_t dev) 251 { 252 struct ata_channel *ch = device_get_softc(dev); 253 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR); 254 255 /* clear error bits/interrupt */ 256 ATA_IDX_OUTL(ch, ATA_SERROR, error); 257 258 /* do we have any events flagged ? */ 259 if (error) { 260 struct ata_connect_task *tp; 261 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS); 262 263 /* if we have a connection event deal with it */ 264 if ((error & ATA_SE_PHY_CHANGED) && 265 (tp = (struct ata_connect_task *) 266 kmalloc(sizeof(struct ata_connect_task), 267 M_ATA, M_INTWAIT | M_ZERO))) { 268 269 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) || 270 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) { 271 if (bootverbose) 272 device_printf(ch->dev, "CONNECT requested\n"); 273 tp->action = ATA_C_ATTACH; 274 } 275 else { 276 if (bootverbose) 277 device_printf(ch->dev, "DISCONNECT requested\n"); 278 tp->action = ATA_C_DETACH; 279 } 280 tp->dev = ch->dev; 281 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 282 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 283 } 284 } 285 } 286 287 static void 288 ata_sata_phy_event(void *context, int dummy) 289 { 290 struct ata_connect_task *tp = (struct ata_connect_task *)context; 291 struct ata_channel *ch = device_get_softc(tp->dev); 292 device_t *children; 293 int nchildren, i; 294 295 get_mplock(); 296 if (tp->action == ATA_C_ATTACH) { 297 if (bootverbose) 298 device_printf(tp->dev, "CONNECTED\n"); 299 ATA_RESET(tp->dev); 300 ata_identify(tp->dev); 301 } 302 if (tp->action == ATA_C_DETACH) { 303 if (!device_get_children(tp->dev, &children, &nchildren)) { 304 for (i = 0; i < nchildren; i++) 305 if (children[i]) 306 device_delete_child(tp->dev, children[i]); 307 kfree(children, M_TEMP); 308 } 309 spin_lock_wr(&ch->state_mtx); 310 ch->state = ATA_IDLE; 311 spin_unlock_wr(&ch->state_mtx); 312 if (bootverbose) 313 device_printf(tp->dev, "DISCONNECTED\n"); 314 } 315 rel_mplock(); 316 kfree(tp, M_ATA); 317 } 318 319 static int 320 ata_sata_phy_reset(device_t dev) 321 { 322 struct ata_channel *ch = device_get_softc(dev); 323 int loop, retry; 324 325 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 326 return ata_sata_connect(ch); 327 328 for (retry = 0; retry < 10; retry++) { 329 for (loop = 0; loop < 10; loop++) { 330 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET); 331 ata_udelay(100); 332 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & 333 ATA_SC_DET_MASK) == ATA_SC_DET_RESET) 334 break; 335 } 336 ata_udelay(5000); 337 for (loop = 0; loop < 10; loop++) { 338 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE | 339 ATA_SC_IPM_DIS_PARTIAL | 340 ATA_SC_IPM_DIS_SLUMBER); 341 ata_udelay(100); 342 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0) 343 return ata_sata_connect(ch); 344 } 345 } 346 return 0; 347 } 348 349 static int 350 ata_sata_connect(struct ata_channel *ch) 351 { 352 u_int32_t status; 353 int timeout; 354 355 /* wait up to 1 second for "connect well" */ 356 for (timeout = 0; timeout < 100 ; timeout++) { 357 status = ATA_IDX_INL(ch, ATA_SSTATUS); 358 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 || 359 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2) 360 break; 361 ata_udelay(10000); 362 } 363 if (timeout >= 100) { 364 if (bootverbose) 365 device_printf(ch->dev, "SATA connect status=%08x\n", status); 366 return 0; 367 } 368 369 if (bootverbose) 370 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10); 371 372 /* clear SATA error register */ 373 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 374 375 return 1; 376 } 377 378 static void 379 ata_sata_setmode(device_t dev, int mode) 380 { 381 struct ata_device *atadev = device_get_softc(dev); 382 383 /* 384 * if we detect that the device isn't a real SATA device we limit 385 * the transfer mode to UDMA5/ATA100. 386 * this works around the problems some devices has with the 387 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133. 388 */ 389 if (atadev->param.satacapabilities != 0x0000 && 390 atadev->param.satacapabilities != 0xffff) { 391 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 392 393 /* on some drives we need to set the transfer mode */ 394 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 395 ata_limit_mode(dev, mode, ATA_UDMA6)); 396 397 /* query SATA STATUS for the speed */ 398 if (ch->r_io[ATA_SSTATUS].res && 399 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) == 400 ATA_SS_CONWELL_GEN2)) 401 atadev->mode = ATA_SA300; 402 else 403 atadev->mode = ATA_SA150; 404 } 405 else { 406 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 407 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 408 atadev->mode = mode; 409 } 410 } 411 412 static int 413 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis) 414 { 415 struct ata_device *atadev = device_get_softc(request->dev); 416 417 if (request->flags & ATA_R_ATAPI) { 418 fis[0] = 0x27; /* host to device */ 419 fis[1] = 0x80; /* command FIS (note PM goes here) */ 420 fis[2] = ATA_PACKET_CMD; 421 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) 422 fis[3] = ATA_F_DMA; 423 else { 424 fis[5] = request->transfersize; 425 fis[6] = request->transfersize >> 8; 426 } 427 fis[7] = ATA_D_LBA | atadev->unit; 428 fis[15] = ATA_A_4BIT; 429 return 20; 430 } 431 else { 432 ata_modify_if_48bit(request); 433 fis[0] = 0x27; /* host to device */ 434 fis[1] = 0x80; /* command FIS (note PM goes here) */ 435 fis[2] = request->u.ata.command; 436 fis[3] = request->u.ata.feature; 437 fis[4] = request->u.ata.lba; 438 fis[5] = request->u.ata.lba >> 8; 439 fis[6] = request->u.ata.lba >> 16; 440 fis[7] = ATA_D_LBA | atadev->unit; 441 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 442 fis[7] |= (request->u.ata.lba >> 24 & 0x0f); 443 fis[8] = request->u.ata.lba >> 24; 444 fis[9] = request->u.ata.lba >> 32; 445 fis[10] = request->u.ata.lba >> 40; 446 fis[11] = request->u.ata.feature >> 8; 447 fis[12] = request->u.ata.count; 448 fis[13] = request->u.ata.count >> 8; 449 fis[15] = ATA_A_4BIT; 450 return 20; 451 } 452 return 0; 453 } 454 455 /* 456 * AHCI v1.x compliant SATA chipset support functions 457 */ 458 int 459 ata_ahci_ident(device_t dev) 460 { 461 struct ata_pci_controller *ctlr = device_get_softc(dev); 462 static struct ata_chip_id id = {0, 0, 0, 0x00, ATA_SA300, "AHCI"}; 463 char buffer[64]; 464 465 if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0) 466 return ENXIO; 467 468 if (bootverbose) 469 ksnprintf(buffer, sizeof(buffer), "%s (ID=%08x) AHCI controller", 470 ata_pcivendor2str(dev), pci_get_devid(dev)); 471 else 472 ksnprintf(buffer, sizeof(buffer), "%s AHCI controller", 473 ata_pcivendor2str(dev)); 474 device_set_desc_copy(dev, buffer); 475 ctlr->chip = &id; 476 ctlr->chipinit = ata_ahci_chipinit; 477 return 0; 478 } 479 480 481 /* 482 * AHCI v1.x compliant SATA chipset support functions 483 */ 484 int 485 ata_ahci_chipinit(device_t dev) 486 { 487 struct ata_pci_controller *ctlr = device_get_softc(dev); 488 u_int32_t version; 489 int unit; 490 491 /* enable AHCI mode */ 492 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 493 494 /* reset AHCI controller */ 495 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR); 496 DELAY(1000000); 497 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) { 498 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 499 device_printf(dev, "AHCI controller reset failure\n"); 500 return ENXIO; 501 } 502 503 /* reenable AHCI mode */ 504 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 505 506 /* get the number of HW channels */ 507 ctlr->channels = 508 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)), 509 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 510 511 /* disable interrupt sources and clear interrupts */ 512 for (unit = 0; unit < ctlr->channels; unit++) { 513 int offset = unit << 7; 514 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0); 515 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, -1); 516 } 517 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS)); 518 519 /* enable AHCI interrupts */ 520 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 521 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE); 522 523 ctlr->reset = ata_ahci_reset; 524 ctlr->dmainit = ata_ahci_dmainit; 525 ctlr->allocate = ata_ahci_allocate; 526 ctlr->setmode = ata_sata_setmode; 527 528 /* enable PCI interrupt */ 529 pci_write_config(dev, PCIR_COMMAND, 530 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 531 532 /* announce we support the HW */ 533 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS); 534 device_printf(dev, 535 "AHCI Version %x%x.%x%x controller with %d ports detected\n", 536 (version >> 24) & 0xff, (version >> 16) & 0xff, 537 (version >> 8) & 0xff, version & 0xff, 538 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 539 return 0; 540 } 541 542 static int 543 ata_ahci_allocate(device_t dev) 544 { 545 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 546 struct ata_channel *ch = device_get_softc(dev); 547 u_int64_t work; 548 int offset = ch->unit << 7; 549 550 /* set the SATA resources */ 551 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 552 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset; 553 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 554 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset; 555 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 556 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset; 557 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 558 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset; 559 560 ch->hw.status = ata_ahci_status; 561 ch->hw.begin_transaction = ata_ahci_begin_transaction; 562 ch->hw.end_transaction = ata_ahci_end_transaction; 563 ch->hw.command = NULL; /* not used here */ 564 565 /* setup work areas */ 566 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET; 567 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff); 568 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32); 569 570 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET; 571 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff); 572 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32); 573 574 /* enable wanted port interrupts */ 575 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 576 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF | 577 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF | 578 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP | 579 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS | 580 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR)); 581 582 /* start operations on this channel */ 583 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 584 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 585 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 586 return 0; 587 } 588 589 static int 590 ata_ahci_status(device_t dev) 591 { 592 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 593 struct ata_channel *ch = device_get_softc(dev); 594 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS); 595 int offset = ch->unit << 7; 596 int tag = 0; 597 598 if (action & (1 << ch->unit)) { 599 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset); 600 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset); 601 602 /* clear interrupt(s) */ 603 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit)); 604 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus); 605 606 /* do we have any PHY events ? */ 607 /* XXX SOS check istatus phy bits */ 608 ata_sata_phy_check_events(dev); 609 610 /* do we have a potentially hanging engine to take care of? */ 611 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) { 612 613 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 614 int timeout = 0; 615 616 /* kill off all activity on this channel */ 617 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 618 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 619 620 /* XXX SOS this is not entirely wrong */ 621 do { 622 DELAY(1000); 623 if (timeout++ > 500) { 624 device_printf(dev, "stopping AHCI engine failed\n"); 625 break; 626 } 627 } while (ATA_INL(ctlr->r_res2, 628 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 629 630 /* start operations on this channel */ 631 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 632 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 633 634 return 1; 635 } 636 else 637 return (!(cstatus & (1 << tag))); 638 } 639 return 0; 640 } 641 642 /* must be called with ATA channel locked and state_mtx held */ 643 static int 644 ata_ahci_begin_transaction(struct ata_request *request) 645 { 646 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 647 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 648 struct ata_ahci_cmd_tab *ctp; 649 struct ata_ahci_cmd_list *clp; 650 int offset = ch->unit << 7; 651 int tag = 0, entries = 0; 652 int fis_size; 653 654 /* get a piece of the workspace for this request */ 655 ctp = (struct ata_ahci_cmd_tab *) 656 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag)); 657 658 /* setup the FIS for this request */ 659 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) { 660 device_printf(request->dev, "setting up SATA FIS failed\n"); 661 request->result = EIO; 662 return ATA_OP_FINISHED; 663 } 664 665 /* if request moves data setup and load SG list */ 666 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 667 if (ch->dma->load(ch->dev, request->data, request->bytecount, 668 request->flags & ATA_R_READ, 669 ctp->prd_tab, &entries)) { 670 device_printf(request->dev, "setting up DMA failed\n"); 671 request->result = EIO; 672 return ATA_OP_FINISHED; 673 } 674 } 675 676 /* setup the command list entry */ 677 clp = (struct ata_ahci_cmd_list *) 678 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 679 680 clp->prd_length = entries; 681 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) | 682 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) | 683 (fis_size / sizeof(u_int32_t)); 684 clp->bytecount = 0; 685 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET + 686 (ATA_AHCI_CT_SIZE * tag)); 687 688 /* clear eventual ACTIVE bit */ 689 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag)); 690 691 /* set command type bit */ 692 if (request->flags & ATA_R_ATAPI) 693 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 694 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) | 695 ATA_AHCI_P_CMD_ATAPI); 696 else 697 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 698 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & 699 ~ATA_AHCI_P_CMD_ATAPI); 700 701 /* issue command to controller */ 702 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag)); 703 704 if (!(request->flags & ATA_R_ATAPI)) { 705 /* device reset doesn't interrupt */ 706 if (request->u.ata.command == ATA_DEVICE_RESET) { 707 u_int32_t tf_data; 708 int timeout = 1000000; 709 710 do { 711 DELAY(10); 712 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7)); 713 } while ((tf_data & ATA_S_BUSY) && timeout--); 714 if (bootverbose) 715 device_printf(ch->dev, "device_reset timeout=%dus\n", 716 (1000000-timeout)*10); 717 request->status = tf_data; 718 if (request->status & ATA_S_ERROR) 719 request->error = tf_data >> 8; 720 return ATA_OP_FINISHED; 721 } 722 } 723 724 /* start the timeout */ 725 callout_reset(&request->callout, request->timeout * hz, 726 (timeout_t*)ata_timeout, request); 727 return ATA_OP_CONTINUES; 728 } 729 730 /* must be called with ATA channel locked and state_mtx held */ 731 static int 732 ata_ahci_end_transaction(struct ata_request *request) 733 { 734 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 735 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 736 struct ata_ahci_cmd_list *clp; 737 u_int32_t tf_data; 738 int offset = ch->unit << 7; 739 int tag = 0; 740 741 /* kill the timeout */ 742 callout_stop(&request->callout); 743 744 /* get status */ 745 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset); 746 request->status = tf_data; 747 748 /* if error status get details */ 749 if (request->status & ATA_S_ERROR) 750 request->error = tf_data >> 8; 751 752 /* record how much data we actually moved */ 753 clp = (struct ata_ahci_cmd_list *) 754 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 755 request->donecount = clp->bytecount; 756 757 /* release SG list etc */ 758 ch->dma->unload(ch->dev); 759 760 return ATA_OP_FINISHED; 761 } 762 763 static void 764 ata_ahci_reset(device_t dev) 765 { 766 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 767 struct ata_channel *ch = device_get_softc(dev); 768 u_int32_t cmd, signature; 769 int offset = ch->unit << 7; 770 int timeout; 771 772 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) { 773 device_printf(dev, "port not implemented\n"); 774 return; 775 } 776 ch->devices = 0; 777 778 /* kill off all activity on this channel */ 779 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 780 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 781 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 782 783 /* XXX SOS this is not entirely wrong */ 784 timeout = 0; 785 do { 786 DELAY(1000); 787 if (timeout++ > 500) { 788 device_printf(dev, "stopping AHCI engine failed\n"); 789 break; 790 } 791 } 792 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 793 794 /* issue Command List Override if supported */ 795 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) { 796 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 797 cmd |= ATA_AHCI_P_CMD_CLO; 798 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd); 799 timeout = 0; 800 do { 801 DELAY(1000); 802 if (timeout++ > 500) { 803 device_printf(dev, "executing CLO failed\n"); 804 break; 805 } 806 } 807 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO); 808 } 809 810 /* reset PHY and decide what is present */ 811 if (ata_sata_phy_reset(dev)) { 812 813 /* clear any interrupts pending on this channel */ 814 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, 815 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset)); 816 817 /* clear SATA error register */ 818 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 819 820 /* start operations on this channel */ 821 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 822 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 823 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 824 825 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset); 826 switch (signature) { 827 case 0x00000101: 828 ch->devices = ATA_ATA_MASTER; 829 break; 830 case 0x96690101: 831 ch->devices = ATA_PORTMULTIPLIER; 832 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 833 ch->devices = 0; 834 break; 835 case 0xeb140101: 836 ch->devices = ATA_ATAPI_MASTER; 837 break; 838 default: /* SOS XXX */ 839 if (bootverbose) 840 device_printf(ch->dev, "No signature, assuming disk device\n"); 841 ch->devices = ATA_ATA_MASTER; 842 } 843 } 844 if (bootverbose) 845 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices, 846 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 847 } 848 849 static void 850 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 851 { 852 struct ata_dmasetprd_args *args = xsc; 853 struct ata_ahci_dma_prd *prd = args->dmatab; 854 int i; 855 856 if (!(args->error = error)) { 857 for (i = 0; i < nsegs; i++) { 858 prd[i].dba = htole64(segs[i].ds_addr); 859 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK); 860 } 861 } 862 args->nsegs = nsegs; 863 } 864 865 static void 866 ata_ahci_dmainit(device_t dev) 867 { 868 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 869 struct ata_channel *ch = device_get_softc(dev); 870 871 ata_dmainit(dev); 872 if (ch->dma) { 873 /* note start and stop are not used here */ 874 ch->dma->setprd = ata_ahci_dmasetprd; 875 ch->dma->max_iosize = 8192 * DEV_BSIZE; 876 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT) 877 ch->dma->max_address = BUS_SPACE_MAXADDR; 878 } 879 } 880 881 static int 882 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request) 883 { 884 bzero(ctp->cfis, 64); 885 if (request->flags & ATA_R_ATAPI) { 886 bzero(ctp->acmd, 32); 887 bcopy(request->u.atapi.ccb, ctp->acmd, 16); 888 } 889 return ata_request2fis_h2d(request, &ctp->cfis[0]); 890 } 891 892 /* 893 * Acard chipset support functions 894 */ 895 int 896 ata_acard_ident(device_t dev) 897 { 898 struct ata_pci_controller *ctlr = device_get_softc(dev); 899 struct ata_chip_id *idx; 900 static struct ata_chip_id ids[] = 901 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" }, 902 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" }, 903 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" }, 904 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" }, 905 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" }, 906 { 0, 0, 0, 0, 0, 0}}; 907 char buffer[64]; 908 909 if (!(idx = ata_match_chip(dev, ids))) 910 return ENXIO; 911 912 ksprintf(buffer, "Acard %s %s controller", 913 idx->text, ata_mode2str(idx->max_dma)); 914 device_set_desc_copy(dev, buffer); 915 ctlr->chip = idx; 916 ctlr->chipinit = ata_acard_chipinit; 917 return 0; 918 } 919 920 static int 921 ata_acard_chipinit(device_t dev) 922 { 923 struct ata_pci_controller *ctlr = device_get_softc(dev); 924 925 if (ata_setup_interrupt(dev)) 926 return ENXIO; 927 928 ctlr->allocate = ata_acard_allocate; 929 if (ctlr->chip->cfg1 == ATPOLD) { 930 ctlr->setmode = ata_acard_850_setmode; 931 ctlr->locking = ata_serialize; 932 } 933 else 934 ctlr->setmode = ata_acard_86X_setmode; 935 return 0; 936 } 937 938 static int 939 ata_acard_allocate(device_t dev) 940 { 941 struct ata_channel *ch = device_get_softc(dev); 942 943 /* setup the usual register normal pci style */ 944 if (ata_pci_allocate(dev)) 945 return ENXIO; 946 947 ch->hw.status = ata_acard_status; 948 return 0; 949 } 950 951 static int 952 ata_acard_status(device_t dev) 953 { 954 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 955 struct ata_channel *ch = device_get_softc(dev); 956 957 if (ctlr->chip->cfg1 == ATPOLD && 958 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit) 959 return 0; 960 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) { 961 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 962 963 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != 964 ATA_BMSTAT_INTERRUPT) 965 return 0; 966 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR); 967 DELAY(1); 968 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 969 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 970 DELAY(1); 971 } 972 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 973 DELAY(100); 974 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 975 return 0; 976 } 977 return 1; 978 } 979 980 static void 981 ata_acard_850_setmode(device_t dev, int mode) 982 { 983 device_t gparent = GRANDPARENT(dev); 984 struct ata_pci_controller *ctlr = device_get_softc(gparent); 985 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 986 struct ata_device *atadev = device_get_softc(dev); 987 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 988 int error; 989 990 mode = ata_limit_mode(dev, mode, 991 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 992 993 /* XXX SOS missing WDMA0+1 + PIO modes */ 994 if (mode >= ATA_WDMA2) { 995 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 996 if (bootverbose) 997 device_printf(dev, "%ssetting %s on %s chip\n", 998 (error) ? "FAILURE " : "", 999 ata_mode2str(mode), ctlr->chip->text); 1000 if (!error) { 1001 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1); 1002 1003 reg54 &= ~(0x03 << (devno << 1)); 1004 if (mode >= ATA_UDMA0) 1005 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1)); 1006 pci_write_config(gparent, 0x54, reg54, 1); 1007 pci_write_config(gparent, 0x4a, 0xa6, 1); 1008 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2); 1009 atadev->mode = mode; 1010 return; 1011 } 1012 } 1013 /* we could set PIO mode timings, but we assume the BIOS did that */ 1014 } 1015 1016 static void 1017 ata_acard_86X_setmode(device_t dev, int mode) 1018 { 1019 device_t gparent = GRANDPARENT(dev); 1020 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1021 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1022 struct ata_device *atadev = device_get_softc(dev); 1023 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1024 int error; 1025 1026 1027 mode = ata_limit_mode(dev, mode, 1028 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 1029 1030 mode = ata_check_80pin(dev, mode); 1031 1032 /* XXX SOS missing WDMA0+1 + PIO modes */ 1033 if (mode >= ATA_WDMA2) { 1034 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1035 if (bootverbose) 1036 device_printf(dev, "%ssetting %s on %s chip\n", 1037 (error) ? "FAILURE " : "", 1038 ata_mode2str(mode), ctlr->chip->text); 1039 if (!error) { 1040 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2); 1041 1042 reg44 &= ~(0x000f << (devno << 2)); 1043 if (mode >= ATA_UDMA0) 1044 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2)); 1045 pci_write_config(gparent, 0x44, reg44, 2); 1046 pci_write_config(gparent, 0x4a, 0xa6, 1); 1047 pci_write_config(gparent, 0x40 + devno, 0x31, 1); 1048 atadev->mode = mode; 1049 return; 1050 } 1051 } 1052 /* we could set PIO mode timings, but we assume the BIOS did that */ 1053 } 1054 1055 1056 /* 1057 * Acer Labs Inc (ALI) chipset support functions 1058 */ 1059 int 1060 ata_ali_ident(device_t dev) 1061 { 1062 struct ata_pci_controller *ctlr = device_get_softc(dev); 1063 struct ata_chip_id *idx; 1064 static struct ata_chip_id ids[] = 1065 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" }, 1066 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" }, 1067 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" }, 1068 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" }, 1069 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" }, 1070 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" }, 1071 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" }, 1072 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" }, 1073 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" }, 1074 { 0, 0, 0, 0, 0, 0}}; 1075 char buffer[64]; 1076 1077 if (!(idx = ata_match_chip(dev, ids))) 1078 return ENXIO; 1079 1080 ksprintf(buffer, "AcerLabs %s %s controller", 1081 idx->text, ata_mode2str(idx->max_dma)); 1082 device_set_desc_copy(dev, buffer); 1083 ctlr->chip = idx; 1084 ctlr->chipinit = ata_ali_chipinit; 1085 return 0; 1086 } 1087 1088 static int 1089 ata_ali_chipinit(device_t dev) 1090 { 1091 struct ata_pci_controller *ctlr = device_get_softc(dev); 1092 1093 if (ata_setup_interrupt(dev)) 1094 return ENXIO; 1095 1096 switch (ctlr->chip->cfg2) { 1097 case ALISATA: 1098 ctlr->channels = ctlr->chip->cfg1; 1099 ctlr->allocate = ata_ali_sata_allocate; 1100 ctlr->setmode = ata_sata_setmode; 1101 1102 /* if we have a memory resource we can likely do AHCI */ 1103 ctlr->r_type2 = SYS_RES_MEMORY; 1104 ctlr->r_rid2 = PCIR_BAR(5); 1105 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1106 &ctlr->r_rid2, RF_ACTIVE))) 1107 return ata_ahci_chipinit(dev); 1108 1109 /* enable PCI interrupt */ 1110 pci_write_config(dev, PCIR_COMMAND, 1111 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1112 break; 1113 1114 case ALINEW: 1115 /* use device interrupt as byte count end */ 1116 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1); 1117 1118 /* enable cable detection and UDMA support on newer chips */ 1119 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1); 1120 1121 /* enable ATAPI UDMA mode */ 1122 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1); 1123 1124 /* only chips with revision > 0xc4 can do 48bit DMA */ 1125 if (ctlr->chip->chiprev <= 0xc4) 1126 device_printf(dev, 1127 "using PIO transfers above 137GB as workaround for " 1128 "48bit DMA access bug, expect reduced performance\n"); 1129 ctlr->allocate = ata_ali_allocate; 1130 ctlr->reset = ata_ali_reset; 1131 ctlr->setmode = ata_ali_setmode; 1132 break; 1133 1134 case ALIOLD: 1135 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */ 1136 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1); 1137 ctlr->setmode = ata_ali_setmode; 1138 break; 1139 } 1140 return 0; 1141 } 1142 1143 static int 1144 ata_ali_allocate(device_t dev) 1145 { 1146 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1147 struct ata_channel *ch = device_get_softc(dev); 1148 1149 /* setup the usual register normal pci style */ 1150 if (ata_pci_allocate(dev)) 1151 return ENXIO; 1152 1153 /* older chips can't do 48bit DMA transfers */ 1154 if (ctlr->chip->chiprev <= 0xc4) 1155 ch->flags |= ATA_NO_48BIT_DMA; 1156 1157 return 0; 1158 } 1159 1160 static int 1161 ata_ali_sata_allocate(device_t dev) 1162 { 1163 device_t parent = device_get_parent(dev); 1164 struct ata_pci_controller *ctlr = device_get_softc(parent); 1165 struct ata_channel *ch = device_get_softc(dev); 1166 struct resource *io = NULL, *ctlio = NULL; 1167 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 1168 int i, rid; 1169 1170 rid = PCIR_BAR(0) + (unit01 ? 8 : 0); 1171 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1172 if (!io) 1173 return ENXIO; 1174 1175 rid = PCIR_BAR(1) + (unit01 ? 8 : 0); 1176 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1177 if (!ctlio) { 1178 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io); 1179 return ENXIO; 1180 } 1181 1182 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 1183 ch->r_io[i].res = io; 1184 ch->r_io[i].offset = i + (unit10 ? 8 : 0); 1185 } 1186 ch->r_io[ATA_CONTROL].res = ctlio; 1187 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0); 1188 ch->r_io[ATA_IDX_ADDR].res = io; 1189 ata_default_registers(dev); 1190 if (ctlr->r_res1) { 1191 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 1192 ch->r_io[i].res = ctlr->r_res1; 1193 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 1194 } 1195 } 1196 ch->flags |= ATA_NO_SLAVE; 1197 1198 /* XXX SOS PHY handling awkward in ALI chip not supported yet */ 1199 ata_pci_hw(dev); 1200 return 0; 1201 } 1202 1203 static void 1204 ata_ali_reset(device_t dev) 1205 { 1206 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1207 struct ata_channel *ch = device_get_softc(dev); 1208 device_t *children; 1209 int nchildren, i; 1210 1211 ata_generic_reset(dev); 1212 1213 /* 1214 * workaround for datacorruption bug found on at least SUN Blade-100 1215 * find the ISA function on the southbridge and disable then enable 1216 * the ATA channel tristate buffer 1217 */ 1218 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) { 1219 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) { 1220 for (i = 0; i < nchildren; i++) { 1221 if (pci_get_devid(children[i]) == ATA_ALI_1533) { 1222 pci_write_config(children[i], 0x58, 1223 pci_read_config(children[i], 0x58, 1) & 1224 ~(0x04 << ch->unit), 1); 1225 pci_write_config(children[i], 0x58, 1226 pci_read_config(children[i], 0x58, 1) | 1227 (0x04 << ch->unit), 1); 1228 break; 1229 } 1230 } 1231 kfree(children, M_TEMP); 1232 } 1233 } 1234 } 1235 1236 static void 1237 ata_ali_setmode(device_t dev, int mode) 1238 { 1239 device_t gparent = GRANDPARENT(dev); 1240 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1241 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1242 struct ata_device *atadev = device_get_softc(dev); 1243 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1244 int error; 1245 1246 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1247 1248 if (ctlr->chip->cfg2 & ALINEW) { 1249 if (mode > ATA_UDMA2 && 1250 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) { 1251 ata_print_cable(dev, "controller"); 1252 mode = ATA_UDMA2; 1253 } 1254 } 1255 else 1256 mode = ata_check_80pin(dev, mode); 1257 1258 if (ctlr->chip->cfg2 & ALIOLD) { 1259 /* doesn't support ATAPI DMA on write */ 1260 ch->flags |= ATA_ATAPI_DMA_RO; 1261 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) { 1262 /* doesn't support ATAPI DMA on two ATAPI devices */ 1263 device_printf(dev, "two atapi devices on this channel, no DMA\n"); 1264 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1265 } 1266 } 1267 1268 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1269 1270 if (bootverbose) 1271 device_printf(dev, "%ssetting %s on %s chip\n", 1272 (error) ? "FAILURE " : "", 1273 ata_mode2str(mode), ctlr->chip->text); 1274 if (!error) { 1275 if (mode >= ATA_UDMA0) { 1276 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d}; 1277 u_int32_t word54 = pci_read_config(gparent, 0x54, 4); 1278 1279 word54 &= ~(0x000f000f << (devno << 2)); 1280 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2)); 1281 pci_write_config(gparent, 0x54, word54, 4); 1282 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1283 0x00310001, 4); 1284 } 1285 else { 1286 u_int32_t piotimings[] = 1287 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001, 1288 0x00310001, 0x00440001, 0x00330001, 0x00310001}; 1289 1290 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) & 1291 ~(0x0008000f << (devno << 2)), 4); 1292 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1293 piotimings[ata_mode2idx(mode)], 4); 1294 } 1295 atadev->mode = mode; 1296 } 1297 } 1298 1299 1300 /* 1301 * American Micro Devices (AMD) chipset support functions 1302 */ 1303 int 1304 ata_amd_ident(device_t dev) 1305 { 1306 struct ata_pci_controller *ctlr = device_get_softc(dev); 1307 struct ata_chip_id *idx; 1308 static struct ata_chip_id ids[] = 1309 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" }, 1310 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" }, 1311 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" }, 1312 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" }, 1313 { 0, 0, 0, 0, 0, 0}}; 1314 char buffer[64]; 1315 1316 if (!(idx = ata_match_chip(dev, ids))) 1317 return ENXIO; 1318 1319 ksprintf(buffer, "AMD %s %s controller", 1320 idx->text, ata_mode2str(idx->max_dma)); 1321 device_set_desc_copy(dev, buffer); 1322 ctlr->chip = idx; 1323 ctlr->chipinit = ata_amd_chipinit; 1324 return 0; 1325 } 1326 1327 static int 1328 ata_amd_chipinit(device_t dev) 1329 { 1330 struct ata_pci_controller *ctlr = device_get_softc(dev); 1331 1332 if (ata_setup_interrupt(dev)) 1333 return ENXIO; 1334 1335 /* disable/set prefetch, postwrite */ 1336 if (ctlr->chip->cfg2 & AMDBUG) 1337 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1); 1338 else 1339 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); 1340 1341 ctlr->setmode = ata_via_family_setmode; 1342 return 0; 1343 } 1344 1345 1346 /* 1347 * ATI chipset support functions 1348 */ 1349 int 1350 ata_ati_ident(device_t dev) 1351 { 1352 struct ata_pci_controller *ctlr = device_get_softc(dev); 1353 struct ata_chip_id *idx; 1354 static struct ata_chip_id ids[] = 1355 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" }, 1356 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" }, 1357 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" }, 1358 { ATA_ATI_SB600, 0x00, 0, 0, ATA_UDMA6, "SB600" }, 1359 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" }, 1360 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1361 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1362 { ATA_ATI_SB600_S1, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1363 { ATA_ATI_SB600_S2, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1364 { 0, 0, 0, 0, 0, 0}}; 1365 char buffer[64]; 1366 1367 if (!(idx = ata_match_chip(dev, ids))) 1368 return ENXIO; 1369 1370 ksprintf(buffer, "ATI %s %s controller", 1371 idx->text, ata_mode2str(idx->max_dma)); 1372 device_set_desc_copy(dev, buffer); 1373 ctlr->chip = idx; 1374 1375 /* 1376 * The ATI SATA controllers are actually a SiI 3112 controller, except 1377 * for the SB600. 1378 */ 1379 if (ctlr->chip->cfg1 & SIIMEMIO) 1380 ctlr->chipinit = ata_sii_chipinit; 1381 else 1382 ctlr->chipinit = ata_ati_chipinit; 1383 return 0; 1384 } 1385 1386 static int 1387 ata_ati_chipinit(device_t dev) 1388 { 1389 struct ata_pci_controller *ctlr = device_get_softc(dev); 1390 1391 if (ata_setup_interrupt(dev)) 1392 return ENXIO; 1393 1394 /* The SB600 needs special treatment. */ 1395 if (ctlr->chip->cfg1 & ATIAHCI) { 1396 /* Check if the chip is configured as an AHCI part. */ 1397 if ((pci_get_subclass(dev) == PCIS_STORAGE_SATA) && 1398 (pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI_1_0)) { 1399 /* Check if the chip has PCI BAR 5 as memory resource. */ 1400 ctlr->r_type2 = SYS_RES_MEMORY; 1401 ctlr->r_rid2 = PCIR_BAR(5); /* 0x24 */ 1402 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1403 &ctlr->r_rid2, 1404 RF_ACTIVE))) { 1405 return ata_ahci_chipinit(dev); 1406 } 1407 } 1408 } 1409 1410 ctlr->setmode = ata_ati_setmode; 1411 return 0; 1412 } 1413 1414 static void 1415 ata_ati_setmode(device_t dev, int mode) 1416 { 1417 device_t gparent = GRANDPARENT(dev); 1418 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1419 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1420 struct ata_device *atadev = device_get_softc(dev); 1421 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1422 int offset = (devno ^ 0x01) << 3; 1423 int error; 1424 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 1425 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 1426 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 1427 1428 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1429 1430 mode = ata_check_80pin(dev, mode); 1431 1432 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1433 1434 if (bootverbose) 1435 device_printf(dev, "%ssetting %s on %s chip\n", 1436 (error) ? "FAILURE " : "", 1437 ata_mode2str(mode), ctlr->chip->text); 1438 if (!error) { 1439 if (mode >= ATA_UDMA0) { 1440 pci_write_config(gparent, 0x56, 1441 (pci_read_config(gparent, 0x56, 2) & 1442 ~(0xf << (devno << 2))) | 1443 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 1444 pci_write_config(gparent, 0x54, 1445 pci_read_config(gparent, 0x54, 1) | 1446 (0x01 << devno), 1); 1447 pci_write_config(gparent, 0x44, 1448 (pci_read_config(gparent, 0x44, 4) & 1449 ~(0xff << offset)) | 1450 (dmatimings[2] << offset), 4); 1451 } 1452 else if (mode >= ATA_WDMA0) { 1453 pci_write_config(gparent, 0x54, 1454 pci_read_config(gparent, 0x54, 1) & 1455 ~(0x01 << devno), 1); 1456 pci_write_config(gparent, 0x44, 1457 (pci_read_config(gparent, 0x44, 4) & 1458 ~(0xff << offset)) | 1459 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 1460 } 1461 else 1462 pci_write_config(gparent, 0x54, 1463 pci_read_config(gparent, 0x54, 1) & 1464 ~(0x01 << devno), 1); 1465 1466 pci_write_config(gparent, 0x4a, 1467 (pci_read_config(gparent, 0x4a, 2) & 1468 ~(0xf << (devno << 2))) | 1469 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2); 1470 pci_write_config(gparent, 0x40, 1471 (pci_read_config(gparent, 0x40, 4) & 1472 ~(0xff << offset)) | 1473 (piotimings[ata_mode2idx(mode)] << offset), 4); 1474 atadev->mode = mode; 1475 } 1476 } 1477 1478 /* 1479 * Cyrix chipset support functions 1480 */ 1481 int 1482 ata_cyrix_ident(device_t dev) 1483 { 1484 struct ata_pci_controller *ctlr = device_get_softc(dev); 1485 1486 if (pci_get_devid(dev) == ATA_CYRIX_5530) { 1487 device_set_desc(dev, "Cyrix 5530 ATA33 controller"); 1488 ctlr->chipinit = ata_cyrix_chipinit; 1489 return 0; 1490 } 1491 return ENXIO; 1492 } 1493 1494 static int 1495 ata_cyrix_chipinit(device_t dev) 1496 { 1497 struct ata_pci_controller *ctlr = device_get_softc(dev); 1498 1499 if (ata_setup_interrupt(dev)) 1500 return ENXIO; 1501 1502 if (ctlr->r_res1) 1503 ctlr->setmode = ata_cyrix_setmode; 1504 else 1505 ctlr->setmode = ata_generic_setmode; 1506 return 0; 1507 } 1508 1509 static void 1510 ata_cyrix_setmode(device_t dev, int mode) 1511 { 1512 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1513 struct ata_device *atadev = device_get_softc(dev); 1514 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1515 u_int32_t piotiming[] = 1516 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 }; 1517 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 }; 1518 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 }; 1519 int error; 1520 1521 ch->dma->alignment = 16; 1522 ch->dma->max_iosize = 126 * DEV_BSIZE; 1523 1524 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 1525 1526 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1527 1528 if (bootverbose) 1529 device_printf(dev, "%ssetting %s on Cyrix chip\n", 1530 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1531 if (!error) { 1532 if (mode >= ATA_UDMA0) { 1533 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1534 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]); 1535 } 1536 else if (mode >= ATA_WDMA0) { 1537 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1538 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]); 1539 } 1540 else { 1541 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1542 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]); 1543 } 1544 atadev->mode = mode; 1545 } 1546 } 1547 1548 1549 /* 1550 * Cypress chipset support functions 1551 */ 1552 int 1553 ata_cypress_ident(device_t dev) 1554 { 1555 struct ata_pci_controller *ctlr = device_get_softc(dev); 1556 1557 /* 1558 * the Cypress chip is a mess, it contains two ATA functions, but 1559 * both channels are visible on the first one. 1560 * simply ignore the second function for now, as the right 1561 * solution (ignoring the second channel on the first function) 1562 * doesn't work with the crappy ATA interrupt setup on the alpha. 1563 */ 1564 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 && 1565 pci_get_function(dev) == 1 && 1566 pci_get_subclass(dev) == PCIS_STORAGE_IDE) { 1567 device_set_desc(dev, "Cypress 82C693 ATA controller"); 1568 ctlr->chipinit = ata_cypress_chipinit; 1569 return 0; 1570 } 1571 return ENXIO; 1572 } 1573 1574 static int 1575 ata_cypress_chipinit(device_t dev) 1576 { 1577 struct ata_pci_controller *ctlr = device_get_softc(dev); 1578 1579 if (ata_setup_interrupt(dev)) 1580 return ENXIO; 1581 1582 ctlr->setmode = ata_cypress_setmode; 1583 return 0; 1584 } 1585 1586 static void 1587 ata_cypress_setmode(device_t dev, int mode) 1588 { 1589 device_t gparent = GRANDPARENT(dev); 1590 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1591 struct ata_device *atadev = device_get_softc(dev); 1592 int error; 1593 1594 mode = ata_limit_mode(dev, mode, ATA_WDMA2); 1595 1596 /* XXX SOS missing WDMA0+1 + PIO modes */ 1597 if (mode == ATA_WDMA2) { 1598 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1599 if (bootverbose) 1600 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n", 1601 error ? "FAILURE " : ""); 1602 if (!error) { 1603 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2); 1604 atadev->mode = mode; 1605 return; 1606 } 1607 } 1608 /* we could set PIO mode timings, but we assume the BIOS did that */ 1609 } 1610 1611 1612 /* 1613 * HighPoint chipset support functions 1614 */ 1615 int 1616 ata_highpoint_ident(device_t dev) 1617 { 1618 struct ata_pci_controller *ctlr = device_get_softc(dev); 1619 struct ata_chip_id *idx; 1620 static struct ata_chip_id ids[] = 1621 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" }, 1622 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" }, 1623 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1624 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" }, 1625 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1626 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" }, 1627 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" }, 1628 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" }, 1629 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" }, 1630 { 0, 0, 0, 0, 0, 0}}; 1631 char buffer[64]; 1632 1633 if (!(idx = ata_match_chip(dev, ids))) 1634 return ENXIO; 1635 1636 strcpy(buffer, "HighPoint "); 1637 strcat(buffer, idx->text); 1638 if (idx->cfg1 == HPT374) { 1639 if (pci_get_function(dev) == 0) 1640 strcat(buffer, " (channel 0+1)"); 1641 if (pci_get_function(dev) == 1) 1642 strcat(buffer, " (channel 2+3)"); 1643 } 1644 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 1645 device_set_desc_copy(dev, buffer); 1646 ctlr->chip = idx; 1647 ctlr->chipinit = ata_highpoint_chipinit; 1648 return 0; 1649 } 1650 1651 static int 1652 ata_highpoint_chipinit(device_t dev) 1653 { 1654 struct ata_pci_controller *ctlr = device_get_softc(dev); 1655 1656 if (ata_setup_interrupt(dev)) 1657 return ENXIO; 1658 1659 if (ctlr->chip->cfg2 == HPTOLD) { 1660 /* disable interrupt prediction */ 1661 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 1662 } 1663 else { 1664 /* disable interrupt prediction */ 1665 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 1666 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 1667 1668 /* enable interrupts */ 1669 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 1670 1671 /* set clocks etc */ 1672 if (ctlr->chip->cfg1 < HPT372) 1673 pci_write_config(dev, 0x5b, 0x22, 1); 1674 else 1675 pci_write_config(dev, 0x5b, 1676 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 1677 } 1678 ctlr->allocate = ata_highpoint_allocate; 1679 ctlr->setmode = ata_highpoint_setmode; 1680 return 0; 1681 } 1682 1683 static int 1684 ata_highpoint_allocate(device_t dev) 1685 { 1686 struct ata_channel *ch = device_get_softc(dev); 1687 1688 /* setup the usual register normal pci style */ 1689 if (ata_pci_allocate(dev)) 1690 return ENXIO; 1691 1692 ch->flags |= ATA_ALWAYS_DMASTAT; 1693 return 0; 1694 } 1695 1696 static void 1697 ata_highpoint_setmode(device_t dev, int mode) 1698 { 1699 device_t gparent = GRANDPARENT(dev); 1700 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1701 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1702 struct ata_device *atadev = device_get_softc(dev); 1703 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1704 int error; 1705 u_int32_t timings33[][4] = { 1706 /* HPT366 HPT370 HPT372 HPT374 mode */ 1707 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */ 1708 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */ 1709 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */ 1710 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */ 1711 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */ 1712 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */ 1713 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */ 1714 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */ 1715 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */ 1716 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */ 1717 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */ 1718 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */ 1719 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */ 1720 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */ 1721 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */ 1722 }; 1723 1724 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1725 1726 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev)) 1727 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1728 1729 mode = ata_highpoint_check_80pin(dev, mode); 1730 1731 /* 1732 * most if not all HPT chips cant really handle that the device is 1733 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to 1734 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance 1735 */ 1736 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 1737 ata_limit_mode(dev, mode, ATA_UDMA5)); 1738 if (bootverbose) 1739 device_printf(dev, "%ssetting %s on HighPoint chip\n", 1740 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1741 if (!error) 1742 pci_write_config(gparent, 0x40 + (devno << 2), 1743 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 1744 atadev->mode = mode; 1745 } 1746 1747 static int 1748 ata_highpoint_check_80pin(device_t dev, int mode) 1749 { 1750 device_t gparent = GRANDPARENT(dev); 1751 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1752 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1753 u_int8_t reg, val, res; 1754 1755 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) { 1756 reg = ch->unit ? 0x57 : 0x53; 1757 val = pci_read_config(gparent, reg, 1); 1758 pci_write_config(gparent, reg, val | 0x80, 1); 1759 } 1760 else { 1761 reg = 0x5b; 1762 val = pci_read_config(gparent, reg, 1); 1763 pci_write_config(gparent, reg, val & 0xfe, 1); 1764 } 1765 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2); 1766 pci_write_config(gparent, reg, val, 1); 1767 1768 if (mode > ATA_UDMA2 && res) { 1769 ata_print_cable(dev, "controller"); 1770 mode = ATA_UDMA2; 1771 } 1772 return mode; 1773 } 1774 1775 1776 /* 1777 * Intel chipset support functions 1778 */ 1779 int 1780 ata_intel_ident(device_t dev) 1781 { 1782 struct ata_pci_controller *ctlr = device_get_softc(dev); 1783 struct ata_chip_id *idx; 1784 static struct ata_chip_id ids[] = 1785 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" }, 1786 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" }, 1787 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1788 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1789 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1790 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" }, 1791 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1792 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1793 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1794 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1795 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1796 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1797 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1798 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1799 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" }, 1800 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1801 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1802 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" }, 1803 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1804 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1805 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" }, 1806 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1807 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1808 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" }, 1809 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" }, 1810 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1811 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1812 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1813 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1814 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1815 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1816 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" }, 1817 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1818 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1819 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1820 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1821 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1822 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1823 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1824 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1825 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1826 { ATA_I82801HBM_S1, 0, 0, 0x00, ATA_SA300, "ICH8M" }, 1827 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1828 { ATA_I82801HBM_S3, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1829 { ATA_I82801IB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1830 { ATA_I82801IB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1831 { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1832 { ATA_I82801IB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1833 { ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1834 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" }, 1835 { 0, 0, 0, 0, 0, 0}}; 1836 char buffer[64]; 1837 1838 if (!(idx = ata_match_chip(dev, ids))) 1839 return ENXIO; 1840 1841 ksprintf(buffer, "Intel %s %s controller", 1842 idx->text, ata_mode2str(idx->max_dma)); 1843 device_set_desc_copy(dev, buffer); 1844 ctlr->chip = idx; 1845 ctlr->chipinit = ata_intel_chipinit; 1846 return 0; 1847 } 1848 1849 static int 1850 ata_intel_chipinit(device_t dev) 1851 { 1852 struct ata_pci_controller *ctlr = device_get_softc(dev); 1853 1854 if (ata_setup_interrupt(dev)) 1855 return ENXIO; 1856 1857 /* good old PIIX needs special treatment (not implemented) */ 1858 if (ctlr->chip->chipid == ATA_I82371FB) { 1859 ctlr->setmode = ata_intel_old_setmode; 1860 } 1861 1862 /* the intel 31244 needs special care if in DPA mode */ 1863 else if (ctlr->chip->chipid == ATA_I31244) { 1864 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 1865 ctlr->r_type2 = SYS_RES_MEMORY; 1866 ctlr->r_rid2 = PCIR_BAR(0); 1867 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1868 &ctlr->r_rid2, 1869 RF_ACTIVE))) 1870 return ENXIO; 1871 ctlr->channels = 4; 1872 ctlr->allocate = ata_intel_31244_allocate; 1873 ctlr->reset = ata_intel_31244_reset; 1874 } 1875 ctlr->setmode = ata_sata_setmode; 1876 } 1877 1878 /* non SATA intel chips goes here */ 1879 else if (ctlr->chip->max_dma < ATA_SA150) { 1880 ctlr->allocate = ata_intel_allocate; 1881 ctlr->setmode = ata_intel_new_setmode; 1882 } 1883 1884 /* SATA parts can be either compat or AHCI */ 1885 else { 1886 /* force all ports active "the legacy way" */ 1887 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2); 1888 1889 ctlr->allocate = ata_intel_allocate; 1890 ctlr->reset = ata_intel_reset; 1891 1892 /* 1893 * if we have AHCI capability and BAR(5) as a memory resource 1894 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode 1895 */ 1896 if ((ctlr->chip->cfg1 == AHCI) && 1897 (pci_read_config(dev, 0x90, 1) & 0xc0)) { 1898 ctlr->r_type2 = SYS_RES_MEMORY; 1899 ctlr->r_rid2 = PCIR_BAR(5); 1900 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1901 &ctlr->r_rid2, 1902 RF_ACTIVE))) 1903 return ata_ahci_chipinit(dev); 1904 } 1905 ctlr->setmode = ata_sata_setmode; 1906 1907 /* enable PCI interrupt */ 1908 pci_write_config(dev, PCIR_COMMAND, 1909 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1910 } 1911 return 0; 1912 } 1913 1914 static int 1915 ata_intel_allocate(device_t dev) 1916 { 1917 struct ata_channel *ch = device_get_softc(dev); 1918 1919 /* setup the usual register normal pci style */ 1920 if (ata_pci_allocate(dev)) 1921 return ENXIO; 1922 1923 ch->flags |= ATA_ALWAYS_DMASTAT; 1924 return 0; 1925 } 1926 1927 static void 1928 ata_intel_reset(device_t dev) 1929 { 1930 device_t parent = device_get_parent(dev); 1931 struct ata_pci_controller *ctlr = device_get_softc(parent); 1932 struct ata_channel *ch = device_get_softc(dev); 1933 int mask, timeout; 1934 1935 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */ 1936 if (ctlr->chip->cfg1) { 1937 mask = (0x0005 << ch->unit); 1938 } 1939 else { 1940 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */ 1941 if (pci_read_config(parent, 0x90, 1) & 0x04) 1942 mask = 0x0003; 1943 else { 1944 mask = (0x0001 << ch->unit); 1945 /* XXX SOS should be in intel_allocate if we grow it */ 1946 ch->flags |= ATA_NO_SLAVE; 1947 } 1948 } 1949 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2); 1950 DELAY(10); 1951 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2); 1952 1953 /* wait up to 1 sec for "connect well" */ 1954 for (timeout = 0; timeout < 100 ; timeout++) { 1955 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) && 1956 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 1957 break; 1958 ata_udelay(10000); 1959 } 1960 ata_generic_reset(dev); 1961 } 1962 1963 static void 1964 ata_intel_old_setmode(device_t dev, int mode) 1965 { 1966 /* NOT YET */ 1967 } 1968 1969 static void 1970 ata_intel_new_setmode(device_t dev, int mode) 1971 { 1972 device_t gparent = GRANDPARENT(dev); 1973 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1974 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1975 struct ata_device *atadev = device_get_softc(dev); 1976 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1977 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4); 1978 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1); 1979 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1); 1980 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2); 1981 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2); 1982 u_int32_t mask40 = 0, new40 = 0; 1983 u_int8_t mask44 = 0, new44 = 0; 1984 int error; 1985 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, 1986 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 }; 1987 /* PIO0 PIO1 PIO2 PIO3 PIO4 WDMA0 WDMA1 WDMA2 */ 1988 /* UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 UDMA5 UDMA6 */ 1989 1990 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1991 1992 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { 1993 ata_print_cable(dev, "controller"); 1994 mode = ATA_UDMA2; 1995 } 1996 1997 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1998 1999 if (bootverbose) 2000 device_printf(dev, "%ssetting %s on %s chip\n", 2001 (error) ? "FAILURE " : "", 2002 ata_mode2str(mode), ctlr->chip->text); 2003 if (error) 2004 return; 2005 2006 /* 2007 * reg48: 1 bit per (primary drive 0, primary drive 1, secondary 2008 * drive 0, secondary drive 1) 2009 * 2010 * 0 Disable Ultra DMA mode 2011 * 1 Enable Ultra DMA mode 2012 * 2013 * reg4a: 4 bits per (primary drive 0, primary drive 1, secondary 2014 * drive 0, secondary drive 1). 2015 * 0000 UDMA mode 0 2016 * 0001 UDMA mode 1, 3, 5 2017 * 0010 UDMA mode 2, 4, reserved 2018 * 0011 reserved 2019 * (top two bits for each drive reserved) 2020 */ 2021 #if 0 2022 device_printf(dev, 2023 "regs before 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 2024 reg40, reg44, reg48 ,reg4a, reg54); 2025 #endif 2026 reg48 &= ~(0x0001 << devno); 2027 reg4a &= ~(0x3 << (devno << 2)); 2028 if (mode >= ATA_UDMA0) { 2029 reg48 |= 0x0001 << devno; 2030 if (mode > ATA_UDMA0) 2031 reg4a |= (1 + !(mode & 0x01)) << (devno << 2); 2032 } 2033 pci_write_config(gparent, 0x48, reg48, 2); 2034 pci_write_config(gparent, 0x4a, reg4a, 2); 2035 2036 /* 2037 * reg54: 2038 * 2039 * 32:20 reserved 2040 * 19:18 Secondary ATA signal mode 2041 * 17:16 Primary ATA signal mode 2042 * 00 = Normal (enabled) 2043 * 01 = Tri-state (disabled) 2044 * 10 = Drive Low (disabled) 2045 * 11 = Reserved 2046 * 2047 * 15 Secondary drive 1 - Base Clock 2048 * 14 Secondary drive 0 - Base Clock 2049 * 13 Primary drive 1 - Base Clock 2050 * 12 Primary drive 0 - Base Clock 2051 * 0 = Select 33 MHz clock 2052 * 1 = Select 100 Mhz clock 2053 * 2054 * 11 Reserved 2055 * 10 Vendor specific (set by BIOS?) 2056 * 09:08 Reserved 2057 * 2058 * 07 Secondary drive 1 - Cable Type 2059 * 06 Secondary drive 0 - Cable Type 2060 * 05 Primary drive 1 - Cable Type 2061 * 04 Primary drive 0 - Cable Type 2062 * 0 = 40 Conductor 2063 * 1 = 80 Conductor (or high speed cable) 2064 * 2065 * 03 Secondary drive 1 - Select 33/66 clock 2066 * 02 Secondary drive 0 - Select 33/66 clock 2067 * 01 Primary drive 1 - Select 33/66 clock 2068 * 00 Primary drive 0 - Select 33/66 clock 2069 * 0 = Select 33 MHz 2070 * 1 = Select 66 MHz 2071 * 2072 * It is unclear what this should be set to when operating 2073 * in 100MHz mode. 2074 * 2075 * NOTE: UDMA2 = 33 MHz 2076 * UDMA3 = 40 MHz (?) - unsupported 2077 * UDMA4 = 66 MHz 2078 * UDMA5 = 100 MHz 2079 * UDMA6 = 133 Mhz 2080 */ 2081 reg54 |= 0x0400; /* set vendor specific bit */ 2082 reg54 &= ~((0x1 << devno) | (0x1000 << devno)); 2083 2084 if (mode >= ATA_UDMA5) 2085 reg54 |= (0x1000 << devno); 2086 else if (mode >= ATA_UDMA3) /* XXX should this be ATA_UDMA3 or 4? */ 2087 reg54 |= (0x1 << devno); 2088 2089 pci_write_config(gparent, 0x54, reg54, 2); 2090 2091 /* 2092 * Reg40 (32 bits... well, actually two 16 bit registers) 2093 * 2094 * Primary channel bits 15:00, Secondary channel bits 31:00. Note 2095 * that slave timings are handled in register 44. 2096 * 2097 * 15 ATA Decode Enable (R/W) 1 = enable decoding of I/O ranges 2098 * 2099 * 14 Slave ATA Timing Register Enable (R/W) 2100 * 2101 * 13:12 IORDY Sample Mode 2102 * 00 PIO-0 2103 * 01 PIO-2, SW-2 2104 * 10 PIO-3, PIO-4, MW-1, MW-2 2105 * 11 Reserved 2106 * 2107 * 11:10 Reserved 2108 * 2109 * 09:08 Recovery Mode 2110 * 00 PIO-0, PIO-2, SW-2 2111 * 01 PIO-3, MW-1 2112 * 10 Reserved 2113 * 11 PIO-4, MW-2 2114 * 2115 * 07:04 Secondary Device Control Bits 2116 * 03:00 Primary Device Control Bits 2117 * 2118 * bit 3 DMA Timing Enable 2119 * 2120 * bit 2 Indicate Presence of ATA(1) or ATAPI(0) device 2121 * 2122 * bit 1 Enable IORDY sample point capability for PIO 2123 * xfers. Always enabled for PIO4 and PIO3, enabled 2124 * for PIO2 if indicated by the device, and otherwise 2125 * probably should be 0. 2126 * 2127 * bit 0 Fast Drive Timing Enable. Enables faster then PIO-0 2128 * timing modes. 2129 */ 2130 2131 /* 2132 * Modify reg40 according to the table 2133 */ 2134 if (atadev->unit == ATA_MASTER) { 2135 mask40 = 0x3300; 2136 new40 = timings[ata_mode2idx(mode)] << 8; 2137 } 2138 else { 2139 mask44 = 0x0f; 2140 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) | 2141 (timings[ata_mode2idx(mode)] & 0x03); 2142 } 2143 2144 /* 2145 * Slave ATA timing register enable 2146 */ 2147 mask40 |= 0x4000; 2148 new40 |= 0x4000; 2149 2150 /* 2151 * Device control bits 3:0 for master, 7:4 for slave. 2152 * 2153 * bit3 DMA Timing enable. 2154 * bit2 Indicate presence of ATA(1) or ATAPI(0) device, set accordingly 2155 * bit1 Enable IORDY sample point capability for PIO xfers. Always 2156 * enabled for PIO4 and PIO3, enabled for PIO2 if indicated by 2157 * the device, and otherwise should be 0. 2158 * bit0 Fast Drive Timing Enable. Enable faster then PIO-0 timing modes. 2159 * 2160 * Set to: 0 x 1 1 2161 */ 2162 2163 if (atadev->unit == ATA_MASTER) { 2164 mask40 |= 0x0F; 2165 new40 |= 0x03; 2166 if (!ata_atapi(dev)) 2167 new40 |= 0x04; 2168 } else { 2169 mask40 |= 0xF0; 2170 new40 |= 0x30; 2171 if (!ata_atapi(dev)) 2172 new40 |= 0x40; 2173 } 2174 /* 2175 reg40 &= ~0x00ff00ff; 2176 reg40 |= 0x40774077; 2177 */ 2178 2179 /* 2180 * Primary or Secondary controller 2181 */ 2182 if (ch->unit) { 2183 mask40 <<= 16; 2184 new40 <<= 16; 2185 mask44 <<= 4; 2186 new44 <<= 4; 2187 } 2188 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4); 2189 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1); 2190 2191 #if 0 2192 reg40 = pci_read_config(gparent, 0x40, 4); 2193 reg44 = pci_read_config(gparent, 0x44, 1); 2194 reg48 = pci_read_config(gparent, 0x48, 1); 2195 reg4a = pci_read_config(gparent, 0x4a, 2); 2196 reg54 = pci_read_config(gparent, 0x54, 2); 2197 device_printf(dev, 2198 "regs after 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 2199 reg40, reg44, reg48 ,reg4a, reg54); 2200 #endif 2201 2202 atadev->mode = mode; 2203 } 2204 2205 static int 2206 ata_intel_31244_allocate(device_t dev) 2207 { 2208 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2209 struct ata_channel *ch = device_get_softc(dev); 2210 int i; 2211 int ch_offset; 2212 2213 ch_offset = 0x200 + ch->unit * 0x200; 2214 2215 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 2216 ch->r_io[i].res = ctlr->r_res2; 2217 2218 /* setup ATA registers */ 2219 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 2220 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 2221 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 2222 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 2223 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 2224 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 2225 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 2226 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 2227 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 2228 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 2229 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 2230 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 2231 2232 /* setup DMA registers */ 2233 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 2234 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 2235 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 2236 2237 /* setup SATA registers */ 2238 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 2239 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 2240 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 2241 2242 ch->flags |= ATA_NO_SLAVE; 2243 ata_pci_hw(dev); 2244 ch->hw.status = ata_intel_31244_status; 2245 ch->hw.command = ata_intel_31244_command; 2246 2247 /* enable PHY state change interrupt */ 2248 ATA_OUTL(ctlr->r_res2, 0x4, 2249 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 2250 return 0; 2251 } 2252 2253 static int 2254 ata_intel_31244_status(device_t dev) 2255 { 2256 /* do we have any PHY events ? */ 2257 ata_sata_phy_check_events(dev); 2258 2259 /* any drive action to take care of ? */ 2260 return ata_pci_status(dev); 2261 } 2262 2263 static int 2264 ata_intel_31244_command(struct ata_request *request) 2265 { 2266 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2267 struct ata_device *atadev = device_get_softc(request->dev); 2268 u_int64_t lba; 2269 2270 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 2271 return (ata_generic_command(request)); 2272 2273 lba = request->u.ata.lba; 2274 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 2275 /* enable interrupt */ 2276 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 2277 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 2278 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 2279 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff)); 2280 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) | 2281 ((lba >> 8) & 0x00ff)); 2282 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) | 2283 ((lba >> 16) & 0x00ff)); 2284 2285 /* issue command to controller */ 2286 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 2287 2288 return 0; 2289 } 2290 2291 static void 2292 ata_intel_31244_reset(device_t dev) 2293 { 2294 if (ata_sata_phy_reset(dev)) 2295 ata_generic_reset(dev); 2296 } 2297 2298 2299 /* 2300 * Integrated Technology Express Inc. (ITE) chipset support functions 2301 */ 2302 int 2303 ata_ite_ident(device_t dev) 2304 { 2305 struct ata_pci_controller *ctlr = device_get_softc(dev); 2306 struct ata_chip_id *idx; 2307 static struct ata_chip_id ids[] = 2308 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 2309 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 2310 { 0, 0, 0, 0, 0, 0}}; 2311 char buffer[64]; 2312 2313 if (!(idx = ata_match_chip(dev, ids))) 2314 return ENXIO; 2315 2316 ksprintf(buffer, "ITE %s %s controller", 2317 idx->text, ata_mode2str(idx->max_dma)); 2318 device_set_desc_copy(dev, buffer); 2319 ctlr->chip = idx; 2320 ctlr->chipinit = ata_ite_chipinit; 2321 return 0; 2322 } 2323 2324 static int 2325 ata_ite_chipinit(device_t dev) 2326 { 2327 struct ata_pci_controller *ctlr = device_get_softc(dev); 2328 2329 if (ata_setup_interrupt(dev)) 2330 return ENXIO; 2331 2332 ctlr->setmode = ata_ite_setmode; 2333 2334 /* set PCI mode and 66Mhz reference clock */ 2335 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 2336 2337 /* set default active & recover timings */ 2338 pci_write_config(dev, 0x54, 0x31, 1); 2339 pci_write_config(dev, 0x56, 0x31, 1); 2340 return 0; 2341 } 2342 2343 static void 2344 ata_ite_setmode(device_t dev, int mode) 2345 { 2346 device_t gparent = GRANDPARENT(dev); 2347 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2348 struct ata_device *atadev = device_get_softc(dev); 2349 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2350 int error; 2351 2352 /* correct the mode for what the HW supports */ 2353 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2354 2355 /* check the CBLID bits for 80 conductor cable detection */ 2356 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) & 2357 (ch->unit ? (1<<3) : (1<<2)))) { 2358 ata_print_cable(dev, "controller"); 2359 mode = ATA_UDMA2; 2360 } 2361 2362 /* set the wanted mode on the device */ 2363 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2364 2365 if (bootverbose) 2366 device_printf(dev, "%s setting %s on ITE8212F chip\n", 2367 (error) ? "failed" : "success", ata_mode2str(mode)); 2368 2369 /* if the device accepted the mode change, setup the HW accordingly */ 2370 if (!error) { 2371 if (mode >= ATA_UDMA0) { 2372 u_int8_t udmatiming[] = 2373 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 2374 2375 /* enable UDMA mode */ 2376 pci_write_config(gparent, 0x50, 2377 pci_read_config(gparent, 0x50, 1) & 2378 ~(1 << (devno + 3)), 1); 2379 2380 /* set UDMA timing */ 2381 pci_write_config(gparent, 2382 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit), 2383 udmatiming[mode & ATA_MODE_MASK], 1); 2384 } 2385 else { 2386 u_int8_t chtiming[] = 2387 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 2388 2389 /* disable UDMA mode */ 2390 pci_write_config(gparent, 0x50, 2391 pci_read_config(gparent, 0x50, 1) | 2392 (1 << (devno + 3)), 1); 2393 2394 /* set active and recover timing (shared between master & slave) */ 2395 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) < 2396 chtiming[ata_mode2idx(mode)]) 2397 pci_write_config(gparent, 0x54 + (ch->unit << 2), 2398 chtiming[ata_mode2idx(mode)], 1); 2399 } 2400 atadev->mode = mode; 2401 } 2402 } 2403 2404 2405 /* 2406 * JMicron chipset support functions 2407 */ 2408 int 2409 ata_jmicron_ident(device_t dev) 2410 { 2411 struct ata_pci_controller *ctlr = device_get_softc(dev); 2412 struct ata_chip_id *idx; 2413 static struct ata_chip_id ids[] = 2414 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" }, 2415 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" }, 2416 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" }, 2417 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" }, 2418 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" }, 2419 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" }, 2420 { 0, 0, 0, 0, 0, 0}}; 2421 char buffer[64]; 2422 2423 if (!(idx = ata_match_chip(dev, ids))) 2424 return ENXIO; 2425 2426 if ((pci_read_config(dev, 0xdf, 1) & 0x40) && 2427 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1))) 2428 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2429 idx->text, ata_mode2str(ATA_UDMA6)); 2430 else 2431 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2432 idx->text, ata_mode2str(idx->max_dma)); 2433 device_set_desc_copy(dev, buffer); 2434 ctlr->chip = idx; 2435 ctlr->chipinit = ata_jmicron_chipinit; 2436 return 0; 2437 } 2438 2439 static int 2440 ata_jmicron_chipinit(device_t dev) 2441 { 2442 struct ata_pci_controller *ctlr = device_get_softc(dev); 2443 int error; 2444 2445 if (ata_setup_interrupt(dev)) 2446 return ENXIO; 2447 2448 /* do we have multiple PCI functions ? */ 2449 if (pci_read_config(dev, 0xdf, 1) & 0x40) { 2450 /* if we have a memory BAR(5) we are on the AHCI part */ 2451 ctlr->r_type2 = SYS_RES_MEMORY; 2452 ctlr->r_rid2 = PCIR_BAR(5); 2453 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 2454 &ctlr->r_rid2, RF_ACTIVE))) 2455 return ata_ahci_chipinit(dev); 2456 2457 /* otherwise we are on the PATA part */ 2458 ctlr->allocate = ata_pci_allocate; 2459 ctlr->reset = ata_generic_reset; 2460 ctlr->dmainit = ata_pci_dmainit; 2461 ctlr->setmode = ata_jmicron_setmode; 2462 ctlr->channels = ctlr->chip->cfg2; 2463 } 2464 else { 2465 /* set controller configuration to a combined setup we support */ 2466 pci_write_config(dev, 0x40, 0x80c0a131, 4); 2467 pci_write_config(dev, 0x80, 0x01200000, 4); 2468 2469 ctlr->r_type2 = SYS_RES_MEMORY; 2470 ctlr->r_rid2 = PCIR_BAR(5); 2471 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 2472 &ctlr->r_rid2, RF_ACTIVE))) { 2473 if ((error = ata_ahci_chipinit(dev))) 2474 return error; 2475 } 2476 2477 ctlr->allocate = ata_jmicron_allocate; 2478 ctlr->reset = ata_jmicron_reset; 2479 ctlr->dmainit = ata_jmicron_dmainit; 2480 ctlr->setmode = ata_jmicron_setmode; 2481 2482 /* set the number of HW channels */ 2483 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2; 2484 } 2485 return 0; 2486 } 2487 2488 static int 2489 ata_jmicron_allocate(device_t dev) 2490 { 2491 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2492 struct ata_channel *ch = device_get_softc(dev); 2493 int error; 2494 2495 if (ch->unit >= ctlr->chip->cfg1) { 2496 ch->unit -= ctlr->chip->cfg1; 2497 error = ata_pci_allocate(dev); 2498 ch->unit += ctlr->chip->cfg1; 2499 } 2500 else 2501 error = ata_ahci_allocate(dev); 2502 return error; 2503 } 2504 2505 static void 2506 ata_jmicron_reset(device_t dev) 2507 { 2508 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2509 struct ata_channel *ch = device_get_softc(dev); 2510 2511 if (ch->unit >= ctlr->chip->cfg1) 2512 ata_generic_reset(dev); 2513 else 2514 ata_ahci_reset(dev); 2515 } 2516 2517 static void 2518 ata_jmicron_dmainit(device_t dev) 2519 { 2520 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2521 struct ata_channel *ch = device_get_softc(dev); 2522 2523 if (ch->unit >= ctlr->chip->cfg1) 2524 ata_pci_dmainit(dev); 2525 else 2526 ata_ahci_dmainit(dev); 2527 } 2528 2529 static void 2530 ata_jmicron_setmode(device_t dev, int mode) 2531 { 2532 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 2533 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2534 2535 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) { 2536 struct ata_device *atadev = device_get_softc(dev); 2537 2538 /* check for 80pin cable present */ 2539 if (pci_read_config(dev, 0x40, 1) & 0x08) 2540 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 2541 else 2542 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2543 2544 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2545 atadev->mode = mode; 2546 } 2547 else 2548 ata_sata_setmode(dev, mode); 2549 } 2550 2551 2552 /* 2553 * Marvell chipset support functions 2554 */ 2555 #define ATA_MV_HOST_BASE(ch) \ 2556 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000) 2557 #define ATA_MV_EDMA_BASE(ch) \ 2558 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000) 2559 2560 struct ata_marvell_response { 2561 u_int16_t tag; 2562 u_int8_t edma_status; 2563 u_int8_t dev_status; 2564 u_int32_t timestamp; 2565 }; 2566 2567 struct ata_marvell_dma_prdentry { 2568 u_int32_t addrlo; 2569 u_int32_t count; 2570 u_int32_t addrhi; 2571 u_int32_t reserved; 2572 }; 2573 2574 int 2575 ata_marvell_ident(device_t dev) 2576 { 2577 struct ata_pci_controller *ctlr = device_get_softc(dev); 2578 struct ata_chip_id *idx; 2579 static struct ata_chip_id ids[] = 2580 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" }, 2581 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" }, 2582 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" }, 2583 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" }, 2584 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" }, 2585 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" }, 2586 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" }, 2587 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" }, 2588 { 0, 0, 0, 0, 0, 0}}; 2589 char buffer[64]; 2590 2591 if (!(idx = ata_match_chip(dev, ids))) 2592 return ENXIO; 2593 2594 ksprintf(buffer, "Marvell %s %s controller", 2595 idx->text, ata_mode2str(idx->max_dma)); 2596 device_set_desc_copy(dev, buffer); 2597 ctlr->chip = idx; 2598 switch (ctlr->chip->cfg2) { 2599 case MV50XX: 2600 case MV60XX: 2601 ctlr->chipinit = ata_marvell_edma_chipinit; 2602 break; 2603 case MV61XX: 2604 ctlr->chipinit = ata_marvell_pata_chipinit; 2605 break; 2606 } 2607 return 0; 2608 } 2609 2610 static int 2611 ata_marvell_pata_chipinit(device_t dev) 2612 { 2613 struct ata_pci_controller *ctlr = device_get_softc(dev); 2614 2615 if (ata_setup_interrupt(dev)) 2616 return ENXIO; 2617 2618 ctlr->allocate = ata_marvell_pata_allocate; 2619 ctlr->setmode = ata_marvell_pata_setmode; 2620 ctlr->channels = ctlr->chip->cfg1; 2621 return 0; 2622 } 2623 2624 static int 2625 ata_marvell_pata_allocate(device_t dev) 2626 { 2627 struct ata_channel *ch = device_get_softc(dev); 2628 2629 /* setup the usual register normal pci style */ 2630 if (ata_pci_allocate(dev)) 2631 return ENXIO; 2632 2633 /* dont use 32 bit PIO transfers */ 2634 ch->flags |= ATA_USE_16BIT; 2635 2636 return 0; 2637 } 2638 2639 static void 2640 ata_marvell_pata_setmode(device_t dev, int mode) 2641 { 2642 device_t gparent = GRANDPARENT(dev); 2643 struct ata_pci_controller *ctlr = device_get_softc(gparent); 2644 struct ata_device *atadev = device_get_softc(dev); 2645 2646 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 2647 mode = ata_check_80pin(dev, mode); 2648 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2649 atadev->mode = mode; 2650 } 2651 2652 static int 2653 ata_marvell_edma_chipinit(device_t dev) 2654 { 2655 struct ata_pci_controller *ctlr = device_get_softc(dev); 2656 2657 if (ata_setup_interrupt(dev)) 2658 return ENXIO; 2659 2660 ctlr->r_type1 = SYS_RES_MEMORY; 2661 ctlr->r_rid1 = PCIR_BAR(0); 2662 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 2663 &ctlr->r_rid1, RF_ACTIVE))) 2664 return ENXIO; 2665 2666 /* mask all host controller interrupts */ 2667 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000); 2668 2669 /* mask all PCI interrupts */ 2670 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000); 2671 2672 ctlr->allocate = ata_marvell_edma_allocate; 2673 ctlr->reset = ata_marvell_edma_reset; 2674 ctlr->dmainit = ata_marvell_edma_dmainit; 2675 ctlr->setmode = ata_sata_setmode; 2676 ctlr->channels = ctlr->chip->cfg1; 2677 2678 /* clear host controller interrupts */ 2679 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000); 2680 if (ctlr->chip->cfg1 > 4) 2681 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000); 2682 2683 /* clear PCI interrupts */ 2684 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000); 2685 2686 /* unmask PCI interrupts we want */ 2687 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff); 2688 2689 /* unmask host controller interrupts we want */ 2690 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ | 2691 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25)); 2692 2693 /* enable PCI interrupt */ 2694 pci_write_config(dev, PCIR_COMMAND, 2695 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 2696 return 0; 2697 } 2698 2699 static int 2700 ata_marvell_edma_allocate(device_t dev) 2701 { 2702 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2703 struct ata_channel *ch = device_get_softc(dev); 2704 u_int64_t work = ch->dma->work_bus; 2705 int i; 2706 2707 /* clear work area */ 2708 bzero(ch->dma->work, 1024+256); 2709 2710 /* set legacy ATA resources */ 2711 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 2712 ch->r_io[i].res = ctlr->r_res1; 2713 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch); 2714 } 2715 ch->r_io[ATA_CONTROL].res = ctlr->r_res1; 2716 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch); 2717 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1; 2718 ata_default_registers(dev); 2719 2720 /* set SATA resources */ 2721 switch (ctlr->chip->cfg2) { 2722 case MV50XX: 2723 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2724 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch); 2725 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2726 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch); 2727 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2728 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch); 2729 break; 2730 case MV60XX: 2731 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2732 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch); 2733 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2734 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch); 2735 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2736 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch); 2737 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1; 2738 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch); 2739 break; 2740 } 2741 2742 ch->flags |= ATA_NO_SLAVE; 2743 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */ 2744 ata_generic_hw(dev); 2745 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction; 2746 ch->hw.end_transaction = ata_marvell_edma_end_transaction; 2747 ch->hw.status = ata_marvell_edma_status; 2748 2749 /* disable the EDMA machinery */ 2750 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2751 DELAY(100000); /* SOS should poll for disabled */ 2752 2753 /* set configuration to non-queued 128b read transfers stop on error */ 2754 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13)); 2755 2756 /* request queue base high */ 2757 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32); 2758 2759 /* request queue in ptr */ 2760 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2761 2762 /* request queue out ptr */ 2763 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0); 2764 2765 /* response queue base high */ 2766 work += 1024; 2767 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32); 2768 2769 /* response queue in ptr */ 2770 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0); 2771 2772 /* response queue out ptr */ 2773 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2774 2775 /* clear SATA error register */ 2776 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 2777 2778 /* clear any outstanding error interrupts */ 2779 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2780 2781 /* unmask all error interrupts */ 2782 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 2783 2784 /* enable EDMA machinery */ 2785 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2786 return 0; 2787 } 2788 2789 static int 2790 ata_marvell_edma_status(device_t dev) 2791 { 2792 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2793 struct ata_channel *ch = device_get_softc(dev); 2794 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60); 2795 int shift = (ch->unit << 1) + (ch->unit > 3); 2796 2797 if (cause & (1 << shift)) { 2798 2799 /* clear interrupt(s) */ 2800 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2801 2802 /* do we have any PHY events ? */ 2803 ata_sata_phy_check_events(dev); 2804 } 2805 2806 /* do we have any device action ? */ 2807 return (cause & (2 << shift)); 2808 } 2809 2810 /* must be called with ATA channel locked and state_mtx held */ 2811 static int 2812 ata_marvell_edma_begin_transaction(struct ata_request *request) 2813 { 2814 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2815 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2816 u_int32_t req_in; 2817 u_int8_t *bytep; 2818 u_int16_t *wordp; 2819 u_int32_t *quadp; 2820 int i, tag = 0x07; 2821 int dummy, error, slot; 2822 2823 /* only DMA R/W goes through the EMDA machine */ 2824 if (request->u.ata.command != ATA_READ_DMA && 2825 request->u.ata.command != ATA_WRITE_DMA) { 2826 2827 /* disable the EDMA machinery */ 2828 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001) 2829 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2830 return ata_begin_transaction(request); 2831 } 2832 2833 /* check for 48 bit access and convert if needed */ 2834 ata_modify_if_48bit(request); 2835 2836 /* check sanity, setup SG list and DMA engine */ 2837 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 2838 request->flags & ATA_R_READ, ch->dma->sg, 2839 &dummy))) { 2840 device_printf(request->dev, "setting up DMA failed\n"); 2841 request->result = error; 2842 return ATA_OP_FINISHED; 2843 } 2844 2845 /* get next free request queue slot */ 2846 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch)); 2847 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f; 2848 bytep = (u_int8_t *)(ch->dma->work); 2849 bytep += (slot << 5); 2850 wordp = (u_int16_t *)bytep; 2851 quadp = (u_int32_t *)bytep; 2852 2853 /* fill in this request */ 2854 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff; 2855 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32; 2856 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1); 2857 2858 i = 10; 2859 bytep[i++] = (request->u.ata.count >> 8) & 0xff; 2860 bytep[i++] = 0x10 | ATA_COUNT; 2861 bytep[i++] = request->u.ata.count & 0xff; 2862 bytep[i++] = 0x10 | ATA_COUNT; 2863 2864 bytep[i++] = (request->u.ata.lba >> 24) & 0xff; 2865 bytep[i++] = 0x10 | ATA_SECTOR; 2866 bytep[i++] = request->u.ata.lba & 0xff; 2867 bytep[i++] = 0x10 | ATA_SECTOR; 2868 2869 bytep[i++] = (request->u.ata.lba >> 32) & 0xff; 2870 bytep[i++] = 0x10 | ATA_CYL_LSB; 2871 bytep[i++] = (request->u.ata.lba >> 8) & 0xff; 2872 bytep[i++] = 0x10 | ATA_CYL_LSB; 2873 2874 bytep[i++] = (request->u.ata.lba >> 40) & 0xff; 2875 bytep[i++] = 0x10 | ATA_CYL_MSB; 2876 bytep[i++] = (request->u.ata.lba >> 16) & 0xff; 2877 bytep[i++] = 0x10 | ATA_CYL_MSB; 2878 2879 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf); 2880 bytep[i++] = 0x10 | ATA_DRIVE; 2881 2882 bytep[i++] = request->u.ata.command; 2883 bytep[i++] = 0x90 | ATA_COMMAND; 2884 2885 /* enable EDMA machinery if needed */ 2886 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) { 2887 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2888 while (!(ATA_INL(ctlr->r_res1, 2889 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 2890 DELAY(10); 2891 } 2892 2893 /* tell EDMA it has a new request */ 2894 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f; 2895 req_in &= 0xfffffc00; 2896 req_in += (slot << 5); 2897 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in); 2898 2899 return ATA_OP_CONTINUES; 2900 } 2901 2902 /* must be called with ATA channel locked and state_mtx held */ 2903 static int 2904 ata_marvell_edma_end_transaction(struct ata_request *request) 2905 { 2906 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2907 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2908 int offset = (ch->unit > 3 ? 0x30014 : 0x20014); 2909 u_int32_t icr = ATA_INL(ctlr->r_res1, offset); 2910 int res; 2911 2912 /* EDMA interrupt */ 2913 if ((icr & (0x0001 << (ch->unit & 3)))) { 2914 struct ata_marvell_response *response; 2915 u_int32_t rsp_in, rsp_out; 2916 int slot; 2917 2918 /* stop timeout */ 2919 callout_stop(&request->callout); 2920 2921 /* get response ptr's */ 2922 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch)); 2923 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch)); 2924 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f; 2925 rsp_out &= 0xffffff00; 2926 rsp_out += (slot << 3); 2927 response = (struct ata_marvell_response *) 2928 (ch->dma->work + 1024 + (slot << 3)); 2929 2930 /* record status for this request */ 2931 request->status = response->dev_status; 2932 request->error = 0; 2933 2934 /* ack response */ 2935 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out); 2936 2937 /* update progress */ 2938 if (!(request->status & ATA_S_ERROR) && 2939 !(request->flags & ATA_R_TIMEOUT)) 2940 request->donecount = request->bytecount; 2941 2942 /* unload SG list */ 2943 ch->dma->unload(ch->dev); 2944 2945 res = ATA_OP_FINISHED; 2946 } 2947 2948 /* legacy ATA interrupt */ 2949 else { 2950 res = ata_end_transaction(request); 2951 } 2952 2953 /* ack interrupt */ 2954 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3)))); 2955 return res; 2956 } 2957 2958 static void 2959 ata_marvell_edma_reset(device_t dev) 2960 { 2961 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2962 struct ata_channel *ch = device_get_softc(dev); 2963 2964 /* disable the EDMA machinery */ 2965 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2966 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 2967 DELAY(10); 2968 2969 /* clear SATA error register */ 2970 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 2971 2972 /* clear any outstanding error interrupts */ 2973 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2974 2975 /* unmask all error interrupts */ 2976 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 2977 2978 /* enable channel and test for devices */ 2979 if (ata_sata_phy_reset(dev)) 2980 ata_generic_reset(dev); 2981 2982 /* enable EDMA machinery */ 2983 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2984 } 2985 2986 static void 2987 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, 2988 int error) 2989 { 2990 struct ata_dmasetprd_args *args = xsc; 2991 struct ata_marvell_dma_prdentry *prd = args->dmatab; 2992 int i; 2993 2994 if ((args->error = error)) 2995 return; 2996 2997 for (i = 0; i < nsegs; i++) { 2998 prd[i].addrlo = htole32(segs[i].ds_addr); 2999 prd[i].count = htole32(segs[i].ds_len); 3000 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32); 3001 } 3002 prd[i - 1].count |= htole32(ATA_DMA_EOT); 3003 } 3004 3005 static void 3006 ata_marvell_edma_dmainit(device_t dev) 3007 { 3008 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3009 struct ata_channel *ch = device_get_softc(dev); 3010 3011 ata_dmainit(dev); 3012 if (ch->dma) { 3013 /* note start and stop are not used here */ 3014 ch->dma->setprd = ata_marvell_edma_dmasetprd; 3015 3016 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004) 3017 ch->dma->max_address = BUS_SPACE_MAXADDR; 3018 3019 /* chip does not reliably do 64K DMA transfers */ 3020 ch->dma->max_iosize = 126 * DEV_BSIZE; 3021 } 3022 } 3023 3024 3025 /* 3026 * National chipset support functions 3027 */ 3028 int 3029 ata_national_ident(device_t dev) 3030 { 3031 struct ata_pci_controller *ctlr = device_get_softc(dev); 3032 3033 /* this chip is a clone of the Cyrix chip, bugs and all */ 3034 if (pci_get_devid(dev) == ATA_SC1100) { 3035 device_set_desc(dev, "National Geode SC1100 ATA33 controller"); 3036 ctlr->chipinit = ata_national_chipinit; 3037 return 0; 3038 } 3039 return ENXIO; 3040 } 3041 3042 static int 3043 ata_national_chipinit(device_t dev) 3044 { 3045 struct ata_pci_controller *ctlr = device_get_softc(dev); 3046 3047 if (ata_setup_interrupt(dev)) 3048 return ENXIO; 3049 3050 ctlr->setmode = ata_national_setmode; 3051 return 0; 3052 } 3053 3054 static void 3055 ata_national_setmode(device_t dev, int mode) 3056 { 3057 device_t gparent = GRANDPARENT(dev); 3058 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3059 struct ata_device *atadev = device_get_softc(dev); 3060 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3061 u_int32_t piotiming[] = 3062 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010, 3063 0x00803020, 0x20102010, 0x00100010, 3064 0x00100010, 0x00100010, 0x00100010 }; 3065 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 }; 3066 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 }; 3067 int error; 3068 3069 ch->dma->alignment = 16; 3070 ch->dma->max_iosize = 126 * DEV_BSIZE; 3071 3072 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 3073 3074 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3075 3076 if (bootverbose) 3077 device_printf(dev, "%s setting %s on National chip\n", 3078 (error) ? "failed" : "success", ata_mode2str(mode)); 3079 if (!error) { 3080 if (mode >= ATA_UDMA0) { 3081 pci_write_config(gparent, 0x44 + (devno << 3), 3082 udmatiming[mode & ATA_MODE_MASK], 4); 3083 } 3084 else if (mode >= ATA_WDMA0) { 3085 pci_write_config(gparent, 0x44 + (devno << 3), 3086 dmatiming[mode & ATA_MODE_MASK], 4); 3087 } 3088 else { 3089 pci_write_config(gparent, 0x44 + (devno << 3), 3090 pci_read_config(gparent, 0x44 + (devno << 3), 4) | 3091 0x80000000, 4); 3092 } 3093 pci_write_config(gparent, 0x40 + (devno << 3), 3094 piotiming[ata_mode2idx(mode)], 4); 3095 atadev->mode = mode; 3096 } 3097 } 3098 3099 /* 3100 * NetCell chipset support functions 3101 */ 3102 int 3103 ata_netcell_ident(device_t dev) 3104 { 3105 struct ata_pci_controller *ctlr = device_get_softc(dev); 3106 3107 if (pci_get_devid(dev) == ATA_NETCELL_SR) { 3108 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller"); 3109 ctlr->chipinit = ata_netcell_chipinit; 3110 return 0; 3111 } 3112 return ENXIO; 3113 } 3114 3115 static int 3116 ata_netcell_chipinit(device_t dev) 3117 { 3118 struct ata_pci_controller *ctlr = device_get_softc(dev); 3119 3120 if (ata_generic_chipinit(dev)) 3121 return ENXIO; 3122 3123 ctlr->allocate = ata_netcell_allocate; 3124 return 0; 3125 } 3126 3127 static int 3128 ata_netcell_allocate(device_t dev) 3129 { 3130 struct ata_channel *ch = device_get_softc(dev); 3131 3132 /* setup the usual register normal pci style */ 3133 if (ata_pci_allocate(dev)) 3134 return ENXIO; 3135 3136 /* the NetCell only supports 16 bit PIO transfers */ 3137 ch->flags |= ATA_USE_16BIT; 3138 3139 return 0; 3140 } 3141 3142 3143 /* 3144 * nVidia chipset support functions 3145 */ 3146 int 3147 ata_nvidia_ident(device_t dev) 3148 { 3149 struct ata_pci_controller *ctlr = device_get_softc(dev); 3150 struct ata_chip_id *idx; 3151 static struct ata_chip_id ids[] = 3152 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" }, 3153 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" }, 3154 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" }, 3155 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" }, 3156 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" }, 3157 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" }, 3158 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3159 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3160 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" }, 3161 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3162 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3163 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" }, 3164 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3165 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3166 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" }, 3167 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3168 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3169 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" }, 3170 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3171 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3172 { 0, 0, 0, 0, 0, 0}} ; 3173 char buffer[64] ; 3174 3175 if (!(idx = ata_match_chip(dev, ids))) 3176 return ENXIO; 3177 3178 ksprintf(buffer, "nVidia %s %s controller", 3179 idx->text, ata_mode2str(idx->max_dma)); 3180 device_set_desc_copy(dev, buffer); 3181 ctlr->chip = idx; 3182 ctlr->chipinit = ata_nvidia_chipinit; 3183 return 0; 3184 } 3185 3186 static int 3187 ata_nvidia_chipinit(device_t dev) 3188 { 3189 struct ata_pci_controller *ctlr = device_get_softc(dev); 3190 3191 if (ata_setup_interrupt(dev)) 3192 return ENXIO; 3193 3194 if (ctlr->chip->max_dma >= ATA_SA150) { 3195 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1) 3196 ctlr->r_type2 = SYS_RES_IOPORT; 3197 else 3198 ctlr->r_type2 = SYS_RES_MEMORY; 3199 ctlr->r_rid2 = PCIR_BAR(5); 3200 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3201 &ctlr->r_rid2, RF_ACTIVE))) { 3202 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3203 3204 ctlr->allocate = ata_nvidia_allocate; 3205 ctlr->reset = ata_nvidia_reset; 3206 3207 /* enable control access */ 3208 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1); 3209 3210 if (ctlr->chip->cfg2 & NVQ) { 3211 /* clear interrupt status */ 3212 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff); 3213 3214 /* enable device and PHY state change interrupts */ 3215 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d); 3216 3217 /* disable NCQ support */ 3218 ATA_OUTL(ctlr->r_res2, 0x0400, 3219 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9); 3220 } 3221 else { 3222 /* clear interrupt status */ 3223 ATA_OUTB(ctlr->r_res2, offset, 0xff); 3224 3225 /* enable device and PHY state change interrupts */ 3226 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd); 3227 } 3228 3229 /* enable PCI interrupt */ 3230 pci_write_config(dev, PCIR_COMMAND, 3231 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 3232 3233 } 3234 ctlr->setmode = ata_sata_setmode; 3235 } 3236 else { 3237 /* disable prefetch, postwrite */ 3238 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1); 3239 ctlr->setmode = ata_via_family_setmode; 3240 } 3241 return 0; 3242 } 3243 3244 static int 3245 ata_nvidia_allocate(device_t dev) 3246 { 3247 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3248 struct ata_channel *ch = device_get_softc(dev); 3249 3250 /* setup the usual register normal pci style */ 3251 if (ata_pci_allocate(dev)) 3252 return ENXIO; 3253 3254 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3255 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6); 3256 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3257 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6); 3258 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3259 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6); 3260 3261 ch->hw.status = ata_nvidia_status; 3262 ch->flags |= ATA_NO_SLAVE; 3263 3264 return 0; 3265 } 3266 3267 static int 3268 ata_nvidia_status(device_t dev) 3269 { 3270 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3271 struct ata_channel *ch = device_get_softc(dev); 3272 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3273 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2); 3274 u_int32_t istatus = ATA_INL(ctlr->r_res2, offset); 3275 3276 /* do we have any PHY events ? */ 3277 if (istatus & (0x0c << shift)) 3278 ata_sata_phy_check_events(dev); 3279 3280 /* clear interrupt(s) */ 3281 ATA_OUTB(ctlr->r_res2, offset, 3282 (0x0f << shift) | (ctlr->chip->cfg2 & NVQ ? 0x00f000f0 : 0)); 3283 3284 /* do we have any device action ? */ 3285 return (istatus & (0x01 << shift)); 3286 } 3287 3288 static void 3289 ata_nvidia_reset(device_t dev) 3290 { 3291 if (ata_sata_phy_reset(dev)) 3292 ata_generic_reset(dev); 3293 } 3294 3295 3296 /* 3297 * Promise chipset support functions 3298 */ 3299 #define ATA_PDC_APKT_OFFSET 0x00000010 3300 #define ATA_PDC_HPKT_OFFSET 0x00000040 3301 #define ATA_PDC_ASG_OFFSET 0x00000080 3302 #define ATA_PDC_LSG_OFFSET 0x000000c0 3303 #define ATA_PDC_HSG_OFFSET 0x00000100 3304 #define ATA_PDC_CHN_OFFSET 0x00000400 3305 #define ATA_PDC_BUF_BASE 0x00400000 3306 #define ATA_PDC_BUF_OFFSET 0x00100000 3307 #define ATA_PDC_MAX_HPKT 8 3308 #define ATA_PDC_WRITE_REG 0x00 3309 #define ATA_PDC_WRITE_CTL 0x0e 3310 #define ATA_PDC_WRITE_END 0x08 3311 #define ATA_PDC_WAIT_NBUSY 0x10 3312 #define ATA_PDC_WAIT_READY 0x18 3313 #define ATA_PDC_1B 0x20 3314 #define ATA_PDC_2B 0x40 3315 3316 struct host_packet { 3317 u_int32_t addr; 3318 TAILQ_ENTRY(host_packet) chain; 3319 }; 3320 3321 struct ata_promise_sx4 { 3322 struct spinlock mtx; 3323 TAILQ_HEAD(, host_packet) queue; 3324 int busy; 3325 }; 3326 3327 int 3328 ata_promise_ident(device_t dev) 3329 { 3330 struct ata_pci_controller *ctlr = device_get_softc(dev); 3331 struct ata_chip_id *idx; 3332 static struct ata_chip_id ids[] = 3333 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" }, 3334 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" }, 3335 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" }, 3336 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" }, 3337 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" }, 3338 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" }, 3339 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" }, 3340 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" }, 3341 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" }, 3342 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" }, 3343 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" }, 3344 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" }, 3345 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" }, 3346 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" }, 3347 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" }, 3348 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" }, 3349 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" }, 3350 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" }, 3351 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" }, 3352 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" }, 3353 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" }, 3354 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" }, 3355 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" }, 3356 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" }, 3357 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" }, 3358 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" }, 3359 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" }, 3360 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" }, 3361 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" }, 3362 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" }, 3363 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" }, 3364 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" }, 3365 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" }, 3366 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" }, 3367 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" }, 3368 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" }, 3369 { 0, 0, 0, 0, 0, 0}}; 3370 char buffer[64]; 3371 uintptr_t devid = 0; 3372 3373 if (!(idx = ata_match_chip(dev, ids))) 3374 return ENXIO; 3375 3376 /* if we are on a SuperTrak SX6000 dont attach */ 3377 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3378 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3379 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3380 devid == ATA_I960RM) 3381 return ENXIO; 3382 3383 strcpy(buffer, "Promise "); 3384 strcat(buffer, idx->text); 3385 3386 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 3387 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3388 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3389 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3390 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 3391 static long start = 0, end = 0; 3392 3393 if (pci_get_slot(dev) == 1) { 3394 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 3395 strcat(buffer, " (channel 0+1)"); 3396 } 3397 else if (pci_get_slot(dev) == 2 && start && end) { 3398 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 3399 strcat(buffer, " (channel 2+3)"); 3400 } 3401 else { 3402 start = end = 0; 3403 } 3404 } 3405 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 3406 device_set_desc_copy(dev, buffer); 3407 ctlr->chip = idx; 3408 ctlr->chipinit = ata_promise_chipinit; 3409 return 0; 3410 } 3411 3412 static int 3413 ata_promise_chipinit(device_t dev) 3414 { 3415 struct ata_pci_controller *ctlr = device_get_softc(dev); 3416 int fake_reg, stat_reg; 3417 3418 if (ata_setup_interrupt(dev)) 3419 return ENXIO; 3420 3421 switch (ctlr->chip->cfg1) { 3422 case PRNEW: 3423 /* setup clocks */ 3424 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 3425 3426 ctlr->dmainit = ata_promise_dmainit; 3427 /* FALLTHROUGH */ 3428 3429 case PROLD: 3430 /* enable burst mode */ 3431 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 3432 ctlr->allocate = ata_promise_allocate; 3433 ctlr->setmode = ata_promise_setmode; 3434 return 0; 3435 3436 case PRTX: 3437 ctlr->allocate = ata_promise_tx2_allocate; 3438 ctlr->setmode = ata_promise_setmode; 3439 return 0; 3440 3441 case PRMIO: 3442 ctlr->r_type1 = SYS_RES_MEMORY; 3443 ctlr->r_rid1 = PCIR_BAR(4); 3444 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 3445 &ctlr->r_rid1, RF_ACTIVE))) 3446 goto failnfree; 3447 3448 ctlr->r_type2 = SYS_RES_MEMORY; 3449 ctlr->r_rid2 = PCIR_BAR(3); 3450 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3451 &ctlr->r_rid2, RF_ACTIVE))) 3452 goto failnfree; 3453 3454 if (ctlr->chip->cfg2 == PRSX4X) { 3455 struct ata_promise_sx4 *hpkt; 3456 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 3457 3458 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3459 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3460 ata_promise_sx4_intr, ctlr, &ctlr->handle, NULL)) { 3461 device_printf(dev, "unable to setup interrupt\n"); 3462 goto failnfree; 3463 } 3464 3465 /* print info about cache memory */ 3466 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 3467 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 3468 ((dimm >> 24) & 0xff), 3469 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 3470 " ECC enabled" : "" ); 3471 3472 /* adjust cache memory parameters */ 3473 ATA_OUTL(ctlr->r_res2, 0x000c000c, 3474 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 3475 3476 /* setup host packet controls */ 3477 hpkt = kmalloc(sizeof(struct ata_promise_sx4), 3478 M_TEMP, M_INTWAIT | M_ZERO); 3479 spin_init(&hpkt->mtx); 3480 TAILQ_INIT(&hpkt->queue); 3481 hpkt->busy = 0; 3482 device_set_ivars(dev, hpkt); 3483 ctlr->allocate = ata_promise_mio_allocate; 3484 ctlr->reset = ata_promise_mio_reset; 3485 ctlr->dmainit = ata_promise_mio_dmainit; 3486 ctlr->setmode = ata_promise_setmode; 3487 ctlr->channels = 4; 3488 return 0; 3489 } 3490 3491 /* mio type controllers need an interrupt intercept */ 3492 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3493 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3494 ata_promise_mio_intr, ctlr, &ctlr->handle, NULL)) { 3495 device_printf(dev, "unable to setup interrupt\n"); 3496 goto failnfree; 3497 } 3498 3499 switch (ctlr->chip->cfg2) { 3500 case PRPATA: 3501 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 3502 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 3503 goto sata150; 3504 case PRCMBO: 3505 ctlr->channels = 3; 3506 goto sata150; 3507 case PRSATA: 3508 ctlr->channels = 4; 3509 sata150: 3510 fake_reg = 0x60; 3511 stat_reg = 0x6c; 3512 break; 3513 3514 case PRCMBO2: 3515 ctlr->channels = 3; 3516 goto sataii; 3517 case PRSATA2: 3518 default: 3519 ctlr->channels = 4; 3520 sataii: 3521 fake_reg = 0x54; 3522 stat_reg = 0x60; 3523 break; 3524 } 3525 3526 /* prime fake interrupt register */ 3527 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3528 3529 /* clear SATA status */ 3530 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 3531 3532 ctlr->allocate = ata_promise_mio_allocate; 3533 ctlr->reset = ata_promise_mio_reset; 3534 ctlr->dmainit = ata_promise_mio_dmainit; 3535 ctlr->setmode = ata_promise_mio_setmode; 3536 3537 return 0; 3538 } 3539 3540 failnfree: 3541 if (ctlr->r_res2) 3542 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 3543 if (ctlr->r_res1) 3544 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 3545 return ENXIO; 3546 } 3547 3548 static int 3549 ata_promise_allocate(device_t dev) 3550 { 3551 struct ata_channel *ch = device_get_softc(dev); 3552 3553 if (ata_pci_allocate(dev)) 3554 return ENXIO; 3555 3556 ch->hw.status = ata_promise_status; 3557 return 0; 3558 } 3559 3560 static int 3561 ata_promise_status(device_t dev) 3562 { 3563 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3564 struct ata_channel *ch = device_get_softc(dev); 3565 3566 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 3567 return ata_pci_status(dev); 3568 } 3569 return 0; 3570 } 3571 3572 static int 3573 ata_promise_dmastart(device_t dev) 3574 { 3575 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3576 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3577 struct ata_device *atadev = device_get_softc(dev); 3578 3579 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3580 ATA_OUTB(ctlr->r_res1, 0x11, 3581 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 3582 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 3583 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) | 3584 (ch->dma->cur_iosize >> 1)); 3585 } 3586 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 3587 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 3588 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus); 3589 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3590 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) | 3591 ATA_BMCMD_START_STOP); 3592 ch->flags |= ATA_DMA_ACTIVE; 3593 return 0; 3594 } 3595 3596 static int 3597 ata_promise_dmastop(device_t dev) 3598 { 3599 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3600 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3601 struct ata_device *atadev = device_get_softc(dev); 3602 int error; 3603 3604 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3605 ATA_OUTB(ctlr->r_res1, 0x11, 3606 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 3607 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 3608 } 3609 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 3610 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3611 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3612 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3613 ch->flags &= ~ATA_DMA_ACTIVE; 3614 return error; 3615 } 3616 3617 static void 3618 ata_promise_dmareset(device_t dev) 3619 { 3620 struct ata_channel *ch = device_get_softc(dev); 3621 3622 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3623 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3624 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3625 ch->flags &= ~ATA_DMA_ACTIVE; 3626 } 3627 3628 static void 3629 ata_promise_dmainit(device_t dev) 3630 { 3631 struct ata_channel *ch = device_get_softc(dev); 3632 3633 ata_dmainit(dev); 3634 if (ch->dma) { 3635 ch->dma->start = ata_promise_dmastart; 3636 ch->dma->stop = ata_promise_dmastop; 3637 ch->dma->reset = ata_promise_dmareset; 3638 } 3639 } 3640 3641 static void 3642 ata_promise_setmode(device_t dev, int mode) 3643 { 3644 device_t gparent = GRANDPARENT(dev); 3645 struct ata_pci_controller *ctlr = device_get_softc(gparent); 3646 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3647 struct ata_device *atadev = device_get_softc(dev); 3648 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3649 int error; 3650 u_int32_t timings[][2] = { 3651 /* PROLD PRNEW mode */ 3652 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 3653 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 3654 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 3655 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 3656 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 3657 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 3658 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 3659 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 3660 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 3661 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 3662 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 3663 { 0, 0x00424ef6 }, /* UDMA 3 */ 3664 { 0, 0x004127f3 }, /* UDMA 4 */ 3665 { 0, 0x004127f3 } /* UDMA 5 */ 3666 }; 3667 3668 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 3669 3670 switch (ctlr->chip->cfg1) { 3671 case PROLD: 3672 case PRNEW: 3673 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) & 3674 (ch->unit ? 1 << 11 : 1 << 10))) { 3675 ata_print_cable(dev, "controller"); 3676 mode = ATA_UDMA2; 3677 } 3678 if (ata_atapi(dev) && mode > ATA_PIO_MAX) 3679 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 3680 break; 3681 3682 case PRTX: 3683 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3684 if (mode > ATA_UDMA2 && 3685 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 3686 ata_print_cable(dev, "controller"); 3687 mode = ATA_UDMA2; 3688 } 3689 break; 3690 3691 case PRMIO: 3692 if (mode > ATA_UDMA2 && 3693 (ATA_INL(ctlr->r_res2, 3694 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) + 3695 (ch->unit << 7)) & 0x01000000)) { 3696 ata_print_cable(dev, "controller"); 3697 mode = ATA_UDMA2; 3698 } 3699 break; 3700 } 3701 3702 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3703 3704 if (bootverbose) 3705 device_printf(dev, "%ssetting %s on %s chip\n", 3706 (error) ? "FAILURE " : "", 3707 ata_mode2str(mode), ctlr->chip->text); 3708 if (!error) { 3709 if (ctlr->chip->cfg1 < PRTX) 3710 pci_write_config(gparent, 0x60 + (devno << 2), 3711 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 3712 atadev->mode = mode; 3713 } 3714 return; 3715 } 3716 3717 static int 3718 ata_promise_tx2_allocate(device_t dev) 3719 { 3720 struct ata_channel *ch = device_get_softc(dev); 3721 3722 if (ata_pci_allocate(dev)) 3723 return ENXIO; 3724 3725 ch->hw.status = ata_promise_tx2_status; 3726 return 0; 3727 } 3728 3729 static int 3730 ata_promise_tx2_status(device_t dev) 3731 { 3732 struct ata_channel *ch = device_get_softc(dev); 3733 3734 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3735 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 3736 return ata_pci_status(dev); 3737 } 3738 return 0; 3739 } 3740 3741 static int 3742 ata_promise_mio_allocate(device_t dev) 3743 { 3744 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3745 struct ata_channel *ch = device_get_softc(dev); 3746 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0; 3747 int i; 3748 3749 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 3750 ch->r_io[i].res = ctlr->r_res2; 3751 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 3752 } 3753 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 3754 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 3755 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 3756 ata_default_registers(dev); 3757 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) || 3758 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) { 3759 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3760 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 3761 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3762 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 3763 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3764 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 3765 ch->flags |= ATA_NO_SLAVE; 3766 } 3767 ch->flags |= ATA_USE_16BIT; 3768 3769 ata_generic_hw(dev); 3770 if (ctlr->chip->cfg2 & PRSX4X) { 3771 ch->hw.command = ata_promise_sx4_command; 3772 } 3773 else { 3774 ch->hw.command = ata_promise_mio_command; 3775 ch->hw.status = ata_promise_mio_status; 3776 } 3777 return 0; 3778 } 3779 3780 static void 3781 ata_promise_mio_intr(void *data) 3782 { 3783 struct ata_pci_controller *ctlr = data; 3784 struct ata_channel *ch; 3785 u_int32_t vector; 3786 int unit, fake_reg; 3787 3788 switch (ctlr->chip->cfg2) { 3789 case PRPATA: 3790 case PRCMBO: 3791 case PRSATA: 3792 fake_reg = 0x60; 3793 break; 3794 case PRCMBO2: 3795 case PRSATA2: 3796 default: 3797 fake_reg = 0x54; 3798 break; 3799 } 3800 3801 /* 3802 * since reading interrupt status register on early "mio" chips 3803 * clears the status bits we cannot read it for each channel later on 3804 * in the generic interrupt routine. 3805 * store the bits in an unused register in the chip so we can read 3806 * it from there safely to get around this "feature". 3807 */ 3808 vector = ATA_INL(ctlr->r_res2, 0x040); 3809 ATA_OUTL(ctlr->r_res2, 0x040, vector); 3810 ATA_OUTL(ctlr->r_res2, fake_reg, vector); 3811 3812 for (unit = 0; unit < ctlr->channels; unit++) { 3813 if ((ch = ctlr->interrupt[unit].argument)) 3814 ctlr->interrupt[unit].function(ch); 3815 } 3816 3817 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3818 } 3819 3820 static int 3821 ata_promise_mio_status(device_t dev) 3822 { 3823 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3824 struct ata_channel *ch = device_get_softc(dev); 3825 struct ata_connect_task *tp; 3826 u_int32_t fake_reg, stat_reg, vector, status; 3827 3828 switch (ctlr->chip->cfg2) { 3829 case PRPATA: 3830 case PRCMBO: 3831 case PRSATA: 3832 fake_reg = 0x60; 3833 stat_reg = 0x6c; 3834 break; 3835 case PRCMBO2: 3836 case PRSATA2: 3837 default: 3838 fake_reg = 0x54; 3839 stat_reg = 0x60; 3840 break; 3841 } 3842 3843 /* read and acknowledge interrupt */ 3844 vector = ATA_INL(ctlr->r_res2, fake_reg); 3845 3846 /* read and clear interface status */ 3847 status = ATA_INL(ctlr->r_res2, stat_reg); 3848 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 3849 3850 /* check for and handle disconnect events */ 3851 if ((status & (0x00000001 << ch->unit)) && 3852 (tp = (struct ata_connect_task *) 3853 kmalloc(sizeof(struct ata_connect_task), 3854 M_ATA, M_INTWAIT | M_ZERO))) { 3855 3856 if (bootverbose) 3857 device_printf(ch->dev, "DISCONNECT requested\n"); 3858 tp->action = ATA_C_DETACH; 3859 tp->dev = ch->dev; 3860 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3861 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3862 } 3863 3864 /* check for and handle connect events */ 3865 if ((status & (0x00000010 << ch->unit)) && 3866 (tp = (struct ata_connect_task *) 3867 kmalloc(sizeof(struct ata_connect_task), 3868 M_ATA, M_INTWAIT | M_ZERO))) { 3869 3870 if (bootverbose) 3871 device_printf(ch->dev, "CONNECT requested\n"); 3872 tp->action = ATA_C_ATTACH; 3873 tp->dev = ch->dev; 3874 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3875 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3876 } 3877 3878 /* do we have any device action ? */ 3879 return (vector & (1 << (ch->unit + 1))); 3880 } 3881 3882 static int 3883 ata_promise_mio_command(struct ata_request *request) 3884 { 3885 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 3886 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 3887 u_int32_t *wordp = (u_int32_t *)ch->dma->work; 3888 3889 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 3890 3891 /* XXX SOS add ATAPI commands support later */ 3892 switch (request->u.ata.command) { 3893 default: 3894 return ata_generic_command(request); 3895 3896 case ATA_READ_DMA: 3897 case ATA_READ_DMA48: 3898 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3899 break; 3900 3901 case ATA_WRITE_DMA: 3902 case ATA_WRITE_DMA48: 3903 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3904 break; 3905 } 3906 wordp[1] = htole32(ch->dma->sg_bus); 3907 wordp[2] = 0; 3908 ata_promise_apkt((u_int8_t*)wordp, request); 3909 3910 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus); 3911 return 0; 3912 } 3913 3914 static void 3915 ata_promise_mio_reset(device_t dev) 3916 { 3917 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3918 struct ata_channel *ch = device_get_softc(dev); 3919 struct ata_promise_sx4 *hpktp; 3920 3921 switch (ctlr->chip->cfg2) { 3922 case PRSX4X: 3923 3924 /* softreset channel ATA module */ 3925 hpktp = device_get_ivars(ctlr->dev); 3926 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 3927 ata_udelay(1000); 3928 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 3929 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 3930 ~0x00003f9f) | (ch->unit + 1)); 3931 3932 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 3933 spin_lock_wr(&hpktp->mtx); 3934 ATA_OUTL(ctlr->r_res2, 0xc012c, 3935 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 3936 DELAY(10); 3937 ATA_OUTL(ctlr->r_res2, 0xc012c, 3938 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 3939 hpktp->busy = 0; 3940 spin_unlock_wr(&hpktp->mtx); 3941 ata_generic_reset(dev); 3942 break; 3943 3944 case PRPATA: 3945 case PRCMBO: 3946 case PRSATA: 3947 if ((ctlr->chip->cfg2 == PRSATA) || 3948 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 3949 3950 /* mask plug/unplug intr */ 3951 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 3952 } 3953 3954 /* softreset channels ATA module */ 3955 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 3956 ata_udelay(10000); 3957 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 3958 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 3959 ~0x00003f9f) | (ch->unit + 1)); 3960 3961 if ((ctlr->chip->cfg2 == PRSATA) || 3962 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 3963 3964 if (ata_sata_phy_reset(dev)) 3965 ata_generic_reset(dev); 3966 3967 /* reset and enable plug/unplug intr */ 3968 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 3969 } 3970 else 3971 ata_generic_reset(dev); 3972 break; 3973 3974 case PRCMBO2: 3975 case PRSATA2: 3976 if ((ctlr->chip->cfg2 == PRSATA2) || 3977 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 3978 /* set portmultiplier port */ 3979 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 3980 3981 /* mask plug/unplug intr */ 3982 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 3983 } 3984 3985 /* softreset channels ATA module */ 3986 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 3987 ata_udelay(10000); 3988 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 3989 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 3990 ~0x00003f9f) | (ch->unit + 1)); 3991 3992 if ((ctlr->chip->cfg2 == PRSATA2) || 3993 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 3994 3995 /* set PHY mode to "improved" */ 3996 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 3997 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 3998 ~0x00000003) | 0x00000001); 3999 4000 if (ata_sata_phy_reset(dev)) 4001 ata_generic_reset(dev); 4002 4003 /* reset and enable plug/unplug intr */ 4004 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 4005 4006 /* set portmultiplier port */ 4007 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 4008 } 4009 else 4010 ata_generic_reset(dev); 4011 break; 4012 4013 } 4014 } 4015 4016 static void 4017 ata_promise_mio_dmainit(device_t dev) 4018 { 4019 /* note start and stop are not used here */ 4020 ata_dmainit(dev); 4021 } 4022 4023 static void 4024 ata_promise_mio_setmode(device_t dev, int mode) 4025 { 4026 device_t gparent = GRANDPARENT(dev); 4027 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4028 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4029 4030 if ( (ctlr->chip->cfg2 == PRSATA) || 4031 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) || 4032 (ctlr->chip->cfg2 == PRSATA2) || 4033 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) 4034 ata_sata_setmode(dev, mode); 4035 else 4036 ata_promise_setmode(dev, mode); 4037 } 4038 4039 static void 4040 ata_promise_sx4_intr(void *data) 4041 { 4042 struct ata_pci_controller *ctlr = data; 4043 struct ata_channel *ch; 4044 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 4045 int unit; 4046 4047 for (unit = 0; unit < ctlr->channels; unit++) { 4048 if (vector & (1 << (unit + 1))) 4049 if ((ch = ctlr->interrupt[unit].argument)) 4050 ctlr->interrupt[unit].function(ch); 4051 if (vector & (1 << (unit + 5))) 4052 if ((ch = ctlr->interrupt[unit].argument)) 4053 ata_promise_queue_hpkt(ctlr, 4054 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 4055 ATA_PDC_HPKT_OFFSET)); 4056 if (vector & (1 << (unit + 9))) { 4057 ata_promise_next_hpkt(ctlr); 4058 if ((ch = ctlr->interrupt[unit].argument)) 4059 ctlr->interrupt[unit].function(ch); 4060 } 4061 if (vector & (1 << (unit + 13))) { 4062 ata_promise_next_hpkt(ctlr); 4063 if ((ch = ctlr->interrupt[unit].argument)) 4064 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4065 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 4066 ATA_PDC_APKT_OFFSET)); 4067 } 4068 } 4069 } 4070 4071 static int 4072 ata_promise_sx4_command(struct ata_request *request) 4073 { 4074 device_t gparent = GRANDPARENT(request->dev); 4075 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4076 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4077 struct ata_dma_prdentry *prd = ch->dma->sg; 4078 caddr_t window = rman_get_virtual(ctlr->r_res1); 4079 u_int32_t *wordp; 4080 int i, idx, length = 0; 4081 4082 /* XXX SOS add ATAPI commands support later */ 4083 switch (request->u.ata.command) { 4084 4085 default: 4086 return -1; 4087 4088 case ATA_ATA_IDENTIFY: 4089 case ATA_READ: 4090 case ATA_READ48: 4091 case ATA_READ_MUL: 4092 case ATA_READ_MUL48: 4093 case ATA_WRITE: 4094 case ATA_WRITE48: 4095 case ATA_WRITE_MUL: 4096 case ATA_WRITE_MUL48: 4097 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4098 return ata_generic_command(request); 4099 4100 case ATA_SETFEATURES: 4101 case ATA_FLUSHCACHE: 4102 case ATA_FLUSHCACHE48: 4103 case ATA_SLEEP: 4104 case ATA_SET_MULTI: 4105 wordp = (u_int32_t *) 4106 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4107 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 4108 wordp[1] = 0; 4109 wordp[2] = 0; 4110 ata_promise_apkt((u_int8_t *)wordp, request); 4111 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4112 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4113 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4114 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 4115 return 0; 4116 4117 case ATA_READ_DMA: 4118 case ATA_READ_DMA48: 4119 case ATA_WRITE_DMA: 4120 case ATA_WRITE_DMA48: 4121 wordp = (u_int32_t *) 4122 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 4123 i = idx = 0; 4124 do { 4125 wordp[idx++] = prd[i].addr; 4126 wordp[idx++] = prd[i].count; 4127 length += (prd[i].count & ~ATA_DMA_EOT); 4128 } while (!(prd[i++].count & ATA_DMA_EOT)); 4129 4130 wordp = (u_int32_t *) 4131 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 4132 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4133 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4134 4135 wordp = (u_int32_t *) 4136 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 4137 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4138 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4139 4140 wordp = (u_int32_t *) 4141 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 4142 if (request->flags & ATA_R_READ) 4143 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 4144 if (request->flags & ATA_R_WRITE) 4145 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 4146 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 4147 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 4148 wordp[3] = 0; 4149 4150 wordp = (u_int32_t *) 4151 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4152 if (request->flags & ATA_R_READ) 4153 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 4154 if (request->flags & ATA_R_WRITE) 4155 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 4156 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 4157 wordp[2] = 0; 4158 ata_promise_apkt((u_int8_t *)wordp, request); 4159 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4160 4161 if (request->flags & ATA_R_READ) { 4162 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 4163 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 4164 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4165 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 4166 } 4167 if (request->flags & ATA_R_WRITE) { 4168 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 4169 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 4170 ata_promise_queue_hpkt(ctlr, 4171 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 4172 } 4173 return 0; 4174 } 4175 } 4176 4177 static int 4178 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 4179 { 4180 struct ata_device *atadev = device_get_softc(request->dev); 4181 int i = 12; 4182 4183 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 4184 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit; 4185 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 4186 bytep[i++] = ATA_A_4BIT; 4187 4188 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 4189 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4190 bytep[i++] = request->u.ata.feature >> 8; 4191 bytep[i++] = request->u.ata.feature; 4192 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 4193 bytep[i++] = request->u.ata.count >> 8; 4194 bytep[i++] = request->u.ata.count; 4195 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4196 bytep[i++] = request->u.ata.lba >> 24; 4197 bytep[i++] = request->u.ata.lba; 4198 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4199 bytep[i++] = request->u.ata.lba >> 32; 4200 bytep[i++] = request->u.ata.lba >> 8; 4201 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4202 bytep[i++] = request->u.ata.lba >> 40; 4203 bytep[i++] = request->u.ata.lba >> 16; 4204 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4205 bytep[i++] = ATA_D_LBA | atadev->unit; 4206 } 4207 else { 4208 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4209 bytep[i++] = request->u.ata.feature; 4210 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 4211 bytep[i++] = request->u.ata.count; 4212 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4213 bytep[i++] = request->u.ata.lba; 4214 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4215 bytep[i++] = request->u.ata.lba >> 8; 4216 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4217 bytep[i++] = request->u.ata.lba >> 16; 4218 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4219 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) | 4220 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf); 4221 } 4222 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 4223 bytep[i++] = request->u.ata.command; 4224 return i; 4225 } 4226 4227 static void 4228 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 4229 { 4230 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4231 4232 spin_lock_wr(&hpktp->mtx); 4233 if (hpktp->busy) { 4234 struct host_packet *hp = 4235 kmalloc(sizeof(struct host_packet), M_TEMP, M_INTWAIT | M_ZERO); 4236 hp->addr = hpkt; 4237 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 4238 } 4239 else { 4240 hpktp->busy = 1; 4241 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 4242 } 4243 spin_unlock_wr(&hpktp->mtx); 4244 } 4245 4246 static void 4247 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 4248 { 4249 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4250 struct host_packet *hp; 4251 4252 spin_lock_wr(&hpktp->mtx); 4253 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 4254 TAILQ_REMOVE(&hpktp->queue, hp, chain); 4255 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 4256 kfree(hp, M_TEMP); 4257 } 4258 else 4259 hpktp->busy = 0; 4260 spin_unlock_wr(&hpktp->mtx); 4261 } 4262 4263 4264 /* 4265 * ServerWorks chipset support functions 4266 */ 4267 int 4268 ata_serverworks_ident(device_t dev) 4269 { 4270 struct ata_pci_controller *ctlr = device_get_softc(dev); 4271 struct ata_chip_id *idx; 4272 static struct ata_chip_id ids[] = 4273 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" }, 4274 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" }, 4275 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" }, 4276 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" }, 4277 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" }, 4278 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" }, 4279 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" }, 4280 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" }, 4281 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" }, 4282 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" }, 4283 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" }, 4284 { 0, 0, 0, 0, 0, 0}}; 4285 char buffer[64]; 4286 4287 if (!(idx = ata_match_chip(dev, ids))) 4288 return ENXIO; 4289 4290 ksprintf(buffer, "ServerWorks %s %s controller", 4291 idx->text, ata_mode2str(idx->max_dma)); 4292 device_set_desc_copy(dev, buffer); 4293 ctlr->chip = idx; 4294 ctlr->chipinit = ata_serverworks_chipinit; 4295 return 0; 4296 } 4297 4298 static int 4299 ata_serverworks_chipinit(device_t dev) 4300 { 4301 struct ata_pci_controller *ctlr = device_get_softc(dev); 4302 4303 if (ata_setup_interrupt(dev)) 4304 return ENXIO; 4305 4306 if (ctlr->chip->cfg1 == SWKSMIO) { 4307 ctlr->r_type2 = SYS_RES_MEMORY; 4308 ctlr->r_rid2 = PCIR_BAR(5); 4309 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4310 &ctlr->r_rid2, RF_ACTIVE))) 4311 return ENXIO; 4312 4313 ctlr->channels = ctlr->chip->cfg2; 4314 ctlr->allocate = ata_serverworks_allocate; 4315 ctlr->setmode = ata_sata_setmode; 4316 return 0; 4317 } 4318 else if (ctlr->chip->cfg1 == SWKS33) { 4319 device_t *children; 4320 int nchildren, i; 4321 4322 /* locate the ISA part in the southbridge and enable UDMA33 */ 4323 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 4324 for (i = 0; i < nchildren; i++) { 4325 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 4326 pci_write_config(children[i], 0x64, 4327 (pci_read_config(children[i], 0x64, 4) & 4328 ~0x00002000) | 0x00004000, 4); 4329 break; 4330 } 4331 } 4332 kfree(children, M_TEMP); 4333 } 4334 } 4335 else { 4336 pci_write_config(dev, 0x5a, 4337 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 4338 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1); 4339 } 4340 ctlr->setmode = ata_serverworks_setmode; 4341 return 0; 4342 } 4343 4344 static int 4345 ata_serverworks_allocate(device_t dev) 4346 { 4347 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4348 struct ata_channel *ch = device_get_softc(dev); 4349 int ch_offset; 4350 int i; 4351 4352 ch_offset = ch->unit * 0x100; 4353 4354 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 4355 ch->r_io[i].res = ctlr->r_res2; 4356 4357 /* setup ATA registers */ 4358 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 4359 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 4360 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 4361 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 4362 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 4363 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 4364 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 4365 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 4366 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 4367 ata_default_registers(dev); 4368 4369 /* setup DMA registers */ 4370 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 4371 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 4372 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 4373 4374 /* setup SATA registers */ 4375 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 4376 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 4377 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 4378 4379 ch->flags |= ATA_NO_SLAVE; 4380 ata_pci_hw(dev); 4381 4382 /* chip does not reliably do 64K DMA transfers */ 4383 if (ch->dma) 4384 ch->dma->max_iosize = 126 * DEV_BSIZE; 4385 4386 return 0; 4387 } 4388 4389 static void 4390 ata_serverworks_setmode(device_t dev, int mode) 4391 { 4392 device_t gparent = GRANDPARENT(dev); 4393 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4394 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4395 struct ata_device *atadev = device_get_softc(dev); 4396 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4397 int offset = (devno ^ 0x01) << 3; 4398 int error; 4399 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 4400 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 4401 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 4402 4403 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4404 4405 mode = ata_check_80pin(dev, mode); 4406 4407 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4408 4409 if (bootverbose) 4410 device_printf(dev, "%ssetting %s on %s chip\n", 4411 (error) ? "FAILURE " : "", 4412 ata_mode2str(mode), ctlr->chip->text); 4413 if (!error) { 4414 if (mode >= ATA_UDMA0) { 4415 pci_write_config(gparent, 0x56, 4416 (pci_read_config(gparent, 0x56, 2) & 4417 ~(0xf << (devno << 2))) | 4418 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 4419 pci_write_config(gparent, 0x54, 4420 pci_read_config(gparent, 0x54, 1) | 4421 (0x01 << devno), 1); 4422 pci_write_config(gparent, 0x44, 4423 (pci_read_config(gparent, 0x44, 4) & 4424 ~(0xff << offset)) | 4425 (dmatimings[2] << offset), 4); 4426 } 4427 else if (mode >= ATA_WDMA0) { 4428 pci_write_config(gparent, 0x54, 4429 pci_read_config(gparent, 0x54, 1) & 4430 ~(0x01 << devno), 1); 4431 pci_write_config(gparent, 0x44, 4432 (pci_read_config(gparent, 0x44, 4) & 4433 ~(0xff << offset)) | 4434 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 4435 } 4436 else 4437 pci_write_config(gparent, 0x54, 4438 pci_read_config(gparent, 0x54, 1) & 4439 ~(0x01 << devno), 1); 4440 4441 pci_write_config(gparent, 0x40, 4442 (pci_read_config(gparent, 0x40, 4) & 4443 ~(0xff << offset)) | 4444 (piotimings[ata_mode2idx(mode)] << offset), 4); 4445 atadev->mode = mode; 4446 } 4447 } 4448 4449 4450 /* 4451 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 4452 */ 4453 int 4454 ata_sii_ident(device_t dev) 4455 { 4456 struct ata_pci_controller *ctlr = device_get_softc(dev); 4457 struct ata_chip_id *idx; 4458 static struct ata_chip_id ids[] = 4459 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" }, 4460 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" }, 4461 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4462 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4463 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" }, 4464 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4465 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4466 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" }, 4467 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" }, 4468 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" }, 4469 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" }, 4470 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" }, 4471 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" }, 4472 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" }, 4473 { 0, 0, 0, 0, 0, 0}}; 4474 char buffer[64]; 4475 4476 if (!(idx = ata_match_chip(dev, ids))) 4477 return ENXIO; 4478 4479 ksprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); 4480 device_set_desc_copy(dev, buffer); 4481 ctlr->chip = idx; 4482 ctlr->chipinit = ata_sii_chipinit; 4483 return 0; 4484 } 4485 4486 static int 4487 ata_sii_chipinit(device_t dev) 4488 { 4489 struct ata_pci_controller *ctlr = device_get_softc(dev); 4490 4491 if (ata_setup_interrupt(dev)) 4492 return ENXIO; 4493 4494 switch (ctlr->chip->cfg1) { 4495 case SIIPRBIO: 4496 ctlr->r_type1 = SYS_RES_MEMORY; 4497 ctlr->r_rid1 = PCIR_BAR(0); 4498 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 4499 &ctlr->r_rid1, RF_ACTIVE))) 4500 return ENXIO; 4501 4502 ctlr->r_rid2 = PCIR_BAR(2); 4503 ctlr->r_type2 = SYS_RES_MEMORY; 4504 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4505 &ctlr->r_rid2, RF_ACTIVE))){ 4506 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 4507 return ENXIO; 4508 } 4509 ctlr->allocate = ata_siiprb_allocate; 4510 ctlr->reset = ata_siiprb_reset; 4511 ctlr->dmainit = ata_siiprb_dmainit; 4512 ctlr->setmode = ata_sata_setmode; 4513 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2; 4514 4515 /* reset controller */ 4516 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 4517 DELAY(10000); 4518 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 4519 4520 /* enable PCI interrupt */ 4521 pci_write_config(dev, PCIR_COMMAND, 4522 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 4523 break; 4524 4525 case SIIMEMIO: 4526 ctlr->r_type2 = SYS_RES_MEMORY; 4527 ctlr->r_rid2 = PCIR_BAR(5); 4528 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4529 &ctlr->r_rid2, RF_ACTIVE))) 4530 return ENXIO; 4531 4532 if (ctlr->chip->cfg2 & SIISETCLK) { 4533 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4534 pci_write_config(dev, 0x8a, 4535 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 4536 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4537 device_printf(dev, "%s could not set ATA133 clock\n", 4538 ctlr->chip->text); 4539 } 4540 4541 /* if we have 4 channels enable the second set */ 4542 if (ctlr->chip->cfg2 & SII4CH) { 4543 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 4544 ctlr->channels = 4; 4545 } 4546 4547 /* dont block interrupts from any channel */ 4548 pci_write_config(dev, 0x48, 4549 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 4550 4551 /* enable PCI interrupt as BIOS might not */ 4552 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 4553 4554 ctlr->allocate = ata_sii_allocate; 4555 if (ctlr->chip->max_dma >= ATA_SA150) { 4556 ctlr->reset = ata_sii_reset; 4557 ctlr->setmode = ata_sata_setmode; 4558 } 4559 else 4560 ctlr->setmode = ata_sii_setmode; 4561 break; 4562 4563 default: 4564 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 4565 device_printf(dev, "HW has secondary channel disabled\n"); 4566 ctlr->channels = 1; 4567 } 4568 4569 /* enable interrupt as BIOS might not */ 4570 pci_write_config(dev, 0x71, 0x01, 1); 4571 4572 ctlr->allocate = ata_cmd_allocate; 4573 ctlr->setmode = ata_cmd_setmode; 4574 break; 4575 } 4576 return 0; 4577 } 4578 4579 static int 4580 ata_cmd_allocate(device_t dev) 4581 { 4582 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4583 struct ata_channel *ch = device_get_softc(dev); 4584 4585 /* setup the usual register normal pci style */ 4586 if (ata_pci_allocate(dev)) 4587 return ENXIO; 4588 4589 if (ctlr->chip->cfg2 & SIIINTR) 4590 ch->hw.status = ata_cmd_status; 4591 4592 return 0; 4593 } 4594 4595 static int 4596 ata_cmd_status(device_t dev) 4597 { 4598 struct ata_channel *ch = device_get_softc(dev); 4599 u_int8_t reg71; 4600 4601 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) & 4602 (ch->unit ? 0x08 : 0x04))) { 4603 pci_write_config(device_get_parent(ch->dev), 0x71, 4604 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 4605 return ata_pci_status(dev); 4606 } 4607 return 0; 4608 } 4609 4610 static void 4611 ata_cmd_setmode(device_t dev, int mode) 4612 { 4613 device_t gparent = GRANDPARENT(dev); 4614 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4615 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4616 struct ata_device *atadev = device_get_softc(dev); 4617 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4618 int error; 4619 4620 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4621 4622 mode = ata_check_80pin(dev, mode); 4623 4624 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4625 4626 if (bootverbose) 4627 device_printf(dev, "%ssetting %s on %s chip\n", 4628 (error) ? "FAILURE " : "", 4629 ata_mode2str(mode), ctlr->chip->text); 4630 if (!error) { 4631 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 4632 int ureg = ch->unit ? 0x7b : 0x73; 4633 4634 if (mode >= ATA_UDMA0) { 4635 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 4636 { 0x11, 0x42 }, { 0x25, 0x8a }, 4637 { 0x15, 0x4a }, { 0x05, 0x0a } }; 4638 4639 u_int8_t umode = pci_read_config(gparent, ureg, 1); 4640 4641 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca); 4642 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)]; 4643 pci_write_config(gparent, ureg, umode, 1); 4644 } 4645 else if (mode >= ATA_WDMA0) { 4646 int dmatimings[] = { 0x87, 0x32, 0x3f }; 4647 4648 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1); 4649 pci_write_config(gparent, ureg, 4650 pci_read_config(gparent, ureg, 1) & 4651 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4652 } 4653 else { 4654 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f }; 4655 pci_write_config(gparent, treg, 4656 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1); 4657 pci_write_config(gparent, ureg, 4658 pci_read_config(gparent, ureg, 1) & 4659 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4660 } 4661 atadev->mode = mode; 4662 } 4663 } 4664 4665 static int 4666 ata_sii_allocate(device_t dev) 4667 { 4668 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4669 struct ata_channel *ch = device_get_softc(dev); 4670 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 4671 int i; 4672 4673 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 4674 ch->r_io[i].res = ctlr->r_res2; 4675 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 4676 } 4677 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 4678 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 4679 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 4680 ata_default_registers(dev); 4681 4682 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 4683 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 4684 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 4685 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 4686 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 4687 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 4688 4689 if (ctlr->chip->max_dma >= ATA_SA150) { 4690 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4691 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 4692 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4693 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 4694 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4695 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 4696 ch->flags |= ATA_NO_SLAVE; 4697 4698 /* enable PHY state change interrupt */ 4699 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 4700 } 4701 4702 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) { 4703 /* work around errata in early chips */ 4704 ch->dma->boundary = 16 * DEV_BSIZE; 4705 ch->dma->segsize = 15 * DEV_BSIZE; 4706 } 4707 4708 ata_pci_hw(dev); 4709 ch->hw.status = ata_sii_status; 4710 return 0; 4711 } 4712 4713 static int 4714 ata_sii_status(device_t dev) 4715 { 4716 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4717 struct ata_channel *ch = device_get_softc(dev); 4718 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 4719 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 4720 4721 /* do we have any PHY events ? */ 4722 if (ctlr->chip->max_dma >= ATA_SA150 && 4723 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 4724 ata_sata_phy_check_events(dev); 4725 4726 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 4727 return ata_pci_status(dev); 4728 else 4729 return 0; 4730 } 4731 4732 static void 4733 ata_sii_reset(device_t dev) 4734 { 4735 if (ata_sata_phy_reset(dev)) 4736 ata_generic_reset(dev); 4737 } 4738 4739 static void 4740 ata_sii_setmode(device_t dev, int mode) 4741 { 4742 device_t gparent = GRANDPARENT(dev); 4743 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4744 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4745 struct ata_device *atadev = device_get_softc(dev); 4746 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1); 4747 int mreg = ch->unit ? 0x84 : 0x80; 4748 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2); 4749 int mval = pci_read_config(gparent, mreg, 1) & ~mask; 4750 int error; 4751 4752 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4753 4754 if (ctlr->chip->cfg2 & SIISETCLK) { 4755 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) & 4756 (ch->unit ? 0x02 : 0x01))) { 4757 ata_print_cable(dev, "controller"); 4758 mode = ATA_UDMA2; 4759 } 4760 } 4761 else 4762 mode = ata_check_80pin(dev, mode); 4763 4764 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4765 4766 if (bootverbose) 4767 device_printf(dev, "%ssetting %s on %s chip\n", 4768 (error) ? "FAILURE " : "", 4769 ata_mode2str(mode), ctlr->chip->text); 4770 if (error) 4771 return; 4772 4773 if (mode >= ATA_UDMA0) { 4774 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 4775 u_int8_t ureg = 0xac + rego; 4776 4777 pci_write_config(gparent, mreg, 4778 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1); 4779 pci_write_config(gparent, ureg, 4780 (pci_read_config(gparent, ureg, 1) & ~0x3f) | 4781 udmatimings[mode & ATA_MODE_MASK], 1); 4782 4783 } 4784 else if (mode >= ATA_WDMA0) { 4785 u_int8_t dreg = 0xa8 + rego; 4786 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 4787 4788 pci_write_config(gparent, mreg, 4789 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1); 4790 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 4791 4792 } 4793 else { 4794 u_int8_t preg = 0xa4 + rego; 4795 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 4796 4797 pci_write_config(gparent, mreg, 4798 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1); 4799 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2); 4800 } 4801 atadev->mode = mode; 4802 } 4803 4804 struct ata_siiprb_dma_prdentry { 4805 u_int64_t addr; 4806 u_int32_t count; 4807 u_int32_t control; 4808 } __packed; 4809 4810 struct ata_siiprb_ata_command { 4811 u_int32_t reserved0; 4812 struct ata_siiprb_dma_prdentry prd[126]; 4813 } __packed; 4814 4815 struct ata_siiprb_atapi_command { 4816 u_int8_t cdb[16]; 4817 struct ata_siiprb_dma_prdentry prd[125]; 4818 } __packed; 4819 4820 struct ata_siiprb_command { 4821 u_int16_t control; 4822 u_int16_t protocol_override; 4823 u_int32_t transfer_count; 4824 u_int8_t fis[20]; 4825 union { 4826 struct ata_siiprb_ata_command ata; 4827 struct ata_siiprb_atapi_command atapi; 4828 } u; 4829 } __packed; 4830 4831 static int 4832 ata_siiprb_allocate(device_t dev) 4833 { 4834 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4835 struct ata_channel *ch = device_get_softc(dev); 4836 int offset = ch->unit * 0x2000; 4837 4838 /* set the SATA resources */ 4839 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4840 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 4841 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4842 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 4843 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4844 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 4845 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 4846 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 4847 4848 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 4849 ch->hw.end_transaction = ata_siiprb_end_transaction; 4850 ch->hw.status = ata_siiprb_status; 4851 ch->hw.command = NULL; /* not used here */ 4852 return 0; 4853 } 4854 4855 static int 4856 ata_siiprb_status(device_t dev) 4857 { 4858 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4859 struct ata_channel *ch = device_get_softc(dev); 4860 int offset = ch->unit * 0x2000; 4861 4862 if ((ATA_INL(ctlr->r_res1, 0x0044) & (1 << ch->unit))) { 4863 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 4864 4865 /* do we have any PHY events ? */ 4866 ata_sata_phy_check_events(dev); 4867 4868 /* clear interrupt(s) */ 4869 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 4870 4871 /* do we have any device action ? */ 4872 return (istatus & 0x00000001); 4873 } 4874 return 0; 4875 } 4876 4877 static int 4878 ata_siiprb_begin_transaction(struct ata_request *request) 4879 { 4880 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 4881 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4882 struct ata_siiprb_command *prb; 4883 int offset = ch->unit * 0x2000; 4884 u_int64_t prb_bus; 4885 int tag = 0, dummy; 4886 4887 /* check for 48 bit access and convert if needed */ 4888 ata_modify_if_48bit(request); 4889 4890 /* get a piece of the workspace for this request */ 4891 prb = (struct ata_siiprb_command *) 4892 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 4893 4894 /* set basic prd options ata/atapi etc etc */ 4895 bzero(prb, sizeof(struct ata_siiprb_command)); 4896 4897 /* setup the FIS for this request */ 4898 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 4899 device_printf(request->dev, "setting up SATA FIS failed\n"); 4900 request->result = EIO; 4901 return ATA_OP_FINISHED; 4902 } 4903 4904 /* if request moves data setup and load SG list */ 4905 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 4906 struct ata_siiprb_dma_prdentry *prd; 4907 4908 if (request->flags & ATA_R_ATAPI) 4909 prd = &prb->u.atapi.prd[0]; 4910 else 4911 prd = &prb->u.ata.prd[0]; 4912 if (ch->dma->load(ch->dev, request->data, request->bytecount, 4913 request->flags & ATA_R_READ, prd, &dummy)) { 4914 device_printf(request->dev, "setting up DMA failed\n"); 4915 request->result = EIO; 4916 return ATA_OP_FINISHED; 4917 } 4918 } 4919 4920 /* activate the prb */ 4921 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 4922 ATA_OUTL(ctlr->r_res2, 4923 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 4924 ATA_OUTL(ctlr->r_res2, 4925 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 4926 4927 /* start the timeout */ 4928 callout_reset(&request->callout, request->timeout * hz, 4929 (timeout_t*)ata_timeout, request); 4930 return ATA_OP_CONTINUES; 4931 } 4932 4933 static int 4934 ata_siiprb_end_transaction(struct ata_request *request) 4935 { 4936 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 4937 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4938 struct ata_siiprb_command *prb; 4939 int offset = ch->unit * 0x2000; 4940 int error, tag = 0; 4941 4942 /* kill the timeout */ 4943 callout_stop(&request->callout); 4944 4945 prb = (struct ata_siiprb_command *) 4946 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 4947 4948 /* if error status get details */ 4949 request->status = prb->fis[2]; 4950 if (request->status & ATA_S_ERROR) 4951 request->error = prb->fis[3]; 4952 4953 /* update progress */ 4954 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 4955 if (request->flags & ATA_R_READ) 4956 request->donecount = prb->transfer_count; 4957 else 4958 request->donecount = request->bytecount; 4959 } 4960 4961 /* any controller errors flagged ? */ 4962 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 4963 kprintf("ata_siiprb_end_transaction %s error=%08x\n", 4964 ata_cmd2str(request), error); 4965 } 4966 4967 /* release SG list etc */ 4968 ch->dma->unload(ch->dev); 4969 4970 return ATA_OP_FINISHED; 4971 } 4972 4973 static void 4974 ata_siiprb_reset(device_t dev) 4975 { 4976 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4977 struct ata_channel *ch = device_get_softc(dev); 4978 int offset = ch->unit * 0x2000; 4979 struct ata_siiprb_command *prb; 4980 u_int64_t prb_bus; 4981 u_int32_t status, signature; 4982 int timeout, tag = 0; 4983 4984 /* reset channel HW */ 4985 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 4986 DELAY(1000); 4987 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 4988 DELAY(10000); 4989 4990 /* poll for channel ready */ 4991 for (timeout = 0; timeout < 1000; timeout++) { 4992 if ((status = ATA_INL(ctlr->r_res2, 0x1000 + offset)) & 0x00040000) 4993 break; 4994 DELAY(1000); 4995 } 4996 if (timeout >= 1000) { 4997 device_printf(ch->dev, "channel HW reset timeout reset failure\n"); 4998 ch->devices = 0; 4999 goto finish; 5000 } 5001 if (bootverbose) 5002 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout * 1); 5003 5004 /* reset phy */ 5005 if (!ata_sata_phy_reset(dev)) { 5006 if (bootverbose) 5007 device_printf(ch->dev, "phy reset found no device\n"); 5008 ch->devices = 0; 5009 goto finish; 5010 } 5011 5012 /* get a piece of the workspace for a soft reset request */ 5013 prb = (struct ata_siiprb_command *) 5014 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 5015 bzero(prb, sizeof(struct ata_siiprb_command)); 5016 prb->control = htole16(0x0080); 5017 5018 /* activate the soft reset prb */ 5019 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 5020 ATA_OUTL(ctlr->r_res2, 5021 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 5022 ATA_OUTL(ctlr->r_res2, 5023 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 5024 5025 /* poll for channel ready */ 5026 for (timeout = 0; timeout < 1000; timeout++) { 5027 DELAY(1000); 5028 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 5029 break; 5030 } 5031 if (timeout >= 1000) { 5032 device_printf(ch->dev, "reset timeout - no device found\n"); 5033 ch->devices = 0; 5034 goto finish; 5035 } 5036 if (bootverbose) 5037 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n", 5038 timeout, status); 5039 5040 /* find out whats there */ 5041 prb = (struct ata_siiprb_command *) 5042 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 5043 signature = 5044 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 5045 if (bootverbose) 5046 device_printf(ch->dev, "signature=%08x\n", signature); 5047 switch (signature) { 5048 case 0xeb140101: 5049 ch->devices = ATA_ATAPI_MASTER; 5050 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n"); 5051 ch->devices = 0; 5052 break; 5053 case 0x96690101: 5054 ch->devices = ATA_PORTMULTIPLIER; 5055 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 5056 ch->devices = 0; 5057 break; 5058 case 0x00000101: 5059 ch->devices = ATA_ATA_MASTER; 5060 break; 5061 default: 5062 ch->devices = 0; 5063 } 5064 5065 finish: 5066 /* clear interrupt(s) */ 5067 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 5068 5069 /* require explicit interrupt ack */ 5070 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 5071 5072 /* 64bit mode */ 5073 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 5074 5075 /* enable interrupts wanted */ 5076 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 5077 } 5078 5079 static void 5080 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 5081 { 5082 struct ata_dmasetprd_args *args = xsc; 5083 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 5084 int i; 5085 5086 if ((args->error = error)) 5087 return; 5088 5089 for (i = 0; i < nsegs; i++) { 5090 prd[i].addr = htole64(segs[i].ds_addr); 5091 prd[i].count = htole32(segs[i].ds_len); 5092 } 5093 prd[i - 1].control = htole32(ATA_DMA_EOT); 5094 } 5095 5096 static void 5097 ata_siiprb_dmainit(device_t dev) 5098 { 5099 struct ata_channel *ch = device_get_softc(dev); 5100 5101 ata_dmainit(dev); 5102 if (ch->dma) { 5103 /* note start and stop are not used here */ 5104 ch->dma->setprd = ata_siiprb_dmasetprd; 5105 ch->dma->max_address = BUS_SPACE_MAXADDR; 5106 } 5107 } 5108 5109 5110 /* 5111 * Silicon Integrated Systems Corp. (SiS) chipset support functions 5112 */ 5113 int 5114 ata_sis_ident(device_t dev) 5115 { 5116 struct ata_pci_controller *ctlr = device_get_softc(dev); 5117 struct ata_chip_id *idx; 5118 static struct ata_chip_id ids[] = 5119 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */ 5120 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */ 5121 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */ 5122 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */ 5123 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */ 5124 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */ 5125 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */ 5126 5127 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */ 5128 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */ 5129 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */ 5130 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */ 5131 5132 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */ 5133 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */ 5134 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */ 5135 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */ 5136 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */ 5137 5138 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" }, 5139 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" }, 5140 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" }, 5141 5142 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" }, 5143 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" }, 5144 { 0, 0, 0, 0, 0, 0 }}; 5145 char buffer[64]; 5146 int found = 0; 5147 5148 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev)))) 5149 return ENXIO; 5150 5151 if (idx->cfg2 && !found) { 5152 u_int8_t reg57 = pci_read_config(dev, 0x57, 1); 5153 5154 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1); 5155 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) { 5156 found = 1; 5157 idx->cfg1 = SIS133NEW; 5158 idx->max_dma = ATA_UDMA6; 5159 ksprintf(buffer, "SiS 962/963 %s controller", 5160 ata_mode2str(idx->max_dma)); 5161 } 5162 pci_write_config(dev, 0x57, reg57, 1); 5163 } 5164 if (idx->cfg2 && !found) { 5165 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1); 5166 5167 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1); 5168 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) { 5169 struct ata_chip_id id[] = 5170 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }}; 5171 5172 found = 1; 5173 if (ata_find_chip(dev, id, pci_get_slot(dev))) { 5174 idx->cfg1 = SIS133OLD; 5175 idx->max_dma = ATA_UDMA6; 5176 } 5177 else { 5178 idx->cfg1 = SIS100NEW; 5179 idx->max_dma = ATA_UDMA5; 5180 } 5181 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma)); 5182 } 5183 pci_write_config(dev, 0x4a, reg4a, 1); 5184 } 5185 if (!found) 5186 ksprintf(buffer,"SiS %s %s controller", 5187 idx->text, ata_mode2str(idx->max_dma)); 5188 5189 device_set_desc_copy(dev, buffer); 5190 ctlr->chip = idx; 5191 ctlr->chipinit = ata_sis_chipinit; 5192 return 0; 5193 } 5194 5195 static int 5196 ata_sis_chipinit(device_t dev) 5197 { 5198 struct ata_pci_controller *ctlr = device_get_softc(dev); 5199 5200 if (ata_setup_interrupt(dev)) 5201 return ENXIO; 5202 5203 switch (ctlr->chip->cfg1) { 5204 case SIS33: 5205 break; 5206 case SIS66: 5207 case SIS100OLD: 5208 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1); 5209 break; 5210 case SIS100NEW: 5211 case SIS133OLD: 5212 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1); 5213 break; 5214 case SIS133NEW: 5215 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2); 5216 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2); 5217 break; 5218 case SISSATA: 5219 ctlr->r_type2 = SYS_RES_IOPORT; 5220 ctlr->r_rid2 = PCIR_BAR(5); 5221 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5222 &ctlr->r_rid2, RF_ACTIVE))) { 5223 ctlr->allocate = ata_sis_allocate; 5224 ctlr->reset = ata_sis_reset; 5225 5226 /* enable PCI interrupt */ 5227 pci_write_config(dev, PCIR_COMMAND, 5228 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5229 } 5230 ctlr->setmode = ata_sata_setmode; 5231 return 0; 5232 default: 5233 return ENXIO; 5234 } 5235 ctlr->setmode = ata_sis_setmode; 5236 return 0; 5237 } 5238 5239 static int 5240 ata_sis_allocate(device_t dev) 5241 { 5242 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5243 struct ata_channel *ch = device_get_softc(dev); 5244 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6); 5245 5246 /* setup the usual register normal pci style */ 5247 if (ata_pci_allocate(dev)) 5248 return ENXIO; 5249 5250 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5251 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; 5252 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5253 ch->r_io[ATA_SERROR].offset = 0x04 + offset; 5254 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5255 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; 5256 ch->flags |= ATA_NO_SLAVE; 5257 5258 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ 5259 /* XXX SOS unknown how to enable PHY state change interrupt */ 5260 return 0; 5261 } 5262 5263 static void 5264 ata_sis_reset(device_t dev) 5265 { 5266 if (ata_sata_phy_reset(dev)) 5267 ata_generic_reset(dev); 5268 } 5269 5270 static void 5271 ata_sis_setmode(device_t dev, int mode) 5272 { 5273 device_t gparent = GRANDPARENT(dev); 5274 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5275 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5276 struct ata_device *atadev = device_get_softc(dev); 5277 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5278 int error; 5279 5280 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5281 5282 if (ctlr->chip->cfg1 == SIS133NEW) { 5283 if (mode > ATA_UDMA2 && 5284 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) { 5285 ata_print_cable(dev, "controller"); 5286 mode = ATA_UDMA2; 5287 } 5288 } 5289 else { 5290 if (mode > ATA_UDMA2 && 5291 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) { 5292 ata_print_cable(dev, "controller"); 5293 mode = ATA_UDMA2; 5294 } 5295 } 5296 5297 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5298 5299 if (bootverbose) 5300 device_printf(dev, "%ssetting %s on %s chip\n", 5301 (error) ? "FAILURE " : "", 5302 ata_mode2str(mode), ctlr->chip->text); 5303 if (!error) { 5304 switch (ctlr->chip->cfg1) { 5305 case SIS133NEW: { 5306 u_int32_t timings[] = 5307 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 5308 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 5309 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; 5310 u_int32_t reg; 5311 5312 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); 5313 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4); 5314 break; 5315 } 5316 case SIS133OLD: { 5317 u_int16_t timings[] = 5318 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 5319 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; 5320 5321 u_int16_t reg = 0x40 + (devno << 1); 5322 5323 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5324 break; 5325 } 5326 case SIS100NEW: { 5327 u_int16_t timings[] = 5328 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 5329 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; 5330 u_int16_t reg = 0x40 + (devno << 1); 5331 5332 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5333 break; 5334 } 5335 case SIS100OLD: 5336 case SIS66: 5337 case SIS33: { 5338 u_int16_t timings[] = 5339 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 5340 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; 5341 u_int16_t reg = 0x40 + (devno << 1); 5342 5343 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5344 break; 5345 } 5346 } 5347 atadev->mode = mode; 5348 } 5349 } 5350 5351 5352 /* VIA Technologies Inc. chipset support functions */ 5353 int 5354 ata_via_ident(device_t dev) 5355 { 5356 struct ata_pci_controller *ctlr = device_get_softc(dev); 5357 struct ata_chip_id *idx; 5358 static struct ata_chip_id ids[] = 5359 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 5360 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 5361 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 5362 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 5363 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 5364 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 5365 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 5366 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 5367 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 5368 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 5369 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 5370 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 5371 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 5372 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 5373 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 5374 { 0, 0, 0, 0, 0, 0 }}; 5375 static struct ata_chip_id new_ids[] = 5376 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 5377 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 5378 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 5379 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 5380 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" }, 5381 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" }, 5382 { 0, 0, 0, 0, 0, 0 }}; 5383 char buffer[64]; 5384 5385 if (pci_get_devid(dev) == ATA_VIA82C571) { 5386 if (!(idx = ata_find_chip(dev, ids, -99))) 5387 return ENXIO; 5388 } 5389 else { 5390 if (!(idx = ata_match_chip(dev, new_ids))) 5391 return ENXIO; 5392 } 5393 5394 ksprintf(buffer, "VIA %s %s controller", 5395 idx->text, ata_mode2str(idx->max_dma)); 5396 device_set_desc_copy(dev, buffer); 5397 ctlr->chip = idx; 5398 ctlr->chipinit = ata_via_chipinit; 5399 return 0; 5400 } 5401 5402 static int 5403 ata_via_chipinit(device_t dev) 5404 { 5405 struct ata_pci_controller *ctlr = device_get_softc(dev); 5406 5407 if (ata_setup_interrupt(dev)) 5408 return ENXIO; 5409 5410 if (ctlr->chip->max_dma >= ATA_SA150) { 5411 if (ctlr->chip->cfg2 == VIAAHCI) { 5412 ctlr->r_type2 = SYS_RES_MEMORY; 5413 ctlr->r_rid2 = PCIR_BAR(5); 5414 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5415 &ctlr->r_rid2, 5416 RF_ACTIVE))) { 5417 return ata_ahci_chipinit(dev); 5418 } 5419 } 5420 ctlr->r_type2 = SYS_RES_IOPORT; 5421 ctlr->r_rid2 = PCIR_BAR(5); 5422 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5423 &ctlr->r_rid2, RF_ACTIVE))) { 5424 ctlr->allocate = ata_via_allocate; 5425 ctlr->reset = ata_via_reset; 5426 5427 /* enable PCI interrupt */ 5428 pci_write_config(dev, PCIR_COMMAND, 5429 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5430 } 5431 5432 if (ctlr->chip->cfg2 & VIABAR) { 5433 ctlr->channels = 3; 5434 ctlr->setmode = ata_via_setmode; 5435 } 5436 else 5437 ctlr->setmode = ata_sata_setmode; 5438 return 0; 5439 } 5440 5441 /* prepare for ATA-66 on the 82C686a and 82C596b */ 5442 if (ctlr->chip->cfg2 & VIACLK) 5443 pci_write_config(dev, 0x50, 0x030b030b, 4); 5444 5445 /* the southbridge might need the data corruption fix */ 5446 if (ctlr->chip->cfg2 & VIABUG) 5447 ata_via_southbridge_fixup(dev); 5448 5449 /* set fifo configuration half'n'half */ 5450 pci_write_config(dev, 0x43, 5451 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 5452 5453 /* set status register read retry */ 5454 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 5455 5456 /* set DMA read & end-of-sector fifo flush */ 5457 pci_write_config(dev, 0x46, 5458 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 5459 5460 /* set sector size */ 5461 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 5462 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 5463 5464 ctlr->setmode = ata_via_family_setmode; 5465 return 0; 5466 } 5467 5468 static int 5469 ata_via_allocate(device_t dev) 5470 { 5471 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5472 struct ata_channel *ch = device_get_softc(dev); 5473 5474 /* newer SATA chips has resources in one BAR for each channel */ 5475 if (ctlr->chip->cfg2 & VIABAR) { 5476 struct resource *r_io; 5477 int i, rid; 5478 5479 rid = PCIR_BAR(ch->unit); 5480 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 5481 SYS_RES_IOPORT, 5482 &rid, RF_ACTIVE))) 5483 return ENXIO; 5484 5485 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 5486 ch->r_io[i].res = r_io; 5487 ch->r_io[i].offset = i; 5488 } 5489 ch->r_io[ATA_CONTROL].res = r_io; 5490 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 5491 ch->r_io[ATA_IDX_ADDR].res = r_io; 5492 ata_default_registers(dev); 5493 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 5494 ch->r_io[i].res = ctlr->r_res1; 5495 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 5496 } 5497 ata_pci_hw(dev); 5498 if (ch->unit >= 2) 5499 return 0; 5500 } 5501 else { 5502 /* setup the usual register normal pci style */ 5503 if (ata_pci_allocate(dev)) 5504 return ENXIO; 5505 } 5506 5507 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5508 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 5509 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5510 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 5511 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5512 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 5513 ch->flags |= ATA_NO_SLAVE; 5514 5515 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */ 5516 /* XXX SOS unknown how to enable PHY state change interrupt */ 5517 return 0; 5518 } 5519 5520 static void 5521 ata_via_reset(device_t dev) 5522 { 5523 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5524 struct ata_channel *ch = device_get_softc(dev); 5525 5526 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 5527 ata_generic_reset(dev); 5528 else 5529 if (ata_sata_phy_reset(dev)) 5530 ata_generic_reset(dev); 5531 } 5532 5533 static void 5534 ata_via_setmode(device_t dev, int mode) 5535 { 5536 device_t gparent = GRANDPARENT(dev); 5537 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5538 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5539 struct ata_device *atadev = device_get_softc(dev); 5540 int error; 5541 5542 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 5543 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20, 5544 0x65, 0x32, 0x20, 5545 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5546 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 5547 5548 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6)); 5549 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5550 if (bootverbose) 5551 device_printf(dev, "%ssetting %s on %s chip\n", 5552 (error) ? "FAILURE " : "", ata_mode2str(mode), 5553 ctlr->chip->text); 5554 if (!error) { 5555 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1); 5556 if (mode >= ATA_UDMA0) 5557 pci_write_config(gparent, 0xb3, 5558 dma_timings[mode & ATA_MODE_MASK], 1); 5559 atadev->mode = mode; 5560 } 5561 } 5562 else 5563 ata_sata_setmode(dev, mode); 5564 } 5565 5566 static void 5567 ata_via_southbridge_fixup(device_t dev) 5568 { 5569 device_t *children; 5570 int nchildren, i; 5571 5572 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5573 return; 5574 5575 for (i = 0; i < nchildren; i++) { 5576 if (pci_get_devid(children[i]) == ATA_VIA8363 || 5577 pci_get_devid(children[i]) == ATA_VIA8371 || 5578 pci_get_devid(children[i]) == ATA_VIA8662 || 5579 pci_get_devid(children[i]) == ATA_VIA8361) { 5580 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 5581 5582 if ((reg76 & 0xf0) != 0xd0) { 5583 device_printf(dev, 5584 "Correcting VIA config for southbridge data corruption bug\n"); 5585 pci_write_config(children[i], 0x75, 0x80, 1); 5586 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 5587 } 5588 break; 5589 } 5590 } 5591 kfree(children, M_TEMP); 5592 } 5593 5594 5595 /* common code for VIA, AMD & nVidia */ 5596 static void 5597 ata_via_family_setmode(device_t dev, int mode) 5598 { 5599 device_t gparent = GRANDPARENT(dev); 5600 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5601 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5602 struct ata_device *atadev = device_get_softc(dev); 5603 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20, 5604 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5605 int modes[][7] = { 5606 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 5607 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 5608 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 5609 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */ 5610 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */ 5611 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5612 int reg = 0x53 - devno; 5613 int error; 5614 5615 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5616 5617 if (ctlr->chip->cfg2 & AMDCABLE) { 5618 if (mode > ATA_UDMA2 && 5619 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) { 5620 ata_print_cable(dev, "controller"); 5621 mode = ATA_UDMA2; 5622 } 5623 } 5624 else 5625 mode = ata_check_80pin(dev, mode); 5626 5627 if (ctlr->chip->cfg2 & NVIDIA) 5628 reg += 0x10; 5629 5630 if (ctlr->chip->cfg1 != VIA133) 5631 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1); 5632 5633 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5634 5635 if (bootverbose) 5636 device_printf(dev, "%ssetting %s on %s chip\n", 5637 (error) ? "FAILURE " : "", ata_mode2str(mode), 5638 ctlr->chip->text); 5639 if (!error) { 5640 if (mode >= ATA_UDMA0) 5641 pci_write_config(gparent, reg, 5642 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 5643 else 5644 pci_write_config(gparent, reg, 0x8b, 1); 5645 atadev->mode = mode; 5646 } 5647 } 5648 5649 5650 /* misc functions */ 5651 static struct ata_chip_id * 5652 ata_match_chip(device_t dev, struct ata_chip_id *index) 5653 { 5654 while (index->chipid != 0) { 5655 if (pci_get_devid(dev) == index->chipid && 5656 pci_get_revid(dev) >= index->chiprev) 5657 return index; 5658 index++; 5659 } 5660 return NULL; 5661 } 5662 5663 static struct ata_chip_id * 5664 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot) 5665 { 5666 device_t *children; 5667 int nchildren, i; 5668 5669 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5670 return 0; 5671 5672 while (index->chipid != 0) { 5673 for (i = 0; i < nchildren; i++) { 5674 if (((slot >= 0 && pci_get_slot(children[i]) == slot) || 5675 (slot < 0 && pci_get_slot(children[i]) <= -slot)) && 5676 pci_get_devid(children[i]) == index->chipid && 5677 pci_get_revid(children[i]) >= index->chiprev) { 5678 kfree(children, M_TEMP); 5679 return index; 5680 } 5681 } 5682 index++; 5683 } 5684 kfree(children, M_TEMP); 5685 return NULL; 5686 } 5687 5688 static int 5689 ata_setup_interrupt(device_t dev) 5690 { 5691 struct ata_pci_controller *ctlr = device_get_softc(dev); 5692 int rid = ATA_IRQ_RID; 5693 5694 if (!ata_legacy(dev)) { 5695 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 5696 RF_SHAREABLE | RF_ACTIVE))) { 5697 device_printf(dev, "unable to map interrupt\n"); 5698 return ENXIO; 5699 } 5700 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 5701 ata_generic_intr, ctlr, &ctlr->handle, NULL))) { 5702 device_printf(dev, "unable to setup interrupt\n"); 5703 return ENXIO; 5704 } 5705 } 5706 return 0; 5707 } 5708 5709 struct ata_serialize { 5710 struct spinlock locked_mtx; 5711 int locked_ch; 5712 int restart_ch; 5713 }; 5714 5715 static int 5716 ata_serialize(device_t dev, int flags) 5717 { 5718 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5719 struct ata_channel *ch = device_get_softc(dev); 5720 struct ata_serialize *serial; 5721 static int inited = 0; 5722 int res; 5723 5724 if (!inited) { 5725 serial = kmalloc(sizeof(struct ata_serialize), 5726 M_TEMP, M_INTWAIT | M_ZERO); 5727 spin_init(&serial->locked_mtx); 5728 serial->locked_ch = -1; 5729 serial->restart_ch = -1; 5730 device_set_ivars(ctlr->dev, serial); 5731 inited = 1; 5732 } 5733 else 5734 serial = device_get_ivars(ctlr->dev); 5735 5736 spin_lock_wr(&serial->locked_mtx); 5737 switch (flags) { 5738 case ATA_LF_LOCK: 5739 if (serial->locked_ch == -1) 5740 serial->locked_ch = ch->unit; 5741 if (serial->locked_ch != ch->unit) 5742 serial->restart_ch = ch->unit; 5743 break; 5744 5745 case ATA_LF_UNLOCK: 5746 if (serial->locked_ch == ch->unit) { 5747 serial->locked_ch = -1; 5748 if (serial->restart_ch != -1) { 5749 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) { 5750 serial->restart_ch = -1; 5751 spin_unlock_wr(&serial->locked_mtx); 5752 ata_start(ch->dev); 5753 return -1; 5754 } 5755 } 5756 } 5757 break; 5758 5759 case ATA_LF_WHICH: 5760 break; 5761 } 5762 res = serial->locked_ch; 5763 spin_unlock_wr(&serial->locked_mtx); 5764 return res; 5765 } 5766 5767 static void 5768 ata_print_cable(device_t dev, u_int8_t *who) 5769 { 5770 device_printf(dev, 5771 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who); 5772 } 5773 5774 static int 5775 ata_atapi(device_t dev) 5776 { 5777 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5778 struct ata_device *atadev = device_get_softc(dev); 5779 5780 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || 5781 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE)); 5782 } 5783 5784 static int 5785 ata_check_80pin(device_t dev, int mode) 5786 { 5787 struct ata_device *atadev = device_get_softc(dev); 5788 5789 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) { 5790 ata_print_cable(dev, "device"); 5791 mode = ATA_UDMA2; 5792 } 5793 return mode; 5794 } 5795 5796 static int 5797 ata_mode2idx(int mode) 5798 { 5799 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) 5800 return (mode & ATA_MODE_MASK) + 8; 5801 if ((mode & ATA_DMA_MASK) == ATA_WDMA0) 5802 return (mode & ATA_MODE_MASK) + 5; 5803 return (mode & ATA_MODE_MASK) - ATA_PIO0; 5804 } 5805