1 /*- 2 * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.196 2007/04/08 19:18:51 sos Exp $ 27 */ 28 29 #include "opt_ata.h" 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/bus_dma.h> 34 #include <sys/bus_resource.h> 35 #include <sys/callout.h> 36 #include <sys/endian.h> 37 #include <sys/libkern.h> 38 #include <sys/lock.h> /* for {get,rel}_mplock() */ 39 #include <sys/malloc.h> 40 #include <sys/nata.h> 41 #include <sys/queue.h> 42 #include <sys/rman.h> 43 #include <sys/spinlock.h> 44 #include <sys/systm.h> 45 #include <sys/taskqueue.h> 46 #include <sys/machintr.h> 47 48 #include <sys/spinlock2.h> 49 #include <sys/mplock2.h> 50 51 #include <machine/bus_dma.h> 52 53 #include <bus/pci/pcireg.h> 54 #include <bus/pci/pcivar.h> 55 56 #include "ata-all.h" 57 #include "ata-pci.h" 58 #include "ata_if.h" 59 60 /* local prototypes */ 61 /* ata-chipset.c */ 62 static int ata_generic_chipinit(device_t dev); 63 static void ata_generic_intr(void *data); 64 static void ata_generic_setmode(device_t dev, int mode); 65 static void ata_sata_phy_check_events(device_t dev); 66 static void ata_sata_phy_event(void *context, int dummy); 67 static int ata_sata_phy_reset(device_t dev); 68 static int ata_sata_connect(struct ata_channel *ch); 69 static void ata_sata_setmode(device_t dev, int mode); 70 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); 71 static int ata_ahci_chipinit(device_t dev); 72 static int ata_ahci_allocate(device_t dev); 73 static int ata_ahci_status(device_t dev); 74 static int ata_ahci_begin_transaction(struct ata_request *request); 75 static int ata_ahci_end_transaction(struct ata_request *request); 76 static void ata_ahci_reset(device_t dev); 77 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 78 static void ata_ahci_dmainit(device_t dev); 79 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request); 80 static int ata_acard_chipinit(device_t dev); 81 static int ata_acard_allocate(device_t dev); 82 static int ata_acard_status(device_t dev); 83 static void ata_acard_850_setmode(device_t dev, int mode); 84 static void ata_acard_86X_setmode(device_t dev, int mode); 85 static int ata_ali_chipinit(device_t dev); 86 static int ata_ali_allocate(device_t dev); 87 static int ata_ali_sata_allocate(device_t dev); 88 static void ata_ali_reset(device_t dev); 89 static void ata_ali_setmode(device_t dev, int mode); 90 static int ata_amd_chipinit(device_t dev); 91 static int ata_ati_chipinit(device_t dev); 92 static void ata_ati_setmode(device_t dev, int mode); 93 static int ata_cyrix_chipinit(device_t dev); 94 static void ata_cyrix_setmode(device_t dev, int mode); 95 static int ata_cypress_chipinit(device_t dev); 96 static void ata_cypress_setmode(device_t dev, int mode); 97 static int ata_highpoint_chipinit(device_t dev); 98 static int ata_highpoint_allocate(device_t dev); 99 static void ata_highpoint_setmode(device_t dev, int mode); 100 static int ata_highpoint_check_80pin(device_t dev, int mode); 101 static int ata_intel_chipinit(device_t dev); 102 static int ata_intel_allocate(device_t dev); 103 static void ata_intel_reset(device_t dev); 104 static void ata_intel_old_setmode(device_t dev, int mode); 105 static void ata_intel_new_setmode(device_t dev, int mode); 106 static void ata_intel_sata_setmode(device_t dev, int mode); 107 static int ata_intel_31244_allocate(device_t dev); 108 static int ata_intel_31244_status(device_t dev); 109 static int ata_intel_31244_command(struct ata_request *request); 110 static void ata_intel_31244_reset(device_t dev); 111 static int ata_ite_chipinit(device_t dev); 112 static void ata_ite_setmode(device_t dev, int mode); 113 static int ata_jmicron_chipinit(device_t dev); 114 static int ata_jmicron_allocate(device_t dev); 115 static void ata_jmicron_reset(device_t dev); 116 static void ata_jmicron_dmainit(device_t dev); 117 static void ata_jmicron_setmode(device_t dev, int mode); 118 static int ata_marvell_pata_chipinit(device_t dev); 119 static int ata_marvell_pata_allocate(device_t dev); 120 static void ata_marvell_pata_setmode(device_t dev, int mode); 121 static int ata_marvell_edma_chipinit(device_t dev); 122 static int ata_marvell_edma_allocate(device_t dev); 123 static int ata_marvell_edma_status(device_t dev); 124 static int ata_marvell_edma_begin_transaction(struct ata_request *request); 125 static int ata_marvell_edma_end_transaction(struct ata_request *request); 126 static void ata_marvell_edma_reset(device_t dev); 127 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 128 static void ata_marvell_edma_dmainit(device_t dev); 129 static int ata_national_chipinit(device_t dev); 130 static void ata_national_setmode(device_t dev, int mode); 131 static int ata_netcell_chipinit(device_t dev); 132 static int ata_netcell_allocate(device_t dev); 133 static int ata_nvidia_chipinit(device_t dev); 134 static int ata_nvidia_allocate(device_t dev); 135 static int ata_nvidia_status(device_t dev); 136 static void ata_nvidia_reset(device_t dev); 137 static int ata_promise_chipinit(device_t dev); 138 static int ata_promise_allocate(device_t dev); 139 static int ata_promise_status(device_t dev); 140 static int ata_promise_dmastart(device_t dev); 141 static int ata_promise_dmastop(device_t dev); 142 static void ata_promise_dmareset(device_t dev); 143 static void ata_promise_dmainit(device_t dev); 144 static void ata_promise_setmode(device_t dev, int mode); 145 static int ata_promise_tx2_allocate(device_t dev); 146 static int ata_promise_tx2_status(device_t dev); 147 static int ata_promise_mio_allocate(device_t dev); 148 static void ata_promise_mio_intr(void *data); 149 static int ata_promise_mio_status(device_t dev); 150 static int ata_promise_mio_command(struct ata_request *request); 151 static void ata_promise_mio_reset(device_t dev); 152 static void ata_promise_mio_dmainit(device_t dev); 153 static void ata_promise_mio_setmode(device_t dev, int mode); 154 static void ata_promise_sx4_intr(void *data); 155 static int ata_promise_sx4_command(struct ata_request *request); 156 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 157 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 158 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 159 static int ata_serverworks_chipinit(device_t dev); 160 static int ata_serverworks_allocate(device_t dev); 161 static void ata_serverworks_setmode(device_t dev, int mode); 162 static int ata_sii_chipinit(device_t dev); 163 static int ata_cmd_allocate(device_t dev); 164 static int ata_cmd_status(device_t dev); 165 static void ata_cmd_setmode(device_t dev, int mode); 166 static int ata_sii_allocate(device_t dev); 167 static int ata_sii_status(device_t dev); 168 static void ata_sii_reset(device_t dev); 169 static void ata_sii_setmode(device_t dev, int mode); 170 static int ata_siiprb_allocate(device_t dev); 171 static int ata_siiprb_status(device_t dev); 172 static int ata_siiprb_begin_transaction(struct ata_request *request); 173 static int ata_siiprb_end_transaction(struct ata_request *request); 174 static void ata_siiprb_reset(device_t dev); 175 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 176 static void ata_siiprb_dmainit(device_t dev); 177 static int ata_sis_chipinit(device_t dev); 178 static int ata_sis_allocate(device_t dev); 179 static void ata_sis_reset(device_t dev); 180 static void ata_sis_setmode(device_t dev, int mode); 181 static int ata_via_chipinit(device_t dev); 182 static int ata_via_allocate(device_t dev); 183 static void ata_via_reset(device_t dev); 184 static void ata_via_setmode(device_t dev, int mode); 185 static void ata_via_southbridge_fixup(device_t dev); 186 static void ata_via_family_setmode(device_t dev, int mode); 187 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index); 188 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot); 189 static int ata_setup_interrupt(device_t dev); 190 static void ata_teardown_interrupt(device_t dev); 191 static int ata_serialize(device_t dev, int flags); 192 static void ata_print_cable(device_t dev, u_int8_t *who); 193 static int ata_atapi(device_t dev); 194 static int ata_check_80pin(device_t dev, int mode); 195 static int ata_mode2idx(int mode); 196 197 198 /* 199 * generic ATA support functions 200 */ 201 int 202 ata_generic_ident(device_t dev) 203 { 204 struct ata_pci_controller *ctlr = device_get_softc(dev); 205 char buffer[64]; 206 207 ksnprintf(buffer, sizeof(buffer), 208 "%s ATA controller", ata_pcivendor2str(dev)); 209 device_set_desc_copy(dev, buffer); 210 ctlr->chipinit = ata_generic_chipinit; 211 return 0; 212 } 213 214 static int 215 ata_generic_chipinit(device_t dev) 216 { 217 struct ata_pci_controller *ctlr = device_get_softc(dev); 218 219 if (ata_setup_interrupt(dev)) 220 return ENXIO; 221 ctlr->setmode = ata_generic_setmode; 222 return 0; 223 } 224 225 static void 226 ata_generic_intr(void *data) 227 { 228 struct ata_pci_controller *ctlr = data; 229 struct ata_channel *ch; 230 int unit; 231 232 for (unit = 0; unit < ctlr->channels; unit++) { 233 if ((ch = ctlr->interrupt[unit].argument)) 234 ctlr->interrupt[unit].function(ch); 235 } 236 } 237 238 static void 239 ata_generic_setmode(device_t dev, int mode) 240 { 241 struct ata_device *atadev = device_get_softc(dev); 242 243 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 244 mode = ata_check_80pin(dev, mode); 245 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 246 atadev->mode = mode; 247 } 248 249 250 /* 251 * SATA support functions 252 */ 253 static void 254 ata_sata_phy_check_events(device_t dev) 255 { 256 struct ata_channel *ch = device_get_softc(dev); 257 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR); 258 259 /* clear error bits/interrupt */ 260 ATA_IDX_OUTL(ch, ATA_SERROR, error); 261 262 /* do we have any events flagged ? */ 263 if (error) { 264 struct ata_connect_task *tp; 265 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS); 266 267 /* if we have a connection event deal with it */ 268 if ((error & ATA_SE_PHY_CHANGED) && 269 (tp = (struct ata_connect_task *) 270 kmalloc(sizeof(struct ata_connect_task), 271 M_ATA, M_INTWAIT | M_ZERO))) { 272 273 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) || 274 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) { 275 if (bootverbose) 276 device_printf(ch->dev, "CONNECT requested\n"); 277 tp->action = ATA_C_ATTACH; 278 } 279 else { 280 if (bootverbose) 281 device_printf(ch->dev, "DISCONNECT requested\n"); 282 tp->action = ATA_C_DETACH; 283 } 284 tp->dev = ch->dev; 285 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 286 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 287 } 288 } 289 } 290 291 static void 292 ata_sata_phy_event(void *context, int dummy) 293 { 294 struct ata_connect_task *tp = (struct ata_connect_task *)context; 295 struct ata_channel *ch = device_get_softc(tp->dev); 296 device_t *children; 297 int nchildren, i; 298 299 get_mplock(); 300 if (tp->action == ATA_C_ATTACH) { 301 if (bootverbose) 302 device_printf(tp->dev, "CONNECTED\n"); 303 ATA_RESET(tp->dev); 304 ata_identify(tp->dev); 305 } 306 if (tp->action == ATA_C_DETACH) { 307 if (!device_get_children(tp->dev, &children, &nchildren)) { 308 for (i = 0; i < nchildren; i++) 309 if (children[i]) 310 device_delete_child(tp->dev, children[i]); 311 kfree(children, M_TEMP); 312 } 313 spin_lock(&ch->state_mtx); 314 ch->state = ATA_IDLE; 315 spin_unlock(&ch->state_mtx); 316 if (bootverbose) 317 device_printf(tp->dev, "DISCONNECTED\n"); 318 } 319 rel_mplock(); 320 kfree(tp, M_ATA); 321 } 322 323 static int 324 ata_sata_phy_reset(device_t dev) 325 { 326 struct ata_channel *ch = device_get_softc(dev); 327 int loop, retry; 328 329 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 330 return ata_sata_connect(ch); 331 332 for (retry = 0; retry < 10; retry++) { 333 for (loop = 0; loop < 10; loop++) { 334 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET); 335 ata_udelay(100); 336 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & 337 ATA_SC_DET_MASK) == ATA_SC_DET_RESET) 338 break; 339 } 340 ata_udelay(5000); 341 for (loop = 0; loop < 10; loop++) { 342 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE | 343 ATA_SC_IPM_DIS_PARTIAL | 344 ATA_SC_IPM_DIS_SLUMBER); 345 ata_udelay(100); 346 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0) 347 return ata_sata_connect(ch); 348 } 349 } 350 return 0; 351 } 352 353 static int 354 ata_sata_connect(struct ata_channel *ch) 355 { 356 u_int32_t status; 357 int timeout; 358 359 /* wait up to 1 second for "connect well" */ 360 for (timeout = 0; timeout < 100 ; timeout++) { 361 status = ATA_IDX_INL(ch, ATA_SSTATUS); 362 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 || 363 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2) 364 break; 365 ata_udelay(10000); 366 } 367 if (timeout >= 100) { 368 if (bootverbose) 369 device_printf(ch->dev, "SATA connect status=%08x\n", status); 370 return 0; 371 } 372 373 if (bootverbose) 374 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10); 375 376 /* clear SATA error register */ 377 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 378 379 return 1; 380 } 381 382 static void 383 ata_sata_setmode(device_t dev, int mode) 384 { 385 struct ata_device *atadev = device_get_softc(dev); 386 387 /* 388 * if we detect that the device isn't a real SATA device we limit 389 * the transfer mode to UDMA5/ATA100. 390 * this works around the problems some devices has with the 391 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133. 392 */ 393 if (atadev->param.satacapabilities != 0x0000 && 394 atadev->param.satacapabilities != 0xffff) { 395 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 396 397 /* on some drives we need to set the transfer mode */ 398 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 399 ata_limit_mode(dev, mode, ATA_UDMA6)); 400 401 /* query SATA STATUS for the speed */ 402 if (ch->r_io[ATA_SSTATUS].res && 403 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) == 404 ATA_SS_CONWELL_GEN2)) 405 atadev->mode = ATA_SA300; 406 else 407 atadev->mode = ATA_SA150; 408 } 409 else { 410 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 411 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 412 atadev->mode = mode; 413 } 414 } 415 416 static int 417 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis) 418 { 419 struct ata_device *atadev = device_get_softc(request->dev); 420 421 if (request->flags & ATA_R_ATAPI) { 422 fis[0] = 0x27; /* host to device */ 423 fis[1] = 0x80; /* command FIS (note PM goes here) */ 424 fis[2] = ATA_PACKET_CMD; 425 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) 426 fis[3] = ATA_F_DMA; 427 else { 428 fis[5] = request->transfersize; 429 fis[6] = request->transfersize >> 8; 430 } 431 fis[7] = ATA_D_LBA | atadev->unit; 432 fis[15] = ATA_A_4BIT; 433 return 20; 434 } 435 else { 436 ata_modify_if_48bit(request); 437 fis[0] = 0x27; /* host to device */ 438 fis[1] = 0x80; /* command FIS (note PM goes here) */ 439 fis[2] = request->u.ata.command; 440 fis[3] = request->u.ata.feature; 441 fis[4] = request->u.ata.lba; 442 fis[5] = request->u.ata.lba >> 8; 443 fis[6] = request->u.ata.lba >> 16; 444 fis[7] = ATA_D_LBA | atadev->unit; 445 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 446 fis[7] |= (request->u.ata.lba >> 24 & 0x0f); 447 fis[8] = request->u.ata.lba >> 24; 448 fis[9] = request->u.ata.lba >> 32; 449 fis[10] = request->u.ata.lba >> 40; 450 fis[11] = request->u.ata.feature >> 8; 451 fis[12] = request->u.ata.count; 452 fis[13] = request->u.ata.count >> 8; 453 fis[15] = ATA_A_4BIT; 454 return 20; 455 } 456 return 0; 457 } 458 459 /* 460 * AHCI v1.x compliant SATA chipset support functions 461 */ 462 int 463 ata_ahci_ident(device_t dev) 464 { 465 struct ata_pci_controller *ctlr = device_get_softc(dev); 466 static struct ata_chip_id id = {0, 0, 0, 0x00, ATA_SA300, "AHCI"}; 467 char buffer[64]; 468 469 if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0) 470 return ENXIO; 471 472 if (bootverbose) 473 ksnprintf(buffer, sizeof(buffer), "%s (ID=%08x) AHCI controller", 474 ata_pcivendor2str(dev), pci_get_devid(dev)); 475 else 476 ksnprintf(buffer, sizeof(buffer), "%s AHCI controller", 477 ata_pcivendor2str(dev)); 478 device_set_desc_copy(dev, buffer); 479 ctlr->chip = &id; 480 ctlr->chipinit = ata_ahci_chipinit; 481 return 0; 482 } 483 484 485 /* 486 * AHCI v1.x compliant SATA chipset support functions 487 */ 488 int 489 ata_ahci_chipinit(device_t dev) 490 { 491 struct ata_pci_controller *ctlr = device_get_softc(dev); 492 u_int32_t version; 493 int unit; 494 495 /* if we have a memory BAR(5) we are likely on an AHCI part */ 496 ctlr->r_type2 = SYS_RES_MEMORY; 497 ctlr->r_rid2 = PCIR_BAR(5); 498 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 499 &ctlr->r_rid2, RF_ACTIVE))) 500 return ENXIO; 501 502 /* setup interrupt delivery if not done allready by a vendor driver */ 503 if (!ctlr->r_irq) { 504 if (ata_setup_interrupt(dev)) 505 return ENXIO; 506 } 507 else 508 device_printf(dev, "AHCI called from vendor specific driver\n"); 509 510 /* enable AHCI mode */ 511 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 512 513 /* reset AHCI controller */ 514 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR); 515 DELAY(1000000); 516 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) { 517 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 518 device_printf(dev, "AHCI controller reset failure\n"); 519 return ENXIO; 520 } 521 522 /* reenable AHCI mode */ 523 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 524 525 /* get the number of HW channels */ 526 ctlr->channels = 527 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)), 528 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 529 530 /* disable interrupt sources and clear interrupts */ 531 for (unit = 0; unit < ctlr->channels; unit++) { 532 int offset = unit << 7; 533 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0); 534 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, -1); 535 } 536 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS)); 537 538 /* enable AHCI interrupts */ 539 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 540 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE); 541 542 ctlr->reset = ata_ahci_reset; 543 ctlr->dmainit = ata_ahci_dmainit; 544 ctlr->allocate = ata_ahci_allocate; 545 ctlr->setmode = ata_sata_setmode; 546 547 /* enable PCI interrupt */ 548 pci_write_config(dev, PCIR_COMMAND, 549 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 550 551 /* announce we support the HW */ 552 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS); 553 device_printf(dev, 554 "AHCI Version %x%x.%x%x controller with %d ports detected\n", 555 (version >> 24) & 0xff, (version >> 16) & 0xff, 556 (version >> 8) & 0xff, version & 0xff, 557 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 558 return 0; 559 } 560 561 static int 562 ata_ahci_allocate(device_t dev) 563 { 564 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 565 struct ata_channel *ch = device_get_softc(dev); 566 u_int64_t work; 567 int offset = ch->unit << 7; 568 569 /* set the SATA resources */ 570 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 571 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset; 572 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 573 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset; 574 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 575 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset; 576 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 577 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset; 578 579 ch->hw.status = ata_ahci_status; 580 ch->hw.begin_transaction = ata_ahci_begin_transaction; 581 ch->hw.end_transaction = ata_ahci_end_transaction; 582 ch->hw.command = NULL; /* not used here */ 583 584 /* setup work areas */ 585 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET; 586 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff); 587 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32); 588 589 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET; 590 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff); 591 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32); 592 593 /* enable wanted port interrupts */ 594 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 595 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF | 596 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF | 597 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP | 598 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS | 599 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR)); 600 601 /* start operations on this channel */ 602 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 603 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 604 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 605 return 0; 606 } 607 608 static int 609 ata_ahci_status(device_t dev) 610 { 611 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 612 struct ata_channel *ch = device_get_softc(dev); 613 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS); 614 int offset = ch->unit << 7; 615 int tag = 0; 616 617 if (action & (1 << ch->unit)) { 618 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset); 619 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset); 620 621 /* clear interrupt(s) */ 622 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit)); 623 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus); 624 625 /* do we have any PHY events ? */ 626 /* XXX SOS check istatus phy bits */ 627 ata_sata_phy_check_events(dev); 628 629 /* do we have a potentially hanging engine to take care of? */ 630 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) { 631 632 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 633 int timeout = 0; 634 635 /* kill off all activity on this channel */ 636 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 637 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 638 639 /* XXX SOS this is not entirely wrong */ 640 do { 641 DELAY(1000); 642 if (timeout++ > 500) { 643 device_printf(dev, "stopping AHCI engine failed\n"); 644 break; 645 } 646 } while (ATA_INL(ctlr->r_res2, 647 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 648 649 /* start operations on this channel */ 650 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 651 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 652 653 return 1; 654 } 655 else 656 return (!(cstatus & (1 << tag))); 657 } 658 return 0; 659 } 660 661 /* must be called with ATA channel locked and state_mtx held */ 662 static int 663 ata_ahci_begin_transaction(struct ata_request *request) 664 { 665 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 666 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 667 struct ata_ahci_cmd_tab *ctp; 668 struct ata_ahci_cmd_list *clp; 669 int offset = ch->unit << 7; 670 int tag = 0, entries = 0; 671 int fis_size; 672 673 /* get a piece of the workspace for this request */ 674 ctp = (struct ata_ahci_cmd_tab *) 675 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag)); 676 677 /* setup the FIS for this request */ 678 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) { 679 device_printf(request->dev, "setting up SATA FIS failed\n"); 680 request->result = EIO; 681 return ATA_OP_FINISHED; 682 } 683 684 /* if request moves data setup and load SG list */ 685 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 686 if (ch->dma->load(ch->dev, request->data, request->bytecount, 687 request->flags & ATA_R_READ, 688 ctp->prd_tab, &entries)) { 689 device_printf(request->dev, "setting up DMA failed\n"); 690 request->result = EIO; 691 return ATA_OP_FINISHED; 692 } 693 } 694 695 /* setup the command list entry */ 696 clp = (struct ata_ahci_cmd_list *) 697 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 698 699 clp->prd_length = entries; 700 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) | 701 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) | 702 (fis_size / sizeof(u_int32_t)); 703 clp->bytecount = 0; 704 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET + 705 (ATA_AHCI_CT_SIZE * tag)); 706 707 /* clear eventual ACTIVE bit */ 708 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag)); 709 710 /* set command type bit */ 711 if (request->flags & ATA_R_ATAPI) 712 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 713 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) | 714 ATA_AHCI_P_CMD_ATAPI); 715 else 716 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 717 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & 718 ~ATA_AHCI_P_CMD_ATAPI); 719 720 /* issue command to controller */ 721 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag)); 722 723 if (!(request->flags & ATA_R_ATAPI)) { 724 /* device reset doesn't interrupt */ 725 if (request->u.ata.command == ATA_DEVICE_RESET) { 726 u_int32_t tf_data; 727 int timeout = 1000000; 728 729 do { 730 DELAY(10); 731 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7)); 732 } while ((tf_data & ATA_S_BUSY) && timeout--); 733 if (bootverbose) 734 device_printf(ch->dev, "device_reset timeout=%dus\n", 735 (1000000-timeout)*10); 736 request->status = tf_data; 737 if (request->status & ATA_S_ERROR) 738 request->error = tf_data >> 8; 739 return ATA_OP_FINISHED; 740 } 741 } 742 743 /* start the timeout */ 744 callout_reset(&request->callout, request->timeout * hz, 745 (timeout_t*)ata_timeout, request); 746 return ATA_OP_CONTINUES; 747 } 748 749 /* must be called with ATA channel locked and state_mtx held */ 750 static int 751 ata_ahci_end_transaction(struct ata_request *request) 752 { 753 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 754 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 755 struct ata_ahci_cmd_list *clp; 756 u_int32_t tf_data; 757 int offset = ch->unit << 7; 758 int tag = 0; 759 760 /* kill the timeout */ 761 callout_stop(&request->callout); 762 763 /* get status */ 764 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset); 765 request->status = tf_data; 766 767 /* if error status get details */ 768 if (request->status & ATA_S_ERROR) 769 request->error = tf_data >> 8; 770 771 /* record how much data we actually moved */ 772 clp = (struct ata_ahci_cmd_list *) 773 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 774 request->donecount = clp->bytecount; 775 776 /* release SG list etc */ 777 ch->dma->unload(ch->dev); 778 779 return ATA_OP_FINISHED; 780 } 781 782 static void 783 ata_ahci_reset(device_t dev) 784 { 785 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 786 struct ata_channel *ch = device_get_softc(dev); 787 u_int32_t cmd, signature; 788 int offset = ch->unit << 7; 789 int timeout; 790 791 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) { 792 device_printf(dev, "port not implemented\n"); 793 return; 794 } 795 ch->devices = 0; 796 797 /* kill off all activity on this channel */ 798 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 799 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 800 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 801 802 /* XXX SOS this is not entirely wrong */ 803 timeout = 0; 804 do { 805 DELAY(1000); 806 if (timeout++ > 500) { 807 device_printf(dev, "stopping AHCI engine failed\n"); 808 break; 809 } 810 } 811 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 812 813 /* issue Command List Override if supported */ 814 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) { 815 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 816 cmd |= ATA_AHCI_P_CMD_CLO; 817 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd); 818 timeout = 0; 819 do { 820 DELAY(1000); 821 if (timeout++ > 500) { 822 device_printf(dev, "executing CLO failed\n"); 823 break; 824 } 825 } 826 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO); 827 } 828 829 /* reset PHY and decide what is present */ 830 if (ata_sata_phy_reset(dev)) { 831 832 /* clear any interrupts pending on this channel */ 833 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, 834 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset)); 835 836 /* clear SATA error register */ 837 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 838 839 /* start operations on this channel */ 840 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 841 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 842 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 843 844 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset); 845 switch (signature) { 846 case 0x00000101: 847 ch->devices = ATA_ATA_MASTER; 848 break; 849 case 0x96690101: 850 ch->devices = ATA_PORTMULTIPLIER; 851 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 852 ch->devices = 0; 853 break; 854 case 0xeb140101: 855 ch->devices = ATA_ATAPI_MASTER; 856 break; 857 default: /* SOS XXX */ 858 if (bootverbose) 859 device_printf(ch->dev, "No signature, assuming disk device\n"); 860 ch->devices = ATA_ATA_MASTER; 861 } 862 } 863 if (bootverbose) 864 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices, 865 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 866 } 867 868 static void 869 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 870 { 871 struct ata_dmasetprd_args *args = xsc; 872 struct ata_ahci_dma_prd *prd = args->dmatab; 873 int i; 874 875 if (!(args->error = error)) { 876 for (i = 0; i < nsegs; i++) { 877 prd[i].dba = htole64(segs[i].ds_addr); 878 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK); 879 } 880 } 881 args->nsegs = nsegs; 882 } 883 884 static void 885 ata_ahci_dmainit(device_t dev) 886 { 887 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 888 struct ata_channel *ch = device_get_softc(dev); 889 890 ata_dmainit(dev); 891 if (ch->dma) { 892 /* note start and stop are not used here */ 893 ch->dma->setprd = ata_ahci_dmasetprd; 894 ch->dma->max_iosize = 8192 * DEV_BSIZE; 895 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT) 896 ch->dma->max_address = BUS_SPACE_MAXADDR; 897 } 898 } 899 900 static int 901 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request) 902 { 903 bzero(ctp->cfis, 64); 904 if (request->flags & ATA_R_ATAPI) { 905 bzero(ctp->acmd, 32); 906 bcopy(request->u.atapi.ccb, ctp->acmd, 16); 907 } 908 return ata_request2fis_h2d(request, &ctp->cfis[0]); 909 } 910 911 /* 912 * Acard chipset support functions 913 */ 914 int 915 ata_acard_ident(device_t dev) 916 { 917 struct ata_pci_controller *ctlr = device_get_softc(dev); 918 struct ata_chip_id *idx; 919 static struct ata_chip_id ids[] = 920 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" }, 921 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" }, 922 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" }, 923 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" }, 924 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" }, 925 { 0, 0, 0, 0, 0, 0}}; 926 char buffer[64]; 927 928 if (!(idx = ata_match_chip(dev, ids))) 929 return ENXIO; 930 931 ksprintf(buffer, "Acard %s %s controller", 932 idx->text, ata_mode2str(idx->max_dma)); 933 device_set_desc_copy(dev, buffer); 934 ctlr->chip = idx; 935 ctlr->chipinit = ata_acard_chipinit; 936 return 0; 937 } 938 939 static int 940 ata_acard_chipinit(device_t dev) 941 { 942 struct ata_pci_controller *ctlr = device_get_softc(dev); 943 944 if (ata_setup_interrupt(dev)) 945 return ENXIO; 946 947 ctlr->allocate = ata_acard_allocate; 948 if (ctlr->chip->cfg1 == ATPOLD) { 949 ctlr->setmode = ata_acard_850_setmode; 950 ctlr->locking = ata_serialize; 951 } 952 else 953 ctlr->setmode = ata_acard_86X_setmode; 954 return 0; 955 } 956 957 static int 958 ata_acard_allocate(device_t dev) 959 { 960 struct ata_channel *ch = device_get_softc(dev); 961 962 /* setup the usual register normal pci style */ 963 if (ata_pci_allocate(dev)) 964 return ENXIO; 965 966 ch->hw.status = ata_acard_status; 967 return 0; 968 } 969 970 static int 971 ata_acard_status(device_t dev) 972 { 973 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 974 struct ata_channel *ch = device_get_softc(dev); 975 976 if (ctlr->chip->cfg1 == ATPOLD && 977 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit) 978 return 0; 979 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) { 980 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 981 982 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != 983 ATA_BMSTAT_INTERRUPT) 984 return 0; 985 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR); 986 DELAY(1); 987 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 988 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 989 DELAY(1); 990 } 991 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 992 DELAY(100); 993 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 994 return 0; 995 } 996 return 1; 997 } 998 999 static void 1000 ata_acard_850_setmode(device_t dev, int mode) 1001 { 1002 device_t gparent = GRANDPARENT(dev); 1003 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1004 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1005 struct ata_device *atadev = device_get_softc(dev); 1006 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1007 int error; 1008 1009 mode = ata_limit_mode(dev, mode, 1010 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 1011 1012 /* XXX SOS missing WDMA0+1 + PIO modes */ 1013 if (mode >= ATA_WDMA2) { 1014 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1015 if (bootverbose) 1016 device_printf(dev, "%ssetting %s on %s chip\n", 1017 (error) ? "FAILURE " : "", 1018 ata_mode2str(mode), ctlr->chip->text); 1019 if (!error) { 1020 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1); 1021 1022 reg54 &= ~(0x03 << (devno << 1)); 1023 if (mode >= ATA_UDMA0) 1024 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1)); 1025 pci_write_config(gparent, 0x54, reg54, 1); 1026 pci_write_config(gparent, 0x4a, 0xa6, 1); 1027 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2); 1028 atadev->mode = mode; 1029 return; 1030 } 1031 } 1032 /* we could set PIO mode timings, but we assume the BIOS did that */ 1033 } 1034 1035 static void 1036 ata_acard_86X_setmode(device_t dev, int mode) 1037 { 1038 device_t gparent = GRANDPARENT(dev); 1039 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1040 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1041 struct ata_device *atadev = device_get_softc(dev); 1042 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1043 int error; 1044 1045 1046 mode = ata_limit_mode(dev, mode, 1047 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 1048 1049 mode = ata_check_80pin(dev, mode); 1050 1051 /* XXX SOS missing WDMA0+1 + PIO modes */ 1052 if (mode >= ATA_WDMA2) { 1053 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1054 if (bootverbose) 1055 device_printf(dev, "%ssetting %s on %s chip\n", 1056 (error) ? "FAILURE " : "", 1057 ata_mode2str(mode), ctlr->chip->text); 1058 if (!error) { 1059 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2); 1060 1061 reg44 &= ~(0x000f << (devno << 2)); 1062 if (mode >= ATA_UDMA0) 1063 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2)); 1064 pci_write_config(gparent, 0x44, reg44, 2); 1065 pci_write_config(gparent, 0x4a, 0xa6, 1); 1066 pci_write_config(gparent, 0x40 + devno, 0x31, 1); 1067 atadev->mode = mode; 1068 return; 1069 } 1070 } 1071 /* we could set PIO mode timings, but we assume the BIOS did that */ 1072 } 1073 1074 1075 /* 1076 * Acer Labs Inc (ALI) chipset support functions 1077 */ 1078 int 1079 ata_ali_ident(device_t dev) 1080 { 1081 struct ata_pci_controller *ctlr = device_get_softc(dev); 1082 struct ata_chip_id *idx; 1083 static struct ata_chip_id ids[] = 1084 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" }, 1085 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" }, 1086 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" }, 1087 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" }, 1088 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" }, 1089 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" }, 1090 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" }, 1091 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" }, 1092 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" }, 1093 { 0, 0, 0, 0, 0, 0}}; 1094 char buffer[64]; 1095 1096 if (!(idx = ata_match_chip(dev, ids))) 1097 return ENXIO; 1098 1099 ksprintf(buffer, "AcerLabs %s %s controller", 1100 idx->text, ata_mode2str(idx->max_dma)); 1101 device_set_desc_copy(dev, buffer); 1102 ctlr->chip = idx; 1103 ctlr->chipinit = ata_ali_chipinit; 1104 return 0; 1105 } 1106 1107 static int 1108 ata_ali_chipinit(device_t dev) 1109 { 1110 struct ata_pci_controller *ctlr = device_get_softc(dev); 1111 1112 if (ata_setup_interrupt(dev)) 1113 return ENXIO; 1114 1115 switch (ctlr->chip->cfg2) { 1116 case ALISATA: 1117 ctlr->channels = ctlr->chip->cfg1; 1118 ctlr->allocate = ata_ali_sata_allocate; 1119 ctlr->setmode = ata_sata_setmode; 1120 1121 /* AHCI mode is correctly supported only on the ALi 5288. */ 1122 if ((ctlr->chip->chipid == ATA_ALI_5288) && 1123 (ata_ahci_chipinit(dev) != ENXIO)) 1124 return 0; 1125 1126 /* enable PCI interrupt */ 1127 pci_write_config(dev, PCIR_COMMAND, 1128 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1129 break; 1130 1131 case ALINEW: 1132 /* use device interrupt as byte count end */ 1133 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1); 1134 1135 /* enable cable detection and UDMA support on newer chips */ 1136 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1); 1137 1138 /* enable ATAPI UDMA mode */ 1139 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1); 1140 1141 /* only chips with revision > 0xc4 can do 48bit DMA */ 1142 if (ctlr->chip->chiprev <= 0xc4) 1143 device_printf(dev, 1144 "using PIO transfers above 137GB as workaround for " 1145 "48bit DMA access bug, expect reduced performance\n"); 1146 ctlr->allocate = ata_ali_allocate; 1147 ctlr->reset = ata_ali_reset; 1148 ctlr->setmode = ata_ali_setmode; 1149 break; 1150 1151 case ALIOLD: 1152 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */ 1153 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1); 1154 ctlr->setmode = ata_ali_setmode; 1155 break; 1156 } 1157 return 0; 1158 } 1159 1160 static int 1161 ata_ali_allocate(device_t dev) 1162 { 1163 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1164 struct ata_channel *ch = device_get_softc(dev); 1165 1166 /* setup the usual register normal pci style */ 1167 if (ata_pci_allocate(dev)) 1168 return ENXIO; 1169 1170 /* older chips can't do 48bit DMA transfers */ 1171 if (ctlr->chip->chiprev <= 0xc4) 1172 ch->flags |= ATA_NO_48BIT_DMA; 1173 1174 return 0; 1175 } 1176 1177 static int 1178 ata_ali_sata_allocate(device_t dev) 1179 { 1180 device_t parent = device_get_parent(dev); 1181 struct ata_pci_controller *ctlr = device_get_softc(parent); 1182 struct ata_channel *ch = device_get_softc(dev); 1183 struct resource *io = NULL, *ctlio = NULL; 1184 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 1185 int i, rid; 1186 1187 rid = PCIR_BAR(0) + (unit01 ? 8 : 0); 1188 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1189 if (!io) 1190 return ENXIO; 1191 1192 rid = PCIR_BAR(1) + (unit01 ? 8 : 0); 1193 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1194 if (!ctlio) { 1195 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io); 1196 return ENXIO; 1197 } 1198 1199 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 1200 ch->r_io[i].res = io; 1201 ch->r_io[i].offset = i + (unit10 ? 8 : 0); 1202 } 1203 ch->r_io[ATA_CONTROL].res = ctlio; 1204 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0); 1205 ch->r_io[ATA_IDX_ADDR].res = io; 1206 ata_default_registers(dev); 1207 if (ctlr->r_res1) { 1208 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 1209 ch->r_io[i].res = ctlr->r_res1; 1210 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 1211 } 1212 } 1213 ch->flags |= ATA_NO_SLAVE; 1214 1215 /* XXX SOS PHY handling awkward in ALI chip not supported yet */ 1216 ata_pci_hw(dev); 1217 return 0; 1218 } 1219 1220 static void 1221 ata_ali_reset(device_t dev) 1222 { 1223 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1224 struct ata_channel *ch = device_get_softc(dev); 1225 device_t *children; 1226 int nchildren, i; 1227 1228 ata_generic_reset(dev); 1229 1230 /* 1231 * workaround for datacorruption bug found on at least SUN Blade-100 1232 * find the ISA function on the southbridge and disable then enable 1233 * the ATA channel tristate buffer 1234 */ 1235 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) { 1236 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) { 1237 for (i = 0; i < nchildren; i++) { 1238 if (pci_get_devid(children[i]) == ATA_ALI_1533) { 1239 pci_write_config(children[i], 0x58, 1240 pci_read_config(children[i], 0x58, 1) & 1241 ~(0x04 << ch->unit), 1); 1242 pci_write_config(children[i], 0x58, 1243 pci_read_config(children[i], 0x58, 1) | 1244 (0x04 << ch->unit), 1); 1245 break; 1246 } 1247 } 1248 kfree(children, M_TEMP); 1249 } 1250 } 1251 } 1252 1253 static void 1254 ata_ali_setmode(device_t dev, int mode) 1255 { 1256 device_t gparent = GRANDPARENT(dev); 1257 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1258 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1259 struct ata_device *atadev = device_get_softc(dev); 1260 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1261 int error; 1262 1263 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1264 1265 if (ctlr->chip->cfg2 & ALINEW) { 1266 if (mode > ATA_UDMA2 && 1267 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) { 1268 ata_print_cable(dev, "controller"); 1269 mode = ATA_UDMA2; 1270 } 1271 } 1272 else 1273 mode = ata_check_80pin(dev, mode); 1274 1275 if (ctlr->chip->cfg2 & ALIOLD) { 1276 /* doesn't support ATAPI DMA on write */ 1277 ch->flags |= ATA_ATAPI_DMA_RO; 1278 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) { 1279 /* doesn't support ATAPI DMA on two ATAPI devices */ 1280 device_printf(dev, "two atapi devices on this channel, no DMA\n"); 1281 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1282 } 1283 } 1284 1285 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1286 1287 if (bootverbose) 1288 device_printf(dev, "%ssetting %s on %s chip\n", 1289 (error) ? "FAILURE " : "", 1290 ata_mode2str(mode), ctlr->chip->text); 1291 if (!error) { 1292 if (mode >= ATA_UDMA0) { 1293 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d}; 1294 u_int32_t word54 = pci_read_config(gparent, 0x54, 4); 1295 1296 word54 &= ~(0x000f000f << (devno << 2)); 1297 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2)); 1298 pci_write_config(gparent, 0x54, word54, 4); 1299 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1300 0x00310001, 4); 1301 } 1302 else { 1303 u_int32_t piotimings[] = 1304 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001, 1305 0x00310001, 0x00440001, 0x00330001, 0x00310001}; 1306 1307 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) & 1308 ~(0x0008000f << (devno << 2)), 4); 1309 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1310 piotimings[ata_mode2idx(mode)], 4); 1311 } 1312 atadev->mode = mode; 1313 } 1314 } 1315 1316 1317 /* 1318 * American Micro Devices (AMD) chipset support functions 1319 */ 1320 int 1321 ata_amd_ident(device_t dev) 1322 { 1323 struct ata_pci_controller *ctlr = device_get_softc(dev); 1324 struct ata_chip_id *idx; 1325 static struct ata_chip_id ids[] = 1326 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" }, 1327 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" }, 1328 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" }, 1329 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" }, 1330 { 0, 0, 0, 0, 0, 0}}; 1331 char buffer[64]; 1332 1333 if (!(idx = ata_match_chip(dev, ids))) 1334 return ENXIO; 1335 1336 ksprintf(buffer, "AMD %s %s controller", 1337 idx->text, ata_mode2str(idx->max_dma)); 1338 device_set_desc_copy(dev, buffer); 1339 ctlr->chip = idx; 1340 ctlr->chipinit = ata_amd_chipinit; 1341 return 0; 1342 } 1343 1344 static int 1345 ata_amd_chipinit(device_t dev) 1346 { 1347 struct ata_pci_controller *ctlr = device_get_softc(dev); 1348 1349 if (ata_setup_interrupt(dev)) 1350 return ENXIO; 1351 1352 /* disable/set prefetch, postwrite */ 1353 if (ctlr->chip->cfg2 & AMDBUG) 1354 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1); 1355 else 1356 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); 1357 1358 ctlr->setmode = ata_via_family_setmode; 1359 return 0; 1360 } 1361 1362 1363 /* 1364 * ATI chipset support functions 1365 */ 1366 int 1367 ata_ati_ident(device_t dev) 1368 { 1369 struct ata_pci_controller *ctlr = device_get_softc(dev); 1370 struct ata_chip_id *idx; 1371 static struct ata_chip_id ids[] = 1372 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" }, 1373 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" }, 1374 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" }, 1375 { ATA_ATI_SB600, 0x00, 0, 0, ATA_UDMA6, "SB600" }, 1376 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" }, 1377 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1378 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1379 { ATA_ATI_SB600_S1, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1380 { ATA_ATI_SB600_S2, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1381 { 0, 0, 0, 0, 0, 0}}; 1382 char buffer[64]; 1383 1384 if (!(idx = ata_match_chip(dev, ids))) 1385 return ENXIO; 1386 1387 ksprintf(buffer, "ATI %s %s controller", 1388 idx->text, ata_mode2str(idx->max_dma)); 1389 device_set_desc_copy(dev, buffer); 1390 ctlr->chip = idx; 1391 1392 /* 1393 * The ATI SATA controllers are actually a SiI 3112 controller, except 1394 * for the SB600. 1395 */ 1396 if (ctlr->chip->cfg1 & SIIMEMIO) 1397 ctlr->chipinit = ata_sii_chipinit; 1398 else 1399 ctlr->chipinit = ata_ati_chipinit; 1400 return 0; 1401 } 1402 1403 static int 1404 ata_ati_chipinit(device_t dev) 1405 { 1406 struct ata_pci_controller *ctlr = device_get_softc(dev); 1407 1408 if (ata_setup_interrupt(dev)) 1409 return ENXIO; 1410 1411 /* The SB600 needs special treatment. */ 1412 if (ctlr->chip->cfg1 & ATIAHCI) { 1413 /* Check if the chip is configured as an AHCI part. */ 1414 if ((pci_get_subclass(dev) == PCIS_STORAGE_SATA) && 1415 (pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI_1_0)) { 1416 if (ata_ahci_chipinit(dev) != ENXIO) 1417 return 0; 1418 } 1419 } 1420 1421 ctlr->setmode = ata_ati_setmode; 1422 return 0; 1423 } 1424 1425 static void 1426 ata_ati_setmode(device_t dev, int mode) 1427 { 1428 device_t gparent = GRANDPARENT(dev); 1429 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1430 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1431 struct ata_device *atadev = device_get_softc(dev); 1432 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1433 int offset = (devno ^ 0x01) << 3; 1434 int error; 1435 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 1436 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 1437 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 1438 1439 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1440 1441 mode = ata_check_80pin(dev, mode); 1442 1443 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1444 1445 if (bootverbose) 1446 device_printf(dev, "%ssetting %s on %s chip\n", 1447 (error) ? "FAILURE " : "", 1448 ata_mode2str(mode), ctlr->chip->text); 1449 if (!error) { 1450 if (mode >= ATA_UDMA0) { 1451 pci_write_config(gparent, 0x56, 1452 (pci_read_config(gparent, 0x56, 2) & 1453 ~(0xf << (devno << 2))) | 1454 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 1455 pci_write_config(gparent, 0x54, 1456 pci_read_config(gparent, 0x54, 1) | 1457 (0x01 << devno), 1); 1458 pci_write_config(gparent, 0x44, 1459 (pci_read_config(gparent, 0x44, 4) & 1460 ~(0xff << offset)) | 1461 (dmatimings[2] << offset), 4); 1462 } 1463 else if (mode >= ATA_WDMA0) { 1464 pci_write_config(gparent, 0x54, 1465 pci_read_config(gparent, 0x54, 1) & 1466 ~(0x01 << devno), 1); 1467 pci_write_config(gparent, 0x44, 1468 (pci_read_config(gparent, 0x44, 4) & 1469 ~(0xff << offset)) | 1470 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 1471 } 1472 else 1473 pci_write_config(gparent, 0x54, 1474 pci_read_config(gparent, 0x54, 1) & 1475 ~(0x01 << devno), 1); 1476 1477 pci_write_config(gparent, 0x4a, 1478 (pci_read_config(gparent, 0x4a, 2) & 1479 ~(0xf << (devno << 2))) | 1480 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2); 1481 pci_write_config(gparent, 0x40, 1482 (pci_read_config(gparent, 0x40, 4) & 1483 ~(0xff << offset)) | 1484 (piotimings[ata_mode2idx(mode)] << offset), 4); 1485 atadev->mode = mode; 1486 } 1487 } 1488 1489 /* 1490 * Cyrix chipset support functions 1491 */ 1492 int 1493 ata_cyrix_ident(device_t dev) 1494 { 1495 struct ata_pci_controller *ctlr = device_get_softc(dev); 1496 1497 if (pci_get_devid(dev) == ATA_CYRIX_5530) { 1498 device_set_desc(dev, "Cyrix 5530 ATA33 controller"); 1499 ctlr->chipinit = ata_cyrix_chipinit; 1500 return 0; 1501 } 1502 return ENXIO; 1503 } 1504 1505 static int 1506 ata_cyrix_chipinit(device_t dev) 1507 { 1508 struct ata_pci_controller *ctlr = device_get_softc(dev); 1509 1510 if (ata_setup_interrupt(dev)) 1511 return ENXIO; 1512 1513 if (ctlr->r_res1) 1514 ctlr->setmode = ata_cyrix_setmode; 1515 else 1516 ctlr->setmode = ata_generic_setmode; 1517 return 0; 1518 } 1519 1520 static void 1521 ata_cyrix_setmode(device_t dev, int mode) 1522 { 1523 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1524 struct ata_device *atadev = device_get_softc(dev); 1525 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1526 u_int32_t piotiming[] = 1527 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 }; 1528 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 }; 1529 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 }; 1530 int error; 1531 1532 ch->dma->alignment = 16; 1533 ch->dma->max_iosize = 126 * DEV_BSIZE; 1534 1535 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 1536 1537 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1538 1539 if (bootverbose) 1540 device_printf(dev, "%ssetting %s on Cyrix chip\n", 1541 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1542 if (!error) { 1543 if (mode >= ATA_UDMA0) { 1544 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1545 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]); 1546 } 1547 else if (mode >= ATA_WDMA0) { 1548 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1549 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]); 1550 } 1551 else { 1552 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1553 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]); 1554 } 1555 atadev->mode = mode; 1556 } 1557 } 1558 1559 1560 /* 1561 * Cypress chipset support functions 1562 */ 1563 int 1564 ata_cypress_ident(device_t dev) 1565 { 1566 struct ata_pci_controller *ctlr = device_get_softc(dev); 1567 1568 /* 1569 * the Cypress chip is a mess, it contains two ATA functions, but 1570 * both channels are visible on the first one. 1571 * simply ignore the second function for now, as the right 1572 * solution (ignoring the second channel on the first function) 1573 * doesn't work with the crappy ATA interrupt setup on the alpha. 1574 */ 1575 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 && 1576 pci_get_function(dev) == 1 && 1577 pci_get_subclass(dev) == PCIS_STORAGE_IDE) { 1578 device_set_desc(dev, "Cypress 82C693 ATA controller"); 1579 ctlr->chipinit = ata_cypress_chipinit; 1580 return 0; 1581 } 1582 return ENXIO; 1583 } 1584 1585 static int 1586 ata_cypress_chipinit(device_t dev) 1587 { 1588 struct ata_pci_controller *ctlr = device_get_softc(dev); 1589 1590 if (ata_setup_interrupt(dev)) 1591 return ENXIO; 1592 1593 ctlr->setmode = ata_cypress_setmode; 1594 return 0; 1595 } 1596 1597 static void 1598 ata_cypress_setmode(device_t dev, int mode) 1599 { 1600 device_t gparent = GRANDPARENT(dev); 1601 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1602 struct ata_device *atadev = device_get_softc(dev); 1603 int error; 1604 1605 mode = ata_limit_mode(dev, mode, ATA_WDMA2); 1606 1607 /* XXX SOS missing WDMA0+1 + PIO modes */ 1608 if (mode == ATA_WDMA2) { 1609 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1610 if (bootverbose) 1611 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n", 1612 error ? "FAILURE " : ""); 1613 if (!error) { 1614 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2); 1615 atadev->mode = mode; 1616 return; 1617 } 1618 } 1619 /* we could set PIO mode timings, but we assume the BIOS did that */ 1620 } 1621 1622 1623 /* 1624 * HighPoint chipset support functions 1625 */ 1626 int 1627 ata_highpoint_ident(device_t dev) 1628 { 1629 struct ata_pci_controller *ctlr = device_get_softc(dev); 1630 struct ata_chip_id *idx; 1631 static struct ata_chip_id ids[] = 1632 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" }, 1633 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" }, 1634 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1635 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" }, 1636 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1637 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" }, 1638 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" }, 1639 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" }, 1640 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" }, 1641 { 0, 0, 0, 0, 0, 0}}; 1642 char buffer[64]; 1643 1644 if (!(idx = ata_match_chip(dev, ids))) 1645 return ENXIO; 1646 1647 strcpy(buffer, "HighPoint "); 1648 strcat(buffer, idx->text); 1649 if (idx->cfg1 == HPT374) { 1650 if (pci_get_function(dev) == 0) 1651 strcat(buffer, " (channel 0+1)"); 1652 if (pci_get_function(dev) == 1) 1653 strcat(buffer, " (channel 2+3)"); 1654 } 1655 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 1656 device_set_desc_copy(dev, buffer); 1657 ctlr->chip = idx; 1658 ctlr->chipinit = ata_highpoint_chipinit; 1659 return 0; 1660 } 1661 1662 static int 1663 ata_highpoint_chipinit(device_t dev) 1664 { 1665 struct ata_pci_controller *ctlr = device_get_softc(dev); 1666 1667 if (ata_setup_interrupt(dev)) 1668 return ENXIO; 1669 1670 if (ctlr->chip->cfg2 == HPTOLD) { 1671 /* disable interrupt prediction */ 1672 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 1673 } 1674 else { 1675 /* disable interrupt prediction */ 1676 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 1677 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 1678 1679 /* enable interrupts */ 1680 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 1681 1682 /* set clocks etc */ 1683 if (ctlr->chip->cfg1 < HPT372) 1684 pci_write_config(dev, 0x5b, 0x22, 1); 1685 else 1686 pci_write_config(dev, 0x5b, 1687 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 1688 } 1689 ctlr->allocate = ata_highpoint_allocate; 1690 ctlr->setmode = ata_highpoint_setmode; 1691 return 0; 1692 } 1693 1694 static int 1695 ata_highpoint_allocate(device_t dev) 1696 { 1697 struct ata_channel *ch = device_get_softc(dev); 1698 1699 /* setup the usual register normal pci style */ 1700 if (ata_pci_allocate(dev)) 1701 return ENXIO; 1702 1703 ch->flags |= ATA_ALWAYS_DMASTAT; 1704 return 0; 1705 } 1706 1707 static void 1708 ata_highpoint_setmode(device_t dev, int mode) 1709 { 1710 device_t gparent = GRANDPARENT(dev); 1711 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1712 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1713 struct ata_device *atadev = device_get_softc(dev); 1714 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1715 int error; 1716 u_int32_t timings33[][4] = { 1717 /* HPT366 HPT370 HPT372 HPT374 mode */ 1718 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */ 1719 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */ 1720 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */ 1721 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */ 1722 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */ 1723 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */ 1724 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */ 1725 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */ 1726 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */ 1727 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */ 1728 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */ 1729 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */ 1730 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */ 1731 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */ 1732 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */ 1733 }; 1734 1735 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1736 1737 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev)) 1738 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1739 1740 mode = ata_highpoint_check_80pin(dev, mode); 1741 1742 /* 1743 * most if not all HPT chips cant really handle that the device is 1744 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to 1745 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance 1746 */ 1747 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 1748 ata_limit_mode(dev, mode, ATA_UDMA5)); 1749 if (bootverbose) 1750 device_printf(dev, "%ssetting %s on HighPoint chip\n", 1751 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1752 if (!error) 1753 pci_write_config(gparent, 0x40 + (devno << 2), 1754 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 1755 atadev->mode = mode; 1756 } 1757 1758 static int 1759 ata_highpoint_check_80pin(device_t dev, int mode) 1760 { 1761 device_t gparent = GRANDPARENT(dev); 1762 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1763 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1764 u_int8_t reg, val, res; 1765 1766 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) { 1767 reg = ch->unit ? 0x57 : 0x53; 1768 val = pci_read_config(gparent, reg, 1); 1769 pci_write_config(gparent, reg, val | 0x80, 1); 1770 } 1771 else { 1772 reg = 0x5b; 1773 val = pci_read_config(gparent, reg, 1); 1774 pci_write_config(gparent, reg, val & 0xfe, 1); 1775 } 1776 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2); 1777 pci_write_config(gparent, reg, val, 1); 1778 1779 if (mode > ATA_UDMA2 && res) { 1780 ata_print_cable(dev, "controller"); 1781 mode = ATA_UDMA2; 1782 } 1783 return mode; 1784 } 1785 1786 1787 /* 1788 * Intel chipset support functions 1789 */ 1790 int 1791 ata_intel_ident(device_t dev) 1792 { 1793 struct ata_pci_controller *ctlr = device_get_softc(dev); 1794 struct ata_chip_id *idx; 1795 static struct ata_chip_id ids[] = 1796 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" }, 1797 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" }, 1798 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1799 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1800 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1801 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" }, 1802 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1803 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1804 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1805 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1806 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1807 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1808 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1809 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1810 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" }, 1811 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1812 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1813 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" }, 1814 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1815 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1816 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" }, 1817 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1818 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1819 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" }, 1820 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" }, 1821 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1822 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1823 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1824 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1825 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1826 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1827 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" }, 1828 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1829 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1830 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1831 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1832 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1833 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1834 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1835 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1836 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1837 { ATA_I82801HBM_S1, 0, 0, 0x00, ATA_SA300, "ICH8M" }, 1838 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1839 { ATA_I82801HBM_S3, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1840 { ATA_I82801IB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1841 { ATA_I82801IB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1842 { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1843 { ATA_I82801IB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1844 { ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1845 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" }, 1846 { 0, 0, 0, 0, 0, 0}}; 1847 char buffer[64]; 1848 1849 if (!(idx = ata_match_chip(dev, ids))) 1850 return ENXIO; 1851 1852 ksprintf(buffer, "Intel %s %s controller", 1853 idx->text, ata_mode2str(idx->max_dma)); 1854 device_set_desc_copy(dev, buffer); 1855 ctlr->chip = idx; 1856 ctlr->chipinit = ata_intel_chipinit; 1857 return 0; 1858 } 1859 1860 static int 1861 ata_intel_chipinit(device_t dev) 1862 { 1863 struct ata_pci_controller *ctlr = device_get_softc(dev); 1864 1865 if (ata_setup_interrupt(dev)) 1866 return ENXIO; 1867 1868 /* good old PIIX needs special treatment (not implemented) */ 1869 if (ctlr->chip->chipid == ATA_I82371FB) { 1870 ctlr->setmode = ata_intel_old_setmode; 1871 } 1872 1873 /* the intel 31244 needs special care if in DPA mode */ 1874 else if (ctlr->chip->chipid == ATA_I31244) { 1875 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 1876 ctlr->r_type2 = SYS_RES_MEMORY; 1877 ctlr->r_rid2 = PCIR_BAR(0); 1878 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1879 &ctlr->r_rid2, 1880 RF_ACTIVE))) { 1881 ata_teardown_interrupt(dev); 1882 return ENXIO; 1883 } 1884 ctlr->channels = 4; 1885 ctlr->allocate = ata_intel_31244_allocate; 1886 ctlr->reset = ata_intel_31244_reset; 1887 } 1888 ctlr->setmode = ata_sata_setmode; 1889 } 1890 1891 /* non SATA intel chips goes here */ 1892 else if (ctlr->chip->max_dma < ATA_SA150) { 1893 ctlr->allocate = ata_intel_allocate; 1894 ctlr->setmode = ata_intel_new_setmode; 1895 } 1896 1897 /* SATA parts can be either compat or AHCI */ 1898 else { 1899 /* force all ports active "the legacy way" */ 1900 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2); 1901 1902 ctlr->allocate = ata_intel_allocate; 1903 ctlr->reset = ata_intel_reset; 1904 1905 /* 1906 * if we have AHCI capability and BAR(5) as a memory resource 1907 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode 1908 */ 1909 if ((ctlr->chip->cfg1 == AHCI) && 1910 (pci_read_config(dev, 0x90, 1) & 0xc0) && 1911 (ata_ahci_chipinit(dev) != ENXIO)) 1912 return 0; 1913 1914 /* if BAR(5) is IO it should point to SATA interface registers */ 1915 ctlr->r_type2 = SYS_RES_IOPORT; 1916 ctlr->r_rid2 = PCIR_BAR(5); 1917 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1918 &ctlr->r_rid2, RF_ACTIVE))) 1919 ctlr->setmode = ata_intel_sata_setmode; 1920 else 1921 ctlr->setmode = ata_sata_setmode; 1922 1923 /* enable PCI interrupt */ 1924 pci_write_config(dev, PCIR_COMMAND, 1925 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1926 } 1927 return 0; 1928 } 1929 1930 static int 1931 ata_intel_allocate(device_t dev) 1932 { 1933 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1934 struct ata_channel *ch = device_get_softc(dev); 1935 1936 /* setup the usual register normal pci style */ 1937 if (ata_pci_allocate(dev)) 1938 return ENXIO; 1939 1940 /* if r_res2 is valid it points to SATA interface registers */ 1941 if (ctlr->r_res2) { 1942 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 1943 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 1944 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 1945 ch->r_io[ATA_IDX_DATA].offset = 0x04; 1946 } 1947 1948 ch->flags |= ATA_ALWAYS_DMASTAT; 1949 return 0; 1950 } 1951 1952 static void 1953 ata_intel_reset(device_t dev) 1954 { 1955 device_t parent = device_get_parent(dev); 1956 struct ata_pci_controller *ctlr = device_get_softc(parent); 1957 struct ata_channel *ch = device_get_softc(dev); 1958 int mask, timeout; 1959 1960 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */ 1961 if (ctlr->chip->cfg1) { 1962 mask = (0x0005 << ch->unit); 1963 } 1964 else { 1965 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */ 1966 if (pci_read_config(parent, 0x90, 1) & 0x04) 1967 mask = 0x0003; 1968 else { 1969 mask = (0x0001 << ch->unit); 1970 /* XXX SOS should be in intel_allocate if we grow it */ 1971 ch->flags |= ATA_NO_SLAVE; 1972 } 1973 } 1974 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2); 1975 DELAY(10); 1976 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2); 1977 1978 /* wait up to 1 sec for "connect well" */ 1979 for (timeout = 0; timeout < 100 ; timeout++) { 1980 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) && 1981 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 1982 break; 1983 ata_udelay(10000); 1984 } 1985 ata_generic_reset(dev); 1986 } 1987 1988 static void 1989 ata_intel_old_setmode(device_t dev, int mode) 1990 { 1991 /* NOT YET */ 1992 } 1993 1994 static void 1995 ata_intel_new_setmode(device_t dev, int mode) 1996 { 1997 device_t gparent = GRANDPARENT(dev); 1998 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1999 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2000 struct ata_device *atadev = device_get_softc(dev); 2001 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2002 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4); 2003 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1); 2004 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1); 2005 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2); 2006 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2); 2007 u_int32_t mask40 = 0, new40 = 0; 2008 u_int8_t mask44 = 0, new44 = 0; 2009 int error; 2010 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, 2011 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 }; 2012 /* PIO0 PIO1 PIO2 PIO3 PIO4 WDMA0 WDMA1 WDMA2 */ 2013 /* UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 UDMA5 UDMA6 */ 2014 2015 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 2016 2017 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { 2018 ata_print_cable(dev, "controller"); 2019 mode = ATA_UDMA2; 2020 } 2021 2022 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2023 2024 if (bootverbose) 2025 device_printf(dev, "%ssetting %s on %s chip\n", 2026 (error) ? "FAILURE " : "", 2027 ata_mode2str(mode), ctlr->chip->text); 2028 if (error) 2029 return; 2030 2031 /* 2032 * reg48: 1 bit per (primary drive 0, primary drive 1, secondary 2033 * drive 0, secondary drive 1) 2034 * 2035 * 0 Disable Ultra DMA mode 2036 * 1 Enable Ultra DMA mode 2037 * 2038 * reg4a: 4 bits per (primary drive 0, primary drive 1, secondary 2039 * drive 0, secondary drive 1). 2040 * 0000 UDMA mode 0 2041 * 0001 UDMA mode 1, 3, 5 2042 * 0010 UDMA mode 2, 4, reserved 2043 * 0011 reserved 2044 * (top two bits for each drive reserved) 2045 */ 2046 #if 0 2047 device_printf(dev, 2048 "regs before 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 2049 reg40, reg44, reg48 ,reg4a, reg54); 2050 #endif 2051 reg48 &= ~(0x0001 << devno); 2052 reg4a &= ~(0x3 << (devno << 2)); 2053 if (mode >= ATA_UDMA0) { 2054 reg48 |= 0x0001 << devno; 2055 if (mode > ATA_UDMA0) 2056 reg4a |= (1 + !(mode & 0x01)) << (devno << 2); 2057 } 2058 pci_write_config(gparent, 0x48, reg48, 2); 2059 pci_write_config(gparent, 0x4a, reg4a, 2); 2060 2061 /* 2062 * reg54: 2063 * 2064 * 32:20 reserved 2065 * 19:18 Secondary ATA signal mode 2066 * 17:16 Primary ATA signal mode 2067 * 00 = Normal (enabled) 2068 * 01 = Tri-state (disabled) 2069 * 10 = Drive Low (disabled) 2070 * 11 = Reserved 2071 * 2072 * 15 Secondary drive 1 - Base Clock 2073 * 14 Secondary drive 0 - Base Clock 2074 * 13 Primary drive 1 - Base Clock 2075 * 12 Primary drive 0 - Base Clock 2076 * 0 = Select 33 MHz clock 2077 * 1 = Select 100 Mhz clock 2078 * 2079 * 11 Reserved 2080 * 10 Vendor specific (set by BIOS?) 2081 * 09:08 Reserved 2082 * 2083 * 07 Secondary drive 1 - Cable Type 2084 * 06 Secondary drive 0 - Cable Type 2085 * 05 Primary drive 1 - Cable Type 2086 * 04 Primary drive 0 - Cable Type 2087 * 0 = 40 Conductor 2088 * 1 = 80 Conductor (or high speed cable) 2089 * 2090 * 03 Secondary drive 1 - Select 33/66 clock 2091 * 02 Secondary drive 0 - Select 33/66 clock 2092 * 01 Primary drive 1 - Select 33/66 clock 2093 * 00 Primary drive 0 - Select 33/66 clock 2094 * 0 = Select 33 MHz 2095 * 1 = Select 66 MHz 2096 * 2097 * It is unclear what this should be set to when operating 2098 * in 100MHz mode. 2099 * 2100 * NOTE: UDMA2 = 33 MHz 2101 * UDMA3 = 40 MHz (?) - unsupported 2102 * UDMA4 = 66 MHz 2103 * UDMA5 = 100 MHz 2104 * UDMA6 = 133 Mhz 2105 */ 2106 reg54 |= 0x0400; /* set vendor specific bit */ 2107 reg54 &= ~((0x1 << devno) | (0x1000 << devno)); 2108 2109 if (mode >= ATA_UDMA5) 2110 reg54 |= (0x1000 << devno); 2111 else if (mode >= ATA_UDMA3) /* XXX should this be ATA_UDMA3 or 4? */ 2112 reg54 |= (0x1 << devno); 2113 2114 pci_write_config(gparent, 0x54, reg54, 2); 2115 2116 /* 2117 * Reg40 (32 bits... well, actually two 16 bit registers) 2118 * 2119 * Primary channel bits 15:00, Secondary channel bits 31:00. Note 2120 * that slave timings are handled in register 44. 2121 * 2122 * 15 ATA Decode Enable (R/W) 1 = enable decoding of I/O ranges 2123 * 2124 * 14 Slave ATA Timing Register Enable (R/W) 2125 * 2126 * 13:12 IORDY Sample Mode 2127 * 00 PIO-0 2128 * 01 PIO-2, SW-2 2129 * 10 PIO-3, PIO-4, MW-1, MW-2 2130 * 11 Reserved 2131 * 2132 * 11:10 Reserved 2133 * 2134 * 09:08 Recovery Mode 2135 * 00 PIO-0, PIO-2, SW-2 2136 * 01 PIO-3, MW-1 2137 * 10 Reserved 2138 * 11 PIO-4, MW-2 2139 * 2140 * 07:04 Secondary Device Control Bits 2141 * 03:00 Primary Device Control Bits 2142 * 2143 * bit 3 DMA Timing Enable 2144 * 2145 * bit 2 Indicate Presence of ATA(1) or ATAPI(0) device 2146 * 2147 * bit 1 Enable IORDY sample point capability for PIO 2148 * xfers. Always enabled for PIO4 and PIO3, enabled 2149 * for PIO2 if indicated by the device, and otherwise 2150 * probably should be 0. 2151 * 2152 * bit 0 Fast Drive Timing Enable. Enables faster then PIO-0 2153 * timing modes. 2154 */ 2155 2156 /* 2157 * Modify reg40 according to the table 2158 */ 2159 if (atadev->unit == ATA_MASTER) { 2160 mask40 = 0x3300; 2161 new40 = timings[ata_mode2idx(mode)] << 8; 2162 } 2163 else { 2164 mask44 = 0x0f; 2165 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) | 2166 (timings[ata_mode2idx(mode)] & 0x03); 2167 } 2168 2169 /* 2170 * Slave ATA timing register enable 2171 */ 2172 mask40 |= 0x4000; 2173 new40 |= 0x4000; 2174 2175 /* 2176 * Device control bits 3:0 for master, 7:4 for slave. 2177 * 2178 * bit3 DMA Timing enable. 2179 * bit2 Indicate presence of ATA(1) or ATAPI(0) device, set accordingly 2180 * bit1 Enable IORDY sample point capability for PIO xfers. Always 2181 * enabled for PIO4 and PIO3, enabled for PIO2 if indicated by 2182 * the device, and otherwise should be 0. 2183 * bit0 Fast Drive Timing Enable. Enable faster then PIO-0 timing modes. 2184 * 2185 * Set to: 0 x 1 1 2186 */ 2187 2188 if (atadev->unit == ATA_MASTER) { 2189 mask40 |= 0x0F; 2190 new40 |= 0x03; 2191 if (!ata_atapi(dev)) 2192 new40 |= 0x04; 2193 } else { 2194 mask40 |= 0xF0; 2195 new40 |= 0x30; 2196 if (!ata_atapi(dev)) 2197 new40 |= 0x40; 2198 } 2199 /* 2200 reg40 &= ~0x00ff00ff; 2201 reg40 |= 0x40774077; 2202 */ 2203 2204 /* 2205 * Primary or Secondary controller 2206 */ 2207 if (ch->unit) { 2208 mask40 <<= 16; 2209 new40 <<= 16; 2210 mask44 <<= 4; 2211 new44 <<= 4; 2212 } 2213 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4); 2214 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1); 2215 2216 #if 0 2217 reg40 = pci_read_config(gparent, 0x40, 4); 2218 reg44 = pci_read_config(gparent, 0x44, 1); 2219 reg48 = pci_read_config(gparent, 0x48, 1); 2220 reg4a = pci_read_config(gparent, 0x4a, 2); 2221 reg54 = pci_read_config(gparent, 0x54, 2); 2222 device_printf(dev, 2223 "regs after 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 2224 reg40, reg44, reg48 ,reg4a, reg54); 2225 #endif 2226 2227 atadev->mode = mode; 2228 } 2229 2230 static void 2231 ata_intel_sata_setmode(device_t dev, int mode) 2232 { 2233 struct ata_device *atadev = device_get_softc(dev); 2234 2235 if (atadev->param.satacapabilities != 0x0000 && 2236 atadev->param.satacapabilities != 0xffff) { 2237 2238 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2239 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2240 2241 /* on some drives we need to set the transfer mode */ 2242 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 2243 ata_limit_mode(dev, mode, ATA_UDMA6)); 2244 2245 /* set ATA_SSTATUS register offset */ 2246 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100); 2247 2248 /* query SATA STATUS for the speed */ 2249 if ((ATA_IDX_INL(ch, ATA_IDX_DATA) & ATA_SS_CONWELL_MASK) == 2250 ATA_SS_CONWELL_GEN2) 2251 atadev->mode = ATA_SA300; 2252 else 2253 atadev->mode = ATA_SA150; 2254 } 2255 else { 2256 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 2257 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2258 atadev->mode = mode; 2259 } 2260 } 2261 2262 static int 2263 ata_intel_31244_allocate(device_t dev) 2264 { 2265 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2266 struct ata_channel *ch = device_get_softc(dev); 2267 int i; 2268 int ch_offset; 2269 2270 ch_offset = 0x200 + ch->unit * 0x200; 2271 2272 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 2273 ch->r_io[i].res = ctlr->r_res2; 2274 2275 /* setup ATA registers */ 2276 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 2277 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 2278 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 2279 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 2280 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 2281 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 2282 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 2283 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 2284 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 2285 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 2286 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 2287 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 2288 2289 /* setup DMA registers */ 2290 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 2291 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 2292 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 2293 2294 /* setup SATA registers */ 2295 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 2296 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 2297 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 2298 2299 ch->flags |= ATA_NO_SLAVE; 2300 ata_pci_hw(dev); 2301 ch->hw.status = ata_intel_31244_status; 2302 ch->hw.command = ata_intel_31244_command; 2303 2304 /* enable PHY state change interrupt */ 2305 ATA_OUTL(ctlr->r_res2, 0x4, 2306 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 2307 return 0; 2308 } 2309 2310 static int 2311 ata_intel_31244_status(device_t dev) 2312 { 2313 /* do we have any PHY events ? */ 2314 ata_sata_phy_check_events(dev); 2315 2316 /* any drive action to take care of ? */ 2317 return ata_pci_status(dev); 2318 } 2319 2320 static int 2321 ata_intel_31244_command(struct ata_request *request) 2322 { 2323 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2324 struct ata_device *atadev = device_get_softc(request->dev); 2325 u_int64_t lba; 2326 2327 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 2328 return (ata_generic_command(request)); 2329 2330 lba = request->u.ata.lba; 2331 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 2332 /* enable interrupt */ 2333 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 2334 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 2335 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 2336 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff)); 2337 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) | 2338 ((lba >> 8) & 0x00ff)); 2339 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) | 2340 ((lba >> 16) & 0x00ff)); 2341 2342 /* issue command to controller */ 2343 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 2344 2345 return 0; 2346 } 2347 2348 static void 2349 ata_intel_31244_reset(device_t dev) 2350 { 2351 if (ata_sata_phy_reset(dev)) 2352 ata_generic_reset(dev); 2353 } 2354 2355 2356 /* 2357 * Integrated Technology Express Inc. (ITE) chipset support functions 2358 */ 2359 int 2360 ata_ite_ident(device_t dev) 2361 { 2362 struct ata_pci_controller *ctlr = device_get_softc(dev); 2363 struct ata_chip_id *idx; 2364 static struct ata_chip_id ids[] = 2365 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 2366 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 2367 { 0, 0, 0, 0, 0, 0}}; 2368 char buffer[64]; 2369 2370 if (!(idx = ata_match_chip(dev, ids))) 2371 return ENXIO; 2372 2373 ksprintf(buffer, "ITE %s %s controller", 2374 idx->text, ata_mode2str(idx->max_dma)); 2375 device_set_desc_copy(dev, buffer); 2376 ctlr->chip = idx; 2377 ctlr->chipinit = ata_ite_chipinit; 2378 return 0; 2379 } 2380 2381 static int 2382 ata_ite_chipinit(device_t dev) 2383 { 2384 struct ata_pci_controller *ctlr = device_get_softc(dev); 2385 2386 if (ata_setup_interrupt(dev)) 2387 return ENXIO; 2388 2389 ctlr->setmode = ata_ite_setmode; 2390 2391 /* set PCI mode and 66Mhz reference clock */ 2392 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 2393 2394 /* set default active & recover timings */ 2395 pci_write_config(dev, 0x54, 0x31, 1); 2396 pci_write_config(dev, 0x56, 0x31, 1); 2397 return 0; 2398 } 2399 2400 static void 2401 ata_ite_setmode(device_t dev, int mode) 2402 { 2403 device_t gparent = GRANDPARENT(dev); 2404 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2405 struct ata_device *atadev = device_get_softc(dev); 2406 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2407 int error; 2408 2409 /* correct the mode for what the HW supports */ 2410 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2411 2412 /* check the CBLID bits for 80 conductor cable detection */ 2413 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) & 2414 (ch->unit ? (1<<3) : (1<<2)))) { 2415 ata_print_cable(dev, "controller"); 2416 mode = ATA_UDMA2; 2417 } 2418 2419 /* set the wanted mode on the device */ 2420 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2421 2422 if (bootverbose) 2423 device_printf(dev, "%s setting %s on ITE8212F chip\n", 2424 (error) ? "failed" : "success", ata_mode2str(mode)); 2425 2426 /* if the device accepted the mode change, setup the HW accordingly */ 2427 if (!error) { 2428 if (mode >= ATA_UDMA0) { 2429 u_int8_t udmatiming[] = 2430 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 2431 2432 /* enable UDMA mode */ 2433 pci_write_config(gparent, 0x50, 2434 pci_read_config(gparent, 0x50, 1) & 2435 ~(1 << (devno + 3)), 1); 2436 2437 /* set UDMA timing */ 2438 pci_write_config(gparent, 2439 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit), 2440 udmatiming[mode & ATA_MODE_MASK], 1); 2441 } 2442 else { 2443 u_int8_t chtiming[] = 2444 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 2445 2446 /* disable UDMA mode */ 2447 pci_write_config(gparent, 0x50, 2448 pci_read_config(gparent, 0x50, 1) | 2449 (1 << (devno + 3)), 1); 2450 2451 /* set active and recover timing (shared between master & slave) */ 2452 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) < 2453 chtiming[ata_mode2idx(mode)]) 2454 pci_write_config(gparent, 0x54 + (ch->unit << 2), 2455 chtiming[ata_mode2idx(mode)], 1); 2456 } 2457 atadev->mode = mode; 2458 } 2459 } 2460 2461 2462 /* 2463 * JMicron chipset support functions 2464 */ 2465 int 2466 ata_jmicron_ident(device_t dev) 2467 { 2468 struct ata_pci_controller *ctlr = device_get_softc(dev); 2469 struct ata_chip_id *idx; 2470 static struct ata_chip_id ids[] = 2471 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" }, 2472 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" }, 2473 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" }, 2474 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" }, 2475 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" }, 2476 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" }, 2477 { 0, 0, 0, 0, 0, 0}}; 2478 char buffer[64]; 2479 2480 if (!(idx = ata_match_chip(dev, ids))) 2481 return ENXIO; 2482 2483 if ((pci_read_config(dev, 0xdf, 1) & 0x40) && 2484 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1))) 2485 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2486 idx->text, ata_mode2str(ATA_UDMA6)); 2487 else 2488 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2489 idx->text, ata_mode2str(idx->max_dma)); 2490 device_set_desc_copy(dev, buffer); 2491 ctlr->chip = idx; 2492 ctlr->chipinit = ata_jmicron_chipinit; 2493 return 0; 2494 } 2495 2496 static int 2497 ata_jmicron_chipinit(device_t dev) 2498 { 2499 struct ata_pci_controller *ctlr = device_get_softc(dev); 2500 int error; 2501 2502 if (ata_setup_interrupt(dev)) 2503 return ENXIO; 2504 2505 /* do we have multiple PCI functions ? */ 2506 if (pci_read_config(dev, 0xdf, 1) & 0x40) { 2507 /* are we on the AHCI part ? */ 2508 if (ata_ahci_chipinit(dev) != ENXIO) 2509 return 0; 2510 2511 /* otherwise we are on the PATA part */ 2512 ctlr->allocate = ata_pci_allocate; 2513 ctlr->reset = ata_generic_reset; 2514 ctlr->dmainit = ata_pci_dmainit; 2515 ctlr->setmode = ata_jmicron_setmode; 2516 ctlr->channels = ctlr->chip->cfg2; 2517 } 2518 else { 2519 /* set controller configuration to a combined setup we support */ 2520 pci_write_config(dev, 0x40, 0x80c0a131, 4); 2521 pci_write_config(dev, 0x80, 0x01200000, 4); 2522 2523 if ((error = ata_ahci_chipinit(dev))) { 2524 ata_teardown_interrupt(dev); 2525 return error; 2526 } 2527 2528 ctlr->allocate = ata_jmicron_allocate; 2529 ctlr->reset = ata_jmicron_reset; 2530 ctlr->dmainit = ata_jmicron_dmainit; 2531 ctlr->setmode = ata_jmicron_setmode; 2532 2533 /* set the number of HW channels */ 2534 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2; 2535 } 2536 return 0; 2537 } 2538 2539 static int 2540 ata_jmicron_allocate(device_t dev) 2541 { 2542 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2543 struct ata_channel *ch = device_get_softc(dev); 2544 int error; 2545 2546 if (ch->unit >= ctlr->chip->cfg1) { 2547 ch->unit -= ctlr->chip->cfg1; 2548 error = ata_pci_allocate(dev); 2549 ch->unit += ctlr->chip->cfg1; 2550 } 2551 else 2552 error = ata_ahci_allocate(dev); 2553 return error; 2554 } 2555 2556 static void 2557 ata_jmicron_reset(device_t dev) 2558 { 2559 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2560 struct ata_channel *ch = device_get_softc(dev); 2561 2562 if (ch->unit >= ctlr->chip->cfg1) 2563 ata_generic_reset(dev); 2564 else 2565 ata_ahci_reset(dev); 2566 } 2567 2568 static void 2569 ata_jmicron_dmainit(device_t dev) 2570 { 2571 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2572 struct ata_channel *ch = device_get_softc(dev); 2573 2574 if (ch->unit >= ctlr->chip->cfg1) 2575 ata_pci_dmainit(dev); 2576 else 2577 ata_ahci_dmainit(dev); 2578 } 2579 2580 static void 2581 ata_jmicron_setmode(device_t dev, int mode) 2582 { 2583 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 2584 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2585 2586 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) { 2587 struct ata_device *atadev = device_get_softc(dev); 2588 2589 /* check for 80pin cable present */ 2590 if (pci_read_config(dev, 0x40, 1) & 0x08) 2591 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 2592 else 2593 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2594 2595 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2596 atadev->mode = mode; 2597 } 2598 else 2599 ata_sata_setmode(dev, mode); 2600 } 2601 2602 2603 /* 2604 * Marvell chipset support functions 2605 */ 2606 #define ATA_MV_HOST_BASE(ch) \ 2607 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000) 2608 #define ATA_MV_EDMA_BASE(ch) \ 2609 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000) 2610 2611 struct ata_marvell_response { 2612 u_int16_t tag; 2613 u_int8_t edma_status; 2614 u_int8_t dev_status; 2615 u_int32_t timestamp; 2616 }; 2617 2618 struct ata_marvell_dma_prdentry { 2619 u_int32_t addrlo; 2620 u_int32_t count; 2621 u_int32_t addrhi; 2622 u_int32_t reserved; 2623 }; 2624 2625 int 2626 ata_marvell_ident(device_t dev) 2627 { 2628 struct ata_pci_controller *ctlr = device_get_softc(dev); 2629 struct ata_chip_id *idx; 2630 static struct ata_chip_id ids[] = 2631 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" }, 2632 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" }, 2633 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" }, 2634 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" }, 2635 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" }, 2636 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" }, 2637 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" }, 2638 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" }, 2639 { 0, 0, 0, 0, 0, 0}}; 2640 char buffer[64]; 2641 2642 if (!(idx = ata_match_chip(dev, ids))) 2643 return ENXIO; 2644 2645 ksprintf(buffer, "Marvell %s %s controller", 2646 idx->text, ata_mode2str(idx->max_dma)); 2647 device_set_desc_copy(dev, buffer); 2648 ctlr->chip = idx; 2649 switch (ctlr->chip->cfg2) { 2650 case MV50XX: 2651 case MV60XX: 2652 ctlr->chipinit = ata_marvell_edma_chipinit; 2653 break; 2654 case MV61XX: 2655 ctlr->chipinit = ata_marvell_pata_chipinit; 2656 break; 2657 } 2658 return 0; 2659 } 2660 2661 static int 2662 ata_marvell_pata_chipinit(device_t dev) 2663 { 2664 struct ata_pci_controller *ctlr = device_get_softc(dev); 2665 2666 if (ata_setup_interrupt(dev)) 2667 return ENXIO; 2668 2669 ctlr->allocate = ata_marvell_pata_allocate; 2670 ctlr->setmode = ata_marvell_pata_setmode; 2671 ctlr->channels = ctlr->chip->cfg1; 2672 return 0; 2673 } 2674 2675 static int 2676 ata_marvell_pata_allocate(device_t dev) 2677 { 2678 struct ata_channel *ch = device_get_softc(dev); 2679 2680 /* setup the usual register normal pci style */ 2681 if (ata_pci_allocate(dev)) 2682 return ENXIO; 2683 2684 /* dont use 32 bit PIO transfers */ 2685 ch->flags |= ATA_USE_16BIT; 2686 2687 return 0; 2688 } 2689 2690 static void 2691 ata_marvell_pata_setmode(device_t dev, int mode) 2692 { 2693 device_t gparent = GRANDPARENT(dev); 2694 struct ata_pci_controller *ctlr = device_get_softc(gparent); 2695 struct ata_device *atadev = device_get_softc(dev); 2696 2697 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 2698 mode = ata_check_80pin(dev, mode); 2699 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2700 atadev->mode = mode; 2701 } 2702 2703 static int 2704 ata_marvell_edma_chipinit(device_t dev) 2705 { 2706 struct ata_pci_controller *ctlr = device_get_softc(dev); 2707 2708 if (ata_setup_interrupt(dev)) 2709 return ENXIO; 2710 2711 ctlr->r_type1 = SYS_RES_MEMORY; 2712 ctlr->r_rid1 = PCIR_BAR(0); 2713 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 2714 &ctlr->r_rid1, RF_ACTIVE))) { 2715 ata_teardown_interrupt(dev); 2716 return ENXIO; 2717 } 2718 2719 /* mask all host controller interrupts */ 2720 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000); 2721 2722 /* mask all PCI interrupts */ 2723 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000); 2724 2725 ctlr->allocate = ata_marvell_edma_allocate; 2726 ctlr->reset = ata_marvell_edma_reset; 2727 ctlr->dmainit = ata_marvell_edma_dmainit; 2728 ctlr->setmode = ata_sata_setmode; 2729 ctlr->channels = ctlr->chip->cfg1; 2730 2731 /* clear host controller interrupts */ 2732 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000); 2733 if (ctlr->chip->cfg1 > 4) 2734 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000); 2735 2736 /* clear PCI interrupts */ 2737 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000); 2738 2739 /* unmask PCI interrupts we want */ 2740 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff); 2741 2742 /* unmask host controller interrupts we want */ 2743 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ | 2744 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25)); 2745 2746 /* enable PCI interrupt */ 2747 pci_write_config(dev, PCIR_COMMAND, 2748 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 2749 return 0; 2750 } 2751 2752 static int 2753 ata_marvell_edma_allocate(device_t dev) 2754 { 2755 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2756 struct ata_channel *ch = device_get_softc(dev); 2757 u_int64_t work = ch->dma->work_bus; 2758 int i; 2759 2760 /* clear work area */ 2761 bzero(ch->dma->work, 1024+256); 2762 2763 /* set legacy ATA resources */ 2764 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 2765 ch->r_io[i].res = ctlr->r_res1; 2766 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch); 2767 } 2768 ch->r_io[ATA_CONTROL].res = ctlr->r_res1; 2769 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch); 2770 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1; 2771 ata_default_registers(dev); 2772 2773 /* set SATA resources */ 2774 switch (ctlr->chip->cfg2) { 2775 case MV50XX: 2776 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2777 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch); 2778 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2779 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch); 2780 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2781 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch); 2782 break; 2783 case MV60XX: 2784 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2785 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch); 2786 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2787 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch); 2788 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2789 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch); 2790 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1; 2791 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch); 2792 break; 2793 } 2794 2795 ch->flags |= ATA_NO_SLAVE; 2796 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */ 2797 ata_generic_hw(dev); 2798 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction; 2799 ch->hw.end_transaction = ata_marvell_edma_end_transaction; 2800 ch->hw.status = ata_marvell_edma_status; 2801 2802 /* disable the EDMA machinery */ 2803 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2804 DELAY(100000); /* SOS should poll for disabled */ 2805 2806 /* set configuration to non-queued 128b read transfers stop on error */ 2807 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13)); 2808 2809 /* request queue base high */ 2810 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32); 2811 2812 /* request queue in ptr */ 2813 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2814 2815 /* request queue out ptr */ 2816 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0); 2817 2818 /* response queue base high */ 2819 work += 1024; 2820 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32); 2821 2822 /* response queue in ptr */ 2823 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0); 2824 2825 /* response queue out ptr */ 2826 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2827 2828 /* clear SATA error register */ 2829 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 2830 2831 /* clear any outstanding error interrupts */ 2832 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2833 2834 /* unmask all error interrupts */ 2835 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 2836 2837 /* enable EDMA machinery */ 2838 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2839 return 0; 2840 } 2841 2842 static int 2843 ata_marvell_edma_status(device_t dev) 2844 { 2845 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2846 struct ata_channel *ch = device_get_softc(dev); 2847 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60); 2848 int shift = (ch->unit << 1) + (ch->unit > 3); 2849 2850 if (cause & (1 << shift)) { 2851 2852 /* clear interrupt(s) */ 2853 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2854 2855 /* do we have any PHY events ? */ 2856 ata_sata_phy_check_events(dev); 2857 } 2858 2859 /* do we have any device action ? */ 2860 return (cause & (2 << shift)); 2861 } 2862 2863 /* must be called with ATA channel locked and state_mtx held */ 2864 static int 2865 ata_marvell_edma_begin_transaction(struct ata_request *request) 2866 { 2867 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2868 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2869 u_int32_t req_in; 2870 u_int8_t *bytep; 2871 u_int16_t *wordp; 2872 u_int32_t *quadp; 2873 int i, tag = 0x07; 2874 int dummy, error, slot; 2875 2876 /* only DMA R/W goes through the EMDA machine */ 2877 if (request->u.ata.command != ATA_READ_DMA && 2878 request->u.ata.command != ATA_WRITE_DMA) { 2879 2880 /* disable the EDMA machinery */ 2881 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001) 2882 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2883 return ata_begin_transaction(request); 2884 } 2885 2886 /* check for 48 bit access and convert if needed */ 2887 ata_modify_if_48bit(request); 2888 2889 /* check sanity, setup SG list and DMA engine */ 2890 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 2891 request->flags & ATA_R_READ, ch->dma->sg, 2892 &dummy))) { 2893 device_printf(request->dev, "setting up DMA failed\n"); 2894 request->result = error; 2895 return ATA_OP_FINISHED; 2896 } 2897 2898 /* get next free request queue slot */ 2899 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch)); 2900 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f; 2901 bytep = (u_int8_t *)(ch->dma->work); 2902 bytep += (slot << 5); 2903 wordp = (u_int16_t *)bytep; 2904 quadp = (u_int32_t *)bytep; 2905 2906 /* fill in this request */ 2907 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff; 2908 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32; 2909 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1); 2910 2911 i = 10; 2912 bytep[i++] = (request->u.ata.count >> 8) & 0xff; 2913 bytep[i++] = 0x10 | ATA_COUNT; 2914 bytep[i++] = request->u.ata.count & 0xff; 2915 bytep[i++] = 0x10 | ATA_COUNT; 2916 2917 bytep[i++] = (request->u.ata.lba >> 24) & 0xff; 2918 bytep[i++] = 0x10 | ATA_SECTOR; 2919 bytep[i++] = request->u.ata.lba & 0xff; 2920 bytep[i++] = 0x10 | ATA_SECTOR; 2921 2922 bytep[i++] = (request->u.ata.lba >> 32) & 0xff; 2923 bytep[i++] = 0x10 | ATA_CYL_LSB; 2924 bytep[i++] = (request->u.ata.lba >> 8) & 0xff; 2925 bytep[i++] = 0x10 | ATA_CYL_LSB; 2926 2927 bytep[i++] = (request->u.ata.lba >> 40) & 0xff; 2928 bytep[i++] = 0x10 | ATA_CYL_MSB; 2929 bytep[i++] = (request->u.ata.lba >> 16) & 0xff; 2930 bytep[i++] = 0x10 | ATA_CYL_MSB; 2931 2932 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf); 2933 bytep[i++] = 0x10 | ATA_DRIVE; 2934 2935 bytep[i++] = request->u.ata.command; 2936 bytep[i++] = 0x90 | ATA_COMMAND; 2937 2938 /* enable EDMA machinery if needed */ 2939 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) { 2940 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2941 while (!(ATA_INL(ctlr->r_res1, 2942 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 2943 DELAY(10); 2944 } 2945 2946 /* tell EDMA it has a new request */ 2947 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f; 2948 req_in &= 0xfffffc00; 2949 req_in += (slot << 5); 2950 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in); 2951 2952 return ATA_OP_CONTINUES; 2953 } 2954 2955 /* must be called with ATA channel locked and state_mtx held */ 2956 static int 2957 ata_marvell_edma_end_transaction(struct ata_request *request) 2958 { 2959 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2960 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2961 int offset = (ch->unit > 3 ? 0x30014 : 0x20014); 2962 u_int32_t icr = ATA_INL(ctlr->r_res1, offset); 2963 int res; 2964 2965 /* EDMA interrupt */ 2966 if ((icr & (0x0001 << (ch->unit & 3)))) { 2967 struct ata_marvell_response *response; 2968 u_int32_t rsp_in, rsp_out; 2969 int slot; 2970 2971 /* stop timeout */ 2972 callout_stop(&request->callout); 2973 2974 /* get response ptr's */ 2975 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch)); 2976 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch)); 2977 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f; 2978 rsp_out &= 0xffffff00; 2979 rsp_out += (slot << 3); 2980 response = (struct ata_marvell_response *) 2981 (ch->dma->work + 1024 + (slot << 3)); 2982 2983 /* record status for this request */ 2984 request->status = response->dev_status; 2985 request->error = 0; 2986 2987 /* ack response */ 2988 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out); 2989 2990 /* update progress */ 2991 if (!(request->status & ATA_S_ERROR) && 2992 !(request->flags & ATA_R_TIMEOUT)) 2993 request->donecount = request->bytecount; 2994 2995 /* unload SG list */ 2996 ch->dma->unload(ch->dev); 2997 2998 res = ATA_OP_FINISHED; 2999 } 3000 3001 /* legacy ATA interrupt */ 3002 else { 3003 res = ata_end_transaction(request); 3004 } 3005 3006 /* ack interrupt */ 3007 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3)))); 3008 return res; 3009 } 3010 3011 static void 3012 ata_marvell_edma_reset(device_t dev) 3013 { 3014 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3015 struct ata_channel *ch = device_get_softc(dev); 3016 3017 /* disable the EDMA machinery */ 3018 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 3019 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 3020 DELAY(10); 3021 3022 /* clear SATA error register */ 3023 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 3024 3025 /* clear any outstanding error interrupts */ 3026 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 3027 3028 /* unmask all error interrupts */ 3029 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 3030 3031 /* enable channel and test for devices */ 3032 if (ata_sata_phy_reset(dev)) 3033 ata_generic_reset(dev); 3034 3035 /* enable EDMA machinery */ 3036 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 3037 } 3038 3039 static void 3040 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, 3041 int error) 3042 { 3043 struct ata_dmasetprd_args *args = xsc; 3044 struct ata_marvell_dma_prdentry *prd = args->dmatab; 3045 int i; 3046 3047 if ((args->error = error)) 3048 return; 3049 3050 for (i = 0; i < nsegs; i++) { 3051 prd[i].addrlo = htole32(segs[i].ds_addr); 3052 prd[i].count = htole32(segs[i].ds_len); 3053 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32); 3054 } 3055 prd[i - 1].count |= htole32(ATA_DMA_EOT); 3056 } 3057 3058 static void 3059 ata_marvell_edma_dmainit(device_t dev) 3060 { 3061 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3062 struct ata_channel *ch = device_get_softc(dev); 3063 3064 ata_dmainit(dev); 3065 if (ch->dma) { 3066 /* note start and stop are not used here */ 3067 ch->dma->setprd = ata_marvell_edma_dmasetprd; 3068 3069 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004) 3070 ch->dma->max_address = BUS_SPACE_MAXADDR; 3071 3072 /* chip does not reliably do 64K DMA transfers */ 3073 ch->dma->max_iosize = 126 * DEV_BSIZE; 3074 } 3075 } 3076 3077 3078 /* 3079 * National chipset support functions 3080 */ 3081 int 3082 ata_national_ident(device_t dev) 3083 { 3084 struct ata_pci_controller *ctlr = device_get_softc(dev); 3085 3086 /* this chip is a clone of the Cyrix chip, bugs and all */ 3087 if (pci_get_devid(dev) == ATA_SC1100) { 3088 device_set_desc(dev, "National Geode SC1100 ATA33 controller"); 3089 ctlr->chipinit = ata_national_chipinit; 3090 return 0; 3091 } 3092 return ENXIO; 3093 } 3094 3095 static int 3096 ata_national_chipinit(device_t dev) 3097 { 3098 struct ata_pci_controller *ctlr = device_get_softc(dev); 3099 3100 if (ata_setup_interrupt(dev)) 3101 return ENXIO; 3102 3103 ctlr->setmode = ata_national_setmode; 3104 return 0; 3105 } 3106 3107 static void 3108 ata_national_setmode(device_t dev, int mode) 3109 { 3110 device_t gparent = GRANDPARENT(dev); 3111 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3112 struct ata_device *atadev = device_get_softc(dev); 3113 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3114 u_int32_t piotiming[] = 3115 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010, 3116 0x00803020, 0x20102010, 0x00100010, 3117 0x00100010, 0x00100010, 0x00100010 }; 3118 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 }; 3119 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 }; 3120 int error; 3121 3122 ch->dma->alignment = 16; 3123 ch->dma->max_iosize = 126 * DEV_BSIZE; 3124 3125 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 3126 3127 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3128 3129 if (bootverbose) 3130 device_printf(dev, "%s setting %s on National chip\n", 3131 (error) ? "failed" : "success", ata_mode2str(mode)); 3132 if (!error) { 3133 if (mode >= ATA_UDMA0) { 3134 pci_write_config(gparent, 0x44 + (devno << 3), 3135 udmatiming[mode & ATA_MODE_MASK], 4); 3136 } 3137 else if (mode >= ATA_WDMA0) { 3138 pci_write_config(gparent, 0x44 + (devno << 3), 3139 dmatiming[mode & ATA_MODE_MASK], 4); 3140 } 3141 else { 3142 pci_write_config(gparent, 0x44 + (devno << 3), 3143 pci_read_config(gparent, 0x44 + (devno << 3), 4) | 3144 0x80000000, 4); 3145 } 3146 pci_write_config(gparent, 0x40 + (devno << 3), 3147 piotiming[ata_mode2idx(mode)], 4); 3148 atadev->mode = mode; 3149 } 3150 } 3151 3152 /* 3153 * NetCell chipset support functions 3154 */ 3155 int 3156 ata_netcell_ident(device_t dev) 3157 { 3158 struct ata_pci_controller *ctlr = device_get_softc(dev); 3159 3160 if (pci_get_devid(dev) == ATA_NETCELL_SR) { 3161 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller"); 3162 ctlr->chipinit = ata_netcell_chipinit; 3163 return 0; 3164 } 3165 return ENXIO; 3166 } 3167 3168 static int 3169 ata_netcell_chipinit(device_t dev) 3170 { 3171 struct ata_pci_controller *ctlr = device_get_softc(dev); 3172 3173 if (ata_generic_chipinit(dev)) 3174 return ENXIO; 3175 3176 ctlr->allocate = ata_netcell_allocate; 3177 return 0; 3178 } 3179 3180 static int 3181 ata_netcell_allocate(device_t dev) 3182 { 3183 struct ata_channel *ch = device_get_softc(dev); 3184 3185 /* setup the usual register normal pci style */ 3186 if (ata_pci_allocate(dev)) 3187 return ENXIO; 3188 3189 /* the NetCell only supports 16 bit PIO transfers */ 3190 ch->flags |= ATA_USE_16BIT; 3191 3192 return 0; 3193 } 3194 3195 3196 /* 3197 * nVidia chipset support functions 3198 */ 3199 int 3200 ata_nvidia_ident(device_t dev) 3201 { 3202 struct ata_pci_controller *ctlr = device_get_softc(dev); 3203 struct ata_chip_id *idx; 3204 static struct ata_chip_id ids[] = 3205 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" }, 3206 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" }, 3207 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" }, 3208 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" }, 3209 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" }, 3210 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" }, 3211 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3212 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3213 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" }, 3214 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3215 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3216 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" }, 3217 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3218 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3219 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" }, 3220 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3221 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3222 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" }, 3223 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3224 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3225 { ATA_NFORCE_MCP61, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP61" }, 3226 { ATA_NFORCE_MCP61_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" }, 3227 { ATA_NFORCE_MCP61_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" }, 3228 { ATA_NFORCE_MCP61_S3, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" }, 3229 { ATA_NFORCE_MCP65, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP65" }, 3230 { ATA_NFORCE_MCP67, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP67" }, 3231 { ATA_NFORCE_MCP67_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP67" }, 3232 { ATA_NFORCE_MCP73, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP73" }, 3233 { ATA_NFORCE_MCP77, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP77" }, 3234 { 0, 0, 0, 0, 0, 0}} ; 3235 char buffer[64] ; 3236 3237 if (!(idx = ata_match_chip(dev, ids))) 3238 return ENXIO; 3239 3240 ksprintf(buffer, "nVidia %s %s controller", 3241 idx->text, ata_mode2str(idx->max_dma)); 3242 device_set_desc_copy(dev, buffer); 3243 ctlr->chip = idx; 3244 ctlr->chipinit = ata_nvidia_chipinit; 3245 return 0; 3246 } 3247 3248 static int 3249 ata_nvidia_chipinit(device_t dev) 3250 { 3251 struct ata_pci_controller *ctlr = device_get_softc(dev); 3252 3253 if (ata_setup_interrupt(dev)) 3254 return ENXIO; 3255 3256 if (ctlr->chip->max_dma >= ATA_SA150) { 3257 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1) 3258 ctlr->r_type2 = SYS_RES_IOPORT; 3259 else 3260 ctlr->r_type2 = SYS_RES_MEMORY; 3261 ctlr->r_rid2 = PCIR_BAR(5); 3262 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3263 &ctlr->r_rid2, RF_ACTIVE))) { 3264 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3265 3266 ctlr->allocate = ata_nvidia_allocate; 3267 ctlr->reset = ata_nvidia_reset; 3268 3269 /* enable control access */ 3270 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1); 3271 3272 if (ctlr->chip->cfg2 & NVQ) { 3273 /* clear interrupt status */ 3274 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff); 3275 3276 /* enable device and PHY state change interrupts */ 3277 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d); 3278 3279 /* disable NCQ support */ 3280 ATA_OUTL(ctlr->r_res2, 0x0400, 3281 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9); 3282 } 3283 else { 3284 /* clear interrupt status */ 3285 ATA_OUTB(ctlr->r_res2, offset, 0xff); 3286 3287 /* enable device and PHY state change interrupts */ 3288 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd); 3289 } 3290 3291 /* enable PCI interrupt */ 3292 pci_write_config(dev, PCIR_COMMAND, 3293 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 3294 3295 } 3296 ctlr->setmode = ata_sata_setmode; 3297 } 3298 else { 3299 /* disable prefetch, postwrite */ 3300 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1); 3301 ctlr->setmode = ata_via_family_setmode; 3302 } 3303 return 0; 3304 } 3305 3306 static int 3307 ata_nvidia_allocate(device_t dev) 3308 { 3309 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3310 struct ata_channel *ch = device_get_softc(dev); 3311 3312 /* setup the usual register normal pci style */ 3313 if (ata_pci_allocate(dev)) 3314 return ENXIO; 3315 3316 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3317 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6); 3318 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3319 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6); 3320 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3321 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6); 3322 3323 ch->hw.status = ata_nvidia_status; 3324 ch->flags |= ATA_NO_SLAVE; 3325 3326 return 0; 3327 } 3328 3329 static int 3330 ata_nvidia_status(device_t dev) 3331 { 3332 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3333 struct ata_channel *ch = device_get_softc(dev); 3334 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3335 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2); 3336 u_int32_t istatus; 3337 3338 /* get interrupt status */ 3339 if (ctlr->chip->cfg2 & NVQ) 3340 istatus = ATA_INL(ctlr->r_res2, offset); 3341 else 3342 istatus = ATA_INB(ctlr->r_res2, offset); 3343 3344 /* do we have any PHY events ? */ 3345 if (istatus & (0x0c << shift)) 3346 ata_sata_phy_check_events(dev); 3347 3348 /* clear interrupt(s) */ 3349 if (ctlr->chip->cfg2 & NVQ) 3350 ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0); 3351 else 3352 ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift)); 3353 3354 /* do we have any device action ? */ 3355 return (istatus & (0x01 << shift)); 3356 } 3357 3358 static void 3359 ata_nvidia_reset(device_t dev) 3360 { 3361 if (ata_sata_phy_reset(dev)) 3362 ata_generic_reset(dev); 3363 } 3364 3365 3366 /* 3367 * Promise chipset support functions 3368 */ 3369 #define ATA_PDC_APKT_OFFSET 0x00000010 3370 #define ATA_PDC_HPKT_OFFSET 0x00000040 3371 #define ATA_PDC_ASG_OFFSET 0x00000080 3372 #define ATA_PDC_LSG_OFFSET 0x000000c0 3373 #define ATA_PDC_HSG_OFFSET 0x00000100 3374 #define ATA_PDC_CHN_OFFSET 0x00000400 3375 #define ATA_PDC_BUF_BASE 0x00400000 3376 #define ATA_PDC_BUF_OFFSET 0x00100000 3377 #define ATA_PDC_MAX_HPKT 8 3378 #define ATA_PDC_WRITE_REG 0x00 3379 #define ATA_PDC_WRITE_CTL 0x0e 3380 #define ATA_PDC_WRITE_END 0x08 3381 #define ATA_PDC_WAIT_NBUSY 0x10 3382 #define ATA_PDC_WAIT_READY 0x18 3383 #define ATA_PDC_1B 0x20 3384 #define ATA_PDC_2B 0x40 3385 3386 struct host_packet { 3387 u_int32_t addr; 3388 TAILQ_ENTRY(host_packet) chain; 3389 }; 3390 3391 struct ata_promise_sx4 { 3392 struct spinlock mtx; 3393 TAILQ_HEAD(, host_packet) queue; 3394 int busy; 3395 }; 3396 3397 int 3398 ata_promise_ident(device_t dev) 3399 { 3400 struct ata_pci_controller *ctlr = device_get_softc(dev); 3401 struct ata_chip_id *idx; 3402 static struct ata_chip_id ids[] = 3403 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" }, 3404 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" }, 3405 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" }, 3406 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" }, 3407 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" }, 3408 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" }, 3409 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" }, 3410 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" }, 3411 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" }, 3412 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" }, 3413 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" }, 3414 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" }, 3415 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" }, 3416 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" }, 3417 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" }, 3418 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" }, 3419 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" }, 3420 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" }, 3421 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" }, 3422 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" }, 3423 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" }, 3424 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" }, 3425 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" }, 3426 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" }, 3427 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" }, 3428 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" }, 3429 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" }, 3430 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" }, 3431 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" }, 3432 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" }, 3433 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" }, 3434 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" }, 3435 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" }, 3436 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" }, 3437 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" }, 3438 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" }, 3439 { 0, 0, 0, 0, 0, 0}}; 3440 char buffer[64]; 3441 uintptr_t devid = 0; 3442 3443 if (!(idx = ata_match_chip(dev, ids))) 3444 return ENXIO; 3445 3446 /* if we are on a SuperTrak SX6000 dont attach */ 3447 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3448 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3449 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3450 devid == ATA_I960RM) 3451 return ENXIO; 3452 3453 strcpy(buffer, "Promise "); 3454 strcat(buffer, idx->text); 3455 3456 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 3457 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3458 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3459 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3460 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 3461 static long start = 0, end = 0; 3462 3463 if (pci_get_slot(dev) == 1) { 3464 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 3465 strcat(buffer, " (channel 0+1)"); 3466 } 3467 else if (pci_get_slot(dev) == 2 && start && end) { 3468 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end, 3469 machintr_legacy_intr_cpuid(start)); 3470 strcat(buffer, " (channel 2+3)"); 3471 } 3472 else { 3473 start = end = 0; 3474 } 3475 } 3476 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 3477 device_set_desc_copy(dev, buffer); 3478 ctlr->chip = idx; 3479 ctlr->chipinit = ata_promise_chipinit; 3480 return 0; 3481 } 3482 3483 static int 3484 ata_promise_chipinit(device_t dev) 3485 { 3486 struct ata_pci_controller *ctlr = device_get_softc(dev); 3487 int fake_reg, stat_reg; 3488 3489 if (ata_setup_interrupt(dev)) 3490 return ENXIO; 3491 3492 switch (ctlr->chip->cfg1) { 3493 case PRNEW: 3494 /* setup clocks */ 3495 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 3496 3497 ctlr->dmainit = ata_promise_dmainit; 3498 /* FALLTHROUGH */ 3499 3500 case PROLD: 3501 /* enable burst mode */ 3502 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 3503 ctlr->allocate = ata_promise_allocate; 3504 ctlr->setmode = ata_promise_setmode; 3505 return 0; 3506 3507 case PRTX: 3508 ctlr->allocate = ata_promise_tx2_allocate; 3509 ctlr->setmode = ata_promise_setmode; 3510 return 0; 3511 3512 case PRMIO: 3513 ctlr->r_type1 = SYS_RES_MEMORY; 3514 ctlr->r_rid1 = PCIR_BAR(4); 3515 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 3516 &ctlr->r_rid1, RF_ACTIVE))) 3517 goto failnfree; 3518 3519 ctlr->r_type2 = SYS_RES_MEMORY; 3520 ctlr->r_rid2 = PCIR_BAR(3); 3521 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3522 &ctlr->r_rid2, RF_ACTIVE))) 3523 goto failnfree; 3524 3525 if (ctlr->chip->cfg2 == PRSX4X) { 3526 struct ata_promise_sx4 *hpkt; 3527 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 3528 3529 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3530 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3531 ata_promise_sx4_intr, ctlr, &ctlr->handle, NULL)) { 3532 device_printf(dev, "unable to setup interrupt\n"); 3533 goto failnfree; 3534 } 3535 3536 /* print info about cache memory */ 3537 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 3538 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 3539 ((dimm >> 24) & 0xff), 3540 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 3541 " ECC enabled" : "" ); 3542 3543 /* adjust cache memory parameters */ 3544 ATA_OUTL(ctlr->r_res2, 0x000c000c, 3545 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 3546 3547 /* setup host packet controls */ 3548 hpkt = kmalloc(sizeof(struct ata_promise_sx4), 3549 M_TEMP, M_INTWAIT | M_ZERO); 3550 spin_init(&hpkt->mtx, "chipinit"); 3551 TAILQ_INIT(&hpkt->queue); 3552 hpkt->busy = 0; 3553 device_set_ivars(dev, hpkt); 3554 ctlr->allocate = ata_promise_mio_allocate; 3555 ctlr->reset = ata_promise_mio_reset; 3556 ctlr->dmainit = ata_promise_mio_dmainit; 3557 ctlr->setmode = ata_promise_setmode; 3558 ctlr->channels = 4; 3559 return 0; 3560 } 3561 3562 /* mio type controllers need an interrupt intercept */ 3563 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3564 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3565 ata_promise_mio_intr, ctlr, &ctlr->handle, NULL)) { 3566 device_printf(dev, "unable to setup interrupt\n"); 3567 goto failnfree; 3568 } 3569 3570 switch (ctlr->chip->cfg2) { 3571 case PRPATA: 3572 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 3573 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 3574 goto sata150; 3575 case PRCMBO: 3576 ctlr->channels = 3; 3577 goto sata150; 3578 case PRSATA: 3579 ctlr->channels = 4; 3580 sata150: 3581 fake_reg = 0x60; 3582 stat_reg = 0x6c; 3583 break; 3584 3585 case PRCMBO2: 3586 ctlr->channels = 3; 3587 goto sataii; 3588 case PRSATA2: 3589 default: 3590 ctlr->channels = 4; 3591 sataii: 3592 fake_reg = 0x54; 3593 stat_reg = 0x60; 3594 break; 3595 } 3596 3597 /* prime fake interrupt register */ 3598 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3599 3600 /* clear SATA status */ 3601 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 3602 3603 ctlr->allocate = ata_promise_mio_allocate; 3604 ctlr->reset = ata_promise_mio_reset; 3605 ctlr->dmainit = ata_promise_mio_dmainit; 3606 ctlr->setmode = ata_promise_mio_setmode; 3607 3608 return 0; 3609 } 3610 3611 failnfree: 3612 if (ctlr->r_res2) 3613 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 3614 if (ctlr->r_res1) 3615 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 3616 return ENXIO; 3617 } 3618 3619 static int 3620 ata_promise_allocate(device_t dev) 3621 { 3622 struct ata_channel *ch = device_get_softc(dev); 3623 3624 if (ata_pci_allocate(dev)) 3625 return ENXIO; 3626 3627 ch->hw.status = ata_promise_status; 3628 return 0; 3629 } 3630 3631 static int 3632 ata_promise_status(device_t dev) 3633 { 3634 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3635 struct ata_channel *ch = device_get_softc(dev); 3636 3637 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 3638 return ata_pci_status(dev); 3639 } 3640 return 0; 3641 } 3642 3643 static int 3644 ata_promise_dmastart(device_t dev) 3645 { 3646 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3647 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3648 struct ata_device *atadev = device_get_softc(dev); 3649 3650 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3651 ATA_OUTB(ctlr->r_res1, 0x11, 3652 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 3653 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 3654 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) | 3655 (ch->dma->cur_iosize >> 1)); 3656 } 3657 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 3658 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 3659 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus); 3660 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3661 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) | 3662 ATA_BMCMD_START_STOP); 3663 ch->flags |= ATA_DMA_ACTIVE; 3664 return 0; 3665 } 3666 3667 static int 3668 ata_promise_dmastop(device_t dev) 3669 { 3670 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3671 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3672 struct ata_device *atadev = device_get_softc(dev); 3673 int error; 3674 3675 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3676 ATA_OUTB(ctlr->r_res1, 0x11, 3677 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 3678 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 3679 } 3680 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 3681 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3682 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3683 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3684 ch->flags &= ~ATA_DMA_ACTIVE; 3685 return error; 3686 } 3687 3688 static void 3689 ata_promise_dmareset(device_t dev) 3690 { 3691 struct ata_channel *ch = device_get_softc(dev); 3692 3693 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3694 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3695 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3696 ch->flags &= ~ATA_DMA_ACTIVE; 3697 } 3698 3699 static void 3700 ata_promise_dmainit(device_t dev) 3701 { 3702 struct ata_channel *ch = device_get_softc(dev); 3703 3704 ata_dmainit(dev); 3705 if (ch->dma) { 3706 ch->dma->start = ata_promise_dmastart; 3707 ch->dma->stop = ata_promise_dmastop; 3708 ch->dma->reset = ata_promise_dmareset; 3709 } 3710 } 3711 3712 static void 3713 ata_promise_setmode(device_t dev, int mode) 3714 { 3715 device_t gparent = GRANDPARENT(dev); 3716 struct ata_pci_controller *ctlr = device_get_softc(gparent); 3717 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3718 struct ata_device *atadev = device_get_softc(dev); 3719 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3720 int error; 3721 u_int32_t timings[][2] = { 3722 /* PROLD PRNEW mode */ 3723 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 3724 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 3725 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 3726 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 3727 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 3728 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 3729 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 3730 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 3731 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 3732 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 3733 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 3734 { 0, 0x00424ef6 }, /* UDMA 3 */ 3735 { 0, 0x004127f3 }, /* UDMA 4 */ 3736 { 0, 0x004127f3 } /* UDMA 5 */ 3737 }; 3738 3739 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 3740 3741 switch (ctlr->chip->cfg1) { 3742 case PROLD: 3743 case PRNEW: 3744 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) & 3745 (ch->unit ? 1 << 11 : 1 << 10))) { 3746 ata_print_cable(dev, "controller"); 3747 mode = ATA_UDMA2; 3748 } 3749 if (ata_atapi(dev) && mode > ATA_PIO_MAX) 3750 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 3751 break; 3752 3753 case PRTX: 3754 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3755 if (mode > ATA_UDMA2 && 3756 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 3757 ata_print_cable(dev, "controller"); 3758 mode = ATA_UDMA2; 3759 } 3760 break; 3761 3762 case PRMIO: 3763 if (mode > ATA_UDMA2 && 3764 (ATA_INL(ctlr->r_res2, 3765 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) + 3766 (ch->unit << 7)) & 0x01000000)) { 3767 ata_print_cable(dev, "controller"); 3768 mode = ATA_UDMA2; 3769 } 3770 break; 3771 } 3772 3773 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3774 3775 if (bootverbose) 3776 device_printf(dev, "%ssetting %s on %s chip\n", 3777 (error) ? "FAILURE " : "", 3778 ata_mode2str(mode), ctlr->chip->text); 3779 if (!error) { 3780 if (ctlr->chip->cfg1 < PRTX) 3781 pci_write_config(gparent, 0x60 + (devno << 2), 3782 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 3783 atadev->mode = mode; 3784 } 3785 return; 3786 } 3787 3788 static int 3789 ata_promise_tx2_allocate(device_t dev) 3790 { 3791 struct ata_channel *ch = device_get_softc(dev); 3792 3793 if (ata_pci_allocate(dev)) 3794 return ENXIO; 3795 3796 ch->hw.status = ata_promise_tx2_status; 3797 return 0; 3798 } 3799 3800 static int 3801 ata_promise_tx2_status(device_t dev) 3802 { 3803 struct ata_channel *ch = device_get_softc(dev); 3804 3805 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3806 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 3807 return ata_pci_status(dev); 3808 } 3809 return 0; 3810 } 3811 3812 static int 3813 ata_promise_mio_allocate(device_t dev) 3814 { 3815 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3816 struct ata_channel *ch = device_get_softc(dev); 3817 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0; 3818 int i; 3819 3820 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 3821 ch->r_io[i].res = ctlr->r_res2; 3822 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 3823 } 3824 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 3825 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 3826 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 3827 ata_default_registers(dev); 3828 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) || 3829 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) { 3830 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3831 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 3832 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3833 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 3834 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3835 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 3836 ch->flags |= ATA_NO_SLAVE; 3837 } 3838 ch->flags |= ATA_USE_16BIT; 3839 3840 ata_generic_hw(dev); 3841 if (ctlr->chip->cfg2 & PRSX4X) { 3842 ch->hw.command = ata_promise_sx4_command; 3843 } 3844 else { 3845 ch->hw.command = ata_promise_mio_command; 3846 ch->hw.status = ata_promise_mio_status; 3847 } 3848 return 0; 3849 } 3850 3851 static void 3852 ata_promise_mio_intr(void *data) 3853 { 3854 struct ata_pci_controller *ctlr = data; 3855 struct ata_channel *ch; 3856 u_int32_t vector; 3857 int unit, fake_reg; 3858 3859 switch (ctlr->chip->cfg2) { 3860 case PRPATA: 3861 case PRCMBO: 3862 case PRSATA: 3863 fake_reg = 0x60; 3864 break; 3865 case PRCMBO2: 3866 case PRSATA2: 3867 default: 3868 fake_reg = 0x54; 3869 break; 3870 } 3871 3872 /* 3873 * since reading interrupt status register on early "mio" chips 3874 * clears the status bits we cannot read it for each channel later on 3875 * in the generic interrupt routine. 3876 * store the bits in an unused register in the chip so we can read 3877 * it from there safely to get around this "feature". 3878 */ 3879 vector = ATA_INL(ctlr->r_res2, 0x040); 3880 ATA_OUTL(ctlr->r_res2, 0x040, vector); 3881 ATA_OUTL(ctlr->r_res2, fake_reg, vector); 3882 3883 for (unit = 0; unit < ctlr->channels; unit++) { 3884 if ((ch = ctlr->interrupt[unit].argument)) 3885 ctlr->interrupt[unit].function(ch); 3886 } 3887 3888 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3889 } 3890 3891 static int 3892 ata_promise_mio_status(device_t dev) 3893 { 3894 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3895 struct ata_channel *ch = device_get_softc(dev); 3896 struct ata_connect_task *tp; 3897 u_int32_t fake_reg, stat_reg, vector, status; 3898 3899 switch (ctlr->chip->cfg2) { 3900 case PRPATA: 3901 case PRCMBO: 3902 case PRSATA: 3903 fake_reg = 0x60; 3904 stat_reg = 0x6c; 3905 break; 3906 case PRCMBO2: 3907 case PRSATA2: 3908 default: 3909 fake_reg = 0x54; 3910 stat_reg = 0x60; 3911 break; 3912 } 3913 3914 /* read and acknowledge interrupt */ 3915 vector = ATA_INL(ctlr->r_res2, fake_reg); 3916 3917 /* read and clear interface status */ 3918 status = ATA_INL(ctlr->r_res2, stat_reg); 3919 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 3920 3921 /* check for and handle disconnect events */ 3922 if ((status & (0x00000001 << ch->unit)) && 3923 (tp = (struct ata_connect_task *) 3924 kmalloc(sizeof(struct ata_connect_task), 3925 M_ATA, M_INTWAIT | M_ZERO))) { 3926 3927 if (bootverbose) 3928 device_printf(ch->dev, "DISCONNECT requested\n"); 3929 tp->action = ATA_C_DETACH; 3930 tp->dev = ch->dev; 3931 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3932 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3933 } 3934 3935 /* check for and handle connect events */ 3936 if ((status & (0x00000010 << ch->unit)) && 3937 (tp = (struct ata_connect_task *) 3938 kmalloc(sizeof(struct ata_connect_task), 3939 M_ATA, M_INTWAIT | M_ZERO))) { 3940 3941 if (bootverbose) 3942 device_printf(ch->dev, "CONNECT requested\n"); 3943 tp->action = ATA_C_ATTACH; 3944 tp->dev = ch->dev; 3945 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3946 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3947 } 3948 3949 /* do we have any device action ? */ 3950 return (vector & (1 << (ch->unit + 1))); 3951 } 3952 3953 static int 3954 ata_promise_mio_command(struct ata_request *request) 3955 { 3956 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 3957 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 3958 u_int32_t *wordp = (u_int32_t *)ch->dma->work; 3959 3960 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 3961 3962 /* XXX SOS add ATAPI commands support later */ 3963 switch (request->u.ata.command) { 3964 default: 3965 return ata_generic_command(request); 3966 3967 case ATA_READ_DMA: 3968 case ATA_READ_DMA48: 3969 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3970 break; 3971 3972 case ATA_WRITE_DMA: 3973 case ATA_WRITE_DMA48: 3974 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3975 break; 3976 } 3977 wordp[1] = htole32(ch->dma->sg_bus); 3978 wordp[2] = 0; 3979 ata_promise_apkt((u_int8_t*)wordp, request); 3980 3981 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus); 3982 return 0; 3983 } 3984 3985 static void 3986 ata_promise_mio_reset(device_t dev) 3987 { 3988 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3989 struct ata_channel *ch = device_get_softc(dev); 3990 struct ata_promise_sx4 *hpktp; 3991 3992 switch (ctlr->chip->cfg2) { 3993 case PRSX4X: 3994 3995 /* softreset channel ATA module */ 3996 hpktp = device_get_ivars(ctlr->dev); 3997 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 3998 ata_udelay(1000); 3999 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 4000 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 4001 ~0x00003f9f) | (ch->unit + 1)); 4002 4003 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 4004 spin_lock(&hpktp->mtx); 4005 ATA_OUTL(ctlr->r_res2, 0xc012c, 4006 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 4007 DELAY(10); 4008 ATA_OUTL(ctlr->r_res2, 0xc012c, 4009 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 4010 hpktp->busy = 0; 4011 spin_unlock(&hpktp->mtx); 4012 ata_generic_reset(dev); 4013 break; 4014 4015 case PRPATA: 4016 case PRCMBO: 4017 case PRSATA: 4018 if ((ctlr->chip->cfg2 == PRSATA) || 4019 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 4020 4021 /* mask plug/unplug intr */ 4022 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 4023 } 4024 4025 /* softreset channels ATA module */ 4026 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 4027 ata_udelay(10000); 4028 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 4029 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 4030 ~0x00003f9f) | (ch->unit + 1)); 4031 4032 if ((ctlr->chip->cfg2 == PRSATA) || 4033 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 4034 4035 if (ata_sata_phy_reset(dev)) 4036 ata_generic_reset(dev); 4037 4038 /* reset and enable plug/unplug intr */ 4039 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 4040 } 4041 else 4042 ata_generic_reset(dev); 4043 break; 4044 4045 case PRCMBO2: 4046 case PRSATA2: 4047 if ((ctlr->chip->cfg2 == PRSATA2) || 4048 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 4049 /* set portmultiplier port */ 4050 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 4051 4052 /* mask plug/unplug intr */ 4053 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 4054 } 4055 4056 /* softreset channels ATA module */ 4057 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 4058 ata_udelay(10000); 4059 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 4060 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 4061 ~0x00003f9f) | (ch->unit + 1)); 4062 4063 if ((ctlr->chip->cfg2 == PRSATA2) || 4064 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 4065 4066 /* set PHY mode to "improved" */ 4067 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 4068 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 4069 ~0x00000003) | 0x00000001); 4070 4071 if (ata_sata_phy_reset(dev)) 4072 ata_generic_reset(dev); 4073 4074 /* reset and enable plug/unplug intr */ 4075 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 4076 4077 /* set portmultiplier port */ 4078 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 4079 } 4080 else 4081 ata_generic_reset(dev); 4082 break; 4083 4084 } 4085 } 4086 4087 static void 4088 ata_promise_mio_dmainit(device_t dev) 4089 { 4090 /* note start and stop are not used here */ 4091 ata_dmainit(dev); 4092 } 4093 4094 static void 4095 ata_promise_mio_setmode(device_t dev, int mode) 4096 { 4097 device_t gparent = GRANDPARENT(dev); 4098 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4099 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4100 4101 if ( (ctlr->chip->cfg2 == PRSATA) || 4102 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) || 4103 (ctlr->chip->cfg2 == PRSATA2) || 4104 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) 4105 ata_sata_setmode(dev, mode); 4106 else 4107 ata_promise_setmode(dev, mode); 4108 } 4109 4110 static void 4111 ata_promise_sx4_intr(void *data) 4112 { 4113 struct ata_pci_controller *ctlr = data; 4114 struct ata_channel *ch; 4115 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 4116 int unit; 4117 4118 for (unit = 0; unit < ctlr->channels; unit++) { 4119 if (vector & (1 << (unit + 1))) 4120 if ((ch = ctlr->interrupt[unit].argument)) 4121 ctlr->interrupt[unit].function(ch); 4122 if (vector & (1 << (unit + 5))) 4123 if ((ch = ctlr->interrupt[unit].argument)) 4124 ata_promise_queue_hpkt(ctlr, 4125 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 4126 ATA_PDC_HPKT_OFFSET)); 4127 if (vector & (1 << (unit + 9))) { 4128 ata_promise_next_hpkt(ctlr); 4129 if ((ch = ctlr->interrupt[unit].argument)) 4130 ctlr->interrupt[unit].function(ch); 4131 } 4132 if (vector & (1 << (unit + 13))) { 4133 ata_promise_next_hpkt(ctlr); 4134 if ((ch = ctlr->interrupt[unit].argument)) 4135 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4136 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 4137 ATA_PDC_APKT_OFFSET)); 4138 } 4139 } 4140 } 4141 4142 static int 4143 ata_promise_sx4_command(struct ata_request *request) 4144 { 4145 device_t gparent = GRANDPARENT(request->dev); 4146 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4147 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4148 struct ata_dma_prdentry *prd = ch->dma->sg; 4149 caddr_t window = rman_get_virtual(ctlr->r_res1); 4150 u_int32_t *wordp; 4151 int i, idx, length = 0; 4152 4153 /* XXX SOS add ATAPI commands support later */ 4154 switch (request->u.ata.command) { 4155 4156 default: 4157 return -1; 4158 4159 case ATA_ATA_IDENTIFY: 4160 case ATA_READ: 4161 case ATA_READ48: 4162 case ATA_READ_MUL: 4163 case ATA_READ_MUL48: 4164 case ATA_WRITE: 4165 case ATA_WRITE48: 4166 case ATA_WRITE_MUL: 4167 case ATA_WRITE_MUL48: 4168 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4169 return ata_generic_command(request); 4170 4171 case ATA_SETFEATURES: 4172 case ATA_FLUSHCACHE: 4173 case ATA_FLUSHCACHE48: 4174 case ATA_SLEEP: 4175 case ATA_SET_MULTI: 4176 wordp = (u_int32_t *) 4177 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4178 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 4179 wordp[1] = 0; 4180 wordp[2] = 0; 4181 ata_promise_apkt((u_int8_t *)wordp, request); 4182 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4183 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4184 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4185 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 4186 return 0; 4187 4188 case ATA_READ_DMA: 4189 case ATA_READ_DMA48: 4190 case ATA_WRITE_DMA: 4191 case ATA_WRITE_DMA48: 4192 wordp = (u_int32_t *) 4193 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 4194 i = idx = 0; 4195 do { 4196 wordp[idx++] = prd[i].addr; 4197 wordp[idx++] = prd[i].count; 4198 length += (prd[i].count & ~ATA_DMA_EOT); 4199 } while (!(prd[i++].count & ATA_DMA_EOT)); 4200 4201 wordp = (u_int32_t *) 4202 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 4203 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4204 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4205 4206 wordp = (u_int32_t *) 4207 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 4208 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4209 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4210 4211 wordp = (u_int32_t *) 4212 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 4213 if (request->flags & ATA_R_READ) 4214 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 4215 if (request->flags & ATA_R_WRITE) 4216 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 4217 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 4218 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 4219 wordp[3] = 0; 4220 4221 wordp = (u_int32_t *) 4222 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4223 if (request->flags & ATA_R_READ) 4224 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 4225 if (request->flags & ATA_R_WRITE) 4226 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 4227 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 4228 wordp[2] = 0; 4229 ata_promise_apkt((u_int8_t *)wordp, request); 4230 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4231 4232 if (request->flags & ATA_R_READ) { 4233 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 4234 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 4235 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4236 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 4237 } 4238 if (request->flags & ATA_R_WRITE) { 4239 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 4240 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 4241 ata_promise_queue_hpkt(ctlr, 4242 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 4243 } 4244 return 0; 4245 } 4246 } 4247 4248 static int 4249 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 4250 { 4251 struct ata_device *atadev = device_get_softc(request->dev); 4252 int i = 12; 4253 4254 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 4255 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit; 4256 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 4257 bytep[i++] = ATA_A_4BIT; 4258 4259 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 4260 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4261 bytep[i++] = request->u.ata.feature >> 8; 4262 bytep[i++] = request->u.ata.feature; 4263 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 4264 bytep[i++] = request->u.ata.count >> 8; 4265 bytep[i++] = request->u.ata.count; 4266 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4267 bytep[i++] = request->u.ata.lba >> 24; 4268 bytep[i++] = request->u.ata.lba; 4269 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4270 bytep[i++] = request->u.ata.lba >> 32; 4271 bytep[i++] = request->u.ata.lba >> 8; 4272 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4273 bytep[i++] = request->u.ata.lba >> 40; 4274 bytep[i++] = request->u.ata.lba >> 16; 4275 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4276 bytep[i++] = ATA_D_LBA | atadev->unit; 4277 } 4278 else { 4279 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4280 bytep[i++] = request->u.ata.feature; 4281 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 4282 bytep[i++] = request->u.ata.count; 4283 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4284 bytep[i++] = request->u.ata.lba; 4285 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4286 bytep[i++] = request->u.ata.lba >> 8; 4287 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4288 bytep[i++] = request->u.ata.lba >> 16; 4289 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4290 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) | 4291 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf); 4292 } 4293 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 4294 bytep[i++] = request->u.ata.command; 4295 return i; 4296 } 4297 4298 static void 4299 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 4300 { 4301 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4302 4303 spin_lock(&hpktp->mtx); 4304 if (hpktp->busy) { 4305 struct host_packet *hp = 4306 kmalloc(sizeof(struct host_packet), M_TEMP, M_INTWAIT | M_ZERO); 4307 hp->addr = hpkt; 4308 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 4309 } 4310 else { 4311 hpktp->busy = 1; 4312 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 4313 } 4314 spin_unlock(&hpktp->mtx); 4315 } 4316 4317 static void 4318 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 4319 { 4320 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4321 struct host_packet *hp; 4322 4323 spin_lock(&hpktp->mtx); 4324 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 4325 TAILQ_REMOVE(&hpktp->queue, hp, chain); 4326 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 4327 kfree(hp, M_TEMP); 4328 } 4329 else 4330 hpktp->busy = 0; 4331 spin_unlock(&hpktp->mtx); 4332 } 4333 4334 4335 /* 4336 * ServerWorks chipset support functions 4337 */ 4338 int 4339 ata_serverworks_ident(device_t dev) 4340 { 4341 struct ata_pci_controller *ctlr = device_get_softc(dev); 4342 struct ata_chip_id *idx; 4343 static struct ata_chip_id ids[] = 4344 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" }, 4345 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" }, 4346 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" }, 4347 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" }, 4348 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" }, 4349 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" }, 4350 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" }, 4351 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" }, 4352 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" }, 4353 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" }, 4354 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" }, 4355 { 0, 0, 0, 0, 0, 0}}; 4356 char buffer[64]; 4357 4358 if (!(idx = ata_match_chip(dev, ids))) 4359 return ENXIO; 4360 4361 ksprintf(buffer, "ServerWorks %s %s controller", 4362 idx->text, ata_mode2str(idx->max_dma)); 4363 device_set_desc_copy(dev, buffer); 4364 ctlr->chip = idx; 4365 ctlr->chipinit = ata_serverworks_chipinit; 4366 return 0; 4367 } 4368 4369 static int 4370 ata_serverworks_chipinit(device_t dev) 4371 { 4372 struct ata_pci_controller *ctlr = device_get_softc(dev); 4373 4374 if (ata_setup_interrupt(dev)) 4375 return ENXIO; 4376 4377 if (ctlr->chip->cfg1 == SWKSMIO) { 4378 ctlr->r_type2 = SYS_RES_MEMORY; 4379 ctlr->r_rid2 = PCIR_BAR(5); 4380 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4381 &ctlr->r_rid2, RF_ACTIVE))){ 4382 ata_teardown_interrupt(dev); 4383 return ENXIO; 4384 } 4385 4386 ctlr->channels = ctlr->chip->cfg2; 4387 ctlr->allocate = ata_serverworks_allocate; 4388 ctlr->setmode = ata_sata_setmode; 4389 return 0; 4390 } 4391 else if (ctlr->chip->cfg1 == SWKS33) { 4392 device_t *children; 4393 int nchildren, i; 4394 4395 /* locate the ISA part in the southbridge and enable UDMA33 */ 4396 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 4397 for (i = 0; i < nchildren; i++) { 4398 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 4399 pci_write_config(children[i], 0x64, 4400 (pci_read_config(children[i], 0x64, 4) & 4401 ~0x00002000) | 0x00004000, 4); 4402 break; 4403 } 4404 } 4405 kfree(children, M_TEMP); 4406 } 4407 } 4408 else { 4409 pci_write_config(dev, 0x5a, 4410 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 4411 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1); 4412 } 4413 ctlr->setmode = ata_serverworks_setmode; 4414 return 0; 4415 } 4416 4417 static int 4418 ata_serverworks_allocate(device_t dev) 4419 { 4420 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4421 struct ata_channel *ch = device_get_softc(dev); 4422 int ch_offset; 4423 int i; 4424 4425 ch_offset = ch->unit * 0x100; 4426 4427 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 4428 ch->r_io[i].res = ctlr->r_res2; 4429 4430 /* setup ATA registers */ 4431 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 4432 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 4433 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 4434 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 4435 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 4436 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 4437 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 4438 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 4439 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 4440 ata_default_registers(dev); 4441 4442 /* setup DMA registers */ 4443 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 4444 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 4445 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 4446 4447 /* setup SATA registers */ 4448 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 4449 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 4450 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 4451 4452 ch->flags |= ATA_NO_SLAVE; 4453 ata_pci_hw(dev); 4454 4455 /* chip does not reliably do 64K DMA transfers */ 4456 if (ch->dma) 4457 ch->dma->max_iosize = 126 * DEV_BSIZE; 4458 4459 return 0; 4460 } 4461 4462 static void 4463 ata_serverworks_setmode(device_t dev, int mode) 4464 { 4465 device_t gparent = GRANDPARENT(dev); 4466 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4467 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4468 struct ata_device *atadev = device_get_softc(dev); 4469 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4470 int offset = (devno ^ 0x01) << 3; 4471 int error; 4472 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 4473 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 4474 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 4475 4476 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4477 4478 mode = ata_check_80pin(dev, mode); 4479 4480 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4481 4482 if (bootverbose) 4483 device_printf(dev, "%ssetting %s on %s chip\n", 4484 (error) ? "FAILURE " : "", 4485 ata_mode2str(mode), ctlr->chip->text); 4486 if (!error) { 4487 if (mode >= ATA_UDMA0) { 4488 pci_write_config(gparent, 0x56, 4489 (pci_read_config(gparent, 0x56, 2) & 4490 ~(0xf << (devno << 2))) | 4491 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 4492 pci_write_config(gparent, 0x54, 4493 pci_read_config(gparent, 0x54, 1) | 4494 (0x01 << devno), 1); 4495 pci_write_config(gparent, 0x44, 4496 (pci_read_config(gparent, 0x44, 4) & 4497 ~(0xff << offset)) | 4498 (dmatimings[2] << offset), 4); 4499 } 4500 else if (mode >= ATA_WDMA0) { 4501 pci_write_config(gparent, 0x54, 4502 pci_read_config(gparent, 0x54, 1) & 4503 ~(0x01 << devno), 1); 4504 pci_write_config(gparent, 0x44, 4505 (pci_read_config(gparent, 0x44, 4) & 4506 ~(0xff << offset)) | 4507 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 4508 } 4509 else 4510 pci_write_config(gparent, 0x54, 4511 pci_read_config(gparent, 0x54, 1) & 4512 ~(0x01 << devno), 1); 4513 4514 pci_write_config(gparent, 0x40, 4515 (pci_read_config(gparent, 0x40, 4) & 4516 ~(0xff << offset)) | 4517 (piotimings[ata_mode2idx(mode)] << offset), 4); 4518 atadev->mode = mode; 4519 } 4520 } 4521 4522 4523 /* 4524 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 4525 */ 4526 int 4527 ata_sii_ident(device_t dev) 4528 { 4529 struct ata_pci_controller *ctlr = device_get_softc(dev); 4530 struct ata_chip_id *idx; 4531 static struct ata_chip_id ids[] = 4532 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" }, 4533 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" }, 4534 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4535 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4536 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" }, 4537 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4538 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4539 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" }, 4540 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" }, 4541 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" }, 4542 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" }, 4543 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" }, 4544 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" }, 4545 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" }, 4546 { 0, 0, 0, 0, 0, 0}}; 4547 char buffer[64]; 4548 4549 if (!(idx = ata_match_chip(dev, ids))) 4550 return ENXIO; 4551 4552 ksprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); 4553 device_set_desc_copy(dev, buffer); 4554 ctlr->chip = idx; 4555 ctlr->chipinit = ata_sii_chipinit; 4556 return 0; 4557 } 4558 4559 static int 4560 ata_sii_chipinit(device_t dev) 4561 { 4562 struct ata_pci_controller *ctlr = device_get_softc(dev); 4563 4564 if (ata_setup_interrupt(dev)) 4565 return ENXIO; 4566 4567 switch (ctlr->chip->cfg1) { 4568 case SIIPRBIO: 4569 ctlr->r_type1 = SYS_RES_MEMORY; 4570 ctlr->r_rid1 = PCIR_BAR(0); 4571 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 4572 &ctlr->r_rid1, RF_ACTIVE))){ 4573 ata_teardown_interrupt(dev); 4574 return ENXIO; 4575 } 4576 4577 ctlr->r_rid2 = PCIR_BAR(2); 4578 ctlr->r_type2 = SYS_RES_MEMORY; 4579 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4580 &ctlr->r_rid2, RF_ACTIVE))){ 4581 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 4582 ata_teardown_interrupt(dev); 4583 return ENXIO; 4584 } 4585 ctlr->allocate = ata_siiprb_allocate; 4586 ctlr->reset = ata_siiprb_reset; 4587 ctlr->dmainit = ata_siiprb_dmainit; 4588 ctlr->setmode = ata_sata_setmode; 4589 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2; 4590 4591 /* reset controller */ 4592 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 4593 DELAY(10000); 4594 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 4595 4596 /* enable PCI interrupt */ 4597 pci_write_config(dev, PCIR_COMMAND, 4598 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 4599 break; 4600 4601 case SIIMEMIO: 4602 ctlr->r_type2 = SYS_RES_MEMORY; 4603 ctlr->r_rid2 = PCIR_BAR(5); 4604 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4605 &ctlr->r_rid2, RF_ACTIVE))){ 4606 ata_teardown_interrupt(dev); 4607 return ENXIO; 4608 } 4609 4610 if (ctlr->chip->cfg2 & SIISETCLK) { 4611 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4612 pci_write_config(dev, 0x8a, 4613 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 4614 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4615 device_printf(dev, "%s could not set ATA133 clock\n", 4616 ctlr->chip->text); 4617 } 4618 4619 /* if we have 4 channels enable the second set */ 4620 if (ctlr->chip->cfg2 & SII4CH) { 4621 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 4622 ctlr->channels = 4; 4623 } 4624 4625 /* dont block interrupts from any channel */ 4626 pci_write_config(dev, 0x48, 4627 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 4628 4629 /* enable PCI interrupt as BIOS might not */ 4630 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 4631 4632 ctlr->allocate = ata_sii_allocate; 4633 if (ctlr->chip->max_dma >= ATA_SA150) { 4634 ctlr->reset = ata_sii_reset; 4635 ctlr->setmode = ata_sata_setmode; 4636 } 4637 else 4638 ctlr->setmode = ata_sii_setmode; 4639 break; 4640 4641 default: 4642 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 4643 device_printf(dev, "HW has secondary channel disabled\n"); 4644 ctlr->channels = 1; 4645 } 4646 4647 /* enable interrupt as BIOS might not */ 4648 pci_write_config(dev, 0x71, 0x01, 1); 4649 4650 ctlr->allocate = ata_cmd_allocate; 4651 ctlr->setmode = ata_cmd_setmode; 4652 break; 4653 } 4654 return 0; 4655 } 4656 4657 static int 4658 ata_cmd_allocate(device_t dev) 4659 { 4660 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4661 struct ata_channel *ch = device_get_softc(dev); 4662 4663 /* setup the usual register normal pci style */ 4664 if (ata_pci_allocate(dev)) 4665 return ENXIO; 4666 4667 if (ctlr->chip->cfg2 & SIIINTR) 4668 ch->hw.status = ata_cmd_status; 4669 4670 return 0; 4671 } 4672 4673 static int 4674 ata_cmd_status(device_t dev) 4675 { 4676 struct ata_channel *ch = device_get_softc(dev); 4677 u_int8_t reg71; 4678 4679 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) & 4680 (ch->unit ? 0x08 : 0x04))) { 4681 pci_write_config(device_get_parent(ch->dev), 0x71, 4682 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 4683 return ata_pci_status(dev); 4684 } 4685 return 0; 4686 } 4687 4688 static void 4689 ata_cmd_setmode(device_t dev, int mode) 4690 { 4691 device_t gparent = GRANDPARENT(dev); 4692 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4693 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4694 struct ata_device *atadev = device_get_softc(dev); 4695 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4696 int error; 4697 4698 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4699 4700 mode = ata_check_80pin(dev, mode); 4701 4702 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4703 4704 if (bootverbose) 4705 device_printf(dev, "%ssetting %s on %s chip\n", 4706 (error) ? "FAILURE " : "", 4707 ata_mode2str(mode), ctlr->chip->text); 4708 if (!error) { 4709 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 4710 int ureg = ch->unit ? 0x7b : 0x73; 4711 4712 if (mode >= ATA_UDMA0) { 4713 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 4714 { 0x11, 0x42 }, { 0x25, 0x8a }, 4715 { 0x15, 0x4a }, { 0x05, 0x0a } }; 4716 4717 u_int8_t umode = pci_read_config(gparent, ureg, 1); 4718 4719 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca); 4720 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)]; 4721 pci_write_config(gparent, ureg, umode, 1); 4722 } 4723 else if (mode >= ATA_WDMA0) { 4724 int dmatimings[] = { 0x87, 0x32, 0x3f }; 4725 4726 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1); 4727 pci_write_config(gparent, ureg, 4728 pci_read_config(gparent, ureg, 1) & 4729 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4730 } 4731 else { 4732 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f }; 4733 pci_write_config(gparent, treg, 4734 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1); 4735 pci_write_config(gparent, ureg, 4736 pci_read_config(gparent, ureg, 1) & 4737 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4738 } 4739 atadev->mode = mode; 4740 } 4741 } 4742 4743 static int 4744 ata_sii_allocate(device_t dev) 4745 { 4746 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4747 struct ata_channel *ch = device_get_softc(dev); 4748 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 4749 int i; 4750 4751 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 4752 ch->r_io[i].res = ctlr->r_res2; 4753 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 4754 } 4755 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 4756 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 4757 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 4758 ata_default_registers(dev); 4759 4760 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 4761 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 4762 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 4763 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 4764 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 4765 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 4766 4767 if (ctlr->chip->max_dma >= ATA_SA150) { 4768 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4769 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 4770 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4771 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 4772 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4773 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 4774 ch->flags |= ATA_NO_SLAVE; 4775 4776 /* enable PHY state change interrupt */ 4777 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 4778 } 4779 4780 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) { 4781 /* work around errata in early chips */ 4782 ch->dma->boundary = 16 * DEV_BSIZE; 4783 ch->dma->segsize = 15 * DEV_BSIZE; 4784 } 4785 4786 ata_pci_hw(dev); 4787 ch->hw.status = ata_sii_status; 4788 return 0; 4789 } 4790 4791 static int 4792 ata_sii_status(device_t dev) 4793 { 4794 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4795 struct ata_channel *ch = device_get_softc(dev); 4796 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 4797 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 4798 4799 /* do we have any PHY events ? */ 4800 if (ctlr->chip->max_dma >= ATA_SA150 && 4801 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 4802 ata_sata_phy_check_events(dev); 4803 4804 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 4805 return ata_pci_status(dev); 4806 else 4807 return 0; 4808 } 4809 4810 static void 4811 ata_sii_reset(device_t dev) 4812 { 4813 if (ata_sata_phy_reset(dev)) 4814 ata_generic_reset(dev); 4815 } 4816 4817 static void 4818 ata_sii_setmode(device_t dev, int mode) 4819 { 4820 device_t gparent = GRANDPARENT(dev); 4821 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4822 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4823 struct ata_device *atadev = device_get_softc(dev); 4824 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1); 4825 int mreg = ch->unit ? 0x84 : 0x80; 4826 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2); 4827 int mval = pci_read_config(gparent, mreg, 1) & ~mask; 4828 int error; 4829 4830 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4831 4832 if (ctlr->chip->cfg2 & SIISETCLK) { 4833 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) & 4834 (ch->unit ? 0x02 : 0x01))) { 4835 ata_print_cable(dev, "controller"); 4836 mode = ATA_UDMA2; 4837 } 4838 } 4839 else 4840 mode = ata_check_80pin(dev, mode); 4841 4842 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4843 4844 if (bootverbose) 4845 device_printf(dev, "%ssetting %s on %s chip\n", 4846 (error) ? "FAILURE " : "", 4847 ata_mode2str(mode), ctlr->chip->text); 4848 if (error) 4849 return; 4850 4851 if (mode >= ATA_UDMA0) { 4852 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 4853 u_int8_t ureg = 0xac + rego; 4854 4855 pci_write_config(gparent, mreg, 4856 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1); 4857 pci_write_config(gparent, ureg, 4858 (pci_read_config(gparent, ureg, 1) & ~0x3f) | 4859 udmatimings[mode & ATA_MODE_MASK], 1); 4860 4861 } 4862 else if (mode >= ATA_WDMA0) { 4863 u_int8_t dreg = 0xa8 + rego; 4864 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 4865 4866 pci_write_config(gparent, mreg, 4867 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1); 4868 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 4869 4870 } 4871 else { 4872 u_int8_t preg = 0xa4 + rego; 4873 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 4874 4875 pci_write_config(gparent, mreg, 4876 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1); 4877 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2); 4878 } 4879 atadev->mode = mode; 4880 } 4881 4882 struct ata_siiprb_dma_prdentry { 4883 u_int64_t addr; 4884 u_int32_t count; 4885 u_int32_t control; 4886 } __packed; 4887 4888 struct ata_siiprb_ata_command { 4889 u_int32_t reserved0; 4890 struct ata_siiprb_dma_prdentry prd[126]; 4891 } __packed; 4892 4893 struct ata_siiprb_atapi_command { 4894 u_int8_t cdb[16]; 4895 struct ata_siiprb_dma_prdentry prd[125]; 4896 } __packed; 4897 4898 struct ata_siiprb_command { 4899 u_int16_t control; 4900 u_int16_t protocol_override; 4901 u_int32_t transfer_count; 4902 u_int8_t fis[20]; 4903 union { 4904 struct ata_siiprb_ata_command ata; 4905 struct ata_siiprb_atapi_command atapi; 4906 } u; 4907 } __packed; 4908 4909 static int 4910 ata_siiprb_allocate(device_t dev) 4911 { 4912 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4913 struct ata_channel *ch = device_get_softc(dev); 4914 int offset = ch->unit * 0x2000; 4915 4916 /* set the SATA resources */ 4917 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4918 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 4919 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4920 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 4921 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4922 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 4923 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 4924 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 4925 4926 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 4927 ch->hw.end_transaction = ata_siiprb_end_transaction; 4928 ch->hw.status = ata_siiprb_status; 4929 ch->hw.command = NULL; /* not used here */ 4930 return 0; 4931 } 4932 4933 static int 4934 ata_siiprb_status(device_t dev) 4935 { 4936 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4937 struct ata_channel *ch = device_get_softc(dev); 4938 int offset = ch->unit * 0x2000; 4939 4940 if ((ATA_INL(ctlr->r_res1, 0x0044) & (1 << ch->unit))) { 4941 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 4942 4943 /* do we have any PHY events ? */ 4944 ata_sata_phy_check_events(dev); 4945 4946 /* clear interrupt(s) */ 4947 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 4948 4949 /* do we have any device action ? */ 4950 return (istatus & 0x00000001); 4951 } 4952 return 0; 4953 } 4954 4955 static int 4956 ata_siiprb_begin_transaction(struct ata_request *request) 4957 { 4958 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 4959 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4960 struct ata_siiprb_command *prb; 4961 int offset = ch->unit * 0x2000; 4962 u_int64_t prb_bus; 4963 int tag = 0, dummy; 4964 4965 /* check for 48 bit access and convert if needed */ 4966 ata_modify_if_48bit(request); 4967 4968 /* get a piece of the workspace for this request */ 4969 prb = (struct ata_siiprb_command *) 4970 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 4971 4972 /* set basic prd options ata/atapi etc etc */ 4973 bzero(prb, sizeof(struct ata_siiprb_command)); 4974 4975 /* setup the FIS for this request */ 4976 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 4977 device_printf(request->dev, "setting up SATA FIS failed\n"); 4978 request->result = EIO; 4979 return ATA_OP_FINISHED; 4980 } 4981 4982 /* if request moves data setup and load SG list */ 4983 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 4984 struct ata_siiprb_dma_prdentry *prd; 4985 4986 if (request->flags & ATA_R_ATAPI) 4987 prd = &prb->u.atapi.prd[0]; 4988 else 4989 prd = &prb->u.ata.prd[0]; 4990 if (ch->dma->load(ch->dev, request->data, request->bytecount, 4991 request->flags & ATA_R_READ, prd, &dummy)) { 4992 device_printf(request->dev, "setting up DMA failed\n"); 4993 request->result = EIO; 4994 return ATA_OP_FINISHED; 4995 } 4996 } 4997 4998 /* activate the prb */ 4999 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 5000 ATA_OUTL(ctlr->r_res2, 5001 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 5002 ATA_OUTL(ctlr->r_res2, 5003 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 5004 5005 /* start the timeout */ 5006 callout_reset(&request->callout, request->timeout * hz, 5007 (timeout_t*)ata_timeout, request); 5008 return ATA_OP_CONTINUES; 5009 } 5010 5011 static int 5012 ata_siiprb_end_transaction(struct ata_request *request) 5013 { 5014 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 5015 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 5016 struct ata_siiprb_command *prb; 5017 int offset = ch->unit * 0x2000; 5018 int error, tag = 0; 5019 5020 /* kill the timeout */ 5021 callout_stop(&request->callout); 5022 5023 prb = (struct ata_siiprb_command *) 5024 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 5025 5026 /* if error status get details */ 5027 request->status = prb->fis[2]; 5028 if (request->status & ATA_S_ERROR) 5029 request->error = prb->fis[3]; 5030 5031 /* update progress */ 5032 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 5033 if (request->flags & ATA_R_READ) 5034 request->donecount = prb->transfer_count; 5035 else 5036 request->donecount = request->bytecount; 5037 } 5038 5039 /* any controller errors flagged ? */ 5040 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 5041 kprintf("ata_siiprb_end_transaction %s error=%08x\n", 5042 ata_cmd2str(request), error); 5043 } 5044 5045 /* release SG list etc */ 5046 ch->dma->unload(ch->dev); 5047 5048 return ATA_OP_FINISHED; 5049 } 5050 5051 static void 5052 ata_siiprb_reset(device_t dev) 5053 { 5054 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5055 struct ata_channel *ch = device_get_softc(dev); 5056 int offset = ch->unit * 0x2000; 5057 struct ata_siiprb_command *prb; 5058 u_int64_t prb_bus; 5059 u_int32_t status, signature; 5060 int timeout, tag = 0; 5061 5062 /* reset channel HW */ 5063 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 5064 DELAY(1000); 5065 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 5066 DELAY(10000); 5067 5068 /* poll for channel ready */ 5069 for (timeout = 0; timeout < 1000; timeout++) { 5070 if ((status = ATA_INL(ctlr->r_res2, 0x1000 + offset)) & 0x00040000) 5071 break; 5072 DELAY(1000); 5073 } 5074 if (timeout >= 1000) { 5075 device_printf(ch->dev, "channel HW reset timeout reset failure\n"); 5076 ch->devices = 0; 5077 goto finish; 5078 } 5079 if (bootverbose) 5080 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout * 1); 5081 5082 /* reset phy */ 5083 if (!ata_sata_phy_reset(dev)) { 5084 if (bootverbose) 5085 device_printf(ch->dev, "phy reset found no device\n"); 5086 ch->devices = 0; 5087 goto finish; 5088 } 5089 5090 /* get a piece of the workspace for a soft reset request */ 5091 prb = (struct ata_siiprb_command *) 5092 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 5093 bzero(prb, sizeof(struct ata_siiprb_command)); 5094 prb->control = htole16(0x0080); 5095 5096 /* activate the soft reset prb */ 5097 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 5098 ATA_OUTL(ctlr->r_res2, 5099 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 5100 ATA_OUTL(ctlr->r_res2, 5101 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 5102 5103 /* poll for channel ready */ 5104 for (timeout = 0; timeout < 1000; timeout++) { 5105 DELAY(1000); 5106 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 5107 break; 5108 } 5109 if (timeout >= 1000) { 5110 device_printf(ch->dev, "reset timeout - no device found\n"); 5111 ch->devices = 0; 5112 goto finish; 5113 } 5114 if (bootverbose) 5115 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n", 5116 timeout, status); 5117 5118 /* find out whats there */ 5119 prb = (struct ata_siiprb_command *) 5120 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 5121 signature = 5122 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 5123 if (bootverbose) 5124 device_printf(ch->dev, "signature=%08x\n", signature); 5125 switch (signature) { 5126 case 0xeb140101: 5127 ch->devices = ATA_ATAPI_MASTER; 5128 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n"); 5129 ch->devices = 0; 5130 break; 5131 case 0x96690101: 5132 ch->devices = ATA_PORTMULTIPLIER; 5133 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 5134 ch->devices = 0; 5135 break; 5136 case 0x00000101: 5137 ch->devices = ATA_ATA_MASTER; 5138 break; 5139 default: 5140 ch->devices = 0; 5141 } 5142 5143 finish: 5144 /* clear interrupt(s) */ 5145 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 5146 5147 /* require explicit interrupt ack */ 5148 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 5149 5150 /* 64bit mode */ 5151 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 5152 5153 /* enable interrupts wanted */ 5154 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 5155 } 5156 5157 static void 5158 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 5159 { 5160 struct ata_dmasetprd_args *args = xsc; 5161 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 5162 int i; 5163 5164 if ((args->error = error)) 5165 return; 5166 5167 for (i = 0; i < nsegs; i++) { 5168 prd[i].addr = htole64(segs[i].ds_addr); 5169 prd[i].count = htole32(segs[i].ds_len); 5170 } 5171 prd[i - 1].control = htole32(ATA_DMA_EOT); 5172 } 5173 5174 static void 5175 ata_siiprb_dmainit(device_t dev) 5176 { 5177 struct ata_channel *ch = device_get_softc(dev); 5178 5179 ata_dmainit(dev); 5180 if (ch->dma) { 5181 /* note start and stop are not used here */ 5182 ch->dma->setprd = ata_siiprb_dmasetprd; 5183 ch->dma->max_address = BUS_SPACE_MAXADDR; 5184 } 5185 } 5186 5187 5188 /* 5189 * Silicon Integrated Systems Corp. (SiS) chipset support functions 5190 */ 5191 int 5192 ata_sis_ident(device_t dev) 5193 { 5194 struct ata_pci_controller *ctlr = device_get_softc(dev); 5195 struct ata_chip_id *idx; 5196 static struct ata_chip_id ids[] = 5197 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */ 5198 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */ 5199 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */ 5200 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */ 5201 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */ 5202 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */ 5203 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */ 5204 5205 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */ 5206 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */ 5207 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */ 5208 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */ 5209 5210 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */ 5211 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */ 5212 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */ 5213 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */ 5214 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */ 5215 5216 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" }, 5217 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" }, 5218 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" }, 5219 5220 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" }, 5221 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" }, 5222 { 0, 0, 0, 0, 0, 0 }}; 5223 char buffer[64]; 5224 int found = 0; 5225 5226 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev)))) 5227 return ENXIO; 5228 5229 if (idx->cfg2 && !found) { 5230 u_int8_t reg57 = pci_read_config(dev, 0x57, 1); 5231 5232 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1); 5233 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) { 5234 found = 1; 5235 idx->cfg1 = SIS133NEW; 5236 idx->max_dma = ATA_UDMA6; 5237 ksprintf(buffer, "SiS 962/963 %s controller", 5238 ata_mode2str(idx->max_dma)); 5239 } 5240 pci_write_config(dev, 0x57, reg57, 1); 5241 } 5242 if (idx->cfg2 && !found) { 5243 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1); 5244 5245 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1); 5246 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) { 5247 struct ata_chip_id id[] = 5248 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }}; 5249 5250 found = 1; 5251 if (ata_find_chip(dev, id, pci_get_slot(dev))) { 5252 idx->cfg1 = SIS133OLD; 5253 idx->max_dma = ATA_UDMA6; 5254 } 5255 else { 5256 idx->cfg1 = SIS100NEW; 5257 idx->max_dma = ATA_UDMA5; 5258 } 5259 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma)); 5260 } 5261 pci_write_config(dev, 0x4a, reg4a, 1); 5262 } 5263 if (!found) 5264 ksprintf(buffer,"SiS %s %s controller", 5265 idx->text, ata_mode2str(idx->max_dma)); 5266 5267 device_set_desc_copy(dev, buffer); 5268 ctlr->chip = idx; 5269 ctlr->chipinit = ata_sis_chipinit; 5270 return 0; 5271 } 5272 5273 static int 5274 ata_sis_chipinit(device_t dev) 5275 { 5276 struct ata_pci_controller *ctlr = device_get_softc(dev); 5277 5278 if (ata_setup_interrupt(dev)) 5279 return ENXIO; 5280 5281 switch (ctlr->chip->cfg1) { 5282 case SIS33: 5283 break; 5284 case SIS66: 5285 case SIS100OLD: 5286 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1); 5287 break; 5288 case SIS100NEW: 5289 case SIS133OLD: 5290 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1); 5291 break; 5292 case SIS133NEW: 5293 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2); 5294 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2); 5295 break; 5296 case SISSATA: 5297 ctlr->r_type2 = SYS_RES_IOPORT; 5298 ctlr->r_rid2 = PCIR_BAR(5); 5299 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5300 &ctlr->r_rid2, RF_ACTIVE))) { 5301 ctlr->allocate = ata_sis_allocate; 5302 ctlr->reset = ata_sis_reset; 5303 5304 /* enable PCI interrupt */ 5305 pci_write_config(dev, PCIR_COMMAND, 5306 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5307 } 5308 ctlr->setmode = ata_sata_setmode; 5309 return 0; 5310 default: 5311 ata_teardown_interrupt(dev); 5312 return ENXIO; 5313 } 5314 ctlr->setmode = ata_sis_setmode; 5315 return 0; 5316 } 5317 5318 static int 5319 ata_sis_allocate(device_t dev) 5320 { 5321 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5322 struct ata_channel *ch = device_get_softc(dev); 5323 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6); 5324 5325 /* setup the usual register normal pci style */ 5326 if (ata_pci_allocate(dev)) 5327 return ENXIO; 5328 5329 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5330 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; 5331 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5332 ch->r_io[ATA_SERROR].offset = 0x04 + offset; 5333 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5334 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; 5335 ch->flags |= ATA_NO_SLAVE; 5336 5337 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ 5338 /* XXX SOS unknown how to enable PHY state change interrupt */ 5339 return 0; 5340 } 5341 5342 static void 5343 ata_sis_reset(device_t dev) 5344 { 5345 if (ata_sata_phy_reset(dev)) 5346 ata_generic_reset(dev); 5347 } 5348 5349 static void 5350 ata_sis_setmode(device_t dev, int mode) 5351 { 5352 device_t gparent = GRANDPARENT(dev); 5353 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5354 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5355 struct ata_device *atadev = device_get_softc(dev); 5356 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5357 int error; 5358 5359 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5360 5361 if (ctlr->chip->cfg1 == SIS133NEW) { 5362 if (mode > ATA_UDMA2 && 5363 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) { 5364 ata_print_cable(dev, "controller"); 5365 mode = ATA_UDMA2; 5366 } 5367 } 5368 else { 5369 if (mode > ATA_UDMA2 && 5370 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) { 5371 ata_print_cable(dev, "controller"); 5372 mode = ATA_UDMA2; 5373 } 5374 } 5375 5376 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5377 5378 if (bootverbose) 5379 device_printf(dev, "%ssetting %s on %s chip\n", 5380 (error) ? "FAILURE " : "", 5381 ata_mode2str(mode), ctlr->chip->text); 5382 if (!error) { 5383 switch (ctlr->chip->cfg1) { 5384 case SIS133NEW: { 5385 u_int32_t timings[] = 5386 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 5387 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 5388 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; 5389 u_int32_t reg; 5390 5391 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); 5392 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4); 5393 break; 5394 } 5395 case SIS133OLD: { 5396 u_int16_t timings[] = 5397 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 5398 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; 5399 5400 u_int16_t reg = 0x40 + (devno << 1); 5401 5402 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5403 break; 5404 } 5405 case SIS100NEW: { 5406 u_int16_t timings[] = 5407 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 5408 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; 5409 u_int16_t reg = 0x40 + (devno << 1); 5410 5411 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5412 break; 5413 } 5414 case SIS100OLD: 5415 case SIS66: 5416 case SIS33: { 5417 u_int16_t timings[] = 5418 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 5419 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; 5420 u_int16_t reg = 0x40 + (devno << 1); 5421 5422 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5423 break; 5424 } 5425 } 5426 atadev->mode = mode; 5427 } 5428 } 5429 5430 5431 /* VIA Technologies Inc. chipset support functions */ 5432 int 5433 ata_via_ident(device_t dev) 5434 { 5435 struct ata_pci_controller *ctlr = device_get_softc(dev); 5436 struct ata_chip_id *idx; 5437 static struct ata_chip_id ids[] = 5438 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 5439 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 5440 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 5441 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 5442 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 5443 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 5444 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 5445 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 5446 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 5447 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 5448 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 5449 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 5450 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 5451 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 5452 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 5453 { 0, 0, 0, 0, 0, 0 }}; 5454 static struct ata_chip_id new_ids[] = 5455 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 5456 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 5457 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 5458 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 5459 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" }, 5460 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" }, 5461 { 0, 0, 0, 0, 0, 0 }}; 5462 char buffer[64]; 5463 5464 if (pci_get_devid(dev) == ATA_VIA82C571) { 5465 if (!(idx = ata_find_chip(dev, ids, -99))) 5466 return ENXIO; 5467 } 5468 else { 5469 if (!(idx = ata_match_chip(dev, new_ids))) 5470 return ENXIO; 5471 } 5472 5473 ksprintf(buffer, "VIA %s %s controller", 5474 idx->text, ata_mode2str(idx->max_dma)); 5475 device_set_desc_copy(dev, buffer); 5476 ctlr->chip = idx; 5477 ctlr->chipinit = ata_via_chipinit; 5478 return 0; 5479 } 5480 5481 static int 5482 ata_via_chipinit(device_t dev) 5483 { 5484 struct ata_pci_controller *ctlr = device_get_softc(dev); 5485 5486 if (ata_setup_interrupt(dev)) 5487 return ENXIO; 5488 5489 if (ctlr->chip->max_dma >= ATA_SA150) { 5490 /* do we have AHCI capability ? */ 5491 if ((ctlr->chip->cfg2 == VIAAHCI) && ata_ahci_chipinit(dev) != ENXIO) 5492 return 0; 5493 5494 ctlr->r_type2 = SYS_RES_IOPORT; 5495 ctlr->r_rid2 = PCIR_BAR(5); 5496 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5497 &ctlr->r_rid2, RF_ACTIVE))) { 5498 ctlr->allocate = ata_via_allocate; 5499 ctlr->reset = ata_via_reset; 5500 5501 /* enable PCI interrupt */ 5502 pci_write_config(dev, PCIR_COMMAND, 5503 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5504 } 5505 5506 if (ctlr->chip->cfg2 & VIABAR) { 5507 ctlr->channels = 3; 5508 ctlr->setmode = ata_via_setmode; 5509 } 5510 else 5511 ctlr->setmode = ata_sata_setmode; 5512 return 0; 5513 } 5514 5515 /* prepare for ATA-66 on the 82C686a and 82C596b */ 5516 if (ctlr->chip->cfg2 & VIACLK) 5517 pci_write_config(dev, 0x50, 0x030b030b, 4); 5518 5519 /* the southbridge might need the data corruption fix */ 5520 if (ctlr->chip->cfg2 & VIABUG) 5521 ata_via_southbridge_fixup(dev); 5522 5523 /* set fifo configuration half'n'half */ 5524 pci_write_config(dev, 0x43, 5525 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 5526 5527 /* set status register read retry */ 5528 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 5529 5530 /* set DMA read & end-of-sector fifo flush */ 5531 pci_write_config(dev, 0x46, 5532 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 5533 5534 /* set sector size */ 5535 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 5536 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 5537 5538 ctlr->setmode = ata_via_family_setmode; 5539 return 0; 5540 } 5541 5542 static int 5543 ata_via_allocate(device_t dev) 5544 { 5545 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5546 struct ata_channel *ch = device_get_softc(dev); 5547 5548 /* newer SATA chips has resources in one BAR for each channel */ 5549 if (ctlr->chip->cfg2 & VIABAR) { 5550 struct resource *r_io; 5551 int i, rid; 5552 5553 rid = PCIR_BAR(ch->unit); 5554 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 5555 SYS_RES_IOPORT, 5556 &rid, RF_ACTIVE))) 5557 return ENXIO; 5558 5559 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 5560 ch->r_io[i].res = r_io; 5561 ch->r_io[i].offset = i; 5562 } 5563 ch->r_io[ATA_CONTROL].res = r_io; 5564 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 5565 ch->r_io[ATA_IDX_ADDR].res = r_io; 5566 ata_default_registers(dev); 5567 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 5568 ch->r_io[i].res = ctlr->r_res1; 5569 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 5570 } 5571 ata_pci_hw(dev); 5572 if (ch->unit >= 2) 5573 return 0; 5574 } 5575 else { 5576 /* setup the usual register normal pci style */ 5577 if (ata_pci_allocate(dev)) 5578 return ENXIO; 5579 } 5580 5581 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5582 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 5583 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5584 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 5585 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5586 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 5587 ch->flags |= ATA_NO_SLAVE; 5588 5589 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */ 5590 /* XXX SOS unknown how to enable PHY state change interrupt */ 5591 return 0; 5592 } 5593 5594 static void 5595 ata_via_reset(device_t dev) 5596 { 5597 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5598 struct ata_channel *ch = device_get_softc(dev); 5599 5600 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 5601 ata_generic_reset(dev); 5602 else 5603 if (ata_sata_phy_reset(dev)) 5604 ata_generic_reset(dev); 5605 } 5606 5607 static void 5608 ata_via_setmode(device_t dev, int mode) 5609 { 5610 device_t gparent = GRANDPARENT(dev); 5611 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5612 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5613 struct ata_device *atadev = device_get_softc(dev); 5614 int error; 5615 5616 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 5617 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20, 5618 0x65, 0x32, 0x20, 5619 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5620 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 5621 5622 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6)); 5623 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5624 if (bootverbose) 5625 device_printf(dev, "%ssetting %s on %s chip\n", 5626 (error) ? "FAILURE " : "", ata_mode2str(mode), 5627 ctlr->chip->text); 5628 if (!error) { 5629 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1); 5630 if (mode >= ATA_UDMA0) 5631 pci_write_config(gparent, 0xb3, 5632 dma_timings[mode & ATA_MODE_MASK], 1); 5633 atadev->mode = mode; 5634 } 5635 } 5636 else 5637 ata_sata_setmode(dev, mode); 5638 } 5639 5640 static void 5641 ata_via_southbridge_fixup(device_t dev) 5642 { 5643 device_t *children; 5644 int nchildren, i; 5645 5646 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5647 return; 5648 5649 for (i = 0; i < nchildren; i++) { 5650 if (pci_get_devid(children[i]) == ATA_VIA8363 || 5651 pci_get_devid(children[i]) == ATA_VIA8371 || 5652 pci_get_devid(children[i]) == ATA_VIA8662 || 5653 pci_get_devid(children[i]) == ATA_VIA8361) { 5654 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 5655 5656 if ((reg76 & 0xf0) != 0xd0) { 5657 device_printf(dev, 5658 "Correcting VIA config for southbridge data corruption bug\n"); 5659 pci_write_config(children[i], 0x75, 0x80, 1); 5660 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 5661 } 5662 break; 5663 } 5664 } 5665 kfree(children, M_TEMP); 5666 } 5667 5668 5669 /* common code for VIA, AMD & nVidia */ 5670 static void 5671 ata_via_family_setmode(device_t dev, int mode) 5672 { 5673 device_t gparent = GRANDPARENT(dev); 5674 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5675 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5676 struct ata_device *atadev = device_get_softc(dev); 5677 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20, 5678 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5679 int modes[][7] = { 5680 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 5681 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 5682 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 5683 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */ 5684 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */ 5685 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5686 int reg = 0x53 - devno; 5687 int error; 5688 5689 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5690 5691 if (ctlr->chip->cfg2 & AMDCABLE) { 5692 if (mode > ATA_UDMA2 && 5693 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) { 5694 ata_print_cable(dev, "controller"); 5695 mode = ATA_UDMA2; 5696 } 5697 } 5698 else 5699 mode = ata_check_80pin(dev, mode); 5700 5701 if (ctlr->chip->cfg2 & NVIDIA) 5702 reg += 0x10; 5703 5704 if (ctlr->chip->cfg1 != VIA133) 5705 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1); 5706 5707 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5708 5709 if (bootverbose) 5710 device_printf(dev, "%ssetting %s on %s chip\n", 5711 (error) ? "FAILURE " : "", ata_mode2str(mode), 5712 ctlr->chip->text); 5713 if (!error) { 5714 if (mode >= ATA_UDMA0) 5715 pci_write_config(gparent, reg, 5716 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 5717 else 5718 pci_write_config(gparent, reg, 0x8b, 1); 5719 atadev->mode = mode; 5720 } 5721 } 5722 5723 5724 /* misc functions */ 5725 static struct ata_chip_id * 5726 ata_match_chip(device_t dev, struct ata_chip_id *index) 5727 { 5728 while (index->chipid != 0) { 5729 if (pci_get_devid(dev) == index->chipid && 5730 pci_get_revid(dev) >= index->chiprev) 5731 return index; 5732 index++; 5733 } 5734 return NULL; 5735 } 5736 5737 static struct ata_chip_id * 5738 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot) 5739 { 5740 device_t *children; 5741 int nchildren, i; 5742 5743 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5744 return 0; 5745 5746 while (index->chipid != 0) { 5747 for (i = 0; i < nchildren; i++) { 5748 if (((slot >= 0 && pci_get_slot(children[i]) == slot) || 5749 (slot < 0 && pci_get_slot(children[i]) <= -slot)) && 5750 pci_get_devid(children[i]) == index->chipid && 5751 pci_get_revid(children[i]) >= index->chiprev) { 5752 kfree(children, M_TEMP); 5753 return index; 5754 } 5755 } 5756 index++; 5757 } 5758 kfree(children, M_TEMP); 5759 return NULL; 5760 } 5761 5762 static int 5763 ata_setup_interrupt(device_t dev) 5764 { 5765 struct ata_pci_controller *ctlr = device_get_softc(dev); 5766 int rid = ATA_IRQ_RID; 5767 5768 if (!ctlr->legacy) { 5769 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 5770 RF_SHAREABLE | RF_ACTIVE))) { 5771 device_printf(dev, "unable to map interrupt\n"); 5772 return ENXIO; 5773 } 5774 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 5775 ata_generic_intr, ctlr, &ctlr->handle, NULL))) { 5776 device_printf(dev, "unable to setup interrupt\n"); 5777 bus_release_resource(dev, SYS_RES_IRQ, rid, ctlr->r_irq); 5778 ctlr->r_irq = 0; 5779 return ENXIO; 5780 } 5781 } 5782 return 0; 5783 } 5784 5785 static void 5786 ata_teardown_interrupt(device_t dev) 5787 { 5788 struct ata_pci_controller *ctlr = device_get_softc(dev); 5789 5790 if (!ctlr->legacy) { 5791 if (ctlr->r_irq) { 5792 bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle); 5793 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ctlr->r_irq); 5794 ctlr->r_irq = 0; 5795 } 5796 } 5797 } 5798 5799 struct ata_serialize { 5800 struct spinlock locked_mtx; 5801 int locked_ch; 5802 int restart_ch; 5803 }; 5804 5805 static int 5806 ata_serialize(device_t dev, int flags) 5807 { 5808 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5809 struct ata_channel *ch = device_get_softc(dev); 5810 struct ata_serialize *serial; 5811 static int inited = 0; 5812 int res; 5813 5814 if (!inited) { 5815 serial = kmalloc(sizeof(struct ata_serialize), 5816 M_TEMP, M_INTWAIT | M_ZERO); 5817 spin_init(&serial->locked_mtx, "ataserialize"); 5818 serial->locked_ch = -1; 5819 serial->restart_ch = -1; 5820 device_set_ivars(ctlr->dev, serial); 5821 inited = 1; 5822 } 5823 else 5824 serial = device_get_ivars(ctlr->dev); 5825 5826 spin_lock(&serial->locked_mtx); 5827 switch (flags) { 5828 case ATA_LF_LOCK: 5829 if (serial->locked_ch == -1) 5830 serial->locked_ch = ch->unit; 5831 if (serial->locked_ch != ch->unit) 5832 serial->restart_ch = ch->unit; 5833 break; 5834 5835 case ATA_LF_UNLOCK: 5836 if (serial->locked_ch == ch->unit) { 5837 serial->locked_ch = -1; 5838 if (serial->restart_ch != -1) { 5839 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) { 5840 serial->restart_ch = -1; 5841 spin_unlock(&serial->locked_mtx); 5842 ata_start(ch->dev); 5843 return -1; 5844 } 5845 } 5846 } 5847 break; 5848 5849 case ATA_LF_WHICH: 5850 break; 5851 } 5852 res = serial->locked_ch; 5853 spin_unlock(&serial->locked_mtx); 5854 return res; 5855 } 5856 5857 static void 5858 ata_print_cable(device_t dev, u_int8_t *who) 5859 { 5860 device_printf(dev, 5861 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who); 5862 } 5863 5864 static int 5865 ata_atapi(device_t dev) 5866 { 5867 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5868 struct ata_device *atadev = device_get_softc(dev); 5869 5870 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || 5871 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE)); 5872 } 5873 5874 static int 5875 ata_check_80pin(device_t dev, int mode) 5876 { 5877 struct ata_device *atadev = device_get_softc(dev); 5878 5879 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) { 5880 ata_print_cable(dev, "device"); 5881 mode = ATA_UDMA2; 5882 } 5883 return mode; 5884 } 5885 5886 static int 5887 ata_mode2idx(int mode) 5888 { 5889 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) 5890 return (mode & ATA_MODE_MASK) + 8; 5891 if ((mode & ATA_DMA_MASK) == ATA_WDMA0) 5892 return (mode & ATA_MODE_MASK) + 5; 5893 return (mode & ATA_MODE_MASK) - ATA_PIO0; 5894 } 5895