1 /*- 2 * Copyright (c) 1998 - 2006 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/ata/ata-lowlevel.c,v 1.77 2006/07/04 20:36:03 sos Exp $ 27 * $DragonFly: src/sys/dev/disk/nata/ata-lowlevel.c,v 1.2 2006/12/22 23:26:16 swildner Exp $ 28 */ 29 30 #include "opt_ata.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/callout.h> 35 #include <sys/libkern.h> 36 #include <sys/nata.h> 37 #include <sys/systm.h> 38 39 #include "ata-all.h" 40 #include "ata_if.h" 41 42 /* prototypes */ 43 static int ata_generic_status(device_t dev); 44 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t); 45 static void ata_pio_read(struct ata_request *, int); 46 static void ata_pio_write(struct ata_request *, int); 47 48 /* 49 * low level ATA functions 50 */ 51 void 52 ata_generic_hw(device_t dev) 53 { 54 struct ata_channel *ch = device_get_softc(dev); 55 56 ch->hw.begin_transaction = ata_begin_transaction; 57 ch->hw.end_transaction = ata_end_transaction; 58 ch->hw.status = ata_generic_status; 59 ch->hw.command = ata_generic_command; 60 } 61 62 /* must be called with ATA channel locked and state_mtx held */ 63 int 64 ata_begin_transaction(struct ata_request *request) 65 { 66 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 67 struct ata_device *atadev = device_get_softc(request->dev); 68 int dummy, error; 69 70 ATA_DEBUG_RQ(request, "begin transaction"); 71 72 /* disable ATAPI DMA writes if HW doesn't support it */ 73 if ((ch->flags & ATA_ATAPI_DMA_RO) && 74 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 75 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 76 request->flags &= ~ATA_R_DMA; 77 78 /* check for 48 bit access and convert if needed */ 79 ata_modify_if_48bit(request); 80 81 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 82 83 /* ATA PIO data transfer and control commands */ 84 default: 85 { 86 /* record command direction here as our request might be gone later */ 87 int write = (request->flags & ATA_R_WRITE); 88 89 /* issue command */ 90 if (ch->hw.command(request)) { 91 device_printf(request->dev, "error issuing %s command\n", 92 ata_cmd2str(request)); 93 request->result = EIO; 94 goto begin_finished; 95 } 96 97 /* device reset doesn't interrupt */ 98 if (request->u.ata.command == ATA_DEVICE_RESET) { 99 int timeout = 1000000; 100 do { 101 DELAY(10); 102 request->status = ATA_IDX_INB(ch, ATA_STATUS); 103 } while (request->status & ATA_S_BUSY && timeout--); 104 if (request->status & ATA_S_ERROR) 105 request->error = ATA_IDX_INB(ch, ATA_ERROR); 106 goto begin_finished; 107 } 108 109 /* if write command output the data */ 110 if (write) { 111 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 112 device_printf(request->dev, 113 "timeout waiting for write DRQ\n"); 114 request->result = EIO; 115 goto begin_finished; 116 } 117 ata_pio_write(request, request->transfersize); 118 } 119 } 120 goto begin_continue; 121 122 /* ATA DMA data transfer commands */ 123 case ATA_R_DMA: 124 /* check sanity, setup SG list and DMA engine */ 125 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 126 request->flags & ATA_R_READ, ch->dma->sg, 127 &dummy))) { 128 device_printf(request->dev, "setting up DMA failed\n"); 129 request->result = error; 130 goto begin_finished; 131 } 132 133 /* issue command */ 134 if (ch->hw.command(request)) { 135 device_printf(request->dev, "error issuing %s command\n", 136 ata_cmd2str(request)); 137 request->result = EIO; 138 goto begin_finished; 139 } 140 141 /* start DMA engine */ 142 if (ch->dma->start && ch->dma->start(request->dev)) { 143 device_printf(request->dev, "error starting DMA\n"); 144 request->result = EIO; 145 goto begin_finished; 146 } 147 goto begin_continue; 148 149 /* ATAPI PIO commands */ 150 case ATA_R_ATAPI: 151 /* is this just a POLL DSC command ? */ 152 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 153 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 154 DELAY(10); 155 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 156 request->result = EBUSY; 157 goto begin_finished; 158 } 159 160 /* start ATAPI operation */ 161 if (ch->hw.command(request)) { 162 device_printf(request->dev, "error issuing ATA PACKET command\n"); 163 request->result = EIO; 164 goto begin_finished; 165 } 166 goto begin_continue; 167 168 /* ATAPI DMA commands */ 169 case ATA_R_ATAPI|ATA_R_DMA: 170 /* is this just a POLL DSC command ? */ 171 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 172 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 173 DELAY(10); 174 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 175 request->result = EBUSY; 176 goto begin_finished; 177 } 178 179 /* check sanity, setup SG list and DMA engine */ 180 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 181 request->flags & ATA_R_READ, ch->dma->sg, 182 &dummy))) { 183 device_printf(request->dev, "setting up DMA failed\n"); 184 request->result = error; 185 goto begin_finished; 186 } 187 188 /* start ATAPI operation */ 189 if (ch->hw.command(request)) { 190 device_printf(request->dev, "error issuing ATA PACKET command\n"); 191 request->result = EIO; 192 goto begin_finished; 193 } 194 195 /* start DMA engine */ 196 if (ch->dma->start && ch->dma->start(request->dev)) { 197 request->result = EIO; 198 goto begin_finished; 199 } 200 goto begin_continue; 201 } 202 /* NOT REACHED */ 203 kprintf("ata_begin_transaction OOPS!!!\n"); 204 205 begin_finished: 206 if (ch->dma && ch->dma->flags & ATA_DMA_LOADED) 207 ch->dma->unload(ch->dev); 208 return ATA_OP_FINISHED; 209 210 begin_continue: 211 /* caller holds ch->state_mtx */ 212 callout_reset(&request->callout, request->timeout * hz, 213 (timeout_t*)ata_timeout, request); 214 return ATA_OP_CONTINUES; 215 } 216 217 /* must be called with ATA channel locked and state_mtx held */ 218 int 219 ata_end_transaction(struct ata_request *request) 220 { 221 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 222 struct ata_device *atadev = device_get_softc(request->dev); 223 int length; 224 225 ATA_DEBUG_RQ(request, "end transaction"); 226 227 /* clear interrupt and get status */ 228 request->status = ATA_IDX_INB(ch, ATA_STATUS); 229 230 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 231 232 /* ATA PIO data transfer and control commands */ 233 default: 234 235 /* on timeouts we have no data or anything so just return */ 236 if (request->flags & ATA_R_TIMEOUT) 237 goto end_finished; 238 239 /* on control commands read back registers to the request struct */ 240 if (request->flags & ATA_R_CONTROL) { 241 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 242 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB); 243 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8); 244 request->u.ata.lba = 245 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) | 246 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | 247 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40); 248 249 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 250 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT); 251 request->u.ata.lba |= 252 (ATA_IDX_INB(ch, ATA_SECTOR) | 253 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 254 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16)); 255 } 256 else { 257 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 258 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 259 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 260 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 261 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24); 262 } 263 } 264 265 /* if we got an error we are done with the HW */ 266 if (request->status & ATA_S_ERROR) { 267 request->error = ATA_IDX_INB(ch, ATA_ERROR); 268 goto end_finished; 269 } 270 271 /* are we moving data ? */ 272 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 273 274 /* if read data get it */ 275 if (request->flags & ATA_R_READ) { 276 int flags = ATA_S_DRQ; 277 278 if (request->u.ata.command != ATA_ATAPI_IDENTIFY) 279 flags |= ATA_S_READY; 280 if (ata_wait(ch, atadev, flags) < 0) { 281 device_printf(request->dev, 282 "timeout waiting for read DRQ\n"); 283 request->result = EIO; 284 goto end_finished; 285 } 286 ata_pio_read(request, request->transfersize); 287 } 288 289 /* update how far we've gotten */ 290 request->donecount += request->transfersize; 291 292 /* do we need a scoop more ? */ 293 if (request->bytecount > request->donecount) { 294 295 /* set this transfer size according to HW capabilities */ 296 request->transfersize = 297 min((request->bytecount - request->donecount), 298 request->transfersize); 299 300 /* if data write command, output the data */ 301 if (request->flags & ATA_R_WRITE) { 302 303 /* if we get an error here we are done with the HW */ 304 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 305 device_printf(request->dev, 306 "timeout waiting for write DRQ\n"); 307 request->status = ATA_IDX_INB(ch, ATA_STATUS); 308 goto end_finished; 309 } 310 311 /* output data and return waiting for new interrupt */ 312 ata_pio_write(request, request->transfersize); 313 goto end_continue; 314 } 315 316 /* if data read command, return & wait for interrupt */ 317 if (request->flags & ATA_R_READ) 318 goto end_continue; 319 } 320 } 321 /* done with HW */ 322 goto end_finished; 323 324 /* ATA DMA data transfer commands */ 325 case ATA_R_DMA: 326 327 /* stop DMA engine and get status */ 328 if (ch->dma->stop) 329 request->dmastat = ch->dma->stop(request->dev); 330 331 /* did we get error or data */ 332 if (request->status & ATA_S_ERROR) 333 request->error = ATA_IDX_INB(ch, ATA_ERROR); 334 else if (request->dmastat & ATA_BMSTAT_ERROR) 335 request->status |= ATA_S_ERROR; 336 else if (!(request->flags & ATA_R_TIMEOUT)) 337 request->donecount = request->bytecount; 338 339 /* release SG list etc */ 340 ch->dma->unload(ch->dev); 341 342 /* done with HW */ 343 goto end_finished; 344 345 /* ATAPI PIO commands */ 346 case ATA_R_ATAPI: 347 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 348 349 /* on timeouts we have no data or anything so just return */ 350 if (request->flags & ATA_R_TIMEOUT) 351 goto end_finished; 352 353 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 354 (request->status & ATA_S_DRQ)) { 355 356 case ATAPI_P_CMDOUT: 357 /* this seems to be needed for some (slow) devices */ 358 DELAY(10); 359 360 if (!(request->status & ATA_S_DRQ)) { 361 device_printf(request->dev, "command interrupt without DRQ\n"); 362 request->status = ATA_S_ERROR; 363 goto end_finished; 364 } 365 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 366 (atadev->param.config & 367 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 368 /* return wait for interrupt */ 369 goto end_continue; 370 371 case ATAPI_P_WRITE: 372 if (request->flags & ATA_R_READ) { 373 request->status = ATA_S_ERROR; 374 device_printf(request->dev, 375 "%s trying to write on read buffer\n", 376 ata_cmd2str(request)); 377 goto end_finished; 378 break; 379 } 380 ata_pio_write(request, length); 381 request->donecount += length; 382 383 /* set next transfer size according to HW capabilities */ 384 request->transfersize = min((request->bytecount-request->donecount), 385 request->transfersize); 386 /* return wait for interrupt */ 387 goto end_continue; 388 389 case ATAPI_P_READ: 390 if (request->flags & ATA_R_WRITE) { 391 request->status = ATA_S_ERROR; 392 device_printf(request->dev, 393 "%s trying to read on write buffer\n", 394 ata_cmd2str(request)); 395 goto end_finished; 396 } 397 ata_pio_read(request, length); 398 request->donecount += length; 399 400 /* set next transfer size according to HW capabilities */ 401 request->transfersize = min((request->bytecount-request->donecount), 402 request->transfersize); 403 /* return wait for interrupt */ 404 goto end_continue; 405 406 case ATAPI_P_DONEDRQ: 407 device_printf(request->dev, 408 "WARNING - %s DONEDRQ non conformant device\n", 409 ata_cmd2str(request)); 410 if (request->flags & ATA_R_READ) { 411 ata_pio_read(request, length); 412 request->donecount += length; 413 } 414 else if (request->flags & ATA_R_WRITE) { 415 ata_pio_write(request, length); 416 request->donecount += length; 417 } 418 else 419 request->status = ATA_S_ERROR; 420 /* FALLTHROUGH */ 421 422 case ATAPI_P_ABORT: 423 case ATAPI_P_DONE: 424 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 425 request->error = ATA_IDX_INB(ch, ATA_ERROR); 426 goto end_finished; 427 428 default: 429 device_printf(request->dev, "unknown transfer phase\n"); 430 request->status = ATA_S_ERROR; 431 } 432 433 /* done with HW */ 434 goto end_finished; 435 436 /* ATAPI DMA commands */ 437 case ATA_R_ATAPI|ATA_R_DMA: 438 439 /* stop DMA engine and get status */ 440 if (ch->dma->stop) 441 request->dmastat = ch->dma->stop(request->dev); 442 443 /* did we get error or data */ 444 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 445 request->error = ATA_IDX_INB(ch, ATA_ERROR); 446 else if (request->dmastat & ATA_BMSTAT_ERROR) 447 request->status |= ATA_S_ERROR; 448 else if (!(request->flags & ATA_R_TIMEOUT)) 449 request->donecount = request->bytecount; 450 451 /* release SG list etc */ 452 ch->dma->unload(ch->dev); 453 454 /* done with HW */ 455 goto end_finished; 456 } 457 /* NOT REACHED */ 458 kprintf("ata_end_transaction OOPS!!\n"); 459 460 end_finished: 461 callout_stop(&request->callout); 462 return ATA_OP_FINISHED; 463 464 end_continue: 465 return ATA_OP_CONTINUES; 466 } 467 468 /* must be called with ATA channel locked and state_mtx held */ 469 void 470 ata_generic_reset(device_t dev) 471 { 472 struct ata_channel *ch = device_get_softc(dev); 473 474 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 475 u_int8_t err = 0, lsb = 0, msb = 0; 476 int mask = 0, timeout; 477 478 /* do we have any signs of ATA/ATAPI HW being present ? */ 479 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER); 480 DELAY(10); 481 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 482 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 483 stat0 = ATA_S_BUSY; 484 mask |= 0x01; 485 } 486 487 /* in some setups we dont want to test for a slave */ 488 if (!(ch->flags & ATA_NO_SLAVE)) { 489 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_SLAVE); 490 DELAY(10); 491 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 492 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 493 stat1 = ATA_S_BUSY; 494 mask |= 0x02; 495 } 496 } 497 498 if (bootverbose) 499 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 500 mask, ostat0, ostat1); 501 502 /* if nothing showed up there is no need to get any further */ 503 /* XXX SOS is that too strong?, we just might loose devices here */ 504 ch->devices = 0; 505 if (!mask) 506 return; 507 508 /* reset (both) devices on this channel */ 509 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER); 510 DELAY(10); 511 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 512 ata_udelay(10000); 513 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 514 ata_udelay(100000); 515 ATA_IDX_INB(ch, ATA_ERROR); 516 517 /* wait for BUSY to go inactive */ 518 for (timeout = 0; timeout < 310; timeout++) { 519 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 520 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); 521 DELAY(10); 522 err = ATA_IDX_INB(ch, ATA_ERROR); 523 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 524 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 525 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 526 if (bootverbose) 527 device_printf(dev, 528 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 529 stat0, err, lsb, msb); 530 if (stat0 == err && lsb == err && msb == err && 531 timeout > (stat0 & ATA_S_BUSY ? 100 : 10)) 532 mask &= ~0x01; 533 if (!(stat0 & ATA_S_BUSY)) { 534 if ((err & 0x7f) == ATA_E_ILI) { 535 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 536 ch->devices |= ATA_ATAPI_MASTER; 537 } 538 else if (stat0 & ATA_S_READY) { 539 ch->devices |= ATA_ATA_MASTER; 540 } 541 } 542 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 543 stat0 |= ATA_S_BUSY; 544 } 545 } 546 } 547 548 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) && 549 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) { 550 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); 551 DELAY(10); 552 err = ATA_IDX_INB(ch, ATA_ERROR); 553 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 554 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 555 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 556 if (bootverbose) 557 device_printf(dev, 558 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 559 stat1, err, lsb, msb); 560 if (stat1 == err && lsb == err && msb == err && 561 timeout > (stat1 & ATA_S_BUSY ? 100 : 10)) 562 mask &= ~0x02; 563 if (!(stat1 & ATA_S_BUSY)) { 564 if ((err & 0x7f) == ATA_E_ILI) { 565 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 566 ch->devices |= ATA_ATAPI_SLAVE; 567 } 568 else if (stat1 & ATA_S_READY) { 569 ch->devices |= ATA_ATA_SLAVE; 570 } 571 } 572 else if ((stat1 & 0x0f) && err == lsb && err == msb) { 573 stat1 |= ATA_S_BUSY; 574 } 575 } 576 } 577 578 if (mask == 0x00) /* nothing to wait for */ 579 break; 580 if (mask == 0x01) /* wait for master only */ 581 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10)) 582 break; 583 if (mask == 0x02) /* wait for slave only */ 584 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10)) 585 break; 586 if (mask == 0x03) { /* wait for both master & slave */ 587 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 588 break; 589 if ((stat0 == 0xff) && (timeout > 20)) 590 mask &= ~0x01; 591 if ((stat1 == 0xff) && (timeout > 20)) 592 mask &= ~0x02; 593 } 594 ata_udelay(100000); 595 } 596 597 if (bootverbose) 598 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n", 599 stat0, stat1, ch->devices, 600 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 601 } 602 603 /* must be called with ATA channel locked and state_mtx held */ 604 int 605 ata_generic_status(device_t dev) 606 { 607 struct ata_channel *ch = device_get_softc(dev); 608 609 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 610 DELAY(100); 611 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 612 return 0; 613 } 614 return 1; 615 } 616 617 static int 618 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask) 619 { 620 u_int8_t status; 621 int timeout = 0; 622 623 DELAY(1); 624 625 /* wait at max 1 second for device to get !BUSY */ 626 while (timeout < 1000000) { 627 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 628 629 /* if drive fails status, reselect the drive and try again */ 630 if (status == 0xff) { 631 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit); 632 timeout += 1000; 633 DELAY(1000); 634 continue; 635 } 636 637 /* are we done ? */ 638 if (!(status & ATA_S_BUSY)) 639 break; 640 641 if (timeout > 1000) { 642 timeout += 1000; 643 DELAY(1000); 644 } 645 else { 646 timeout += 10; 647 DELAY(10); 648 } 649 } 650 if (timeout >= 1000000) 651 return -2; 652 if (!mask) 653 return (status & ATA_S_ERROR); 654 655 DELAY(1); 656 657 /* wait 50 msec for bits wanted */ 658 timeout = 5000; 659 while (timeout--) { 660 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 661 if ((status & mask) == mask) 662 return (status & ATA_S_ERROR); 663 DELAY(10); 664 } 665 return -3; 666 } 667 668 int 669 ata_generic_command(struct ata_request *request) 670 { 671 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 672 struct ata_device *atadev = device_get_softc(request->dev); 673 674 /* select device */ 675 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 676 677 /* ready to issue command ? */ 678 if (ata_wait(ch, atadev, 0) < 0) { 679 device_printf(request->dev, "timeout waiting to issue command\n"); 680 return -1; 681 } 682 683 /* enable interrupt */ 684 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 685 686 if (request->flags & ATA_R_ATAPI) { 687 int timeout = 5000; 688 689 /* issue packet command to controller */ 690 if (request->flags & ATA_R_DMA) { 691 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA); 692 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0); 693 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0); 694 } 695 else { 696 ATA_IDX_OUTB(ch, ATA_FEATURE, 0); 697 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize); 698 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8); 699 } 700 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD); 701 702 /* command interrupt device ? just return and wait for interrupt */ 703 if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR) 704 return 0; 705 706 /* wait for ready to write ATAPI command block */ 707 while (timeout--) { 708 int reason = ATA_IDX_INB(ch, ATA_IREASON); 709 int status = ATA_IDX_INB(ch, ATA_STATUS); 710 711 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 712 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 713 break; 714 DELAY(20); 715 } 716 if (timeout <= 0) { 717 device_printf(request->dev, "timeout waiting for ATAPI ready\n"); 718 request->result = EIO; 719 return -1; 720 } 721 722 /* this seems to be needed for some (slow) devices */ 723 DELAY(10); 724 725 /* output command block */ 726 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 727 (atadev->param.config & ATA_PROTO_MASK) == 728 ATA_PROTO_ATAPI_12 ? 6 : 8); 729 } 730 else { 731 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 732 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8); 733 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 734 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8); 735 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 736 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24); 737 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 738 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32); 739 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 740 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40); 741 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 742 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit); 743 } 744 else { 745 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 746 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 747 if (atadev->flags & ATA_D_USE_CHS) { 748 int heads, sectors; 749 750 if (atadev->param.atavalid & ATA_FLAG_54_58) { 751 heads = atadev->param.current_heads; 752 sectors = atadev->param.current_sectors; 753 } 754 else { 755 heads = atadev->param.heads; 756 sectors = atadev->param.sectors; 757 } 758 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 759 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 760 (request->u.ata.lba / (sectors * heads))); 761 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 762 (request->u.ata.lba / (sectors * heads)) >> 8); 763 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit | 764 (((request->u.ata.lba% (sectors * heads)) / 765 sectors) & 0xf)); 766 } 767 else { 768 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 769 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 770 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 771 ATA_IDX_OUTB(ch, ATA_DRIVE, 772 ATA_D_IBM | ATA_D_LBA | atadev->unit | 773 ((request->u.ata.lba >> 24) & 0x0f)); 774 } 775 } 776 777 /* issue command to controller */ 778 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 779 } 780 781 return 0; 782 } 783 784 static void 785 ata_pio_read(struct ata_request *request, int length) 786 { 787 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 788 int size = min(request->transfersize, length); 789 int resid; 790 791 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 792 ATA_IDX_INSW_STRM(ch, ATA_DATA, 793 (void*)((uintptr_t)request->data+request->donecount), 794 size / sizeof(int16_t)); 795 else 796 ATA_IDX_INSL_STRM(ch, ATA_DATA, 797 (void*)((uintptr_t)request->data+request->donecount), 798 size / sizeof(int32_t)); 799 800 if (request->transfersize < length) { 801 device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n", 802 ata_cmd2str(request), length, request->transfersize); 803 for (resid = request->transfersize; resid < length; 804 resid += sizeof(int16_t)) 805 ATA_IDX_INW(ch, ATA_DATA); 806 } 807 } 808 809 static void 810 ata_pio_write(struct ata_request *request, int length) 811 { 812 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 813 int size = min(request->transfersize, length); 814 int resid; 815 816 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 817 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 818 (void*)((uintptr_t)request->data+request->donecount), 819 size / sizeof(int16_t)); 820 else 821 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 822 (void*)((uintptr_t)request->data+request->donecount), 823 size / sizeof(int32_t)); 824 825 if (request->transfersize < length) { 826 device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n", 827 ata_cmd2str(request), length, request->transfersize); 828 for (resid = request->transfersize; resid < length; 829 resid += sizeof(int16_t)) 830 ATA_IDX_OUTW(ch, ATA_DATA, 0); 831 } 832 } 833