1 /*- 2 * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/ata/ata-lowlevel.c,v 1.77 2006/07/04 20:36:03 sos Exp $ 27 */ 28 29 #include "opt_ata.h" 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/callout.h> 34 #include <sys/libkern.h> 35 #include <sys/nata.h> 36 #include <sys/systm.h> 37 38 #include "ata-all.h" 39 #include "ata_if.h" 40 41 /* prototypes */ 42 static int ata_generic_status(device_t dev); 43 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t); 44 static void ata_pio_read(struct ata_request *, int); 45 static void ata_pio_write(struct ata_request *, int); 46 static void ata_tf_read(struct ata_request *); 47 static void ata_tf_write(struct ata_request *); 48 49 /* 50 * low level ATA functions 51 */ 52 void 53 ata_generic_hw(device_t dev) 54 { 55 struct ata_channel *ch = device_get_softc(dev); 56 57 ch->hw.begin_transaction = ata_begin_transaction; 58 ch->hw.end_transaction = ata_end_transaction; 59 ch->hw.status = ata_generic_status; 60 ch->hw.command = ata_generic_command; 61 ch->hw.tf_read = ata_tf_read; 62 ch->hw.tf_write = ata_tf_write; 63 } 64 65 /* must be called with ATA channel locked and state_mtx held */ 66 int 67 ata_begin_transaction(struct ata_request *request) 68 { 69 struct ata_channel *ch = device_get_softc(request->parent); 70 struct ata_device *atadev = device_get_softc(request->dev); 71 int dummy, error; 72 73 ATA_DEBUG_RQ(request, "begin transaction"); 74 75 /* disable ATAPI DMA writes if HW doesn't support it */ 76 if ((ch->flags & ATA_ATAPI_DMA_RO) && 77 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 78 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 79 request->flags &= ~ATA_R_DMA; 80 81 /* check for 48 bit access and convert if needed */ 82 ata_modify_if_48bit(request); 83 84 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 85 86 /* ATA PIO data transfer and control commands */ 87 default: 88 { 89 /* record command direction here as our request might be gone later */ 90 int write = (request->flags & ATA_R_WRITE); 91 92 /* issue command */ 93 if (ch->hw.command(request)) { 94 device_printf(request->dev, "error issuing %s command\n", 95 ata_cmd2str(request)); 96 request->result = EIO; 97 goto begin_finished; 98 } 99 100 /* device reset doesn't interrupt */ 101 if (request->u.ata.command == ATA_DEVICE_RESET) { 102 int timeout = 1000000; 103 do { 104 DELAY(10); 105 request->status = ATA_IDX_INB(ch, ATA_STATUS); 106 } while (request->status & ATA_S_BUSY && timeout--); 107 if (request->status & ATA_S_ERROR) 108 request->error = ATA_IDX_INB(ch, ATA_ERROR); 109 goto begin_finished; 110 } 111 112 /* if write command output the data */ 113 if (write) { 114 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 115 device_printf(request->dev, 116 "timeout waiting for write DRQ\n"); 117 request->result = EIO; 118 goto begin_finished; 119 } 120 ata_pio_write(request, request->transfersize); 121 } 122 } 123 goto begin_continue; 124 125 /* ATA DMA data transfer commands */ 126 case ATA_R_DMA: 127 /* check sanity, setup SG list and DMA engine */ 128 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 129 request->flags & ATA_R_READ, ch->dma->sg, 130 &dummy))) { 131 device_printf(request->dev, "setting up DMA failed\n"); 132 request->result = error; 133 goto begin_finished; 134 } 135 136 /* issue command */ 137 if (ch->hw.command(request)) { 138 device_printf(request->dev, "error issuing %s command\n", 139 ata_cmd2str(request)); 140 request->result = EIO; 141 goto begin_finished; 142 } 143 144 /* start DMA engine */ 145 if (ch->dma->start && ch->dma->start(request->dev)) { 146 device_printf(request->dev, "error starting DMA\n"); 147 request->result = EIO; 148 goto begin_finished; 149 } 150 goto begin_continue; 151 152 /* ATAPI PIO commands */ 153 case ATA_R_ATAPI: 154 /* is this just a POLL DSC command ? */ 155 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 156 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit)); 157 DELAY(10); 158 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 159 request->result = EBUSY; 160 goto begin_finished; 161 } 162 163 /* start ATAPI operation */ 164 if (ch->hw.command(request)) { 165 device_printf(request->dev, "error issuing ATA PACKET command\n"); 166 request->result = EIO; 167 goto begin_finished; 168 } 169 goto begin_continue; 170 171 /* ATAPI DMA commands */ 172 case ATA_R_ATAPI|ATA_R_DMA: 173 /* is this just a POLL DSC command ? */ 174 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 175 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit)); 176 DELAY(10); 177 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 178 request->result = EBUSY; 179 goto begin_finished; 180 } 181 182 /* check sanity, setup SG list and DMA engine */ 183 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 184 request->flags & ATA_R_READ, ch->dma->sg, 185 &dummy))) { 186 device_printf(request->dev, "setting up DMA failed\n"); 187 request->result = error; 188 goto begin_finished; 189 } 190 191 /* start ATAPI operation */ 192 if (ch->hw.command(request)) { 193 device_printf(request->dev, "error issuing ATA PACKET command\n"); 194 request->result = EIO; 195 goto begin_finished; 196 } 197 198 /* start DMA engine */ 199 if (ch->dma->start && ch->dma->start(request->dev)) { 200 request->result = EIO; 201 goto begin_finished; 202 } 203 goto begin_continue; 204 } 205 /* NOT REACHED */ 206 kprintf("ata_begin_transaction OOPS!!!\n"); 207 208 begin_finished: 209 if (ch->dma && ch->dma->flags & ATA_DMA_LOADED) 210 ch->dma->unload(ch->dev); 211 return ATA_OP_FINISHED; 212 213 begin_continue: 214 /* caller holds ch->state_mtx */ 215 callout_reset(&request->callout, request->timeout * hz, 216 (timeout_t*)ata_timeout, request); 217 return ATA_OP_CONTINUES; 218 } 219 220 /* must be called with ATA channel locked and state_mtx held */ 221 int 222 ata_end_transaction(struct ata_request *request) 223 { 224 struct ata_channel *ch = device_get_softc(request->parent); 225 struct ata_device *atadev = device_get_softc(request->dev); 226 int length; 227 228 ATA_DEBUG_RQ(request, "end transaction"); 229 230 /* clear interrupt and get status */ 231 request->status = ATA_IDX_INB(ch, ATA_STATUS); 232 233 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 234 235 /* ATA PIO data transfer and control commands */ 236 default: 237 238 /* on timeouts we have no data or anything so just return */ 239 if (request->flags & ATA_R_TIMEOUT) 240 goto end_finished; 241 242 /* on control commands read back registers to the request struct */ 243 if (request->flags & ATA_R_CONTROL) { 244 ch->hw.tf_read(request); 245 } 246 247 /* if we got an error we are done with the HW */ 248 if (request->status & ATA_S_ERROR) { 249 request->error = ATA_IDX_INB(ch, ATA_ERROR); 250 goto end_finished; 251 } 252 253 /* are we moving data ? */ 254 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 255 256 /* if read data get it */ 257 if (request->flags & ATA_R_READ) { 258 int flags = ATA_S_DRQ; 259 260 if (request->u.ata.command != ATA_ATAPI_IDENTIFY) 261 flags |= ATA_S_READY; 262 if (ata_wait(ch, atadev, flags) < 0) { 263 device_printf(request->dev, 264 "timeout waiting for read DRQ\n"); 265 request->result = EIO; 266 goto end_finished; 267 } 268 ata_pio_read(request, request->transfersize); 269 } 270 271 /* update how far we've gotten */ 272 request->donecount += request->transfersize; 273 274 /* do we need a scoop more ? */ 275 if (request->bytecount > request->donecount) { 276 277 /* set this transfer size according to HW capabilities */ 278 request->transfersize = 279 min((request->bytecount - request->donecount), 280 request->transfersize); 281 282 /* if data write command, output the data */ 283 if (request->flags & ATA_R_WRITE) { 284 285 /* if we get an error here we are done with the HW */ 286 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) { 287 device_printf(request->dev, 288 "timeout waiting for write DRQ\n"); 289 request->status = ATA_IDX_INB(ch, ATA_STATUS); 290 goto end_finished; 291 } 292 293 /* output data and return waiting for new interrupt */ 294 ata_pio_write(request, request->transfersize); 295 goto end_continue; 296 } 297 298 /* if data read command, return & wait for interrupt */ 299 if (request->flags & ATA_R_READ) 300 goto end_continue; 301 } 302 } 303 /* done with HW */ 304 goto end_finished; 305 306 /* ATA DMA data transfer commands */ 307 case ATA_R_DMA: 308 309 /* stop DMA engine and get status */ 310 if (ch->dma->stop) 311 request->dmastat = ch->dma->stop(request->dev); 312 313 /* did we get error or data */ 314 if (request->status & ATA_S_ERROR) 315 request->error = ATA_IDX_INB(ch, ATA_ERROR); 316 else if (request->dmastat & ATA_BMSTAT_ERROR) 317 request->status |= ATA_S_ERROR; 318 else if (!(request->flags & ATA_R_TIMEOUT)) 319 request->donecount = request->bytecount; 320 321 /* release SG list etc */ 322 ch->dma->unload(ch->dev); 323 324 /* done with HW */ 325 goto end_finished; 326 327 /* ATAPI PIO commands */ 328 case ATA_R_ATAPI: 329 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 330 331 /* on timeouts we have no data or anything so just return */ 332 if (request->flags & ATA_R_TIMEOUT) 333 goto end_finished; 334 335 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 336 (request->status & ATA_S_DRQ)) { 337 338 case ATAPI_P_CMDOUT: 339 /* this seems to be needed for some (slow) devices */ 340 DELAY(10); 341 342 if (!(request->status & ATA_S_DRQ)) { 343 device_printf(request->dev, "command interrupt without DRQ\n"); 344 request->status = ATA_S_ERROR; 345 goto end_finished; 346 } 347 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 348 (atadev->param.config & 349 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); 350 /* return wait for interrupt */ 351 goto end_continue; 352 353 case ATAPI_P_WRITE: 354 if (request->flags & ATA_R_READ) { 355 request->status = ATA_S_ERROR; 356 device_printf(request->dev, 357 "%s trying to write on read buffer\n", 358 ata_cmd2str(request)); 359 goto end_finished; 360 } 361 ata_pio_write(request, length); 362 request->donecount += length; 363 364 /* set next transfer size according to HW capabilities */ 365 request->transfersize = min((request->bytecount-request->donecount), 366 request->transfersize); 367 /* return wait for interrupt */ 368 goto end_continue; 369 370 case ATAPI_P_READ: 371 if (request->flags & ATA_R_WRITE) { 372 request->status = ATA_S_ERROR; 373 device_printf(request->dev, 374 "%s trying to read on write buffer\n", 375 ata_cmd2str(request)); 376 goto end_finished; 377 } 378 ata_pio_read(request, length); 379 request->donecount += length; 380 381 /* set next transfer size according to HW capabilities */ 382 request->transfersize = min((request->bytecount-request->donecount), 383 request->transfersize); 384 /* return wait for interrupt */ 385 goto end_continue; 386 387 case ATAPI_P_DONEDRQ: 388 device_printf(request->dev, 389 "WARNING - %s DONEDRQ non conformant device\n", 390 ata_cmd2str(request)); 391 if (request->flags & ATA_R_READ) { 392 ata_pio_read(request, length); 393 request->donecount += length; 394 } 395 else if (request->flags & ATA_R_WRITE) { 396 ata_pio_write(request, length); 397 request->donecount += length; 398 } 399 else 400 request->status = ATA_S_ERROR; 401 /* FALLTHROUGH */ 402 403 case ATAPI_P_ABORT: 404 case ATAPI_P_DONE: 405 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 406 request->error = ATA_IDX_INB(ch, ATA_ERROR); 407 goto end_finished; 408 409 default: 410 device_printf(request->dev, "unknown transfer phase\n"); 411 request->status = ATA_S_ERROR; 412 } 413 414 /* done with HW */ 415 goto end_finished; 416 417 /* ATAPI DMA commands */ 418 case ATA_R_ATAPI|ATA_R_DMA: 419 420 /* stop DMA engine and get status */ 421 if (ch->dma->stop) 422 request->dmastat = ch->dma->stop(request->dev); 423 424 /* did we get error or data */ 425 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 426 request->error = ATA_IDX_INB(ch, ATA_ERROR); 427 else if (request->dmastat & ATA_BMSTAT_ERROR) 428 request->status |= ATA_S_ERROR; 429 else if (!(request->flags & ATA_R_TIMEOUT)) 430 request->donecount = request->bytecount; 431 432 /* release SG list etc */ 433 ch->dma->unload(ch->dev); 434 435 /* done with HW */ 436 goto end_finished; 437 } 438 /* NOT REACHED */ 439 kprintf("ata_end_transaction OOPS!!\n"); 440 441 end_finished: 442 callout_cancel(&request->callout); 443 return ATA_OP_FINISHED; 444 445 end_continue: 446 return ATA_OP_CONTINUES; 447 } 448 449 /* must be called with ATA channel locked and state_mtx held */ 450 void 451 ata_generic_reset(device_t dev) 452 { 453 struct ata_channel *ch = device_get_softc(dev); 454 455 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 456 u_int8_t err = 0, lsb = 0, msb = 0; 457 int mask = 0, timeout; 458 459 /* do we have any signs of ATA/ATAPI HW being present ? */ 460 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 461 DELAY(10); 462 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 463 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { 464 stat0 = ATA_S_BUSY; 465 mask |= 0x01; 466 } 467 468 /* in some setups we dont want to test for a slave */ 469 if (!(ch->flags & ATA_NO_SLAVE)) { 470 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE)); 471 DELAY(10); 472 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 473 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { 474 stat1 = ATA_S_BUSY; 475 mask |= 0x02; 476 } 477 } 478 479 if (bootverbose) 480 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 481 mask, ostat0, ostat1); 482 483 /* if nothing showed up there is no need to get any further */ 484 /* XXX SOS is that too strong?, we just might loose devices here */ 485 ch->devices = 0; 486 if (!mask) 487 return; 488 489 /* reset (both) devices on this channel */ 490 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 491 DELAY(10); 492 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 493 ata_udelay(10000); 494 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 495 ata_udelay(100000); 496 ATA_IDX_INB(ch, ATA_ERROR); 497 498 /* wait for BUSY to go inactive */ 499 for (timeout = 0; timeout < 310; timeout++) { 500 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 501 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER)); 502 DELAY(10); 503 err = ATA_IDX_INB(ch, ATA_ERROR); 504 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 505 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 506 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 507 if (bootverbose) 508 device_printf(dev, 509 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 510 stat0, err, lsb, msb); 511 if (stat0 == err && lsb == err && msb == err && 512 timeout > (stat0 & ATA_S_BUSY ? 100 : 10)) 513 mask &= ~0x01; 514 if (!(stat0 & ATA_S_BUSY)) { 515 if ((err & 0x7f) == ATA_E_ILI) { 516 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 517 ch->devices |= ATA_ATAPI_MASTER; 518 } 519 else if (stat0 & ATA_S_READY) { 520 ch->devices |= ATA_ATA_MASTER; 521 } 522 } 523 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 524 stat0 |= ATA_S_BUSY; 525 } 526 } 527 } 528 529 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) && 530 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) { 531 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE)); 532 DELAY(10); 533 err = ATA_IDX_INB(ch, ATA_ERROR); 534 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 535 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 536 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 537 if (bootverbose) 538 device_printf(dev, 539 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 540 stat1, err, lsb, msb); 541 if (stat1 == err && lsb == err && msb == err && 542 timeout > (stat1 & ATA_S_BUSY ? 100 : 10)) 543 mask &= ~0x02; 544 if (!(stat1 & ATA_S_BUSY)) { 545 if ((err & 0x7f) == ATA_E_ILI) { 546 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 547 ch->devices |= ATA_ATAPI_SLAVE; 548 } 549 else if (stat1 & ATA_S_READY) { 550 ch->devices |= ATA_ATA_SLAVE; 551 } 552 } 553 else if ((stat1 & 0x0f) && err == lsb && err == msb) { 554 stat1 |= ATA_S_BUSY; 555 } 556 } 557 } 558 559 if (mask == 0x00) /* nothing to wait for */ 560 break; 561 if (mask == 0x01) /* wait for master only */ 562 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10)) 563 break; 564 if (mask == 0x02) /* wait for slave only */ 565 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10)) 566 break; 567 if (mask == 0x03) { /* wait for both master & slave */ 568 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY)) 569 break; 570 if ((stat0 == 0xff) && (timeout > 20)) 571 mask &= ~0x01; 572 if ((stat1 == 0xff) && (timeout > 20)) 573 mask &= ~0x02; 574 } 575 ata_udelay(100000); 576 } 577 578 if (bootverbose) 579 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n", 580 stat0, stat1, ch->devices); 581 } 582 583 /* must be called with ATA channel locked and state_mtx held */ 584 static int 585 ata_generic_status(device_t dev) 586 { 587 struct ata_channel *ch = device_get_softc(dev); 588 589 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 590 DELAY(100); 591 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 592 return 0; 593 } 594 return 1; 595 } 596 597 static int 598 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask) 599 { 600 u_int8_t status; 601 int timeout = 0; 602 603 DELAY(1); 604 605 /* wait at max 1 second for device to get !BUSY */ 606 while (timeout < 1000000) { 607 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 608 609 /* if drive fails status, reselect the drive and try again */ 610 if (status == 0xff) { 611 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit)); 612 timeout += 1000; 613 DELAY(1000); 614 continue; 615 } 616 617 /* are we done ? */ 618 if (!(status & ATA_S_BUSY)) 619 break; 620 621 if (timeout > 1000) { 622 timeout += 1000; 623 DELAY(1000); 624 } 625 else { 626 timeout += 10; 627 DELAY(10); 628 } 629 } 630 if (timeout >= 1000000) 631 return -2; 632 if (!mask) 633 return (status & ATA_S_ERROR); 634 635 DELAY(1); 636 637 /* wait 50 msec for bits wanted */ 638 timeout = 5000; 639 while (timeout--) { 640 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 641 if ((status & mask) == mask) 642 return (status & ATA_S_ERROR); 643 DELAY(10); 644 } 645 return -3; 646 } 647 648 int 649 ata_generic_command(struct ata_request *request) 650 { 651 struct ata_channel *ch = device_get_softc(request->parent); 652 struct ata_device *atadev = device_get_softc(request->dev); 653 654 /* select device */ 655 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(atadev->unit)); 656 657 /* ready to issue command ? */ 658 if (ata_wait(ch, atadev, 0) < 0) { 659 device_printf(request->dev, "timeout waiting to issue command\n"); 660 return -1; 661 } 662 663 /* enable interrupt */ 664 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 665 666 if (request->flags & ATA_R_ATAPI) { 667 int timeout = 5000; 668 669 /* issue packet command to controller */ 670 if (request->flags & ATA_R_DMA) { 671 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA); 672 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0); 673 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0); 674 } 675 else { 676 ATA_IDX_OUTB(ch, ATA_FEATURE, 0); 677 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize); 678 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8); 679 } 680 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD); 681 682 /* command interrupt device ? just return and wait for interrupt */ 683 if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR) 684 return 0; 685 686 /* wait for ready to write ATAPI command block */ 687 while (timeout--) { 688 int reason = ATA_IDX_INB(ch, ATA_IREASON); 689 int status = ATA_IDX_INB(ch, ATA_STATUS); 690 691 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 692 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 693 break; 694 DELAY(20); 695 } 696 if (timeout <= 0) { 697 device_printf(request->dev, "timeout waiting for ATAPI ready\n"); 698 request->result = EIO; 699 return -1; 700 } 701 702 /* this seems to be needed for some (slow) devices */ 703 DELAY(10); 704 705 /* output command block */ 706 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 707 (atadev->param.config & ATA_PROTO_MASK) == 708 ATA_PROTO_ATAPI_12 ? 6 : 8); 709 } 710 else { 711 ch->hw.tf_write(request); 712 713 /* issue command to controller */ 714 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 715 } 716 return 0; 717 } 718 719 static void 720 ata_tf_read(struct ata_request *request) 721 { 722 struct ata_channel *ch = device_get_softc(request->parent); 723 struct ata_device *atadev = device_get_softc(request->dev); 724 725 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 726 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB); 727 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8); 728 request->u.ata.lba = 729 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) | 730 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | 731 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40); 732 733 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 734 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT); 735 request->u.ata.lba |= 736 (ATA_IDX_INB(ch, ATA_SECTOR) | 737 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 738 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16)); 739 } 740 else { 741 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 742 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 743 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 744 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 745 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24); 746 } 747 } 748 749 static void 750 ata_tf_write(struct ata_request *request) 751 { 752 struct ata_channel *ch = device_get_softc(request->parent); 753 struct ata_device *atadev = device_get_softc(request->dev); 754 755 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 756 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8); 757 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 758 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8); 759 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 760 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24); 761 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 762 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32); 763 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 764 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40); 765 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 766 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(atadev->unit)); 767 } 768 else { 769 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 770 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 771 if (atadev->flags & ATA_D_USE_CHS) { 772 int heads, sectors; 773 774 if (atadev->param.atavalid & ATA_FLAG_54_58) { 775 heads = atadev->param.current_heads; 776 sectors = atadev->param.current_sectors; 777 } 778 else { 779 heads = atadev->param.heads; 780 sectors = atadev->param.sectors; 781 } 782 783 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 784 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 785 (request->u.ata.lba / (sectors * heads))); 786 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 787 (request->u.ata.lba / (sectors * heads)) >> 8); 788 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit) | 789 (((request->u.ata.lba% (sectors * heads)) / 790 sectors) & 0xf)); 791 } 792 else { 793 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 794 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 795 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 796 ATA_IDX_OUTB(ch, ATA_DRIVE, 797 ATA_D_IBM | ATA_D_LBA | ATA_DEV(atadev->unit) | 798 ((request->u.ata.lba >> 24) & 0x0f)); 799 } 800 } 801 } 802 803 static void 804 ata_pio_read(struct ata_request *request, int length) 805 { 806 struct ata_channel *ch = device_get_softc(request->parent); 807 int size = min(request->transfersize, length); 808 int resid; 809 810 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 811 ATA_IDX_INSW_STRM(ch, ATA_DATA, 812 (void*)((uintptr_t)request->data+request->donecount), 813 size / sizeof(int16_t)); 814 else 815 ATA_IDX_INSL_STRM(ch, ATA_DATA, 816 (void*)((uintptr_t)request->data+request->donecount), 817 size / sizeof(int32_t)); 818 819 if (request->transfersize < length) { 820 device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n", 821 ata_cmd2str(request), length, request->transfersize); 822 for (resid = request->transfersize; resid < length; 823 resid += sizeof(int16_t)) 824 ATA_IDX_INW(ch, ATA_DATA); 825 } 826 } 827 828 static void 829 ata_pio_write(struct ata_request *request, int length) 830 { 831 struct ata_channel *ch = device_get_softc(request->parent); 832 int size = min(request->transfersize, length); 833 int resid; 834 835 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) 836 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, 837 (void*)((uintptr_t)request->data+request->donecount), 838 size / sizeof(int16_t)); 839 else 840 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 841 (void*)((uintptr_t)request->data+request->donecount), 842 size / sizeof(int32_t)); 843 844 if (request->transfersize < length) { 845 device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n", 846 ata_cmd2str(request), length, request->transfersize); 847 for (resid = request->transfersize; resid < length; 848 resid += sizeof(int16_t)) 849 ATA_IDX_OUTW(ch, ATA_DATA, 0); 850 } 851 } 852